diff --git a/README-CN.md b/README-CN.md index 7a909fc35b6d69d38527c471bcda321514a4de2b..2210a90863e588b72851915a65cc252eb27843bf 100755 --- a/README-CN.md +++ b/README-CN.md @@ -185,7 +185,7 @@ organization={IEEE} | 子模块 | 来源 | 详细用途 | | -------------- | ----------------------------------------------------------------------------------------------------- | ----------------------------------------------------------------- | -| flute3 | [FastRoute](http://home.eng.iastate.edu/~cnchu/FastRoute) | 借助flute3来产生rectange steiner tree. | +| flute3 | [FastRoute](https://github.com/The-OpenROAD-Project-Attic/flute3) | 借助flute3来产生rectange steiner tree. | | abseil-cpp | [Google abseil](https://github.com/abseil/abseil-cpp.git) | 使用Google的高性能C++容器和算法库提升性能，相比STL会改进程序性能. | | json | [JSON for Modern C++](https://github.com/nlohmann/json) | Json C++库，用来解析程序Json配置文件. | | magic_enum | [Static reflection for enums (to string, from string, iteration)](https://github.com/Neargye/magic_enum) | 支持 enum 值和字符串的相互转换. | @@ -196,12 +196,13 @@ organization={IEEE} | def lef | [def lef parser](https://github.com/asyncvlsi/lefdef.git) | 解析物理设计DEF/LEF文件. | | ThreadPool | [Jakob Progsch, Václav Zeman threadpool](https://github.com/progschj/ThreadPool.git) | C++11模板库实现的多线程池. | | fft | [fft](https://www.kurims.kyoto-u.ac.jp/~ooura/fft.html) | 快速傅立叶变换库. | -| hMETIS | [hMETIS](http://glaros.dtc.umn.edu/gkhome/metis/hmetis/overview) | 高效的图划分算法. | +| hMETIS | [hMETIS](https://github.com/KarypisLab/METIS) | 高效的图划分算法. | | lemon | [lemon](https://lemon.cs.elte.hu/trac/lemon) | 图、网络中的高效建模和优化. | | SALT | [SALT]([SALT](https://github.com/chengengjie/salt)) | 生成VLSI路由拓扑，在路径长度(浅度)和总线长(亮度)之间进行权衡. | | scipoptsuite | [SCIP](https://scipopt.org/index.php#welcome) | 用于快速求解混合整数规划 (MIP) 和混合整数非线性规划 (MINLP) . | | mt-kahypar | [mt-kahypar]([mt-kahypar]https://github.com/kahypar/mt-kahypar.git) | 多线程超图划分器. | + 我们深深地感谢来自开源社区的支持，我们也鼓励其他开源项目在[木兰宽松许可证](LICENSE)的范围下复用我们的代码。 diff --git a/README.md b/README.md index 1544116e0388c7c7e9b2a7928a62ba37af2edf6c..1a8c190f3c2dbfc38dfc85853f7f3cc2d2a20bcb 100755 --- a/README.md +++ b/README.md @@ -211,7 +211,7 @@ In the development of iEDA, some sub-modules from the open-source community are | Sub-module | Source | Detail | | -------------- | ----------------------------------------------------------------------------------------------------- | ------------------------------------------------------------------------------------------------------------- | -| flute3 | [FastRoute](http://home.eng.iastate.edu/~cnchu/FastRoute) | Generate rectange steiner tree by flute3. | +| flute3 | [FastRoute](https://github.com/The-OpenROAD-Project-Attic/flute3) | Generate rectange steiner tree by flute3. | | abseil-cpp | [Google abseil](https://github.com/abseil/abseil-cpp.git) | Use Google's high performance C++ container and algorithm library to improve performance compared to STL. | | json | [JSON for Modern C++](https://github.com/nlohmann/json) | Json C++ library, used to parse the program Json configuration file. | | magic_enum | [Static reflection for enums (to string, from string, iteration)](https://github.com/Neargye/magic_enum) | Supports the conversion of enum values and character strings. | @@ -220,9 +220,9 @@ In the development of iEDA, some sub-modules from the open-source community are | pybind11 | [pybind 11](https://github.com/pybind/pybind11.git) | Easy for python to call C++. | | VCDParser | [ben-marshall verilog-vcd-parser](https://github.com/ben-marshall/verilog-vcd-parser.git) | Parse power VCD waveform file. | | def lef | [def lef parser](https://github.com/asyncvlsi/lefdef.git) | Parse physical layout and design DEF/LEF files. | -| ThreadPool | [Jakob Progsch, Václav Zeman threadpool](https://github.com/progschj/ThreadPool.git) | C++11 template library implementation of multithreaded pool. | +| ThreadPool | [Jakob Progsch, Václav Zeman threadpool](https://github.com/progschj/ThreadPool.git) | C++11 template library implementation of multithreaded pool. | | fft | [fft](https://www.kurims.kyoto-u.ac.jp/~ooura/fft.html) | Fast Fourier transform library. | -| hMETIS | [hMETIS](http://glaros.dtc.umn.edu/gkhome/metis/hmetis/overview) | Efficient graph partitioning algorithm. | +| hMETIS | [hMETIS](https://github.com/KarypisLab/METIS) | Efficient graph partitioning algorithm. | | lemon | [lemon](https://lemon.cs.elte.hu/trac/lemon) | Efficient modeling and optimization in graphs and networks. | | SALT | [SALT]([SALT](https://github.com/chengengjie/salt)) | Generating VLSI routing topology, It trades off between path length (shallowness) and wirelength (lightness). | | scipoptsuite | [SCIP](https://scipopt.org/index.php#welcome) | It is used to quickly solve mixed integer programming (MIP) and mixed integer nonlinear programming (MINLP). | diff --git a/src/database/data/design/IdbEnum.h b/src/database/data/design/IdbEnum.h index 29cd5009f1ab3ba267eafe89cd36dda9538b95ea..94047a3503a4bf992bc1825428a739bdc0d85151 100644 --- a/src/database/data/design/IdbEnum.h +++ b/src/database/data/design/IdbEnum.h @@ -103,14 +103,6 @@ class IdbInstancePropertyMap //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// enum class IdbSiteClass : uint8_t -{ - kNone = 0, - kCore, - kPad, - kMax -}; - -enum class IdbSiteType : uint8_t { kNone = 0, kCore, @@ -119,6 +111,15 @@ enum class IdbSiteType : uint8_t kMax }; +// enum class IdbSiteType : uint8_t +// { +// kNone = 0, +// kCore, +// kPad, +// kCorner, +// kMax +// }; + enum class IdbSymmetry : uint8_t { kNone = 0, diff --git a/src/database/data/design/IdbLayout.cpp b/src/database/data/design/IdbLayout.cpp index 8f84623cdbb603d534bedf575062be7342309961..1c327362c7aa984f0ff0ff623c192bc23e7d7a17 100644 --- a/src/database/data/design/IdbLayout.cpp +++ b/src/database/data/design/IdbLayout.cpp @@ -34,6 +34,7 @@ #include #include +#include namespace idb { @@ -112,7 +113,14 @@ IdbCore* IdbLayout::get_core() int32_t max_x = INT_MIN; int32_t max_y = INT_MIN; for (IdbRow* row : _rows->get_row_list()) { + if (row->get_site() != nullptr && row->get_site()->is_core_site() == false) { + std::cout << "Warning: row " << row->get_name() << " " << row->get_site()->get_name() << " site is not core site!" << std::endl; + continue; + } IdbRect* row_rect = row->get_bounding_box(); + if (row_rect == nullptr) { + continue; + } min_x = std::min(min_x, row_rect->get_low_x()); min_y = std::min(min_y, row_rect->get_low_y()); max_x = std::max(max_x, row_rect->get_high_x()); diff --git a/src/database/data/design/db_layout/IdbSite.cpp b/src/database/data/design/db_layout/IdbSite.cpp index 0d39ce3d122a198ebf12803c1604f8041809abd9..863862cf2209775c3ad740fcd4e0dd8076733532 100644 --- a/src/database/data/design/db_layout/IdbSite.cpp +++ b/src/database/data/design/db_layout/IdbSite.cpp @@ -67,22 +67,6 @@ IdbSite* IdbSite::clone() void IdbSite::set_class(string site_class) { _site_class = IdbEnum::GetInstance()->get_site_property()->get_class_type(site_class); - - switch (_site_class) { - case IdbSiteClass::kCore: - set_type_core(); - break; - case IdbSiteClass::kPad: - if (_width == _heigtht) { - set_type_corner(); - } else { - set_type_pad(); - } - break; - - default: - break; - } } void IdbSite::set_orient_by_enum(int32_t lef_orient) diff --git a/src/database/data/design/db_layout/IdbSite.h b/src/database/data/design/db_layout/IdbSite.h index 5d86f21b9fe53a89a1c2a53033e55dd19e81e51e..fccc327710a0786207aa80f0312f4fda7d528304 100644 --- a/src/database/data/design/db_layout/IdbSite.h +++ b/src/database/data/design/db_layout/IdbSite.h @@ -59,9 +59,9 @@ class IdbSite const int32_t get_height() const { return _heigtht; } const IdbOrient get_orient() { return _orient; } - bool is_core_site() { return _type == IdbSiteType::kCore ? true : false; } - bool is_pad_site() { return _type == IdbSiteType::kPad ? true : false; } - bool is_corner_site() { return _type == IdbSiteType::kCorner ? true : false; } + bool is_core_site() { return _site_class == IdbSiteClass::kCore ? true : false; } + bool is_pad_site() { return _site_class == IdbSiteClass::kPad ? true : false; } + bool is_corner_site() { return _site_class == IdbSiteClass::kCorner || _width == _heigtht ? true : false; } IdbSite* clone(); @@ -76,9 +76,9 @@ class IdbSite void set_width(int32_t width) { _width = width; } void set_height(int32_t height) { _heigtht = height; } - void set_type_core() { _type = IdbSiteType::kCore; } - void set_type_pad() { _type = IdbSiteType::kPad; } - void set_type_corner() { _type = IdbSiteType::kCorner; } + void set_type_core() { _site_class = IdbSiteClass::kCore; } + void set_type_pad() { _site_class = IdbSiteClass::kPad; } + void set_type_corner() { _site_class = IdbSiteClass::kCorner; } private: string _name; @@ -90,7 +90,7 @@ class IdbSite IdbSymmetry _symmetry; IdbOrient _orient; - IdbSiteType _type = IdbSiteType::kNone; + // IdbSiteType _type = IdbSiteType::kNone; // RowPattern预留 }; @@ -111,23 +111,42 @@ class IdbSites // setter void set_io_site(IdbSite* site) { - site->set_type_pad(); _io_site = site; } void set_corener_site(IdbSite* site) { - site->set_type_corner(); _corner_site = site; } void set_core_site(IdbSite* site) { - site->set_type_core(); + _core_site = site; } void set_sites_number(uint32_t number) { _site_num = number; } IdbSite* add_site_list(IdbSite* site = nullptr); IdbSite* add_site_list(string site_name); void reset(); + + bool is_core_site(string site_name){ + if(_core_site != nullptr && _core_site->get_name() == site_name){ + return true; + } + return false; + } + + bool is_corner_site(string site_name){ + if(_corner_site != nullptr && _corner_site->get_name() == site_name){ + return true; + } + return false; + } + + bool is_io_site(string site_name){ + if(_io_site != nullptr && _io_site->get_name() == site_name){ + return true; + } + return false; + } private: uint32_t _site_num; diff --git a/src/database/manager/parser/liberty/LibClassifyCell.cc b/src/database/manager/parser/liberty/LibClassifyCell.cc index 7c0aea1f8e979c7f318ff9070d098852804e9d91..6abff0b9d22ca7e212a54f4399877862dc00f6bd 100644 --- a/src/database/manager/parser/liberty/LibClassifyCell.cc +++ b/src/database/manager/parser/liberty/LibClassifyCell.cc @@ -230,7 +230,8 @@ bool LibClassifyCell::compareTimingArc(LibArcSet* set1, LibArcSet* set2) { return Str::equal(set1->front()->get_src_port(), set2->front()->get_src_port()) && Str::equal(set1->front()->get_snk_port(), set2->front()->get_snk_port()) - && set1->front()->get_timing_type() == set2->front()->get_timing_type(); + && set1->front()->get_timing_type() == set2->front()->get_timing_type() + && set1->front()->get_timing_sense() == set2->front()->get_timing_sense(); } /** @@ -315,4 +316,4 @@ void LibClassifyCell::classifyLibCell(std::vector& the_libs) } } -} // namespace ista \ No newline at end of file +} // namespace ista diff --git a/src/interface/python/CMakeLists.txt b/src/interface/python/CMakeLists.txt index 14cbe740aee29b7c05b11c0ee1382b5db7a5e745..0c5f2405c5ec711f27499850523e639af6af9e14 100644 --- a/src/interface/python/CMakeLists.txt +++ b/src/interface/python/CMakeLists.txt @@ -54,3 +54,7 @@ target_link_libraries(ieda_py py_vec py_ipnp ) + +set_target_properties(ieda_py PROPERTIES + LIBRARY_OUTPUT_DIRECTORY ${CMAKE_RUNTIME_OUTPUT_DIRECTORY} +) diff --git a/src/operation/iCTS/source/solver/Solver.cc b/src/operation/iCTS/source/solver/Solver.cc index e7173882db562a0f44ab16ef5f5092e25b46231d..5bae58ed503b1385d1363f97b2378f2b265024f4 100644 --- a/src/operation/iCTS/source/solver/Solver.cc +++ b/src/operation/iCTS/source/solver/Solver.cc @@ -226,7 +226,8 @@ std::vector Solver::assignApply(const std::vector& load_pins, const = BalanceClustering::clusteringEnhancement(enhanced_clusters, max_fanout, max_cap, max_net_len, skew_bound, 200, 0.95, 10000); } // top guide - auto guide_centers = BalanceClustering::guideCenter(enhanced_clusters, std::nullopt, TimingPropagator::getMinLength(), 1); + // auto guide_centers = BalanceClustering::guideCenter(enhanced_clusters, std::nullopt, TimingPropagator::getMinLength(), 1); + auto guide_centers = BalanceClustering::getCentroids(enhanced_clusters); std::vector next_level_load_pins; // if (_level > 1) { // higherDelayOpt(enhanced_clusters, guide_centers, next_level_load_pins); diff --git a/src/operation/iDRC/interface/DRCInterface.cpp b/src/operation/iDRC/interface/DRCInterface.cpp index 13d8f56d3360f023f7fd50637fbba8ddd31c40be..8d1aee23ad9a661e0cd6bd916a9be669ca332c61 100644 --- a/src/operation/iDRC/interface/DRCInterface.cpp +++ b/src/operation/iDRC/interface/DRCInterface.cpp @@ -87,7 +87,8 @@ void DRCInterface::checkDef() } printSummary(type_violation_map); outputViolationJson(type_violation_map); - outputSummary(type_violation_map); + // outputViolationFile(type_violation_map); + outputTofeature(type_violation_map); } void DRCInterface::destroyDRC() @@ -1187,7 +1188,47 @@ void DRCInterface::outputViolationJson(std::map>& type_violation_map) +void DRCInterface::outputViolationFile(std::map>& type_violation_map) +{ + Monitor monitor; + DRCLOG.info(Loc::current(), "Starting..."); + + std::vector& routing_layer_list = DRCDM.getDatabase().get_routing_layer_list(); + std::vector& cut_layer_list = DRCDM.getDatabase().get_cut_layer_list(); + std::string& temp_directory_path = DRCDM.getConfig().temp_directory_path; + + std::vector& idb_net_list = dmInst->get_idb_def_service()->get_design()->get_net_list()->get_net_list(); + for (auto& [type, violation_list] : type_violation_map) { + std::ofstream* violation_file = DRCUTIL.getOutputFileStream(DRCUTIL.getString(temp_directory_path, type, ".txt")); + for (ids::Violation& violation : violation_list) { + DRCUTIL.pushStream(violation_file, violation.ll_x, " ", violation.ll_y, " ", violation.ur_x, " ", violation.ur_y, " "); + if (violation.is_routing) { + DRCUTIL.pushStream(violation_file, routing_layer_list[violation.layer_idx].get_layer_name(), " "); + } else { + DRCUTIL.pushStream(violation_file, cut_layer_list[violation.layer_idx].get_layer_name(), " "); + } + DRCUTIL.pushStream(violation_file, violation.is_routing ? "true" : "false", " "); + + DRCUTIL.pushStream(violation_file, "{ "); + for (int32_t net_idx : violation.violation_net_set) { + if (net_idx != -1) { + DRCUTIL.pushStream(violation_file, idb_net_list[net_idx]->get_net_name(), " "); + } else { + DRCUTIL.pushStream(violation_file, "-1", " "); + } + } + DRCUTIL.pushStream(violation_file, "}", " "); + + DRCUTIL.pushStream(violation_file, violation.required_size, " "); + DRCUTIL.pushStream(violation_file, "\n"); + } + DRCUTIL.closeFileStream(violation_file); + } + + DRCLOG.info(Loc::current(), "Completed", monitor.getStatsInfo()); +} + +void DRCInterface::outputTofeature(std::map>& type_violation_map) { std::vector& routing_layer_list = DRCDM.getDatabase().get_routing_layer_list(); std::vector& cut_layer_list = DRCDM.getDatabase().get_cut_layer_list(); diff --git a/src/operation/iDRC/interface/DRCInterface.hpp b/src/operation/iDRC/interface/DRCInterface.hpp index 7675b5be85e997ba16fad471ca63cd7655694af2..15937d8f4afb57d58d44d027f3bcc730f333fab0 100644 --- a/src/operation/iDRC/interface/DRCInterface.hpp +++ b/src/operation/iDRC/interface/DRCInterface.hpp @@ -99,7 +99,8 @@ class DRCInterface std::vector buildResultShapeList(); void printSummary(std::map>& type_violation_map); void outputViolationJson(std::map>& type_violation_map); - void outputSummary(std::map>& type_violation_map); + void outputViolationFile(std::map>& type_violation_map); + void outputTofeature(std::map>& type_violation_map); DRCShape convertToDRCShape(const ids::Shape& ids_shape); #endif diff --git a/src/operation/iDRC/source/module/rule_validator/RuleValidator.cpp b/src/operation/iDRC/source/module/rule_validator/RuleValidator.cpp index 7b9270da71d2d8c59fa8ac8607a2742444ac5d70..cec6e29f1d5c685382d2f185ece28a72669899a9 100644 --- a/src/operation/iDRC/source/module/rule_validator/RuleValidator.cpp +++ b/src/operation/iDRC/source/module/rule_validator/RuleValidator.cpp @@ -59,7 +59,6 @@ std::vector RuleValidator::verify(std::vector& drc_env_shap verifyRVModel(rv_model); buildViolationList(rv_model); // debugPlotRVModel(rv_model, "best"); - // debugOutputViolation(rv_model); DRCLOG.info(Loc::current(), "Completed", monitor.getStatsInfo()); return rv_model.get_violation_list(); } @@ -183,7 +182,7 @@ void RuleValidator::verifyRVModel(RVModel& rv_model) { Monitor monitor; DRCLOG.info(Loc::current(), "Starting..."); -#pragma omp parallel for +#pragma omp parallel for schedule(dynamic) for (RVCluster& rv_cluster : rv_model.get_rv_cluster_list()) { buildRVCluster(rv_cluster); if (needVerifying(rv_cluster)) { @@ -544,45 +543,6 @@ void RuleValidator::debugPlotRVCluster(RVCluster& rv_cluster, std::string flag) DRCGP.plot(gp_gds, gds_file_path); } -void RuleValidator::debugOutputViolation(RVModel& rv_model) -{ - Monitor monitor; - DRCLOG.info(Loc::current(), "Starting..."); - - std::vector& routing_layer_list = DRCDM.getDatabase().get_routing_layer_list(); - std::vector& cut_layer_list = DRCDM.getDatabase().get_cut_layer_list(); - std::string& rv_temp_directory_path = DRCDM.getConfig().rv_temp_directory_path; - - std::map> type_violation_list_map; - for (Violation& violation : rv_model.get_violation_list()) { - type_violation_list_map[violation.get_violation_type()].push_back(&violation); - } - for (auto& [type, violation_list] : type_violation_list_map) { - std::ofstream* violation_file = DRCUTIL.getOutputFileStream(DRCUTIL.getString(rv_temp_directory_path, GetViolationTypeName()(type), ".txt")); - for (Violation* violation : violation_list) { - DRCUTIL.pushStream(violation_file, violation->get_ll_x(), " ", violation->get_ll_y(), " ", violation->get_ur_x(), " ", violation->get_ur_y(), " "); - if (violation->get_is_routing()) { - DRCUTIL.pushStream(violation_file, routing_layer_list[violation->get_layer_idx()].get_layer_name(), " "); - } else { - DRCUTIL.pushStream(violation_file, cut_layer_list[violation->get_layer_idx()].get_layer_name(), " "); - } - DRCUTIL.pushStream(violation_file, violation->get_is_routing() ? "true" : "false", " "); - - DRCUTIL.pushStream(violation_file, "{ "); - for (int32_t net_idx : violation->get_violation_net_set()) { - DRCUTIL.pushStream(violation_file, net_idx, " "); - } - DRCUTIL.pushStream(violation_file, "}", " "); - - DRCUTIL.pushStream(violation_file, violation->get_required_size(), " "); - DRCUTIL.pushStream(violation_file, "\n"); - } - DRCUTIL.closeFileStream(violation_file); - } - - DRCLOG.info(Loc::current(), "Completed", monitor.getStatsInfo()); -} - #endif } // namespace idrc diff --git a/src/operation/iDRC/source/module/rule_validator/RuleValidator.hpp b/src/operation/iDRC/source/module/rule_validator/RuleValidator.hpp index 2c54c2570a2de4fe49207d27b0eea22a0f55e2da..fdf95eaed0c5c61290ae76f5ec193fa00d003b2f 100644 --- a/src/operation/iDRC/source/module/rule_validator/RuleValidator.hpp +++ b/src/operation/iDRC/source/module/rule_validator/RuleValidator.hpp @@ -94,7 +94,6 @@ class RuleValidator #if 1 // debug void debugPlotRVModel(RVModel& rv_model, std::string flag); void debugPlotRVCluster(RVCluster& rv_cluster, std::string flag); - void debugOutputViolation(RVModel& rv_model); #endif }; diff --git a/src/operation/iFP/source/module/init_design/init_design.cpp b/src/operation/iFP/source/module/init_design/init_design.cpp index 41eae431f1e7ea2b7ef04638ded838336010e8e7..5c69b1b3977e5642cf16b0e1526b5fb02889ff06 100644 --- a/src/operation/iFP/source/module/init_design/init_design.cpp +++ b/src/operation/iFP/source/module/init_design/init_design.cpp @@ -88,7 +88,11 @@ bool InitDesign::initCore(double core_lx, double core_ly, double core_ux, double auto orient = row % 2 == 0 ? idb::IdbOrient::kFS_MX : idb::IdbOrient::kN_R0; /// set original horizontal - dmInst->createRow(("ROW_" + std::to_string(row)), core_site_name, core_lx_int, index_y, orient, site_number, 1, site_dx, 0); + auto idb_row = dmInst->createRow(("ROW_" + std::to_string(row)), core_site_name, core_lx_int, index_y, orient, site_number, 1, site_dx, 0); + if (idb_row->get_site()->is_core_site() == false) { + std::cout << "crate row " << idb_row->get_name() << " " << idb_row->get_site()->get_name() << " is not core site!" << std::endl; + continue; + } index_y += site_dy; } diff --git a/src/operation/iPA/test/CMakeLists.txt b/src/operation/iPA/test/CMakeLists.txt index 93e87f184bfac1f333f87d8198a771de705154d4..0d6b3651a7b1cecf128015811e791980c8ec1a8f 100644 --- a/src/operation/iPA/test/CMakeLists.txt +++ b/src/operation/iPA/test/CMakeLists.txt @@ -5,21 +5,22 @@ set(CMAKE_CXX_STANDARD 20) SET(CMAKE_BUILD_TYPE "Debug") find_package(GTest REQUIRED) +find_package(Boost REQUIRED) aux_source_directory(./ SRC) -add_executable(iPowerTest ${SRC}) +# add_executable(iPowerTest ${SRC}) -target_link_libraries( - iPowerTest - PUBLIC - gtest - gtest_main - boost_system - PRIVATE - vcd_wrapper - log - power - usage ista-engine core calc_power plot_power +# target_link_libraries( +# iPowerTest +# PUBLIC +# gtest +# gtest_main +# Boost::headers +# PRIVATE +# vcd_wrapper +# log +# power +# usage ista-engine core calc_power plot_power -) +# ) diff --git a/src/operation/iPL/api/PLAPI.cc b/src/operation/iPL/api/PLAPI.cc index 158b13ffa42b20f6c816159ffccbe6ce8d392bb4..8cf4638ba5064b6e00378fe7390de5173117b2e5 100644 --- a/src/operation/iPL/api/PLAPI.cc +++ b/src/operation/iPL/api/PLAPI.cc @@ -841,7 +841,8 @@ bool PLAPI::checkLegality() bool PLAPI::isSTAStarted() { - return _external_api->isSTAStarted(); + // return _external_api->isSTAStarted(); + return false; } bool PLAPI::isPlacerDBStarted() diff --git a/src/operation/iRT/source/module/detailed_router/DetailedRouter.cpp b/src/operation/iRT/source/module/detailed_router/DetailedRouter.cpp index 404a3bec8998a24ac2d10e4a65ebf2e29cab6a0e..2ed7a0cd841b4147c8392ffe6f597e53acfc7194 100644 --- a/src/operation/iRT/source/module/detailed_router/DetailedRouter.cpp +++ b/src/operation/iRT/source/module/detailed_router/DetailedRouter.cpp @@ -119,9 +119,12 @@ void DetailedRouter::routeDRModel(DRModel& dr_model) dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 0, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 3, 10); dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 4, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 3, 10); dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 8, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 3, 10); - dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 0, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 3, 10); - dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 4, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 3, 10); - dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 8, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 3, 10); + dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 0, 3, 2 * fixed_rect_unit, 2 * routed_rect_unit, 2 * violation_unit, 3, 10); + dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 4, 3, 2 * fixed_rect_unit, 2 * routed_rect_unit, 2 * violation_unit, 3, 10); + dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 8, 3, 2 * fixed_rect_unit, 2 * routed_rect_unit, 2 * violation_unit, 3, 10); + dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 0, 3, 4 * fixed_rect_unit, 4 * routed_rect_unit, 4 * violation_unit, 3, 10); + dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 4, 3, 4 * fixed_rect_unit, 4 * routed_rect_unit, 4 * violation_unit, 3, 10); + dr_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, bend_unit, via_unit, 12, 8, 3, 4 * fixed_rect_unit, 4 * routed_rect_unit, 4 * violation_unit, 3, 10); // clang-format on initRoutingState(dr_model); for (int32_t i = 0, iter = 1; i < static_cast(dr_iter_param_list.size()); i++, iter++) { diff --git a/src/operation/iRT/source/module/drc_engine/DRCEngine.cpp b/src/operation/iRT/source/module/drc_engine/DRCEngine.cpp index 027dfef660247cba49aac943921504926dbb527a..59ceaf5d2c922a66717c3a8a6abcf2a202b29b57 100644 --- a/src/operation/iRT/source/module/drc_engine/DRCEngine.cpp +++ b/src/operation/iRT/source/module/drc_engine/DRCEngine.cpp @@ -71,18 +71,6 @@ std::vector DRCEngine::getViolationList(DETask& de_task) return de_task.get_violation_list(); } -void DRCEngine::addTempIgnoredViolation(std::vector& violation_list) -{ - for (Violation& violation : violation_list) { - _temp_ignored_violation_set.insert(violation); - } -} - -void DRCEngine::clearTempIgnoredViolationSet() -{ - _temp_ignored_violation_set.clear(); -} - void DRCEngine::destroy() { Monitor monitor; @@ -172,7 +160,7 @@ void DRCEngine::filterViolationList(DETask& de_task) // net不包含布线net的舍弃 continue; } - if (RTUTIL.exist(_ignored_violation_set, violation) || RTUTIL.exist(_temp_ignored_violation_set, violation)) { + if (RTUTIL.exist(_ignored_violation_set, violation)) { // 自带的违例舍弃 continue; } diff --git a/src/operation/iRT/source/module/drc_engine/DRCEngine.hpp b/src/operation/iRT/source/module/drc_engine/DRCEngine.hpp index c02f80b71f8942d78336d807854dca86a02b6ffa..088f07ac4730cae34cce3df59aee8961b9313ab3 100644 --- a/src/operation/iRT/source/module/drc_engine/DRCEngine.hpp +++ b/src/operation/iRT/source/module/drc_engine/DRCEngine.hpp @@ -35,15 +35,12 @@ class DRCEngine // function void init(); std::vector getViolationList(DETask& de_task); - void addTempIgnoredViolation(std::vector& violation_list); - void clearTempIgnoredViolationSet(); void destroy(); private: // self static DRCEngine* _de_instance; std::set _ignored_violation_set; - std::set _temp_ignored_violation_set; DRCEngine() = default; DRCEngine(const DRCEngine& other) = delete; diff --git a/src/operation/iRT/source/module/early_router/EarlyRouter.cpp b/src/operation/iRT/source/module/early_router/EarlyRouter.cpp index 385cfa17ea1f4b756bb60447487b6b065369f1d4..61d60bc81c753108f6c1048d4331a766f0270b25 100644 --- a/src/operation/iRT/source/module/early_router/EarlyRouter.cpp +++ b/src/operation/iRT/source/module/early_router/EarlyRouter.cpp @@ -2763,7 +2763,8 @@ void EarlyRouter::outputPlanarSupplyCSV(ERModel& er_model) int32_t total_supply = 0; for (RoutingLayer& routing_layer : routing_layer_list) { for (auto& [orient, supply] : gcell_map[x][y].get_routing_orient_supply_map()[routing_layer.get_layer_idx()]) { - total_supply += supply; + // boundary_supply + internal_supply + total_supply += (2 * supply); } } RTUTIL.pushStream(supply_csv_file, total_supply, ","); @@ -2905,7 +2906,8 @@ void EarlyRouter::outputLayerSupplyCSV(ERModel& er_model) for (int32_t x = 0; x < gcell_map.get_x_size(); x++) { int32_t total_supply = 0; for (auto& [orient, supply] : gcell_map[x][y].get_routing_orient_supply_map()[routing_layer.get_layer_idx()]) { - total_supply += supply; + // boundary_supply + internal_supply + total_supply += (2 * supply); } RTUTIL.pushStream(supply_csv_file, total_supply, ","); } @@ -3186,8 +3188,9 @@ void EarlyRouter::printSupplySummary(ERModel& er_model) for (int32_t y = 0; y < gcell_map.get_y_size(); y++) { for (auto& [routing_layer_idx, orient_supply_map] : gcell_map[x][y].get_routing_orient_supply_map()) { for (auto& [orient, supply] : orient_supply_map) { - routing_supply_map[routing_layer_idx] += supply; - total_supply += supply; + // boundary_supply + internal_supply + routing_supply_map[routing_layer_idx] += (2 * supply); + total_supply += (2 * supply); } } } diff --git a/src/operation/iRT/source/module/early_router/er_data_manager/ERNode.hpp b/src/operation/iRT/source/module/early_router/er_data_manager/ERNode.hpp index d312699006be80e3bc4ad7ff11993057bc0e7cfc..f0204f6439dabf2e7a740ac49a3e5b0eb432f2ad 100644 --- a/src/operation/iRT/source/module/early_router/er_data_manager/ERNode.hpp +++ b/src/operation/iRT/source/module/early_router/er_data_manager/ERNode.hpp @@ -89,7 +89,7 @@ class ERNode : public LayerCoord } double boundary_supply = 0; if (RTUTIL.exist(_orient_supply_map, orient)) { - boundary_supply = (_orient_supply_map[orient] * _boundary_wire_unit); + boundary_supply = _orient_supply_map[orient]; } boundary_overflow += calcCost(boundary_demand, boundary_supply); } @@ -121,7 +121,7 @@ class ERNode : public LayerCoord } double internal_supply = 0; for (auto& [orient, supply] : _orient_supply_map) { - internal_supply += (supply * _internal_wire_unit); + internal_supply += supply; } internal_overflow += calcCost(internal_demand, internal_supply); } @@ -162,16 +162,30 @@ class ERNode : public LayerCoord double boundary_demand = 0; for (Orientation orient : {Orientation::kEast, Orientation::kWest, Orientation::kSouth, Orientation::kNorth}) { if (RTUTIL.exist(_orient_net_map, orient)) { - boundary_demand += (static_cast(_orient_net_map[orient].size()) * _boundary_wire_unit); + for (int32_t demand_net_idx : _orient_net_map[orient]) { + if (RTUTIL.exist(_ignore_net_orient_map, demand_net_idx) && RTUTIL.exist(_ignore_net_orient_map[demand_net_idx], orient)) { + continue; + } + boundary_demand += _boundary_wire_unit; + } } } double internal_demand = 0; for (Orientation orient : {Orientation::kEast, Orientation::kWest, Orientation::kSouth, Orientation::kNorth}) { if (RTUTIL.exist(_orient_net_map, orient)) { - internal_demand += (static_cast(_orient_net_map[orient].size()) * _internal_wire_unit); + for (int32_t demand_net_idx : _orient_net_map[orient]) { + if (RTUTIL.exist(_ignore_net_orient_map, demand_net_idx) && RTUTIL.exist(_ignore_net_orient_map[demand_net_idx], orient)) { + continue; + } + internal_demand += _internal_wire_unit; + } } } for (auto& [net_idx, orient_set] : _net_orient_map) { + if (RTUTIL.exist(_ignore_net_orient_map, net_idx) + && (RTUTIL.exist(_ignore_net_orient_map[net_idx], Orientation::kAbove) || RTUTIL.exist(_ignore_net_orient_map[net_idx], Orientation::kBelow))) { + continue; + } if (RTUTIL.exist(orient_set, Orientation::kEast) || RTUTIL.exist(orient_set, Orientation::kWest) || RTUTIL.exist(orient_set, Orientation::kSouth) || RTUTIL.exist(orient_set, Orientation::kNorth)) { continue; @@ -200,7 +214,7 @@ class ERNode : public LayerCoord } double boundary_supply = 0; if (RTUTIL.exist(_orient_supply_map, orient)) { - boundary_supply = (_orient_supply_map[orient] * _boundary_wire_unit); + boundary_supply = _orient_supply_map[orient]; } boundary_overflow += std::max(0.0, boundary_demand - boundary_supply); } @@ -232,7 +246,7 @@ class ERNode : public LayerCoord } double internal_supply = 0; for (auto& [orient, supply] : _orient_supply_map) { - internal_supply += (supply * _internal_wire_unit); + internal_supply += supply; } internal_overflow += std::max(0.0, internal_demand - internal_supply); } diff --git a/src/operation/iRT/source/module/layer_assigner/la_data_manager/LANode.hpp b/src/operation/iRT/source/module/layer_assigner/la_data_manager/LANode.hpp index ded3f0d55eee1fa52c3c7a69686f67707d56ce9c..05968519aadf686a26012993b314e46f3c51fd12 100644 --- a/src/operation/iRT/source/module/layer_assigner/la_data_manager/LANode.hpp +++ b/src/operation/iRT/source/module/layer_assigner/la_data_manager/LANode.hpp @@ -89,7 +89,7 @@ class LANode : public LayerCoord } double boundary_supply = 0; if (RTUTIL.exist(_orient_supply_map, orient)) { - boundary_supply = (_orient_supply_map[orient] * _boundary_wire_unit); + boundary_supply = _orient_supply_map[orient]; } boundary_overflow += calcCost(boundary_demand, boundary_supply); } @@ -121,7 +121,7 @@ class LANode : public LayerCoord } double internal_supply = 0; for (auto& [orient, supply] : _orient_supply_map) { - internal_supply += (supply * _internal_wire_unit); + internal_supply += supply; } internal_overflow += calcCost(internal_demand, internal_supply); } @@ -162,16 +162,30 @@ class LANode : public LayerCoord double boundary_demand = 0; for (Orientation orient : {Orientation::kEast, Orientation::kWest, Orientation::kSouth, Orientation::kNorth}) { if (RTUTIL.exist(_orient_net_map, orient)) { - boundary_demand += (static_cast(_orient_net_map[orient].size()) * _boundary_wire_unit); + for (int32_t demand_net_idx : _orient_net_map[orient]) { + if (RTUTIL.exist(_ignore_net_orient_map, demand_net_idx) && RTUTIL.exist(_ignore_net_orient_map[demand_net_idx], orient)) { + continue; + } + boundary_demand += _boundary_wire_unit; + } } } double internal_demand = 0; for (Orientation orient : {Orientation::kEast, Orientation::kWest, Orientation::kSouth, Orientation::kNorth}) { if (RTUTIL.exist(_orient_net_map, orient)) { - internal_demand += (static_cast(_orient_net_map[orient].size()) * _internal_wire_unit); + for (int32_t demand_net_idx : _orient_net_map[orient]) { + if (RTUTIL.exist(_ignore_net_orient_map, demand_net_idx) && RTUTIL.exist(_ignore_net_orient_map[demand_net_idx], orient)) { + continue; + } + internal_demand += _internal_wire_unit; + } } } for (auto& [net_idx, orient_set] : _net_orient_map) { + if (RTUTIL.exist(_ignore_net_orient_map, net_idx) + && (RTUTIL.exist(_ignore_net_orient_map[net_idx], Orientation::kAbove) || RTUTIL.exist(_ignore_net_orient_map[net_idx], Orientation::kBelow))) { + continue; + } if (RTUTIL.exist(orient_set, Orientation::kEast) || RTUTIL.exist(orient_set, Orientation::kWest) || RTUTIL.exist(orient_set, Orientation::kSouth) || RTUTIL.exist(orient_set, Orientation::kNorth)) { continue; @@ -200,7 +214,7 @@ class LANode : public LayerCoord } double boundary_supply = 0; if (RTUTIL.exist(_orient_supply_map, orient)) { - boundary_supply = (_orient_supply_map[orient] * _boundary_wire_unit); + boundary_supply = _orient_supply_map[orient]; } boundary_overflow += std::max(0.0, boundary_demand - boundary_supply); } @@ -232,7 +246,7 @@ class LANode : public LayerCoord } double internal_supply = 0; for (auto& [orient, supply] : _orient_supply_map) { - internal_supply += (supply * _internal_wire_unit); + internal_supply += supply; } internal_overflow += std::max(0.0, internal_demand - internal_supply); } diff --git a/src/operation/iRT/source/module/pin_accessor/PinAccessor.cpp b/src/operation/iRT/source/module/pin_accessor/PinAccessor.cpp index bfaee7f710c426d8af97c78c64e1bbdf40d6aed6..90df1001d179b0da4f99b2181b7ff3677f9876ee 100644 --- a/src/operation/iRT/source/module/pin_accessor/PinAccessor.cpp +++ b/src/operation/iRT/source/module/pin_accessor/PinAccessor.cpp @@ -552,9 +552,9 @@ void PinAccessor::routePAModel(PAModel& pa_model) pa_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, via_unit, 3, 0, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 20, 10); pa_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, via_unit, 3, 1, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 20, 10); pa_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, via_unit, 3, 2, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 20, 10); - pa_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, via_unit, 3, 0, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 20, 10); - pa_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, via_unit, 3, 1, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 20, 10); - pa_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, via_unit, 3, 2, 3, fixed_rect_unit, routed_rect_unit, violation_unit, 20, 10); + pa_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, via_unit, 3, 0, 3, 2 * fixed_rect_unit, 2 * routed_rect_unit, 2 * violation_unit, 20, 10); + pa_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, via_unit, 3, 1, 3, 2 * fixed_rect_unit, 2 * routed_rect_unit, 2 * violation_unit, 20, 10); + pa_iter_param_list.emplace_back(prefer_wire_unit, non_prefer_wire_unit, via_unit, 3, 2, 3, 2 * fixed_rect_unit, 2 * routed_rect_unit, 2 * violation_unit, 20, 10); // clang-format on initRoutingState(pa_model); for (int32_t i = 0, iter = 1; i < static_cast(pa_iter_param_list.size()); i++, iter++) { diff --git a/src/operation/iRT/source/module/space_router/sr_data_manager/SRNode.hpp b/src/operation/iRT/source/module/space_router/sr_data_manager/SRNode.hpp index 9db971ae3a720475737fe5d2bcff2950a0d8f113..530d324d1e348c6fb52a83261dee27c7d91cb016 100644 --- a/src/operation/iRT/source/module/space_router/sr_data_manager/SRNode.hpp +++ b/src/operation/iRT/source/module/space_router/sr_data_manager/SRNode.hpp @@ -103,7 +103,7 @@ class SRNode : public LayerCoord } double boundary_supply = 0; if (RTUTIL.exist(_orient_supply_map, orient)) { - boundary_supply = (_orient_supply_map[orient] * _boundary_wire_unit); + boundary_supply = _orient_supply_map[orient]; } boundary_overflow += calcCost(boundary_demand, boundary_supply); } @@ -135,7 +135,7 @@ class SRNode : public LayerCoord } double internal_supply = 0; for (auto& [orient, supply] : _orient_supply_map) { - internal_supply += (supply * _internal_wire_unit); + internal_supply += supply; } internal_overflow += calcCost(internal_demand, internal_supply); } @@ -176,16 +176,30 @@ class SRNode : public LayerCoord double boundary_demand = 0; for (Orientation orient : {Orientation::kEast, Orientation::kWest, Orientation::kSouth, Orientation::kNorth}) { if (RTUTIL.exist(_orient_net_map, orient)) { - boundary_demand += (static_cast(_orient_net_map[orient].size()) * _boundary_wire_unit); + for (int32_t demand_net_idx : _orient_net_map[orient]) { + if (RTUTIL.exist(_ignore_net_orient_map, demand_net_idx) && RTUTIL.exist(_ignore_net_orient_map[demand_net_idx], orient)) { + continue; + } + boundary_demand += _boundary_wire_unit; + } } } double internal_demand = 0; for (Orientation orient : {Orientation::kEast, Orientation::kWest, Orientation::kSouth, Orientation::kNorth}) { if (RTUTIL.exist(_orient_net_map, orient)) { - internal_demand += (static_cast(_orient_net_map[orient].size()) * _internal_wire_unit); + for (int32_t demand_net_idx : _orient_net_map[orient]) { + if (RTUTIL.exist(_ignore_net_orient_map, demand_net_idx) && RTUTIL.exist(_ignore_net_orient_map[demand_net_idx], orient)) { + continue; + } + internal_demand += _internal_wire_unit; + } } } for (auto& [net_idx, orient_set] : _net_orient_map) { + if (RTUTIL.exist(_ignore_net_orient_map, net_idx) + && (RTUTIL.exist(_ignore_net_orient_map[net_idx], Orientation::kAbove) || RTUTIL.exist(_ignore_net_orient_map[net_idx], Orientation::kBelow))) { + continue; + } if (RTUTIL.exist(orient_set, Orientation::kEast) || RTUTIL.exist(orient_set, Orientation::kWest) || RTUTIL.exist(orient_set, Orientation::kSouth) || RTUTIL.exist(orient_set, Orientation::kNorth)) { continue; @@ -214,7 +228,7 @@ class SRNode : public LayerCoord } double boundary_supply = 0; if (RTUTIL.exist(_orient_supply_map, orient)) { - boundary_supply = (_orient_supply_map[orient] * _boundary_wire_unit); + boundary_supply = _orient_supply_map[orient]; } boundary_overflow += std::max(0.0, boundary_demand - boundary_supply); } @@ -246,7 +260,7 @@ class SRNode : public LayerCoord } double internal_supply = 0; for (auto& [orient, supply] : _orient_supply_map) { - internal_supply += (supply * _internal_wire_unit); + internal_supply += supply; } internal_overflow += std::max(0.0, internal_demand - internal_supply); } @@ -270,7 +284,7 @@ class SRNode : public LayerCoord } double boundary_supply = 0; if (RTUTIL.exist(_orient_supply_map, orient)) { - boundary_supply = (_orient_supply_map[orient] * _boundary_wire_unit); + boundary_supply = _orient_supply_map[orient]; } if (boundary_demand - boundary_supply > 0) { overflow_net_set.insert(_orient_net_map[orient].begin(), _orient_net_map[orient].end()); @@ -303,7 +317,7 @@ class SRNode : public LayerCoord } double internal_supply = 0; for (auto& [orient, supply] : _orient_supply_map) { - internal_supply += (supply * _internal_wire_unit); + internal_supply += supply; } if (internal_demand - internal_supply > 0) { for (auto& [net_idx, orient_set] : _net_orient_map) { diff --git a/src/operation/iRT/source/module/supply_analyzer/SupplyAnalyzer.cpp b/src/operation/iRT/source/module/supply_analyzer/SupplyAnalyzer.cpp index ccf8db35150485cadc7eae109ac1c5d1cd36ca07..baa3999f42116c98945e5fab22a03632633f42c7 100644 --- a/src/operation/iRT/source/module/supply_analyzer/SupplyAnalyzer.cpp +++ b/src/operation/iRT/source/module/supply_analyzer/SupplyAnalyzer.cpp @@ -400,8 +400,9 @@ void SupplyAnalyzer::updateSummary(SAModel& sa_model) for (int32_t y = 0; y < gcell_map.get_y_size(); y++) { for (auto& [routing_layer_idx, orient_supply_map] : gcell_map[x][y].get_routing_orient_supply_map()) { for (auto& [orient, supply] : orient_supply_map) { - routing_supply_map[routing_layer_idx] += supply; - total_supply += supply; + // boundary_supply + internal_supply + routing_supply_map[routing_layer_idx] += (2 * supply); + total_supply += (2 * supply); } } } @@ -449,7 +450,8 @@ void SupplyAnalyzer::outputPlanarSupplyCSV(SAModel& sa_model) int32_t total_supply = 0; for (RoutingLayer& routing_layer : routing_layer_list) { for (auto& [orient, supply] : gcell_map[x][y].get_routing_orient_supply_map()[routing_layer.get_layer_idx()]) { - total_supply += supply; + // boundary_supply + internal_supply + total_supply += (2 * supply); } } RTUTIL.pushStream(supply_csv_file, total_supply, ","); @@ -479,7 +481,8 @@ void SupplyAnalyzer::outputLayerSupplyCSV(SAModel& sa_model) for (int32_t x = 0; x < gcell_map.get_x_size(); x++) { int32_t total_supply = 0; for (auto& [orient, supply] : gcell_map[x][y].get_routing_orient_supply_map()[routing_layer.get_layer_idx()]) { - total_supply += supply; + // boundary_supply + internal_supply + total_supply += (2 * supply); } RTUTIL.pushStream(supply_csv_file, total_supply, ","); } diff --git a/src/operation/iRT/source/module/topology_generator/TopologyGenerator.cpp b/src/operation/iRT/source/module/topology_generator/TopologyGenerator.cpp index b1cd31e280bf878ec6861f011fa3e1f81fd673e3..6950b500a070174dd48cb849e009106dcf462889 100644 --- a/src/operation/iRT/source/module/topology_generator/TopologyGenerator.cpp +++ b/src/operation/iRT/source/module/topology_generator/TopologyGenerator.cpp @@ -110,9 +110,9 @@ TGNet TopologyGenerator::convertToTGNet(Net& net) void TopologyGenerator::setTGComParam(TGModel& tg_model) { - int32_t topo_spilt_length = 10; - int32_t expand_step_num = 5; - int32_t expand_step_length = 2; + int32_t topo_spilt_length = 30; + int32_t expand_step_num = 30; + int32_t expand_step_length = 1; double prefer_wire_unit = 1; double non_prefer_wire_unit = 2.5 * prefer_wire_unit; double overflow_unit = 4 * non_prefer_wire_unit; diff --git a/src/operation/iRT/source/module/topology_generator/tg_data_manager/TGNode.hpp b/src/operation/iRT/source/module/topology_generator/tg_data_manager/TGNode.hpp index fee544c878e06d71fc128acc98ad6edfe071e1e5..5cf0a807d6c2370bbfcbaf8d632b6dd591291ce4 100644 --- a/src/operation/iRT/source/module/topology_generator/tg_data_manager/TGNode.hpp +++ b/src/operation/iRT/source/module/topology_generator/tg_data_manager/TGNode.hpp @@ -89,7 +89,7 @@ class TGNode : public PlanarCoord } double boundary_supply = 0; if (RTUTIL.exist(_orient_supply_map, orient)) { - boundary_supply = (_orient_supply_map[orient] * _boundary_wire_unit); + boundary_supply = _orient_supply_map[orient]; } boundary_overflow += calcCost(boundary_demand, boundary_supply); } @@ -108,7 +108,7 @@ class TGNode : public PlanarCoord } double internal_supply = 0; for (auto& [orient, supply] : _orient_supply_map) { - internal_supply += (supply * _internal_wire_unit); + internal_supply += supply; } internal_overflow += calcCost(internal_demand, internal_supply); } @@ -146,13 +146,23 @@ class TGNode : public PlanarCoord double boundary_demand = 0; for (Orientation orient : {Orientation::kEast, Orientation::kWest, Orientation::kSouth, Orientation::kNorth}) { if (RTUTIL.exist(_orient_net_map, orient)) { - boundary_demand += (static_cast(_orient_net_map[orient].size()) * _boundary_wire_unit); + for (int32_t demand_net_idx : _orient_net_map[orient]) { + if (RTUTIL.exist(_ignore_net_orient_map, demand_net_idx) && RTUTIL.exist(_ignore_net_orient_map[demand_net_idx], orient)) { + continue; + } + boundary_demand += _boundary_wire_unit; + } } } double internal_demand = 0; for (Orientation orient : {Orientation::kEast, Orientation::kWest, Orientation::kSouth, Orientation::kNorth}) { if (RTUTIL.exist(_orient_net_map, orient)) { - internal_demand += (static_cast(_orient_net_map[orient].size()) * _internal_wire_unit); + for (int32_t demand_net_idx : _orient_net_map[orient]) { + if (RTUTIL.exist(_ignore_net_orient_map, demand_net_idx) && RTUTIL.exist(_ignore_net_orient_map[demand_net_idx], orient)) { + continue; + } + internal_demand += _internal_wire_unit; + } } } return (boundary_demand + internal_demand); @@ -175,7 +185,7 @@ class TGNode : public PlanarCoord } double boundary_supply = 0; if (RTUTIL.exist(_orient_supply_map, orient)) { - boundary_supply = (_orient_supply_map[orient] * _boundary_wire_unit); + boundary_supply = _orient_supply_map[orient]; } boundary_overflow += std::max(0.0, boundary_demand - boundary_supply); } @@ -194,7 +204,7 @@ class TGNode : public PlanarCoord } double internal_supply = 0; for (auto& [orient, supply] : _orient_supply_map) { - internal_supply += (supply * _internal_wire_unit); + internal_supply += supply; } internal_overflow += std::max(0.0, internal_demand - internal_supply); } diff --git a/src/operation/iSTA/api/TimingEngine.cc b/src/operation/iSTA/api/TimingEngine.cc index 1ff881c3c7a922505fd4a4b08118cb1db562065b..76d179d6df60ceea55aa09c9ec69d7c0dbd317e1 100644 --- a/src/operation/iSTA/api/TimingEngine.cc +++ b/src/operation/iSTA/api/TimingEngine.cc @@ -1770,6 +1770,11 @@ unsigned TimingEngine::isSequentialCell(const char* instance_name) { auto* design_instance = design_netlist->findInstance(instance_name); auto* lib_cell = design_instance->get_inst_cell(); + if (lib_cell == nullptr) { + LOG_WARNING << "Can not find cell name = " << instance_name; + return 0; + } + bool is_sequential = lib_cell->isSequentialCell(); return is_sequential;