# efang

**Repository Path**: pei-jun-chen/efang

## Basic Information

- **Project Name**: efang
- **Description**: riscv cpu core
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2024-01-15
- **Last Updated**: 2024-12-03

## Categories & Tags

**Categories**: Uncategorized

**Tags**: riscv, Verilog, CPU

## README

RISC-V的CPU核，基本整数指令集，不带乘除，不带原子操作，带中断，带CSR寄存器.


var name:
parameter input start with: i_, e.g.
input  [AW-1:0] i_reset_pc,

parameter output start with: o_, e.g.
output o_cmd_valid, // Handshake valid

exception: clk, rst_n(0 valid)

local reg end with: -r, e.g.
reg[AW-1:0] pc_r;