# LogicLoopChecker

**Repository Path**: phane99/logic-loop-checker

## Basic Information

- **Project Name**: LogicLoopChecker
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2024-10-22
- **Last Updated**: 2024-10-25

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

This package includes the gate-level netlists and the VPI C code for 
getting the gate instance and connections by different logic simulators.
You can run the run.sh script in each simulator directory to get all
netlist instance info.

Update date: 2024.09.24
  Updated the testcase reference results.

Content:
├── README                              : This File   
│
├── code                                : VPI C code to get gate instance
│   │                                     and node connection for different simulators.
│   ├── setUpSystemFunc.cpp             : Code for vcs and xcelium.
│   ├── setUpSystemFunc_iverilog.cpp    : Code for iverilog.
│   ├── setUpSystemFunc_verisim.cpp     : Code for verisim.
│   ├── sv_vpi_user.h, vpi_user.h       : VPI header files.
│   └── systf.tab                       : VPI map file, used for VPI system task mapping.
│
├── testcase                            : Test case directory, includes different scale 
│   │                                     gate-level netlists. There are also reference
│   │                                     results in each test case.
│   ├── test.v                          : Example case
│   ├── gate_1000_1000_50.v
│   ├── gate_100_100_20.v
│   ├── gate_200_200_20.v
│   ├── gate_20_20_10.v
│   ├── gate_20_20_5.v
│   ├── gate_30_30_10.v
│   ├── gate_40_40_10.v
│   └── gate_500_500_50.v
│ 
├── iverilog                            : The iverilog simulator directory.
│   ├── iverilog_11_vpiHighConn.patch   : The iverilog code patch for supporting get model
│   │                                     port highconn function by VPI.
│   └── run.sh                          : Startup script for iverilog.
│
├── verisim                             : Verisim simulator directory
│   └── run.sh                          : Startup script for Verisim.
│
├── vcs                                 : Vcs simulator directory
│   └── run.sh                          : Startup script for vcs
│
└── xrun                                : Xcelium simulator directory
    └── run.sh                          : Startup script for xcelium.


Usage:
  1. For verisim, vcs and xcelium, run run.sh file in the verisim/vcs/xrun directory.
  2. For iverilog, because iverilog does not fully support VPI, you need apply a code patch firstly to enhance the iverilog VPI function.
     The code patch is based on iverilog v11 and is located under iverilog directory, named "iverilog_11_vpiHighConn.patch".
     After you recompile iverilog with the code patch, run the run.sh script under iverilog directory.