From b695b17cc321f77412c5aab7c227728fd4714c8a Mon Sep 17 00:00:00 2001 From: huanghe Date: Mon, 5 Jul 2021 08:55:33 +0800 Subject: [PATCH 01/12] =?UTF-8?q?=E5=A2=9E=E5=8A=A0spin=20=E6=B5=8B?= =?UTF-8?q?=E8=AF=95?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../example/aarch32_cache_mmu_wr/sdkconfig | 14 +-- .../example/aarch32_cache_mmu_wr/sdkconfig.h | 1 - .../aarch32_cache_mmu_wr/sdkconfig.old | 4 +- .../example/aarch32_cache_mmu_wr/test_cache.c | 14 ++- .../example/aarch32_timer_irq/test_timer.c | 7 +- bsp/arch/armv8/aarch32/fsleep.c | 10 +- bsp/arch/armv8/aarch32/gcc/smccc-call.S | 36 +++++++ bsp/arch/armv8/aarch32/gcc/start.S | 1 + bsp/arch/armv8/aarch32/generic_timer.c | 34 +++--- bsp/arch/armv8/aarch32/generic_timer.h | 14 +-- bsp/arch/armv8/aarch32/platform/E2000/_cpu.c | 100 ++++++++++++++++++ bsp/arch/armv8/aarch32/platform/E2000/_cpu.h | 23 ++++ .../armv8/aarch32/platform/E2000/parameters.h | 5 + bsp/arch/armv8/aarch32/platform/ft2004/_cpu.c | 100 ++++++++++++++++++ bsp/arch/armv8/aarch32/platform/ft2004/_cpu.h | 18 ++++ .../aarch32/platform/ft2004/parameters.h | 5 + bsp/arch/armv8/aarch32/psci.c | 77 ++++++++++++++ bsp/arch/armv8/aarch32/psci.h | 31 ++++++ bsp/arch/armv8/aarch32/smc.h | 42 ++++++++ bsp/arch/armv8/aarch64/psci.c | 5 + bsp/arch/armv8/aarch64/psci.h | 10 ++ bsp/drivers/usart/pl011_uart/pl011_uart.h | 2 +- 22 files changed, 502 insertions(+), 51 deletions(-) create mode 100644 bsp/arch/armv8/aarch32/gcc/smccc-call.S create mode 100644 bsp/arch/armv8/aarch32/platform/E2000/_cpu.c create mode 100644 bsp/arch/armv8/aarch32/platform/E2000/_cpu.h create mode 100644 bsp/arch/armv8/aarch32/platform/ft2004/_cpu.c create mode 100644 bsp/arch/armv8/aarch32/platform/ft2004/_cpu.h create mode 100644 bsp/arch/armv8/aarch32/psci.c create mode 100644 bsp/arch/armv8/aarch32/psci.h create mode 100644 bsp/arch/armv8/aarch32/smc.h diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig index 5c92e7e23..8d7c0e995 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig @@ -11,7 +11,7 @@ CONFIG_TARGET_NAME="cache_test" # end of Project Configuration # -# Build Target +# Target Setting # CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set @@ -20,14 +20,10 @@ CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set CONFIG_TARGET_E2000=y -CONFIG_TARGET_BARE_METAL=y -# CONFIG_TARGET_FREE_RTOS is not set -# CONFIG_TARGET_RT_THREAD is not set -# CONFIG_TARGET_U_BOOT is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -43,12 +39,10 @@ CONFIG_COMPILER_NO_STD_STARUP=y # GNU linker # CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h index ea7cbaf4d..5ca6f570a 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h @@ -1,7 +1,6 @@ #define CONFIG_TARGET_NAME "cache_test" #define CONFIG_TARGET_ARMV8_AARCH32 1 #define CONFIG_TARGET_E2000 1 -#define CONFIG_TARGET_BARE_METAL 1 #define CONFIG_ENVI_UBUNTU_20_04 1 #define CONFIG_COMPILER_NO_STD_STARUP 1 #define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old index 2d41ff199..5c92e7e23 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old @@ -16,10 +16,10 @@ CONFIG_TARGET_NAME="cache_test" CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set # CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_F2000_4 is not set # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set +CONFIG_TARGET_E2000=y CONFIG_TARGET_BARE_METAL=y # CONFIG_TARGET_FREE_RTOS is not set # CONFIG_TARGET_RT_THREAD is not set diff --git a/baremetal/example/aarch32_cache_mmu_wr/test_cache.c b/baremetal/example/aarch32_cache_mmu_wr/test_cache.c index 7a339ee99..176ed31a3 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/test_cache.c +++ b/baremetal/example/aarch32_cache_mmu_wr/test_cache.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 10:36:06 - * @LastEditTime: 2021-06-29 15:26:04 + * @LastEditTime: 2021-07-05 08:27:31 * @Description:  This files is for * * @Modify History: @@ -18,9 +18,9 @@ #include "ft_debug.h" #define DATA_LENGTH 128 -#define MAGIC_NUM1 0xA0A00505 -#define MAGIC_NUM2 0xB0B00606 -#define MAGIC_NUM3 0xC0C00707 +#define MAGIC_NUM1 0xA0A00505 +#define MAGIC_NUM2 0xB0B00606 +#define MAGIC_NUM3 0xC0C00707 static u32 Data[DATA_LENGTH] __attribute__((aligned(64))); @@ -58,4 +58,10 @@ void CacheTest() DcacheOps(CACHE_INVALIDATE, (void *)Data, sizeof(Data)); FtDumpHexWord(Data, DATA_LENGTH); + + printf("start spin test \r\n "); + + SpinLock(); + + printf("spin is pass \r\n"); } \ No newline at end of file diff --git a/baremetal/example/aarch32_timer_irq/test_timer.c b/baremetal/example/aarch32_timer_irq/test_timer.c index e7050a8ff..49c3d73a0 100644 --- a/baremetal/example/aarch32_timer_irq/test_timer.c +++ b/baremetal/example/aarch32_timer_irq/test_timer.c @@ -35,12 +35,12 @@ u32 PlatformGetGicDistBase(void) void ArchTimerTest() { - Aarch32TimerCompare(tickRateHz); - Aarch32TimerStart(); + Aarch32TimerCompare(tickRateHz); + GenericTimerStart(); Aarch32TimerInterruptEnable(); printf("timer init done\r\n"); - + ArmGicRedistAddressSet(0, GICV3_RD_BASEADDRESS + 0, 0); InterruptInit(); InterruptSetPriority(irqID, irqPriority); @@ -50,6 +50,5 @@ void ArchTimerTest() while (1) { - } } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/fsleep.c b/bsp/arch/armv8/aarch32/fsleep.c index 00f53631e..89a8c5250 100644 --- a/bsp/arch/armv8/aarch32/fsleep.c +++ b/bsp/arch/armv8/aarch32/fsleep.c @@ -22,13 +22,13 @@ u32 fsleep_seconds(u32 seconds) { u64 end_time; u64 cur_time; - Aarch32TimerStart(); - cur_time = Aarch32TimerRead(); - end_time = cur_time + ((u64)seconds * Aarch32TimerFrequecy()); - printf("%d \r\n", Aarch32TimerFrequecy()); + GenericTimerStart(); + cur_time = GenericTimerRead(); + end_time = cur_time + ((u64)seconds * GenericTimerFrequecy()); + printf("%d \r\n", GenericTimerFrequecy()); do { - cur_time = Aarch32TimerRead(); + cur_time = GenericTimerRead(); } while (cur_time < end_time); return 0; diff --git a/bsp/arch/armv8/aarch32/gcc/smccc-call.S b/bsp/arch/armv8/aarch32/gcc/smccc-call.S new file mode 100644 index 000000000..c610350eb --- /dev/null +++ b/bsp/arch/armv8/aarch32/gcc/smccc-call.S @@ -0,0 +1,36 @@ + + +/******************************************************************************* +* +* FSmc_Call - initiate SMC call +* +* This routine initiates SMC call which traps the processor into Monitor Mode. +* The ARM SMC Call Convetion defines that up to eight registers can be exchanged +* during an SMC call. The input parameter contains eight INT32 valeus which are +* to be passed in the SMC call; similarily the output parameter also contains +* eight INT32 values which are returned from the SMC call. +* +* \NOMANUAL +* +* RETURNS: OK +* +* void FSmc_Call +* ( +* FSmc_Data_t * input, /@ r0 - input register values @/ +* FSmc_Data_t * output /@ r1 - output register values @/ +* ) +*/ + +.arm +.align 4 +.globl FSmc_Call +FSmc_Call: + STMDB sp!, {r0-r7} /* save clobbered registers to stack */ + ldr r12, [sp, #(4 * 0)] /* get 1st argument (ptr to input struct) */ + ldmia r12, {r0-r7} /* save input argument to r0-r7 */ + smc #0 + ldr r12, [sp, #(4 * 1)] /* get 2th argument (ptr to output result) */ + stmia r12, {r0-r7} /* get output argument from r0-r7 */ + ldmfd sp!, {r0-r7} /* restore clobbered registers from stack */ + bx lr +.size FSmc_Call, .- FSmc_Call diff --git a/bsp/arch/armv8/aarch32/gcc/start.S b/bsp/arch/armv8/aarch32/gcc/start.S index 6ea0ff376..afbb93f72 100644 --- a/bsp/arch/armv8/aarch32/gcc/start.S +++ b/bsp/arch/armv8/aarch32/gcc/start.S @@ -109,6 +109,7 @@ el2_mode: el1_mode: #endif +.balign 2048 .global Reset_Handler Reset_Handler: cpsid i /* Mask interrupts */ diff --git a/bsp/arch/armv8/aarch32/generic_timer.c b/bsp/arch/armv8/aarch32/generic_timer.c index a3a900bfb..8ef86ca79 100644 --- a/bsp/arch/armv8/aarch32/generic_timer.c +++ b/bsp/arch/armv8/aarch32/generic_timer.c @@ -24,15 +24,15 @@ #define A32GT_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) #define A32GT_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) #else -#define A32GT_ERROR(format, ...) -#define A32GT_DEBUG_I(format, ...) -#define A32GT_DEBUG_W(format, ...) +#define A32GT_ERROR(format, ...) +#define A32GT_DEBUG_I(format, ...) +#define A32GT_DEBUG_W(format, ...) #endif -#define AARCH32_CNTP_CTL_ENABLE_MASK (1ul << 0) -#define AARCH32_CNTP_CTL_INTERRUPT_MASK (1ul << 1) +#define AARCH32_CNTP_CTL_ENABLE_MASK (1ul << 0) +#define AARCH32_CNTP_CTL_INTERRUPT_MASK (1ul << 1) -void Aarch32TimerStart(void) +void GenericTimerStart(void) { u32 ctrl = aarch32_cntp_ctl_get(); @@ -45,7 +45,7 @@ void Aarch32TimerStart(void) A32GT_DEBUG_I("ctrl: 0x%x", aarch32_cntp_ctl_get()); } -void Aarch32TimerStop(void) +void GenericTimerStop(void) { u32 ctrl = aarch32_cntp_ctl_get(); if ((ctrl & AARCH32_CNTP_CTL_ENABLE_MASK)) @@ -55,7 +55,7 @@ void Aarch32TimerStop(void) } } -void Aarch32TimerInterruptEnable(void) +void GenericTimerInterruptEnable(void) { u32 ctrl = aarch32_cntp_ctl_get(); if (ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK) @@ -66,7 +66,7 @@ void Aarch32TimerInterruptEnable(void) A32GT_DEBUG_I("i mask: 0x%x", aarch32_cntp_ctl_get()); } -void Aarch32TimerInterruptDisable(void) +void GenericTimerInterruptDisable(void) { u64 ctrl = aarch32_cntp_ctl_get(); if (!(ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK)) @@ -76,40 +76,40 @@ void Aarch32TimerInterruptDisable(void) } } -u32 Aarch32TimerFrequecy(void) +u32 GenericTimerFrequecy(void) { u32 rate = aarch32_cntfrq_get(); return (rate != 0) ? rate : 1000000; } -u64 Aarch32TimerRead(void) +u64 GenericTimerRead(void) { return aarch32_cntpct_get(); } -void Aarch32TimerCompare(u32 interval) +void GenericTimerCompare(u32 interval) { aarch32_cntp_tval_set(interval); } void Aarch32Delay(u32 ms) { - u64 current = Aarch32TimerRead(); + u64 current = GenericTimerRead(); u64 condition = current + GENERIC_TIMER_CLK_FREQ_KHZ * ms; while (condition > current) { - current = Aarch32TimerRead(); + current = GenericTimerRead(); } } void Aarch32Udelay(u32 us) { - u64 current = Aarch32TimerRead(); + u64 current = GenericTimerRead(); u64 condition = current + GENERIC_TIMER_CLK_FREQ_MHZ * us; while (condition > current) { - current = Aarch32TimerRead(); - } + current = GenericTimerRead(); + } } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/generic_timer.h b/bsp/arch/armv8/aarch32/generic_timer.h index 4fa0f2f78..3143089fe 100644 --- a/bsp/arch/armv8/aarch32/generic_timer.h +++ b/bsp/arch/armv8/aarch32/generic_timer.h @@ -22,13 +22,13 @@ extern "C" #include "ft_types.h" - void Aarch32TimerStart(void); - void Aarch32TimerStop(void); - void Aarch32TimerInterruptEnable(void); - void Aarch32TimerInterruptDisable(void); - u32 Aarch32TimerFrequecy(void); - u64 Aarch32TimerRead(void); - void Aarch32TimerCompare(u32 interval); + void GenericTimerStart(void); + void GenericTimerStop(void); + void GenericTimerInterruptEnable(void); + void GenericTimerInterruptDisable(void); + u32 GenericTimerFrequecy(void); + u64 GenericTimerRead(void); + void GenericTimerCompare(u32 interval); void Aarch32Delay(u32 ms); void Aarch32Udelay(u32 us); diff --git a/bsp/arch/armv8/aarch32/platform/E2000/_cpu.c b/bsp/arch/armv8/aarch32/platform/E2000/_cpu.c new file mode 100644 index 000000000..f965890f0 --- /dev/null +++ b/bsp/arch/armv8/aarch32/platform/E2000/_cpu.c @@ -0,0 +1,100 @@ +#include "ft_types.h" +#include "_cpu.h" +#include "parameters.h" + +typedef union +{ + u64 slock; + struct ArchTicket + { + u32 owner; + u32 next; + } Tickets; +} FCpuLock; + +FCpuLock _lock = {0}; + +u32 GetCpuId(void) +{ + u32 affinity = 0; + + __asm__ volatile( + "mrc p15, 0, %0, c0, c0, 5" + : "=r"(affinity)); + + switch (affinity & 0xfff) + { + case CORE0_AFF: + return 0; + case CORE1_AFF: + return 1; + case CORE2_AFF: + return 2; + case CORE3_AFF: + return 3; + default: + return 0; + } + return 0; +} + +unsigned long GetCpuCluster(u32 cpu_id) +{ + switch (cpu_id) + { + case 0: + return CORE0_AFF; + case 1: + return CORE1_AFF; + case 2: + return CORE2_AFF; + case 3: + return CORE3_AFF; + default: + return 0; + } +} + +void SpinLockInit(void) +{ + _lock.slock = 0; +} + +void SpinLock(void) +{ + u64 tmp; + u64 new_val; + FCpuLock lock_val; + + __asm__ __volatile__( + "pld [%0]" ::"r"(&_lock.slock)); + + __asm__ __volatile__( + "1: ldrexd %0, [%3]\n" + " add %1, %0, %4\n" + " strexd %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r"(lock_val), "=&r"(new_val), "=&r"(tmp) + : "r"(&_lock.slock), "I"(1 << 16) + : "cc"); + + while (lock_val.Tickets.next != lock_val.Tickets.owner) + { + __asm__ __volatile__("wfe" :: + : "memory"); + lock_val.Tickets.owner = *(volatile unsigned short *)(&_lock.Tickets.owner); + } + + __asm__ volatile("dmb" :: + : "memory"); +} + +void SpinUnlock(void) +{ + __asm__ volatile("dmb" :: + : "memory"); + _lock.Tickets.owner++; + __asm__ volatile("dsb ishst\nsev" :: + : "memory"); +} diff --git a/bsp/arch/armv8/aarch32/platform/E2000/_cpu.h b/bsp/arch/armv8/aarch32/platform/E2000/_cpu.h new file mode 100644 index 000000000..cc5cfd302 --- /dev/null +++ b/bsp/arch/armv8/aarch32/platform/E2000/_cpu.h @@ -0,0 +1,23 @@ +#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H +#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + u32 GetAffinity(void); + u32 GetCpuId(void); + unsigned long GetCpuCluster(u32 cpu_id); + + void SpinLockInit(void); + void SpinLock(void); + void SpinUnlock(void); + +#ifdef __cplusplus +} +#endif + +#endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/E2000/parameters.h b/bsp/arch/armv8/aarch32/platform/E2000/parameters.h index c48c205d6..66103cf97 100644 --- a/bsp/arch/armv8/aarch32/platform/E2000/parameters.h +++ b/bsp/arch/armv8/aarch32/platform/E2000/parameters.h @@ -6,6 +6,11 @@ extern "C" { #endif +#define CORE0_AFF 0x0 +#define CORE1_AFF 0x100 +#define CORE2_AFF 0x200 +#define CORE3_AFF 0x201 + /* Device register address */ #define FT_DEV_BASE_ADDR 0x28000000 #define FT_DEV_END_ADDR 0x2FFFFFFF diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.c b/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.c new file mode 100644 index 000000000..c2b9590e6 --- /dev/null +++ b/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.c @@ -0,0 +1,100 @@ +#include "ft_types.h" +#include "_cpu.h" +#include "parameters.h" + +typedef union +{ + u32 slock; + struct ArchTicket + { + u16 owner; + u16 next; + } Tickets; +} FCpuLock; + +FCpuLock _lock = {0}; + +u32 GetCpuId(void) +{ + u32 affinity = 0; + + __asm__ volatile( + "mrc p15, 0, %0, c0, c0, 5" + : "=r"(affinity)); + + switch (affinity & 0xfff) + { + case CORE0_AFF: + return 0; + case CORE1_AFF: + return 1; + case CORE2_AFF: + return 2; + case CORE3_AFF: + return 3; + default: + return 0; + } + return 0; +} + +unsigned long GetCpuCluster(u32 cpu_id) +{ + switch (cpu_id) + { + case 0: + return CORE0_AFF; + case 1: + return CORE1_AFF; + case 2: + return CORE2_AFF; + case 3: + return CORE3_AFF; + default: + return 0; + } +} + +void SpinLockInit(void) +{ + _lock.slock = 0; +} + +void SpinLock(void) +{ + u32 tmp; + u32 new_val; + FCpuLock lock_val; + + __asm__ __volatile__( + "pld [%0]" ::"r"(&_lock.slock)); + + __asm__ __volatile__( + "1: ldrex %0, [%3]\n" + " add %1, %0, %4\n" + " strex %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r"(lock_val), "=&r"(new_val), "=&r"(tmp) + : "r"(&_lock.slock), "I"(1 << 16) + : "cc"); + + while (lock_val.Tickets.next != lock_val.Tickets.owner) + { + __asm__ __volatile__("wfe" :: + : "memory"); + lock_val.Tickets.owner = *(volatile unsigned short *)(&_lock.Tickets.owner); + } + + __asm__ volatile("dmb" :: + : "memory"); +} + +void SpinUnlock(void) +{ + __asm__ volatile("dmb" :: + : "memory"); + _lock.Tickets.owner++; + __asm__ volatile("dsb ishst\nsev" :: + : "memory"); +} diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.h b/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.h new file mode 100644 index 000000000..1a3c03a8e --- /dev/null +++ b/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.h @@ -0,0 +1,18 @@ +#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H +#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + u32 GetAffinity(void); + u32 GetCpuId(void); + unsigned long GetCpuCluster(u32 cpu_id); +#ifdef __cplusplus +} +#endif + +#endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h b/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h index 854ba4fce..3cfc80294 100644 --- a/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h +++ b/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h @@ -17,6 +17,11 @@ #include "ft_types.h" +#define CORE0_AFF 0x0 +#define CORE1_AFF 0x1 +#define CORE2_AFF 0x100 +#define CORE3_AFF 0x101 + /* Device register address */ #define FT_DEV_BASE_ADDR 0x28000000 #define FT_DEV_END_ADDR 0x2FFFFFFF diff --git a/bsp/arch/armv8/aarch32/psci.c b/bsp/arch/armv8/aarch32/psci.c new file mode 100644 index 000000000..20974d514 --- /dev/null +++ b/bsp/arch/armv8/aarch32/psci.c @@ -0,0 +1,77 @@ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-21 10:43:52 + * @LastEditTime: 2021-07-02 15:51:01 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include "psci.h" +#include "smc.h" +#include "parameters.h" + +#define PSCI_CPUON_NUM 0x84000003 +#define PSCI_RESET_NUM 0x84000009 +const u32 SoftAffiTable[4] = {CORE0_AFF, CORE1_AFF, CORE2_AFF, CORE3_AFF}; +/** + * @name: FPsci_CpuOn + * @msg: Power up a core + * @in param CpuList: Bits[24:31]: Must be zero. + * Bits[16:23] Aff2: Match Aff2 of target core MPIDR + * Bits[8:15] Aff1: Match Aff1 of target core MPIDR + * Bits[0:7] Aff0: Match Aff0 of target core MPIDR + * @in param BootAddr: a 32-bit entry point physical address (or IPA). + * @return {None} + */ +void PsciCpuOn(s32 CpuIdMask, u32 BootAddr) +{ + + FSmc_Data_t Input = {0}; + FSmc_Data_t Output = {0}; + Input.FunctionIdentifier = PSCI_CPUON_NUM; + + if ((1 << 0) == CpuIdMask) + { + Input.a1 = SoftAffiTable[0]; + } + else if ((1 << 1) == CpuIdMask) + { + Input.a1 = SoftAffiTable[1]; + } + else if ((1 << 2) == CpuIdMask) + { + Input.a1 = SoftAffiTable[2]; + } + else if ((1 << 3) == CpuIdMask) + { + Input.a1 = SoftAffiTable[3]; + } + else + { + return; + } + + /*input.a2 = (u32)(BootAddr >> 32);*/ + Input.a2 = (u32)(BootAddr & 0xFFFFFFFF); + FSmc_Call(&Input, &Output); + __asm__ volatile("NOP"); +} + +void PsciCpuReset(void) +{ + + FSmc_Data_t Input = {0}; + FSmc_Data_t Output = {0}; + + Input.FunctionIdentifier = PSCI_RESET_NUM; + FSmc_Call(&Input, &Output); + + __asm__ volatile("NOP"); + while (1) + ; +} diff --git a/bsp/arch/armv8/aarch32/psci.h b/bsp/arch/armv8/aarch32/psci.h new file mode 100644 index 000000000..798fef1dc --- /dev/null +++ b/bsp/arch/armv8/aarch32/psci.h @@ -0,0 +1,31 @@ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-21 10:43:59 + * @LastEditTime: 2021-07-01 18:42:35 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_PSCI_H +#define BSP_ARCH_ARMV8_AARCH32_PSCI_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + void PsciCpuOn(s32 CpuIdMask, u32 BootAddr); + void PsciCpuReset(void); + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/arch/armv8/aarch32/smc.h b/bsp/arch/armv8/aarch32/smc.h new file mode 100644 index 000000000..334d1e7ca --- /dev/null +++ b/bsp/arch/armv8/aarch32/smc.h @@ -0,0 +1,42 @@ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-21 11:53:38 + * @LastEditTime: 2021-07-01 18:43:29 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_SMC_H +#define BSP_ARCH_ARMV8_AARCH32_SMC_H + +#ifdef __cplusplus +extern "C" +{ +#endif +#include "ft_types.h" + + typedef struct + { + /* data */ + u32 FunctionIdentifier; + u32 a1; + u32 a2; + u32 a3; + u32 a4; + u32 a5; + u32 a6; + + } FSmc_Data_t; + + void FSmc_Call(FSmc_Data_t *Input, FSmc_Data_t *Output); + +#ifdef __cplusplus +} +#endif + +#endif // !FT_SMC_H diff --git a/bsp/arch/armv8/aarch64/psci.c b/bsp/arch/armv8/aarch64/psci.c index 8bede3aa9..082396f4b 100644 --- a/bsp/arch/armv8/aarch64/psci.c +++ b/bsp/arch/armv8/aarch64/psci.c @@ -22,4 +22,9 @@ void PsciCpuOn(s32 cpu_id_mask, void *entry) struct arm_smccc_res res; cluster = GetCpuCluster(cpu_id_mask); arm_smccc_smc(0xc4000003, cluster, (u64)entry, 0, 0, 0, 0, 0, &res); +} +void PsciCpuReset(void) +{ + struct arm_smccc_res res; + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/psci.h b/bsp/arch/armv8/aarch64/psci.h index 3ea187ac5..c326abf61 100644 --- a/bsp/arch/armv8/aarch64/psci.h +++ b/bsp/arch/armv8/aarch64/psci.h @@ -14,7 +14,17 @@ #ifndef BSP_ARCH_AARMV8_AARCH64_PSCI_H #define BSP_ARCH_AARMV8_AARCH64_PSCI_H +#ifdef __cplusplus +extern "C" +{ +#endif +#include "ft_types.h" + void PsciCpuOn(s32 cpu_id_mask, void *entry); + void PsciCpuReset(void); +#ifdef __cplusplus +} +#endif #endif // !BSP_ARCH_AARMV8_AARCH64_PSCI_H \ No newline at end of file diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart.h b/bsp/drivers/usart/pl011_uart/pl011_uart.h index b4bd7fad7..a9f6a091f 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart.h +++ b/bsp/drivers/usart/pl011_uart/pl011_uart.h @@ -4,7 +4,7 @@  * SPDX-License-Identifier: Apache-2.0.  * * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-06-28 09:56:39 + * @LastEditTime: 2021-07-02 16:56:15 * @Description:  This files is for uart functions * * @Modify History: -- Gitee From caffbaf30b7225b23dd6cb112e0bf82cf4773664 Mon Sep 17 00:00:00 2001 From: huanghe Date: Wed, 7 Jul 2021 21:03:36 +0800 Subject: [PATCH 02/12] =?UTF-8?q?=E5=AE=8C=E6=88=90=20rtt=2064=20=E4=B8=8E?= =?UTF-8?q?32bit=20=E7=9A=84=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/common/ft_debug.c | 10 +++++----- bsp/drivers/usart/pl011_uart/pl011_uart_intr.c | 4 +--- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/bsp/common/ft_debug.c b/bsp/common/ft_debug.c index 5c085cb7c..fcd743e44 100644 --- a/bsp/common/ft_debug.c +++ b/bsp/common/ft_debug.c @@ -4,7 +4,7 @@  * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-04-25 16:44:23 - * @LastEditTime: 2021-06-25 14:59:49 + * @LastEditTime: 2021-07-07 17:49:33 * @Description:  Description of file * @Modify History: * * * Ver   Who        Date         Changes @@ -16,11 +16,11 @@ void FtDumpHexByte(const u8 *ptr, u32 buflen) { unsigned char *buf = (unsigned char *)ptr; - u32 i, j; + fsize_t i, j; for (i = 0; i < buflen; i += 16) { - printf("0x%08X: ", ptr + i); + printf("0x%lX: ", (fsize_t)ptr + i); for (j = 0; j < 16; j++) if (i + j < buflen) @@ -39,11 +39,11 @@ void FtDumpHexByte(const u8 *ptr, u32 buflen) void FtDumpHexWord(const u32 *ptr, u32 buflen) { u32 *buf = (u32 *)ptr; - u32 i, j; + fsize_t i, j; buflen = buflen / 4; for (i = 0; i < buflen; i += 4) { - printf("0x%08X: ", ptr + i); + printf("0x%lX: ", (fsize_t)ptr + i); for (j = 0; j < 4; j++) { diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c b/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c index d780c01e5..68ae6a3bc 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c @@ -4,7 +4,7 @@  * SPDX-License-Identifier: Apache-2.0.  * * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-07-01 18:03:22 + * @LastEditTime: 2021-07-07 17:55:12 * @Description:  This files is for uart irq functions * * @Modify History: @@ -185,8 +185,6 @@ static void Pl011ReceiveTimeoutHandler(Pl011 *uart_p) static void Pl011SendDataHandler(Pl011 *uart_p, u32 InterruptStatus) { - u32 RegValue; - if (uart_p->send_buffer.remaining_bytes == (u32)0) { if (uart_p->handler) -- Gitee From fe53bbe507158b8d6eac87c6422096bbb220a337 Mon Sep 17 00:00:00 2001 From: huanghe Date: Thu, 8 Jul 2021 10:01:11 +0800 Subject: [PATCH 03/12] =?UTF-8?q?=E5=AE=8C=E6=88=90rtt=20=E9=A1=B9?= =?UTF-8?q?=E7=9B=AE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/drivers/gic/gicv3_arrch32/gicv3.c | 40 ++-- bsp/drivers/gic/gicv3_arrch32/gicv3.h | 280 +++++++++++++------------- lib/nostdlib/nostdlib.c | 4 +- lib/nostdlib/printf-stdarg.c | 2 +- 4 files changed, 163 insertions(+), 163 deletions(-) diff --git a/bsp/drivers/gic/gicv3_arrch32/gicv3.c b/bsp/drivers/gic/gicv3_arrch32/gicv3.c index e8ee31e44..6c41e4560 100644 --- a/bsp/drivers/gic/gicv3_arrch32/gicv3.c +++ b/bsp/drivers/gic/gicv3_arrch32/gicv3.c @@ -317,8 +317,8 @@ void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value) value &= 0xFFUL; /* enable irq and fiq */ __set_gicv3_reg(ICC_SRE, value); - __asm__ volatile ("isb 0xF":: - :"memory"); + __asm__ volatile("isb 0xF" :: + : "memory"); } u32 ArmGicGetSystemRegisterEnableMask(u32 index) @@ -390,10 +390,10 @@ void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode) sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". /* Write the ICC_SGI1R registers */ __asm__ volatile("dsb 0xF" :: - : "memory"); + : "memory"); __set_cp64(15, 0, sgi_val, 12); __asm__ volatile("isb 0xF" :: - : "memory"); + : "memory"); } else { @@ -407,10 +407,10 @@ void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode) ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); __asm__ volatile("dsb 0xF" :: - : "memory"); + : "memory"); __set_cp64(15, 0, sgi_val, 12); __asm__ volatile("isb 0xF" :: - : "memory"); + : "memory"); } } } @@ -500,7 +500,7 @@ int ArmGicDistInit(u32 index, u32 dist_base, int irq_start) _gic_table[index].dist_hw_base = dist_base; _gic_table[index].offset = irq_start; - // printf("index: %d, offset: 0x%x, redist_hw_base: 0x%x, dist_hw_base: 0x%x, cpu_hw_base: 0x%x\r\n", + // printf("index: %d, offset: 0x%x, redist_hw_base: 0x%x, dist_hw_base: 0x%x, cpu_hw_base: 0x%x\r\n", // index, // _gic_table[index].offset, // _gic_table[index].redist_hw_base[0], @@ -642,7 +642,7 @@ int ArmGicCpuInit(u32 index) value = ArmGicGetSystemRegisterEnableMask(index); value |= (1U << 0); ArmGicSetSystemRegisterEnableMask(index, value); - + __set_gicv3_reg(ICC_CTLR, 0); ArmGicSetInterfacePriorMask(index, 0xFFU); @@ -685,11 +685,11 @@ void ArmGicDumpType(u32 index) gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); printf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\r\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1U << 10U) ? "has" : "no", - gic_type); + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); } void ArmGicDump(u32 index) @@ -702,24 +702,24 @@ void ArmGicDump(u32 index) for (i = 0U; i < _gic_max_irq / 32U; i++) { printf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32U)); + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); } printf("\r\n--- hw pending ---\r\n"); for (i = 0U; i < _gic_max_irq / 32U; i++) { printf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32U)); + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); } - + printf("\r\n--- hw active ---\r\n"); for (i = 0U; i < _gic_max_irq / 32U; i++) { printf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32U)); + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); } printf("\r\n"); diff --git a/bsp/drivers/gic/gicv3_arrch32/gicv3.h b/bsp/drivers/gic/gicv3_arrch32/gicv3.h index 6e238c972..4ff30efca 100644 --- a/bsp/drivers/gic/gicv3_arrch32/gicv3.h +++ b/bsp/drivers/gic/gicv3_arrch32/gicv3.h @@ -34,175 +34,175 @@ extern "C" /* AArch32 System register interface to GICv3 */ /* Group 0, reads this register to obtain the INTID, acts as an acknowledge for the interrupt */ -#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" +#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" /* Group 1 */ -#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" +#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" /* writes to this register to inform the CPU interface that it has completed the processing */ -#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" -#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" +#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" +#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" /* GET the INTID of highest priority pending interrupt */ -#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2" -#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2" -#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" -#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" -#define ICC_DIR "p15, 0, %0, c12, c11, 1" -#define ICC_PMR "p15, 0, %0, c4, c6, 0" -#define ICC_RPR "p15, 0, %0, c12, c11, 3" -#define ICC_CTLR "p15, 0, %0, c12, c12, 4" -#define ICC_MCTLR "p15, 6, %0, c12, c12, 4" -#define ICC_SRE "p15, 0, %0, c12, c12, 5" -#define ICC_HSRE "p15, 4, %0, c12, c9, 5" -#define ICC_MSRE "p15, 6, %0, c12, c12, 5" +#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2" +#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2" +#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" +#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" +#define ICC_DIR "p15, 0, %0, c12, c11, 1" +#define ICC_PMR "p15, 0, %0, c4, c6, 0" +#define ICC_RPR "p15, 0, %0, c12, c11, 3" +#define ICC_CTLR "p15, 0, %0, c12, c12, 4" +#define ICC_MCTLR "p15, 6, %0, c12, c12, 4" +#define ICC_SRE "p15, 0, %0, c12, c12, 5" +#define ICC_HSRE "p15, 4, %0, c12, c9, 5" +#define ICC_MSRE "p15, 6, %0, c12, c12, 5" #define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" #define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" #define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7" -#define __REG32(x) (*((volatile unsigned int*)((u32)x))) +#define __REG32(x) (*((volatile unsigned int *)((u32)x))) #define ROUTED_TO_ALL (1) #define ROUTED_TO_SPEC (0) /** Macro to access the Distributor Control Register (GICD_CTLR) */ -#define GICD_CTLR_RWP (1<<31) -#define GICD_CTLR_E1NWF (1<<7) -#define GICD_CTLR_DS (1<<6) -#define GICD_CTLR_ARE_NS (1<<5) -#define GICD_CTLR_ARE_S (1<<4) -#define GICD_CTLR_ENGRP1S (1<<2) -#define GICD_CTLR_ENGRP1NS (1<<1) -#define GICD_CTLR_ENGRP0 (1<<0) +#define GICD_CTLR_RWP (1 << 31) +#define GICD_CTLR_E1NWF (1 << 7) +#define GICD_CTLR_DS (1 << 6) +#define GICD_CTLR_ARE_NS (1 << 5) +#define GICD_CTLR_ARE_S (1 << 4) +#define GICD_CTLR_ENGRP1S (1 << 2) +#define GICD_CTLR_ENGRP1NS (1 << 1) +#define GICD_CTLR_ENGRP0 (1 << 0) /** Macro to access the Redistributor Control Register (GICR_CTLR) */ -#define GICR_CTLR_UWP (1<<31) -#define GICR_CTLR_DPG1S (1<<26) -#define GICR_CTLR_DPG1NS (1<<25) -#define GICR_CTLR_DPG0 (1<<24) -#define GICR_CTLR_RWP (1<<3) -#define GICR_CTLR_IR (1<<2) -#define GICR_CTLR_CES (1<<1) -#define GICR_CTLR_EnableLPI (1<<0) +#define GICR_CTLR_UWP (1 << 31) +#define GICR_CTLR_DPG1S (1 << 26) +#define GICR_CTLR_DPG1NS (1 << 25) +#define GICR_CTLR_DPG0 (1 << 24) +#define GICR_CTLR_RWP (1 << 3) +#define GICR_CTLR_IR (1 << 2) +#define GICR_CTLR_CES (1 << 1) +#define GICR_CTLR_EnableLPI (1 << 0) /** Macro to access the Generic Interrupt Controller Interface (GICC) */ -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) -#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) /** Macro to access the Generic Interrupt Controller Distributor (GICD) */ -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) -#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) -#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) -#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n) / 32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n) / 4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n) / 4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) +#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) +#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) /* SGI base address is at 64K offset from Redistributor base address */ #define GIC_RSGI_OFFSET 0x10000 /** Macro to access the Generic Interrupt Controller Redistributor (GICD) */ -#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) -#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) -#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) -#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) -#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) -#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) -#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) -#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) -#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) -#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) - -#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) -#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) -#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) -#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) -#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) -#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) -#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) -#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) -#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) -#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) -#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) -#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) - -#define GIC_RSGI_AFF1_OFFSET 16 -#define GIC_RSGI_AFF2_OFFSET 32 -#define GIC_RSGI_AFF3_OFFSET 48 - -u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list); -u64 GetMainCpuAffval(void); -int ArmGicGetActiveIrq(u32 index); -void ArmGicAck(u32 index, int irq); - -void ArmGicMask(u32 index, int irq); -void ArmGicUmask(u32 index, int irq); - -u32 ArmGicGetPendingIrq(u32 index, int irq); -void ArmGicSetPendingIrq(u32 index, int irq); -void ArmGicClearPendingIrq(u32 index, int irq); - -void ArmGicSetConfiguration(u32 index, int irq, uint32_t config); -u32 ArmGicGetConfiguration(u32 index, int irq); - -void ArmGicClearActive(u32 index, int irq); - -void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask); -u32 ArmGicGetTargetCpu(u32 index, int irq); - -void ArmGicSetPriority(u32 index, int irq, u32 priority); -u32 ArmGicGetPriority(u32 index, int irq); - -void ArmGicSetInterfacePriorMask(u32 index, u32 priority); -u32 ArmGicGetInterfacePriorMask(u32 index); - -void ArmGicSetBinaryPoint(u32 index, u32 binary_point); -u32 ArmGicGetBinaryPoint(u32 index); - -u32 ArmGicGetIrqStatus(u32 index, int irq); - -void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode); -u32 ArmGicGetHighPendingIrq(u32 index); - -u32 ArmGicGetInterfaceId(u32 index); - -void ArmGicSetGroup(u32 index, int irq, u32 group); -u32 ArmGicGetGroup(u32 index, int irq); - -int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id); -int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id); -int ArmGicDistInit(u32 index, u32 dist_base, int irq_start); -int ArmGicCpuInit(u32 index); -int ArmGicRedistInit(u32 index); - -void ArmGicDumpType(u32 index); -void ArmGicDump(u32 index); - -void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value); -u32 ArmGicGetSystemRegisterEnableMask(u32 index); -void ArmGicSecondaryCpuInit(void); +#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) +#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) +#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) +#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) +#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) +#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) +#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) +#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) +#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) +#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) + +#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) +#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) +#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) +#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) +#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) +#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) +#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) +#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) +#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) +#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) +#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) +#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) + +#define GIC_RSGI_AFF1_OFFSET 16 +#define GIC_RSGI_AFF2_OFFSET 32 +#define GIC_RSGI_AFF3_OFFSET 48 + + u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list); + u64 GetMainCpuAffval(void); + int ArmGicGetActiveIrq(u32 index); + void ArmGicAck(u32 index, int irq); + + void ArmGicMask(u32 index, int irq); + void ArmGicUmask(u32 index, int irq); + + u32 ArmGicGetPendingIrq(u32 index, int irq); + void ArmGicSetPendingIrq(u32 index, int irq); + void ArmGicClearPendingIrq(u32 index, int irq); + + void ArmGicSetConfiguration(u32 index, int irq, uint32_t config); + u32 ArmGicGetConfiguration(u32 index, int irq); + + void ArmGicClearActive(u32 index, int irq); + + void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask); + u32 ArmGicGetTargetCpu(u32 index, int irq); + + void ArmGicSetPriority(u32 index, int irq, u32 priority); + u32 ArmGicGetPriority(u32 index, int irq); + + void ArmGicSetInterfacePriorMask(u32 index, u32 priority); + u32 ArmGicGetInterfacePriorMask(u32 index); + + void ArmGicSetBinaryPoint(u32 index, u32 binary_point); + u32 ArmGicGetBinaryPoint(u32 index); + + u32 ArmGicGetIrqStatus(u32 index, int irq); + + void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode); + u32 ArmGicGetHighPendingIrq(u32 index); + + u32 ArmGicGetInterfaceId(u32 index); + + void ArmGicSetGroup(u32 index, int irq, u32 group); + u32 ArmGicGetGroup(u32 index, int irq); + + int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id); + int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id); + int ArmGicDistInit(u32 index, u32 dist_base, int irq_start); + int ArmGicCpuInit(u32 index); + int ArmGicRedistInit(u32 index); + + void ArmGicDumpType(u32 index); + void ArmGicDump(u32 index); + + void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value); + u32 ArmGicGetSystemRegisterEnableMask(u32 index); + void ArmGicSecondaryCpuInit(void); /* for Gic trace */ #include "ft_debug.h" diff --git a/lib/nostdlib/nostdlib.c b/lib/nostdlib/nostdlib.c index 0ac68c3a4..14c115ea5 100644 --- a/lib/nostdlib/nostdlib.c +++ b/lib/nostdlib/nostdlib.c @@ -211,10 +211,10 @@ char *strcpy(char *destination, const char *source) } /****************************************************************/ -int strlen(const char *str) +long unsigned int strlen(const char *str) { char *s = (char *)str; - int len = 0; + long unsigned int len = 0; if (s == NULL) return 0; diff --git a/lib/nostdlib/printf-stdarg.c b/lib/nostdlib/printf-stdarg.c index 27687f814..9d869f9f1 100644 --- a/lib/nostdlib/printf-stdarg.c +++ b/lib/nostdlib/printf-stdarg.c @@ -235,7 +235,7 @@ int sprintf(char *out, const char *format, ...) return print(&out, format, args); } -int snprintf(char *buf, unsigned int count, const char *format, ...) +int snprintf(char *buf, long unsigned int count, const char *format, ...) { va_list args; -- Gitee From d7551d5b60b2b328169ccb7f0df8db1f2c0dedb7 Mon Sep 17 00:00:00 2001 From: huanghe Date: Thu, 8 Jul 2021 10:44:50 +0800 Subject: [PATCH 04/12] =?UTF-8?q?=E4=BF=AE=E6=94=B9aarch32=20=E5=90=AF?= =?UTF-8?q?=E5=8A=A8=E4=B8=8D=E6=AD=A3=E5=B8=B8=E5=8A=9F=E8=83=BD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../example/aarch32_cache_mmu_wr/Makefile | 2 +- .../example/aarch32_cache_mmu_wr/sdkconfig | 4 ++-- .../example/aarch32_cache_mmu_wr/sdkconfig.h | 2 +- .../aarch32_cache_mmu_wr/sdkconfig.old | 14 ++++------- baremetal/example/aarch32_timer_irq/Makefile | 2 +- baremetal/example/aarch32_timer_irq/main.c | 4 ++-- baremetal/example/aarch32_timer_irq/sdkconfig | 10 ++++---- .../example/aarch32_timer_irq/sdkconfig.old | 4 ---- .../example/aarch32_timer_irq/test_timer.c | 6 ++--- .../example/aarch64_uart_irq_send/sdkconfig | 8 +++---- .../aarch64_uart_irq_send/sdkconfig.old | 23 +++++++------------ bsp/arch/armv8/aarch32/gcc/start.S | 3 ++- 12 files changed, 32 insertions(+), 50 deletions(-) diff --git a/baremetal/example/aarch32_cache_mmu_wr/Makefile b/baremetal/example/aarch32_cache_mmu_wr/Makefile index 11e445886..192319805 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/Makefile +++ b/baremetal/example/aarch32_cache_mmu_wr/Makefile @@ -10,4 +10,4 @@ rebuild: boot: make - @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ \ No newline at end of file + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ \ No newline at end of file diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig index 8d7c0e995..6cffbf020 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig @@ -16,10 +16,10 @@ CONFIG_TARGET_NAME="cache_test" CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set # CONFIG_TARGET_ARMV7 is not set -# CONFIG_TARGET_F2000_4 is not set +CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set -CONFIG_TARGET_E2000=y +# CONFIG_TARGET_E2000 is not set # end of Target Setting # diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h index 5ca6f570a..8e1b3c132 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h @@ -1,6 +1,6 @@ #define CONFIG_TARGET_NAME "cache_test" #define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_E2000 1 +#define CONFIG_TARGET_F2000_4 1 #define CONFIG_ENVI_UBUNTU_20_04 1 #define CONFIG_COMPILER_NO_STD_STARUP 1 #define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old index 5c92e7e23..8d7c0e995 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old @@ -11,7 +11,7 @@ CONFIG_TARGET_NAME="cache_test" # end of Project Configuration # -# Build Target +# Target Setting # CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set @@ -20,14 +20,10 @@ CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set CONFIG_TARGET_E2000=y -CONFIG_TARGET_BARE_METAL=y -# CONFIG_TARGET_FREE_RTOS is not set -# CONFIG_TARGET_RT_THREAD is not set -# CONFIG_TARGET_U_BOOT is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -43,12 +39,10 @@ CONFIG_COMPILER_NO_STD_STARUP=y # GNU linker # CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration diff --git a/baremetal/example/aarch32_timer_irq/Makefile b/baremetal/example/aarch32_timer_irq/Makefile index df9921cb3..1e9def789 100644 --- a/baremetal/example/aarch32_timer_irq/Makefile +++ b/baremetal/example/aarch32_timer_irq/Makefile @@ -9,4 +9,4 @@ rebuild: boot: make - @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ \ No newline at end of file + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ \ No newline at end of file diff --git a/baremetal/example/aarch32_timer_irq/main.c b/baremetal/example/aarch32_timer_irq/main.c index a3568d8b6..c18c49214 100644 --- a/baremetal/example/aarch32_timer_irq/main.c +++ b/baremetal/example/aarch32_timer_irq/main.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-07-01 16:49:09 - * @LastEditTime: 2021-07-02 09:42:27 + * @LastEditTime: 2021-07-08 10:42:19 * @Description:  This files is for * * @Modify History: @@ -25,6 +25,6 @@ int main() Aarch32Delay(1000); //wait for 1 second printf("loop tick\r\n"); } - + return 0; } \ No newline at end of file diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig b/baremetal/example/aarch32_timer_irq/sdkconfig index 5908f83fd..114ad191b 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig +++ b/baremetal/example/aarch32_timer_irq/sdkconfig @@ -11,7 +11,7 @@ CONFIG_TARGET_NAME="ft2004_baremetal" # end of Project Configuration # -# Build Target +# Target Setting # CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set @@ -20,10 +20,10 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -39,12 +39,10 @@ CONFIG_COMPILER_NO_STD_STARUP=y # GNU linker # CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig.old b/baremetal/example/aarch32_timer_irq/sdkconfig.old index acaf77a26..5908f83fd 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig.old +++ b/baremetal/example/aarch32_timer_irq/sdkconfig.old @@ -20,10 +20,6 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -CONFIG_TARGET_BARE_METAL=y -# CONFIG_TARGET_FREE_RTOS is not set -# CONFIG_TARGET_RT_THREAD is not set -# CONFIG_TARGET_U_BOOT is not set # end of Build Target # diff --git a/baremetal/example/aarch32_timer_irq/test_timer.c b/baremetal/example/aarch32_timer_irq/test_timer.c index 49c3d73a0..5d282abfb 100644 --- a/baremetal/example/aarch32_timer_irq/test_timer.c +++ b/baremetal/example/aarch32_timer_irq/test_timer.c @@ -25,7 +25,7 @@ const u32 irqID = 30; void TickHandler(s32 vector, void *param) { printf("irq ticked\r\n"); - Aarch32TimerCompare(tickRateHz); + GenericTimerCompare(tickRateHz); } u32 PlatformGetGicDistBase(void) @@ -35,9 +35,9 @@ u32 PlatformGetGicDistBase(void) void ArchTimerTest() { - Aarch32TimerCompare(tickRateHz); + GenericTimerCompare(tickRateHz); GenericTimerStart(); - Aarch32TimerInterruptEnable(); + GenericTimerInterruptEnable(); printf("timer init done\r\n"); diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig b/baremetal/example/aarch64_uart_irq_send/sdkconfig index 6adf3b568..838a710ba 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig @@ -1,6 +1,6 @@ # -# Build Target +# Target Setting # # CONFIG_TARGET_ARMV8_AARCH32 is not set CONFIG_TARGET_ARMV8_AARCH64=y @@ -9,10 +9,10 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -31,7 +31,7 @@ CONFIG_COMPILER_NO_STD_STARUP=y CONFIG_E2000_FT20004_AARCH64_RAM_LD=y # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig.old b/baremetal/example/aarch64_uart_irq_send/sdkconfig.old index b2055c658..55b0be668 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig.old +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig.old @@ -1,6 +1,6 @@ # -# Build Target +# Target Setting # # CONFIG_TARGET_ARMV8_AARCH32 is not set CONFIG_TARGET_ARMV8_AARCH64=y @@ -9,14 +9,10 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -CONFIG_TARGET_BARE_METAL=y -# CONFIG_TARGET_FREE_RTOS is not set -# CONFIG_TARGET_RT_THREAD is not set -# CONFIG_TARGET_U_BOOT is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -24,21 +20,18 @@ CONFIG_ENVI_UBUNTU_20_04=y # # Cross-Compiler Setting # -# CONFIG_COMPILER_NO_STD_STARUP is not set -CONFIG_USE_EXT_COMPILER=y -CONFIG_EXT_COMPILER_PREFIX="/home/carl/aarch64/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf" +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set # end of Cross-Compiler Setting # # GNU linker # # CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set CONFIG_E2000_FT20004_AARCH64_RAM_LD=y -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration @@ -88,8 +81,8 @@ CONFIG_USE_MMU=y # # Library Configuration # -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y # end of Library Configuration # diff --git a/bsp/arch/armv8/aarch32/gcc/start.S b/bsp/arch/armv8/aarch32/gcc/start.S index afbb93f72..8a77c6bf4 100644 --- a/bsp/arch/armv8/aarch32/gcc/start.S +++ b/bsp/arch/armv8/aarch32/gcc/start.S @@ -113,7 +113,8 @@ el1_mode: .global Reset_Handler Reset_Handler: cpsid i /* Mask interrupts */ - + ldr r0,=#0 + mrc p15, 0, r0, c1, c0, 0 /* set VBAR to the system_vectors address in linker script */ ldr r0, =system_vectors mcr p15, 0, r0, c12, c0, 0 -- Gitee From 62b55ae2a2aa5b91bdaa20048295a0d9bb8474ec Mon Sep 17 00:00:00 2001 From: huanghe Date: Fri, 9 Jul 2021 19:33:34 +0800 Subject: [PATCH 05/12] =?UTF-8?q?=E5=AD=98=E5=9C=A8libc=20=E4=BE=9D?= =?UTF-8?q?=E8=B5=96=E6=9F=90=E4=B8=AA=E7=89=B9=E5=AE=9A=E7=BC=96=E8=AF=91?= =?UTF-8?q?=E9=93=BE=E7=9A=84=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .vscode/settings.json | 3 +- .../example/aarch32_cache_mmu_wr/sdkconfig | 10 +- .../example/aarch32_cache_mmu_wr/sdkconfig.h | 2 + .../aarch32_cache_mmu_wr/sdkconfig.old | 18 +- .../example/aarch32_hello_world/Makefile | 2 +- .../ft2004_baremetal.map_o | 2174 +++++++++++++++++ baremetal/example/aarch32_hello_world/main.c | 10 +- .../example/aarch32_hello_world/sdkconfig | 16 +- .../example/aarch32_hello_world/sdkconfig.h | 5 +- .../example/aarch32_hello_world/sdkconfig.old | 21 +- baremetal/example/aarch32_uart_irq/sdkconfig | 18 +- .../example/aarch32_uart_irq/sdkconfig.h | 5 +- .../example/aarch32_uart_irq/sdkconfig.old | 4 - .../example/aarch64_uart_irq_send/sdkconfig | 4 +- .../example/aarch64_uart_irq_send/sdkconfig.h | 2 +- .../aarch64_uart_irq_send/sdkconfig.old | 4 +- bsp/arch/armv8/aarch32/aarch32.h | 11 + bsp/arch/armv8/aarch32/fsleep.c | 4 +- bsp/arch/armv8/aarch32/gcc/cp15.S | 3 +- bsp/arch/armv8/aarch32/gcc/exception_debug.c | 108 + bsp/arch/armv8/aarch32/gcc/start.S | 140 +- bsp/arch/armv8/aarch32/gcc/vector.S | 79 +- bsp/arch/armv8/aarch32/mmu.c | 77 +- .../aarch32/platform/ft2004/parameters.c | 4 +- bsp/common/trap.c | 34 +- bsp/common/trap.h | 25 +- lib/libc/retarget.c | 6 +- make/complier.mk | 14 +- make/complier.mk_o | 189 ++ make/ld/e2000_ft2004_aarch32_ram.ld | 75 +- 30 files changed, 2928 insertions(+), 139 deletions(-) create mode 100644 baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o create mode 100644 bsp/arch/armv8/aarch32/gcc/exception_debug.c create mode 100644 make/complier.mk_o diff --git a/.vscode/settings.json b/.vscode/settings.json index 0c05f9d14..9f8492057 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -17,6 +17,7 @@ "pl011_uart.h": "c", "early_uart.h": "c", "message_buffer.h": "c", - "early_uart.h": "c" + "*.c_a64": "c", + "*.c_old": "c" } } \ No newline at end of file diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig index 6cffbf020..5b6895371 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig @@ -61,7 +61,15 @@ CONFIG_LOG_ERROR=y # # Components Configuration # -# CONFIG_USE_SPI is not set +CONFIG_USE_SPI=y + +# +# SPI Configuration +# +CONFIG_SPI_POLLING_MODE=y +# CONFIG_SPI_IRQ_MODE is not set +# end of SPI Configuration + # CONFIG_USE_QSPI is not set CONFIG_USE_GIC=y diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h index 8e1b3c132..012549a74 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h @@ -5,6 +5,8 @@ #define CONFIG_COMPILER_NO_STD_STARUP 1 #define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 #define CONFIG_LOG_ERROR 1 +#define CONFIG_USE_SPI 1 +#define CONFIG_SPI_POLLING_MODE 1 #define CONFIG_USE_GIC 1 #define CONFIG_EBABLE_GICV3 1 #define CONFIG_USE_CACHE 1 diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old index 8d7c0e995..76a59fea1 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old @@ -16,10 +16,10 @@ CONFIG_TARGET_NAME="cache_test" CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set # CONFIG_TARGET_ARMV7 is not set -# CONFIG_TARGET_F2000_4 is not set +CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set -CONFIG_TARGET_E2000=y +# CONFIG_TARGET_E2000 is not set # end of Target Setting # @@ -61,7 +61,15 @@ CONFIG_LOG_ERROR=y # # Components Configuration # -# CONFIG_USE_SPI is not set +CONFIG_USE_SPI=y + +# +# SPI Configuration +# +CONFIG_SPI_POLLING_MODE=y +# CONFIG_SPI_IRQ_MODE is not set +# end of SPI Configuration + # CONFIG_USE_QSPI is not set CONFIG_USE_GIC=y @@ -86,6 +94,6 @@ CONFIG_USE_MMU=y # # Library Configuration # -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y # end of Library Configuration diff --git a/baremetal/example/aarch32_hello_world/Makefile b/baremetal/example/aarch32_hello_world/Makefile index df9921cb3..1e9def789 100644 --- a/baremetal/example/aarch32_hello_world/Makefile +++ b/baremetal/example/aarch32_hello_world/Makefile @@ -9,4 +9,4 @@ rebuild: boot: make - @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ \ No newline at end of file + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ \ No newline at end of file diff --git a/baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o b/baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o new file mode 100644 index 000000000..bd5a22d15 --- /dev/null +++ b/baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o @@ -0,0 +1,2174 @@ +Archive member included to satisfy reference by file (symbol) + +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (atexit) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o (__errno) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (exit) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (__libc_fini_array) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) (_global_impure_ptr) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (__libc_init_array) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (memset) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o (printf) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o (setvbuf) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + 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+/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) (_calloc_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) (_close_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) (_fclose_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) (fiprintf) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) (_fputwc_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) (_fstat_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) (__sfvwrite_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) (_isatty_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) (__locale_mb_cur_max) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) (_lseek_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (__ascii_mbtowc) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) (memmove) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) (_read_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) (_realloc_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) (errno) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (strcmp) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) (__swbuf_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) (_wcrtomb_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (__ascii_wctomb) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) (abort) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (_ctype_) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) (raise) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) (_kill_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_dmul) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_uidiv) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) (__aeabi_idiv) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_dsub) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_ddiv) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__aeabi_dcmpeq) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__aeabi_dcmpun) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_d2iz) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__aeabi_uldivmod) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4) + +Allocating common symbols +Common symbol size file + +errno 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) +isr_table 0x500 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o +ft_assert_status 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + +Memory Configuration + +Name Origin Length Attributes +ROM 0x0000000080100000 0x0000000000100000 xr +RAM 0x0000000081000000 0x0000000002000000 xrw +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o +LOAD ./build/./main.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libm.a +START GROUP +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a +END GROUP +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + 0x0000000000000400 HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400 + +.text 0x0000000080100000 0xee0d + 0x0000000080100000 _text_start = . + *(.Startup_Aarch32) + .Startup_Aarch32 + 0x0000000080100000 0x360 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + 0x0000000080100000 Startup_Aarch32 + 0x0000000080100118 RST_Handler + *(.vector_table) + *fill* 0x0000000080100360 0x4a0 + .vector_table 0x0000000080100800 0xcc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + 0x0000000080100800 system_vectors + 0x0000000080100820 Abort_Exception + 0x0000000080100830 IRQ_Handler + 0x000000008010087c FIQ_Handler + 0x0000000080100884 UDF_Handler + 0x000000008010088c SWI_Handler + 0x0000000080100894 PRF_Handler + 0x00000000801008c0 DAT_Handler + *(.text*) + .text 0x00000000801008cc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o + .text 0x00000000801008cc 0xa8 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + .text 0x0000000080100974 0xdc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + 0x0000000080100974 _stack_init + 0x00000000801009e8 _mainCRTStartup + 0x00000000801009e8 _start + .text 0x0000000080100a50 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .text 0x0000000080100a50 0x8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + 0x0000000080100a50 c_startup + .text 0x0000000080100a58 0x178 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + 0x0000000080100a58 cpu_get_smp_id + 0x0000000080100a60 cpu_mmu_disable + 0x0000000080100a78 cpu_mmu_enable + 0x0000000080100a8c cpu_tlb_set + 0x0000000080100aa4 cpu_dcache_clean_flush + 0x0000000080100b38 cpu_icache_flush + 0x0000000080100b4c cpu_vector_set_base + 0x0000000080100b64 cpu_dcache_disable + 0x0000000080100b80 cpu_icache_disable + 0x0000000080100b90 cpu_icache_enable + 0x0000000080100ba0 cpu_dcache_enable + 0x0000000080100bb0 cp15_get_cpu_id + 0x0000000080100bc0 cp15_set_vector_base + .text 0x0000000080100bd0 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + 0x0000000080100bd0 DisableInterrupt + 0x0000000080100bdc EnableInterrupt + .text 0x0000000080100be4 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + *fill* 0x0000000080100be4 0xc + .text 0x0000000080100bf0 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + 0x0000000080100bf0 FSmc_Call + .text 0x0000000080100c10 0x330 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + 0x0000000080100c10 FtDumpHexByte + 0x0000000080100d9c FtDumpHexWord + .text 0x0000000080100f40 0x254 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + 0x0000000080100f40 ShowExceptionRegisters + 0x0000000080101050 PrfTrap + 0x0000000080101080 SystemIrqHandler + 0x00000000801010f0 IrqHandleException + 0x000000008010117c fiq_handle + .text 0x0000000080101194 0x41c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + 0x0000000080101194 PlatformGetIrqStartNum + 0x00000000801011b0 PlatformGetGicDistBase + 0x00000000801011cc InterruptInit + 0x000000008010122c InterruptMask + 0x0000000080101254 InterruptUmask + 0x000000008010127c InterruptGetIrq + 0x0000000080101298 InterruptAck + 0x00000000801012c0 InterruptSetTargetCpus + 0x00000000801012f0 InterruptGetTargetCpus + 0x000000008010131c InterruptSetTrigerMode + 0x000000008010134c InterruptGetTrigerMode + 0x0000000080101378 InterruptSetPending + 0x00000000801013a0 InterruptGetPending + 0x00000000801013cc InterruptClearPending + 0x00000000801013f4 InterruptSetPriority + 0x0000000080101424 InterruptGetPriority + 0x0000000080101450 InterruptSetPriorityMask + 0x0000000080101478 InterruptGetPriorityMask + 0x0000000080101494 InterruptSetPriorGroupBits + 0x00000000801014e8 InterruptGetPriorGroupBits + 0x000000008010151c InterruptInstall + .text 0x00000000801015b0 0x98 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + 0x00000000801015b0 FtAssert + 0x0000000080101618 FtAssertSetCb + .text 0x0000000080101648 0x378 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + 0x0000000080101648 GenericTimerStart + 0x00000000801016a8 GenericTimerStop + 0x0000000080101708 GenericTimerInterruptEnable + 0x0000000080101768 GenericTimerInterruptDisable + 0x00000000801017e8 GenericTimerFrequecy + 0x0000000080101834 GenericTimerRead + 0x00000000801018b4 GenericTimerCompare + 0x00000000801018e8 Aarch32Delay + 0x0000000080101954 Aarch32Udelay + .text 0x00000000801019c0 0x16c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + 0x00000000801019c0 PsciCpuOn + 0x0000000080101ab0 PsciCpuReset + .text 0x0000000080101b2c 0x5ec ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + 0x0000000080101b2c Dump2ndPageTable + 0x0000000080101cdc DumpPageTable + 0x0000000080101f24 SetMMUTable + 0x0000000080101fe0 SetDomainReg + 0x0000000080102014 InitMMUTable + 0x0000000080102084 InitMMU + 0x00000000801020c4 InitCache + .text 0x0000000080102118 0x374 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + 0x0000000080102118 AsmFlushL3Dcache + 0x0000000080102134 AsmInvaliDateL3dcache + 0x00000000801021bc IcacheInvalidate + 0x0000000080102268 DcacheInvalidate + 0x0000000080102314 DcacheClean + 0x00000000801023c0 IcacheOps + 0x00000000801023fc DcacheOps + 0x0000000080102454 GetCpuIcacheStatus + 0x0000000080102470 GetCpuDcacheStatus + .text 0x000000008010248c 0x8c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + 0x000000008010248c fsleep_seconds + .text 0x0000000080102518 0x19c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + 0x0000000080102518 FiqDebug + 0x0000000080102530 UdfDebug + 0x0000000080102548 SwiDebug + 0x0000000080102560 PrfDebug + 0x0000000080102578 DatDebug + 0x0000000080102590 TraceDebug + 0x00000000801025ac TraceDebug1 + 0x00000000801025c8 TraceDebug2 + 0x00000000801025e4 TraceSctrl + 0x000000008010261c TraceTLB + 0x0000000080102654 TraceR0 + 0x0000000080102680 TraceR0R1 + .text 0x00000000801026b4 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .text 0x00000000801026b4 0x1e4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + 0x00000000801026b4 GetCpuId + 0x0000000080102748 GetCpuCluster + 0x00000000801027ac SpinLockInit + 0x00000000801027d4 SpinLock + 0x0000000080102854 SpinUnlock + .text 0x0000000080102898 0xf8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + 0x00000000801028f8 OutByte + 0x000000008010294c GetByte + .text 0x0000000080102990 0x28d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + 0x0000000080102990 ArmGicCpuMaskToAffval + 0x00000000801029bc GetMainCpuAffval + 0x00000000801029e0 ArmGicGetActiveIrq + 0x0000000080102a70 ArmGicAck + 0x0000000080102b20 ArmGicMask + 0x0000000080102cbc ArmGicUmask + 0x0000000080102e58 ArmGicGetPendingIrq + 0x0000000080102fe8 ArmGicSetPendingIrq + 0x0000000080103128 ArmGicClearPendingIrq + 0x0000000080103290 ArmGicSetConfiguration + 0x0000000080103404 ArmGicGetConfiguration + 0x0000000080103514 ArmGicClearActive + 0x0000000080103620 ArmGicSetCpu + 0x000000008010378c ArmGicGetTargetCpu + 0x000000008010389c ArmGicSetPriority + 0x0000000080103b28 ArmGicGetPriority + 0x0000000080103ce8 ArmGicSetSystemRegisterEnableMask + 0x0000000080103d60 ArmGicGetSystemRegisterEnableMask + 0x0000000080103dd0 ArmGicSetInterfacePriorMask + 0x0000000080103e44 ArmGicGetInterfacePriorMask + 0x0000000080103eb4 ArmGicSetBinaryPoint + 0x0000000080103eec ArmGicGetBinaryPoint + 0x0000000080103f18 ArmGicGetIrqStatus + 0x0000000080104080 ArmGicSendAffinitySgi + 0x00000000801042a8 ArmGicGetHighPendingIrq + 0x0000000080104318 ArmGicGetInterfaceId + 0x00000000801043a0 ArmGicSetGroup + 0x0000000080104558 ArmGicGetGroup + 0x00000000801047a8 ArmGicDistInit + 0x0000000080104b20 ArmGicRedistAddressSet + 0x0000000080104c04 ArmGicCpuInterfaceAddressSet + 0x0000000080104cec ArmGicRedistInit + 0x0000000080104ed4 ArmGicCpuInit + 0x0000000080104fa0 ArmGicDumpType + 0x0000000080105074 ArmGicDump + 0x000000008010523c gic_dump + .text 0x0000000080105260 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .text 0x0000000080105260 0x164 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + 0x00000000801052c0 Pl011SendByte + 0x0000000080105318 Pl011RecvByte + 0x000000008010536c Pl011GetChar + .text 0x00000000801053c4 0x88 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + 0x00000000801053c4 Pl011LookupConfig + .text 0x000000008010544c 0xcbc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + 0x00000000801054ac Pl011CfgInitialize + 0x000000008010568c Pl011Send + 0x000000008010581c Pl011PutChar + 0x0000000080105958 Pl011SendBuffer + 0x0000000080105a58 Pl011Receive + 0x0000000080105be4 Pl011ReceiveBuffer + 0x0000000080105d2c Pl011BlockSend + 0x0000000080105e68 Pl011BlockReceive + 0x0000000080105f30 Pl011SetBaudRate + 0x0000000080106088 Pl011IrqClearReciveTimeOut + 0x00000000801060c8 Pl011IrqEnableReciveTimeOut + .text 0x0000000080106108 0x4d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + 0x0000000080106168 Pl011SetOptions + 0x0000000080106334 Pl011SetSpecificOptions + 0x0000000080106484 Pl011ClearSpecificOptions + .text 0x00000000801065d8 0x620 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + 0x0000000080106638 Pl011GetInterruptMask + 0x00000000801066b4 Pl011SetInterruptMask + 0x0000000080106740 Pl011SetHandler + 0x0000000080106850 Pl011InterruptHandler + .text 0x0000000080106bf8 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .text 0x0000000080106bf8 0x2d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + 0x0000000080106bf8 initialise_monitor_handles + 0x0000000080106c48 _read + 0x0000000080106cb8 _write + 0x0000000080106d48 _lseek + 0x0000000080106d80 _close + 0x0000000080106da4 _fstat + 0x0000000080106dd8 _isatty + 0x0000000080106e08 _sbrk + 0x0000000080106e5c _exit + 0x0000000080106e78 _getpid + 0x0000000080106e94 _kill + .text 0x0000000080106ec8 0x40 ./build/./main.o + 0x0000000080106ec8 main + 0x0000000080106ef0 test_pos + .text 0x0000000080106f08 0xc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + 0x0000000080106f08 atexit + .text 0x0000000080106f14 0xc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + 0x0000000080106f14 __errno + .text 0x0000000080106f20 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + 0x0000000080106f20 exit + .text 0x0000000080106f40 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + 0x0000000080106f40 __libc_fini_array + .text 0x0000000080106f70 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .text 0x0000000080106f70 0x50 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + 0x0000000080106f70 __libc_init_array + .text 0x0000000080106fc0 0xa0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + 0x0000000080106fc0 memset + .text 0x0000000080107060 0x4c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + 0x0000000080107060 _printf_r + 0x0000000080107080 printf + .text 0x00000000801070ac 0x154 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + 0x00000000801070ac setvbuf + .text 0x0000000080107200 0x160c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + 0x0000000080107200 _vfprintf_r + 0x0000000080108788 vfprintf + .text 0x000000008010880c 0xc8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + 0x000000008010880c __swsetup_r + .text 0x00000000801088d4 0x6c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + 0x00000000801088d4 __register_exitproc + .text 0x0000000080108940 0x9c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + 0x0000000080108940 __call_exitprocs + .text.startup 0x00000000801089dc 0x18 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + *fill* 0x00000000801089f4 0x4 + .text 0x00000000801089f8 0x10c0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + 0x0000000080108b38 _dtoa_r + .text 0x0000000080109ab8 0x1b0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + 0x0000000080109ab8 __sflush_r + 0x0000000080109c0c _fflush_r + 0x0000000080109c40 fflush + .text 0x0000000080109c68 0x210 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + 0x0000000080109c6c _cleanup_r + 0x0000000080109d60 __sfmoreglue + 0x0000000080109d90 __sfp + 0x0000000080109e18 _cleanup + 0x0000000080109e30 __sinit + 0x0000000080109e38 __sfp_lock_acquire + 0x0000000080109e3c __sfp_lock_release + 0x0000000080109e40 __sinit_lock_acquire + 0x0000000080109e44 __sinit_lock_release + 0x0000000080109e48 __fp_lock_all + 0x0000000080109e60 __fp_unlock_all + .text 0x0000000080109e78 0x2a8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + 0x0000000080109e78 _malloc_trim_r + 0x0000000080109f24 _free_r + .text 0x000000008010a120 0x98 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + 0x000000008010a120 _fwalk + 0x000000008010a168 _fwalk_reent + .text 0x000000008010a1b8 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + 0x000000008010a1b8 __localeconv_l + 0x000000008010a1bc _localeconv_r + 0x000000008010a1c4 localeconv + .text 0x000000008010a1cc 0xf8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + 0x000000008010a1cc __swhatbuf_r + 0x000000008010a228 __smakebuf_r + .text 0x000000008010a2c4 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + 0x000000008010a2c4 malloc + 0x000000008010a2d4 free + .text 0x000000008010a2e4 0x588 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + 0x000000008010a2e4 _malloc_r + .text 0x000000008010a86c 0x8c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + 0x000000008010a86c memchr + .text 0x000000008010a8f8 0xec /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + 0x000000008010a8f8 memcpy + .text 0x000000008010a9e4 0x8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + 0x000000008010a9e4 __malloc_lock + 0x000000008010a9e8 __malloc_unlock + .text 0x000000008010a9ec 0x9e0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + 0x000000008010a9ec _Balloc + 0x000000008010aa38 _Bfree + 0x000000008010aa4c __multadd + 0x000000008010aafc __s2b + 0x000000008010abb4 __hi0bits + 0x000000008010abf4 __lo0bits + 0x000000008010ac50 __i2b + 0x000000008010ac80 __multiply + 0x000000008010ade0 __pow5mult + 0x000000008010ae7c __lshift + 0x000000008010af54 __mcmp + 0x000000008010af90 __mdiff + 0x000000008010b0d0 __ulp + 0x000000008010b110 __b2d + 0x000000008010b1d4 __d2b + 0x000000008010b29c __ratio + 0x000000008010b2f4 _mprec_log10 + 0x000000008010b32c __copybits + 0x000000008010b374 __any_on + .text 0x000000008010b3cc 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + 0x000000008010b3cc _sbrk_r + .text 0x000000008010b3f4 0x90 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + 0x000000008010b3f4 __sread + 0x000000008010b418 __seofread + 0x000000008010b41c __swrite + 0x000000008010b45c __sseek + 0x000000008010b47c __sclose + .text 0x000000008010b484 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + 0x000000008010b484 strlen + .text 0x000000008010b4e0 0xd68 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + 0x000000008010b554 __sprint_r + 0x000000008010b564 _vfiprintf_r + 0x000000008010c1c4 vfiprintf + .text 0x000000008010c248 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + 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./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .data 0x0000000081000008 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .data 0x0000000081000008 0x90 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + 0x0000000081000008 platform_mem_desc + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .data 0x0000000081000098 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .data 0x0000000081000098 0x30 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .data 0x00000000810000c8 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .data 0x00000000810000c8 0x40 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + 0x00000000810000c8 Pl011ConfigTable + .data 0x0000000081000108 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .data 0x000000008100010c 0x0 ./build/./main.o + .data 0x000000008100010c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .data 0x000000008100010c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .data 0x000000008100010c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .data 0x000000008100010c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + *fill* 0x000000008100010c 0x4 + .data 0x0000000081000110 0x430 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + 0x0000000081000110 _impure_ptr + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .data 0x0000000081000540 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .data 0x0000000081000540 0x410 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + 0x0000000081000540 __malloc_av_ + 0x0000000081000948 __malloc_sbrk_base + 0x000000008100094c __malloc_trim_threshold + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .data 0x0000000081000950 0x0 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+ .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .data 0x0000000081000950 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .data 0x0000000081000950 0x16c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + 0x0000000081000950 __global_locale + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + .data 0x0000000081000abc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + 0x0000000081001000 . = ALIGN (0x1000) + *fill* 0x0000000081000abc 0x544 + 0x0000000081001000 _data_end = . + +.init_array 0x0000000081001000 0x4 load address 0x0000000080110000 + .init_array 0x0000000081001000 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + +.tm_clone_table + 0x0000000081001004 0x0 load address 0x0000000080110004 + .tm_clone_table + 0x0000000081001004 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + .tm_clone_table + 0x0000000081001004 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + +.igot.plt 0x0000000081001004 0x0 load address 0x0000000080110004 + .igot.plt 0x0000000081001004 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + +.init_array.00000 + 0x0000000081001004 0x4 load address 0x0000000080110004 + .init_array.00000 + 0x0000000081001004 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + +.bss 0x0000000081004000 0x8558 load address 0x0000000080114000 + 0x0000000081004000 __bss_start__ = . + 0x0000000081004000 _bss_start = __bss_start__ + *(.bss) + .bss 0x0000000081004000 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o + .bss 0x0000000081004000 0x1c /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + .bss 0x000000008100401c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .bss 0x000000008100401c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .bss 0x000000008100401c 0xc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + 0x000000008100401c rt_interrupt_from_thread + 0x0000000081004020 rt_interrupt_to_thread + 0x0000000081004024 rt_thread_switch_interrupt_flag + .bss 0x0000000081004028 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .bss 0x000000008100402c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .bss 0x000000008100402c 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + *fill* 0x000000008100402c 0x3fd4 + .bss 0x0000000081008000 0x4000 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .bss 0x000000008100c000 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .bss 0x000000008100c000 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .bss 0x000000008100c000 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .bss 0x000000008100c000 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .bss 0x000000008100c000 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + 0x000000008100c000 _lock + .bss 0x000000008100c004 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .bss 0x000000008100c004 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .bss 0x000000008100c018 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .bss 0x000000008100c018 0x0 ./build/./main.o + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + .bss 0x000000008100c018 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + .bss 0x000000008100c018 0x34 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + 0x000000008100c018 __malloc_top_pad + 0x000000008100c01c __malloc_current_mallinfo + 0x000000008100c044 __malloc_max_sbrked_mem + 0x000000008100c048 __malloc_max_total_mem + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .bss 0x000000008100c04c 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .bss 0x000000008100c04c 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + 0x000000008100c04c _PathLocale + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + 0x000000008100c050 __bss_end__ = . + 0x000000008100c050 _bss_end = __bss_end__ + COMMON 0x000000008100c050 0x500 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + 0x000000008100c050 isr_table + COMMON 0x000000008100c550 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + 0x000000008100c550 ft_assert_status + COMMON 0x000000008100c554 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + 0x000000008100c554 errno + +.heap 0x000000008100c558 0xaa8 load address 0x000000008011c558 + 0x000000008100c558 . = ALIGN (0x8) + 0x000000008100c558 __end__ = . + 0x000000008100c558 PROVIDE (end = .) + 0x000000008100c558 __HeapBase = . + 0x000000008100c958 . = (. + HEAP_SIZE) + *fill* 0x000000008100c558 0x400 + 0x000000008100d000 . = ALIGN (0x1000) + *fill* 0x000000008100c958 0x6a8 + 0x000000008100d000 __HeapLimit = . + 0x000000008100d000 __heap_limit = . + 0x000000008100d000 _fiq_stack_start = (ADDR (.heap) + SIZEOF (.heap)) + 0x000000008100e000 _fiq_stack_end = (_fiq_stack_start + 0x1000) + 0x000000008100e000 _irq_stack_start = _fiq_stack_end + 0x000000008100f000 _irq_stack_end = (_irq_stack_start + 0x1000) + 0x000000008100f000 _sys_stack_start = _irq_stack_end + 0x0000000081010000 _sys_stack_end = (_sys_stack_start + 0x1000) + 0x0000000081010000 _svc_stack_start = _sys_stack_end + 0x0000000081011000 _svc_stack_end = (_svc_stack_start + 0x1000) + 0x0000000000001000 _irq_stack_size = (_irq_stack_end - _irq_stack_start) + 0x0000000000001000 _fiq_stack_size = (_fiq_stack_end - _fiq_stack_start) + 0x0000000000001000 _sys_stack_size = (_sys_stack_end - _sys_stack_start) + 0x0000000000001000 _svc_stack_size = (_svc_stack_end - _svc_stack_start) +OUTPUT(ft2004_baremetal.elf elf32-littlearm) +LOAD linker stubs + +.ARM.attributes + 0x0000000000000000 0x33 + .ARM.attributes + 0x0000000000000000 0x19 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o + .ARM.attributes + 0x0000000000000019 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + .ARM.attributes + 0x0000000000000042 0x17 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + .ARM.attributes + 0x0000000000000059 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .ARM.attributes + 0x000000000000007e 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + .ARM.attributes + 0x00000000000000a3 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + .ARM.attributes + 0x00000000000000c8 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + .ARM.attributes + 0x00000000000000ed 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + .ARM.attributes + 0x0000000000000112 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + .ARM.attributes + 0x0000000000000137 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .ARM.attributes + 0x000000000000016e 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .ARM.attributes + 0x00000000000001a5 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .ARM.attributes + 0x00000000000001dc 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .ARM.attributes + 0x0000000000000213 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .ARM.attributes + 0x000000000000024a 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .ARM.attributes + 0x0000000000000281 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .ARM.attributes + 0x00000000000002b8 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .ARM.attributes + 0x00000000000002ef 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .ARM.attributes + 0x0000000000000326 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .ARM.attributes + 0x000000000000035d 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .ARM.attributes + 0x0000000000000394 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .ARM.attributes + 0x00000000000003cb 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .ARM.attributes + 0x0000000000000402 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .ARM.attributes + 0x0000000000000439 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .ARM.attributes + 0x0000000000000470 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .ARM.attributes + 0x00000000000004a7 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .ARM.attributes + 0x00000000000004de 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .ARM.attributes + 0x0000000000000515 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .ARM.attributes + 0x000000000000054c 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .ARM.attributes + 0x0000000000000583 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .ARM.attributes + 0x00000000000005ba 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .ARM.attributes + 0x00000000000005f1 0x37 ./build/./main.o + .ARM.attributes + 0x0000000000000628 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .ARM.attributes + 0x0000000000000651 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + .ARM.attributes + 0x000000000000067a 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + .ARM.attributes + 0x00000000000006a3 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + .ARM.attributes + 0x00000000000006cc 0x29 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/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + .ARM.attributes + 0x0000000000000814 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + .ARM.attributes + 0x000000000000083d 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + .ARM.attributes + 0x0000000000000866 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + .ARM.attributes + 0x000000000000088f 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + .ARM.attributes + 0x00000000000008b8 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + .ARM.attributes + 0x00000000000008e1 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + .ARM.attributes + 0x000000000000090a 0x29 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/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .debug_str 0x0000000000004198 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .debug_str 0x0000000000004198 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .debug_str 0x0000000000004198 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .debug_str 0x0000000000004198 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x9d (size before relaxing) + .debug_str 0x00000000000041c4 0x10a2 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + 0x1193 (size before relaxing) + +.debug_frame 0x0000000000000000 0x2b48 + .debug_frame 0x0000000000000000 0x50 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .debug_frame 0x0000000000000050 0xb0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .debug_frame 0x0000000000000100 0x2a8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .debug_frame 0x00000000000003a8 0x50 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .debug_frame 0x00000000000003f8 0x150 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .debug_frame 0x0000000000000548 0x4c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .debug_frame 0x0000000000000594 0xec ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .debug_frame 0x0000000000000680 0x170 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .debug_frame 0x00000000000007f0 0x38 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .debug_frame 0x0000000000000828 0x184 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/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) + .debug_loc 0x000000000000d676 0x14f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) + .debug_loc 0x000000000000d7c5 0x24b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + .debug_loc 0x000000000000da10 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + .debug_loc 0x000000000000da6c 0x179 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + .debug_loc 0x000000000000dbe5 0xa6 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + .debug_loc 0x000000000000dc8b 0x3bf /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) + .debug_loc 0x000000000000e04a 0x9b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) + .debug_loc 0x000000000000e0e5 0x695 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .debug_loc 0x000000000000e77a 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .debug_loc 0x000000000000e7d6 0x169 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + .debug_loc 0x000000000000e93f 0xbd /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .debug_loc 0x000000000000e9fc 0x24f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .debug_loc 0x000000000000ec4b 0x373 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .debug_loc 0x000000000000efbe 0xbd /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .debug_loc 0x000000000000f07b 0xf5d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .debug_loc 0x000000000000ffd8 0x152 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .debug_loc 0x000000000001012a 0x1d7 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .debug_loc 0x0000000000010301 0x281 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .debug_loc 0x0000000000010582 0x118 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .debug_loc 0x000000000001069a 0x47b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .debug_loc 0x0000000000010b15 0xc0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .debug_loc 0x0000000000010bd5 0x20d /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) diff --git a/baremetal/example/aarch32_hello_world/main.c b/baremetal/example/aarch32_hello_world/main.c index 429c0c01f..186830fc7 100644 --- a/baremetal/example/aarch32_hello_world/main.c +++ b/baremetal/example/aarch32_hello_world/main.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-07-01 17:12:55 - * @LastEditTime: 2021-07-01 17:13:03 + * @LastEditTime: 2021-07-09 17:58:31 * @Description:  This files is for * * @Modify History: @@ -20,7 +20,13 @@ int main(void) while (1) { /* code */ - printf("hello world \r\n "); + OutByte('1'); + printf("hello world \r\n"); fsleep_seconds(10); } +} + +void test_pos(void) +{ + OutByte('1'); } \ No newline at end of file diff --git a/baremetal/example/aarch32_hello_world/sdkconfig b/baremetal/example/aarch32_hello_world/sdkconfig index 6edad1040..3f8d35b31 100644 --- a/baremetal/example/aarch32_hello_world/sdkconfig +++ b/baremetal/example/aarch32_hello_world/sdkconfig @@ -11,7 +11,7 @@ CONFIG_TARGET_NAME="ft2004_baremetal" # end of Project Configuration # -# Build Target +# Target Setting # CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set @@ -20,10 +20,10 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -42,7 +42,7 @@ CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration @@ -83,13 +83,15 @@ CONFIG_ENABLE_Pl011_UART=y # # Arch Configuration # -# CONFIG_USE_CACHE is not set +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y # end of Arch Configuration # end of Board Configuration # # Library Configuration # -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y # end of Library Configuration diff --git a/baremetal/example/aarch32_hello_world/sdkconfig.h b/baremetal/example/aarch32_hello_world/sdkconfig.h index 31000411d..be78f3ff5 100644 --- a/baremetal/example/aarch32_hello_world/sdkconfig.h +++ b/baremetal/example/aarch32_hello_world/sdkconfig.h @@ -9,4 +9,7 @@ #define CONFIG_EBABLE_GICV3 1 #define CONFIG_USE_USART 1 #define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_NOSTD_LIBC 1 +#define CONFIG_USE_CACHE 1 +#define CONFIG_USE_L3CACHE 1 +#define CONFIG_USE_MMU 1 +#define CONFIG_USE_LIBC 1 diff --git a/baremetal/example/aarch32_hello_world/sdkconfig.old b/baremetal/example/aarch32_hello_world/sdkconfig.old index 5908f83fd..b82fce4cb 100644 --- a/baremetal/example/aarch32_hello_world/sdkconfig.old +++ b/baremetal/example/aarch32_hello_world/sdkconfig.old @@ -11,7 +11,7 @@ CONFIG_TARGET_NAME="ft2004_baremetal" # end of Project Configuration # -# Build Target +# Target Setting # CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set @@ -20,10 +20,10 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -32,19 +32,18 @@ CONFIG_ENVI_UBUNTU_20_04=y # Cross-Compiler Setting # CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set +CONFIG_USE_EXT_COMPILER=y +CONFIG_EXT_COMPILER_PREFIX="/usr" # end of Cross-Compiler Setting # # GNU linker # CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration @@ -85,13 +84,15 @@ CONFIG_ENABLE_Pl011_UART=y # # Arch Configuration # -# CONFIG_USE_CACHE is not set +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y # end of Arch Configuration # end of Board Configuration # # Library Configuration # -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y # end of Library Configuration diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig b/baremetal/example/aarch32_uart_irq/sdkconfig index 5908f83fd..3f8d35b31 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig +++ b/baremetal/example/aarch32_uart_irq/sdkconfig @@ -11,7 +11,7 @@ CONFIG_TARGET_NAME="ft2004_baremetal" # end of Project Configuration # -# Build Target +# Target Setting # CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set @@ -20,10 +20,10 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -39,12 +39,10 @@ CONFIG_COMPILER_NO_STD_STARUP=y # GNU linker # CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration @@ -85,13 +83,15 @@ CONFIG_ENABLE_Pl011_UART=y # # Arch Configuration # -# CONFIG_USE_CACHE is not set +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y # end of Arch Configuration # end of Board Configuration # # Library Configuration # -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y # end of Library Configuration diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig.h b/baremetal/example/aarch32_uart_irq/sdkconfig.h index 31000411d..be78f3ff5 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig.h +++ b/baremetal/example/aarch32_uart_irq/sdkconfig.h @@ -9,4 +9,7 @@ #define CONFIG_EBABLE_GICV3 1 #define CONFIG_USE_USART 1 #define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_NOSTD_LIBC 1 +#define CONFIG_USE_CACHE 1 +#define CONFIG_USE_L3CACHE 1 +#define CONFIG_USE_MMU 1 +#define CONFIG_USE_LIBC 1 diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig.old b/baremetal/example/aarch32_uart_irq/sdkconfig.old index acaf77a26..5908f83fd 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig.old +++ b/baremetal/example/aarch32_uart_irq/sdkconfig.old @@ -20,10 +20,6 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -CONFIG_TARGET_BARE_METAL=y -# CONFIG_TARGET_FREE_RTOS is not set -# CONFIG_TARGET_RT_THREAD is not set -# CONFIG_TARGET_U_BOOT is not set # end of Build Target # diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig b/baremetal/example/aarch64_uart_irq_send/sdkconfig index 838a710ba..55b0be668 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig @@ -81,8 +81,8 @@ CONFIG_USE_MMU=y # # Library Configuration # -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y # end of Library Configuration # diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig.h b/baremetal/example/aarch64_uart_irq_send/sdkconfig.h index 44d53db18..9feb5759e 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig.h +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig.h @@ -11,5 +11,5 @@ #define CONFIG_USE_CACHE 1 #define CONFIG_USE_L3CACHE 1 #define CONFIG_USE_MMU 1 -#define CONFIG_USE_NOSTD_LIBC 1 +#define CONFIG_USE_LIBC 1 #define CONFIG_TARGET_NAME "uart_irq_send" diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig.old b/baremetal/example/aarch64_uart_irq_send/sdkconfig.old index 55b0be668..838a710ba 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig.old +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig.old @@ -81,8 +81,8 @@ CONFIG_USE_MMU=y # # Library Configuration # -# CONFIG_USE_NOSTD_LIBC is not set -CONFIG_USE_LIBC=y +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set # end of Library Configuration # diff --git a/bsp/arch/armv8/aarch32/aarch32.h b/bsp/arch/armv8/aarch32/aarch32.h index 7a67ba379..361088f09 100644 --- a/bsp/arch/armv8/aarch32/aarch32.h +++ b/bsp/arch/armv8/aarch32/aarch32.h @@ -63,6 +63,17 @@ extern "C" return __MRC(15, 0, 14, 2, 1); } + /** + * @name: aarch32_cntp_tlb_get + * @msg: + * @return {*} + * @param {__STATIC_INLINE u32} aarch32_cntp_ctl_get + */ + __attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_tlb_get(void) + { + return __MRC(15, 0, 0, 2, 0); + } + /** * @name: aarch32_cntp_ctl_set * @msg: Read the register that holds the timer value for the EL1 physical timer. diff --git a/bsp/arch/armv8/aarch32/fsleep.c b/bsp/arch/armv8/aarch32/fsleep.c index 89a8c5250..6cf9af695 100644 --- a/bsp/arch/armv8/aarch32/fsleep.c +++ b/bsp/arch/armv8/aarch32/fsleep.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-07-01 18:40:52 - * @LastEditTime: 2021-07-01 18:41:47 + * @LastEditTime: 2021-07-09 17:58:46 * @Description:  This files is for * * @Modify History: @@ -25,7 +25,7 @@ u32 fsleep_seconds(u32 seconds) GenericTimerStart(); cur_time = GenericTimerRead(); end_time = cur_time + ((u64)seconds * GenericTimerFrequecy()); - printf("%d \r\n", GenericTimerFrequecy()); + // printf("%d \r\n", GenericTimerFrequecy()); do { cur_time = GenericTimerRead(); diff --git a/bsp/arch/armv8/aarch32/gcc/cp15.S b/bsp/arch/armv8/aarch32/gcc/cp15.S index 2fa70bf2b..97b55e9e8 100644 --- a/bsp/arch/armv8/aarch32/gcc/cp15.S +++ b/bsp/arch/armv8/aarch32/gcc/cp15.S @@ -15,13 +15,14 @@ cpu_mmu_disable: .globl cpu_mmu_enable cpu_mmu_enable: mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x001 + orr r0, r0, #0x001 @ bit 1, mmu enable mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit dsb bx lr .globl cpu_tlb_set cpu_tlb_set: + orr r1, r0, #0x6a mcr p15, #0, r0, c2, c0, #0 dmb bx lr diff --git a/bsp/arch/armv8/aarch32/gcc/exception_debug.c b/bsp/arch/armv8/aarch32/gcc/exception_debug.c new file mode 100644 index 000000000..af19667a8 --- /dev/null +++ b/bsp/arch/armv8/aarch32/gcc/exception_debug.c @@ -0,0 +1,108 @@ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-06 08:08:20 + * @LastEditTime: 2021-07-06 19:58:00 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include +#include "aarch32.h" + +//#define EXCEPTION_DEBUG_ON + +void FiqDebug() +{ +#ifdef EXCEPTION_DEBUG_ON + printf("fiq abort\r\n"); +#endif +} + +void UdfDebug() +{ +#ifdef EXCEPTION_DEBUG_ON + printf("undefine abort\r\n"); +#endif +} + +void SwiDebug() +{ +#ifdef EXCEPTION_DEBUG_ON + printf("software irq abort\r\n"); +#endif +} + +void PrfDebug() +{ +#ifdef EXCEPTION_DEBUG_ON + printf("prefetch abort\r\n"); +#endif +} + +void DatDebug() +{ +#ifdef EXCEPTION_DEBUG_ON + printf("data abort\r\n"); +#endif +} + +void TraceDebug() +{ + printf("stub \r\n"); +} + +void TraceDebug1() +{ + printf("stub 1\r\n"); +} + +void TraceDebug2() +{ + printf("stub 1\r\n"); +} + +void TraceSctrl() +{ + /* SCTLR bit : 0 -- M – Enable the MMU + 1 -- A – Alignment check enable + 2 -- C – Cache enable bit + 3 -- nTLSMD + 4 -- LSMAOE + 5 -- CP15BEN + 6 -- UNK + 11 -- Z – Branch prediction enable + 12 -- I – Instruction cache enable bit + 13 -- V – This bit selects the base address of the exception vector table + 16 -- nTWI + 18 -- nTWE, Traps EL0 execution + 21 -- FI – FIQ configuration enable + 22 -- U – Indicates use of the alignment model. + 23 -- SPAN, Set Privileged Access Never + 25 -- EE - Exception endianness + 30 -- TE – Thumb exception enable */ + printf("MRC: 0x%x\r\n", aarch32_sctrl_get()); +} + +void TraceTLB() +{ + /* + TTBR0 + */ + printf("TLB: 0x%x\r\n", aarch32_cntp_tlb_get()); +} + +void TraceR0(u32 r0) +{ + printf("r0: 0x%x \r\n", r0); +} + +void TraceR0R1(u32 r0, u32 r1) +{ + printf("r0: 0x%x r1: 0x%x\r\n", r0, r1); +} \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/gcc/start.S b/bsp/arch/armv8/aarch32/gcc/start.S index 8a77c6bf4..5b9f918b9 100644 --- a/bsp/arch/armv8/aarch32/gcc/start.S +++ b/bsp/arch/armv8/aarch32/gcc/start.S @@ -1,8 +1,12 @@ #include "sdkconfig.h" +.equ MODE_USR, 0x10 .equ MODE_FIQ, 0x11 .equ MODE_IRQ, 0x12 .equ MODE_SVC, 0x13 +.equ MODE_ABT, 0x17 +.equ MODE_UND, 0x1B +.equ MODE_SYS, 0x1f .section .text /* The code segment, RD, program’s executable code */ /******************************************************************************* @@ -109,12 +113,15 @@ el2_mode: el1_mode: #endif -.balign 2048 -.global Reset_Handler -Reset_Handler: +.global RST_Handler +RST_Handler: cpsid i /* Mask interrupts */ - ldr r0,=#0 - mrc p15, 0, r0, c1, c0, 0 + + @mrc p15, 0, r0, c1, c0, 0 + ldr r0, =#0x0 + mcr p15, 0, r0, c1, c0, 0 /* reset control register */ + isb + /* set VBAR to the system_vectors address in linker script */ ldr r0, =system_vectors mcr p15, 0, r0, c12, c0, 0 @@ -128,7 +135,8 @@ Reset_Handler: beq overHyped b continue -overHyped: /* Get out of HYP mode */ +/* Get out of HYP mode */ +overHyped: adr r1, continue msr ELR_hyp, r1 mrs r1, cpsr_all @@ -140,16 +148,23 @@ overHyped: /* Get out of HYP mode */ continue: cps MODE_SVC +invalidate_caches_tlb: + mov r0,#0 /* r0 = 0 */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */ + bl invalidate_dcache /* invalidate dcache */ + disable_cache_mmu: @ Disable MMU - MRC p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data - BIC r1, r1, #0x1 - MCR p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data + mrc p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data + bic r1, r1, #0x1 + mcr p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data @ Disable L1 Caches - MRC p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data - BIC r1, r1, #(0x1 << 12) @ Disable I Cache - BIC r1, r1, #(0x1 << 2) @ Disable D Cache - MCR p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data + mrc p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data + bic r1, r1, #(0x1 << 12) @ Disable I Cache + bic r1, r1, #(0x1 << 2) @ Disable D Cache + mcr p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data /* disable the data alignment check */ mrc p15, 0, r1, c1, c0, 0 @@ -186,16 +201,27 @@ irq_loop: strlt r0, [r1], #4 blt irq_loop + /* System mode */ + msr cpsr_c, MODE_SYS + ldr r1, =_sys_stack_start + ldr sp, =_sys_stack_end + +sys_loop: + cmp r1, sp + strlt r0, [r1], #4 + blt sys_loop + +/* PUT SVC IN THE END, START UP WITH SVC MODE!!! */ /* Supervisor mode */ msr cpsr_c, MODE_SVC - ldr r1, =_stack_start - ldr sp, =_stack_end + ldr r1, =_svc_stack_start + ldr sp, =_svc_stack_end /* fill the supervisor mode stack */ -stack_loop: +svc_loop: cmp r1, sp strlt r0, [r1], #4 - blt stack_loop + blt svc_loop /* Start copying data */ ldr r0, =_text_end /* section address has been defined in ld script */ @@ -222,16 +248,94 @@ bss_loop: strlt r0, [r1], #4 blt bss_loop +@ using fpu +mov r4, #0xfffffff +mcr p15, 0, r4, c1, c0, 2 + #ifdef CONFIG_USE_CACHE +enable_branch_pred: + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #(1<<11) + mcr p15, 0, r0, c1, c0, 0 + init_cache_mmu: ldr r0, =platform_mem_desc ldr r1, =platform_mem_desc_size ldr r1, [r1] bl InitMMUTable bl InitCache -#endif +#endif + +extra_init: + @ Enable access to FP registers. + mov r1, #(0xF << 20) + mcr p15, 0, r1, c1, c0, 2 // CPACR full access to cp11 and cp10. + @ Enable Floating point and Neon unit. + mov r1, #(0x1 << 30) + vmsr FPEXC, r1 + ISB @Ensure the enable operation takes effect. start_up: cpsie i /* enable irq */ b c_startup /* jump to C startup code */ b Abort_Exception + +/* + ************************************************************************* + * + * invalidate_dcache - invalidate the entire d-cache by set/way + * + * Note: for Cortex-A53, there is no cp instruction for invalidating + * the whole D-cache. Need to invalidate each line. + * + ************************************************************************* + */ +invalidate_dcache: + mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */ + ands r3, r0, #0x7000000 + mov r3, r3, lsr #23 /* cache level value (naturally aligned) */ + beq finished + mov r10, #0 /* start with level 0 */ +loop1: + add r2, r10, r10, lsr #1 /* work out 3xcachelevel */ + mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */ + and r1, r1, #7 /* get those 3 bits alone */ + cmp r1, #2 + blt skip /* no cache or only instruction cache at this level */ + mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */ + isb /* isb to sync the change to the CacheSizeID reg */ + mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */ + and r2, r1, #7 /* extract the line length field */ + add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */ + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */ + clz r5, r4 /* r5 is the bit position of the way size increment */ + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */ +loop2: + mov r9, r4 /* r9 working copy of the max way size (right aligned) */ +loop3: + orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */ + orr r11, r11, r7, lsl r2 /* factor in the index number */ + mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */ + subs r9, r9, #1 /* decrement the way number */ + bge loop3 + subs r7, r7, #1 /* decrement the index */ + bge loop2 +skip: + add r10, r10, #2 /* increment the cache number */ + cmp r3, r10 + bgt loop1 + +finished: + mov r10, #0 /* switch back to cache level 0 */ + mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */ + dsb + isb + + bx lr + +.end +/** +* @} End of "addtogroup a53_32_boot_code". +*/ \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/gcc/vector.S b/bsp/arch/armv8/aarch32/gcc/vector.S index 2a337a2dd..5425378f9 100644 --- a/bsp/arch/armv8/aarch32/gcc/vector.S +++ b/bsp/arch/armv8/aarch32/gcc/vector.S @@ -1,4 +1,5 @@ #include "sdkconfig.h" +.equ MODE_SVC, 0x13 /* allocatable and executable */ .section .vector_table, "ax" @@ -6,24 +7,36 @@ .balign 2048 .global system_vectors system_vectors: - b Reset_Handler - b Undef_Handler /* 0x4 Undefined Instruction */ + b RST_Handler + b UDF_Handler /* 0x4 Undefined Instruction */ b SWI_Handler /* 0x8 Software Interrupt */ - b Pref_Handler /* 0xC Prefetch Abort */ - b Databt_Handler /* 0x10 Data Abort */ + b PRF_Handler /* 0xC Prefetch Abort */ + b DAT_Handler /* 0x10 Data Abort */ b . /* 0x14 Reserved */ b IRQ_Handler /* 0x18 IRQ */ - b Fiq_Handler /* 0x1C FIQ */ + b FIQ_Handler /* 0x1C FIQ */ .global Abort_Exception Abort_Exception: swi 0xFF +.macro PushSVCRegisters + sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} @/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr @/* Save CPSR */ + str lr, [r0, #15*4] @/* Push PC */ + str r6, [r0, #16*4] @/* Push CPSR */ + cps #MODE_SVC + str sp, [r0, #13*4] @/* Save calling SP */ + str lr, [r0, #14*4] @/* Save calling PC */ +.endm + .align 4 .arm .weak IRQ_Handler .type IRQ_Handler, %function -.global IRQ_Handler +@.global IRQ_Handler IRQ_Handler: /* 0x18 IRQ */ push {lr} /* Save return address+4 */ push {r0-r3, r12} /* Push caller save registers */ @@ -57,14 +70,27 @@ IRQ_Handler: /* 0x18 IRQ */ pop {r0-r3, r12} pop {lr} subs pc, lr, #4 + .size IRQ_Handler, . - IRQ_Handler -.global Fiq_Handler -Fiq_Handler: /* 0x18 IRQ */ - b Abort_Exception +.align 2 +.arm +.weak FIQ_Handler +.type FIQ_Handler, %function +.global FIQ_Handler +FIQ_Handler: /* 0x18 IRQ */ + bl FiqDebug + b Abort_Exception + .size FIQ_Handler, . - FIQ_Handler -.global Undef_Handler -Undef_Handler: /* 0x4 Undefined Instruction */ - b Abort_Exception +.align 2 +.arm +.weak UDF_Handler +.type UDF_Handler, %function +.global UDF_Handler +UDF_Handler: /* 0x4 Undefined Instruction */ + bl UdfDebug + b Abort_Exception + .size UDF_Handler, . - UDF_Handler .align 2 .arm @@ -72,12 +98,27 @@ Undef_Handler: /* 0x4 Undefined Instruction */ .type SWI_Handler, %function .global SWI_Handler SWI_Handler: /* 0x8 Software Interrupt */ - b Abort_Exception + bl SwiDebug + b Abort_Exception + .size SWI_Handler, . - SWI_Handler -.global Pref_Handler -Pref_Handler: /* 0xC Prefetch Abort */ - b Abort_Exception +.align 2 +.arm +.weak PRF_Handler +.type PRF_Handler, %function +.global PRF_Handler +PRF_Handler: /* 0xC Prefetch Abort */ + PushSVCRegisters + bl PrfTrap + b Abort_Exception + .size PRF_Handler, . - PRF_Handler -.global Databt_Handler -Databt_Handler: /* 0x10 Data Abort */ - b Abort_Exception \ No newline at end of file +.align 2 +.arm +.weak DAT_Handler +.type DAT_Handler, %function +.global DAT_Handler +DAT_Handler: /* 0x10 Data Abort */ + bl DatDebug + b Abort_Exception + .size DAT_Handler, . - DAT_Handler \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/mmu.c b/bsp/arch/armv8/aarch32/mmu.c index 847b4c123..730799000 100644 --- a/bsp/arch/armv8/aarch32/mmu.c +++ b/bsp/arch/armv8/aarch32/mmu.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 09:20:24 - * @LastEditTime: 2021-06-29 10:09:30 + * @LastEditTime: 2021-07-09 14:29:18 * @Description:  This files is for * * @Modify History: @@ -16,9 +16,10 @@ #include "ft_types.h" #include "mmu.h" #include "cp15.h" +#include "sdkconfig.h" /* dump 2nd level page table */ -void Dump2ndPageTable(u32 *ptb) +void Dump2ndPageTable(u32 *ptb) { int i; int fcnt = 0; @@ -49,26 +50,26 @@ void Dump2ndPageTable(u32 *ptb) if ((pte2 & 0x3) == 0x1) { printf("L,ap:%x,xn:%d,texcb:%02x\n", - ((pte2 >> 7) | (pte2 >> 4))& 0xf, - (pte2 >> 15) & 0x1, - ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + ((pte2 >> 7) | (pte2 >> 4)) & 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); } else { printf("S,ap:%x,xn:%d,texcb:%02x\n", - ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, - ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + ((pte2 >> 7) | (pte2 >> 4)) & 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); } } } -void DumpPageTable(u32 *ptb) +void DumpPageTable(u32 *ptb) { int i; int fcnt = 0; printf("page table@%p\n", ptb); - for (i = 0; i < 1024*4; i++) + for (i = 0; i < 1024 * 4; i++) { u32 pte1 = ptb[i]; if ((pte1 & 0x3) == 0) @@ -96,7 +97,7 @@ void DumpPageTable(u32 *ptb) else if ((pte1 & 0x3) == 0x1) { printf("pte,ns:%d,domain:%d\n", - (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); /* *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) * - 0x80000000 + 0xC0000000)); @@ -105,37 +106,38 @@ void DumpPageTable(u32 *ptb) else if (pte1 & (1 << 18)) { printf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10)) & 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); } else { printf("section,ns:%d,ap:%x," - "xn:%d,texcb:%02x,domain:%d\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - (((pte1 & (0x7 << 12)) >> 10) | - ((pte1 & 0x0c) >> 2)) & 0x1f, - (pte1 >> 5) & 0xf); + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10)) & 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & + 0x1f, + (pte1 >> 5) & 0xf); } } } /* level1 page table, each entry for 1MB memory. */ -static volatile unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +static volatile unsigned long MMUTable[4 * 1024] __attribute__((aligned(16 * 1024))); void SetMMUTable(u32 vaddrStart, - u32 vaddrEnd, - u32 paddrStart, - u32 attr) + u32 vaddrEnd, + u32 paddrStart, + u32 attr) { volatile u32 *pTT; volatile int i, nSec; - pTT = (u32 *)MMUTable + (vaddrStart >> 20); + pTT = (u32 *)MMUTable + (vaddrStart >> 20); nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); - for(i = 0; i <= nSec; i++) + for (i = 0; i <= nSec; i++) { *pTT = attr | (((paddrStart >> 20) + i) << 20); pTT++; @@ -146,16 +148,20 @@ unsigned long SetDomainReg(unsigned long domain_val) { unsigned long old_domain; - asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); - asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + asm volatile("mrc p15, 0, %0, c3, c0\n" + : "=r"(old_domain)); + asm volatile("mcr p15, 0, %0, c3, c0\n" + : + : "r"(domain_val) + : "memory"); return old_domain; } -void InitMMUTable(struct mem_desc *mdesc, u32 size) +void InitMMUTable(struct mem_desc *mdesc, u32 size) { /* set page table */ - for(; size > 0; size--) + for (; size > 0; size--) { SetMMUTable(mdesc->vaddr_start, mdesc->vaddr_end, mdesc->paddr_start, mdesc->attr); @@ -169,20 +175,25 @@ void InitMMU(void) cpu_mmu_disable(); /*rt_hw_cpu_dump_page_table(MMUTable);*/ SetDomainReg(0x55555555); + OutByte('7'); cpu_tlb_set(MMUTable); + OutByte('8'); cpu_mmu_enable(); #endif } void InitCache(void) { + OutByte('2'); + OutByte('3'); cpu_dcache_clean_flush(); cpu_icache_flush(); cpu_dcache_disable(); cpu_icache_disable(); - + OutByte('3'); InitMMU(); - + OutByte('4'); cpu_icache_enable(); cpu_dcache_enable(); + OutByte('5'); } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/parameters.c b/bsp/arch/armv8/aarch32/platform/ft2004/parameters.c index be7723741..c4c0cb72f 100644 --- a/bsp/arch/armv8/aarch32/platform/ft2004/parameters.c +++ b/bsp/arch/armv8/aarch32/platform/ft2004/parameters.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 15:13:47 - * @LastEditTime: 2021-06-29 15:14:59 + * @LastEditTime: 2021-07-09 14:29:06 * @Description:  This files is for * * @Modify History: @@ -15,7 +15,7 @@ #include "parameters.h" #include "mmu.h" -#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWT | DESC_SEC) +#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC) struct mem_desc platform_mem_desc[] = { {0x80000000, diff --git a/bsp/common/trap.c b/bsp/common/trap.c index 8e36afa1d..8b80048ea 100644 --- a/bsp/common/trap.c +++ b/bsp/common/trap.c @@ -16,7 +16,7 @@ #include "exception.h" #include -#ifndef CONFIG_TARGET_ARMV8_AARCH32 +#ifdef CONFIG_TARGET_ARMV8_AARCH64 #define aarch64_read_sysreg(reg) ( \ { \ uint64_t val; \ @@ -187,6 +187,38 @@ void SerrHandle(exception_frame *regs) } #endif +#ifdef CONFIG_TARGET_ARMV8_AARCH32 +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void ShowExceptionRegisters(struct ExceptionStack *regs) +{ + printf("Execption:\r\n"); + printf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\r\n", regs->r0, regs->r1, regs->r2, regs->r3); + printf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\r\n", regs->r4, regs->r5, regs->r6, regs->r7); + printf("r08:0x%08x r09:0x%08x r10:0x%08x\r\n", regs->r8, regs->r9, regs->r10); + printf("fp :0x%08x ip :0x%08x\r\n", regs->fp, regs->ip); + printf("sp :0x%08x lr :0x%08x pc :0x%08x\r\n", regs->sp, regs->lr, regs->pc); + printf("cpsr:0x%08x\r\n", regs->cpsr); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void PrfTrap(struct ExceptionStack *regs) +{ + printf("prefetch abort:\r\n"); + ShowExceptionRegisters(regs); +} +#endif + #define GIC_ACK_INTID_MASK 0x000003ff int InterruptGetIrq(void); diff --git a/bsp/common/trap.h b/bsp/common/trap.h index 187252303..ae9e4f6cd 100644 --- a/bsp/common/trap.h +++ b/bsp/common/trap.h @@ -16,7 +16,7 @@ #include "sdkconfig.h" #include "exception.h" -#ifndef CONFIG_TARGET_ARMV8_AARCH32 +#ifdef CONFIG_TARGET_ARMV8_AARCH64 void ShowRegister(exception_frame *regs); /** @@ -30,6 +30,29 @@ void ShowRegister(exception_frame *regs); void SerrHandle(exception_frame *regs); #endif +#ifdef CONFIG_TARGET_ARMV8_AARCH32 +struct ExceptionStack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; +#endif + int InterruptGetIrq(void); void InterruptAck(int fiq_irq); diff --git a/lib/libc/retarget.c b/lib/libc/retarget.c index e23f0f40b..80d2d94e4 100644 --- a/lib/libc/retarget.c +++ b/lib/libc/retarget.c @@ -21,13 +21,15 @@ void initialise_monitor_handles() { /* 关闭行缓冲 */ setvbuf(stdout, NULL, _IONBF, 0); + // OutByte('a'); setvbuf(stdin, NULL, _IONBF, 0); + // OutByte('b'); } int _read(int file, char *ptr, int len) { int i; - + OutByte('h'); for (i = 0; i < len; ++i) { ptr[i] = GetByte(); @@ -37,7 +39,9 @@ int _read(int file, char *ptr, int len) int _write(int file, char *ptr, int len) { + int i; + OutByte('h'); for (i = 0; i < len; ++i) { if (ptr[i] == '\n') diff --git a/make/complier.mk b/make/complier.mk index ad6dff3a6..d0dfcd821 100644 --- a/make/complier.mk +++ b/make/complier.mk @@ -20,7 +20,7 @@ OPT_LEVEL ?= 0 # Other switches the user should not normally need to change: ifdef CONFIG_TARGET_ARMV8_AARCH32 - ARCH = armv8-a + ARCH = armv7-a endif ifdef CONFIG_TARGET_ARMV8_AARCH64 @@ -106,12 +106,10 @@ ASFLAGS = $(CFLAGS) LIBC ?= LIBPATH ?= ifdef CONFIG_TARGET_ARMV8_AARCH32 - LIBC += $(CROSS_PATH)/arm-none-eabi/lib/libc_nano.a - LIBC += $(CROSS_PATH)/arm-none-eabi/lib/libnosys.a - LIBPATH += $(CROSS_PATH)/lib/gcc/arm-none-eabi/10.2.1 + LIBPATH += $(CROSS_PATH)/arm-none-eabi/lib/thumb/v7/nofp # support float and div, turn on by default for aarch64 - ASFLAGS := $(ASFLAGS) -mfpu=vfpv3-fp16 -ftree-vectorize -mfloat-abi=softfp -ffast-math -fsingle-precision-constant -march=armv8-a - CFLAGS := $(CFLAGS) -mfpu=vfpv3-fp16 -mfloat-abi=softfp -march=armv8-a + ASFLAGS := $(ASFLAGS) -mfpu=vfpv3-fp16 -ftree-vectorize -mfloat-abi=softfp -ffast-math -fsingle-precision-constant -march=$(ARCH) + CFLAGS := $(CFLAGS) -mfpu=vfpv3-fp16 -mfloat-abi=softfp -march=$(ARCH) endif ifdef CONFIG_TARGET_ARMV8_AARCH64 @@ -120,7 +118,9 @@ endif LDFLAGS = -T$(LDSNAME) -Wl,--build-id=none ifdef CONFIG_USE_LIBC -# LDFLAGS += -lgcc -L $(LIBPATH) +ifdef CONFIG_TARGET_ARMV8_AARCH32 +LDFLAGS += -lgcc -L $(LIBPATH) +endif else LDFLAGS += -nostdlib -nostartfiles endif diff --git a/make/complier.mk_o b/make/complier.mk_o new file mode 100644 index 000000000..ad6dff3a6 --- /dev/null +++ b/make/complier.mk_o @@ -0,0 +1,189 @@ +# Copyright (C) ARM Limited, 2014-2016. All rights reserved. +# +# This example is intended to be built with Linaro bare-metal GCC +# +# Environment variables for build options that the user might wish to change +# +# Variable Example Value +# ---------- ------------- +# APP myapp.axf +# QUIET @ for terse output, or leave blank for detailed output +# OPT_LEVEL 0, 1, 2 or 3 +# DEFINES -D MYDEFINE + +#include $(SDK_ROOT)/make/preconfig.mk + +APP ?= $(CONFIG_TARGET_NAME) + +QUIET ?=@ +OPT_LEVEL ?= 0 + +# Other switches the user should not normally need to change: +ifdef CONFIG_TARGET_ARMV8_AARCH32 + ARCH = armv8-a +endif + +ifdef CONFIG_TARGET_ARMV8_AARCH64 + ARCH = armv8-a +endif + +ifdef CONFIG_TARGET_ARMV7 + ARCH = armv7-a +endif + + +DEBUG_FLAGS = -g + +CPPFLAGS_EXTRA := + +ifndef SDK_ROOT +$(error error, please set SDK_ROOT first!!) +endif + +ifeq ($(QUIET),@) +PROGRESS = @echo Compiling $<... +endif + +ifdef CONFIG_TARGET_ARMV8_AARCH64 + ifdef CONFIG_USE_EXT_COMPILER + CROSS_PATH := $(CONFIG_EXT_COMPILER_PREFIX) + else + CROSS_PATH := $(AARCH64_CROSS_PATH) + endif +CROSS_COMPILE := $(CROSS_PATH)/bin/aarch64-none-elf- +endif + +ifdef CONFIG_TARGET_ARMV8_AARCH32 + ifdef CONFIG_USE_EXT_COMPILER + CROSS_PATH := $(CONFIG_EXT_COMPILER_PREFIX) + else + CROSS_PATH := $(AARCH32_CROSS_PATH) + endif +CROSS_COMPILE := $(CROSS_PATH)/bin/arm-none-eabi- +endif + +CC = $(CROSS_COMPILE)gcc +OC = $(CROSS_COMPILE)objcopy +OD = $(CROSS_COMPILE)objdump +LD = $(CROSS_COMPILE)ld + +# Commit hash from git +COMMIT=$(shell git rev-parse --short HEAD) +PACK_DATA=$(shell date +'%m%d_%H%M') +INC_DIR ?= # include 目录 +SRC_DIR ?= # 源文件目录 +EXCL_SRC ?= # 在源文件目录中不编译 +#OUTPUT_DIR ?= build # 输出目录 +$(shell if [ ! -e $(OUTPUT_DIR) ];then mkdir -p $(OUTPUT_DIR); fi) + +# include componet makefile +include $(SDK_ROOT)/bsp/bsp.mk +include $(SDK_ROOT)/lib/lib.mk +include $(SDK_ROOT)/make/ld.mk + +INC_DIR := $(INC_DIR) $(USR_INC_DIR) +INCLUDES := $(patsubst %, -I %, $(INC_DIR)) + +define EOL = + +endef + +ifeq ($(OS),Windows_NT) +RM_FILES = $(foreach file,$(1),if exist $(file) del /q $(file)$(EOL)) +RM_D +IRS = $(foreach dir,$(1),if exist $(dir) rmdir /s /q $(dir)$(EOL)) +else +RM_FILES = $(foreach file,$(1),rm -f $(file)$(EOL)) +RM_DIRS = $(foreach dir,$(1),rm -rf $(dir)$(EOL)) +endif + +DEPEND_FLAGS = -MD -MF $@.d + +CPPFLAGS = $(DEFINES) $(INCLUDES) $(DEPEND_FLAGS) $(CPPFLAGS_EXTRA) +CFLAGS = $(DEBUG_FLAGS) -DGUEST -ffreestanding -Wextra -g -O$(OPT_LEVEL) +ASFLAGS = $(CFLAGS) + +LIBC ?= +LIBPATH ?= +ifdef CONFIG_TARGET_ARMV8_AARCH32 + LIBC += $(CROSS_PATH)/arm-none-eabi/lib/libc_nano.a + LIBC += $(CROSS_PATH)/arm-none-eabi/lib/libnosys.a + LIBPATH += $(CROSS_PATH)/lib/gcc/arm-none-eabi/10.2.1 +# support float and div, turn on by default for aarch64 + ASFLAGS := $(ASFLAGS) -mfpu=vfpv3-fp16 -ftree-vectorize -mfloat-abi=softfp -ffast-math -fsingle-precision-constant -march=armv8-a + CFLAGS := $(CFLAGS) -mfpu=vfpv3-fp16 -mfloat-abi=softfp -march=armv8-a +endif + +ifdef CONFIG_TARGET_ARMV8_AARCH64 + CROSS_PATH := $(AARCH64_CROSS_PATH) +endif + +LDFLAGS = -T$(LDSNAME) -Wl,--build-id=none +ifdef CONFIG_USE_LIBC +# LDFLAGS += -lgcc -L $(LIBPATH) +else +LDFLAGS += -nostdlib -nostartfiles +endif + +TARGET_ARCH = -march=$(ARCH) + +#mkdir 创建输出文件目录 +X_OUTPUT_DIRS := $(patsubst %, $(OUTPUT_DIR)/%, $(SRC_DIR)) + +SRC_DIR := $(SRC_DIR) $(USR_SRC_DIR) + +APP_C_SRC := $(foreach dir, $(SRC_DIR), $(wildcard $(dir)/*.c)) +APP_S_SRC := $(foreach dir, $(SRC_DIR), $(wildcard $(dir)/*.S)) + +OBJ_FILES := $(patsubst %, $(OUTPUT_DIR)/%, $(APP_S_SRC:.S=.o)) \ + $(patsubst %, $(OUTPUT_DIR)/%, $(APP_C_SRC:.c=.o)) + +EXCL_OBJS ?= $(patsubst %, $(OUTPUT_DIR)/%, $(EXCL_SRC:.c=.o)) +OBJ_FILES := $(filter-out $(EXCL_OBJS), $(OBJ_FILES)) +OBJ_FILES += $(LIBC) + +DEP_FILES := $(OBJ_FILES:%=%.d) + +ifdef CONFIG_DUMMY_COMPILE + DO_ECHO = @echo +else + DO_ECHO = +endif + +.phony: all clean rebuild +all: $(APP) + +$(APP): $(OBJ_FILES) $(LDSNAME) + @echo Linking $@.elf + @echo Dumping $@.map + + $(DO_ECHO) $(QUIET) $(CC) $(TARGET_ARCH) $(LDFLAGS) --output $@.elf -Wl,-Map=$@.map $(OBJ_FILES) -lm + @echo Objcopying $@.bin + $(DO_ECHO) $(QUIET) $(OC) -v -O binary $@.elf $@.bin + $(DO_ECHO) $(QUIET) $(OD) -D $@.elf > $@.dis + @echo Done. + +clean: + $(call RM_DIRS,$(OUTPUT_DIR)) + $(call RM_FILES,*.elf) + $(call RM_FILES,*.bin) + $(call RM_FILES,*.dis) + $(call RM_FILES,*.map) + $(call RM_FILES,*.tar.gz) + +$(X_OUTPUT_DIRS): + @mkdir -p $@ + +$(OUTPUT_DIR)/%.o : %.S | $(X_OUTPUT_DIRS) + $(PROGRESS) + $(QUIET) $(CC) -c $(TARGET_ARCH) $(CPPFLAGS) $(ASFLAGS) -o $@ $< + +$(OUTPUT_DIR)/%.o : %.c | $(X_OUTPUT_DIRS) + $(PROGRESS) + $(QUIET) $(CC) -c $(TARGET_ARCH) $(CPPFLAGS) $(CFLAGS) -o $@ $< + + +# Make sure everything is rebuilt if this makefile is changed +$(OBJ_FILES) $(APP): makefile + +-include $(DEP_FILES) diff --git a/make/ld/e2000_ft2004_aarch32_ram.ld b/make/ld/e2000_ft2004_aarch32_ram.ld index 033a82e25..39c5463b6 100644 --- a/make/ld/e2000_ft2004_aarch32_ram.ld +++ b/make/ld/e2000_ft2004_aarch32_ram.ld @@ -34,9 +34,62 @@ SECTIONS *(.ARM.exidx* .gnu.linkonce.armexidx.*) /* This is used by the startup in order to initialize the .data secion */ } > ROM + + .rodata : + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } > ROM + + .init : + { + KEEP (*(SORT_NONE(.init))) + }> ROM + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + }> ROM + + .eh_frame : + { + KEEP (*(.eh_frame)) + }> ROM + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + }> ROM + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + }> ROM + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array )) + PROVIDE_HIDDEN (__fini_array_end = .); + }> ROM + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + . = ALIGN(16); + _rom_end = .; + }> ROM + + . = ALIGN(4096); /* align to page size */ _text_end = .; - + /* data segment, contains data that can be modified by the program at run-time, global and static variables that have a non-zero initial value will normally go here */ .data : AT(_text_end){ @@ -48,10 +101,11 @@ SECTIONS /* unitialized data segment, variables explicitly initialized with zero to BSS */ .bss : { - _bss_start = .; + __bss_start__ = .; + _bss_start = __bss_start__; *(.bss) - . = ALIGN(4096); /* align to page size */ - _bss_end = .; + __bss_end__ = .; + _bss_end = __bss_end__; } > RAM .heap : @@ -61,19 +115,26 @@ SECTIONS PROVIDE(end = .); __HeapBase = .; . += HEAP_SIZE; + . = ALIGN(4096); /* align to page size */ __HeapLimit = .; __heap_limit = .; /* Add for _sbrk */ } > RAM - _fiq_stack_start = ADDR(.bss) + SIZEOF(.bss); + _fiq_stack_start = ADDR(.heap) + SIZEOF(.heap); _fiq_stack_end = _fiq_stack_start + 0x1000; /* 64 KB */ _irq_stack_start = _fiq_stack_end; _irq_stack_end = _irq_stack_start + 0x1000; /* 64 KB */ - _stack_start = _irq_stack_end; - _stack_end = _stack_start + 0x1000; /* 64 KB */ + _sys_stack_start = _irq_stack_end; + _sys_stack_end = _sys_stack_start + 0x1000; /* 64 KB */ + + /* put svc at end and start up with SVC mode */ + _svc_stack_start = _sys_stack_end; + _svc_stack_end = _svc_stack_start + 0x1000; /* 64 KB */ _irq_stack_size = _irq_stack_end - _irq_stack_start; _fiq_stack_size = _fiq_stack_end - _fiq_stack_start; + _sys_stack_size = _sys_stack_end - _sys_stack_start; + _svc_stack_size = _svc_stack_end - _svc_stack_start; } -- Gitee From 122d134005ebe79bd0206e09c5be3bbfa67ab155 Mon Sep 17 00:00:00 2001 From: huanghe Date: Mon, 12 Jul 2021 11:42:38 +0800 Subject: [PATCH 06/12] =?UTF-8?q?=E5=AE=8C=E6=88=90aarch32=20libc=20?= =?UTF-8?q?=E7=9A=84=E4=BD=BF=E7=94=A8=E5=8A=9F=E8=83=BD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- baremetal/example/aarch32_hello_world/main.c | 8 +- baremetal/example/aarch32_math_test/Kconfig | 19 ++++ baremetal/example/aarch32_math_test/Makefile | 12 +++ baremetal/example/aarch32_math_test/main.c | 49 ++++++++++ baremetal/example/aarch32_math_test/sdkconfig | 97 ++++++++++++++++++ .../example/aarch32_math_test/sdkconfig.h | 15 +++ .../example/aarch32_math_test/sdkconfig.old | 98 +++++++++++++++++++ bsp/arch/armv8/aarch32/mmu.c | 9 +- export.sh | 4 +- lib/libc/retarget.c | 2 - make/complier.mk | 6 +- 11 files changed, 297 insertions(+), 22 deletions(-) create mode 100644 baremetal/example/aarch32_math_test/Kconfig create mode 100644 baremetal/example/aarch32_math_test/Makefile create mode 100644 baremetal/example/aarch32_math_test/main.c create mode 100644 baremetal/example/aarch32_math_test/sdkconfig create mode 100644 baremetal/example/aarch32_math_test/sdkconfig.h create mode 100644 baremetal/example/aarch32_math_test/sdkconfig.old diff --git a/baremetal/example/aarch32_hello_world/main.c b/baremetal/example/aarch32_hello_world/main.c index 186830fc7..117be3f6b 100644 --- a/baremetal/example/aarch32_hello_world/main.c +++ b/baremetal/example/aarch32_hello_world/main.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-07-01 17:12:55 - * @LastEditTime: 2021-07-09 17:58:31 + * @LastEditTime: 2021-07-12 10:13:25 * @Description:  This files is for * * @Modify History: @@ -20,13 +20,7 @@ int main(void) while (1) { /* code */ - OutByte('1'); printf("hello world \r\n"); fsleep_seconds(10); } } - -void test_pos(void) -{ - OutByte('1'); -} \ No newline at end of file diff --git a/baremetal/example/aarch32_math_test/Kconfig b/baremetal/example/aarch32_math_test/Kconfig new file mode 100644 index 000000000..cfd89b186 --- /dev/null +++ b/baremetal/example/aarch32_math_test/Kconfig @@ -0,0 +1,19 @@ +# +# For a description of the syntax of this configuration file, +# see tools/kconfiglib/kconfig-language.txt. +# + +mainmenu "Phytium Baremetal Configuration" + +menu "Project Configuration" + menu "FT2000-4 AARCH32 Baremetal Configuration" + + config TARGET_NAME + string "Build Target Name" + default "ft2004_baremetal" + help + Build Target name for the demo + endmenu +endmenu + +source "$(SDK_ROOT)/Kconfig" \ No newline at end of file diff --git a/baremetal/example/aarch32_math_test/Makefile b/baremetal/example/aarch32_math_test/Makefile new file mode 100644 index 000000000..1e9def789 --- /dev/null +++ b/baremetal/example/aarch32_math_test/Makefile @@ -0,0 +1,12 @@ +export PROJECT_DIR ?= . + +# prepare output dir and start make +include $(SDK_ROOT)/make/build_baremetal.mk + +rebuild: + make clean + make + +boot: + make + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ \ No newline at end of file diff --git a/baremetal/example/aarch32_math_test/main.c b/baremetal/example/aarch32_math_test/main.c new file mode 100644 index 000000000..a8bdafc77 --- /dev/null +++ b/baremetal/example/aarch32_math_test/main.c @@ -0,0 +1,49 @@ +/* + * @[H]: Copyright (C) 2014-2021 Phytium Technology.  All rights reserved. + * + *  Permission is hereby granted, free of charge, to any person obtaining a copy + *  of this software and associated documentation files (the "Software"), to deal + *  in the Software without restriction, including without limitation the rights + *  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + *  copies of the Software, and to permit persons to whom the Software is + *  furnished to do so, subject to the following conditions: + * + *  The above copyright notice and this permission notice shall be included in + *  all copies or substantial portions of the Software. + * + *  Use of the Software is limited solely to applications: + *  (a) running on a Phytium device, or + *  (b) that interact with a Phytium device through a bus or interconnect. + * + *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + *  PHYTIUM  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + *  WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + *  OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + *  SOFTWARE. + * + *  Except as contained in this notice, the name of the Phytium shall not be used + *  in advertising or otherwise to promote the sale, use or other dealings in + *  this Software without prior written authorization from Phytium.  + * + * @Date: 2021-07-12 10:27:46 + * @LastEditTime: 2021-07-12 10:27:46 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include + +void main(void) +{ + float a = 0; + float b = 0; + float c; + + c = 20.0 / 0.0; + + printf("a %f, b %f, c %f\n", a, b, c); +} \ No newline at end of file diff --git a/baremetal/example/aarch32_math_test/sdkconfig b/baremetal/example/aarch32_math_test/sdkconfig new file mode 100644 index 000000000..3f8d35b31 --- /dev/null +++ b/baremetal/example/aarch32_math_test/sdkconfig @@ -0,0 +1,97 @@ + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration diff --git a/baremetal/example/aarch32_math_test/sdkconfig.h b/baremetal/example/aarch32_math_test/sdkconfig.h new file mode 100644 index 000000000..be78f3ff5 --- /dev/null +++ b/baremetal/example/aarch32_math_test/sdkconfig.h @@ -0,0 +1,15 @@ +#define CONFIG_TARGET_NAME "ft2004_baremetal" +#define CONFIG_TARGET_ARMV8_AARCH32 1 +#define CONFIG_TARGET_F2000_4 1 +#define CONFIG_ENVI_UBUNTU_20_04 1 +#define CONFIG_COMPILER_NO_STD_STARUP 1 +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 +#define CONFIG_LOG_ERROR 1 +#define CONFIG_USE_GIC 1 +#define CONFIG_EBABLE_GICV3 1 +#define CONFIG_USE_USART 1 +#define CONFIG_ENABLE_Pl011_UART 1 +#define CONFIG_USE_CACHE 1 +#define CONFIG_USE_L3CACHE 1 +#define CONFIG_USE_MMU 1 +#define CONFIG_USE_LIBC 1 diff --git a/baremetal/example/aarch32_math_test/sdkconfig.old b/baremetal/example/aarch32_math_test/sdkconfig.old new file mode 100644 index 000000000..b82fce4cb --- /dev/null +++ b/baremetal/example/aarch32_math_test/sdkconfig.old @@ -0,0 +1,98 @@ + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +CONFIG_USE_EXT_COMPILER=y +CONFIG_EXT_COMPILER_PREFIX="/usr" +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration diff --git a/bsp/arch/armv8/aarch32/mmu.c b/bsp/arch/armv8/aarch32/mmu.c index 730799000..75e09d367 100644 --- a/bsp/arch/armv8/aarch32/mmu.c +++ b/bsp/arch/armv8/aarch32/mmu.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 09:20:24 - * @LastEditTime: 2021-07-09 14:29:18 + * @LastEditTime: 2021-07-12 10:16:10 * @Description:  This files is for * * @Modify History: @@ -175,25 +175,18 @@ void InitMMU(void) cpu_mmu_disable(); /*rt_hw_cpu_dump_page_table(MMUTable);*/ SetDomainReg(0x55555555); - OutByte('7'); cpu_tlb_set(MMUTable); - OutByte('8'); cpu_mmu_enable(); #endif } void InitCache(void) { - OutByte('2'); - OutByte('3'); cpu_dcache_clean_flush(); cpu_icache_flush(); cpu_dcache_disable(); cpu_icache_disable(); - OutByte('3'); InitMMU(); - OutByte('4'); cpu_icache_enable(); cpu_dcache_enable(); - OutByte('5'); } \ No newline at end of file diff --git a/export.sh b/export.sh index f6fa6dc67..0dc6083c1 100644 --- a/export.sh +++ b/export.sh @@ -5,7 +5,7 @@ # SPDX-License-Identifier: Apache-2.0. # # @Date: 2021-06-30 17:24:45 - # @LastEditTime: 2021-07-01 19:03:48 + # @LastEditTime: 2021-07-12 11:35:59 # @Description:  This files is for  # # @Modify History: @@ -59,7 +59,7 @@ AARCH32_CC_PACK=gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz AARCH64_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.2-2020.11/binrel/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz AARCH64_CC_PACK=gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz INSTALL_PATH=$SDK_ROOT/tools -export AARCH32_CROSS_PATH=$INSTALL_PATH/gcc-arm-none-eabi-10-2020-q4-major +export AARCH32_CROSS_PATH=$INSTALL_PATH/gcc-arm-none-eabi-phytium-major export AARCH64_CROSS_PATH=$INSTALL_PATH/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf if [ $OFFLINE_INSTALL -ne 1 ]; then diff --git a/lib/libc/retarget.c b/lib/libc/retarget.c index 80d2d94e4..88c0cfce1 100644 --- a/lib/libc/retarget.c +++ b/lib/libc/retarget.c @@ -29,7 +29,6 @@ void initialise_monitor_handles() int _read(int file, char *ptr, int len) { int i; - OutByte('h'); for (i = 0; i < len; ++i) { ptr[i] = GetByte(); @@ -41,7 +40,6 @@ int _write(int file, char *ptr, int len) { int i; - OutByte('h'); for (i = 0; i < len; ++i) { if (ptr[i] == '\n') diff --git a/make/complier.mk b/make/complier.mk index d0dfcd821..01e203059 100644 --- a/make/complier.mk +++ b/make/complier.mk @@ -20,7 +20,7 @@ OPT_LEVEL ?= 0 # Other switches the user should not normally need to change: ifdef CONFIG_TARGET_ARMV8_AARCH32 - ARCH = armv7-a + ARCH = armv8-a endif ifdef CONFIG_TARGET_ARMV8_AARCH64 @@ -108,8 +108,8 @@ LIBPATH ?= ifdef CONFIG_TARGET_ARMV8_AARCH32 LIBPATH += $(CROSS_PATH)/arm-none-eabi/lib/thumb/v7/nofp # support float and div, turn on by default for aarch64 - ASFLAGS := $(ASFLAGS) -mfpu=vfpv3-fp16 -ftree-vectorize -mfloat-abi=softfp -ffast-math -fsingle-precision-constant -march=$(ARCH) - CFLAGS := $(CFLAGS) -mfpu=vfpv3-fp16 -mfloat-abi=softfp -march=$(ARCH) + ASFLAGS := $(ASFLAGS) -mfpu=vfpv3-fp16 -ftree-vectorize -mfloat-abi=soft -ffast-math -fsingle-precision-constant -march=$(ARCH) + CFLAGS := $(CFLAGS) -mfpu=vfpv3-fp16 -mfloat-abi=soft -march=$(ARCH) endif ifdef CONFIG_TARGET_ARMV8_AARCH64 -- Gitee From 6cae50e9f88cfcf53e177e9b668df5608a456757 Mon Sep 17 00:00:00 2001 From: huanghe Date: Mon, 12 Jul 2021 14:06:14 +0800 Subject: [PATCH 07/12] =?UTF-8?q?v0.0.4=20=E6=8F=90=E4=BA=A4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Kconfig | 18 +- README.md | 215 ++++---- .../example/aarch32_cache_mmu_wr/test_cache.c | 8 +- baremetal/example/aarch32_uart_irq/Makefile | 2 +- bsp/arch/armv8/aarch32/gcc/exception_debug.c | 14 + bsp/common/Kconfig | 7 +- bsp/common/ft_debug.h | 27 +- bsp/common/interrupt.c | 9 +- doc/ChangeLog.md | 35 +- install.sh | 106 ++++ lib/libc/retarget.c | 4 +- make/buildinfo.mk | 8 + make/complier.mk | 4 +- make/complier.mk_o | 189 ------- make/ld.mk | 4 + make/preconfig.mk | 1 + third-party/Kconfig | 10 + third-party/coremark/README.md | 474 +++++++++++++++++ third-party/coremark/core_list_join.c | 495 ++++++++++++++++++ third-party/coremark/core_main.c | 369 +++++++++++++ third-party/coremark/core_matrix.c | 308 +++++++++++ third-party/coremark/core_portme.c | 143 +++++ third-party/coremark/core_portme.h | 221 ++++++++ third-party/coremark/core_state.c | 277 ++++++++++ third-party/coremark/core_util.c | 210 ++++++++ third-party/coremark/coremark.c | 25 + third-party/coremark/coremark.h | 174 ++++++ third-party/coremark/coremark_entry.h | 19 + third-party/third-party.mk | 6 + 29 files changed, 3043 insertions(+), 339 deletions(-) create mode 100644 install.sh delete mode 100644 make/complier.mk_o create mode 100644 third-party/Kconfig create mode 100644 third-party/coremark/README.md create mode 100644 third-party/coremark/core_list_join.c create mode 100644 third-party/coremark/core_main.c create mode 100644 third-party/coremark/core_matrix.c create mode 100644 third-party/coremark/core_portme.c create mode 100644 third-party/coremark/core_portme.h create mode 100644 third-party/coremark/core_state.c create mode 100644 third-party/coremark/core_util.c create mode 100644 third-party/coremark/coremark.c create mode 100644 third-party/coremark/coremark.h create mode 100644 third-party/coremark/coremark_entry.h create mode 100644 third-party/third-party.mk diff --git a/Kconfig b/Kconfig index 0c29ba6ef..83a7c92d9 100644 --- a/Kconfig +++ b/Kconfig @@ -63,6 +63,21 @@ string "" default "arm-none-eabi-" if TARGET_ARMV8_AARCH32 default "aarch64-none-elf-" if TARGET_ARMV8_AARCH64 + + choice USE_FLOAT + prompt "Add Float Support" + depends on USE_LIBC + default USE_SOFT_FLOAT + help + Select Soft/Hard Float. + + config USE_SOFT_FLOAT + bool + prompt "Soft Float" + config USE_HARD_FLOAT + bool + prompt "Hard Float" + endchoice #USE_FLOAT endmenu source "$(SDK_ROOT)/make/ld/Kconfig" @@ -70,4 +85,5 @@ # add all kconfig source files, but specify their depends source "$(SDK_ROOT)/bsp/Kconfig" -source "$(SDK_ROOT)/lib/Kconfig" \ No newline at end of file +source "$(SDK_ROOT)/lib/Kconfig" +source "$(SDK_ROOT)/third-party/Kconfig" \ No newline at end of file diff --git a/README.md b/README.md index 13e5d5388..9a73a87b4 100644 --- a/README.md +++ b/README.md @@ -1,17 +1,3 @@ - - # Phytium-Standalone-SDK ## 1. 介绍 @@ -19,146 +5,123 @@ ## 2. Ubuntu 20.04 x86_64环境下使用Standalone SDK -### 2.1. 配置SDK +### 2.1 获取SDK源代码 -#### 2.1.1. 下载SDK源代码 +- 将SDK源代码拉取/解压(e.g. ~/standalone-sdk) -- 通过Gitee拉取源代码 -``` -$ git clone https://gitee.com/zhugengyu/phytium-mangosteen-sdk.git ./ft_sdk -$ cd ./ft_sdk -``` +### 2.2 完成安装注册 -#### 2.1.2 选择在线方式安装SDK +#### 2.2.1 选择在线方式安装SDK（需要联网） -- 选择在线方式安装Standalone SDK在~/ft_sdk +- 安装过程中会下载编译构建工具 ``` -$ ./export.sh -online - +$ ./install.sh -online ``` -![download cc](https://images.gitee.com/uploads/images/2021/0701/190528_d93eb2f0_8736513.png "download cc.png") -#### 2.1.3 选择离线方式安装SDK +![](https://images.gitee.com/uploads/images/2021/0709/144018_82e159a3_8736513.png "屏幕截图.png") + +#### 2.2.2 选择离线方式安装SDK -- 在ARM官网下载[AARCH32](https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz)和[AARCH64](https://developer.arm.com/-/media/Files/downloads/gnu-a/10.2-2020.11/binrel/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz)编译器 -- 将下载的编译器安装包放置在'~/ft_sdk/tools'路径下 -- 安装SDK开发环境，没有打印错误信息表示安装成功 +- 下载[AARCH32](https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz)和[AARCH64](https://developer.arm.com/-/media/Files/downloads/gnu-a/10.2-2020.11/binrel/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz)编译器 +- 将下载的编译器安装包放置在`~/standalone-sdk/tools`路径下 ``` -$ ./export.sh -Please type in 'source ./export.sh' -Phytium Embedded SDK Setup Done!! -Install AARCH32 Compiler at /home/ubuntu/ft_sdk/tools/gcc-arm-none-eabi-10-2020-q4-major -Install AARCH64 Compiler at /home/ubuntu/ft_sdk/tools/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf -SDK Path is set as /home/ubuntu/ft_sdk/standalone-sdk-master +$ ./install.sh ``` -- **通过离线/在线方式完成安装后，关闭当前窗口或者运行以下命令，立即生效SDK环境变量** +#### 2.2.3 完成SDK安装注册 +- 通过离线/在线方式完成安装后，重启系统或者运行以下命令，立即生效SDK环境变量 ``` $ source ~/.profile ``` -### 2.2 快速使用例程 +### 2.3 新建一个baremetal应用工程 -#### 2.2.1 使用FT2000-4开发板，快速体验SDK ->ft_sdk/baremetal/example/aarch32_hello_world -- 编译例程hello_world +- 复制`~/standalone-sdk/example/template`目录，作为baremetal应用工程 -![compiling ft2004](https://images.gitee.com/uploads/images/2021/0701/192403_054be566_8736513.png "compiling ft2004.png") - -- 通过TFTP服务器下载到开发板上 - -![load-bin](https://images.gitee.com/uploads/images/2021/0701/192709_af8b1f88_8736513.png "load-bin.PNG") - -- 跳转启动例程 - -![boot os](https://images.gitee.com/uploads/images/2021/0701/192737_3bb24c8d_8736513.png "boot-os.PNG") +>`*` 表示可选文件 +``` +$ ls +Kconfig --> 应用工程配置menu文件 +Makefile --> makefile +inc --> 用户头文件* +main.c --> 包含main函数 +sdkconfig --> 配置输出 +sdkconfig.h --> 配置输出 +src --> 用户源文件* +``` -#### 2.2.2 没有开发板，可以通过模拟器体验一下SDK ->ft_sdk/baremetal/example/aarch32/qemu_debug -- 编译例程qemu_debug +- 编译应用工程, 生成*.bin文件用于下载到开发板 ``` $ make +$ ls +template.bin --> 二进制文件 +template.dis --> 反汇编文件 +template.elf --> ELF文件 +template.map --> 内存布局文件 ``` -![make qemu example](https://images.gitee.com/uploads/images/2021/0701/191952_9eaf3c22_8736513.png "make qemu example.png") +![输入图片说明](https://images.gitee.com/uploads/images/2021/0709/141655_f20b6d98_8736513.png "屏幕截图.png") -- 运行例程qemu_debug -``` -$ make run -``` -![run qemu](https://images.gitee.com/uploads/images/2021/0701/192204_eb73c296_8736513.png "run qemu.png") +### 2.4 快速使用例程 -#### 2.2.3 新建Baremetal应用工程 +>~/standalone-sdk/example/aarch32_hello_world -- 复制例程hello_world -- 在工程目录下添加源文件 -- 通过'make menuconfig'修改配置 -![menuconfig](https://images.gitee.com/uploads/images/2021/0702/102317_ff00742c_8736513.png "menuconfig.png") +![输入图片说明](https://images.gitee.com/uploads/images/2021/0709/145025_398f6501_8736513.png "屏幕截图.png") -``` -Project Configuration --> 当前工程的私有配置 -Target Setting --> 配置目标硬件平台 -Building Option --> 配置编译开发环境 -Board Configuration --> 配置开发板组件 -Library Configuration --> 配置依赖库 -``` -- 通过'make info'观察构建信息 -``` -$make info --> 查看交叉编译器的信号，编译输出路径，SDK根目录等信息 -$make info-srcs --> 查看编译过程中用到的源文件 -$make info-incs --> 查看编译过程中引用的目录 -$make info-flags --> 查看编译过程中的flags -``` -- 通过'make'完成编译构建 +## 3. SDK源代码结构 -## 3. Standalone源码结构 ``` . -├── Kconfig --> 顶层配置选项定义 -├── LICENSE -├── README.en.md +├── Kconfig --> 配置定义 +├── LICENSE --> 版权声明 ├── README.md -├── baremetal -│   └── example --> 已经配置好的baremetal例程 -├── bsp --> 板级支持包 -│   ├── Kconfig -│   ├── arch --> 架构相关源码 armv7/a32/a64 -│   ├── bsp.mk -│   ├── common --> BSP 不同平台的共用源码 -│   └── drivers --> 各类驱动 -├── configs --> 各平台默认匹配文件 -│   ├── aarch32_defconfig -│   └── aarch64_defconfig +├── baremetal +│ └── example --> 裸机例程 +├── bsp --> 板级支持包 +│ ├── Kconfig +│ ├── arch +│ ├── bsp.mk +│ ├── common +│ └── drivers +├── configs --> 各板子启动用的默认配置 +│ ├── aarch32_defconfig +│ └── aarch64_defconfig ├── doc -│   ├── ChangeLog.md --> 版本变更日志 -│   ├── baremetal.dio -│   └── baremetal.png -├── export.sh --> SDK注册安装脚本 -├── lib -│   ├── Kconfig -│   ├── Kconfiglib -│   ├── lib.mk -│   ├── libc -│   └── nostdlib -├── make --> SDK共用Makefile -│   ├── build_baremetal.mk -│   ├── buildinfo.mk -│   ├── complier.mk -│   ├── ld -│   ├── ld.mk -│   ├── menuconfig.mk -│   ├── packsource.mk -│   └── preconfig.mk -├── scripts -│   ├── kill_qemu_instance.sh -│   └── mount2vxbox.sh -└── tools --> 必要的工具，编译器安装在这个路径下 +│ ├── ChangeLog.md +│ ├── baremetal.dio +│ ├── baremetal.png +│ └── checklist.md +├── install.sh --> 环境变量安装脚本 +├── lib --> 依赖库 +│ ├── Kconfig +│ ├── Kconfiglib +│ ├── lib.mk +│ ├── libc +│ └── nostdlib +├── make --> Makefile文件 +│ ├── build_baremetal.mk +│ ├── buildinfo.mk +│ ├── complier.mk +│ ├── ld +│ ├── ld.mk +│ ├── menuconfig.mk +│ ├── packsource.mk +│ └── preconfig.mk +├── scripts --> 相关脚本 +│ ├── diffdir.md +│ ├── diffdir.sh +│ ├── kill_qemu_instance.sh +│ ├── mount2vxbox.sh +│ ├── release_tag.sh +│ └── wsl_import_export.bat +├── third-party --> 第三方库 +│ ├── Kconfig +│ ├── coremark +│ └── third-party.mk +└── tools --> 编译构建相关工具 ├── README.md ├── gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf - ├── gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz - ├── gcc-arm-none-eabi-10-2020-q4-major --> SDK注册过程中下载安装 - └── gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz ``` ## 4. 驱动描述 @@ -168,11 +131,15 @@ $make info-flags --> 查看编译过程中的flags ## 6. 参考资源 - ARM Architecture Reference Manual - +- ARM Cortex-A Series Programmer’s Guide +- Programmer Guide for ARMv8-A +- ARM System Developers Guide Designing and Optimizing System Software - FT-2000／4 软件编程手册-V1.4 - -- Mastering the FreeRTOS Real Time Kernel-A Hands-On Tutorial Guide - +- Bare-metal programming for ARM —— A hands-on guide +- Using the GNU Compiler Collection +- Using ld, The GNU Linker +- Using as, The GNU Assembler +- Armv8-A memory model guide --- ## 7. 贡献方法 diff --git a/baremetal/example/aarch32_cache_mmu_wr/test_cache.c b/baremetal/example/aarch32_cache_mmu_wr/test_cache.c index 176ed31a3..79ba21d63 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/test_cache.c +++ b/baremetal/example/aarch32_cache_mmu_wr/test_cache.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 10:36:06 - * @LastEditTime: 2021-07-05 08:27:31 + * @LastEditTime: 2021-07-12 14:02:53 * @Description:  This files is for * * @Modify History: @@ -58,10 +58,4 @@ void CacheTest() DcacheOps(CACHE_INVALIDATE, (void *)Data, sizeof(Data)); FtDumpHexWord(Data, DATA_LENGTH); - - printf("start spin test \r\n "); - - SpinLock(); - - printf("spin is pass \r\n"); } \ No newline at end of file diff --git a/baremetal/example/aarch32_uart_irq/Makefile b/baremetal/example/aarch32_uart_irq/Makefile index 8ceecac5c..affd48252 100644 --- a/baremetal/example/aarch32_uart_irq/Makefile +++ b/baremetal/example/aarch32_uart_irq/Makefile @@ -8,4 +8,4 @@ rebuild: boot: make - @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ \ No newline at end of file + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/gcc/exception_debug.c b/bsp/arch/armv8/aarch32/gcc/exception_debug.c index af19667a8..a01d5fea4 100644 --- a/bsp/arch/armv8/aarch32/gcc/exception_debug.c +++ b/bsp/arch/armv8/aarch32/gcc/exception_debug.c @@ -16,6 +16,7 @@ #include "aarch32.h" //#define EXCEPTION_DEBUG_ON +#define NO_PRINTF void FiqDebug() { @@ -52,19 +53,32 @@ void DatDebug() #endif } +extern void OutByte(s8 byte); void TraceDebug() { +#ifdef NO_PRINTF + OutByte('0'); +#else printf("stub \r\n"); +#endif } void TraceDebug1() { +#ifdef NO_PRINTF + OutByte('1'); +#else printf("stub 1\r\n"); +#endif } void TraceDebug2() { +#ifdef NO_PRINTF + OutByte('2'); +#else printf("stub 1\r\n"); +#endif } void TraceSctrl() diff --git a/bsp/common/Kconfig b/bsp/common/Kconfig index e43d6c104..d074d8650 100644 --- a/bsp/common/Kconfig +++ b/bsp/common/Kconfig @@ -12,19 +12,16 @@ choice DEBUG_LOG_LEVEL config LOG_VERBOS bool "VERBOS" - select LOG_LEVEL_VERBOS config LOG_DEBUG bool "DEBUG" - select LOG_LEVEL_DEBUG config LOG_INFO bool "INFO" - select LOG_LEVEL_INFO config LOG_WARN bool "WARN" - select LOG_LEVEL_WARN config LOG_ERROR bool "ERROR" - select LOG_LEVEL_ERROR + config LOG_NONE + bool "NONE" endchoice # DEBUG_LOG_LEVEL diff --git a/bsp/common/ft_debug.h b/bsp/common/ft_debug.h index d63dfc4d2..0bfcfff0b 100644 --- a/bsp/common/ft_debug.h +++ b/bsp/common/ft_debug.h @@ -15,6 +15,7 @@ #ifndef BSP_COMMON_FT_DEBUG_H #define BSP_COMMON_FT_DEBUG_H #include +#include "sdkconfig.h" #include "ft_types.h" typedef enum @@ -43,8 +44,21 @@ typedef enum #define LOG_COLOR_D #define LOG_COLOR_V -#ifndef LOG_LOCAL_LEVEL -#define LOG_LOCAL_LEVEL FT_LOG_VERBOSE +/* select debug log level */ +#ifdef CONFIG_LOG_ERROR +#define LOG_LOCAL_LEVEL FT_LOG_ERROR +#endif + +#ifdef CONFIG_LOG_WARN +#define LOG_LOCAL_LEVEL FT_LOG_WARN +#endif + +#ifdef CONFIG_LOG_INFO +#define LOG_LOCAL_LEVEL FT_LOG_INFO +#endif + +#ifdef CONFIG_LOG_DEBUG +#define LOG_LOCAL_LEVEL FT_LOG_DEBUG #endif #define LOG_FORMAT(letter, format) LOG_COLOR_##letter " %s: " format LOG_RESET_COLOR "\r\n" @@ -65,11 +79,20 @@ typedef enum #define EARLY_LOGW(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_WARN, W, ##__VA_ARGS__) #define EARLY_LOGV(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_VERBOSE, W, ##__VA_ARGS__) +/* do not compile log if define CONFIG_LOG_NONE */ +#ifndef CONFIG_LOG_NONE #define FT_DEBUG_PRINT_I(TAG, format, ...) EARLY_LOGI(TAG, format, ##__VA_ARGS__) #define FT_DEBUG_PRINT_E(TAG, format, ...) EARLY_LOGE(TAG, format, ##__VA_ARGS__) #define FT_DEBUG_PRINT_D(TAG, format, ...) EARLY_LOGD(TAG, format, ##__VA_ARGS__) #define FT_DEBUG_PRINT_W(TAG, format, ...) EARLY_LOGW(TAG, format, ##__VA_ARGS__) #define FT_DEBUG_PRINT_V(TAG, format, ...) EARLY_LOGV(TAG, format, ##__VA_ARGS__) +#else +#define FT_DEBUG_PRINT_I(TAG, format, ...) +#define FT_DEBUG_PRINT_E(TAG, format, ...) +#define FT_DEBUG_PRINT_D(TAG, format, ...) +#define FT_DEBUG_PRINT_W(TAG, format, ...) +#define FT_DEBUG_PRINT_V(TAG, format, ...) +#endif #define FT_RAW_PRINTF(format, ...) PORT_KPRINTF(format, ##__VA_ARGS__) diff --git a/bsp/common/interrupt.c b/bsp/common/interrupt.c index d666e1848..3db1650ea 100644 --- a/bsp/common/interrupt.c +++ b/bsp/common/interrupt.c @@ -2,11 +2,14 @@ #include #include "interrupt.h" +#include "sdkconfig.h" -#ifdef RT_USING_GIC_V2 -#include "gic.h" -#else +#ifdef CONFIG_USE_GIC +#ifdef CONFIG_EBABLE_GICV3 #include "gicv3.h" +#else +#include "gic.h" +#endif #endif #define MAX_HANDLERS 160 diff --git a/doc/ChangeLog.md b/doc/ChangeLog.md index 6155da37c..0b7209816 100644 --- a/doc/ChangeLog.md +++ b/doc/ChangeLog.md @@ -1,4 +1,31 @@ -# Phytium Standalone SDK v0.0.1 ChangeLog +# Phytium Standalone SDK v0.0.4 ChangeLog + +Change Log sinc v0.0.2 + +## BSP + +- support Rt-Thread 32 bit single and smp Mode +- Support Rt-Thread 64 bit single Mode +- 32bit , 64 bit baremetal support libc +- 32bit , 64 bit support fpu + +## baremetal/example + +- aarch32_math_test + +# Phytium Standalone SDK v0.0.2 ChangeLog + +Change Log sinc v0.0.1 + +## BSP + +- support SYS Mode for Freertos +- support OS defined Irq/Swi handler for FreeRTOS + +## Doc + +- add checklist for pre-release check +- update Readme Change Log since init @@ -10,7 +37,7 @@ Change Log since init - aarch32_qemu_debug: hello world and step debug in qemu - aarch32_timer_irq: run with generic timer tick irq - aarch32_cache_mmu_wr: run with cache (L1/L2/L3) and mmu enabled -- aarch32_uart_irq: run with uart tx and rx irq +- aarch32_uart_irq: run with uart tx and rx irq - aarch64_uart_irq_send: run with uart tx and rx irq in aarch64 ## BSP @@ -25,11 +52,13 @@ Change Log since init - support system error coding ## Lib + - support c standard lib - support c no standard lib - add kconfiglib to support menuconfig ## Make + - add basic compile scripts, 'complier.mk' 'ld.mk' - add compile info print script, 'buildinfo.mk' - add menuconfig setting script, 'preconfig.mk' @@ -38,4 +67,4 @@ Change Log since init ## Scripts - add sdk install and register script, 'export.sh' -- add utility script \ No newline at end of file +- add utility script diff --git a/install.sh b/install.sh new file mode 100644 index 000000000..3acfa4411 --- /dev/null +++ b/install.sh @@ -0,0 +1,106 @@ +### +### + # @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + #   + # SPDX-License-Identifier: Apache-2.0. + # + # @Date: 2021-06-30 17:24:45 + # @LastEditTime: 2021-07-12 13:59:49 + # @Description:  This files is for  + # + # @Modify History: + #  Ver   Who        Date         Changes + # ----- ------     --------    -------------------------------------- + +#!/bin/sh +# online install would wget cc and install +# offline install need put cc package under folder 'tools' +if [ "$1" = "-online" ]; then + OFFLINE_INSTALL=0 +else + OFFLINE_INSTALL=1 +fi + +# setup u git +git config core.ignorecase false + +# make sure all src file ends with LF +#find . -type f -exec dos2unix {} \; + +# update +##################SET ROOT PATH############## +# profile to save environment variables +PROFILE_PATH=~/.profile + +# get absoulte path of sdk +export SDK_ROOT="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" + +# delete SDK_ROOT if exists +sed -i '/export SDK_ROOT=/d' $PROFILE_PATH +# append SDK_ROOT environment +echo "export SDK_ROOT=$SDK_ROOT" >> $PROFILE_PATH + +###################CHANGE FILE MODE############## +# make sure sdk scripts are executable +chmod +x $SDK_ROOT/*.sh --silent +chmod +x $SDK_ROOT/scripts/*.sh --silent +chmod +x $SDK_ROOT/make/*.mk --silent +chmod +x $SDK_ROOT/lib/Kconfiglib/*.py --silent + +# install gcc compiler +if [ ! -d $SDK_ROOT ]; then + echo "Please set the SDK Root Path first !!!" + exit 1 +fi + +# if define offline install, put aarch32 & aarch64 compiler package under dir tools +INSTALL_PATH=$SDK_ROOT/tools +if [ $(arch) == x86_64 ]; then + echo "X86_64" + AARCH32_URL=https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz + AARCH32_CC_PACK=gcc-arm-none-eabi-phytium.xz + AARCH64_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.2-2020.11/binrel/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz + AARCH64_CC_PACK=gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz + export AARCH32_CROSS_PATH=$INSTALL_PATH/gcc-arm-none-eabi-phytium-major + export AARCH64_CROSS_PATH=$INSTALL_PATH/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf +fi + +if [ $(arch) == aarch64 ]; then + echo "AARCH64" + AARCH32_URL=https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-aarch64-linux.tar.bz + AARCH64_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.2-2020.11/binrel/gcc-arm-10.2-2020.11-aarch64-arm-none-eabi.tar.xz + AARCH32_CC_PACK=gcc-arm-none-eabi-10-2020-q4-major-aarch64-linux.tar.bz + AARCH64_CC_PACK=gcc-arm-10.2-2020.11-aarch64-aarch64-none-elf.tar.xz + export AARCH32_CROSS_PATH=$INSTALL_PATH/gcc-arm-none-eabi-10-2020-q4-major + export AARCH64_CROSS_PATH=$INSTALL_PATH/gcc-arm-10.2-2020.11-aarch64-aarch64-none-elf +fi + +if [ $OFFLINE_INSTALL -ne 1 ]; then +# do not download if package exists + [ ! -d $AARCH32_CROSS_PATH ] && [ ! -f $INSTALL_PATH/$AARCH32_CC_PACK ] && wget -P $INSTALL_PATH/ $AARCH32_URL + [ ! -d $AARCH64_CROSS_PATH ] && [ ! -f $INSTALL_PATH/$AARCH64_CC_PACK ] && wget -P $INSTALL_PATH/ $AARCH64_URL +fi + +##################SET COMPILER PATH############## +## AARCH32 CC +[ ! -d $AARCH32_CROSS_PATH ] && sudo tar -C $INSTALL_PATH/ -jxvf $INSTALL_PATH/$AARCH32_CC_PACK +sed -i '/export AARCH32_CROSS_PATH=/d' $PROFILE_PATH +sed -i '/export PATH=\"\$PATH:\$AARCH32_CROSS_PATH/d' $PROFILE_PATH +echo "export AARCH32_CROSS_PATH=$AARCH32_CROSS_PATH" >> $PROFILE_PATH +echo "export PATH=\"\$PATH:\$AARCH32_CROSS_PATH/bin\"">> $PROFILE_PATH + +## AARCH64 CC +[ ! -d $AARCH64_CROSS_PATH ] && sudo tar -C $INSTALL_PATH/ -vxf $INSTALL_PATH/$AARCH64_CC_PACK +sed -i '/export AARCH64_CROSS_PATH=/d' $PROFILE_PATH +sed -i '/export PATH=\"\$PATH:\$AARCH64_CROSS_PATH/d' $PROFILE_PATH +echo "export AARCH64_CROSS_PATH=$AARCH64_CROSS_PATH" >> $PROFILE_PATH +echo "export PATH=\"\$PATH:\$AARCH64_CROSS_PATH/bin\"">> $PROFILE_PATH + +##################Show msg, Make Environment Variables works####### +source $PROFILE_PATH + +echo "Please type in 'source ./export.sh'" +echo "Phytium Embedded SDK Setup Done!!" +echo "Install AARCH32 Compiler at " $AARCH32_CROSS_PATH +echo "Install AARCH64 Compiler at " $AARCH64_CROSS_PATH +echo "SDK Path is set as "$SDK_ROOT \ No newline at end of file diff --git a/lib/libc/retarget.c b/lib/libc/retarget.c index 88c0cfce1..e23f0f40b 100644 --- a/lib/libc/retarget.c +++ b/lib/libc/retarget.c @@ -21,14 +21,13 @@ void initialise_monitor_handles() { /* 关闭行缓冲 */ setvbuf(stdout, NULL, _IONBF, 0); - // OutByte('a'); setvbuf(stdin, NULL, _IONBF, 0); - // OutByte('b'); } int _read(int file, char *ptr, int len) { int i; + for (i = 0; i < len; ++i) { ptr[i] = GetByte(); @@ -38,7 +37,6 @@ int _read(int file, char *ptr, int len) int _write(int file, char *ptr, int len) { - int i; for (i = 0; i < len; ++i) { diff --git a/make/buildinfo.mk b/make/buildinfo.mk index 3a8832dde..9718273f3 100644 --- a/make/buildinfo.mk +++ b/make/buildinfo.mk @@ -16,6 +16,10 @@ info: @echo "project path: " $(PROJECT_DIR) @echo + @echo "usr src path: " $(USR_SRC_DIR) + @echo + @echo "usr inc path: " $(USR_INC_DIR) + @echo @echo "sdk path: " $(SDK_ROOT) @echo @echo "output path: " $(OUTPUT_DIR) @@ -49,7 +53,11 @@ info-variables: info-flags: @echo "target arch: "$(TARGET_ARCH) + @echo @echo "link flags: "$(LDFLAGS) + @echo @echo "cpp flags: "$(CPPFLAGS) + @echo @echo "asemblely flags: "$(ASFLAGS) + @echo @echo "c flags: "$(CFLAGS) diff --git a/make/complier.mk b/make/complier.mk index 01e203059..0c68daf92 100644 --- a/make/complier.mk +++ b/make/complier.mk @@ -79,6 +79,7 @@ $(shell if [ ! -e $(OUTPUT_DIR) ];then mkdir -p $(OUTPUT_DIR); fi) # include componet makefile include $(SDK_ROOT)/bsp/bsp.mk include $(SDK_ROOT)/lib/lib.mk +include $(SDK_ROOT)/third-party/third-party.mk include $(SDK_ROOT)/make/ld.mk INC_DIR := $(INC_DIR) $(USR_INC_DIR) @@ -128,9 +129,10 @@ endif TARGET_ARCH = -march=$(ARCH) #mkdir 创建输出文件目录 +SRC_DIR := $(SRC_DIR) $(USR_SRC_DIR) X_OUTPUT_DIRS := $(patsubst %, $(OUTPUT_DIR)/%, $(SRC_DIR)) -SRC_DIR := $(SRC_DIR) $(USR_SRC_DIR) + APP_C_SRC := $(foreach dir, $(SRC_DIR), $(wildcard $(dir)/*.c)) APP_S_SRC := $(foreach dir, $(SRC_DIR), $(wildcard $(dir)/*.S)) diff --git a/make/complier.mk_o b/make/complier.mk_o deleted file mode 100644 index ad6dff3a6..000000000 --- a/make/complier.mk_o +++ /dev/null @@ -1,189 +0,0 @@ -# Copyright (C) ARM Limited, 2014-2016. All rights reserved. -# -# This example is intended to be built with Linaro bare-metal GCC -# -# Environment variables for build options that the user might wish to change -# -# Variable Example Value -# ---------- ------------- -# APP myapp.axf -# QUIET @ for terse output, or leave blank for detailed output -# OPT_LEVEL 0, 1, 2 or 3 -# DEFINES -D MYDEFINE - -#include $(SDK_ROOT)/make/preconfig.mk - -APP ?= $(CONFIG_TARGET_NAME) - -QUIET ?=@ -OPT_LEVEL ?= 0 - -# Other switches the user should not normally need to change: -ifdef CONFIG_TARGET_ARMV8_AARCH32 - ARCH = armv8-a -endif - -ifdef CONFIG_TARGET_ARMV8_AARCH64 - ARCH = armv8-a -endif - -ifdef CONFIG_TARGET_ARMV7 - ARCH = armv7-a -endif - - -DEBUG_FLAGS = -g - -CPPFLAGS_EXTRA := - -ifndef SDK_ROOT -$(error error, please set SDK_ROOT first!!) -endif - -ifeq ($(QUIET),@) -PROGRESS = @echo Compiling $<... -endif - -ifdef CONFIG_TARGET_ARMV8_AARCH64 - ifdef CONFIG_USE_EXT_COMPILER - CROSS_PATH := $(CONFIG_EXT_COMPILER_PREFIX) - else - CROSS_PATH := $(AARCH64_CROSS_PATH) - endif -CROSS_COMPILE := $(CROSS_PATH)/bin/aarch64-none-elf- -endif - -ifdef CONFIG_TARGET_ARMV8_AARCH32 - ifdef CONFIG_USE_EXT_COMPILER - CROSS_PATH := $(CONFIG_EXT_COMPILER_PREFIX) - else - CROSS_PATH := $(AARCH32_CROSS_PATH) - endif -CROSS_COMPILE := $(CROSS_PATH)/bin/arm-none-eabi- -endif - -CC = $(CROSS_COMPILE)gcc -OC = $(CROSS_COMPILE)objcopy -OD = $(CROSS_COMPILE)objdump -LD = $(CROSS_COMPILE)ld - -# Commit hash from git -COMMIT=$(shell git rev-parse --short HEAD) -PACK_DATA=$(shell date +'%m%d_%H%M') -INC_DIR ?= # include 目录 -SRC_DIR ?= # 源文件目录 -EXCL_SRC ?= # 在源文件目录中不编译 -#OUTPUT_DIR ?= build # 输出目录 -$(shell if [ ! -e $(OUTPUT_DIR) ];then mkdir -p $(OUTPUT_DIR); fi) - -# include componet makefile -include $(SDK_ROOT)/bsp/bsp.mk -include $(SDK_ROOT)/lib/lib.mk -include $(SDK_ROOT)/make/ld.mk - -INC_DIR := $(INC_DIR) $(USR_INC_DIR) -INCLUDES := $(patsubst %, -I %, $(INC_DIR)) - -define EOL = - -endef - -ifeq ($(OS),Windows_NT) -RM_FILES = $(foreach file,$(1),if exist $(file) del /q $(file)$(EOL)) -RM_D -IRS = $(foreach dir,$(1),if exist $(dir) rmdir /s /q $(dir)$(EOL)) -else -RM_FILES = $(foreach file,$(1),rm -f $(file)$(EOL)) -RM_DIRS = $(foreach dir,$(1),rm -rf $(dir)$(EOL)) -endif - -DEPEND_FLAGS = -MD -MF $@.d - -CPPFLAGS = $(DEFINES) $(INCLUDES) $(DEPEND_FLAGS) $(CPPFLAGS_EXTRA) -CFLAGS = $(DEBUG_FLAGS) -DGUEST -ffreestanding -Wextra -g -O$(OPT_LEVEL) -ASFLAGS = $(CFLAGS) - -LIBC ?= -LIBPATH ?= -ifdef CONFIG_TARGET_ARMV8_AARCH32 - LIBC += $(CROSS_PATH)/arm-none-eabi/lib/libc_nano.a - LIBC += $(CROSS_PATH)/arm-none-eabi/lib/libnosys.a - LIBPATH += $(CROSS_PATH)/lib/gcc/arm-none-eabi/10.2.1 -# support float and div, turn on by default for aarch64 - ASFLAGS := $(ASFLAGS) -mfpu=vfpv3-fp16 -ftree-vectorize -mfloat-abi=softfp -ffast-math -fsingle-precision-constant -march=armv8-a - CFLAGS := $(CFLAGS) -mfpu=vfpv3-fp16 -mfloat-abi=softfp -march=armv8-a -endif - -ifdef CONFIG_TARGET_ARMV8_AARCH64 - CROSS_PATH := $(AARCH64_CROSS_PATH) -endif - -LDFLAGS = -T$(LDSNAME) -Wl,--build-id=none -ifdef CONFIG_USE_LIBC -# LDFLAGS += -lgcc -L $(LIBPATH) -else -LDFLAGS += -nostdlib -nostartfiles -endif - -TARGET_ARCH = -march=$(ARCH) - -#mkdir 创建输出文件目录 -X_OUTPUT_DIRS := $(patsubst %, $(OUTPUT_DIR)/%, $(SRC_DIR)) - -SRC_DIR := $(SRC_DIR) $(USR_SRC_DIR) - -APP_C_SRC := $(foreach dir, $(SRC_DIR), $(wildcard $(dir)/*.c)) -APP_S_SRC := $(foreach dir, $(SRC_DIR), $(wildcard $(dir)/*.S)) - -OBJ_FILES := $(patsubst %, $(OUTPUT_DIR)/%, $(APP_S_SRC:.S=.o)) \ - $(patsubst %, $(OUTPUT_DIR)/%, $(APP_C_SRC:.c=.o)) - -EXCL_OBJS ?= $(patsubst %, $(OUTPUT_DIR)/%, $(EXCL_SRC:.c=.o)) -OBJ_FILES := $(filter-out $(EXCL_OBJS), $(OBJ_FILES)) -OBJ_FILES += $(LIBC) - -DEP_FILES := $(OBJ_FILES:%=%.d) - -ifdef CONFIG_DUMMY_COMPILE - DO_ECHO = @echo -else - DO_ECHO = -endif - -.phony: all clean rebuild -all: $(APP) - -$(APP): $(OBJ_FILES) $(LDSNAME) - @echo Linking $@.elf - @echo Dumping $@.map - - $(DO_ECHO) $(QUIET) $(CC) $(TARGET_ARCH) $(LDFLAGS) --output $@.elf -Wl,-Map=$@.map $(OBJ_FILES) -lm - @echo Objcopying $@.bin - $(DO_ECHO) $(QUIET) $(OC) -v -O binary $@.elf $@.bin - $(DO_ECHO) $(QUIET) $(OD) -D $@.elf > $@.dis - @echo Done. - -clean: - $(call RM_DIRS,$(OUTPUT_DIR)) - $(call RM_FILES,*.elf) - $(call RM_FILES,*.bin) - $(call RM_FILES,*.dis) - $(call RM_FILES,*.map) - $(call RM_FILES,*.tar.gz) - -$(X_OUTPUT_DIRS): - @mkdir -p $@ - -$(OUTPUT_DIR)/%.o : %.S | $(X_OUTPUT_DIRS) - $(PROGRESS) - $(QUIET) $(CC) -c $(TARGET_ARCH) $(CPPFLAGS) $(ASFLAGS) -o $@ $< - -$(OUTPUT_DIR)/%.o : %.c | $(X_OUTPUT_DIRS) - $(PROGRESS) - $(QUIET) $(CC) -c $(TARGET_ARCH) $(CPPFLAGS) $(CFLAGS) -o $@ $< - - -# Make sure everything is rebuilt if this makefile is changed -$(OBJ_FILES) $(APP): makefile - --include $(DEP_FILES) diff --git a/make/ld.mk b/make/ld.mk index 2b4f457b5..377a7ae54 100644 --- a/make/ld.mk +++ b/make/ld.mk @@ -11,4 +11,8 @@ endif ifdef CONFIG_QEMU_AARCH32_RAM_LD LDSNAME ?= $(LD_DIR)/qemu_aarch32_ram.ld +endif + +ifdef CONFIG_USER_DEFINED_LD +LDSNAME ?= $(EXT_LDSNAME) endif \ No newline at end of file diff --git a/make/preconfig.mk b/make/preconfig.mk index 4a20b7a40..e96b5de2e 100644 --- a/make/preconfig.mk +++ b/make/preconfig.mk @@ -1,3 +1,4 @@ +# define empty if user do not use export USR_SRC_DIR ?= $(PROJECT_DIR) export USR_INC_DIR ?= $(PROJECT_DIR) diff --git a/third-party/Kconfig b/third-party/Kconfig new file mode 100644 index 000000000..d3fac1ee1 --- /dev/null +++ b/third-party/Kconfig @@ -0,0 +1,10 @@ +menu "Standalone Third-Party Configuration" + +config USE_COREMARK + bool + depends on USE_LIBC + prompt "Use Coremark" + help + Include Coremark for Benchmark + +endmenu \ No newline at end of file diff --git a/third-party/coremark/README.md b/third-party/coremark/README.md new file mode 100644 index 000000000..d4a89c19e --- /dev/null +++ b/third-party/coremark/README.md @@ -0,0 +1,474 @@ +# Coremark + +RT-Thread 上的 MCU/CPU 性能测试小工具，在 menuconfig 里选中软件包后，在 msh 中输入： + +``` +msh> core_mark +``` + +就可以看到跑分结果了，例如： + +### STM32F103RC (72MHZ) ARMCC -O3 -Otime 跑分 135: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Oct 13 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +msh >core_mark +Benchmark started, please make sure it runs for at least 10s. + +2K performance run parameters for coremark. +CoreMark Size : 666 +Total ticks : 17776 +Total time (secs): 17.776000 +Iterations/Sec : 135.013501 +Iterations : 2400 +Compiler version : Please put compiler version here (e.g. gcc 4.1) +Compiler flags : +Memory location : STACK +seedcrc : 0xe9f5 +[0]crclist : 0xe714 +[0]crcmatrix : 0x1fd7 +[0]crcstate : 0x8e3a +[0]crcfinal : 0x382f +Correct operation validated. See README.md for run and reporting rules. +CoreMark 1.0 : 135.013501 / Please put compiler version here (e.g. gcc 4.1) / STACK +``` + +### GD32VF103 (108MHz) GCC -Os 跑分 327: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Oct 13 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +msh >core_mark +Benchmark started, please make sure it runs for at least 10s. + +2K performance run parameters for coremark. +CoreMark Size : 666 +Total ticks : 1178 +Total time (secs): 11 +Iterations/Sec : 327 +Iterations : 3600 +Compiler version : GCC8.2.0 +Compiler flags : +Memory location : STACK +seedcrc : 0xe9f5 +[0]crclist : 0xe714 +[0]crcmatrix : 0x1fd7 +[0]crcstate : 0x8e3a +[0]crcfinal : 0x4bfc +Correct operation validated. See README.md for run and reporting rules. +CoreMark 1.0 : 327 / GCC8.2.0 / STACK +``` + +更多测试结果可以在这里看到： + +**https://www.eembc.org/coremark/scores.php** + +## 注意事项 + +- 如果结果希望以小数形式打印，默认会选择 libc 依赖 +- 测试程序需要运行至少 10s，如果 MCU 性能太强劲一下就结束了，可以适当增加迭代次数 + +--------------------------- + +# Introduction + +CoreMark's primary goals are simplicity and providing a method for testing only a processor's core features. For more information about EEMBC's comprehensive embedded benchmark suites, please see www.eembc.org. + +For a more compute-intensive version of CoreMark that uses larger datasets and execution loops taken from common applications, please check out EEMBC's [CoreMark-PRO](https://www.github.com/eembc/coremark-pro) benchmark, also on GitHub. + +# Building and Running + +To build and run the benchmark, type + +`> make` + +Full results are available in the files `run1.log` and `run2.log`. CoreMark result can be found in `run1.log`. + +## Cross Compiling + +For cross compile platforms please adjust `core_portme.mak`, `core_portme.h` (and possibly `core_portme.c`) according to the specific platform used. When porting to a new platform, it is recommended to copy one of the default port folders (e.g. `mkdir && cp linux/* `), adjust the porting files, and run: +~~~ +% make PORT_DIR= +~~~ + +## Make Targets +`run` - Default target, creates `run1.log` and `run2.log`. +`run1.log` - Run the benchmark with performance parameters, and output to `run1.log` +`run2.log` - Run the benchmark with validation parameters, and output to `run2.log` +`run3.log` - Run the benchmark with profile generation parameters, and output to `run3.log` +`compile` - compile the benchmark executable +`link` - link the benchmark executable +`check` - test MD5 of sources that may not be modified +`clean` - clean temporary files + +### Make flag: `ITERATIONS` +By default, the benchmark will run between 10-100 seconds. To override, use `ITERATIONS=N` +~~~ +% make ITERATIONS=10 +~~~ +Will run the benchmark for 10 iterations. It is recommended to set a specific number of iterations in certain situations e.g.: + +* Running with a simulator +* Measuring power/energy +* Timing cannot be restarted + +Minimum required run time: **Results are only valid for reporting if the benchmark ran for at least 10 secs!** + +### Make flag: `XCFLAGS` +To add compiler flags from the command line, use `XCFLAGS` e.g.: + +~~~ +% make XCFLAGS="-g -DMULTITHREAD=4 -DUSE_FORK=1" +~~~ + +### Make flag: `CORE_DEBUG` + +Define to compile for a debug run if you get incorrect CRC. + +~~~ +% make XCFLAGS="-DCORE_DEBUG=1" +~~~ + +### Make flag: `REBUILD` + +Force a rebuild of the executable. + +## Systems Without `make` +The following files need to be compiled: +* `core_list_join.c` +* `core_main.c` +* `core_matrix.c` +* `core_state.c` +* `core_util.c` +* `PORT_DIR/core_portme.c` + +For example: +~~~ +% gcc -O2 -o coremark.exe core_list_join.c core_main.c core_matrix.c core_state.c core_util.c simple/core_portme.c -DPERFORMANCE_RUN=1 -DITERATIONS=1000 +% ./coremark.exe > run1.log +~~~ +The above will compile the benchmark for a performance run and 1000 iterations. Output is redirected to `run1.log`. + +# Parallel Execution +Use `XCFLAGS=-DMULTITHREAD=N` where N is number of threads to run in parallel. Several implementations are available to execute in multiple contexts, or you can implement your own in `core_portme.c`. + +~~~ +% make XCFLAGS="-DMULTITHREAD=4 -DUSE_PTHREAD" +~~~ + +Above will compile the benchmark for execution on 4 cores, using POSIX Threads API. + +# Run Parameters for the Benchmark Executable +CoreMark's executable takes several parameters as follows (but only if `main()` accepts arguments): +1st - A seed value used for initialization of data. +2nd - A seed value used for initialization of data. +3rd - A seed value used for initialization of data. +4th - Number of iterations (0 for auto : default value) +5th - Reserved for internal use. +6th - Reserved for internal use. +7th - For malloc users only, ovreride the size of the input data buffer. + +The run target from make will run coremark with 2 different data initialization seeds. + +## Alternative parameters: +If not using `malloc` or command line arguments are not supported, the buffer size +for the algorithms must be defined via the compiler define `TOTAL_DATA_SIZE`. +`TOTAL_DATA_SIZE` must be set to 2000 bytes (default) for standard runs. +The default for such a target when testing different configurations could be: + +~~~ +% make XCFLAGS="-DTOTAL_DATA_SIZE=6000 -DMAIN_HAS_NOARGC=1" +~~~ + +# Submitting Results + +CoreMark results can be submitted on the web. Open a web browser and go to the [submission page](https://www.eembc.org/coremark/submit.php). After registering an account you may enter a score. + +# Run Rules +What is and is not allowed. + +## Required +1. The benchmark needs to run for at least 10 seconds. +2. All validation must succeed for seeds `0,0,0x66` and `0x3415,0x3415,0x66`, buffer size of 2000 bytes total. + * If not using command line arguments to main: +~~~ + % make XCFLAGS="-DPERFORMANCE_RUN=1" REBUILD=1 run1.log + % make XCFLAGS="-DVALIDATION_RUN=1" REBUILD=1 run2.log +~~~ +3. If using profile guided optimization, profile must be generated using seeds of `8,8,8`, and buffer size of 1200 bytes total. +~~~ + % make XCFLAGS="-DTOTAL_DATA_SIZE=1200 -DPROFILE_RUN=1" REBUILD=1 run3.log +~~~ +4. All source files must be compiled with the same flags. +5. All data type sizes must match size in bits such that: + * `ee_u8` is an unsigned 8-bit datatype. + * `ee_s16` is a signed 16-bit datatype. + * `ee_u16` is an unsigned 16-bit datatype. + * `ee_s32` is a signed 32-bit datatype. + * `ee_u32` is an unsigned 32-bit datatype. + +## Allowed + +1. Changing number of iterations +2. Changing toolchain and build/load/run options +3. Changing method of acquiring a data memory block +5. Changing the method of acquiring seed values +6. Changing implementation `in core_portme.c` +7. Changing configuration values in `core_portme.h` +8. Changing `core_portme.mak` + +## NOT ALLOWED +1. Changing of source file other then `core_portme*` (use `make check` to validate) + +# Reporting rules +Use the following syntax to report results on a data sheet: + +CoreMark 1.0 : N / C [/ P] [/ M] + +N - Number of iterations per second with seeds 0,0,0x66,size=2000) + +C - Compiler version and flags + +P - Parameters such as data and code allocation specifics + +* This parameter *may* be omitted if all data was allocated on the heap in RAM. +* This parameter *may not* be omitted when reporting CoreMark/MHz + +M - Type of parallel execution (if used) and number of contexts +* This parameter may be omitted if parallel execution was not used. + +e.g.: + +~~~ +CoreMark 1.0 : 128 / GCC 4.1.2 -O2 -fprofile-use / Heap in TCRAM / FORK:2 +~~~ +or +~~~ +CoreMark 1.0 : 1400 / GCC 3.4 -O4 +~~~ + +If reporting scaling results, the results must be reported as follows: + +CoreMark/MHz 1.0 : N / C / P [/ M] + +P - When reporting scaling results, memory parameter must also indicate memory frequency:core frequency ratio. +1. If the core has cache and cache frequency to core frequency ratio is configurable, that must also be included. + +e.g.: + +~~~ +CoreMark/MHz 1.0 : 1.47 / GCC 4.1.2 -O2 / DDR3(Heap) 30:1 Memory 1:1 Cache +~~~ + +# Log File Format +The log files have the following format + +~~~ +2K performance run parameters for coremark. (Run type) +CoreMark Size : 666 (Buffer size) +Total ticks : 25875 (platform dependent value) +Total time (secs) : 25.875000 (actual time in seconds) +Iterations/Sec : 3864.734300 (Performance value to report) +Iterations : 100000 (number of iterations used) +Compiler version : GCC3.4.4 (Compiler and version) +Compiler flags : -O2 (Compiler and linker flags) +Memory location : Code in flash, data in on chip RAM +seedcrc : 0xe9f5 (identifier for the input seeds) +[0]crclist : 0xe714 (validation for list part) +[0]crcmatrix : 0x1fd7 (validation for matrix part) +[0]crcstate : 0x8e3a (validation for state part) +[0]crcfinal : 0x33ff (iteration dependent output) +Correct operation validated. See README.md for run and reporting rules. (*Only when run is successful*) +CoreMark 1.0 : 6508.490622 / GCC3.4.4 -O2 / Heap (*Only on a successful performance run*) +~~~ + +# Theory of Operation + +This section describes the initial goals of CoreMark and their implementation. + +## Small and easy to understand + +* X number of source code lines for timed portion of the benchmark. +* Meaningful names for variables and functions. +* Comments for each block of code more than 10 lines long. + +## Portability + +A thin abstraction layer will be provided for I/O and timing in a separate file. All I/O and timing of the benchmark will be done through this layer. + +### Code / data size + +* Compile with gcc on x86 and make sure all sizes are according to requirements. +* If dynamic memory allocation is used, take total memory allocated into account as well. +* Avoid recursive functions and keep track of stack usage. +* Use the same memory block as data site for all algorithms, and initialize the data before each algorithm – while this means that initialization with data happens during the timed portion, it will only happen once during the timed portion and so have negligible effect on the results. + +## Controlled output + +This may be the most difficult goal. Compilers are constantly improving and getting better at analyzing code. To create work that cannot be computed at compile time and must be computed at run time, we will rely on two assumptions: + +* Some system functions (e.g. time, scanf) and parameters cannot be computed at compile time. In most cases, marking a variable volatile means the compiler is force to read this variable every time it is read. This will be used to introduce a factor into the input that cannot be precomputed at compile time. Since the results are input dependent, that will make sure that computation has to happen at run time. + +* Either a system function or I/O (e.g. scanf) or command line parameters or volatile variables will be used before the timed portion to generate data which is not available at compile time. Specific method used is not relevant as long as it can be controlled, and that it cannot be computed or eliminated by the compiler at compile time. E.g. if the clock() functions is a compiler stub, it may not be used. The derived values will be reported on the output so that verification can be done on a different machine. + +* We cannot rely on command line parameters since some embedded systems do not have the capability to provide command line parameters. All 3 methods above will be implemented (time based, scanf and command line parameters) and all 3 are valid if the compiler cannot determine the value at compile time. + +* It is important to note that The actual values that are to be supplied at run time will be standardized. The methodology is not intended to provide random data, but simply to provide controlled data that cannot be precomputed at compile time. + +* Printed results must be valid at run time. This will be used to make sure the computation has been executed. + +* Some embedded systems do not provide “printf” or other I/O functionality. All I/O will be done through a thin abstraction interface to allow execution on such systems (e.g. allow output via JTAG). + +## Key Algorithms + +### Linked List + +The following linked list structure will be used: + +~~~ +typedef struct list_data_s { + ee_s16 data16; + ee_s16 idx; +} list_data; + +typedef struct list_head_s { + struct list_head_s *next; + struct list_data_s *info; +} list_head; +~~~ + +While adding a level of indirection accessing the data, this structure is realistic and used in many embedded applications for small to medium lists. + +The list itself will be initialized on a block of memory that will be passed in to the initialization function. While in general linked lists use malloc for new nodes, embedded applications sometime control the memory for small data structures such as arrays and lists directly to avoid the overhead of system calls, so this approach is realistic. + +The linked list will be initialized such that 1/4 of the list pointers point to sequential areas in memory, and 3/4 of the list pointers are distributed in a non sequential manner. This is done to emulate a linked list that had add/remove happen for a while disrupting the neat order, and then a series of adds that are likely to come from sequential memory locations. + +For the benchmark itself: +- Multiple find operations are going to be performed. These find operations may result in the whole list being traversed. The result of each find will become part of the output chain. +- The list will be sorted using merge sort based on the data16 value, and then derive CRC of the data16 item in order for part of the list. The CRC will become part of the output chain. +- The list will be sorted again using merge sort based on the idx value. This sort will guarantee that the list is returned to the primary state before leaving the function, so that multiple iterations of the function will have the same result. CRC of the data16 for part of the list will again be calculated and become part of the output chain. + +The actual `data16` in each cell will be pseudo random based on a single 16b input that cannot be determined at compile time. In addition, the part of the list which is used for CRC will also be passed to the function, and determined based on an input that cannot be determined at run time. + +### Matrix Multiply + +This very simple algorithm forms the basis of many more complex algorithms. The tight inner loop is the focus of many optimizations (compiler as well as hardware based) and is thus relevant for embedded processing. + +The total available data space will be divided to 3 parts: +1. NxN matrix A. +2. NxN matrix B. +3. NxN matrix C. + +E.g. for 2K we will have 3 12x12 matrices (assuming data type of 32b 12(len)*12(wid)*4(size)*3(num) =1728 bytes). + +Matrix A will be initialized with small values (upper 3/4 of the bits all zero). +Matrix B will be initialized with medium values (upper half of the bits all zero). +Matrix C will be used for the result. + +For the benchmark itself: +- Multiple A by a constant into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain. +- Multiple A by column X of B into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain. +- Multiple A by B into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain. + +The actual values for A and B must be derived based on input that is not available at compile time. + +### State Machine + +This part of the code needs to exercise switch and if statements. As such, we will use a small Moore state machine. In particular, this will be a state machine that identifies string input as numbers and divides them according to format. + +The state machine will parse the input string until either a “,” separator or end of input is encountered. An invalid number will cause the state machine to return invalid state and a valid number will cause the state machine to return with type of number format (int/float/scientific). + +This code will perform a realistic task, be small enough to easily understand, and exercise the required functionality. The other option used in embedded systems is a mealy based state machine, which is driven by a table. The table then determines the number of states and complexity of transitions. This approach, however, tests mainly the load/store and function call mechanisms and less the handling of branches. If analysis of the final results shows that the load/store functionality of the processor is not exercised thoroughly, it may be a good addition to the benchmark (codesize allowing). + +For input, the memory block will be initialized with comma separated values of mixed formats, as well as invalid inputs. + +For the benchmark itself: +- Invoke the state machine on all of the input and count final states and state transitions. CRC of all final states and transitions will become part of the output chain. +- Modify the input at intervals (inject errors) and repeat the state machine operation. +- Modify the input back to original form. + +The actual input must be initialized based on data that cannot be determined at compile time. In addition the intervals for modification of the input and the actual modification must be based on input that cannot be determined at compile time. + +# Validation + +This release was tested on the following platforms: +* x86 cygwin and gcc 3.4 (Quad, dual and single core systems) +* x86 linux (Ubuntu/Fedora) and gcc (4.2/4.1) (Quad and single core systems) +* MIPS64 BE linux and gcc 3.4 16 cores system +* MIPS32 BE linux with CodeSourcery compiler 4.2-177 on Malta/Linux with a 1004K 3-core system +* PPC simulator with gcc 4.2.2 (No OS) +* PPC 64b BE linux (yellowdog) with gcc 3.4 and 4.1 (Dual core system) +* BF533 with VDSP50 +* Renesas R8C/H8 MCU with HEW 4.05 +* NXP LPC1700 armcc v4.0.0.524 +* NEC 78K with IAR v4.61 +* ARM simulator with armcc v4 + +# Memory Analysis + +Valgrind 3.4.0 used and no errors reported. + +# Balance Analysis + +Number of instructions executed for each function tested with cachegrind and found balanced with gcc and -O0. + +# Statistics + +Lines: +~~~ +Lines Blank Cmnts Source AESL +===== ===== ===== ===== ========== ======================================= + 469 66 170 251 627.5 core_list_join.c (C) + 330 18 54 268 670.0 core_main.c (C) + 256 32 80 146 365.0 core_matrix.c (C) + 240 16 51 186 465.0 core_state.c (C) + 165 11 20 134 335.0 core_util.c (C) + 150 23 36 98 245.0 coremark.h (C) + 1610 166 411 1083 2707.5 ----- Benchmark ----- (6 files) + 293 15 74 212 530.0 linux/core_portme.c (C) + 235 30 104 104 260.0 linux/core_portme.h (C) + 528 45 178 316 790.0 ----- Porting ----- (2 files) + +* For comparison, here are the stats for Dhrystone +Lines Blank Cmnts Source AESL +===== ===== ===== ===== ========== ======================================= + 311 15 242 54 135.0 dhry.h (C) + 789 132 119 553 1382.5 dhry_1.c (C) + 186 26 68 107 267.5 dhry_2.c (C) + 1286 173 429 714 1785.0 ----- C ----- (3 files) +~~~ + +# Credits +Many thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name; note that company names may no longer be accurate as this was written in 2009). +* Alan Anderson, ADI +* Adhikary Rajiv, ADI +* Elena Stohr, ARM +* Ian Rickards, ARM +* Andrew Pickard, ARM +* Trent Parker, CAVIUM +* Shay Gal-On, EEMBC +* Markus Levy, EEMBC +* Peter Torelli, EEMBC +* Ron Olson, IBM +* Eyal Barzilay, MIPS +* Jens Eltze, NEC +* Hirohiko Ono, NEC +* Ulrich Drees, NEC +* Frank Roscheda, NEC +* Rob Cosaro, NXP +* Shumpei Kawasaki, RENESAS + +# Legal +Please refer to LICENSE.md in this reposity for a description of your rights to use this code. + +# Copyright +Copyright © 2009 EEMBC All rights reserved. +CoreMark is a trademark of EEMBC and EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium. + diff --git a/third-party/coremark/core_list_join.c b/third-party/coremark/core_list_join.c new file mode 100644 index 000000000..9d544882d --- /dev/null +++ b/third-party/coremark/core_list_join.c @@ -0,0 +1,495 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +#include "coremark.h" +/* +Topic: Description + Benchmark using a linked list. + + Linked list is a common data structure used in many applications. + + For our purposes, this will excercise the memory units of the processor. + In particular, usage of the list pointers to find and alter data. + + We are not using Malloc since some platforms do not support this library. + + Instead, the memory block being passed in is used to create a list, + and the benchmark takes care not to add more items then can be + accomodated by the memory block. The porting layer will make sure + that we have a valid memory block. + + All operations are done in place, without using any extra memory. + + The list itself contains list pointers and pointers to data items. + Data items contain the following: + + idx - An index that captures the initial order of the list. + data - Variable data initialized based on the input parameters. The 16b are divided as follows: + o Upper 8b are backup of original data. + o Bit 7 indicates if the lower 7 bits are to be used as is or calculated. + o Bits 0-2 indicate type of operation to perform to get a 7b value. + o Bits 3-6 provide input for the operation. + +*/ + +/* local functions */ + +list_head *core_list_find(list_head *list,list_data *info); +list_head *core_list_reverse(list_head *list); +list_head *core_list_remove(list_head *item); +list_head *core_list_undo_remove(list_head *item_removed, list_head *item_modified); +list_head *core_list_insert_new(list_head *insert_point + , list_data *info, list_head **memblock, list_data **datablock + , list_head *memblock_end, list_data *datablock_end); +typedef ee_s32(*list_cmp)(list_data *a, list_data *b, core_results *res); +list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res); + +ee_s16 calc_func(ee_s16 *pdata, core_results *res) { + ee_s16 data=*pdata; + ee_s16 retval; + ee_u8 optype=(data>>7) & 1; /* bit 7 indicates if the function result has been cached */ + if (optype) /* if cached, use cache */ + return (data & 0x007f); + else { /* otherwise calculate and cache the result */ + ee_s16 flag=data & 0x7; /* bits 0-2 is type of function to perform */ + ee_s16 dtype=((data>>3) & 0xf); /* bits 3-6 is specific data for the operation */ + dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */ + switch (flag) { + case 0: + if (dtype<0x22) /* set min period for bit corruption */ + dtype=0x22; + retval=core_bench_state(res->size,res->memblock[3],res->seed1,res->seed2,dtype,res->crc); + if (res->crcstate==0) + res->crcstate=retval; + break; + case 1: + retval=core_bench_matrix(&(res->mat),dtype,res->crc); + if (res->crcmatrix==0) + res->crcmatrix=retval; + break; + default: + retval=data; + break; + } + res->crc=crcu16(retval,res->crc); + retval &= 0x007f; + *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */ + return retval; + } +} +/* Function: cmp_complex + Compare the data item in a list cell. + + Can be used by mergesort. +*/ +ee_s32 cmp_complex(list_data *a, list_data *b, core_results *res) { + ee_s16 val1=calc_func(&(a->data16),res); + ee_s16 val2=calc_func(&(b->data16),res); + return val1 - val2; +} + +/* Function: cmp_idx + Compare the idx item in a list cell, and regen the data. + + Can be used by mergesort. +*/ +ee_s32 cmp_idx(list_data *a, list_data *b, core_results *res) { + if (res==NULL) { + a->data16 = (a->data16 & 0xff00) | (0x00ff & (a->data16>>8)); + b->data16 = (b->data16 & 0xff00) | (0x00ff & (b->data16>>8)); + } + return a->idx - b->idx; +} + +void copy_info(list_data *to,list_data *from) { + to->data16=from->data16; + to->idx=from->idx; +} + +/* Benchmark for linked list: + - Try to find multiple data items. + - List sort + - Operate on data from list (crc) + - Single remove/reinsert + * At the end of this function, the list is back to original state +*/ +ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx) { + ee_u16 retval=0; + ee_u16 found=0,missed=0; + list_head *list=res->list; + ee_s16 find_num=res->seed3; + list_head *this_find; + list_head *finder, *remover; + list_data info; + ee_s16 i; + + info.idx=finder_idx; + /* find values in the list, and change the list each time (reverse and cache if value found) */ + for (i=0; inext->info->data16 >> 8) & 1; + } + else { + found++; + if (this_find->info->data16 & 0x1) /* use found value */ + retval+=(this_find->info->data16 >> 9) & 1; + /* and cache next item at the head of the list (if any) */ + if (this_find->next != NULL) { + finder = this_find->next; + this_find->next = finder->next; + finder->next=list->next; + list->next=finder; + } + } + if (info.idx>=0) + info.idx++; +#if CORE_DEBUG + ee_printf("List find %d: [%d,%d,%d]\n",i,retval,missed,found); +#endif + } + retval+=found*4-missed; + /* sort the list by data content and remove one item*/ + if (finder_idx>0) + list=core_list_mergesort(list,cmp_complex,res); + remover=core_list_remove(list->next); + /* CRC data content of list from location of index N forward, and then undo remove */ + finder=core_list_find(list,&info); + if (!finder) + finder=list->next; + while (finder) { + retval=crc16(list->info->data16,retval); + finder=finder->next; + } +#if CORE_DEBUG + ee_printf("List sort 1: %04x\n",retval); +#endif + remover=core_list_undo_remove(remover,list->next); + /* sort the list by index, in effect returning the list to original state */ + list=core_list_mergesort(list,cmp_idx,NULL); + /* CRC data content of list */ + finder=list->next; + while (finder) { + retval=crc16(list->info->data16,retval); + finder=finder->next; + } +#if CORE_DEBUG + ee_printf("List sort 2: %04x\n",retval); +#endif + return retval; +} +/* Function: core_list_init + Initialize list with data. + + Parameters: + blksize - Size of memory to be initialized. + memblock - Pointer to memory block. + seed - Actual values chosen depend on the seed parameter. + The seed parameter MUST be supplied from a source that cannot be determined at compile time + + Returns: + Pointer to the head of the list. + +*/ +list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed) { + /* calculated pointers for the list */ + ee_u32 per_item=16+sizeof(struct list_data_s); + ee_u32 size=(blksize/per_item)-2; /* to accomodate systems with 64b pointers, and make sure same code is executed, set max list elements */ + list_head *memblock_end=memblock+size; + list_data *datablock=(list_data *)(memblock_end); + list_data *datablock_end=datablock+size; + /* some useful variables */ + ee_u32 i; + list_head *finder,*list=memblock; + list_data info; + + /* create a fake items for the list head and tail */ + list->next=NULL; + list->info=datablock; + list->info->idx=0x0000; + list->info->data16=(ee_s16)0x8080; + memblock++; + datablock++; + info.idx=0x7fff; + info.data16=(ee_s16)0xffff; + core_list_insert_new(list,&info,&memblock,&datablock,memblock_end,datablock_end); + + /* then insert size items */ + for (i=0; inext; + i=1; + while (finder->next!=NULL) { + if (iinfo->idx=i++; + else { + ee_u16 pat=(ee_u16)(i++ ^ seed); /* get a pseudo random number */ + finder->info->idx=0x3fff & (((i & 0x07) << 8) | pat); /* make sure the mixed items end up after the ones in sequence */ + } + finder=finder->next; + } + list = core_list_mergesort(list,cmp_idx,NULL); +#if CORE_DEBUG + ee_printf("Initialized list:\n"); + finder=list; + while (finder) { + ee_printf("[%04x,%04x]",finder->info->idx,(ee_u16)finder->info->data16); + finder=finder->next; + } + ee_printf("\n"); +#endif + return list; +} + +/* Function: core_list_insert + Insert an item to the list + + Parameters: + insert_point - where to insert the item. + info - data for the cell. + memblock - pointer for the list header + datablock - pointer for the list data + memblock_end - end of region for list headers + datablock_end - end of region for list data + + Returns: + Pointer to new item. +*/ +list_head *core_list_insert_new(list_head *insert_point, list_data *info, list_head **memblock, list_data **datablock + , list_head *memblock_end, list_data *datablock_end) { + list_head *newitem; + + if ((*memblock+1) >= memblock_end) + return NULL; + if ((*datablock+1) >= datablock_end) + return NULL; + + newitem=*memblock; + (*memblock)++; + newitem->next=insert_point->next; + insert_point->next=newitem; + + newitem->info=*datablock; + (*datablock)++; + copy_info(newitem->info,info); + + return newitem; +} + +/* Function: core_list_remove + Remove an item from the list. + + Operation: + For a singly linked list, remove by copying the data from the next item + over to the current cell, and unlinking the next item. + + Note: + since there is always a fake item at the end of the list, no need to check for NULL. + + Returns: + Removed item. +*/ +list_head *core_list_remove(list_head *item) { + list_data *tmp; + list_head *ret=item->next; + /* swap data pointers */ + tmp=item->info; + item->info=ret->info; + ret->info=tmp; + /* and eliminate item */ + item->next=item->next->next; + ret->next=NULL; + return ret; +} + +/* Function: core_list_undo_remove + Undo a remove operation. + + Operation: + Since we want each iteration of the benchmark to be exactly the same, + we need to be able to undo a remove. + Link the removed item back into the list, and switch the info items. + + Parameters: + item_removed - Return value from the + item_modified - List item that was modified during + + Returns: + The item that was linked back to the list. + +*/ +list_head *core_list_undo_remove(list_head *item_removed, list_head *item_modified) { + list_data *tmp; + /* swap data pointers */ + tmp=item_removed->info; + item_removed->info=item_modified->info; + item_modified->info=tmp; + /* and insert item */ + item_removed->next=item_modified->next; + item_modified->next=item_removed; + return item_removed; +} + +/* Function: core_list_find + Find an item in the list + + Operation: + Find an item by idx (if not 0) or specific data value + + Parameters: + list - list head + info - idx or data to find + + Returns: + Found item, or NULL if not found. +*/ +list_head *core_list_find(list_head *list,list_data *info) { + if (info->idx>=0) { + while (list && (list->info->idx != info->idx)) + list=list->next; + return list; + } else { + while (list && ((list->info->data16 & 0xff) != info->data16)) + list=list->next; + return list; + } +} +/* Function: core_list_reverse + Reverse a list + + Operation: + Rearrange the pointers so the list is reversed. + + Parameters: + list - list head + info - idx or data to find + + Returns: + Found item, or NULL if not found. +*/ + +list_head *core_list_reverse(list_head *list) { + list_head *next=NULL, *tmp; + while (list) { + tmp=list->next; + list->next=next; + next=list; + list=tmp; + } + return next; +} +/* Function: core_list_mergesort + Sort the list in place without recursion. + + Description: + Use mergesort, as for linked list this is a realistic solution. + Also, since this is aimed at embedded, care was taken to use iterative rather then recursive algorithm. + The sort can either return the list to original order (by idx) , + or use the data item to invoke other other algorithms and change the order of the list. + + Parameters: + list - list to be sorted. + cmp - cmp function to use + + Returns: + New head of the list. + + Note: + We have a special header for the list that will always be first, + but the algorithm could theoretically modify where the list starts. + + */ +list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res) { + list_head *p, *q, *e, *tail; + ee_s32 insize, nmerges, psize, qsize, i; + + insize = 1; + + while (1) { + p = list; + list = NULL; + tail = NULL; + + nmerges = 0; /* count number of merges we do in this pass */ + + while (p) { + nmerges++; /* there exists a merge to be done */ + /* step `insize' places along from p */ + q = p; + psize = 0; + for (i = 0; i < insize; i++) { + psize++; + q = q->next; + if (!q) break; + } + + /* if q hasn't fallen off end, we have two lists to merge */ + qsize = insize; + + /* now we have two lists; merge them */ + while (psize > 0 || (qsize > 0 && q)) { + + /* decide whether next element of merge comes from p or q */ + if (psize == 0) { + /* p is empty; e must come from q. */ + e = q; q = q->next; qsize--; + } else if (qsize == 0 || !q) { + /* q is empty; e must come from p. */ + e = p; p = p->next; psize--; + } else if (cmp(p->info,q->info,res) <= 0) { + /* First element of p is lower (or same); e must come from p. */ + e = p; p = p->next; psize--; + } else { + /* First element of q is lower; e must come from q. */ + e = q; q = q->next; qsize--; + } + + /* add the next element to the merged list */ + if (tail) { + tail->next = e; + } else { + list = e; + } + tail = e; + } + + /* now p has stepped `insize' places along, and q has too */ + p = q; + } + + tail->next = NULL; + + /* If we have done only one merge, we're finished. */ + if (nmerges <= 1) /* allow for nmerges==0, the empty list case */ + return list; + + /* Otherwise repeat, merging lists twice the size */ + insize *= 2; + } +#if COMPILER_REQUIRES_SORT_RETURN + return list; +#endif +} diff --git a/third-party/coremark/core_main.c b/third-party/coremark/core_main.c new file mode 100644 index 000000000..597783e08 --- /dev/null +++ b/third-party/coremark/core_main.c @@ -0,0 +1,369 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +/* File: core_main.c + This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results. +*/ +#include "coremark.h" +//#include +/* Function: iterate + Run the benchmark for a specified number of iterations. + + Operation: + For each type of benchmarked algorithm: + a - Initialize the data block for the algorithm. + b - Execute the algorithm N times. + + Returns: + NULL. +*/ +static ee_u16 list_known_crc[] = {(ee_u16)0xd4b0,(ee_u16)0x3340,(ee_u16)0x6a79,(ee_u16)0xe714,(ee_u16)0xe3c1}; +static ee_u16 matrix_known_crc[] = {(ee_u16)0xbe52,(ee_u16)0x1199,(ee_u16)0x5608,(ee_u16)0x1fd7,(ee_u16)0x0747}; +static ee_u16 state_known_crc[] = {(ee_u16)0x5e47,(ee_u16)0x39bf,(ee_u16)0xe5a4,(ee_u16)0x8e3a,(ee_u16)0x8d84}; +void *iterate(void *pres) { + ee_u32 i; + ee_u16 crc; + core_results *res=(core_results *)pres; + ee_u32 iterations=res->iterations; + res->crc=0; + res->crclist=0; + res->crcmatrix=0; + res->crcstate=0; + + for (i=0; icrc=crcu16(crc,res->crc); + crc=core_bench_list(res,-1); + res->crc=crcu16(crc,res->crc); + if (i==0) res->crclist=res->crc; + } + return NULL; +} + +#if (SEED_METHOD==SEED_ARG) +ee_s32 get_seed_args(int i, int argc, char *argv[]); +#define get_seed(x) (ee_s16)get_seed_args(x,argc,argv) +#define get_seed_32(x) get_seed_args(x,argc,argv) +#else /* via function or volatile */ +ee_s32 get_seed_32(int i); +#define get_seed(x) (ee_s16)get_seed_32(x) +#endif + +#if (MEM_METHOD==MEM_STATIC) +ee_u8 static_memblk[TOTAL_DATA_SIZE]; +#endif +char *mem_name[3] = {"Static","Heap","Stack"}; +/* Function: main + Main entry routine for the benchmark. + This function is responsible for the following steps: + + 1 - Initialize input seeds from a source that cannot be determined at compile time. + 2 - Initialize memory block for use. + 3 - Run and time the benchmark. + 4 - Report results, testing the validity of the output if the seeds are known. + + Arguments: + 1 - first seed : Any value + 2 - second seed : Must be identical to first for iterations to be identical + 3 - third seed : Any value, should be at least an order of magnitude less then the input size, but bigger then 32. + 4 - Iterations : Special, if set to 0, iterations will be automatically determined such that the benchmark will run between 10 to 100 secs + +*/ + +#if MAIN_HAS_NOARGC +MAIN_RETURN_TYPE core_mark(void) { + int argc=0; + char *argv[1]; +#else +MAIN_RETURN_TYPE core_mark(int argc, char *argv[]) { +#endif + ee_u16 i,j=0,num_algorithms=0; + ee_s16 known_id=-1,total_errors=0; + ee_u16 seedcrc=0; + CORE_TICKS total_time; + core_results results[MULTITHREAD]; +#if (MEM_METHOD==MEM_STACK) + ee_u8 stack_memblock[TOTAL_DATA_SIZE*MULTITHREAD]; +#endif + /* first call any initializations needed */ + portable_init(&(results[0].port), &argc, argv); + /* First some checks to make sure benchmark will run ok */ + if (sizeof(struct list_head_s)>128) { + ee_printf("list_head structure too big for comparable data!\n"); + return MAIN_RETURN_VAL; + } + results[0].seed1=get_seed(1); + results[0].seed2=get_seed(2); + results[0].seed3=get_seed(3); + results[0].iterations=get_seed_32(4); +#if CORE_DEBUG + results[0].iterations=1; +#endif + results[0].execs=get_seed_32(5); + if (results[0].execs==0) { /* if not supplied, execute all algorithms */ + results[0].execs=ALL_ALGORITHMS_MASK; + } + /* put in some default values based on one seed only for easy testing */ + if ((results[0].seed1==0) && (results[0].seed2==0) && (results[0].seed3==0)) { /* validation run */ + results[0].seed1=0; + results[0].seed2=0; + results[0].seed3=0x66; + } + if ((results[0].seed1==1) && (results[0].seed2==0) && (results[0].seed3==0)) { /* perfromance run */ + results[0].seed1=0x3415; + results[0].seed2=0x3415; + results[0].seed3=0x66; + } +#if (MEM_METHOD==MEM_STATIC) + results[0].memblock[0]=(void *)static_memblk; + results[0].size=TOTAL_DATA_SIZE; + results[0].err=0; + #if (MULTITHREAD>1) + #error "Cannot use a static data area with multiple contexts!" + #endif +#elif (MEM_METHOD==MEM_MALLOC) + for (i=0 ; i1) + if (default_num_contexts>MULTITHREAD) { + default_num_contexts=MULTITHREAD; + } + for (i=0 ; i=0) { + for (i=0 ; i 0) + ee_printf("Iterations/Sec : %f\n",default_num_contexts*results[0].iterations/time_in_secs(total_time)); +#else + ee_printf("Total time (secs): %d\n",time_in_secs(total_time)); + if (time_in_secs(total_time) > 0) + ee_printf("Iterations/Sec : %d\n",default_num_contexts*results[0].iterations/time_in_secs(total_time)); +#endif + if (time_in_secs(total_time) < 10) { + ee_printf("ERROR! Must execute for at least 10 secs for a valid result!\n"); + total_errors++; + } + + ee_printf("Iterations : %lu\n", (long unsigned) default_num_contexts*results[0].iterations); + ee_printf("Compiler version : %s\n",COMPILER_VERSION); + ee_printf("Compiler flags : %s\n",COMPILER_FLAGS); +#if (MULTITHREAD>1) + ee_printf("Parallel %s : %d\n",PARALLEL_METHOD,default_num_contexts); +#endif + ee_printf("Memory location : %s\n",MEM_LOCATION); + /* output for verification */ + ee_printf("seedcrc : 0x%04x\n",seedcrc); + if (results[0].execs & ID_LIST) + for (i=0 ; i1) + ee_printf(" / %d:%s",default_num_contexts,PARALLEL_METHOD); +#endif + ee_printf("\n"); + } +#else + if (known_id==3) { + ee_printf("CoreMark 1.0 : %d / %s %s",default_num_contexts*results[0].iterations/time_in_secs(total_time),COMPILER_VERSION,COMPILER_FLAGS); +#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC) + ee_printf(" / %s",MEM_LOCATION); +#else + ee_printf(" / %s",mem_name[MEM_METHOD]); +#endif + +#if (MULTITHREAD>1) + ee_printf(" / %d:%s",default_num_contexts,PARALLEL_METHOD); +#endif + ee_printf("\n"); + } +#endif + } + if (total_errors>0) + ee_printf("Errors detected\n"); + if (total_errors<0) + ee_printf("Cannot validate operation for these seed values, please compare with results on a known platform.\n"); + +#if (MEM_METHOD==MEM_MALLOC) + for (i=0 ; i>(from)) & (~(0xffffffff << (to)))) + +#if CORE_DEBUG +void printmat(MATDAT *A, ee_u32 N, char *name) { + ee_u32 i,j; + ee_printf("Matrix %s [%dx%d]:\n",name,N,N); + for (i=0; i N times, + changing the matrix values slightly by a constant amount each time. +*/ +ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc) { + ee_u32 N=p->N; + MATRES *C=p->C; + MATDAT *A=p->A; + MATDAT *B=p->B; + MATDAT val=(MATDAT)seed; + + crc=crc16(matrix_test(N,C,A,B,val),crc); + + return crc; +} + +/* Function: matrix_test + Perform matrix manipulation. + + Parameters: + N - Dimensions of the matrix. + C - memory for result matrix. + A - input matrix + B - operator matrix (not changed during operations) + + Returns: + A CRC value that captures all results calculated in the function. + In particular, crc of the value calculated on the result matrix + after each step by . + + Operation: + + 1 - Add a constant value to all elements of a matrix. + 2 - Multiply a matrix by a constant. + 3 - Multiply a matrix by a vector. + 4 - Multiply a matrix by a matrix. + 5 - Add a constant value to all elements of a matrix. + + After the last step, matrix A is back to original contents. +*/ +ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val) { + ee_u16 crc=0; + MATDAT clipval=matrix_big(val); + + matrix_add_const(N,A,val); /* make sure data changes */ +#if CORE_DEBUG + printmat(A,N,"matrix_add_const"); +#endif + matrix_mul_const(N,C,A,val); + crc=crc16(matrix_sum(N,C,clipval),crc); +#if CORE_DEBUG + printmatC(C,N,"matrix_mul_const"); +#endif + matrix_mul_vect(N,C,A,B); + crc=crc16(matrix_sum(N,C,clipval),crc); +#if CORE_DEBUG + printmatC(C,N,"matrix_mul_vect"); +#endif + matrix_mul_matrix(N,C,A,B); + crc=crc16(matrix_sum(N,C,clipval),crc); +#if CORE_DEBUG + printmatC(C,N,"matrix_mul_matrix"); +#endif + matrix_mul_matrix_bitextract(N,C,A,B); + crc=crc16(matrix_sum(N,C,clipval),crc); +#if CORE_DEBUG + printmatC(C,N,"matrix_mul_matrix_bitextract"); +#endif + + matrix_add_const(N,A,-val); /* return matrix to initial value */ + return crc; +} + +/* Function : matrix_init + Initialize the memory block for matrix benchmarking. + + Parameters: + blksize - Size of memory to be initialized. + memblk - Pointer to memory block. + seed - Actual values chosen depend on the seed parameter. + p - pointers to containing initialized matrixes. + + Returns: + Matrix dimensions. + + Note: + The seed parameter MUST be supplied from a source that cannot be determined at compile time +*/ +ee_u32 core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p) { + ee_u32 N=0; + MATDAT *A; + MATDAT *B; + ee_s32 order=1; + MATDAT val; + ee_u32 i=0,j=0; + if (seed==0) + seed=1; + while (jA=A; + p->B=B; + p->C=(MATRES *)align_mem(B+N*N); + p->N=N; +#if CORE_DEBUG + printmat(A,N,"A"); + printmat(B,N,"B"); +#endif + return N; +} + +/* Function: matrix_sum + Calculate a function that depends on the values of elements in the matrix. + + For each element, accumulate into a temporary variable. + + As long as this value is under the parameter clipval, + add 1 to the result if the element is bigger then the previous. + + Otherwise, reset the accumulator and add 10 to the result. +*/ +ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) { + MATRES tmp=0,prev=0,cur=0; + ee_s16 ret=0; + ee_u32 i,j; + for (i=0; iclipval) { + ret+=10; + tmp=0; + } else { + ret += (cur>prev) ? 1 : 0; + } + prev=cur; + } + } + return ret; +} + +/* Function: matrix_mul_const + Multiply a matrix by a constant. + This could be used as a scaler for instance. +*/ +void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) { + ee_u32 i,j; + for (i=0; i +#include +//#include +#include "coremark.h" + +#if VALIDATION_RUN + volatile ee_s32 seed1_volatile=0x3415; + volatile ee_s32 seed2_volatile=0x3415; + volatile ee_s32 seed3_volatile=0x66; +#endif +#if PERFORMANCE_RUN + volatile ee_s32 seed1_volatile=0x0; + volatile ee_s32 seed2_volatile=0x0; + volatile ee_s32 seed3_volatile=0x66; +#endif +#if PROFILE_RUN + volatile ee_s32 seed1_volatile=0x8; + volatile ee_s32 seed2_volatile=0x8; + volatile ee_s32 seed3_volatile=0x8; +#endif + volatile ee_s32 seed4_volatile=ITERATIONS; + volatile ee_s32 seed5_volatile=0; +/* Porting : Timing functions + How to capture time and convert to seconds must be ported to whatever is supported by the platform. + e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc. + Sample implementation for standard time.h and windows.h definitions included. +*/ +/* Define : TIMER_RES_DIVIDER + Divider to trade off timer resolution and total time that can be measured. + + Use lower values to increase resolution, but make sure that overflow does not occur. + If there are issues with the return value overflowing, increase this value. + */ +#define NSECS_PER_SEC RT_TICK_PER_SECOND +#define CORETIMETYPE uint32_t +#define GETMYTIME(_t) (*_t=rt_tick_get()) +#define MYTIMEDIFF(fin,ini) ((fin)-(ini)) +#define TIMER_RES_DIVIDER 1 +#define SAMPLE_TIME_IMPLEMENTATION 1 +#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER) + +/** Define Host specific (POSIX), or target specific global time variables. */ +static CORETIMETYPE start_time_val, stop_time_val; + +/* Function : start_time + This function will be called right before starting the timed portion of the benchmark. + + Implementation may be capturing a system timer (as implemented in the example code) + or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0. +*/ +void start_time(void) { + GETMYTIME(&start_time_val ); +} +/* Function : stop_time + This function will be called right after ending the timed portion of the benchmark. + + Implementation may be capturing a system timer (as implemented in the example code) + or other system parameters - e.g. reading the current value of cpu cycles counter. +*/ +void stop_time(void) { + GETMYTIME(&stop_time_val ); +} +/* Function : get_time + Return an abstract "ticks" number that signifies time on the system. + + Actual value returned may be cpu cycles, milliseconds or any other value, + as long as it can be converted to seconds by . + This methodology is taken to accomodate any hardware or simulated platform. + The sample implementation returns millisecs by default, + and the resolution is controlled by +*/ +CORE_TICKS get_time(void) { + CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); + return elapsed; +} +/* Function : time_in_secs + Convert the value returned by get_time to seconds. + + The type is used to accomodate systems with no support for floating point. + Default implementation implemented by the EE_TICKS_PER_SEC macro above. +*/ +secs_ret time_in_secs(CORE_TICKS ticks) { + secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; + return retval; +} + +ee_u32 default_num_contexts=MULTITHREAD; + +/* Function : portable_init + Target specific initialization code + Test for some common mistakes. +*/ +void portable_init(core_portable *p, int *argc, char *argv[]) +{ + ee_printf("Benchmark started, please make sure it runs for at least 10s.\n\n"); + if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) { + ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n"); + } + if (sizeof(ee_u32) != 4) { + ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); + } + p->portable_id=1; +} +/* Function : portable_fini + Target specific final code +*/ +void portable_fini(core_portable *p) +{ + p->portable_id=0; +} + +#if USE_PTHREAD +ee_u8 +core_start_parallel(core_results *res) +{ + return (ee_u8)pthread_create( + &(res->port.thread), NULL, iterate, (void *)res); +} +ee_u8 +core_stop_parallel(core_results *res) +{ + void *retval; + return (ee_u8)pthread_join(res->port.thread, &retval); +} +#endif diff --git a/third-party/coremark/core_portme.h b/third-party/coremark/core_portme.h new file mode 100644 index 000000000..21bd43aa3 --- /dev/null +++ b/third-party/coremark/core_portme.h @@ -0,0 +1,221 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +/* Topic : Description + This file contains configuration constants required to execute on different platforms +*/ +#ifndef CORE_PORTME_H +#define CORE_PORTME_H + +//#include + +#define COREMARK_ITERATIONS 36000 +#define ITERATIONS COREMARK_ITERATIONS + +/************************/ +/* Data types and settings */ +/************************/ +/* Configuration : HAS_FLOAT + Define to 1 if the platform supports floating point. +*/ +#ifndef HAS_FLOAT +#define HAS_FLOAT CORE_MARK_HAS_FLOAT +#endif +/* Configuration : HAS_TIME_H + Define to 1 if platform has the time.h header file, + and implementation of functions thereof. +*/ +#ifndef HAS_TIME_H +#define HAS_TIME_H 1 +#endif +/* Configuration : USE_CLOCK + Define to 1 if platform has the time.h header file, + and implementation of functions thereof. +*/ +#ifndef USE_CLOCK +#define USE_CLOCK 1 +#endif +/* Configuration : HAS_STDIO + Define to 1 if the platform has stdio.h. +*/ +#ifndef HAS_STDIO +#define HAS_STDIO 1 +#endif +/* Configuration : HAS_PRINTF + Define to 1 if the platform has stdio.h and implements the printf function. +*/ +#ifndef HAS_PRINTF +#define HAS_PRINTF 1 +#endif + +/* Configuration : CORE_TICKS + Define type of return from the timing functions. + */ +#include +typedef clock_t CORE_TICKS; + +/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION + Initialize these strings per platform +*/ +#ifndef COMPILER_VERSION + #ifdef __GNUC__ + #define COMPILER_VERSION "GCC"__VERSION__ + #else + #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" + #endif +#endif +#ifndef COMPILER_FLAGS + #define COMPILER_FLAGS "" /* "Please put compiler flags here (e.g. -o3)" */ +#endif +#ifndef MEM_LOCATION + #define MEM_LOCATION "STACK" +#endif + +/* Data Types : + To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in . + + *Imprtant* : + ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!! +*/ +typedef signed short ee_s16; +typedef unsigned short ee_u16; +typedef signed int ee_s32; +typedef double ee_f32; +typedef unsigned char ee_u8; +typedef unsigned int ee_u32; +typedef ee_u32 ee_ptr_int; +typedef size_t ee_size_t; +/* align_mem : + This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks. +*/ +#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3)) + +/* Configuration : SEED_METHOD + Defines method to get seed values that cannot be computed at compile time. + + Valid values : + SEED_ARG - from command line. + SEED_FUNC - from a system function. + SEED_VOLATILE - from volatile variables. +*/ +#ifndef SEED_METHOD +#define SEED_METHOD SEED_VOLATILE +#endif + +/* Configuration : MEM_METHOD + Defines method to get a block of memry. + + Valid values : + MEM_MALLOC - for platforms that implement malloc and have malloc.h. + MEM_STATIC - to use a static memory array. + MEM_STACK - to allocate the data block on the stack (NYI). +*/ +#ifndef MEM_METHOD +#define MEM_METHOD MEM_STACK +#endif + +/* Configuration : MULTITHREAD + Define for parallel execution + + Valid values : + 1 - only one context (default). + N>1 - will execute N copies in parallel. + + Note : + If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined. + + Two sample implementations are provided. Use or to enable them. + + It is valid to have a different implementation of and in , + to fit a particular architecture. +*/ +#ifndef MULTITHREAD +#define MULTITHREAD 1 +#define USE_PTHREAD 0 +#define USE_FORK 0 +#define USE_SOCKET 0 +#endif + +/* Configuration : MAIN_HAS_NOARGC + Needed if platform does not support getting arguments to main. + + Valid values : + 0 - argc/argv to main is supported + 1 - argc/argv to main is not supported + + Note : + This flag only matters if MULTITHREAD has been defined to a value greater then 1. +*/ +#ifndef MAIN_HAS_NOARGC +#define MAIN_HAS_NOARGC 1 +#endif + +/* Configuration : MAIN_HAS_NORETURN + Needed if platform does not support returning a value from main. + + Valid values : + 0 - main returns an int, and return value will be 0. + 1 - platform does not support returning a value from main +*/ +#ifndef MAIN_HAS_NORETURN +#define MAIN_HAS_NORETURN 0 +#endif + +/* Variable : default_num_contexts + Not used for this simple port, must cintain the value 1. +*/ +extern ee_u32 default_num_contexts; + +#if (MULTITHREAD > 1) +#if USE_PTHREAD +#include +#define PARALLEL_METHOD "PThreads" +#endif /* USE_PTHREAD */ +#endif /* MULTITHREAD > 1 */ + +typedef struct CORE_PORTABLE_S { +#if (MULTITHREAD > 1) +#if USE_PTHREAD + pthread_t thread; +#endif /* Method for multithreading */ +#endif /* MULTITHREAD>1 */ + ee_u8 portable_id; +} core_portable; + +/* target specific init/fini */ +void portable_init(core_portable *p, int *argc, char *argv[]); +void portable_fini(core_portable *p); + +#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && !defined(VALIDATION_RUN) +#if (TOTAL_DATA_SIZE==1200) +#define PROFILE_RUN 1 +#elif (TOTAL_DATA_SIZE==2000) +#define PERFORMANCE_RUN 1 +#else +#define VALIDATION_RUN 1 +#endif +#endif + +#if (MULTITHREAD > 1) +#if USE_PTHREAD +#include +#define PARALLEL_METHOD "PThreads" +#endif /* Method for multithreading */ +#endif /* MULTITHREAD > 1 */ + +#endif /* CORE_PORTME_H */ diff --git a/third-party/coremark/core_state.c b/third-party/coremark/core_state.c new file mode 100644 index 000000000..b6bae076f --- /dev/null +++ b/third-party/coremark/core_state.c @@ -0,0 +1,277 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +#include "coremark.h" +/* local functions */ +enum CORE_STATE core_state_transition( ee_u8 **instr , ee_u32 *transition_count); + +/* +Topic: Description + Simple state machines like this one are used in many embedded products. + + For more complex state machines, sometimes a state transition table implementation is used instead, + trading speed of direct coding for ease of maintenance. + + Since the main goal of using a state machine in CoreMark is to excercise the switch/if behaviour, + we are using a small moore machine. + + In particular, this machine tests type of string input, + trying to determine whether the input is a number or something else. + (see core_state.png). +*/ + +/* Function: core_bench_state + Benchmark function + + Go over the input twice, once direct, and once after introducing some corruption. +*/ +ee_u16 core_bench_state(ee_u32 blksize, ee_u8 *memblock, + ee_s16 seed1, ee_s16 seed2, ee_s16 step, ee_u16 crc) +{ + ee_u32 final_counts[NUM_CORE_STATES]; + ee_u32 track_counts[NUM_CORE_STATES]; + ee_u8 *p=memblock; + ee_u32 i; + + +#if CORE_DEBUG + ee_printf("State Bench: %d,%d,%d,%04x\n",seed1,seed2,step,crc); +#endif + for (i=0; i0) { + for(i=0;i>3) & 0x3]; + next=4; + break; + case 3: /* float */ + case 4: /* float */ + buf=floatpat[(seed>>3) & 0x3]; + next=8; + break; + case 5: /* scientific */ + case 6: /* scientific */ + buf=scipat[(seed>>3) & 0x3]; + next=8; + break; + case 7: /* invalid */ + buf=errpat[(seed>>3) & 0x3]; + next=8; + break; + default: /* Never happen, just to make some compilers happy */ + break; + } + } + size++; + while (total='0') & (c<='9')) ? 1 : 0; + return retval; +} + +/* Function: core_state_transition + Actual state machine. + + The state machine will continue scanning until either: + 1 - an invalid input is detcted. + 2 - a valid number has been detected. + + The input pointer is updated to point to the end of the token, and the end state is returned (either specific format determined or invalid). +*/ + +enum CORE_STATE core_state_transition( ee_u8 **instr , ee_u32 *transition_count) { + ee_u8 *str=*instr; + ee_u8 NEXT_SYMBOL; + enum CORE_STATE state=CORE_START; + for( ; *str && state != CORE_INVALID; str++ ) { + NEXT_SYMBOL = *str; + if (NEXT_SYMBOL==',') /* end of this input */ { + str++; + break; + } + switch(state) { + case CORE_START: + if(ee_isdigit(NEXT_SYMBOL)) { + state = CORE_INT; + } + else if( NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-' ) { + state = CORE_S1; + } + else if( NEXT_SYMBOL == '.' ) { + state = CORE_FLOAT; + } + else { + state = CORE_INVALID; + transition_count[CORE_INVALID]++; + } + transition_count[CORE_START]++; + break; + case CORE_S1: + if(ee_isdigit(NEXT_SYMBOL)) { + state = CORE_INT; + transition_count[CORE_S1]++; + } + else if( NEXT_SYMBOL == '.' ) { + state = CORE_FLOAT; + transition_count[CORE_S1]++; + } + else { + state = CORE_INVALID; + transition_count[CORE_S1]++; + } + break; + case CORE_INT: + if( NEXT_SYMBOL == '.' ) { + state = CORE_FLOAT; + transition_count[CORE_INT]++; + } + else if(!ee_isdigit(NEXT_SYMBOL)) { + state = CORE_INVALID; + transition_count[CORE_INT]++; + } + break; + case CORE_FLOAT: + if( NEXT_SYMBOL == 'E' || NEXT_SYMBOL == 'e' ) { + state = CORE_S2; + transition_count[CORE_FLOAT]++; + } + else if(!ee_isdigit(NEXT_SYMBOL)) { + state = CORE_INVALID; + transition_count[CORE_FLOAT]++; + } + break; + case CORE_S2: + if( NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-' ) { + state = CORE_EXPONENT; + transition_count[CORE_S2]++; + } + else { + state = CORE_INVALID; + transition_count[CORE_S2]++; + } + break; + case CORE_EXPONENT: + if(ee_isdigit(NEXT_SYMBOL)) { + state = CORE_SCIENTIFIC; + transition_count[CORE_EXPONENT]++; + } + else { + state = CORE_INVALID; + transition_count[CORE_EXPONENT]++; + } + break; + case CORE_SCIENTIFIC: + if(!ee_isdigit(NEXT_SYMBOL)) { + state = CORE_INVALID; + transition_count[CORE_INVALID]++; + } + break; + default: + break; + } + } + *instr=str; + return state; +} diff --git a/third-party/coremark/core_util.c b/third-party/coremark/core_util.c new file mode 100644 index 000000000..37297e840 --- /dev/null +++ b/third-party/coremark/core_util.c @@ -0,0 +1,210 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +#include "coremark.h" +/* Function: get_seed + Get a values that cannot be determined at compile time. + + Since different embedded systems and compilers are used, 3 different methods are provided: + 1 - Using a volatile variable. This method is only valid if the compiler is forced to generate code that + reads the value of a volatile variable from memory at run time. + Please note, if using this method, you would need to modify core_portme.c to generate training profile. + 2 - Command line arguments. This is the preferred method if command line arguments are supported. + 3 - System function. If none of the first 2 methods is available on the platform, + a system function which is not a stub can be used. + + e.g. read the value on GPIO pins connected to switches, or invoke special simulator functions. +*/ +#if (SEED_METHOD==SEED_VOLATILE) + extern volatile ee_s32 seed1_volatile; + extern volatile ee_s32 seed2_volatile; + extern volatile ee_s32 seed3_volatile; + extern volatile ee_s32 seed4_volatile; + extern volatile ee_s32 seed5_volatile; + ee_s32 get_seed_32(int i) { + ee_s32 retval; + switch (i) { + case 1: + retval=seed1_volatile; + break; + case 2: + retval=seed2_volatile; + break; + case 3: + retval=seed3_volatile; + break; + case 4: + retval=seed4_volatile; + break; + case 5: + retval=seed5_volatile; + break; + default: + retval=0; + break; + } + return retval; + } +#elif (SEED_METHOD==SEED_ARG) +ee_s32 parseval(char *valstring) { + ee_s32 retval=0; + ee_s32 neg=1; + int hexmode=0; + if (*valstring == '-') { + neg=-1; + valstring++; + } + if ((valstring[0] == '0') && (valstring[1] == 'x')) { + hexmode=1; + valstring+=2; + } + /* first look for digits */ + if (hexmode) { + while (((*valstring >= '0') && (*valstring <= '9')) || ((*valstring >= 'a') && (*valstring <= 'f'))) { + ee_s32 digit=*valstring-'0'; + if (digit>9) + digit=10+*valstring-'a'; + retval*=16; + retval+=digit; + valstring++; + } + } else { + while ((*valstring >= '0') && (*valstring <= '9')) { + ee_s32 digit=*valstring-'0'; + retval*=10; + retval+=digit; + valstring++; + } + } + /* now add qualifiers */ + if (*valstring=='K') + retval*=1024; + if (*valstring=='M') + retval*=1024*1024; + + retval*=neg; + return retval; +} + +ee_s32 get_seed_args(int i, int argc, char *argv[]) { + if (argc>i) + return parseval(argv[i]); + return 0; +} + +#elif (SEED_METHOD==SEED_FUNC) +/* If using OS based function, you must define and implement the functions below in core_portme.h and core_portme.c ! */ +ee_s32 get_seed_32(int i) { + ee_s32 retval; + switch (i) { + case 1: + retval=portme_sys1(); + break; + case 2: + retval=portme_sys2(); + break; + case 3: + retval=portme_sys3(); + break; + case 4: + retval=portme_sys4(); + break; + case 5: + retval=portme_sys5(); + break; + default: + retval=0; + break; + } + return retval; +} +#endif + +/* Function: crc* + Service functions to calculate 16b CRC code. + +*/ +ee_u16 crcu8(ee_u8 data, ee_u16 crc ) +{ + ee_u8 i=0,x16=0,carry=0; + + for (i = 0; i < 8; i++) + { + x16 = (ee_u8)((data & 1) ^ ((ee_u8)crc & 1)); + data >>= 1; + + if (x16 == 1) + { + crc ^= 0x4002; + carry = 1; + } + else + carry = 0; + crc >>= 1; + if (carry) + crc |= 0x8000; + else + crc &= 0x7fff; + } + return crc; +} +ee_u16 crcu16(ee_u16 newval, ee_u16 crc) { + crc=crcu8( (ee_u8) (newval) ,crc); + crc=crcu8( (ee_u8) ((newval)>>8) ,crc); + return crc; +} +ee_u16 crcu32(ee_u32 newval, ee_u16 crc) { + crc=crc16((ee_s16) newval ,crc); + crc=crc16((ee_s16) (newval>>16) ,crc); + return crc; +} +ee_u16 crc16(ee_s16 newval, ee_u16 crc) { + return crcu16((ee_u16)newval, crc); +} + +ee_u8 check_data_types() { + ee_u8 retval=0; + if (sizeof(ee_u8) != 1) { + ee_printf("ERROR: ee_u8 is not an 8b datatype!\n"); + retval++; + } + if (sizeof(ee_u16) != 2) { + ee_printf("ERROR: ee_u16 is not a 16b datatype!\n"); + retval++; + } + if (sizeof(ee_s16) != 2) { + ee_printf("ERROR: ee_s16 is not a 16b datatype!\n"); + retval++; + } + if (sizeof(ee_s32) != 4) { + ee_printf("ERROR: ee_s32 is not a 32b datatype!\n"); + retval++; + } + if (sizeof(ee_u32) != 4) { + ee_printf("ERROR: ee_u32 is not a 32b datatype!\n"); + retval++; + } + if (sizeof(ee_ptr_int) != sizeof(int *)) { + ee_printf("ERROR: ee_ptr_int is not a datatype that holds an int pointer!\n"); + retval++; + } + if (retval>0) { + ee_printf("ERROR: Please modify the datatypes in core_portme.h!\n"); + } + return retval; +} diff --git a/third-party/coremark/coremark.c b/third-party/coremark/coremark.c new file mode 100644 index 000000000..713fcaf29 --- /dev/null +++ b/third-party/coremark/coremark.c @@ -0,0 +1,25 @@ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-09 08:39:08 + * @LastEditTime: 2021-07-09 08:50:06 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#include + +int core_mark_entry() +{ + printf("start coremark testing......\r\n"); + + extern int core_mark(void); + core_mark(); + + return 0; +} + diff --git a/third-party/coremark/coremark.h b/third-party/coremark/coremark.h new file mode 100644 index 000000000..e1b898261 --- /dev/null +++ b/third-party/coremark/coremark.h @@ -0,0 +1,174 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +/* Topic: Description + This file contains declarations of the various benchmark functions. +*/ + +/* Configuration: TOTAL_DATA_SIZE + Define total size for data algorithms will operate on +*/ +#ifndef TOTAL_DATA_SIZE +#define TOTAL_DATA_SIZE 2*1000 +#endif + +#define SEED_ARG 0 +#define SEED_FUNC 1 +#define SEED_VOLATILE 2 + +#define MEM_STATIC 0 +#define MEM_MALLOC 1 +#define MEM_STACK 2 + +#include "core_portme.h" + +#if HAS_STDIO +#include +#endif +#if HAS_PRINTF +#define ee_printf printf +#endif + +/* Actual benchmark execution in iterate */ +void *iterate(void *pres); + +/* Typedef: secs_ret + For machines that have floating point support, get number of seconds as a double. + Otherwise an unsigned int. +*/ +#if HAS_FLOAT +typedef double secs_ret; +#else +typedef ee_u32 secs_ret; +#endif + +#if MAIN_HAS_NORETURN +#define MAIN_RETURN_VAL +#define MAIN_RETURN_TYPE void +#else +#define MAIN_RETURN_VAL 0 +#define MAIN_RETURN_TYPE int +#endif + +void start_time(void); +void stop_time(void); +CORE_TICKS get_time(void); +secs_ret time_in_secs(CORE_TICKS ticks); + +/* Misc useful functions */ +ee_u16 crcu8(ee_u8 data, ee_u16 crc); +ee_u16 crc16(ee_s16 newval, ee_u16 crc); +ee_u16 crcu16(ee_u16 newval, ee_u16 crc); +ee_u16 crcu32(ee_u32 newval, ee_u16 crc); +ee_u8 check_data_types(void); +void *portable_malloc(ee_size_t size); +void portable_free(void *p); +ee_s32 parseval(char *valstring); + +/* Algorithm IDS */ +#define ID_LIST (1<<0) +#define ID_MATRIX (1<<1) +#define ID_STATE (1<<2) +#define ALL_ALGORITHMS_MASK (ID_LIST|ID_MATRIX|ID_STATE) +#define NUM_ALGORITHMS 3 + +/* list data structures */ +typedef struct list_data_s { + ee_s16 data16; + ee_s16 idx; +} list_data; + +typedef struct list_head_s { + struct list_head_s *next; + struct list_data_s *info; +} list_head; + + +/*matrix benchmark related stuff */ +#define MATDAT_INT 1 +#if MATDAT_INT +typedef ee_s16 MATDAT; +typedef ee_s32 MATRES; +#else +typedef ee_f16 MATDAT; +typedef ee_f32 MATRES; +#endif + +typedef struct MAT_PARAMS_S { + int N; + MATDAT *A; + MATDAT *B; + MATRES *C; +} mat_params; + +/* state machine related stuff */ +/* List of all the possible states for the FSM */ +typedef enum CORE_STATE { + CORE_START=0, + CORE_INVALID, + CORE_S1, + CORE_S2, + CORE_INT, + CORE_FLOAT, + CORE_EXPONENT, + CORE_SCIENTIFIC, + NUM_CORE_STATES +} core_state_e ; + + +/* Helper structure to hold results */ +typedef struct RESULTS_S { + /* inputs */ + ee_s16 seed1; /* Initializing seed */ + ee_s16 seed2; /* Initializing seed */ + ee_s16 seed3; /* Initializing seed */ + void *memblock[4]; /* Pointer to safe memory location */ + ee_u32 size; /* Size of the data */ + ee_u32 iterations; /* Number of iterations to execute */ + ee_u32 execs; /* Bitmask of operations to execute */ + struct list_head_s *list; + mat_params mat; + /* outputs */ + ee_u16 crc; + ee_u16 crclist; + ee_u16 crcmatrix; + ee_u16 crcstate; + ee_s16 err; + /* ultithread specific */ + core_portable port; +} core_results; + +/* Multicore execution handling */ +#if (MULTITHREAD>1) +ee_u8 core_start_parallel(core_results *res); +ee_u8 core_stop_parallel(core_results *res); +#endif + +/* list benchmark functions */ +list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed); +ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx); + +/* state benchmark functions */ +void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p); +ee_u16 core_bench_state(ee_u32 blksize, ee_u8 *memblock, + ee_s16 seed1, ee_s16 seed2, ee_s16 step, ee_u16 crc); + +/* matrix benchmark functions */ +ee_u32 core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p); +ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc); + diff --git a/third-party/coremark/coremark_entry.h b/third-party/coremark/coremark_entry.h new file mode 100644 index 000000000..a2dfc37bd --- /dev/null +++ b/third-party/coremark/coremark_entry.h @@ -0,0 +1,19 @@ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-09 08:50:39 + * @LastEditTime: 2021-07-09 08:52:12 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#ifndef CORE_MARK_ENTRY_H +#define CORE_MARK_ENTRY_H + +int core_mark_entry(); + +#endif #CORE_MARK_ENTRY_H \ No newline at end of file diff --git a/third-party/third-party.mk b/third-party/third-party.mk new file mode 100644 index 000000000..8405c4028 --- /dev/null +++ b/third-party/third-party.mk @@ -0,0 +1,6 @@ +THIRDP_CUR_DIR := $(SDK_ROOT)/third-party + +ifdef CONFIG_USE_COREMARK + SRC_DIR += $(THIRDP_CUR_DIR)/coremark + INC_DIR += $(THIRDP_CUR_DIR)/coremark +endif #CONFIG_USE_COREMARK \ No newline at end of file -- Gitee From 75f9241b57f0c104aedb6457f59775d98f06bb41 Mon Sep 17 00:00:00 2001 From: huanghe Date: Mon, 12 Jul 2021 15:47:26 +0800 Subject: [PATCH 08/12] =?UTF-8?q?=E5=A2=9E=E5=8A=A0kconfig=20=E4=B8=AD=20?= =?UTF-8?q?=E9=99=84=E5=8A=A0=E5=A4=B4=E6=96=87=E4=BB=B6=E5=8A=9F=E8=83=BD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .vscode/settings.json | 3 +- .../example/aarch32_cache_mmu_wr/sdkconfig.h | 2 +- .../example/aarch32_cache_mmu_wr/test_cache.c | 3 +- .../example/aarch32_cache_mmu_wr/test_mmu.c | 4 +- baremetal/example/aarch32_timer_irq/sdkconfig | 6 + .../example/aarch32_timer_irq/sdkconfig.h | 98 ++++++++++++++-- .../example/aarch32_timer_irq/sdkconfig.old | 10 +- baremetal/example/aarch32_uart_irq/sdkconfig | 9 ++ .../example/aarch32_uart_irq/sdkconfig.h | 106 +++++++++++++++--- .../example/aarch32_uart_irq/sdkconfig.old | 28 +++-- bsp/arch/armv8/aarch32/generic_timer.c | 1 + bsp/common/ft_debug.c | 2 +- bsp/common/ft_debug.h | 6 +- bsp/drivers/gic/gicv3_arrch32/gicv3.c | 1 + bsp/drivers/usart/Kconfig | 2 +- lib/Kconfiglib/genconfig.py | 69 +++++++++++- lib/Kconfiglib/menuconfig.py | 1 - lib/nostdlib/printf-stdarg.c | 1 - 18 files changed, 297 insertions(+), 55 deletions(-) diff --git a/.vscode/settings.json b/.vscode/settings.json index 9f8492057..c4edc9c52 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -18,6 +18,7 @@ "early_uart.h": "c", "message_buffer.h": "c", "*.c_a64": "c", - "*.c_old": "c" + "*.c_old": "c", + "*.h_s": "cpp" } } \ No newline at end of file diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h index 012549a74..cc1a9119f 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h @@ -3,7 +3,7 @@ #define CONFIG_TARGET_F2000_4 1 #define CONFIG_ENVI_UBUNTU_20_04 1 #define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1` #define CONFIG_LOG_ERROR 1 #define CONFIG_USE_SPI 1 #define CONFIG_SPI_POLLING_MODE 1 diff --git a/baremetal/example/aarch32_cache_mmu_wr/test_cache.c b/baremetal/example/aarch32_cache_mmu_wr/test_cache.c index 79ba21d63..bb1488f24 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/test_cache.c +++ b/baremetal/example/aarch32_cache_mmu_wr/test_cache.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 10:36:06 - * @LastEditTime: 2021-07-12 14:02:53 + * @LastEditTime: 2021-07-12 14:33:56 * @Description:  This files is for * * @Modify History: @@ -15,6 +15,7 @@ #include #include "cache.h" #include "aarch32.h" +#include "sdkconfig.h" #include "ft_debug.h" #define DATA_LENGTH 128 diff --git a/baremetal/example/aarch32_cache_mmu_wr/test_mmu.c b/baremetal/example/aarch32_cache_mmu_wr/test_mmu.c index 5d6e30fc3..441b103e2 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/test_mmu.c +++ b/baremetal/example/aarch32_cache_mmu_wr/test_mmu.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 10:36:56 - * @LastEditTime: 2021-06-29 10:43:36 + * @LastEditTime: 2021-07-12 14:40:43 * @Description:  This files is for * * @Modify History: @@ -15,6 +15,4 @@ void MMUTest() { - - } \ No newline at end of file diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig b/baremetal/example/aarch32_timer_irq/sdkconfig index 114ad191b..fdfdd2031 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig +++ b/baremetal/example/aarch32_timer_irq/sdkconfig @@ -56,6 +56,7 @@ CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set # end of Common Configuration # @@ -93,3 +94,8 @@ CONFIG_ENABLE_Pl011_UART=y CONFIG_USE_NOSTD_LIBC=y # CONFIG_USE_LIBC is not set # end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig.h b/baremetal/example/aarch32_timer_irq/sdkconfig.h index 31000411d..c135688b3 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig.h +++ b/baremetal/example/aarch32_timer_irq/sdkconfig.h @@ -1,12 +1,88 @@ +#ifndef SDK_CONFIG_H__ +#define SDK_CONFIG_H__ + +/* Project Configuration */ + +/* FT2000-4 AARCH32 Baremetal Configuration */ + #define CONFIG_TARGET_NAME "ft2004_baremetal" -#define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_F2000_4 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_USART 1 -#define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_NOSTD_LIBC 1 +/* end of FT2000-4 AARCH32 Baremetal Configuration */ +/* end of Project Configuration */ + +/* Target Setting */ + +#define CONFIG_TARGET_ARMV8_AARCH32 +/* CONFIG_TARGET_ARMV8_AARCH64 is not set */ +/* CONFIG_TARGET_ARMV7 is not set */ +#define CONFIG_TARGET_F2000_4 +/* CONFIG_TARGET_AARCH32_QEMU is not set */ +/* CONFIG_TARGET_AARCH64_QEMU is not set */ +/* CONFIG_TARGET_E2000 is not set */ +/* end of Target Setting */ + +/* Building Option */ + +#define CONFIG_ENVI_UBUNTU_20_04 +/* CONFIG_ENVI_WINDOWS10_MINGW is not set */ + +/* Cross-Compiler Setting */ + +#define CONFIG_COMPILER_NO_STD_STARUP +/* CONFIG_USE_EXT_COMPILER is not set */ +/* end of Cross-Compiler Setting */ + +/* GNU linker */ + +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD +/* CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set */ +/* CONFIG_QEMU_AARCH32_RAM_LD is not set */ +/* end of GNU linker */ +/* end of Building Option */ + +/* Board Configuration */ + +/* Common Configuration */ + +/* CONFIG_LOG_VERBOS is not set */ +/* CONFIG_LOG_DEBUG is not set */ +/* CONFIG_LOG_INFO is not set */ +/* CONFIG_LOG_WARN is not set */ +#define CONFIG_LOG_ERROR +/* CONFIG_LOG_NONE is not set */ +/* end of Common Configuration */ + +/* Components Configuration */ + +/* CONFIG_USE_SPI is not set */ +/* CONFIG_USE_QSPI is not set */ +#define CONFIG_USE_GIC + +/* Gic Configuration */ + +#define CONFIG_EBABLE_GICV3 +/* end of Gic Configuration */ +#define CONFIG_USE_USART + +/* Usart Configuration */ + +#define CONFIG_ENABLE_Pl011_UART +/* end of Usart Configuration */ +/* end of Components Configuration */ + +/* Arch Configuration */ + +/* CONFIG_USE_CACHE is not set */ +/* end of Arch Configuration */ +/* end of Board Configuration */ + +/* Library Configuration */ + +#define CONFIG_USE_NOSTD_LIBC +/* CONFIG_USE_LIBC is not set */ +/* end of Library Configuration */ + +/* Standalone Third-Party Configuration */ + +/* end of Standalone Third-Party Configuration */ + +#endif diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig.old b/baremetal/example/aarch32_timer_irq/sdkconfig.old index 5908f83fd..114ad191b 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig.old +++ b/baremetal/example/aarch32_timer_irq/sdkconfig.old @@ -11,7 +11,7 @@ CONFIG_TARGET_NAME="ft2004_baremetal" # end of Project Configuration # -# Build Target +# Target Setting # CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set @@ -20,10 +20,10 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -39,12 +39,10 @@ CONFIG_COMPILER_NO_STD_STARUP=y # GNU linker # CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig b/baremetal/example/aarch32_uart_irq/sdkconfig index 3f8d35b31..02ae58fb4 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig +++ b/baremetal/example/aarch32_uart_irq/sdkconfig @@ -33,6 +33,8 @@ CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_COMPILER_NO_STD_STARUP=y # CONFIG_USE_EXT_COMPILER is not set +CONFIG_USE_SOFT_FLOAT=y +# CONFIG_USE_HARD_FLOAT is not set # end of Cross-Compiler Setting # @@ -56,6 +58,7 @@ CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set # end of Common Configuration # @@ -95,3 +98,9 @@ CONFIG_USE_MMU=y # CONFIG_USE_NOSTD_LIBC is not set CONFIG_USE_LIBC=y # end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# CONFIG_USE_COREMARK is not set +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig.h b/baremetal/example/aarch32_uart_irq/sdkconfig.h index be78f3ff5..9a9a51341 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig.h +++ b/baremetal/example/aarch32_uart_irq/sdkconfig.h @@ -1,15 +1,93 @@ +#ifndef SDK_CONFIG_H__ +#define SDK_CONFIG_H__ + +/* Project Configuration */ + +/* FT2000-4 AARCH32 Baremetal Configuration */ + #define CONFIG_TARGET_NAME "ft2004_baremetal" -#define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_F2000_4 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_USART 1 -#define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_CACHE 1 -#define CONFIG_USE_L3CACHE 1 -#define CONFIG_USE_MMU 1 -#define CONFIG_USE_LIBC 1 +/* end of FT2000-4 AARCH32 Baremetal Configuration */ +/* end of Project Configuration */ + +/* Target Setting */ + +#define CONFIG_TARGET_ARMV8_AARCH32 +/* CONFIG_TARGET_ARMV8_AARCH64 is not set */ +/* CONFIG_TARGET_ARMV7 is not set */ +#define CONFIG_TARGET_F2000_4 +/* CONFIG_TARGET_AARCH32_QEMU is not set */ +/* CONFIG_TARGET_AARCH64_QEMU is not set */ +/* CONFIG_TARGET_E2000 is not set */ +/* end of Target Setting */ + +/* Building Option */ + +#define CONFIG_ENVI_UBUNTU_20_04 +/* CONFIG_ENVI_WINDOWS10_MINGW is not set */ + +/* Cross-Compiler Setting */ + +#define CONFIG_COMPILER_NO_STD_STARUP +/* CONFIG_USE_EXT_COMPILER is not set */ +#define CONFIG_USE_SOFT_FLOAT +/* CONFIG_USE_HARD_FLOAT is not set */ +/* end of Cross-Compiler Setting */ + +/* GNU linker */ + +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD +/* CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set */ +/* CONFIG_QEMU_AARCH32_RAM_LD is not set */ +/* end of GNU linker */ +/* end of Building Option */ + +/* Board Configuration */ + +/* Common Configuration */ + +/* CONFIG_LOG_VERBOS is not set */ +/* CONFIG_LOG_DEBUG is not set */ +/* CONFIG_LOG_INFO is not set */ +/* CONFIG_LOG_WARN is not set */ +#define CONFIG_LOG_ERROR +/* CONFIG_LOG_NONE is not set */ +/* end of Common Configuration */ + +/* Components Configuration */ + +/* CONFIG_USE_SPI is not set */ +/* CONFIG_USE_QSPI is not set */ +#define CONFIG_USE_GIC + +/* Gic Configuration */ + +#define CONFIG_EBABLE_GICV3 +/* end of Gic Configuration */ +#define CONFIG_USE_USART + +/* Usart Configuration */ + +#define CONFIG_ENABLE_Pl011_UART +/* end of Usart Configuration */ +/* end of Components Configuration */ + +/* Arch Configuration */ + +#define CONFIG_USE_CACHE +#define CONFIG_USE_L3CACHE +#define CONFIG_USE_MMU +/* end of Arch Configuration */ +/* end of Board Configuration */ + +/* Library Configuration */ + +/* CONFIG_USE_NOSTD_LIBC is not set */ +#define CONFIG_USE_LIBC +/* end of Library Configuration */ + +/* Standalone Third-Party Configuration */ + +/* CONFIG_USE_COREMARK is not set */ +/* end of Standalone Third-Party Configuration */ + +#endif diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig.old b/baremetal/example/aarch32_uart_irq/sdkconfig.old index 5908f83fd..0eaed0d0e 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig.old +++ b/baremetal/example/aarch32_uart_irq/sdkconfig.old @@ -11,7 +11,7 @@ CONFIG_TARGET_NAME="ft2004_baremetal" # end of Project Configuration # -# Build Target +# Target Setting # CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set @@ -20,10 +20,10 @@ CONFIG_TARGET_F2000_4=y # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set # CONFIG_TARGET_E2000 is not set -# end of Build Target +# end of Target Setting # -# General Setting +# Building Option # CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_ENVI_WINDOWS10_MINGW is not set @@ -33,18 +33,18 @@ CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_COMPILER_NO_STD_STARUP=y # CONFIG_USE_EXT_COMPILER is not set +CONFIG_USE_SOFT_FLOAT=y +# CONFIG_USE_HARD_FLOAT is not set # end of Cross-Compiler Setting # # GNU linker # CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set # CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set # CONFIG_QEMU_AARCH32_RAM_LD is not set # end of GNU linker -# end of General Setting +# end of Building Option # # Board Configuration @@ -58,6 +58,7 @@ CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set # end of Common Configuration # @@ -79,19 +80,28 @@ CONFIG_USE_USART=y # Usart Configuration # CONFIG_ENABLE_Pl011_UART=y +CONFIG_BAUD_RATE=1152000 # end of Usart Configuration # end of Components Configuration # # Arch Configuration # -# CONFIG_USE_CACHE is not set +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y # end of Arch Configuration # end of Board Configuration # # Library Configuration # -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y # end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# CONFIG_USE_COREMARK is not set +# end of Standalone Third-Party Configuration diff --git a/bsp/arch/armv8/aarch32/generic_timer.c b/bsp/arch/armv8/aarch32/generic_timer.c index 8ef86ca79..0d7a9ed15 100644 --- a/bsp/arch/armv8/aarch32/generic_timer.c +++ b/bsp/arch/armv8/aarch32/generic_timer.c @@ -15,6 +15,7 @@ #include "parameters.h" #include "generic_timer.h" #include "aarch32.h" +#include "sdkconfig.h" #include "ft_debug.h" //#define ENABLE_A32GT_DEBUG diff --git a/bsp/common/ft_debug.c b/bsp/common/ft_debug.c index fcd743e44..bb99987d9 100644 --- a/bsp/common/ft_debug.c +++ b/bsp/common/ft_debug.c @@ -4,7 +4,7 @@  * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-04-25 16:44:23 - * @LastEditTime: 2021-07-07 17:49:33 + * @LastEditTime: 2021-07-12 14:34:13 * @Description:  Description of file * @Modify History: * * * Ver   Who        Date         Changes diff --git a/bsp/common/ft_debug.h b/bsp/common/ft_debug.h index 0bfcfff0b..012e6a449 100644 --- a/bsp/common/ft_debug.h +++ b/bsp/common/ft_debug.h @@ -4,7 +4,7 @@  * SPDX-License-Identifier: Apache-2.0.  * * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-06-25 15:01:19 + * @LastEditTime: 2021-07-12 14:35:56 * @Description:  This files is for debug functions * * @Modify History: @@ -15,9 +15,7 @@ #ifndef BSP_COMMON_FT_DEBUG_H #define BSP_COMMON_FT_DEBUG_H #include -#include "sdkconfig.h" #include "ft_types.h" - typedef enum { FT_LOG_NONE, /*!< No log output */ @@ -45,7 +43,7 @@ typedef enum #define LOG_COLOR_V /* select debug log level */ -#ifdef CONFIG_LOG_ERROR +#ifdef CONFIG_LOG_ERROR #define LOG_LOCAL_LEVEL FT_LOG_ERROR #endif diff --git a/bsp/drivers/gic/gicv3_arrch32/gicv3.c b/bsp/drivers/gic/gicv3_arrch32/gicv3.c index 6c41e4560..206285a59 100644 --- a/bsp/drivers/gic/gicv3_arrch32/gicv3.c +++ b/bsp/drivers/gic/gicv3_arrch32/gicv3.c @@ -19,6 +19,7 @@ #include "gicv3.h" #include "cp15.h" #include +#include "sdkconfig.h" #include "ft_debug.h" #ifndef RT_CPUS_NR diff --git a/bsp/drivers/usart/Kconfig b/bsp/drivers/usart/Kconfig index f7ac9611d..f6ec3ad6c 100644 --- a/bsp/drivers/usart/Kconfig +++ b/bsp/drivers/usart/Kconfig @@ -4,5 +4,5 @@ menu "Usart Configuration" bool prompt "Use Pl011 uart" default n - + endmenu \ No newline at end of file diff --git a/lib/Kconfiglib/genconfig.py b/lib/Kconfiglib/genconfig.py index 44bebdde9..cfe93606b 100644 --- a/lib/Kconfiglib/genconfig.py +++ b/lib/Kconfiglib/genconfig.py @@ -35,12 +35,79 @@ headers. Remember to export the variable to the environment. import argparse import os import sys +import re import kconfiglib DEFAULT_SYNC_DEPS_PATH = "deps/" +def is_pkg_special_config(config_str): + ''' judge if it's CONFIG_PKG_XX_PATH or CONFIG_PKG_XX_VER''' + + if type(config_str) == type('a'): + if config_str.startswith("PKG_") and (config_str.endswith('_PATH') or config_str.endswith('_VER')): + return True + return False + + +def mk_sdkconfig(filename): + try: + config = open(filename, 'r') + except: + print('open config:%s failed' % filename) + return + + sdkconfig = open('sdkconfig.h', 'w') + sdkconfig.write('#ifndef SDK_CONFIG_H__\n') + sdkconfig.write('#define SDK_CONFIG_H__\n\n') + + empty_line = 1 + + for line in config: + line = line.lstrip(' ').replace('\n', '').replace('\r', '') + + if len(line) == 0: + continue + + if line[0] == '#': + if len(line) == 1: + if empty_line: + continue + + sdkconfig.write('\n') + empty_line = 1 + continue + + # if line.startswith('# CONFIG_'): + # line = ' ' + line[9:] + # else: + line = line[1:] + sdkconfig.write('/*%s */\n' % line) + + empty_line = 0 + else: + empty_line = 0 + setting = line.split('=') + if len(setting) >= 2: + # if setting[0].startswith('CONFIG_'): + # setting[0] = setting[0][7:] + + # remove CONFIG_PKG_XX_PATH or CONFIG_PKG_XX_VER + if is_pkg_special_config(setting[0]): + continue + + if setting[1] == 'y': + sdkconfig.write('#define %s\n' % setting[0]) + else: + sdkconfig.write('#define %s %s\n' % (setting[0], re.findall(r"^.*?=(.*)$",line)[0])) + + if os.path.isfile('sdkconfig_project.h'): + sdkconfig.write('#include "sdkconfig_project.h"\n') + + sdkconfig.write('\n') + sdkconfig.write('#endif\n') + sdkconfig.close() def main(): parser = argparse.ArgumentParser( @@ -139,7 +206,7 @@ only supported for backwards compatibility). with _open_write(args.env_list) as f: for env_var in kconf.env_vars: f.write("{}={}\n".format(env_var, os.environ[env_var])) - + mk_sdkconfig('sdkconfig') def _open_write(path): # Python 2/3 compatibility. io.open() is available on both, but makes diff --git a/lib/Kconfiglib/menuconfig.py b/lib/Kconfiglib/menuconfig.py index 7e765d36f..4b2128bad 100644 --- a/lib/Kconfiglib/menuconfig.py +++ b/lib/Kconfiglib/menuconfig.py @@ -662,7 +662,6 @@ def _style_attr(fg_color, bg_color, attribs, color_attribs={}): def _main(): menuconfig(standard_kconfig(__doc__)) - def menuconfig(kconf): """ Launches the configuration interface, returning after the user exits. diff --git a/lib/nostdlib/printf-stdarg.c b/lib/nostdlib/printf-stdarg.c index 9d869f9f1..67b6d780b 100644 --- a/lib/nostdlib/printf-stdarg.c +++ b/lib/nostdlib/printf-stdarg.c @@ -22,7 +22,6 @@ #define putchar(c) OutByte(c) */ #include -// #include "sdkconfig.h" #include "early_uart.h" #define putchar(c) OutByte(c) -- Gitee From b9a901807fa1ccb6480c0ebf6e0a336fadbe79b1 Mon Sep 17 00:00:00 2001 From: huanghe Date: Mon, 12 Jul 2021 15:49:04 +0800 Subject: [PATCH 09/12] readly to upload --- doc/ChangeLog.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/doc/ChangeLog.md b/doc/ChangeLog.md index 0b7209816..24bc91d1a 100644 --- a/doc/ChangeLog.md +++ b/doc/ChangeLog.md @@ -13,6 +13,10 @@ Change Log sinc v0.0.2 - aarch32_math_test +## tools + +- add sdkconfig.h header + # Phytium Standalone SDK v0.0.2 ChangeLog Change Log sinc v0.0.1 -- Gitee From 07593f4b269cedbd6905ab4e64aa6e68bd7db613 Mon Sep 17 00:00:00 2001 From: huanghe Date: Tue, 13 Jul 2021 16:27:58 +0800 Subject: [PATCH 10/12] =?UTF-8?q?=20=E4=BF=AE=E6=94=B9=20e2000=20aarch32?= =?UTF-8?q?=20mmu=20=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitee/ISSUE_TEMPLATE.zh-CN.md | 26 +- .gitee/PULL_REQUEST_TEMPLATE.zh-CN.md | 28 +- .gitignore | 120 +- .vscode/launch.json | 58 +- .vscode/settings.json | 49 +- Kconfig | 176 +- LICENSE | 402 +- .../example/aarch32_cache_mmu_wr/README.md | 102 +- .../example/aarch32_cache_mmu_wr/sdkconfig | 198 +- .../example/aarch32_cache_mmu_wr/sdkconfig.h | 30 +- .../aarch32_cache_mmu_wr/sdkconfig.old | 198 +- .../ft2004_baremetal.map_o | 4348 ++--- .../example/aarch32_hello_world/sdkconfig | 17 + .../example/aarch32_hello_world/sdkconfig.h | 112 +- .../example/aarch32_hello_world/sdkconfig.old | 12 +- baremetal/example/aarch32_math_test/sdkconfig | 194 +- .../example/aarch32_math_test/sdkconfig.h | 30 +- .../example/aarch32_math_test/sdkconfig.old | 196 +- .../example/aarch32_qemu_debug/sdkconfig | 178 +- .../example/aarch32_qemu_debug/sdkconfig.h | 18 +- baremetal/example/aarch32_timer_irq/README.md | 102 +- baremetal/example/aarch32_timer_irq/sdkconfig | 202 +- .../example/aarch32_timer_irq/sdkconfig.h | 176 +- .../example/aarch32_timer_irq/sdkconfig.old | 190 +- baremetal/example/aarch32_uart_irq/README.md | 102 +- baremetal/example/aarch32_uart_irq/sdkconfig | 8 +- .../example/aarch32_uart_irq/sdkconfig.h | 7 +- .../example/aarch32_uart_irq/sdkconfig.old | 213 +- .../example/aarch64_uart_irq_send/Kconfig | 32 +- .../example/aarch64_uart_irq_send/Makefile | 34 +- .../example/aarch64_uart_irq_send/main.c | 214 +- .../example/aarch64_uart_irq_send/sdkconfig | 194 +- .../example/aarch64_uart_irq_send/sdkconfig.h | 30 +- .../aarch64_uart_irq_send/sdkconfig.old | 194 +- .../example/aarch64_uart_irq_send/uart1.c | 126 +- bsp/Kconfig | 12 +- bsp/arch/Kconfig | 54 +- bsp/arch/armv8/aarch32/aarch32.h | 806 +- bsp/arch/armv8/aarch32/cp15.h | 80 +- bsp/arch/armv8/aarch32/fsleep.h | 42 +- bsp/arch/armv8/aarch32/gcc/context.S | 22 +- bsp/arch/armv8/aarch32/gcc/cp15.S | 282 +- bsp/arch/armv8/aarch32/gcc/crt0.S | 14 +- bsp/arch/armv8/aarch32/gcc/smccc-call.S | 72 +- bsp/arch/armv8/aarch32/gcc/start.S | 680 +- bsp/arch/armv8/aarch32/gcc/vector.S | 246 +- bsp/arch/armv8/aarch32/generic_timer.c | 230 +- bsp/arch/armv8/aarch32/generic_timer.h | 76 +- .../armv8/aarch32/platform/E2000/early_uart.c | 64 +- .../armv8/aarch32/platform/E2000/early_uart.h | 60 +- .../armv8/aarch32/platform/E2000/parameters.c | 28 +- .../armv8/aarch32/platform/E2000/parameters.h | 186 +- .../aarch32/platform/ft2004/early_uart.c | 64 +- .../aarch32/platform/ft2004/early_uart.h | 60 +- .../aarch32/platform/ft2004/parameters.h | 216 +- .../armv8/aarch32/platform/qemu/early_uart.c | 66 +- .../armv8/aarch32/platform/qemu/early_uart.h | 62 +- bsp/arch/armv8/aarch32/psci.c | 154 +- bsp/arch/armv8/aarch32/psci.h | 62 +- bsp/arch/armv8/aarch32/smc.h | 84 +- bsp/arch/armv8/aarch64/aarch64.c | 626 +- bsp/arch/armv8/aarch64/aarch64.h | 472 +- bsp/arch/armv8/aarch64/arm-smccc.h | 210 +- bsp/arch/armv8/aarch64/cache.c | 384 +- bsp/arch/armv8/aarch64/cache.h | 110 +- bsp/arch/armv8/aarch64/exception.c | 64 +- bsp/arch/armv8/aarch64/exception.h | 212 +- bsp/arch/armv8/aarch64/fsleep.c | 68 +- bsp/arch/armv8/aarch64/fsleep.h | 42 +- bsp/arch/armv8/aarch64/gcc/_uart_test.c | 160 +- bsp/arch/armv8/aarch64/gcc/cache.S | 528 +- bsp/arch/armv8/aarch64/gcc/smccc-call.S | 52 +- bsp/arch/armv8/aarch64/gcc/start.S | 284 +- bsp/arch/armv8/aarch64/gcc/tlb.S | 52 +- bsp/arch/armv8/aarch64/gcc/vector.S | 890 +- bsp/arch/armv8/aarch64/generic_timer.c | 122 +- bsp/arch/armv8/aarch64/generic_timer.h | 56 +- bsp/arch/armv8/aarch64/mmu.c | 762 +- bsp/arch/armv8/aarch64/mmu.h | 350 +- bsp/arch/armv8/aarch64/platform/e2000/_cpu.c | 76 +- bsp/arch/armv8/aarch64/platform/e2000/_cpu.h | 32 +- .../armv8/aarch64/platform/e2000/_cpu_asm.S | 20 +- .../armv8/aarch64/platform/e2000/early_uart.c | 24 +- .../armv8/aarch64/platform/e2000/early_uart.h | 34 +- .../armv8/aarch64/platform/e2000/parameters.c | 68 +- .../armv8/aarch64/platform/e2000/parameters.h | 134 +- bsp/arch/armv8/aarch64/platform/ft2004/_cpu.c | 76 +- bsp/arch/armv8/aarch64/platform/ft2004/_cpu.h | 34 +- .../armv8/aarch64/platform/ft2004/_cpu_asm.S | 20 +- .../aarch64/platform/ft2004/early_uart.c | 40 +- .../aarch64/platform/ft2004/early_uart.h | 34 +- .../aarch64/platform/ft2004/parameters.c | 68 +- .../aarch64/platform/ft2004/parameters.h | 150 +- .../aarch64/platform/qemu_aarch64/_cpu.c | 40 +- .../aarch64/platform/qemu_aarch64/_cpu.h | 32 +- .../aarch64/platform/qemu_aarch64/_cpu_asm.S | 20 +- .../platform/qemu_aarch64/_mmu_global.c | 68 +- .../platform/qemu_aarch64/_parameters.h | 42 +- .../platform/qemu_aarch64/early_uart.c | 82 +- .../platform/qemu_aarch64/early_uart.h | 34 +- .../platform/qemu_aarch64/monitor_uart.c_old | 110 +- bsp/arch/armv8/aarch64/psw.c | 68 +- bsp/arch/armv8/aarch64/psw.h | 82 +- bsp/arch/common/kernel.h | 326 +- bsp/arch/common/linkage.h | 136 +- bsp/arch/common/macro.h | 48 +- bsp/bsp.mk | 230 +- bsp/common/Kconfig | 54 +- bsp/common/ft_assert.c | 86 +- bsp/common/ft_assert.h | 320 +- bsp/common/ft_debug.c | 134 +- bsp/common/ft_debug.h | 198 +- bsp/common/ft_error_code.h | 135 +- bsp/common/ft_io.h | 200 +- bsp/common/ft_types.h | 144 +- bsp/common/interrupt.c | 626 +- bsp/common/interrupt.h | 146 +- bsp/common/trap.c | 554 +- bsp/common/trap.h | 126 +- bsp/drivers/Kconfig | 105 +- bsp/drivers/gic/Kconfig | 10 +- bsp/drivers/gic/gicv3_arrch32/gicv3.c | 1468 +- bsp/drivers/gic/gicv3_arrch32/gicv3.h | 438 +- bsp/drivers/gic/gicv3_arrch64/gicv3.c | 1450 +- bsp/drivers/gic/gicv3_arrch64/gicv3.h | 350 +- bsp/drivers/gic/gicv3_arrch64/gicv3_aliases.h | 204 +- bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.S | 820 +- bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.h | 176 +- bsp/drivers/gpio/Kconfig | 8 + bsp/drivers/gpio/f_gpio/f_gpio.c | 137 + bsp/drivers/gpio/f_gpio/f_gpio.h | 91 + bsp/drivers/gpio/f_gpio/f_gpio_g.c | 31 + bsp/drivers/gpio/f_gpio/f_gpio_hw.h | 52 + bsp/drivers/gpio/f_gpio/f_gpio_intr.c | 103 + bsp/drivers/gpio/f_gpio/f_gpio_sinit.c | 40 + bsp/drivers/qspi/Kconfig | 28 +- bsp/drivers/spi/Kconfig | 32 +- bsp/drivers/usart/Kconfig | 14 +- bsp/drivers/usart/pl011_uart/pl011_uart.c | 690 +- bsp/drivers/usart/pl011_uart/pl011_uart.h | 220 +- bsp/drivers/usart/pl011_uart/pl011_uart_g.c | 68 +- bsp/drivers/usart/pl011_uart/pl011_uart_hw.c | 130 +- bsp/drivers/usart/pl011_uart/pl011_uart_hw.h | 442 +- .../usart/pl011_uart/pl011_uart_intr.c | 404 +- .../usart/pl011_uart/pl011_uart_options.c | 204 +- .../usart/pl011_uart/pl011_uart_selftest.c | 26 +- .../usart/pl011_uart/pl011_uart_sinit.c | 82 +- configs/aarch32_defconfig | 194 +- configs/aarch64_defconfig | 194 +- doc/baremetal.dio | 216 +- export.sh | 99 - install.sh | 2 +- lib/Kconfig | 30 +- lib/Kconfiglib/.config | 68 +- lib/Kconfiglib/.gitignore | 8 +- lib/Kconfiglib/Kconfig | 204 +- lib/Kconfiglib/LICENSE.txt | 10 +- lib/Kconfiglib/defconfig.py | 86 +- lib/Kconfiglib/genconfig.py | 442 +- lib/Kconfiglib/kconfiglib.py | 14320 ++++++++-------- lib/Kconfiglib/listnewconfig.py | 152 +- lib/Kconfiglib/makefile.patch | 96 +- lib/Kconfiglib/menuconfig.py | 6554 +++---- lib/Kconfiglib/oldconfig.py | 492 +- lib/Kconfiglib/olddefconfig.py | 56 +- lib/Kconfiglib/savedefconfig.py | 98 +- lib/Kconfiglib/setconfig.py | 184 +- lib/Kconfiglib/setup.cfg | 14 +- lib/Kconfiglib/setup.py | 192 +- lib/Kconfiglib/testsuite.py | 6406 +++---- lib/lib.mk | 34 +- lib/libc/retarget.c | 210 +- lib/nostdlib/nostdlib.c | 580 +- lib/nostdlib/printf-stdarg.c | 640 +- lib/nostdlib/printf-stdarg.h | 38 +- make/buildinfo.mk | 126 +- make/complier.mk | 382 +- make/ld.mk | 34 +- make/ld/Kconfig | 58 +- make/ld/e2000_ft2004_aarch64_ram.ld | 224 +- make/menuconfig.mk | 72 +- make/packsource.mk | 90 +- make/preconfig.mk | 62 +- scripts/kill_qemu_instance.sh | 30 +- scripts/mount2vxbox.sh | 32 +- scripts/release_tag.sh | 40 +- 186 files changed, 31719 insertions(+), 31206 deletions(-) create mode 100644 bsp/drivers/gpio/Kconfig create mode 100644 bsp/drivers/gpio/f_gpio/f_gpio.c create mode 100644 bsp/drivers/gpio/f_gpio/f_gpio.h create mode 100644 bsp/drivers/gpio/f_gpio/f_gpio_g.c create mode 100644 bsp/drivers/gpio/f_gpio/f_gpio_hw.h create mode 100644 bsp/drivers/gpio/f_gpio/f_gpio_intr.c create mode 100644 bsp/drivers/gpio/f_gpio/f_gpio_sinit.c delete mode 100644 export.sh diff --git a/.gitee/ISSUE_TEMPLATE.zh-CN.md b/.gitee/ISSUE_TEMPLATE.zh-CN.md index f09d98dde..0992470db 100644 --- a/.gitee/ISSUE_TEMPLATE.zh-CN.md +++ b/.gitee/ISSUE_TEMPLATE.zh-CN.md @@ -1,13 +1,13 @@ -### 该问题是怎么引起的？ - - - -### 重现步骤 - - - -### 报错信息 - - - - +### 该问题是怎么引起的？ + + + +### 重现步骤 + + + +### 报错信息 + + + + diff --git a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md index 66d433205..ec91e162c 100644 --- a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md +++ b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md @@ -1,14 +1,14 @@ -### 相关的Issue - - -### 原因（目的、解决的问题等） - - -### 描述（做了什么，变更了什么） - - -### 测试用例（新增、改动、可能影响的功能） - - - - +### 相关的Issue + + +### 原因（目的、解决的问题等） + + +### 描述（做了什么，变更了什么） + + +### 测试用例（新增、改动、可能影响的功能） + + + + diff --git a/.gitignore b/.gitignore index 80a123412..396b9d58b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,61 +1,61 @@ -# Prerequisites -*.d -*.uimg -*.img - -# Object files -*.o -*.ko -*.obj -*.elf - -# Linker output -*.ilk -*.map -*.exp - -# Precompiled Headers -*.gch -*.pch - -# Libraries -*.lib -*.a -*.la -*.lo - -# Shared objects (inc. Windows DLLs) -*.dll -*.so -*.so.* -*.dylib - -# Executables -*.exe -*.out -*.app -*.i*86 -*.x86_64 -*.hex -*.bin -*.dis -app* - -# Debug files -*.dSYM/ -*.su -*.idb -*.pdb - -# Kernel Module Compile Results -*.mod* -*.cmd -.tmp_versions/ -modules.order -Module.symvers -Mkfile.old -dkms.conf - -# Download gcc compiler -/tools/gcc-*/* +# Prerequisites +*.d +*.uimg +*.img + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex +*.bin +*.dis +app* + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf + +# Download gcc compiler +/tools/gcc-*/* /tools/gcc-* \ No newline at end of file diff --git a/.vscode/launch.json b/.vscode/launch.json index 96efa6cb5..f19f943dd 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -1,30 +1,30 @@ -{ - // Use IntelliSense to learn about possible attributes. - // Hover to view descriptions of existing attributes. - // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 - "version": "0.2.0", - "configurations": [ - { - "name": "(gdb) Launch", - "type": "cppdbg", - "request": "launch", - "program": "${workspaceFolder}/baremetal/qemu_genric_timer_irq/qemu_generic_irq_test", # 需要调试的二进制文件 - "args": [], - "stopAtEntry": true, - "cwd": "${workspaceFolder}", - "environment": [], - "externalConsole": true, - "MIMode": "gdb", - "miDebuggerPath": "/usr/local/bin/aarch64-linux-gnu-gdb", # gdb 工具的位置 - // "miDebuggerPath": "D:/ubuntu/rootfs/usr/local/bin/aarch64-linux-gnu-gdb", # gdb 工具的位置 - "miDebuggerServerAddress": "127.0.0.1:1234", # gdb 开启之后的端口号 - "setupCommands": [ - { - "description": "Enable pretty-printing for gdb", - "text": "-enable-pretty-printing", - "ignoreFailures": true - } - ] - } - ] +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "(gdb) Launch", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/baremetal/qemu_genric_timer_irq/qemu_generic_irq_test", # 需要调试的二进制文件 + "args": [], + "stopAtEntry": true, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": true, + "MIMode": "gdb", + "miDebuggerPath": "/usr/local/bin/aarch64-linux-gnu-gdb", # gdb 工具的位置 + // "miDebuggerPath": "D:/ubuntu/rootfs/usr/local/bin/aarch64-linux-gnu-gdb", # gdb 工具的位置 + "miDebuggerServerAddress": "127.0.0.1:1234", # gdb 开启之后的端口号 + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + } + ] + } + ] } \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json index c4edc9c52..e18156714 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,24 +1,27 @@ -{ - "files.associations": { - "irq_test.h": "c", - "parameters.h": "c", - "ft_gicv3.h": "c", - "ft_debug.h": "c", - "ft_types.h": "c", - "gicv3.h": "c", - "exception.h": "c", - "generic_timer.h": "c", - "freertos.h": "c", - "fsleep.h": "c", - "printf-stdarg.h": "c", - "ft_assert.h": "c", - "ft_os_uart.h": "c", - "event_groups.h": "c", - "pl011_uart.h": "c", - "early_uart.h": "c", - "message_buffer.h": "c", - "*.c_a64": "c", - "*.c_old": "c", - "*.h_s": "cpp" - } +{ + "files.associations": { + "irq_test.h": "c", + "parameters.h": "c", + "ft_gicv3.h": "c", + "ft_debug.h": "c", + "ft_types.h": "c", + "gicv3.h": "c", + "exception.h": "c", + "generic_timer.h": "c", + "freertos.h": "c", + "fsleep.h": "c", + "printf-stdarg.h": "c", + "ft_assert.h": "c", + "ft_os_uart.h": "c", + "event_groups.h": "c", + "pl011_uart.h": "c", + "early_uart.h": "c", + "message_buffer.h": "c", + "*.c_a64": "c", + "*.c_old": "c", + "*.h_s": "cpp", + "f_gpio_hw.h": "c", + "pl011_uart_hw.h": "c", + "f_gpio.h": "c" + } } \ No newline at end of file diff --git a/Kconfig b/Kconfig index 83a7c92d9..cfaf464ae 100644 --- a/Kconfig +++ b/Kconfig @@ -1,89 +1,89 @@ -# entry of menuconfig -# mainmenu "Phytium Standalone SDK Configuration" - - menu "Target Setting" - choice BUILD_TARGET_ARCH_TYPE - prompt "Arch" - default TARGET_ARMV8_AARCH32 - help - Select arch for build - config TARGET_ARMV8_AARCH32 - bool "Armv8 Aarch32" - config TARGET_ARMV8_AARCH64 - bool "Armv8 Aarch64" - config TARGET_ARMV7 - bool "Armv7" - endchoice # BUILD_TARGET_ARCH_TYPE - - choice BUILD_TARGET_CHIP_TYPE - prompt "Chip" - default TARGET_AARCH32_QEMU - help - Select chip type for build - - config TARGET_F2000_4 - bool "FT2000-4" - config TARGET_AARCH32_QEMU - bool "QEMU-AARCH32(V9-Express)" - config TARGET_AARCH64_QEMU - bool "QEMU-AARCH64" - config TARGET_E2000 - bool "E2000" - endchoice # BUILD_TARGET_CHIP_TYPE - endmenu - - menu "Building Option" - choice SDK_ENVI_TYPE - prompt "SDK Develope Platfrom" - default ENVI_UBUNTU_20_04 - help - SDK development host environment type. - - config ENVI_UBUNTU_20_04 - bool - prompt "Ubuntu 20.04" - config ENVI_WINDOWS10_MINGW - bool - prompt "MinGW on Windows10" - endchoice # SDK_ENVI_TYPE - - menu "Cross-Compiler Setting" - config COMPILER_NO_STD_STARUP - bool "Non-Use GCC Provide Startup Files" - default y if TARGET_BARE_METAL - help - Select if do not want to gcc provide startup file - - config USE_EXT_COMPILER - bool "Use User-Specified Compiler" - default n - - config EXT_COMPILER_PREFIX - depends on USE_EXT_COMPILER - string "" - default "arm-none-eabi-" if TARGET_ARMV8_AARCH32 - default "aarch64-none-elf-" if TARGET_ARMV8_AARCH64 - - choice USE_FLOAT - prompt "Add Float Support" - depends on USE_LIBC - default USE_SOFT_FLOAT - help - Select Soft/Hard Float. - - config USE_SOFT_FLOAT - bool - prompt "Soft Float" - config USE_HARD_FLOAT - bool - prompt "Hard Float" - endchoice #USE_FLOAT - endmenu - - source "$(SDK_ROOT)/make/ld/Kconfig" - endmenu - -# add all kconfig source files, but specify their depends -source "$(SDK_ROOT)/bsp/Kconfig" -source "$(SDK_ROOT)/lib/Kconfig" +# entry of menuconfig +# mainmenu "Phytium Standalone SDK Configuration" + + menu "Target Setting" + choice BUILD_TARGET_ARCH_TYPE + prompt "Arch" + default TARGET_ARMV8_AARCH32 + help + Select arch for build + config TARGET_ARMV8_AARCH32 + bool "Armv8 Aarch32" + config TARGET_ARMV8_AARCH64 + bool "Armv8 Aarch64" + config TARGET_ARMV7 + bool "Armv7" + endchoice # BUILD_TARGET_ARCH_TYPE + + choice BUILD_TARGET_CHIP_TYPE + prompt "Chip" + default TARGET_AARCH32_QEMU + help + Select chip type for build + + config TARGET_F2000_4 + bool "FT2000-4" + config TARGET_AARCH32_QEMU + bool "QEMU-AARCH32(V9-Express)" + config TARGET_AARCH64_QEMU + bool "QEMU-AARCH64" + config TARGET_E2000 + bool "E2000" + endchoice # BUILD_TARGET_CHIP_TYPE + endmenu + + menu "Building Option" + choice SDK_ENVI_TYPE + prompt "SDK Develope Platfrom" + default ENVI_UBUNTU_20_04 + help + SDK development host environment type. + + config ENVI_UBUNTU_20_04 + bool + prompt "Ubuntu 20.04" + config ENVI_WINDOWS10_MINGW + bool + prompt "MinGW on Windows10" + endchoice # SDK_ENVI_TYPE + + menu "Cross-Compiler Setting" + config COMPILER_NO_STD_STARUP + bool "Non-Use GCC Provide Startup Files" + default y if TARGET_BARE_METAL + help + Select if do not want to gcc provide startup file + + config USE_EXT_COMPILER + bool "Use User-Specified Compiler" + default n + + config EXT_COMPILER_PREFIX + depends on USE_EXT_COMPILER + string "" + default "arm-none-eabi-" if TARGET_ARMV8_AARCH32 + default "aarch64-none-elf-" if TARGET_ARMV8_AARCH64 + + choice USE_FLOAT + prompt "Add Float Support" + depends on USE_LIBC + default USE_SOFT_FLOAT + help + Select Soft/Hard Float. + + config USE_SOFT_FLOAT + bool + prompt "Soft Float" + config USE_HARD_FLOAT + bool + prompt "Hard Float" + endchoice #USE_FLOAT + endmenu + + source "$(SDK_ROOT)/make/ld/Kconfig" + endmenu + +# add all kconfig source files, but specify their depends +source "$(SDK_ROOT)/bsp/Kconfig" +source "$(SDK_ROOT)/lib/Kconfig" source "$(SDK_ROOT)/third-party/Kconfig" \ No newline at end of file diff --git a/LICENSE b/LICENSE index 261eeb9e9..29f81d812 100644 --- a/LICENSE +++ b/LICENSE @@ -1,201 +1,201 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. Definitions. - - "License" shall mean the terms and conditions for use, reproduction, - and distribution as defined by Sections 1 through 9 of this document. - - "Licensor" shall mean the copyright owner or entity authorized by - the copyright owner that is granting the License. - - "Legal Entity" shall mean the union of the acting entity and all - other entities that control, are controlled by, or are under common - control with that entity. For the purposes of this definition, - "control" means (i) the power, direct or indirect, to cause the - direction or management of such entity, whether by contract or - otherwise, or (ii) ownership of fifty percent (50%) or more of the - outstanding shares, or (iii) beneficial ownership of such entity. - - "You" (or "Your") shall mean an individual or Legal Entity - exercising permissions granted by this License. - - "Source" form shall mean the preferred form for making modifications, - including but not limited to software source code, documentation - source, and configuration files. - - "Object" form shall mean any form resulting from mechanical - transformation or translation of a Source form, including but - not limited to compiled object code, generated documentation, - and conversions to other media types. - - "Work" shall mean the work of authorship, whether in Source or - Object form, made available under the License, as indicated by a - copyright notice that is included in or attached to the work - (an example is provided in the Appendix below). - - "Derivative Works" shall mean any work, whether in Source or Object - form, that is based on (or derived from) the Work and for which the - editorial revisions, annotations, elaborations, or other modifications - represent, as a whole, an original work of authorship. For the purposes - of this License, Derivative Works shall not include works that remain - separable from, or merely link (or bind by name) to the interfaces of, - the Work and Derivative Works thereof. - - "Contribution" shall mean any work of authorship, including - the original version of the Work and any modifications or additions - to that Work or Derivative Works thereof, that is intentionally - submitted to Licensor for inclusion in the Work by the copyright owner - or by an individual or Legal Entity authorized to submit on behalf of - the copyright owner. For the purposes of this definition, "submitted" - means any form of electronic, verbal, or written communication sent - to the Licensor or its representatives, including but not limited to - communication on electronic mailing lists, source code control systems, - and issue tracking systems that are managed by, or on behalf of, the - Licensor for the purpose of discussing and improving the Work, but - excluding communication that is conspicuously marked or otherwise - designated in writing by the copyright owner as "Not a Contribution." - - "Contributor" shall mean Licensor and any individual or Legal Entity - on behalf of whom a Contribution has been received by Licensor and - subsequently incorporated within the Work. - - 2. Grant of Copyright License. Subject to the terms and conditions of - this License, each Contributor hereby grants to You a perpetual, - worldwide, non-exclusive, no-charge, royalty-free, irrevocable - copyright license to reproduce, prepare Derivative Works of, - publicly display, publicly perform, sublicense, and distribute the - Work and such Derivative Works in Source or Object form. - - 3. Grant of Patent License. Subject to the terms and conditions of - this License, each Contributor hereby grants to You a perpetual, - worldwide, non-exclusive, no-charge, royalty-free, irrevocable - (except as stated in this section) patent license to make, have made, - use, offer to sell, sell, import, and otherwise transfer the Work, - where such license applies only to those patent claims licensable - by such Contributor that are necessarily infringed by their - Contribution(s) alone or by combination of their Contribution(s) - with the Work to which such Contribution(s) was submitted. If You - institute patent litigation against any entity (including a - cross-claim or counterclaim in a lawsuit) alleging that the Work - or a Contribution incorporated within the Work constitutes direct - or contributory patent infringement, then any patent licenses - granted to You under this License for that Work shall terminate - as of the date such litigation is filed. - - 4. Redistribution. You may reproduce and distribute copies of the - Work or Derivative Works thereof in any medium, with or without - modifications, and in Source or Object form, provided that You - meet the following conditions: - - (a) You must give any other recipients of the Work or - Derivative Works a copy of this License; and - - (b) You must cause any modified files to carry prominent notices - stating that You changed the files; and - - (c) You must retain, in the Source form of any Derivative Works - that You distribute, all copyright, patent, trademark, and - attribution notices from the Source form of the Work, - excluding those notices that do not pertain to any part of - the Derivative Works; and - - (d) If the Work includes a "NOTICE" text file as part of its - distribution, then any Derivative Works that You distribute must - include a readable copy of the attribution notices contained - within such NOTICE file, excluding those notices that do not - pertain to any part of the Derivative Works, in at least one - of the following places: within a NOTICE text file distributed - as part of the Derivative Works; within the Source form or - documentation, if provided along with the Derivative Works; or, - within a display generated by the Derivative Works, if and - wherever such third-party notices normally appear. The contents - of the NOTICE file are for informational purposes only and - do not modify the License. You may add Your own attribution - notices within Derivative Works that You distribute, alongside - or as an addendum to the NOTICE text from the Work, provided - that such additional attribution notices cannot be construed - as modifying the License. - - You may add Your own copyright statement to Your modifications and - may provide additional or different license terms and conditions - for use, reproduction, or distribution of Your modifications, or - for any such Derivative Works as a whole, provided Your use, - reproduction, and distribution of the Work otherwise complies with - the conditions stated in this License. - - 5. Submission of Contributions. Unless You explicitly state otherwise, - any Contribution intentionally submitted for inclusion in the Work - by You to the Licensor shall be under the terms and conditions of - this License, without any additional terms or conditions. - Notwithstanding the above, nothing herein shall supersede or modify - the terms of any separate license agreement you may have executed - with Licensor regarding such Contributions. - - 6. Trademarks. This License does not grant permission to use the trade - names, trademarks, service marks, or product names of the Licensor, - except as required for reasonable and customary use in describing the - origin of the Work and reproducing the content of the NOTICE file. - - 7. Disclaimer of Warranty. Unless required by applicable law or - agreed to in writing, Licensor provides the Work (and each - Contributor provides its Contributions) on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or - implied, including, without limitation, any warranties or conditions - of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A - PARTICULAR PURPOSE. You are solely responsible for determining the - appropriateness of using or redistributing the Work and assume any - risks associated with Your exercise of permissions under this License. - - 8. Limitation of Liability. In no event and under no legal theory, - whether in tort (including negligence), contract, or otherwise, - unless required by applicable law (such as deliberate and grossly - negligent acts) or agreed to in writing, shall any Contributor be - liable to You for damages, including any direct, indirect, special, - incidental, or consequential damages of any character arising as a - result of this License or out of the use or inability to use the - Work (including but not limited to damages for loss of goodwill, - work stoppage, computer failure or malfunction, or any and all - other commercial damages or losses), even if such Contributor - has been advised of the possibility of such damages. - - 9. Accepting Warranty or Additional Liability. While redistributing - the Work or Derivative Works thereof, You may choose to offer, - and charge a fee for, acceptance of support, warranty, indemnity, - or other liability obligations and/or rights consistent with this - License. However, in accepting such obligations, You may act only - on Your own behalf and on Your sole responsibility, not on behalf - of any other Contributor, and only if You agree to indemnify, - defend, and hold each Contributor harmless for any liability - incurred by, or claims asserted against, such Contributor by reason - of your accepting any such warranty or additional liability. - - END OF TERMS AND CONDITIONS - - APPENDIX: How to apply the Apache License to your work. - - To apply the Apache License to your work, attach the following - boilerplate notice, with the fields enclosed by brackets "[]" - replaced with your own identifying information. (Don't include - the brackets!) The text should be enclosed in the appropriate - comment syntax for the file format. We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright [yyyy] [name of copyright owner] - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/baremetal/example/aarch32_cache_mmu_wr/README.md b/baremetal/example/aarch32_cache_mmu_wr/README.md index 688a60641..6e9eea8a1 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/README.md +++ b/baremetal/example/aarch32_cache_mmu_wr/README.md @@ -1,52 +1,52 @@ - - -# host侧设置 -- 重启host侧tftp服务器 -``` -sudo service tftpd-hpa restart -``` - -# 开发板侧设置 - -## 使用go命令跳转 -- 关闭D-cache和I-cache -``` -icache off -dcache off -``` - -- 下载新版本到FT2000-4 -``` -setenv ipaddr 192.168.4.20 -setenv serverip 192.168.4.50 -setenv gatewayip 192.168.4.1 -tftpboot 80100000 ft2004_baremetal.bin -bootvx32 -go 0x80100000 -``` - -``` -tftpboot 80100000 ft2004_test_irq.bin -``` - -## 使用bootvx32命令跳转 -- 下载新版本到FT2000-4 -``` -setenv ipaddr 192.168.4.20 -setenv serverip 192.168.4.50 -setenv gatewayip 192.168.4.1 -tftpboot 80100000 ft2004_baremetal.bin -bootvx32 + + +# host侧设置 +- 重启host侧tftp服务器 +``` +sudo service tftpd-hpa restart +``` + +# 开发板侧设置 + +## 使用go命令跳转 +- 关闭D-cache和I-cache +``` +icache off +dcache off +``` + +- 下载新版本到FT2000-4 +``` +setenv ipaddr 192.168.4.20 +setenv serverip 192.168.4.50 +setenv gatewayip 192.168.4.1 +tftpboot 80100000 ft2004_baremetal.bin +bootvx32 +go 0x80100000 +``` + +``` +tftpboot 80100000 ft2004_test_irq.bin +``` + +## 使用bootvx32命令跳转 +- 下载新版本到FT2000-4 +``` +setenv ipaddr 192.168.4.20 +setenv serverip 192.168.4.50 +setenv gatewayip 192.168.4.1 +tftpboot 80100000 ft2004_baremetal.bin +bootvx32 ``` \ No newline at end of file diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig index 5b6895371..12e197df3 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig @@ -1,99 +1,99 @@ - -# -# Project Configuration -# - -# -# Baremetal Configuration -# -CONFIG_TARGET_NAME="cache_test" -# end of Baremetal Configuration -# end of Project Configuration - -# -# Target Setting -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Target Setting - -# -# Building Option -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of Building Option - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -CONFIG_USE_SPI=y - -# -# SPI Configuration -# -CONFIG_SPI_POLLING_MODE=y -# CONFIG_SPI_IRQ_MODE is not set -# end of SPI Configuration - -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -# CONFIG_USE_USART is not set -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration + +# +# Project Configuration +# + +# +# Baremetal Configuration +# +CONFIG_TARGET_NAME="cache_test" +# end of Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +CONFIG_USE_SPI=y + +# +# SPI Configuration +# +CONFIG_SPI_POLLING_MODE=y +# CONFIG_SPI_IRQ_MODE is not set +# end of SPI Configuration + +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +# CONFIG_USE_USART is not set +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h index cc1a9119f..12d13e5e5 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.h @@ -1,15 +1,15 @@ -#define CONFIG_TARGET_NAME "cache_test" -#define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_F2000_4 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1` -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_SPI 1 -#define CONFIG_SPI_POLLING_MODE 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_CACHE 1 -#define CONFIG_USE_L3CACHE 1 -#define CONFIG_USE_MMU 1 -#define CONFIG_USE_NOSTD_LIBC 1 +#define CONFIG_TARGET_NAME "cache_test" +#define CONFIG_TARGET_ARMV8_AARCH32 1 +#define CONFIG_TARGET_F2000_4 1 +#define CONFIG_ENVI_UBUNTU_20_04 1 +#define CONFIG_COMPILER_NO_STD_STARUP 1 +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1` +#define CONFIG_LOG_ERROR 1 +#define CONFIG_USE_SPI 1 +#define CONFIG_SPI_POLLING_MODE 1 +#define CONFIG_USE_GIC 1 +#define CONFIG_EBABLE_GICV3 1 +#define CONFIG_USE_CACHE 1 +#define CONFIG_USE_L3CACHE 1 +#define CONFIG_USE_MMU 1 +#define CONFIG_USE_NOSTD_LIBC 1 diff --git a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old index 76a59fea1..53455413d 100644 --- a/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old +++ b/baremetal/example/aarch32_cache_mmu_wr/sdkconfig.old @@ -1,99 +1,99 @@ - -# -# Project Configuration -# - -# -# Baremetal Configuration -# -CONFIG_TARGET_NAME="cache_test" -# end of Baremetal Configuration -# end of Project Configuration - -# -# Target Setting -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Target Setting - -# -# Building Option -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of Building Option - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -CONFIG_USE_SPI=y - -# -# SPI Configuration -# -CONFIG_SPI_POLLING_MODE=y -# CONFIG_SPI_IRQ_MODE is not set -# end of SPI Configuration - -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -# CONFIG_USE_USART is not set -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -# CONFIG_USE_NOSTD_LIBC is not set -CONFIG_USE_LIBC=y -# end of Library Configuration + +# +# Project Configuration +# + +# +# Baremetal Configuration +# +CONFIG_TARGET_NAME="cache_test" +# end of Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +CONFIG_USE_SPI=y + +# +# SPI Configuration +# +CONFIG_SPI_POLLING_MODE=y +# CONFIG_SPI_IRQ_MODE is not set +# end of SPI Configuration + +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +# CONFIG_USE_USART is not set +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration diff --git a/baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o b/baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o index bd5a22d15..81a4ad13d 100644 --- a/baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o +++ b/baremetal/example/aarch32_hello_world/ft2004_baremetal.map_o @@ -1,2174 +1,2174 @@ -Archive member included to satisfy reference by file (symbol) - -/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (atexit) -/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) - ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o (__errno) 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-/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) (_fclose_r) -/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) (fiprintf) -/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) (_fputwc_r) -/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fstatr.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) (_fstat_r) -/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) - 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-/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (_ctype_) -/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) (raise) -/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) (_kill_r) -/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_dmul) -/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_uidiv) -/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) (__aeabi_idiv) -/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0) -/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_dsub) -/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_ddiv) -/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) - /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__aeabi_dcmpeq) -/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) - 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./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o - -Memory Configuration - -Name Origin Length Attributes -ROM 0x0000000080100000 0x0000000000100000 xr -RAM 0x0000000081000000 0x0000000002000000 xrw -*default* 0x0000000000000000 0xffffffffffffffff - -Linker script and memory map - -LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o -LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o -LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o -LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o -LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o -LOAD ./build/./main.o -LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libm.a -START GROUP -LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a -LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a -END GROUP -LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o -LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o - 0x0000000000000400 HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400 - -.text 0x0000000080100000 0xee0d - 0x0000000080100000 _text_start = . - *(.Startup_Aarch32) - .Startup_Aarch32 - 0x0000000080100000 0x360 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o - 0x0000000080100000 Startup_Aarch32 - 0x0000000080100118 RST_Handler - *(.vector_table) - *fill* 0x0000000080100360 0x4a0 - .vector_table 0x0000000080100800 0xcc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o - 0x0000000080100800 system_vectors - 0x0000000080100820 Abort_Exception - 0x0000000080100830 IRQ_Handler - 0x000000008010087c FIQ_Handler - 0x0000000080100884 UDF_Handler - 0x000000008010088c SWI_Handler - 0x0000000080100894 PRF_Handler - 0x00000000801008c0 DAT_Handler - *(.text*) - .text 0x00000000801008cc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o - .text 0x00000000801008cc 0xa8 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o - .text 0x0000000080100974 0xdc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o - 0x0000000080100974 _stack_init - 0x00000000801009e8 _mainCRTStartup - 0x00000000801009e8 _start - .text 0x0000000080100a50 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o - .text 0x0000000080100a50 0x8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o - 0x0000000080100a50 c_startup - .text 0x0000000080100a58 0x178 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o - 0x0000000080100a58 cpu_get_smp_id - 0x0000000080100a60 cpu_mmu_disable - 0x0000000080100a78 cpu_mmu_enable - 0x0000000080100a8c cpu_tlb_set - 0x0000000080100aa4 cpu_dcache_clean_flush - 0x0000000080100b38 cpu_icache_flush - 0x0000000080100b4c cpu_vector_set_base - 0x0000000080100b64 cpu_dcache_disable - 0x0000000080100b80 cpu_icache_disable - 0x0000000080100b90 cpu_icache_enable - 0x0000000080100ba0 cpu_dcache_enable - 0x0000000080100bb0 cp15_get_cpu_id - 0x0000000080100bc0 cp15_set_vector_base - .text 0x0000000080100bd0 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o - 0x0000000080100bd0 DisableInterrupt - 0x0000000080100bdc EnableInterrupt - .text 0x0000000080100be4 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o - *fill* 0x0000000080100be4 0xc - .text 0x0000000080100bf0 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o - 0x0000000080100bf0 FSmc_Call - .text 0x0000000080100c10 0x330 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o - 0x0000000080100c10 FtDumpHexByte - 0x0000000080100d9c FtDumpHexWord - .text 0x0000000080100f40 0x254 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o - 0x0000000080100f40 ShowExceptionRegisters - 0x0000000080101050 PrfTrap - 0x0000000080101080 SystemIrqHandler - 0x00000000801010f0 IrqHandleException - 0x000000008010117c fiq_handle - .text 0x0000000080101194 0x41c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o - 0x0000000080101194 PlatformGetIrqStartNum - 0x00000000801011b0 PlatformGetGicDistBase - 0x00000000801011cc InterruptInit - 0x000000008010122c InterruptMask - 0x0000000080101254 InterruptUmask - 0x000000008010127c InterruptGetIrq - 0x0000000080101298 InterruptAck - 0x00000000801012c0 InterruptSetTargetCpus - 0x00000000801012f0 InterruptGetTargetCpus - 0x000000008010131c InterruptSetTrigerMode - 0x000000008010134c InterruptGetTrigerMode - 0x0000000080101378 InterruptSetPending - 0x00000000801013a0 InterruptGetPending - 0x00000000801013cc InterruptClearPending - 0x00000000801013f4 InterruptSetPriority - 0x0000000080101424 InterruptGetPriority - 0x0000000080101450 InterruptSetPriorityMask - 0x0000000080101478 InterruptGetPriorityMask - 0x0000000080101494 InterruptSetPriorGroupBits - 0x00000000801014e8 InterruptGetPriorGroupBits - 0x000000008010151c InterruptInstall - .text 0x00000000801015b0 0x98 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o - 0x00000000801015b0 FtAssert - 0x0000000080101618 FtAssertSetCb - .text 0x0000000080101648 0x378 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o - 0x0000000080101648 GenericTimerStart - 0x00000000801016a8 GenericTimerStop - 0x0000000080101708 GenericTimerInterruptEnable - 0x0000000080101768 GenericTimerInterruptDisable - 0x00000000801017e8 GenericTimerFrequecy - 0x0000000080101834 GenericTimerRead - 0x00000000801018b4 GenericTimerCompare - 0x00000000801018e8 Aarch32Delay - 0x0000000080101954 Aarch32Udelay - .text 0x00000000801019c0 0x16c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o - 0x00000000801019c0 PsciCpuOn - 0x0000000080101ab0 PsciCpuReset - .text 0x0000000080101b2c 0x5ec ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o - 0x0000000080101b2c Dump2ndPageTable - 0x0000000080101cdc DumpPageTable - 0x0000000080101f24 SetMMUTable - 0x0000000080101fe0 SetDomainReg - 0x0000000080102014 InitMMUTable - 0x0000000080102084 InitMMU - 0x00000000801020c4 InitCache - .text 0x0000000080102118 0x374 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o - 0x0000000080102118 AsmFlushL3Dcache - 0x0000000080102134 AsmInvaliDateL3dcache - 0x00000000801021bc IcacheInvalidate - 0x0000000080102268 DcacheInvalidate - 0x0000000080102314 DcacheClean - 0x00000000801023c0 IcacheOps - 0x00000000801023fc DcacheOps - 0x0000000080102454 GetCpuIcacheStatus - 0x0000000080102470 GetCpuDcacheStatus - .text 0x000000008010248c 0x8c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o - 0x000000008010248c fsleep_seconds - .text 0x0000000080102518 0x19c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o - 0x0000000080102518 FiqDebug - 0x0000000080102530 UdfDebug - 0x0000000080102548 SwiDebug - 0x0000000080102560 PrfDebug - 0x0000000080102578 DatDebug - 0x0000000080102590 TraceDebug - 0x00000000801025ac TraceDebug1 - 0x00000000801025c8 TraceDebug2 - 0x00000000801025e4 TraceSctrl - 0x000000008010261c TraceTLB - 0x0000000080102654 TraceR0 - 0x0000000080102680 TraceR0R1 - .text 0x00000000801026b4 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o - .text 0x00000000801026b4 0x1e4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o - 0x00000000801026b4 GetCpuId - 0x0000000080102748 GetCpuCluster - 0x00000000801027ac SpinLockInit - 0x00000000801027d4 SpinLock - 0x0000000080102854 SpinUnlock - .text 0x0000000080102898 0xf8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o - 0x00000000801028f8 OutByte - 0x000000008010294c GetByte - .text 0x0000000080102990 0x28d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o - 0x0000000080102990 ArmGicCpuMaskToAffval - 0x00000000801029bc GetMainCpuAffval - 0x00000000801029e0 ArmGicGetActiveIrq - 0x0000000080102a70 ArmGicAck - 0x0000000080102b20 ArmGicMask - 0x0000000080102cbc ArmGicUmask - 0x0000000080102e58 ArmGicGetPendingIrq - 0x0000000080102fe8 ArmGicSetPendingIrq - 0x0000000080103128 ArmGicClearPendingIrq - 0x0000000080103290 ArmGicSetConfiguration - 0x0000000080103404 ArmGicGetConfiguration - 0x0000000080103514 ArmGicClearActive - 0x0000000080103620 ArmGicSetCpu - 0x000000008010378c ArmGicGetTargetCpu - 0x000000008010389c ArmGicSetPriority - 0x0000000080103b28 ArmGicGetPriority - 0x0000000080103ce8 ArmGicSetSystemRegisterEnableMask - 0x0000000080103d60 ArmGicGetSystemRegisterEnableMask - 0x0000000080103dd0 ArmGicSetInterfacePriorMask - 0x0000000080103e44 ArmGicGetInterfacePriorMask - 0x0000000080103eb4 ArmGicSetBinaryPoint - 0x0000000080103eec ArmGicGetBinaryPoint - 0x0000000080103f18 ArmGicGetIrqStatus - 0x0000000080104080 ArmGicSendAffinitySgi - 0x00000000801042a8 ArmGicGetHighPendingIrq - 0x0000000080104318 ArmGicGetInterfaceId - 0x00000000801043a0 ArmGicSetGroup - 0x0000000080104558 ArmGicGetGroup - 0x00000000801047a8 ArmGicDistInit - 0x0000000080104b20 ArmGicRedistAddressSet - 0x0000000080104c04 ArmGicCpuInterfaceAddressSet - 0x0000000080104cec ArmGicRedistInit - 0x0000000080104ed4 ArmGicCpuInit - 0x0000000080104fa0 ArmGicDumpType - 0x0000000080105074 ArmGicDump - 0x000000008010523c gic_dump - .text 0x0000000080105260 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o - .text 0x0000000080105260 0x164 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o - 0x00000000801052c0 Pl011SendByte - 0x0000000080105318 Pl011RecvByte - 0x000000008010536c Pl011GetChar - .text 0x00000000801053c4 0x88 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o - 0x00000000801053c4 Pl011LookupConfig - .text 0x000000008010544c 0xcbc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o - 0x00000000801054ac Pl011CfgInitialize - 0x000000008010568c Pl011Send - 0x000000008010581c Pl011PutChar - 0x0000000080105958 Pl011SendBuffer - 0x0000000080105a58 Pl011Receive - 0x0000000080105be4 Pl011ReceiveBuffer - 0x0000000080105d2c Pl011BlockSend - 0x0000000080105e68 Pl011BlockReceive - 0x0000000080105f30 Pl011SetBaudRate - 0x0000000080106088 Pl011IrqClearReciveTimeOut - 0x00000000801060c8 Pl011IrqEnableReciveTimeOut - .text 0x0000000080106108 0x4d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o - 0x0000000080106168 Pl011SetOptions - 0x0000000080106334 Pl011SetSpecificOptions - 0x0000000080106484 Pl011ClearSpecificOptions - .text 0x00000000801065d8 0x620 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o - 0x0000000080106638 Pl011GetInterruptMask - 0x00000000801066b4 Pl011SetInterruptMask - 0x0000000080106740 Pl011SetHandler - 0x0000000080106850 Pl011InterruptHandler - .text 0x0000000080106bf8 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o - .text 0x0000000080106bf8 0x2d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o - 0x0000000080106bf8 initialise_monitor_handles - 0x0000000080106c48 _read - 0x0000000080106cb8 _write - 0x0000000080106d48 _lseek - 0x0000000080106d80 _close - 0x0000000080106da4 _fstat - 0x0000000080106dd8 _isatty - 0x0000000080106e08 _sbrk - 0x0000000080106e5c _exit - 0x0000000080106e78 _getpid - 0x0000000080106e94 _kill - .text 0x0000000080106ec8 0x40 ./build/./main.o - 0x0000000080106ec8 main - 0x0000000080106ef0 test_pos - .text 0x0000000080106f08 0xc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) - 0x0000000080106f08 atexit - .text 0x0000000080106f14 0xc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) - 0x0000000080106f14 __errno - .text 0x0000000080106f20 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) - 0x0000000080106f20 exit - .text 0x0000000080106f40 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) - 0x0000000080106f40 __libc_fini_array - .text 0x0000000080106f70 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) - .text 0x0000000080106f70 0x50 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) - 0x0000000080106f70 __libc_init_array - .text 0x0000000080106fc0 0xa0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) - 0x0000000080106fc0 memset - .text 0x0000000080107060 0x4c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) - 0x0000000080107060 _printf_r - 0x0000000080107080 printf - .text 0x00000000801070ac 0x154 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) - 0x00000000801070ac setvbuf - .text 0x0000000080107200 0x160c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) - 0x0000000080107200 _vfprintf_r - 0x0000000080108788 vfprintf - .text 0x000000008010880c 0xc8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) - 0x000000008010880c __swsetup_r - .text 0x00000000801088d4 0x6c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) - 0x00000000801088d4 __register_exitproc - .text 0x0000000080108940 0x9c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) - 0x0000000080108940 __call_exitprocs - .text.startup 0x00000000801089dc 0x18 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) - *fill* 0x00000000801089f4 0x4 - .text 0x00000000801089f8 0x10c0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) - 0x0000000080108b38 _dtoa_r - .text 0x0000000080109ab8 0x1b0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) - 0x0000000080109ab8 __sflush_r - 0x0000000080109c0c _fflush_r - 0x0000000080109c40 fflush - .text 0x0000000080109c68 0x210 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) - 0x0000000080109c6c _cleanup_r - 0x0000000080109d60 __sfmoreglue - 0x0000000080109d90 __sfp - 0x0000000080109e18 _cleanup - 0x0000000080109e30 __sinit - 0x0000000080109e38 __sfp_lock_acquire - 0x0000000080109e3c __sfp_lock_release - 0x0000000080109e40 __sinit_lock_acquire - 0x0000000080109e44 __sinit_lock_release - 0x0000000080109e48 __fp_lock_all - 0x0000000080109e60 __fp_unlock_all - .text 0x0000000080109e78 0x2a8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) - 0x0000000080109e78 _malloc_trim_r - 0x0000000080109f24 _free_r - .text 0x000000008010a120 0x98 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) - 0x000000008010a120 _fwalk - 0x000000008010a168 _fwalk_reent - .text 0x000000008010a1b8 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) - 0x000000008010a1b8 __localeconv_l - 0x000000008010a1bc _localeconv_r - 0x000000008010a1c4 localeconv - .text 0x000000008010a1cc 0xf8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) - 0x000000008010a1cc __swhatbuf_r - 0x000000008010a228 __smakebuf_r - .text 0x000000008010a2c4 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) - 0x000000008010a2c4 malloc - 0x000000008010a2d4 free - .text 0x000000008010a2e4 0x588 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) - 0x000000008010a2e4 _malloc_r - .text 0x000000008010a86c 0x8c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) - 0x000000008010a86c memchr - .text 0x000000008010a8f8 0xec /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) - 0x000000008010a8f8 memcpy - .text 0x000000008010a9e4 0x8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) - 0x000000008010a9e4 __malloc_lock - 0x000000008010a9e8 __malloc_unlock - .text 0x000000008010a9ec 0x9e0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) - 0x000000008010a9ec _Balloc - 0x000000008010aa38 _Bfree - 0x000000008010aa4c __multadd - 0x000000008010aafc __s2b - 0x000000008010abb4 __hi0bits - 0x000000008010abf4 __lo0bits - 0x000000008010ac50 __i2b - 0x000000008010ac80 __multiply - 0x000000008010ade0 __pow5mult - 0x000000008010ae7c __lshift - 0x000000008010af54 __mcmp - 0x000000008010af90 __mdiff - 0x000000008010b0d0 __ulp - 0x000000008010b110 __b2d - 0x000000008010b1d4 __d2b - 0x000000008010b29c __ratio - 0x000000008010b2f4 _mprec_log10 - 0x000000008010b32c __copybits - 0x000000008010b374 __any_on - .text 0x000000008010b3cc 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) - 0x000000008010b3cc _sbrk_r - .text 0x000000008010b3f4 0x90 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) - 0x000000008010b3f4 __sread - 0x000000008010b418 __seofread - 0x000000008010b41c __swrite - 0x000000008010b45c __sseek - 0x000000008010b47c __sclose - .text 0x000000008010b484 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) - 0x000000008010b484 strlen - .text 0x000000008010b4e0 0xd68 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfiprintf.o) - 0x000000008010b554 __sprint_r - 0x000000008010b564 _vfiprintf_r - 0x000000008010c1c4 vfiprintf - .text 0x000000008010c248 0x2c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-writer.o) - 0x000000008010c248 _write_r - .text 0x000000008010c274 0x50 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) - 0x000000008010c274 __assert_func - 0x000000008010c2b8 __assert - .text 0x000000008010c2c4 0x64 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) - 0x000000008010c2c4 _calloc_r - .text 0x000000008010c328 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) - 0x000000008010c328 _close_r - .text 0x000000008010c350 0x98 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) - 0x000000008010c350 _fclose_r - 0x000000008010c3d8 fclose - .text 0x000000008010c3e8 0x4c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) - 0x000000008010c3e8 _fiprintf_r - 0x000000008010c408 fiprintf - .text 0x000000008010c434 0x11c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) - 0x000000008010c434 __fputwc - 0x000000008010c4e8 _fputwc_r - 0x000000008010c50c fputwc - .text 0x000000008010c550 0x2c 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/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) - .debug_loc 0x000000000000ffd8 0x152 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) - .debug_loc 0x000000000001012a 0x1d7 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) - .debug_loc 0x0000000000010301 0x281 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) - .debug_loc 0x0000000000010582 0x118 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) - .debug_loc 0x000000000001069a 0x47b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) - .debug_loc 0x0000000000010b15 0xc0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) - .debug_loc 0x0000000000010bd5 0x20d /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) +Archive member included to satisfy reference by file (symbol) + +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (atexit) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o (__errno) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (exit) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o (__libc_fini_array) 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(setvbuf) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) (_vfprintf_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__swsetup_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) (__register_exitproc) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) (__call_exitprocs) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (_dtoa_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) (_fflush_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) (__sinit) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) (_free_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) (_fwalk) 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/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (memchr) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (memcpy) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) (__malloc_lock) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (_Balloc) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) (_sbrk_r) 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/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__assert_func) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-callocr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) (_calloc_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-closer.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) (_close_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fclose.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) (_fclose_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fiprintf.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) (fiprintf) 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/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) (__locale_mb_cur_max) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) (_lseek_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (__ascii_mbtowc) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) (memmove) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) (_read_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) (_realloc_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) (errno) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strcmp.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (strcmp) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) (__swbuf_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fputwc.o) (_wcrtomb_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (__ascii_wctomb) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-assert.o) (abort) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-ctype_.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) (_ctype_) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-abort.o) (raise) +/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) (_kill_r) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldf3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_dmul) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_uidiv) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) (__aeabi_idiv) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_dsub) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_ddiv) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__aeabi_dcmpeq) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__aeabi_dcmpun) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) (__aeabi_d2iz) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) (__aeabi_uldivmod) +/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4) + +Allocating common symbols +Common symbol size file + +errno 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) +isr_table 0x500 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o +ft_assert_status 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + +Memory Configuration + +Name Origin Length Attributes +ROM 0x0000000080100000 0x0000000000100000 xr +RAM 0x0000000081000000 0x0000000002000000 xrw +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o +LOAD ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o +LOAD ./build/./main.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libm.a +START GROUP +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a +END GROUP +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o +LOAD /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + 0x0000000000000400 HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400 + +.text 0x0000000080100000 0xee0d + 0x0000000080100000 _text_start = . + *(.Startup_Aarch32) + .Startup_Aarch32 + 0x0000000080100000 0x360 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + 0x0000000080100000 Startup_Aarch32 + 0x0000000080100118 RST_Handler + *(.vector_table) + *fill* 0x0000000080100360 0x4a0 + .vector_table 0x0000000080100800 0xcc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + 0x0000000080100800 system_vectors + 0x0000000080100820 Abort_Exception + 0x0000000080100830 IRQ_Handler + 0x000000008010087c FIQ_Handler + 0x0000000080100884 UDF_Handler + 0x000000008010088c SWI_Handler + 0x0000000080100894 PRF_Handler + 0x00000000801008c0 DAT_Handler + *(.text*) + .text 0x00000000801008cc 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crti.o + .text 0x00000000801008cc 0xa8 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtbegin.o + .text 0x0000000080100974 0xdc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/crt0.o + 0x0000000080100974 _stack_init + 0x00000000801009e8 _mainCRTStartup + 0x00000000801009e8 _start + .text 0x0000000080100a50 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/start.o + .text 0x0000000080100a50 0x8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/crt0.o + 0x0000000080100a50 c_startup + .text 0x0000000080100a58 0x178 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/cp15.o + 0x0000000080100a58 cpu_get_smp_id + 0x0000000080100a60 cpu_mmu_disable + 0x0000000080100a78 cpu_mmu_enable + 0x0000000080100a8c cpu_tlb_set + 0x0000000080100aa4 cpu_dcache_clean_flush + 0x0000000080100b38 cpu_icache_flush + 0x0000000080100b4c cpu_vector_set_base + 0x0000000080100b64 cpu_dcache_disable + 0x0000000080100b80 cpu_icache_disable + 0x0000000080100b90 cpu_icache_enable + 0x0000000080100ba0 cpu_dcache_enable + 0x0000000080100bb0 cp15_get_cpu_id + 0x0000000080100bc0 cp15_set_vector_base + .text 0x0000000080100bd0 0x14 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/context.o + 0x0000000080100bd0 DisableInterrupt + 0x0000000080100bdc EnableInterrupt + .text 0x0000000080100be4 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + *fill* 0x0000000080100be4 0xc + .text 0x0000000080100bf0 0x20 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + 0x0000000080100bf0 FSmc_Call + .text 0x0000000080100c10 0x330 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + 0x0000000080100c10 FtDumpHexByte + 0x0000000080100d9c FtDumpHexWord + .text 0x0000000080100f40 0x254 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + 0x0000000080100f40 ShowExceptionRegisters + 0x0000000080101050 PrfTrap + 0x0000000080101080 SystemIrqHandler + 0x00000000801010f0 IrqHandleException + 0x000000008010117c fiq_handle + .text 0x0000000080101194 0x41c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + 0x0000000080101194 PlatformGetIrqStartNum + 0x00000000801011b0 PlatformGetGicDistBase + 0x00000000801011cc InterruptInit + 0x000000008010122c InterruptMask + 0x0000000080101254 InterruptUmask + 0x000000008010127c InterruptGetIrq + 0x0000000080101298 InterruptAck + 0x00000000801012c0 InterruptSetTargetCpus + 0x00000000801012f0 InterruptGetTargetCpus + 0x000000008010131c InterruptSetTrigerMode + 0x000000008010134c InterruptGetTrigerMode + 0x0000000080101378 InterruptSetPending + 0x00000000801013a0 InterruptGetPending + 0x00000000801013cc InterruptClearPending + 0x00000000801013f4 InterruptSetPriority + 0x0000000080101424 InterruptGetPriority + 0x0000000080101450 InterruptSetPriorityMask + 0x0000000080101478 InterruptGetPriorityMask + 0x0000000080101494 InterruptSetPriorGroupBits + 0x00000000801014e8 InterruptGetPriorGroupBits + 0x000000008010151c InterruptInstall + .text 0x00000000801015b0 0x98 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + 0x00000000801015b0 FtAssert + 0x0000000080101618 FtAssertSetCb + .text 0x0000000080101648 0x378 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + 0x0000000080101648 GenericTimerStart + 0x00000000801016a8 GenericTimerStop + 0x0000000080101708 GenericTimerInterruptEnable + 0x0000000080101768 GenericTimerInterruptDisable + 0x00000000801017e8 GenericTimerFrequecy + 0x0000000080101834 GenericTimerRead + 0x00000000801018b4 GenericTimerCompare + 0x00000000801018e8 Aarch32Delay + 0x0000000080101954 Aarch32Udelay + .text 0x00000000801019c0 0x16c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + 0x00000000801019c0 PsciCpuOn + 0x0000000080101ab0 PsciCpuReset + .text 0x0000000080101b2c 0x5ec ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + 0x0000000080101b2c Dump2ndPageTable + 0x0000000080101cdc DumpPageTable + 0x0000000080101f24 SetMMUTable + 0x0000000080101fe0 SetDomainReg + 0x0000000080102014 InitMMUTable + 0x0000000080102084 InitMMU + 0x00000000801020c4 InitCache + .text 0x0000000080102118 0x374 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + 0x0000000080102118 AsmFlushL3Dcache + 0x0000000080102134 AsmInvaliDateL3dcache + 0x00000000801021bc IcacheInvalidate + 0x0000000080102268 DcacheInvalidate + 0x0000000080102314 DcacheClean + 0x00000000801023c0 IcacheOps + 0x00000000801023fc DcacheOps + 0x0000000080102454 GetCpuIcacheStatus + 0x0000000080102470 GetCpuDcacheStatus + .text 0x000000008010248c 0x8c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + 0x000000008010248c fsleep_seconds + .text 0x0000000080102518 0x19c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + 0x0000000080102518 FiqDebug + 0x0000000080102530 UdfDebug + 0x0000000080102548 SwiDebug + 0x0000000080102560 PrfDebug + 0x0000000080102578 DatDebug + 0x0000000080102590 TraceDebug + 0x00000000801025ac TraceDebug1 + 0x00000000801025c8 TraceDebug2 + 0x00000000801025e4 TraceSctrl + 0x000000008010261c TraceTLB + 0x0000000080102654 TraceR0 + 0x0000000080102680 TraceR0R1 + .text 0x00000000801026b4 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .text 0x00000000801026b4 0x1e4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + 0x00000000801026b4 GetCpuId + 0x0000000080102748 GetCpuCluster + 0x00000000801027ac SpinLockInit + 0x00000000801027d4 SpinLock + 0x0000000080102854 SpinUnlock + .text 0x0000000080102898 0xf8 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + 0x00000000801028f8 OutByte + 0x000000008010294c GetByte + .text 0x0000000080102990 0x28d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + 0x0000000080102990 ArmGicCpuMaskToAffval + 0x00000000801029bc GetMainCpuAffval + 0x00000000801029e0 ArmGicGetActiveIrq + 0x0000000080102a70 ArmGicAck + 0x0000000080102b20 ArmGicMask + 0x0000000080102cbc ArmGicUmask + 0x0000000080102e58 ArmGicGetPendingIrq + 0x0000000080102fe8 ArmGicSetPendingIrq + 0x0000000080103128 ArmGicClearPendingIrq + 0x0000000080103290 ArmGicSetConfiguration + 0x0000000080103404 ArmGicGetConfiguration + 0x0000000080103514 ArmGicClearActive + 0x0000000080103620 ArmGicSetCpu + 0x000000008010378c ArmGicGetTargetCpu + 0x000000008010389c ArmGicSetPriority + 0x0000000080103b28 ArmGicGetPriority + 0x0000000080103ce8 ArmGicSetSystemRegisterEnableMask + 0x0000000080103d60 ArmGicGetSystemRegisterEnableMask + 0x0000000080103dd0 ArmGicSetInterfacePriorMask + 0x0000000080103e44 ArmGicGetInterfacePriorMask + 0x0000000080103eb4 ArmGicSetBinaryPoint + 0x0000000080103eec ArmGicGetBinaryPoint + 0x0000000080103f18 ArmGicGetIrqStatus + 0x0000000080104080 ArmGicSendAffinitySgi + 0x00000000801042a8 ArmGicGetHighPendingIrq + 0x0000000080104318 ArmGicGetInterfaceId + 0x00000000801043a0 ArmGicSetGroup + 0x0000000080104558 ArmGicGetGroup + 0x00000000801047a8 ArmGicDistInit + 0x0000000080104b20 ArmGicRedistAddressSet + 0x0000000080104c04 ArmGicCpuInterfaceAddressSet + 0x0000000080104cec ArmGicRedistInit + 0x0000000080104ed4 ArmGicCpuInit + 0x0000000080104fa0 ArmGicDumpType + 0x0000000080105074 ArmGicDump + 0x000000008010523c gic_dump + .text 0x0000000080105260 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .text 0x0000000080105260 0x164 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + 0x00000000801052c0 Pl011SendByte + 0x0000000080105318 Pl011RecvByte + 0x000000008010536c Pl011GetChar + .text 0x00000000801053c4 0x88 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + 0x00000000801053c4 Pl011LookupConfig + .text 0x000000008010544c 0xcbc ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + 0x00000000801054ac Pl011CfgInitialize + 0x000000008010568c Pl011Send + 0x000000008010581c Pl011PutChar + 0x0000000080105958 Pl011SendBuffer + 0x0000000080105a58 Pl011Receive + 0x0000000080105be4 Pl011ReceiveBuffer + 0x0000000080105d2c Pl011BlockSend + 0x0000000080105e68 Pl011BlockReceive + 0x0000000080105f30 Pl011SetBaudRate + 0x0000000080106088 Pl011IrqClearReciveTimeOut + 0x00000000801060c8 Pl011IrqEnableReciveTimeOut + .text 0x0000000080106108 0x4d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + 0x0000000080106168 Pl011SetOptions + 0x0000000080106334 Pl011SetSpecificOptions + 0x0000000080106484 Pl011ClearSpecificOptions + .text 0x00000000801065d8 0x620 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + 0x0000000080106638 Pl011GetInterruptMask + 0x00000000801066b4 Pl011SetInterruptMask + 0x0000000080106740 Pl011SetHandler + 0x0000000080106850 Pl011InterruptHandler + .text 0x0000000080106bf8 0x0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .text 0x0000000080106bf8 0x2d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + 0x0000000080106bf8 initialise_monitor_handles + 0x0000000080106c48 _read + 0x0000000080106cb8 _write + 0x0000000080106d48 _lseek + 0x0000000080106d80 _close + 0x0000000080106da4 _fstat + 0x0000000080106dd8 _isatty + 0x0000000080106e08 _sbrk + 0x0000000080106e5c _exit + 0x0000000080106e78 _getpid + 0x0000000080106e94 _kill + .text 0x0000000080106ec8 0x40 ./build/./main.o + 0x0000000080106ec8 main + 0x0000000080106ef0 test_pos + .text 0x0000000080106f08 0xc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + 0x0000000080106f08 atexit + .text 0x0000000080106f14 0xc /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-errno.o) + 0x0000000080106f14 __errno + .text 0x0000000080106f20 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-exit.o) + 0x0000000080106f20 exit + .text 0x0000000080106f40 0x30 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fini.o) + 0x0000000080106f40 __libc_fini_array + .text 0x0000000080106f70 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-impure.o) + .text 0x0000000080106f70 0x50 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-init.o) + 0x0000000080106f70 __libc_init_array + .text 0x0000000080106fc0 0xa0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memset.o) + 0x0000000080106fc0 memset + .text 0x0000000080107060 0x4c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-printf.o) + 0x0000000080107060 _printf_r + 0x0000000080107080 printf + .text 0x00000000801070ac 0x154 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-setvbuf.o) + 0x00000000801070ac setvbuf + .text 0x0000000080107200 0x160c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-vfprintf.o) + 0x0000000080107200 _vfprintf_r + 0x0000000080108788 vfprintf + .text 0x000000008010880c 0xc8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wsetup.o) + 0x000000008010880c __swsetup_r + .text 0x00000000801088d4 0x6c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__atexit.o) + 0x00000000801088d4 __register_exitproc + .text 0x0000000080108940 0x9c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + 0x0000000080108940 __call_exitprocs + .text.startup 0x00000000801089dc 0x18 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-__call_atexit.o) + *fill* 0x00000000801089f4 0x4 + .text 0x00000000801089f8 0x10c0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-dtoa.o) + 0x0000000080108b38 _dtoa_r + .text 0x0000000080109ab8 0x1b0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fflush.o) + 0x0000000080109ab8 __sflush_r + 0x0000000080109c0c _fflush_r + 0x0000000080109c40 fflush + .text 0x0000000080109c68 0x210 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-findfp.o) + 0x0000000080109c6c _cleanup_r + 0x0000000080109d60 __sfmoreglue + 0x0000000080109d90 __sfp + 0x0000000080109e18 _cleanup + 0x0000000080109e30 __sinit + 0x0000000080109e38 __sfp_lock_acquire + 0x0000000080109e3c __sfp_lock_release + 0x0000000080109e40 __sinit_lock_acquire + 0x0000000080109e44 __sinit_lock_release + 0x0000000080109e48 __fp_lock_all + 0x0000000080109e60 __fp_unlock_all + .text 0x0000000080109e78 0x2a8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-freer.o) + 0x0000000080109e78 _malloc_trim_r + 0x0000000080109f24 _free_r + .text 0x000000008010a120 0x98 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fwalk.o) + 0x000000008010a120 _fwalk + 0x000000008010a168 _fwalk_reent + .text 0x000000008010a1b8 0x14 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-localeconv.o) + 0x000000008010a1b8 __localeconv_l + 0x000000008010a1bc _localeconv_r + 0x000000008010a1c4 localeconv + .text 0x000000008010a1cc 0xf8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-makebuf.o) + 0x000000008010a1cc __swhatbuf_r + 0x000000008010a228 __smakebuf_r + .text 0x000000008010a2c4 0x20 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-malloc.o) + 0x000000008010a2c4 malloc + 0x000000008010a2d4 free + .text 0x000000008010a2e4 0x588 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mallocr.o) + 0x000000008010a2e4 _malloc_r + .text 0x000000008010a86c 0x8c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memchr-stub.o) + 0x000000008010a86c memchr + .text 0x000000008010a8f8 0xec /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memcpy.o) + 0x000000008010a8f8 memcpy + .text 0x000000008010a9e4 0x8 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mlock.o) + 0x000000008010a9e4 __malloc_lock + 0x000000008010a9e8 __malloc_unlock + .text 0x000000008010a9ec 0x9e0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mprec.o) + 0x000000008010a9ec _Balloc + 0x000000008010aa38 _Bfree + 0x000000008010aa4c __multadd + 0x000000008010aafc __s2b + 0x000000008010abb4 __hi0bits + 0x000000008010abf4 __lo0bits + 0x000000008010ac50 __i2b + 0x000000008010ac80 __multiply + 0x000000008010ade0 __pow5mult + 0x000000008010ae7c __lshift + 0x000000008010af54 __mcmp + 0x000000008010af90 __mdiff + 0x000000008010b0d0 __ulp + 0x000000008010b110 __b2d + 0x000000008010b1d4 __d2b + 0x000000008010b29c __ratio + 0x000000008010b2f4 _mprec_log10 + 0x000000008010b32c __copybits + 0x000000008010b374 __any_on + .text 0x000000008010b3cc 0x28 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-sbrkr.o) + 0x000000008010b3cc _sbrk_r + .text 0x000000008010b3f4 0x90 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-stdio.o) + 0x000000008010b3f4 __sread + 0x000000008010b418 __seofread + 0x000000008010b41c __swrite + 0x000000008010b45c __sseek + 0x000000008010b47c __sclose + .text 0x000000008010b484 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-strlen-stub.o) + 0x000000008010b484 strlen + .text 0x000000008010b4e0 0xd68 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/usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_divsi3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_dvmd_tls.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_addsubdf3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_muldivdf3.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_cmpdf2.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_unorddf2.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_arm_fixdfsi.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_aeabi_uldivmod.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtend.o + .bss 0x000000008100c050 0x0 /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/crtn.o + 0x000000008100c050 __bss_end__ = . + 0x000000008100c050 _bss_end = __bss_end__ + COMMON 0x000000008100c050 0x500 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + 0x000000008100c050 isr_table + COMMON 0x000000008100c550 0x4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + 0x000000008100c550 ft_assert_status + COMMON 0x000000008100c554 0x4 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + 0x000000008100c554 errno + +.heap 0x000000008100c558 0xaa8 load address 0x000000008011c558 + 0x000000008100c558 . = ALIGN (0x8) + 0x000000008100c558 __end__ = . + 0x000000008100c558 PROVIDE (end = .) + 0x000000008100c558 __HeapBase = . + 0x000000008100c958 . = (. + HEAP_SIZE) + *fill* 0x000000008100c558 0x400 + 0x000000008100d000 . = ALIGN (0x1000) + *fill* 0x000000008100c958 0x6a8 + 0x000000008100d000 __HeapLimit = . + 0x000000008100d000 __heap_limit = . + 0x000000008100d000 _fiq_stack_start = (ADDR (.heap) + SIZEOF (.heap)) + 0x000000008100e000 _fiq_stack_end = (_fiq_stack_start + 0x1000) + 0x000000008100e000 _irq_stack_start = _fiq_stack_end + 0x000000008100f000 _irq_stack_end = (_irq_stack_start + 0x1000) + 0x000000008100f000 _sys_stack_start = _irq_stack_end + 0x0000000081010000 _sys_stack_end = (_sys_stack_start + 0x1000) + 0x0000000081010000 _svc_stack_start = _sys_stack_end + 0x0000000081011000 _svc_stack_end = (_svc_stack_start + 0x1000) + 0x0000000000001000 _irq_stack_size = (_irq_stack_end - _irq_stack_start) + 0x0000000000001000 _fiq_stack_size = (_fiq_stack_end - _fiq_stack_start) + 0x0000000000001000 _sys_stack_size = (_sys_stack_end - _sys_stack_start) + 0x0000000000001000 _svc_stack_size = (_svc_stack_end - _svc_stack_start) +OUTPUT(ft2004_baremetal.elf elf32-littlearm) +LOAD linker stubs + +.ARM.attributes + 0x0000000000000000 0x33 + .ARM.attributes + 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./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/vector.o + .ARM.attributes + 0x0000000000000112 0x25 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/smccc-call.o + .ARM.attributes + 0x0000000000000137 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_debug.o + .ARM.attributes + 0x000000000000016e 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/trap.o + .ARM.attributes + 0x00000000000001a5 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/interrupt.o + .ARM.attributes + 0x00000000000001dc 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/common/ft_assert.o + .ARM.attributes + 0x0000000000000213 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/generic_timer.o + .ARM.attributes + 0x000000000000024a 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/psci.o + .ARM.attributes + 0x0000000000000281 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/mmu.o + .ARM.attributes + 0x00000000000002b8 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/cache.o + .ARM.attributes + 0x00000000000002ef 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/fsleep.o + .ARM.attributes + 0x0000000000000326 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/gcc/exception_debug.o + .ARM.attributes + 0x000000000000035d 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/parameters.o + .ARM.attributes + 0x0000000000000394 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .ARM.attributes + 0x00000000000003cb 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .ARM.attributes + 0x0000000000000402 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .ARM.attributes + 0x0000000000000439 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.o + .ARM.attributes + 0x0000000000000470 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .ARM.attributes + 0x00000000000004a7 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .ARM.attributes + 0x00000000000004de 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .ARM.attributes + 0x0000000000000515 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_options.o + .ARM.attributes + 0x000000000000054c 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_intr.o + .ARM.attributes + 0x0000000000000583 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_g.o + .ARM.attributes + 0x00000000000005ba 0x37 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/lib/libc/retarget.o + .ARM.attributes + 0x00000000000005f1 0x37 ./build/./main.o + .ARM.attributes + 0x0000000000000628 0x29 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-atexit.o) + .ARM.attributes + 0x0000000000000651 0x29 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./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/_cpu.o + .debug_frame 0x0000000000000a5c 0x8c ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.o + .debug_frame 0x0000000000000ae8 0x4c4 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/gic/gicv3_arrch32/gicv3.o + .debug_frame 0x0000000000000fac 0xb0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_hw.o + .debug_frame 0x000000000000105c 0x30 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.o + .debug_frame 0x000000000000108c 0x1d0 ./build//mnt/d/project/platform/standalone_sdk/phytium-standalone-sdk/bsp/drivers/usart/pl011_uart/pl011_uart.o + .debug_frame 0x000000000000125c 0xb0 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/usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-fvwrite.o) + .debug_loc 0x000000000000e77a 0x5c /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-isattyr.o) + .debug_loc 0x000000000000e7d6 0x169 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-locale.o) + .debug_loc 0x000000000000e93f 0xbd /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-lseekr.o) + .debug_loc 0x000000000000e9fc 0x24f /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-mbtowc_r.o) + .debug_loc 0x000000000000ec4b 0x373 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-memmove.o) + .debug_loc 0x000000000000efbe 0xbd /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-readr.o) + .debug_loc 0x000000000000f07b 0xf5d /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reallocr.o) + .debug_loc 0x000000000000ffd8 0x152 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-reent.o) + .debug_loc 0x000000000001012a 0x1d7 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wbuf.o) + .debug_loc 0x0000000000010301 0x281 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wcrtomb.o) + .debug_loc 0x0000000000010582 0x118 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-wctomb_r.o) + .debug_loc 0x000000000001069a 0x47b /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signal.o) + .debug_loc 0x0000000000010b15 0xc0 /usr/lib/gcc/arm-none-eabi/9.2.1/../../../arm-none-eabi/lib/thumb/v7/nofp/libc.a(lib_a-signalr.o) + .debug_loc 0x0000000000010bd5 0x20d /usr/lib/gcc/arm-none-eabi/9.2.1/thumb/v7/nofp/libgcc.a(_udivmoddi4.o) diff --git a/baremetal/example/aarch32_hello_world/sdkconfig b/baremetal/example/aarch32_hello_world/sdkconfig index 3f8d35b31..715897170 100644 --- a/baremetal/example/aarch32_hello_world/sdkconfig +++ b/baremetal/example/aarch32_hello_world/sdkconfig @@ -33,6 +33,8 @@ CONFIG_ENVI_UBUNTU_20_04=y # CONFIG_COMPILER_NO_STD_STARUP=y # CONFIG_USE_EXT_COMPILER is not set +CONFIG_USE_SOFT_FLOAT=y +# CONFIG_USE_HARD_FLOAT is not set # end of Cross-Compiler Setting # @@ -56,6 +58,7 @@ CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set # end of Common Configuration # @@ -78,6 +81,14 @@ CONFIG_USE_USART=y # CONFIG_ENABLE_Pl011_UART=y # end of Usart Configuration + +CONFIG_USE_GPIO=y + +# +# Gpio Configuration +# +CONFIG_ENABLE_F_GPIO_UART=y +# end of Gpio Configuration # end of Components Configuration # @@ -95,3 +106,9 @@ CONFIG_USE_MMU=y # CONFIG_USE_NOSTD_LIBC is not set CONFIG_USE_LIBC=y # end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# CONFIG_USE_COREMARK is not set +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_hello_world/sdkconfig.h b/baremetal/example/aarch32_hello_world/sdkconfig.h index be78f3ff5..8bb7d84d0 100644 --- a/baremetal/example/aarch32_hello_world/sdkconfig.h +++ b/baremetal/example/aarch32_hello_world/sdkconfig.h @@ -1,15 +1,99 @@ +#ifndef SDK_CONFIG_H__ +#define SDK_CONFIG_H__ + +/* Project Configuration */ + +/* FT2000-4 AARCH32 Baremetal Configuration */ + #define CONFIG_TARGET_NAME "ft2004_baremetal" -#define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_F2000_4 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_USART 1 -#define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_CACHE 1 -#define CONFIG_USE_L3CACHE 1 -#define CONFIG_USE_MMU 1 -#define CONFIG_USE_LIBC 1 +/* end of FT2000-4 AARCH32 Baremetal Configuration */ +/* end of Project Configuration */ + +/* Target Setting */ + +#define CONFIG_TARGET_ARMV8_AARCH32 +/* CONFIG_TARGET_ARMV8_AARCH64 is not set */ +/* CONFIG_TARGET_ARMV7 is not set */ +#define CONFIG_TARGET_F2000_4 +/* CONFIG_TARGET_AARCH32_QEMU is not set */ +/* CONFIG_TARGET_AARCH64_QEMU is not set */ +/* CONFIG_TARGET_E2000 is not set */ +/* end of Target Setting */ + +/* Building Option */ + +#define CONFIG_ENVI_UBUNTU_20_04 +/* CONFIG_ENVI_WINDOWS10_MINGW is not set */ + +/* Cross-Compiler Setting */ + +#define CONFIG_COMPILER_NO_STD_STARUP +/* CONFIG_USE_EXT_COMPILER is not set */ +#define CONFIG_USE_SOFT_FLOAT +/* CONFIG_USE_HARD_FLOAT is not set */ +/* end of Cross-Compiler Setting */ + +/* GNU linker */ + +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD +/* CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set */ +/* CONFIG_QEMU_AARCH32_RAM_LD is not set */ +/* end of GNU linker */ +/* end of Building Option */ + +/* Board Configuration */ + +/* Common Configuration */ + +/* CONFIG_LOG_VERBOS is not set */ +/* CONFIG_LOG_DEBUG is not set */ +/* CONFIG_LOG_INFO is not set */ +/* CONFIG_LOG_WARN is not set */ +#define CONFIG_LOG_ERROR +/* CONFIG_LOG_NONE is not set */ +/* end of Common Configuration */ + +/* Components Configuration */ + +/* CONFIG_USE_SPI is not set */ +/* CONFIG_USE_QSPI is not set */ +#define CONFIG_USE_GIC + +/* Gic Configuration */ + +#define CONFIG_EBABLE_GICV3 +/* end of Gic Configuration */ +#define CONFIG_USE_USART + +/* Usart Configuration */ + +#define CONFIG_ENABLE_Pl011_UART +/* end of Usart Configuration */ +#define CONFIG_USE_GPIO + +/* Gpio Configuration */ + +#define CONFIG_ENABLE_F_GPIO_UART +/* end of Gpio Configuration */ +/* end of Components Configuration */ + +/* Arch Configuration */ + +#define CONFIG_USE_CACHE +#define CONFIG_USE_L3CACHE +#define CONFIG_USE_MMU +/* end of Arch Configuration */ +/* end of Board Configuration */ + +/* Library Configuration */ + +/* CONFIG_USE_NOSTD_LIBC is not set */ +#define CONFIG_USE_LIBC +/* end of Library Configuration */ + +/* Standalone Third-Party Configuration */ + +/* CONFIG_USE_COREMARK is not set */ +/* end of Standalone Third-Party Configuration */ + +#endif diff --git a/baremetal/example/aarch32_hello_world/sdkconfig.old b/baremetal/example/aarch32_hello_world/sdkconfig.old index b82fce4cb..02ae58fb4 100644 --- a/baremetal/example/aarch32_hello_world/sdkconfig.old +++ b/baremetal/example/aarch32_hello_world/sdkconfig.old @@ -32,8 +32,9 @@ CONFIG_ENVI_UBUNTU_20_04=y # Cross-Compiler Setting # CONFIG_COMPILER_NO_STD_STARUP=y -CONFIG_USE_EXT_COMPILER=y -CONFIG_EXT_COMPILER_PREFIX="/usr" +# CONFIG_USE_EXT_COMPILER is not set +CONFIG_USE_SOFT_FLOAT=y +# CONFIG_USE_HARD_FLOAT is not set # end of Cross-Compiler Setting # @@ -57,6 +58,7 @@ CONFIG_E2000_FT2004_AARCH32_RAM_LD=y # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set # end of Common Configuration # @@ -96,3 +98,9 @@ CONFIG_USE_MMU=y # CONFIG_USE_NOSTD_LIBC is not set CONFIG_USE_LIBC=y # end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# CONFIG_USE_COREMARK is not set +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_math_test/sdkconfig b/baremetal/example/aarch32_math_test/sdkconfig index 3f8d35b31..407014a96 100644 --- a/baremetal/example/aarch32_math_test/sdkconfig +++ b/baremetal/example/aarch32_math_test/sdkconfig @@ -1,97 +1,97 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Target Setting -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Target Setting - -# -# Building Option -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of Building Option - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -# CONFIG_USE_NOSTD_LIBC is not set -CONFIG_USE_LIBC=y -# end of Library Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration diff --git a/baremetal/example/aarch32_math_test/sdkconfig.h b/baremetal/example/aarch32_math_test/sdkconfig.h index be78f3ff5..26515e11d 100644 --- a/baremetal/example/aarch32_math_test/sdkconfig.h +++ b/baremetal/example/aarch32_math_test/sdkconfig.h @@ -1,15 +1,15 @@ -#define CONFIG_TARGET_NAME "ft2004_baremetal" -#define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_F2000_4 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_USART 1 -#define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_CACHE 1 -#define CONFIG_USE_L3CACHE 1 -#define CONFIG_USE_MMU 1 -#define CONFIG_USE_LIBC 1 +#define CONFIG_TARGET_NAME "ft2004_baremetal" +#define CONFIG_TARGET_ARMV8_AARCH32 1 +#define CONFIG_TARGET_F2000_4 1 +#define CONFIG_ENVI_UBUNTU_20_04 1 +#define CONFIG_COMPILER_NO_STD_STARUP 1 +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 +#define CONFIG_LOG_ERROR 1 +#define CONFIG_USE_GIC 1 +#define CONFIG_EBABLE_GICV3 1 +#define CONFIG_USE_USART 1 +#define CONFIG_ENABLE_Pl011_UART 1 +#define CONFIG_USE_CACHE 1 +#define CONFIG_USE_L3CACHE 1 +#define CONFIG_USE_MMU 1 +#define CONFIG_USE_LIBC 1 diff --git a/baremetal/example/aarch32_math_test/sdkconfig.old b/baremetal/example/aarch32_math_test/sdkconfig.old index b82fce4cb..0e4ab7c5b 100644 --- a/baremetal/example/aarch32_math_test/sdkconfig.old +++ b/baremetal/example/aarch32_math_test/sdkconfig.old @@ -1,98 +1,98 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Target Setting -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Target Setting - -# -# Building Option -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -CONFIG_USE_EXT_COMPILER=y -CONFIG_EXT_COMPILER_PREFIX="/usr" -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of Building Option - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -# CONFIG_USE_NOSTD_LIBC is not set -CONFIG_USE_LIBC=y -# end of Library Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +CONFIG_USE_EXT_COMPILER=y +CONFIG_EXT_COMPILER_PREFIX="/usr" +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration diff --git a/baremetal/example/aarch32_qemu_debug/sdkconfig b/baremetal/example/aarch32_qemu_debug/sdkconfig index 412e14ebf..a31227001 100644 --- a/baremetal/example/aarch32_qemu_debug/sdkconfig +++ b/baremetal/example/aarch32_qemu_debug/sdkconfig @@ -1,89 +1,89 @@ - -# -# Project Configuration -# - -# -# Qemu AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="qemu_baremetal" -# end of Qemu AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Build Target -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -# CONFIG_TARGET_F2000_4 is not set -CONFIG_TARGET_AARCH32_QEMU=y -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -# CONFIG_COMPILER_NO_STD_STARUP is not set -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -CONFIG_QEMU_AARCH32_RAM_LD=y -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -# CONFIG_USE_USART is not set -# end of Components Configuration - -# -# Arch Configuration -# -# CONFIG_USE_CACHE is not set -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration + +# +# Project Configuration +# + +# +# Qemu AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="qemu_baremetal" +# end of Qemu AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Build Target +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +# CONFIG_TARGET_F2000_4 is not set +CONFIG_TARGET_AARCH32_QEMU=y +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Build Target + +# +# General Setting +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +# CONFIG_COMPILER_NO_STD_STARUP is not set +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +CONFIG_QEMU_AARCH32_RAM_LD=y +# end of GNU linker +# end of General Setting + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +# CONFIG_USE_USART is not set +# end of Components Configuration + +# +# Arch Configuration +# +# CONFIG_USE_CACHE is not set +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration diff --git a/baremetal/example/aarch32_qemu_debug/sdkconfig.h b/baremetal/example/aarch32_qemu_debug/sdkconfig.h index a50a81d26..81c69a49d 100644 --- a/baremetal/example/aarch32_qemu_debug/sdkconfig.h +++ b/baremetal/example/aarch32_qemu_debug/sdkconfig.h @@ -1,9 +1,9 @@ -#define CONFIG_TARGET_NAME "qemu_baremetal" -#define CONFIG_TARGET_ARMV8_AARCH32 1 -#define CONFIG_TARGET_AARCH32_QEMU 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_QEMU_AARCH32_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_NOSTD_LIBC 1 +#define CONFIG_TARGET_NAME "qemu_baremetal" +#define CONFIG_TARGET_ARMV8_AARCH32 1 +#define CONFIG_TARGET_AARCH32_QEMU 1 +#define CONFIG_ENVI_UBUNTU_20_04 1 +#define CONFIG_QEMU_AARCH32_RAM_LD 1 +#define CONFIG_LOG_ERROR 1 +#define CONFIG_USE_GIC 1 +#define CONFIG_EBABLE_GICV3 1 +#define CONFIG_USE_NOSTD_LIBC 1 diff --git a/baremetal/example/aarch32_timer_irq/README.md b/baremetal/example/aarch32_timer_irq/README.md index 688a60641..6e9eea8a1 100644 --- a/baremetal/example/aarch32_timer_irq/README.md +++ b/baremetal/example/aarch32_timer_irq/README.md @@ -1,52 +1,52 @@ - - -# host侧设置 -- 重启host侧tftp服务器 -``` -sudo service tftpd-hpa restart -``` - -# 开发板侧设置 - -## 使用go命令跳转 -- 关闭D-cache和I-cache -``` -icache off -dcache off -``` - -- 下载新版本到FT2000-4 -``` -setenv ipaddr 192.168.4.20 -setenv serverip 192.168.4.50 -setenv gatewayip 192.168.4.1 -tftpboot 80100000 ft2004_baremetal.bin -bootvx32 -go 0x80100000 -``` - -``` -tftpboot 80100000 ft2004_test_irq.bin -``` - -## 使用bootvx32命令跳转 -- 下载新版本到FT2000-4 -``` -setenv ipaddr 192.168.4.20 -setenv serverip 192.168.4.50 -setenv gatewayip 192.168.4.1 -tftpboot 80100000 ft2004_baremetal.bin -bootvx32 + + +# host侧设置 +- 重启host侧tftp服务器 +``` +sudo service tftpd-hpa restart +``` + +# 开发板侧设置 + +## 使用go命令跳转 +- 关闭D-cache和I-cache +``` +icache off +dcache off +``` + +- 下载新版本到FT2000-4 +``` +setenv ipaddr 192.168.4.20 +setenv serverip 192.168.4.50 +setenv gatewayip 192.168.4.1 +tftpboot 80100000 ft2004_baremetal.bin +bootvx32 +go 0x80100000 +``` + +``` +tftpboot 80100000 ft2004_test_irq.bin +``` + +## 使用bootvx32命令跳转 +- 下载新版本到FT2000-4 +``` +setenv ipaddr 192.168.4.20 +setenv serverip 192.168.4.50 +setenv gatewayip 192.168.4.1 +tftpboot 80100000 ft2004_baremetal.bin +bootvx32 ``` \ No newline at end of file diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig b/baremetal/example/aarch32_timer_irq/sdkconfig index fdfdd2031..b47ed5cb6 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig +++ b/baremetal/example/aarch32_timer_irq/sdkconfig @@ -1,101 +1,101 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Target Setting -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Target Setting - -# -# Building Option -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of Building Option - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# CONFIG_LOG_NONE is not set -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -# CONFIG_USE_CACHE is not set -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration - -# -# Standalone Third-Party Configuration -# -# end of Standalone Third-Party Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +# CONFIG_USE_CACHE is not set +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig.h b/baremetal/example/aarch32_timer_irq/sdkconfig.h index c135688b3..6e54c0e23 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig.h +++ b/baremetal/example/aarch32_timer_irq/sdkconfig.h @@ -1,88 +1,88 @@ -#ifndef SDK_CONFIG_H__ -#define SDK_CONFIG_H__ - -/* Project Configuration */ - -/* FT2000-4 AARCH32 Baremetal Configuration */ - -#define CONFIG_TARGET_NAME "ft2004_baremetal" -/* end of FT2000-4 AARCH32 Baremetal Configuration */ -/* end of Project Configuration */ - -/* Target Setting */ - -#define CONFIG_TARGET_ARMV8_AARCH32 -/* CONFIG_TARGET_ARMV8_AARCH64 is not set */ -/* CONFIG_TARGET_ARMV7 is not set */ -#define CONFIG_TARGET_F2000_4 -/* CONFIG_TARGET_AARCH32_QEMU is not set */ -/* CONFIG_TARGET_AARCH64_QEMU is not set */ -/* CONFIG_TARGET_E2000 is not set */ -/* end of Target Setting */ - -/* Building Option */ - -#define CONFIG_ENVI_UBUNTU_20_04 -/* CONFIG_ENVI_WINDOWS10_MINGW is not set */ - -/* Cross-Compiler Setting */ - -#define CONFIG_COMPILER_NO_STD_STARUP -/* CONFIG_USE_EXT_COMPILER is not set */ -/* end of Cross-Compiler Setting */ - -/* GNU linker */ - -#define CONFIG_E2000_FT2004_AARCH32_RAM_LD -/* CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set */ -/* CONFIG_QEMU_AARCH32_RAM_LD is not set */ -/* end of GNU linker */ -/* end of Building Option */ - -/* Board Configuration */ - -/* Common Configuration */ - -/* CONFIG_LOG_VERBOS is not set */ -/* CONFIG_LOG_DEBUG is not set */ -/* CONFIG_LOG_INFO is not set */ -/* CONFIG_LOG_WARN is not set */ -#define CONFIG_LOG_ERROR -/* CONFIG_LOG_NONE is not set */ -/* end of Common Configuration */ - -/* Components Configuration */ - -/* CONFIG_USE_SPI is not set */ -/* CONFIG_USE_QSPI is not set */ -#define CONFIG_USE_GIC - -/* Gic Configuration */ - -#define CONFIG_EBABLE_GICV3 -/* end of Gic Configuration */ -#define CONFIG_USE_USART - -/* Usart Configuration */ - -#define CONFIG_ENABLE_Pl011_UART -/* end of Usart Configuration */ -/* end of Components Configuration */ - -/* Arch Configuration */ - -/* CONFIG_USE_CACHE is not set */ -/* end of Arch Configuration */ -/* end of Board Configuration */ - -/* Library Configuration */ - -#define CONFIG_USE_NOSTD_LIBC -/* CONFIG_USE_LIBC is not set */ -/* end of Library Configuration */ - -/* Standalone Third-Party Configuration */ - -/* end of Standalone Third-Party Configuration */ - -#endif +#ifndef SDK_CONFIG_H__ +#define SDK_CONFIG_H__ + +/* Project Configuration */ + +/* FT2000-4 AARCH32 Baremetal Configuration */ + +#define CONFIG_TARGET_NAME "ft2004_baremetal" +/* end of FT2000-4 AARCH32 Baremetal Configuration */ +/* end of Project Configuration */ + +/* Target Setting */ + +#define CONFIG_TARGET_ARMV8_AARCH32 +/* CONFIG_TARGET_ARMV8_AARCH64 is not set */ +/* CONFIG_TARGET_ARMV7 is not set */ +#define CONFIG_TARGET_F2000_4 +/* CONFIG_TARGET_AARCH32_QEMU is not set */ +/* CONFIG_TARGET_AARCH64_QEMU is not set */ +/* CONFIG_TARGET_E2000 is not set */ +/* end of Target Setting */ + +/* Building Option */ + +#define CONFIG_ENVI_UBUNTU_20_04 +/* CONFIG_ENVI_WINDOWS10_MINGW is not set */ + +/* Cross-Compiler Setting */ + +#define CONFIG_COMPILER_NO_STD_STARUP +/* CONFIG_USE_EXT_COMPILER is not set */ +/* end of Cross-Compiler Setting */ + +/* GNU linker */ + +#define CONFIG_E2000_FT2004_AARCH32_RAM_LD +/* CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set */ +/* CONFIG_QEMU_AARCH32_RAM_LD is not set */ +/* end of GNU linker */ +/* end of Building Option */ + +/* Board Configuration */ + +/* Common Configuration */ + +/* CONFIG_LOG_VERBOS is not set */ +/* CONFIG_LOG_DEBUG is not set */ +/* CONFIG_LOG_INFO is not set */ +/* CONFIG_LOG_WARN is not set */ +#define CONFIG_LOG_ERROR +/* CONFIG_LOG_NONE is not set */ +/* end of Common Configuration */ + +/* Components Configuration */ + +/* CONFIG_USE_SPI is not set */ +/* CONFIG_USE_QSPI is not set */ +#define CONFIG_USE_GIC + +/* Gic Configuration */ + +#define CONFIG_EBABLE_GICV3 +/* end of Gic Configuration */ +#define CONFIG_USE_USART + +/* Usart Configuration */ + +#define CONFIG_ENABLE_Pl011_UART +/* end of Usart Configuration */ +/* end of Components Configuration */ + +/* Arch Configuration */ + +/* CONFIG_USE_CACHE is not set */ +/* end of Arch Configuration */ +/* end of Board Configuration */ + +/* Library Configuration */ + +#define CONFIG_USE_NOSTD_LIBC +/* CONFIG_USE_LIBC is not set */ +/* end of Library Configuration */ + +/* Standalone Third-Party Configuration */ + +/* end of Standalone Third-Party Configuration */ + +#endif diff --git a/baremetal/example/aarch32_timer_irq/sdkconfig.old b/baremetal/example/aarch32_timer_irq/sdkconfig.old index 114ad191b..613976a81 100644 --- a/baremetal/example/aarch32_timer_irq/sdkconfig.old +++ b/baremetal/example/aarch32_timer_irq/sdkconfig.old @@ -1,95 +1,95 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Target Setting -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Target Setting - -# -# Building Option -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of Building Option - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -# CONFIG_USE_CACHE is not set -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +# CONFIG_USE_CACHE is not set +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration diff --git a/baremetal/example/aarch32_uart_irq/README.md b/baremetal/example/aarch32_uart_irq/README.md index 7bfaccd28..fae75708d 100644 --- a/baremetal/example/aarch32_uart_irq/README.md +++ b/baremetal/example/aarch32_uart_irq/README.md @@ -1,52 +1,52 @@ - - -# host侧设置 -- 重启host侧tftp服务器 -``` -sudo service tftpd-hpa restart -``` - -# 开发板侧设置 - -## 使用go命令跳转 -- 关闭D-cache和I-cache -``` -icache off -dcache off -``` - -- 下载新版本到FT2000-4 -``` -setenv ipaddr 192.168.4.20 -setenv serverip 192.168.4.50 -setenv gatewayip 192.168.4.1 -tftpboot 80100000 ft2004_baremetal.bin -bootvx32 -go 0x80100000 -``` - -``` -tftpboot 80100000 ft2004_test_irq.bin -``` - -## 使用bootvx32命令跳转 -- 下载新版本到FT2000-4 -``` -setenv ipaddr 192.168.4.20 -setenv serverip 192.168.4.50 -setenv gatewayip 192.168.4.1 -tftpboot 80100000 ft2004_baremetal.bin -bootvx32 + + +# host侧设置 +- 重启host侧tftp服务器 +``` +sudo service tftpd-hpa restart +``` + +# 开发板侧设置 + +## 使用go命令跳转 +- 关闭D-cache和I-cache +``` +icache off +dcache off +``` + +- 下载新版本到FT2000-4 +``` +setenv ipaddr 192.168.4.20 +setenv serverip 192.168.4.50 +setenv gatewayip 192.168.4.1 +tftpboot 80100000 ft2004_baremetal.bin +bootvx32 +go 0x80100000 +``` + +``` +tftpboot 80100000 ft2004_test_irq.bin +``` + +## 使用bootvx32命令跳转 +- 下载新版本到FT2000-4 +``` +setenv ipaddr 192.168.4.20 +setenv serverip 192.168.4.50 +setenv gatewayip 192.168.4.1 +tftpboot 80100000 ft2004_baremetal.bin +bootvx32 ``` \ No newline at end of file diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig b/baremetal/example/aarch32_uart_irq/sdkconfig index 02ae58fb4..0a16c7415 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig +++ b/baremetal/example/aarch32_uart_irq/sdkconfig @@ -6,7 +6,7 @@ # # FT2000-4 AARCH32 Baremetal Configuration # -CONFIG_TARGET_NAME="ft2004_baremetal" +CONFIG_TARGET_NAME="e2000_uart_irq" # end of FT2000-4 AARCH32 Baremetal Configuration # end of Project Configuration @@ -16,10 +16,10 @@ CONFIG_TARGET_NAME="ft2004_baremetal" CONFIG_TARGET_ARMV8_AARCH32=y # CONFIG_TARGET_ARMV8_AARCH64 is not set # CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_F2000_4 is not set # CONFIG_TARGET_AARCH32_QEMU is not set # CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set +CONFIG_TARGET_E2000=y # end of Target Setting # @@ -81,6 +81,8 @@ CONFIG_USE_USART=y # CONFIG_ENABLE_Pl011_UART=y # end of Usart Configuration + +# CONFIG_USE_GPIO is not set # end of Components Configuration # diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig.h b/baremetal/example/aarch32_uart_irq/sdkconfig.h index 9a9a51341..ba7387024 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig.h +++ b/baremetal/example/aarch32_uart_irq/sdkconfig.h @@ -5,7 +5,7 @@ /* FT2000-4 AARCH32 Baremetal Configuration */ -#define CONFIG_TARGET_NAME "ft2004_baremetal" +#define CONFIG_TARGET_NAME "e2000_uart_irq" /* end of FT2000-4 AARCH32 Baremetal Configuration */ /* end of Project Configuration */ @@ -14,10 +14,10 @@ #define CONFIG_TARGET_ARMV8_AARCH32 /* CONFIG_TARGET_ARMV8_AARCH64 is not set */ /* CONFIG_TARGET_ARMV7 is not set */ -#define CONFIG_TARGET_F2000_4 +/* CONFIG_TARGET_F2000_4 is not set */ /* CONFIG_TARGET_AARCH32_QEMU is not set */ /* CONFIG_TARGET_AARCH64_QEMU is not set */ -/* CONFIG_TARGET_E2000 is not set */ +#define CONFIG_TARGET_E2000 /* end of Target Setting */ /* Building Option */ @@ -69,6 +69,7 @@ #define CONFIG_ENABLE_Pl011_UART /* end of Usart Configuration */ +/* CONFIG_USE_GPIO is not set */ /* end of Components Configuration */ /* Arch Configuration */ diff --git a/baremetal/example/aarch32_uart_irq/sdkconfig.old b/baremetal/example/aarch32_uart_irq/sdkconfig.old index 0eaed0d0e..ce2fd4cec 100644 --- a/baremetal/example/aarch32_uart_irq/sdkconfig.old +++ b/baremetal/example/aarch32_uart_irq/sdkconfig.old @@ -1,107 +1,106 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Target Setting -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Target Setting - -# -# Building Option -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -CONFIG_USE_SOFT_FLOAT=y -# CONFIG_USE_HARD_FLOAT is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of Building Option - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# CONFIG_LOG_NONE is not set -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -CONFIG_BAUD_RATE=1152000 -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -# CONFIG_USE_NOSTD_LIBC is not set -CONFIG_USE_LIBC=y -# end of Library Configuration - -# -# Standalone Third-Party Configuration -# -# CONFIG_USE_COREMARK is not set -# end of Standalone Third-Party Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Target Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +CONFIG_USE_SOFT_FLOAT=y +# CONFIG_USE_HARD_FLOAT is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration + +# +# Standalone Third-Party Configuration +# +# CONFIG_USE_COREMARK is not set +# end of Standalone Third-Party Configuration diff --git a/baremetal/example/aarch64_uart_irq_send/Kconfig b/baremetal/example/aarch64_uart_irq_send/Kconfig index 7c9725ad4..396aa9e32 100644 --- a/baremetal/example/aarch64_uart_irq_send/Kconfig +++ b/baremetal/example/aarch64_uart_irq_send/Kconfig @@ -1,17 +1,17 @@ -# -# For a description of the syntax of this configuration file, -# see tools/kconfiglib/kconfig-language.txt. -# - -source "$(SDK_ROOT)/Kconfig" - -menu "Project Configuration" - menu "Baremetal Configuration" - - config TARGET_NAME - string "Build Target Name" - default "uart_irq_send" - help - Build Target name for the demo - endmenu +# +# For a description of the syntax of this configuration file, +# see tools/kconfiglib/kconfig-language.txt. +# + +source "$(SDK_ROOT)/Kconfig" + +menu "Project Configuration" + menu "Baremetal Configuration" + + config TARGET_NAME + string "Build Target Name" + default "uart_irq_send" + help + Build Target name for the demo + endmenu endmenu \ No newline at end of file diff --git a/baremetal/example/aarch64_uart_irq_send/Makefile b/baremetal/example/aarch64_uart_irq_send/Makefile index 7d394c534..df6dc2309 100644 --- a/baremetal/example/aarch64_uart_irq_send/Makefile +++ b/baremetal/example/aarch64_uart_irq_send/Makefile @@ -1,17 +1,17 @@ - - - -# specify src code dir -export PROJECT_DIR ?= . - -export DEF_KCONFIG = ft2004_aarch64_baremetal_defconfig - -# prepare output dir and start make -include $(SDK_ROOT)/make/build_baremetal.mk - -boot: - make clean - make - @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ - - + + + +# specify src code dir +export PROJECT_DIR ?= . + +export DEF_KCONFIG = ft2004_aarch64_baremetal_defconfig + +# prepare output dir and start make +include $(SDK_ROOT)/make/build_baremetal.mk + +boot: + make clean + make + @cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ + + diff --git a/baremetal/example/aarch64_uart_irq_send/main.c b/baremetal/example/aarch64_uart_irq_send/main.c index f6723ef71..7945c3264 100644 --- a/baremetal/example/aarch64_uart_irq_send/main.c +++ b/baremetal/example/aarch64_uart_irq_send/main.c @@ -1,108 +1,108 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-22 10:23:24 - * @LastEditTime: 2021-06-30 21:12:16 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "fsleep.h" -#include -#include "parameters.h" -#include "gicv3.h" -#include "exception.h" -#include "trap.h" -#include "generic_timer.h" -#include "interrupt.h" -#include "ft_assert.h" -#include "stdio.h" - -extern void Uart1Init(void); -extern void Uart1TestIrq(void); - -void float_test() -{ - float a = 0; - float b = 0; - float c; - - /* trap an floating exception */ - c = 0.0 / 0.0; - - printf("a %f, b %f, c %f\n", a, b, c); -} - -void common_trap_handler(exception_frame *exc) -{ - if ((exc->exc_type & 0xff) == AARCH64_EXC_SYNC_SPX) - { - // printf("AARCH64_EXC_SYNC_SPX)\r\n"); - SerrHandle(exc); - } - - if ((exc->exc_type & 0xff) == AARCH64_EXC_IRQ_SPX) - { - // printf("AARCH64_EXC_IRQ_SPX)\r\n"); - IrqHandleException(exc); - } - return; -} - -static void irq_timer(void *param) -{ - printf("irq is under process \r\n"); - GenericTimerCompare(48000000 * 2); -} - -u32 PlatformGetGicDistBase(void) -{ - return GICV3_BASEADDRESS; -} - -void irq_test_init(void) -{ - /* interrupt init */ - ArmGicRedistAddressSet(0, GICV3_RD_BASEADDRESS + 0, 0); - InterruptInit(); - - ArmGicDumpType(0); - ArmGicDump(0); - - // GenericTimerCompare(48000000 * 2); - // Aarch64TimerStart(); - // Aarch64TimerInterruptEnable(); - - // InterruptSetPriority(30, 0); - // InterruptInstall(30, irq_timer, NULL, "tick"); - // InterruptUmask(30); -} - -void vMainAssertCalled(const char *pcFileName, uint32_t ulLineNumber) -{ - printf("Assert Error is %s : %d \r\n", pcFileName, ulLineNumber); - for (;;) - ; -} - -static void AssertCallback(const char *File, s32 Line) -{ - printf("Assert Error is %s : %d \r\n", File, Line); -} - -int main(void) -{ - FtAssertSetCb((FtAssertCallback)AssertCallback); - irq_test_init(); - float_test(); - Uart1Init(); - Uart1TestIrq(); - while (1) - { - } +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-22 10:23:24 + * @LastEditTime: 2021-06-30 21:12:16 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "fsleep.h" +#include +#include "parameters.h" +#include "gicv3.h" +#include "exception.h" +#include "trap.h" +#include "generic_timer.h" +#include "interrupt.h" +#include "ft_assert.h" +#include "stdio.h" + +extern void Uart1Init(void); +extern void Uart1TestIrq(void); + +void float_test() +{ + float a = 0; + float b = 0; + float c; + + /* trap an floating exception */ + c = 0.0 / 0.0; + + printf("a %f, b %f, c %f\n", a, b, c); +} + +void common_trap_handler(exception_frame *exc) +{ + if ((exc->exc_type & 0xff) == AARCH64_EXC_SYNC_SPX) + { + // printf("AARCH64_EXC_SYNC_SPX)\r\n"); + SerrHandle(exc); + } + + if ((exc->exc_type & 0xff) == AARCH64_EXC_IRQ_SPX) + { + // printf("AARCH64_EXC_IRQ_SPX)\r\n"); + IrqHandleException(exc); + } + return; +} + +static void irq_timer(void *param) +{ + printf("irq is under process \r\n"); + GenericTimerCompare(48000000 * 2); +} + +u32 PlatformGetGicDistBase(void) +{ + return GICV3_BASEADDRESS; +} + +void irq_test_init(void) +{ + /* interrupt init */ + ArmGicRedistAddressSet(0, GICV3_RD_BASEADDRESS + 0, 0); + InterruptInit(); + + ArmGicDumpType(0); + ArmGicDump(0); + + // GenericTimerCompare(48000000 * 2); + // Aarch64TimerStart(); + // Aarch64TimerInterruptEnable(); + + // InterruptSetPriority(30, 0); + // InterruptInstall(30, irq_timer, NULL, "tick"); + // InterruptUmask(30); +} + +void vMainAssertCalled(const char *pcFileName, uint32_t ulLineNumber) +{ + printf("Assert Error is %s : %d \r\n", pcFileName, ulLineNumber); + for (;;) + ; +} + +static void AssertCallback(const char *File, s32 Line) +{ + printf("Assert Error is %s : %d \r\n", File, Line); +} + +int main(void) +{ + FtAssertSetCb((FtAssertCallback)AssertCallback); + irq_test_init(); + float_test(); + Uart1Init(); + Uart1TestIrq(); + while (1) + { + } } \ No newline at end of file diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig b/baremetal/example/aarch64_uart_irq_send/sdkconfig index 55b0be668..598eebc66 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig @@ -1,97 +1,97 @@ - -# -# Target Setting -# -# CONFIG_TARGET_ARMV8_AARCH32 is not set -CONFIG_TARGET_ARMV8_AARCH64=y -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Target Setting - -# -# Building Option -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set -CONFIG_E2000_FT20004_AARCH64_RAM_LD=y -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of Building Option - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -# CONFIG_USE_NOSTD_LIBC is not set -CONFIG_USE_LIBC=y -# end of Library Configuration - -# -# Project Configuration -# - -# -# Baremetal Configuration -# -CONFIG_TARGET_NAME="uart_irq_send" -# end of Baremetal Configuration -# end of Project Configuration + +# +# Target Setting +# +# CONFIG_TARGET_ARMV8_AARCH32 is not set +CONFIG_TARGET_ARMV8_AARCH64=y +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set +CONFIG_E2000_FT20004_AARCH64_RAM_LD=y +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +# CONFIG_USE_NOSTD_LIBC is not set +CONFIG_USE_LIBC=y +# end of Library Configuration + +# +# Project Configuration +# + +# +# Baremetal Configuration +# +CONFIG_TARGET_NAME="uart_irq_send" +# end of Baremetal Configuration +# end of Project Configuration diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig.h b/baremetal/example/aarch64_uart_irq_send/sdkconfig.h index 9feb5759e..7f49fb3e7 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig.h +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig.h @@ -1,15 +1,15 @@ -#define CONFIG_TARGET_ARMV8_AARCH64 1 -#define CONFIG_TARGET_F2000_4 1 -#define CONFIG_ENVI_UBUNTU_20_04 1 -#define CONFIG_COMPILER_NO_STD_STARUP 1 -#define CONFIG_E2000_FT20004_AARCH64_RAM_LD 1 -#define CONFIG_LOG_ERROR 1 -#define CONFIG_USE_GIC 1 -#define CONFIG_EBABLE_GICV3 1 -#define CONFIG_USE_USART 1 -#define CONFIG_ENABLE_Pl011_UART 1 -#define CONFIG_USE_CACHE 1 -#define CONFIG_USE_L3CACHE 1 -#define CONFIG_USE_MMU 1 -#define CONFIG_USE_LIBC 1 -#define CONFIG_TARGET_NAME "uart_irq_send" +#define CONFIG_TARGET_ARMV8_AARCH64 1 +#define CONFIG_TARGET_F2000_4 1 +#define CONFIG_ENVI_UBUNTU_20_04 1 +#define CONFIG_COMPILER_NO_STD_STARUP 1 +#define CONFIG_E2000_FT20004_AARCH64_RAM_LD 1 +#define CONFIG_LOG_ERROR 1 +#define CONFIG_USE_GIC 1 +#define CONFIG_EBABLE_GICV3 1 +#define CONFIG_USE_USART 1 +#define CONFIG_ENABLE_Pl011_UART 1 +#define CONFIG_USE_CACHE 1 +#define CONFIG_USE_L3CACHE 1 +#define CONFIG_USE_MMU 1 +#define CONFIG_USE_LIBC 1 +#define CONFIG_TARGET_NAME "uart_irq_send" diff --git a/baremetal/example/aarch64_uart_irq_send/sdkconfig.old b/baremetal/example/aarch64_uart_irq_send/sdkconfig.old index 838a710ba..9bd2fc98a 100644 --- a/baremetal/example/aarch64_uart_irq_send/sdkconfig.old +++ b/baremetal/example/aarch64_uart_irq_send/sdkconfig.old @@ -1,97 +1,97 @@ - -# -# Target Setting -# -# CONFIG_TARGET_ARMV8_AARCH32 is not set -CONFIG_TARGET_ARMV8_AARCH64=y -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Target Setting - -# -# Building Option -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set -CONFIG_E2000_FT20004_AARCH64_RAM_LD=y -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of Building Option - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration - -# -# Project Configuration -# - -# -# Baremetal Configuration -# -CONFIG_TARGET_NAME="uart_irq_send" -# end of Baremetal Configuration -# end of Project Configuration + +# +# Target Setting +# +# CONFIG_TARGET_ARMV8_AARCH32 is not set +CONFIG_TARGET_ARMV8_AARCH64=y +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Target Setting + +# +# Building Option +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set +CONFIG_E2000_FT20004_AARCH64_RAM_LD=y +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of Building Option + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration + +# +# Project Configuration +# + +# +# Baremetal Configuration +# +CONFIG_TARGET_NAME="uart_irq_send" +# end of Baremetal Configuration +# end of Project Configuration diff --git a/baremetal/example/aarch64_uart_irq_send/uart1.c b/baremetal/example/aarch64_uart_irq_send/uart1.c index 86fc7e7df..42854ef39 100644 --- a/baremetal/example/aarch64_uart_irq_send/uart1.c +++ b/baremetal/example/aarch64_uart_irq_send/uart1.c @@ -1,63 +1,63 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-22 10:23:24 - * @LastEditTime: 2021-07-01 18:03:51 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart.h" -#include "interrupt.h" -#include "gicv3_cpuif.h" -#include "interrupt.h" -#include "stdio.h" -#include "string.h" - -Pl011 pl011_obj; - -volatile u64 get_uart_rx_flg = 0; -volatile u8 set_irq_priority = 0; -u8 get_byte; - -static void FtFreeUartCallback(void *args, u32 event, u32 event_data) -{ - get_uart_rx_flg = 1; - // printf("%x %x \r\n", set_irq_priority, getRunningPriority()); - get_byte = Pl011BlockReceive(&pl011_obj); - Pl011IrqClearReciveTimeOut(&pl011_obj); -} - -static void FtFreertosUartIrq(s32 vector, void *param) -{ - Pl011InterruptHandler(param); -} - -void Uart1Init(void) -{ - Pl011CfgInitialize(&pl011_obj, Pl011LookupConfig(1)); - Pl011SetHandler(&pl011_obj, FtFreeUartCallback, NULL); - InterruptSetPriority(pl011_obj.config.irq_num, set_irq_priority); - InterruptInstall(pl011_obj.config.irq_num, FtFreertosUartIrq, &pl011_obj, "uart1"); - InterruptUmask(pl011_obj.config.irq_num); - Pl011SetOptions(&pl011_obj, FUART_OPTION_UARTEN | FUART_OPTION_RXEN | FUART_OPTION_TXEN | FUART_OPTION_FIFOEN); - Pl011IrqEnableReciveTimeOut(&pl011_obj); -} - -void Uart1TestIrq(void) -{ - char temp_buffer[] = "0123456789abcdefghijklnmopqrstuvwxyz"; - while (1) - { - while (get_uart_rx_flg == 0) - ; - Pl011Send(&pl011_obj, temp_buffer, strlen(temp_buffer)); - get_uart_rx_flg = 0; - Pl011IrqEnableReciveTimeOut(&pl011_obj); - } -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-22 10:23:24 + * @LastEditTime: 2021-07-01 18:03:51 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart.h" +#include "interrupt.h" +#include "gicv3_cpuif.h" +#include "interrupt.h" +#include "stdio.h" +#include "string.h" + +Pl011 pl011_obj; + +volatile u64 get_uart_rx_flg = 0; +volatile u8 set_irq_priority = 0; +u8 get_byte; + +static void FtFreeUartCallback(void *args, u32 event, u32 event_data) +{ + get_uart_rx_flg = 1; + // printf("%x %x \r\n", set_irq_priority, getRunningPriority()); + get_byte = Pl011BlockReceive(&pl011_obj); + Pl011IrqClearReciveTimeOut(&pl011_obj); +} + +static void FtFreertosUartIrq(s32 vector, void *param) +{ + Pl011InterruptHandler(param); +} + +void Uart1Init(void) +{ + Pl011CfgInitialize(&pl011_obj, Pl011LookupConfig(1)); + Pl011SetHandler(&pl011_obj, FtFreeUartCallback, NULL); + InterruptSetPriority(pl011_obj.config.irq_num, set_irq_priority); + InterruptInstall(pl011_obj.config.irq_num, FtFreertosUartIrq, &pl011_obj, "uart1"); + InterruptUmask(pl011_obj.config.irq_num); + Pl011SetOptions(&pl011_obj, FUART_OPTION_UARTEN | FUART_OPTION_RXEN | FUART_OPTION_TXEN | FUART_OPTION_FIFOEN); + Pl011IrqEnableReciveTimeOut(&pl011_obj); +} + +void Uart1TestIrq(void) +{ + char temp_buffer[] = "0123456789abcdefghijklnmopqrstuvwxyz"; + while (1) + { + while (get_uart_rx_flg == 0) + ; + Pl011Send(&pl011_obj, temp_buffer, strlen(temp_buffer)); + get_uart_rx_flg = 0; + Pl011IrqEnableReciveTimeOut(&pl011_obj); + } +} diff --git a/bsp/Kconfig b/bsp/Kconfig index b0023a89a..10a870e30 100644 --- a/bsp/Kconfig +++ b/bsp/Kconfig @@ -1,7 +1,7 @@ -menu "Board Configuration" - -source "$(SDK_ROOT)/bsp/common/Kconfig" -source "$(SDK_ROOT)/bsp/drivers/Kconfig" -source "$(SDK_ROOT)/bsp/arch/Kconfig" - +menu "Board Configuration" + +source "$(SDK_ROOT)/bsp/common/Kconfig" +source "$(SDK_ROOT)/bsp/drivers/Kconfig" +source "$(SDK_ROOT)/bsp/arch/Kconfig" + endmenu \ No newline at end of file diff --git a/bsp/arch/Kconfig b/bsp/arch/Kconfig index 1a5e7251a..4d6b2a521 100644 --- a/bsp/arch/Kconfig +++ b/bsp/arch/Kconfig @@ -1,27 +1,27 @@ -menu "Arch Configuration" - -config USE_CACHE - bool - prompt "Use Cache" - default n - help - Activate the MMU and TLB functions - - if USE_CACHE - config USE_L3CACHE - bool - prompt "Use external L3 Cache" - default n - help - Include L3 Cache and enable - - config USE_MMU - bool - prompt "Use MMU" - default n - help - Include platform mmu setting - endif - -endmenu - +menu "Arch Configuration" + +config USE_CACHE + bool + prompt "Use Cache" + default n + help + Activate the MMU and TLB functions + + if USE_CACHE + config USE_L3CACHE + bool + prompt "Use external L3 Cache" + default n + help + Include L3 Cache and enable + + config USE_MMU + bool + prompt "Use MMU" + default n + help + Include platform mmu setting + endif + +endmenu + diff --git a/bsp/arch/armv8/aarch32/aarch32.h b/bsp/arch/armv8/aarch32/aarch32.h index 361088f09..9c725f3da 100644 --- a/bsp/arch/armv8/aarch32/aarch32.h +++ b/bsp/arch/armv8/aarch32/aarch32.h @@ -1,404 +1,404 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-23 15:01:04 - * @LastEditTime: 2021-06-29 17:30:11 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_AARCH32_ASM_H -#define BSP_AARCH32_ASM_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - -#define __ASM __asm -#define __STATIC_INLINE static inline -#define __STRINGIFY(x) #x -/* C语言实现MCR指令 */ -#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \ - __ASM volatile("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ - "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \ - : \ - : "r"(src) \ - : "memory"); - -/* C语言实现MRC指令 */ -#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \ - ( \ - { \ - u32 __dst; \ - __ASM volatile("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ - "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \ - : "=r"(__dst)::"memory"); \ - __dst; \ - }) - -/* C语言实现MRRC指令 */ -#define __MRRC(coproc, opcode_1, dst_1, dst_2, CRm) ( \ -{ \ - __asm__ __volatile__( \ - "MRRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " "%0,%1," __STRINGIFY(c##CRm) \ - : "=r"(dst_1), "=r"(dst_2)); \ -}) - - /** - * @name: aarch32_cntp_ctl_get - * @msg: Read the register that holds the timer value for the EL1 physical timer. - * @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. - */ - __attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_ctl_get(void) - { - /* MRC p15(coproc) 0(opcode1) CR14(n) CR2(m) 1(opcode2) */ - return __MRC(15, 0, 14, 2, 1); - } - - /** - * @name: aarch32_cntp_tlb_get - * @msg: - * @return {*} - * @param {__STATIC_INLINE u32} aarch32_cntp_ctl_get - */ - __attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_tlb_get(void) - { - return __MRC(15, 0, 0, 2, 0); - } - - /** - * @name: aarch32_cntp_ctl_set - * @msg: Read the register that holds the timer value for the EL1 physical timer. - * @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. - */ - __attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_ctl_set(u32 regVal) - { - /* MRC p15(coproc) regVal 0(opcode1) CR14(n) CR2(m) 1(opcode2) */ - __MCR(15, 0, regVal, 14, 2, 1); - } - - /** - * @name: arm_aarch32_cntfrq_get - * @msg: This register is provided so that software can discover the frequency of the system counter. - * @return {__STATIC_INLINEu32}: frequency of the system counter - */ - __attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntfrq_get(void) - { - return __MRC(15, 0, 14, 0, 0); - } - - /** - * @name: aarch32_cntpct_get - * @msg: get the 64-bit physical count value - * @return {*} - * @param {__STATIC_INLINE u64} aarch32_cntpct_get - */ - __attribute__((always_inline)) __STATIC_INLINE u64 aarch32_cntpct_get() - { - u64 cnt = 0; - u32 cnt_low = 0, cnt_high = 0; - __MRRC(15, 0, cnt_low, cnt_high, 14); - cnt = (u64)cnt_high << 32 | cnt_low; - return cnt; - } - - /** - * @name: aarch32_cntp_tval_set - * @msg: write the register that control register for the EL1 physical timer. - * @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. - */ - __attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_tval_set(u32 RegValue) - { - __MCR(15, 0, RegValue, 14, 2, 0); - } - - /** - * @name: aarch32_sctrl_get - * @msg: read the register that control system - */ - __attribute__((always_inline)) __STATIC_INLINE u32 aarch32_sctrl_get() - { - return __MRC(15, 0, 1, 0, 0); - } - - /** - * @name: aarch32_sctrl_set - * @msg: read the register that control system - */ - #define AARCH32_SCTRL_CACHE_BIT (1 << 2) /* 1: enable, 0: disable */ - __attribute__((always_inline)) __STATIC_INLINE void aarch32_sctrl_set(u32 RegVal) - { - __MCR(15, 0, RegVal, 1, 0, 0); - } - -/**********************************************/ - - __attribute__((always_inline)) __STATIC_INLINE u32 __get_VBAR(void) - { - return __MRC(15, 0, 12, 0, 0); - } - - __attribute__((always_inline)) __STATIC_INLINE void __set_VBAR(u32 vbar) - { - __MCR(15, 0, vbar, 12, 0, 0); - } - - __attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen0_set(u32 value) - { - __MCR(15, 0, value, 12, 12, 6); - } - - __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen0_get(void) - { - return __MRC(15, 0, 12, 12, 6); - } - - __attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen1_set(u32 value) - { - __MCR(15, 0, value, 12, 12, 7); - } - - __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen1_get(void) - { - return __MRC(15, 0, 12, 12, 7); - } - - __attribute__((always_inline)) __STATIC_INLINE void sys_icc_ctlr_set(u32 value) - { - __MCR(15, 0, value, 12, 12, 4); - } - - __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_ctlr_get(void) - { - return __MRC(15, 0, 12, 12, 4); - } - - __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir0_get(void) - { - return __MRC(15, 0, 12, 8, 2); - } - - __attribute__((always_inline)) __STATIC_INLINE void sys_icc_bpr_set(u32 value) - { - __MCR(15, 0, value, 12, 8, 3); - } - - __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_bpr_get(void) - { - return __MRC(15, 0, 12, 8, 3); - } - - __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir1_get(void) - { - return __MRC(15, 0, 12, 12, 2); - } - - __attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir0_set(u32 value) - { - __MCR(15, 0, value, 12, 8, 1); - } - - __attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir1_set(u32 value) - { - __MCR(15, 0, value, 12, 12, 1); - } - - __attribute__((always_inline)) __STATIC_INLINE void sys_icc_pmr_set(u32 value) - { - __MCR(15, 0, value, 4, 6, 0); - } - - __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_pmr_get(void) - { - return __MRC(15, 0, 4, 6, 0); - } - - __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_iar1_get(void) - { - return __MRC(15, 0, 12, 12, 0); - } - - __attribute__((always_inline)) __STATIC_INLINE void sys_icc_sre_set(u32 value) - { - __MCR(15, 0, value, 12, 12, 5); - } - - __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_sre_get(void) - { - return __MRC(15, 0, 12, 12, 5); - } - - __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_rpr_get(void) - { - return __MRC(15, 0, 12, 11, 3); - } - - /* Generic Timer registers */ - /** - * @name: arm_aarch32_cntfrq_get - * @msg: This register is provided so that software can discover the frequency of the system counter. - * @return {__STATIC_INLINEu32}: frequency of the system counter - */ - __attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntfrq_get(void) - { - return __MRC(15, 0, 14, 0, 0); - } - - /* arm_aarch32_cnttimer_set */ - __attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnttimer_set(u32 RegValue) - { - __MCR(15, 0, RegValue, 14, 2, 2); - } - - /** - * @name: arm_aarch32_cnthv_tval_get - * @msg: Provides AArch32 access to the timer value for the EL2 virtual timer. - * @return {__STATIC_INLINEu32}: EL2 virtual timer Cnt. - */ - __attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_tval_get(void) - { - return __MRC(15, 0, 14, 3, 0); - } - - /** - * @name: arm_aarch32_cnthv_ctl_set - * @msg: Provides AArch32 access to the control register for the EL2 virtual timer. - * @in param {u32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled. - * IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit. - * ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. rea-only - */ - __attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_ctl_set(u32 RegValue) - { - __MCR(15, 0, RegValue, 14, 3, 1); - } - - /** - * @name: arm_aarch32_cnthv_ctl_get - * @msg: Provides AArch32 access to the control register for the EL2 virtual timer. - * @return {__STATIC_INLINEu32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled. - * IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit. - * ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. read-only - */ - __attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_ctl_get(void) - { - return __MRC(15, 0, 14, 3, 1); - } - - /** - * @name: arm_aarch32_cnthv_tval_set - * @msg: Provides AArch32 access to the timer value for the EL2 virtual timer. - * @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL2 virtual timer. - */ - __attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_tval_set(u32 RegValue) - { - __MCR(15, 0, RegValue, 14, 3, 0); - } - - /** - * @name: arm_aarch32_cntvct_get - * @msg: Read the register that holds the 64-bit virtual count value. The virtual count value is equal to the physical count value visible in CNTPCT minus the virtual offset visible in CNTVOFF. - * @return {__STATIC_INLINEu64}Bits [63:0] Virtual count value. - */ - __attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntvct_get(void) - { - /* "r0" --- low, - "r1" --- hi - */ - u32 low; - u32 hi; - __asm__ volatile( - ".word 0xec510f1e \n" /* mrrc p15, 1, r0, r1, c14 */ - "mov %0, r0 \n" - "mov %1, r1 \n" - : "=&r"(low), "=&r"(hi)); - return (((u64)hi) << 32) | low; - } - - /* physical */ - - /** - * @name: arm_aarch32_cntp_tval_get - * @msg: Read the register that holds the timer value for the EL1 physical timer. - * @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. - */ - __attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_tval_get(void) - { - return __MRC(15, 0, 14, 2, 0); - } - - /** - * @name: arm_aarch32_cntp_tval_set - * @msg: write the register that control register for the EL1 physical timer. - * @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. - */ - __attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_tval_set(u32 RegValue) - { - __MCR(15, 0, RegValue, 14, 2, 0); - } - - /** - * @name: arm_aarch32_cntp_ctl_set - * @msg: write the register that control register for the EL1 physical timer. - * @in param {u32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer. - */ - __attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_ctl_set(u32 RegValue) - { - __MCR(15, 0, RegValue, 14, 2, 1); - } - - /** - * @name: arm_aarch32_cntp_ctl_get - * @msg: Read the register that control register for the EL1 physical timer. - * @return {__STATIC_INLINEu32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer. - */ - __attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_ctl_get(void) - { - return __MRC(15, 0, 14, 2, 1); - } - - /** - * @name: arm_aarch32_cntpct_get - * @msg: Read the register that holds the 64-bit physical count value. - * @return {__STATIC_INLINEu64} CompareValue, bits [63:0] Physical count value. - */ - __attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntpct_get(void) - { - /* "r0" --- low, - "r1" --- hi - */ - u32 low; - u32 hi; - __asm__ volatile( - - ".word 0xec510f0e \n" /* mrrc p15, 0, r0, r1, c14 */ - "mov %0, r0 \n" - "mov %1, r1 \n" - : "=&r"(low), "=&r"(hi)); - return (((u64)hi) << 32) | low; - } - -#define IRQ_DISABLE() \ - __asm volatile("CPSID i" :: \ - : "memory"); \ - __asm volatile("DSB"); \ - __asm volatile("ISB"); - -#define IRQ_ENABLE() \ - __asm volatile("CPSIE i" :: \ - : "memory"); \ - __asm volatile("DSB"); \ - __asm volatile("ISB"); - -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-23 15:01:04 + * @LastEditTime: 2021-06-29 17:30:11 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_AARCH32_ASM_H +#define BSP_AARCH32_ASM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + +#define __ASM __asm +#define __STATIC_INLINE static inline +#define __STRINGIFY(x) #x +/* C语言实现MCR指令 */ +#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \ + __ASM volatile("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \ + : \ + : "r"(src) \ + : "memory"); + +/* C语言实现MRC指令 */ +#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \ + ( \ + { \ + u32 __dst; \ + __ASM volatile("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \ + : "=r"(__dst)::"memory"); \ + __dst; \ + }) + +/* C语言实现MRRC指令 */ +#define __MRRC(coproc, opcode_1, dst_1, dst_2, CRm) ( \ +{ \ + __asm__ __volatile__( \ + "MRRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " "%0,%1," __STRINGIFY(c##CRm) \ + : "=r"(dst_1), "=r"(dst_2)); \ +}) + + /** + * @name: aarch32_cntp_ctl_get + * @msg: Read the register that holds the timer value for the EL1 physical timer. + * @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. + */ + __attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_ctl_get(void) + { + /* MRC p15(coproc) 0(opcode1) CR14(n) CR2(m) 1(opcode2) */ + return __MRC(15, 0, 14, 2, 1); + } + + /** + * @name: aarch32_cntp_tlb_get + * @msg: + * @return {*} + * @param {__STATIC_INLINE u32} aarch32_cntp_ctl_get + */ + __attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_tlb_get(void) + { + return __MRC(15, 0, 0, 2, 0); + } + + /** + * @name: aarch32_cntp_ctl_set + * @msg: Read the register that holds the timer value for the EL1 physical timer. + * @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. + */ + __attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_ctl_set(u32 regVal) + { + /* MRC p15(coproc) regVal 0(opcode1) CR14(n) CR2(m) 1(opcode2) */ + __MCR(15, 0, regVal, 14, 2, 1); + } + + /** + * @name: arm_aarch32_cntfrq_get + * @msg: This register is provided so that software can discover the frequency of the system counter. + * @return {__STATIC_INLINEu32}: frequency of the system counter + */ + __attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntfrq_get(void) + { + return __MRC(15, 0, 14, 0, 0); + } + + /** + * @name: aarch32_cntpct_get + * @msg: get the 64-bit physical count value + * @return {*} + * @param {__STATIC_INLINE u64} aarch32_cntpct_get + */ + __attribute__((always_inline)) __STATIC_INLINE u64 aarch32_cntpct_get() + { + u64 cnt = 0; + u32 cnt_low = 0, cnt_high = 0; + __MRRC(15, 0, cnt_low, cnt_high, 14); + cnt = (u64)cnt_high << 32 | cnt_low; + return cnt; + } + + /** + * @name: aarch32_cntp_tval_set + * @msg: write the register that control register for the EL1 physical timer. + * @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. + */ + __attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_tval_set(u32 RegValue) + { + __MCR(15, 0, RegValue, 14, 2, 0); + } + + /** + * @name: aarch32_sctrl_get + * @msg: read the register that control system + */ + __attribute__((always_inline)) __STATIC_INLINE u32 aarch32_sctrl_get() + { + return __MRC(15, 0, 1, 0, 0); + } + + /** + * @name: aarch32_sctrl_set + * @msg: read the register that control system + */ + #define AARCH32_SCTRL_CACHE_BIT (1 << 2) /* 1: enable, 0: disable */ + __attribute__((always_inline)) __STATIC_INLINE void aarch32_sctrl_set(u32 RegVal) + { + __MCR(15, 0, RegVal, 1, 0, 0); + } + +/**********************************************/ + + __attribute__((always_inline)) __STATIC_INLINE u32 __get_VBAR(void) + { + return __MRC(15, 0, 12, 0, 0); + } + + __attribute__((always_inline)) __STATIC_INLINE void __set_VBAR(u32 vbar) + { + __MCR(15, 0, vbar, 12, 0, 0); + } + + __attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen0_set(u32 value) + { + __MCR(15, 0, value, 12, 12, 6); + } + + __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen0_get(void) + { + return __MRC(15, 0, 12, 12, 6); + } + + __attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen1_set(u32 value) + { + __MCR(15, 0, value, 12, 12, 7); + } + + __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen1_get(void) + { + return __MRC(15, 0, 12, 12, 7); + } + + __attribute__((always_inline)) __STATIC_INLINE void sys_icc_ctlr_set(u32 value) + { + __MCR(15, 0, value, 12, 12, 4); + } + + __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_ctlr_get(void) + { + return __MRC(15, 0, 12, 12, 4); + } + + __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir0_get(void) + { + return __MRC(15, 0, 12, 8, 2); + } + + __attribute__((always_inline)) __STATIC_INLINE void sys_icc_bpr_set(u32 value) + { + __MCR(15, 0, value, 12, 8, 3); + } + + __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_bpr_get(void) + { + return __MRC(15, 0, 12, 8, 3); + } + + __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir1_get(void) + { + return __MRC(15, 0, 12, 12, 2); + } + + __attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir0_set(u32 value) + { + __MCR(15, 0, value, 12, 8, 1); + } + + __attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir1_set(u32 value) + { + __MCR(15, 0, value, 12, 12, 1); + } + + __attribute__((always_inline)) __STATIC_INLINE void sys_icc_pmr_set(u32 value) + { + __MCR(15, 0, value, 4, 6, 0); + } + + __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_pmr_get(void) + { + return __MRC(15, 0, 4, 6, 0); + } + + __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_iar1_get(void) + { + return __MRC(15, 0, 12, 12, 0); + } + + __attribute__((always_inline)) __STATIC_INLINE void sys_icc_sre_set(u32 value) + { + __MCR(15, 0, value, 12, 12, 5); + } + + __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_sre_get(void) + { + return __MRC(15, 0, 12, 12, 5); + } + + __attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_rpr_get(void) + { + return __MRC(15, 0, 12, 11, 3); + } + + /* Generic Timer registers */ + /** + * @name: arm_aarch32_cntfrq_get + * @msg: This register is provided so that software can discover the frequency of the system counter. + * @return {__STATIC_INLINEu32}: frequency of the system counter + */ + __attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntfrq_get(void) + { + return __MRC(15, 0, 14, 0, 0); + } + + /* arm_aarch32_cnttimer_set */ + __attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnttimer_set(u32 RegValue) + { + __MCR(15, 0, RegValue, 14, 2, 2); + } + + /** + * @name: arm_aarch32_cnthv_tval_get + * @msg: Provides AArch32 access to the timer value for the EL2 virtual timer. + * @return {__STATIC_INLINEu32}: EL2 virtual timer Cnt. + */ + __attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_tval_get(void) + { + return __MRC(15, 0, 14, 3, 0); + } + + /** + * @name: arm_aarch32_cnthv_ctl_set + * @msg: Provides AArch32 access to the control register for the EL2 virtual timer. + * @in param {u32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled. + * IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit. + * ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. rea-only + */ + __attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_ctl_set(u32 RegValue) + { + __MCR(15, 0, RegValue, 14, 3, 1); + } + + /** + * @name: arm_aarch32_cnthv_ctl_get + * @msg: Provides AArch32 access to the control register for the EL2 virtual timer. + * @return {__STATIC_INLINEu32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled. + * IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit. + * ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. read-only + */ + __attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_ctl_get(void) + { + return __MRC(15, 0, 14, 3, 1); + } + + /** + * @name: arm_aarch32_cnthv_tval_set + * @msg: Provides AArch32 access to the timer value for the EL2 virtual timer. + * @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL2 virtual timer. + */ + __attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_tval_set(u32 RegValue) + { + __MCR(15, 0, RegValue, 14, 3, 0); + } + + /** + * @name: arm_aarch32_cntvct_get + * @msg: Read the register that holds the 64-bit virtual count value. The virtual count value is equal to the physical count value visible in CNTPCT minus the virtual offset visible in CNTVOFF. + * @return {__STATIC_INLINEu64}Bits [63:0] Virtual count value. + */ + __attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntvct_get(void) + { + /* "r0" --- low, + "r1" --- hi + */ + u32 low; + u32 hi; + __asm__ volatile( + ".word 0xec510f1e \n" /* mrrc p15, 1, r0, r1, c14 */ + "mov %0, r0 \n" + "mov %1, r1 \n" + : "=&r"(low), "=&r"(hi)); + return (((u64)hi) << 32) | low; + } + + /* physical */ + + /** + * @name: arm_aarch32_cntp_tval_get + * @msg: Read the register that holds the timer value for the EL1 physical timer. + * @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. + */ + __attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_tval_get(void) + { + return __MRC(15, 0, 14, 2, 0); + } + + /** + * @name: arm_aarch32_cntp_tval_set + * @msg: write the register that control register for the EL1 physical timer. + * @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. + */ + __attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_tval_set(u32 RegValue) + { + __MCR(15, 0, RegValue, 14, 2, 0); + } + + /** + * @name: arm_aarch32_cntp_ctl_set + * @msg: write the register that control register for the EL1 physical timer. + * @in param {u32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer. + */ + __attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_ctl_set(u32 RegValue) + { + __MCR(15, 0, RegValue, 14, 2, 1); + } + + /** + * @name: arm_aarch32_cntp_ctl_get + * @msg: Read the register that control register for the EL1 physical timer. + * @return {__STATIC_INLINEu32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer. + */ + __attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_ctl_get(void) + { + return __MRC(15, 0, 14, 2, 1); + } + + /** + * @name: arm_aarch32_cntpct_get + * @msg: Read the register that holds the 64-bit physical count value. + * @return {__STATIC_INLINEu64} CompareValue, bits [63:0] Physical count value. + */ + __attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntpct_get(void) + { + /* "r0" --- low, + "r1" --- hi + */ + u32 low; + u32 hi; + __asm__ volatile( + + ".word 0xec510f0e \n" /* mrrc p15, 0, r0, r1, c14 */ + "mov %0, r0 \n" + "mov %1, r1 \n" + : "=&r"(low), "=&r"(hi)); + return (((u64)hi) << 32) | low; + } + +#define IRQ_DISABLE() \ + __asm volatile("CPSID i" :: \ + : "memory"); \ + __asm volatile("DSB"); \ + __asm volatile("ISB"); + +#define IRQ_ENABLE() \ + __asm volatile("CPSIE i" :: \ + : "memory"); \ + __asm volatile("DSB"); \ + __asm volatile("ISB"); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/cp15.h b/bsp/arch/armv8/aarch32/cp15.h index 74a7a6faa..0f833606c 100644 --- a/bsp/arch/armv8/aarch32/cp15.h +++ b/bsp/arch/armv8/aarch32/cp15.h @@ -1,41 +1,41 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 14:51:38 - * @LastEditTime: 2021-06-22 15:23:59 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_ARCH_ARMV8_AARCH32_CP15 -#define BSP_ARCH_ARMV8_AARCH32_CP15 - -#define __get_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) -#define __set_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) -#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) -#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) - -unsigned long cpu_get_smp_id(void); -void cpu_mmu_disable(void); -void cpu_mmu_enable(void); -void cpu_tlb_set(volatile unsigned long *); -void cpu_dcache_clean_flush(void); -void cpu_icache_flush(void); -void cpu_vector_set_base(unsigned int addr); - -void cpu_dcache_disable(); -void cpu_icache_disable(); -void cpu_icache_enable(); -void cpu_dcache_enable(); - -s32 cp15_get_cpu_id(); -void cp15_set_vector_base(unsigned int addr); -s32 DisableInterrupt(); -void EnableInterrupt(s32 level); - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 14:51:38 + * @LastEditTime: 2021-06-22 15:23:59 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_CP15 +#define BSP_ARCH_ARMV8_AARCH32_CP15 + +#define __get_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +unsigned long cpu_get_smp_id(void); +void cpu_mmu_disable(void); +void cpu_mmu_enable(void); +void cpu_tlb_set(volatile unsigned long *); +void cpu_dcache_clean_flush(void); +void cpu_icache_flush(void); +void cpu_vector_set_base(unsigned int addr); + +void cpu_dcache_disable(); +void cpu_icache_disable(); +void cpu_icache_enable(); +void cpu_dcache_enable(); + +s32 cp15_get_cpu_id(); +void cp15_set_vector_base(unsigned int addr); +s32 DisableInterrupt(); +void EnableInterrupt(s32 level); + #endif /* BSP_ARCH_ARMV8_AARCH32_CP15 */ \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/fsleep.h b/bsp/arch/armv8/aarch32/fsleep.h index 5edc9ce94..e0665eb14 100644 --- a/bsp/arch/armv8/aarch32/fsleep.h +++ b/bsp/arch/armv8/aarch32/fsleep.h @@ -1,22 +1,22 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-28 08:48:40 - * @LastEditTime: 2021-05-28 09:28:55 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _BSP_ARCH_ARMV8_FSLEEP_H -#define _BSP_ARCH_ARMV8_FSLEEP_H - -#include "ft_types.h" - -u32 fsleep_seconds(u32 seconds); - +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-28 08:48:40 + * @LastEditTime: 2021-05-28 09:28:55 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _BSP_ARCH_ARMV8_FSLEEP_H +#define _BSP_ARCH_ARMV8_FSLEEP_H + +#include "ft_types.h" + +u32 fsleep_seconds(u32 seconds); + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/gcc/context.S b/bsp/arch/armv8/aarch32/gcc/context.S index e94e7fb20..62c1529a2 100644 --- a/bsp/arch/armv8/aarch32/gcc/context.S +++ b/bsp/arch/armv8/aarch32/gcc/context.S @@ -1,12 +1,12 @@ -.section .text, "ax" - -.globl DisableInterrupt -DisableInterrupt: - mrs r0, cpsr - cpsid i - bx lr - -.globl EnableInterrupt -EnableInterrupt: - msr cpsr, r0 +.section .text, "ax" + +.globl DisableInterrupt +DisableInterrupt: + mrs r0, cpsr + cpsid i + bx lr + +.globl EnableInterrupt +EnableInterrupt: + msr cpsr, r0 bx lr \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/gcc/cp15.S b/bsp/arch/armv8/aarch32/gcc/cp15.S index 97b55e9e8..12316908f 100644 --- a/bsp/arch/armv8/aarch32/gcc/cp15.S +++ b/bsp/arch/armv8/aarch32/gcc/cp15.S @@ -1,142 +1,142 @@ -.globl cpu_get_smp_id -cpu_get_smp_id: - mrc p15, #0, r0, c0, c0, #5 - bx lr - -.globl cpu_mmu_disable -cpu_mmu_disable: - mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #1 - mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit - dsb - bx lr - -.globl cpu_mmu_enable -cpu_mmu_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x001 @ bit 1, mmu enable - mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit - dsb - bx lr - -.globl cpu_tlb_set -cpu_tlb_set: - orr r1, r0, #0x6a - mcr p15, #0, r0, c2, c0, #0 - dmb - bx lr - -_FLD_MAX_WAY: - .word 0x3ff -_FLD_MAX_IDX: - .word 0x7fff - -.globl cpu_dcache_clean_flush -cpu_dcache_clean_flush: - push {r4-r11} - dmb - mrc p15, #1, r0, c0, c0, #1 @ read clid register - ands r3, r0, #0x7000000 @ get level of coherency - mov r3, r3, lsr #23 - beq finished - mov r10, #0 -loop1: - add r2, r10, r10, lsr #1 - mov r1, r0, lsr r2 - and r1, r1, #7 - cmp r1, #2 - blt skip - mcr p15, #2, r10, c0, c0, #0 - isb - mrc p15, #1, r1, c0, c0, #0 - and r2, r1, #7 - add r2, r2, #4 - ldr r4, _FLD_MAX_WAY - ands r4, r4, r1, lsr #3 - clz r5, r4 - ldr r7, _FLD_MAX_IDX - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 -loop3: - orr r11, r10, r9, lsl r5 - orr r11, r11, r7, lsl r2 - mcr p15, #0, r11, c7, c14, #2 - subs r9, r9, #1 - bge loop3 - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - cmp r3, r10 - bgt loop1 - -finished: - dsb - isb - pop {r4-r11} - bx lr - -.globl cpu_icache_flush -cpu_icache_flush: - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate - dsb - isb - bx lr - -.globl cpu_vector_set_base -cpu_vector_set_base: - /* clear SCTRL.V to customize the vector address */ - mrc p15, #0, r1, c1, c0, #0 - bic r1, #(1 << 13) - mcr p15, #0, r1, c1, c0, #0 - /* set up the vector address */ - mcr p15, #0, r0, c12, c0, #0 - dsb - bx lr - -.globl cpu_dcache_disable -cpu_dcache_disable: - push {r4-r11, lr} - bl cpu_dcache_clean_flush - mrc p15, #0, r0, c1, c0, #0 // Read SCTLR. - bic r0, r0, #(0x1 << 2) // Disable D Cache. - mcr p15, #0, r0, c1, c0, #0 // Write SCTLR. - pop {r4-r11, lr} - bx lr - -.globl cpu_icache_disable -cpu_icache_disable: - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl cpu_icache_enable -cpu_icache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl cpu_dcache_enable -cpu_dcache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl cp15_get_cpu_id -cp15_get_cpu_id: - mrc p15, #0, r0, c0, c0, #5 @ read multiprocessor affinity register - ldr r1, =0xFFFF03 @ Affinity mask off, leaving CPU ID field, [0:1]CPU ID, [8:15]Cluster ID Aff1, [16:23]Cluster ID Aff2 - and r0, r0, r1 - bx lr - -.globl cp15_set_vector_base -cp15_set_vector_base: - mcr p15, #0, r0, c12, c0, #0 - dsb +.globl cpu_get_smp_id +cpu_get_smp_id: + mrc p15, #0, r0, c0, c0, #5 + bx lr + +.globl cpu_mmu_disable +cpu_mmu_disable: + mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit + dsb + bx lr + +.globl cpu_mmu_enable +cpu_mmu_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x001 @ bit 1, mmu enable + mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit + dsb + bx lr + +.globl cpu_tlb_set +cpu_tlb_set: + orr r1, r0, #0x6a + mcr p15, #0, r0, c2, c0, #0 + dmb + bx lr + +_FLD_MAX_WAY: + .word 0x3ff +_FLD_MAX_IDX: + .word 0x7fff + +.globl cpu_dcache_clean_flush +cpu_dcache_clean_flush: + push {r4-r11} + dmb + mrc p15, #1, r0, c0, c0, #1 @ read clid register + ands r3, r0, #0x7000000 @ get level of coherency + mov r3, r3, lsr #23 + beq finished + mov r10, #0 +loop1: + add r2, r10, r10, lsr #1 + mov r1, r0, lsr r2 + and r1, r1, #7 + cmp r1, #2 + blt skip + mcr p15, #2, r10, c0, c0, #0 + isb + mrc p15, #1, r1, c0, c0, #0 + and r2, r1, #7 + add r2, r2, #4 + ldr r4, _FLD_MAX_WAY + ands r4, r4, r1, lsr #3 + clz r5, r4 + ldr r7, _FLD_MAX_IDX + ands r7, r7, r1, lsr #13 +loop2: + mov r9, r4 +loop3: + orr r11, r10, r9, lsl r5 + orr r11, r11, r7, lsl r2 + mcr p15, #0, r11, c7, c14, #2 + subs r9, r9, #1 + bge loop3 + subs r7, r7, #1 + bge loop2 +skip: + add r10, r10, #2 + cmp r3, r10 + bgt loop1 + +finished: + dsb + isb + pop {r4-r11} + bx lr + +.globl cpu_icache_flush +cpu_icache_flush: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + dsb + isb + bx lr + +.globl cpu_vector_set_base +cpu_vector_set_base: + /* clear SCTRL.V to customize the vector address */ + mrc p15, #0, r1, c1, c0, #0 + bic r1, #(1 << 13) + mcr p15, #0, r1, c1, c0, #0 + /* set up the vector address */ + mcr p15, #0, r0, c12, c0, #0 + dsb + bx lr + +.globl cpu_dcache_disable +cpu_dcache_disable: + push {r4-r11, lr} + bl cpu_dcache_clean_flush + mrc p15, #0, r0, c1, c0, #0 // Read SCTLR. + bic r0, r0, #(0x1 << 2) // Disable D Cache. + mcr p15, #0, r0, c1, c0, #0 // Write SCTLR. + pop {r4-r11, lr} + bx lr + +.globl cpu_icache_disable +cpu_icache_disable: + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl cpu_icache_enable +cpu_icache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl cpu_dcache_enable +cpu_dcache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl cp15_get_cpu_id +cp15_get_cpu_id: + mrc p15, #0, r0, c0, c0, #5 @ read multiprocessor affinity register + ldr r1, =0xFFFF03 @ Affinity mask off, leaving CPU ID field, [0:1]CPU ID, [8:15]Cluster ID Aff1, [16:23]Cluster ID Aff2 + and r0, r0, r1 + bx lr + +.globl cp15_set_vector_base +cp15_set_vector_base: + mcr p15, #0, r0, c12, c0, #0 + dsb bx lr \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/gcc/crt0.S b/bsp/arch/armv8/aarch32/gcc/crt0.S index 58f63ea95..dbde23346 100644 --- a/bsp/arch/armv8/aarch32/gcc/crt0.S +++ b/bsp/arch/armv8/aarch32/gcc/crt0.S @@ -1,7 +1,7 @@ -.file "crt0.S" -.align 2 -.text -.globl c_startup -c_startup: - bl main /* continue running in case the main function */ - b Abort_Exception /* indicate an error, never execute when main contains infinite loop */ +.file "crt0.S" +.align 2 +.text +.globl c_startup +c_startup: + bl main /* continue running in case the main function */ + b Abort_Exception /* indicate an error, never execute when main contains infinite loop */ diff --git a/bsp/arch/armv8/aarch32/gcc/smccc-call.S b/bsp/arch/armv8/aarch32/gcc/smccc-call.S index c610350eb..3134cc272 100644 --- a/bsp/arch/armv8/aarch32/gcc/smccc-call.S +++ b/bsp/arch/armv8/aarch32/gcc/smccc-call.S @@ -1,36 +1,36 @@ - - -/******************************************************************************* -* -* FSmc_Call - initiate SMC call -* -* This routine initiates SMC call which traps the processor into Monitor Mode. -* The ARM SMC Call Convetion defines that up to eight registers can be exchanged -* during an SMC call. The input parameter contains eight INT32 valeus which are -* to be passed in the SMC call; similarily the output parameter also contains -* eight INT32 values which are returned from the SMC call. -* -* \NOMANUAL -* -* RETURNS: OK -* -* void FSmc_Call -* ( -* FSmc_Data_t * input, /@ r0 - input register values @/ -* FSmc_Data_t * output /@ r1 - output register values @/ -* ) -*/ - -.arm -.align 4 -.globl FSmc_Call -FSmc_Call: - STMDB sp!, {r0-r7} /* save clobbered registers to stack */ - ldr r12, [sp, #(4 * 0)] /* get 1st argument (ptr to input struct) */ - ldmia r12, {r0-r7} /* save input argument to r0-r7 */ - smc #0 - ldr r12, [sp, #(4 * 1)] /* get 2th argument (ptr to output result) */ - stmia r12, {r0-r7} /* get output argument from r0-r7 */ - ldmfd sp!, {r0-r7} /* restore clobbered registers from stack */ - bx lr -.size FSmc_Call, .- FSmc_Call + + +/******************************************************************************* +* +* FSmc_Call - initiate SMC call +* +* This routine initiates SMC call which traps the processor into Monitor Mode. +* The ARM SMC Call Convetion defines that up to eight registers can be exchanged +* during an SMC call. The input parameter contains eight INT32 valeus which are +* to be passed in the SMC call; similarily the output parameter also contains +* eight INT32 values which are returned from the SMC call. +* +* \NOMANUAL +* +* RETURNS: OK +* +* void FSmc_Call +* ( +* FSmc_Data_t * input, /@ r0 - input register values @/ +* FSmc_Data_t * output /@ r1 - output register values @/ +* ) +*/ + +.arm +.align 4 +.globl FSmc_Call +FSmc_Call: + STMDB sp!, {r0-r7} /* save clobbered registers to stack */ + ldr r12, [sp, #(4 * 0)] /* get 1st argument (ptr to input struct) */ + ldmia r12, {r0-r7} /* save input argument to r0-r7 */ + smc #0 + ldr r12, [sp, #(4 * 1)] /* get 2th argument (ptr to output result) */ + stmia r12, {r0-r7} /* get output argument from r0-r7 */ + ldmfd sp!, {r0-r7} /* restore clobbered registers from stack */ + bx lr +.size FSmc_Call, .- FSmc_Call diff --git a/bsp/arch/armv8/aarch32/gcc/start.S b/bsp/arch/armv8/aarch32/gcc/start.S index 5b9f918b9..3d31df8c2 100644 --- a/bsp/arch/armv8/aarch32/gcc/start.S +++ b/bsp/arch/armv8/aarch32/gcc/start.S @@ -1,341 +1,341 @@ -#include "sdkconfig.h" - -.equ MODE_USR, 0x10 -.equ MODE_FIQ, 0x11 -.equ MODE_IRQ, 0x12 -.equ MODE_SVC, 0x13 -.equ MODE_ABT, 0x17 -.equ MODE_UND, 0x1B -.equ MODE_SYS, 0x1f - -.section .text /* The code segment, RD, program’s executable code */ -/******************************************************************************* -* -* sysInit - start after boot -* -* This routine is the system start-up entry point for VxWorks in RAM, the -* first code executed after booting. It disables interrupts, sets up -* the stack, and jumps to the C routine usrInit() in usrConfig.c. -* -* The initial stack is set to grow down from the address of sysInit(). This -* stack is used only by usrInit() and is never used again. Memory for the -* stack must be accounted for when determining the system load address. -* -* NOTE: This routine should not be called by the user. -* -* RETURNS: N/A -* -* void sysInit (UINT32 startType) /@ THIS IS NOT A CALLABLE ROUTINE @/ -* -*/ -#include "sdkconfig.h" - -/* Qemu no need to switch from aarch64 to aarch32 */ -.section .Startup_Aarch32, "a" -.global Startup_Aarch32 -Startup_Aarch32: -#ifndef CONFIG_TARGET_AARCH32_QEMU - .long 0xd5384240 /* mrs x0, currentel */ - .long 0xd342fc00 /* lsr x0, x0, #2 */ - .long 0x92400400 /* and x0, x0, #0x3 */ - .long 0xf1000c1f /* cmp x0, #0x3 */ - .long 0x540003a1 /* b.ne 1d0080c4 */ - -el3_mode: - .long 0xd53ecca0 /* mrs x0, s3_6_c12_c12_5 - ICC_SRE_EL3 */ - .long 0xb2400c00 /* orr x0, x0, #0xf */ - .long 0xd51ecca0 /* msr s3_6_c12_c12_5, x0 */ - .long 0xd5033fdf /* isb */ - .long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */ - .long 0xb2400c00 /* orr x0, x0, #0xf */ - .long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */ - .long 0xd5033fdf /* isb */ - .long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */ - .long 0xb2400000 /* orr x0, x0, #0x1 */ - .long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */ - .long 0xd5033fdf /* isb */ - - .long 0xd2803620 /* mov x0, #0x1b1 */ - .long 0xd51e1100 /* msr scr_el3, x0 */ - .long 0xd2867fe0 /* mov x0, #0x33ff */ - .long 0xd51c1140 /* msr cptr_el2, x0 */ - .long 0xd2810000 /* mov x0, #0x800 */ - .long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */ - .long 0xd5181000 /* msr sctlr_el1, x0 */ - .long 0x910003e0 /* mov x0, sp */ - .long 0xd51c4100 /* msr sp_el1, x0 */ - .long 0xd53ec000 /* mrs x0, vbar_el3 */ - .long 0xd518c000 /* msr vbar_el1, x0 */ - .long 0xd2803a60 /* mov x0, #0x1d3 */ - .long 0xd51e4000 /* msr spsr_el3, x0 */ - .long 0x10000500 /* adr x0, 1d008158 */ - .long 0xd51e4020 /* msr elr_el3, x0 */ - .long 0xd69f03e0 /* eret */ - -el2_mode: - .long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */ - .long 0xb2400c00 /* orr x0, x0, #0xf */ - .long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */ - .long 0xd5033fdf /* isb */ - .long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */ - .long 0xb2400000 /* orr x0, x0, #0x1 */ - .long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */ - .long 0xd5033fdf /* isb */ - .long 0xd53ce100 /* mrs x0, cnthctl_el2 */ - .long 0xb2400400 /* orr x0, x0, #0x3 */ - .long 0xd51ce100 /* msr cnthctl_el2, x0 */ - .long 0xd51ce07f /* msr cntvoff_el2, xzr */ - .long 0xd5380000 /* mrs x0, midr_el1 */ - .long 0xd53800a1 /* mrs x1, mpidr_el1 */ - .long 0xd51c0000 /* msr vpidr_el2, x0 */ - .long 0xd51c00a1 /* msr vmpidr_el2, x1 */ - .long 0xd2867fe0 /* mov x0, #0x33ff */ - .long 0xd51c1140 /* msr cptr_el2, x0 */ - .long 0xd51c117f /* msr hstr_el2, xzr */ - .long 0xd2a00600 /* mov x0, #0x300000 */ - .long 0xd5181040 /* msr cpacr_el1, x0 */ - .long 0xd2800000 /* mov x0, #0x0 */ - .long 0xb2630000 /* orr x0, x0, #0x20000000 */ - .long 0xd51c1100 /* msr hcr_el2, x0 */ - .long 0xd53c1100 /* mrs x0, hcr_el2 */ - .long 0xd2810000 /* mov x0, #0x800 */ - .long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */ - .long 0xd5181000 /* msr sctlr_el1, x0 */ - .long 0x910003e0 /* mov x0, sp */ - .long 0xd51c4100 /* msr sp_el1, x0 */ - .long 0xd53cc000 /* mrs x0, vbar_el2 */ - .long 0xd518c000 /* msr vbar_el1, x0 */ - .long 0xd2803a60 /* mov x0, #0x1d3 */ - .long 0xd51c4000 /* msr spsr_el2, x0 */ - .long 0x10000060 /* adr x0, 1d008158 */ - .long 0xd51c4020 /* msr elr_el2, x0 */ - .long 0xd69f03e0 /* eret */ -el1_mode: -#endif - -.global RST_Handler -RST_Handler: - cpsid i /* Mask interrupts */ - - @mrc p15, 0, r0, c1, c0, 0 - ldr r0, =#0x0 - mcr p15, 0, r0, c1, c0, 0 /* reset control register */ - isb - - /* set VBAR to the system_vectors address in linker script */ - ldr r0, =system_vectors - mcr p15, 0, r0, c12, c0, 0 - -/* from ARMv8 */ -/* Check for HYP mode */ - mrs r0, cpsr_all - and r0, r0, #0x1F - mov r8, #0x1A - cmp r0, r8 - beq overHyped - b continue - -/* Get out of HYP mode */ -overHyped: - adr r1, continue - msr ELR_hyp, r1 - mrs r1, cpsr_all - and r1, r1, #0x1f ;@ CPSR_MODE_MASK - orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR - msr SPSR_hyp, r1 - eret - -continue: - cps MODE_SVC - -invalidate_caches_tlb: - mov r0,#0 /* r0 = 0 */ - mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ - mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ - mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */ - bl invalidate_dcache /* invalidate dcache */ - -disable_cache_mmu: - @ Disable MMU - mrc p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data - bic r1, r1, #0x1 - mcr p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data - @ Disable L1 Caches - mrc p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data - bic r1, r1, #(0x1 << 12) @ Disable I Cache - bic r1, r1, #(0x1 << 2) @ Disable D Cache - mcr p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data - - /* disable the data alignment check */ - mrc p15, 0, r1, c1, c0, 0 - bic r1, #(1<<1) - mcr p15, 0, r1, c1, c0, 0 - - /* FIQ stack */ - /* Current Program Status Register, - change cpsr without affacting the - condition flags */ - msr cpsr_c, MODE_FIQ /* switch the processor to FIQ mode */ - ldr r1, =_fiq_stack_start /* load start address into R1 */ - ldr sp, =_fiq_stack_end /* load the end address of the FIQ stack into SP */ - movw r0, #0xFEFE - movt r0, #0xFEFE /* corresponds to loading x << 16 | y into r0 */ - -/* This is the loop that actually fills the stack with 0xFEFEFEFE */ -fiq_loop: - cmp r1, sp /* compares the value in R1 to the value in SP */ - strlt r0, [r1], #4 /* If R1 is less than SP, - the value in R0 will be written to the - address stored in R1, - and R1 gets increased by 4 */ - blt fiq_loop /* the loop continues as long as R1 is less than SP */ - - /* IRQ stack */ - msr cpsr_c, MODE_IRQ - ldr r1, =_irq_stack_start - ldr sp, =_irq_stack_end - -/* fill irq stack */ -irq_loop: - cmp r1, sp - strlt r0, [r1], #4 - blt irq_loop - - /* System mode */ - msr cpsr_c, MODE_SYS - ldr r1, =_sys_stack_start - ldr sp, =_sys_stack_end - -sys_loop: - cmp r1, sp - strlt r0, [r1], #4 - blt sys_loop - -/* PUT SVC IN THE END, START UP WITH SVC MODE!!! */ - /* Supervisor mode */ - msr cpsr_c, MODE_SVC - ldr r1, =_svc_stack_start - ldr sp, =_svc_stack_end - -/* fill the supervisor mode stack */ -svc_loop: - cmp r1, sp - strlt r0, [r1], #4 - blt svc_loop - - /* Start copying data */ - ldr r0, =_text_end /* section address has been defined in ld script */ - ldr r1, =_data_start - ldr r2, =_data_end - -/* loop continues over the entirety of .data in ROM */ -data_loop: - cmp r1, r2 - ldrlt r3, [r0], #4 /* t load 4 bytes of data from ROM into R3 */ - strlt r3, [r1], #4 - blt data_loop - -/* Initialize .bss */ -clear_bss: - mov r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end - -/* loop over memory between the addresses _bss_start and _bss_end */ -/* there is no ROM address, and zeros just take up space */ -bss_loop: - cmp r1, r2 - strlt r0, [r1], #4 - blt bss_loop - -@ using fpu -mov r4, #0xfffffff -mcr p15, 0, r4, c1, c0, 2 - -#ifdef CONFIG_USE_CACHE -enable_branch_pred: - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #(1<<11) - mcr p15, 0, r0, c1, c0, 0 - -init_cache_mmu: - ldr r0, =platform_mem_desc - ldr r1, =platform_mem_desc_size - ldr r1, [r1] - bl InitMMUTable - bl InitCache -#endif - -extra_init: - @ Enable access to FP registers. - mov r1, #(0xF << 20) - mcr p15, 0, r1, c1, c0, 2 // CPACR full access to cp11 and cp10. - @ Enable Floating point and Neon unit. - mov r1, #(0x1 << 30) - vmsr FPEXC, r1 - ISB @Ensure the enable operation takes effect. - -start_up: - cpsie i /* enable irq */ - b c_startup /* jump to C startup code */ - b Abort_Exception - -/* - ************************************************************************* - * - * invalidate_dcache - invalidate the entire d-cache by set/way - * - * Note: for Cortex-A53, there is no cp instruction for invalidating - * the whole D-cache. Need to invalidate each line. - * - ************************************************************************* - */ -invalidate_dcache: - mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */ - ands r3, r0, #0x7000000 - mov r3, r3, lsr #23 /* cache level value (naturally aligned) */ - beq finished - mov r10, #0 /* start with level 0 */ -loop1: - add r2, r10, r10, lsr #1 /* work out 3xcachelevel */ - mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */ - and r1, r1, #7 /* get those 3 bits alone */ - cmp r1, #2 - blt skip /* no cache or only instruction cache at this level */ - mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */ - isb /* isb to sync the change to the CacheSizeID reg */ - mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */ - and r2, r1, #7 /* extract the line length field */ - add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */ - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */ - clz r5, r4 /* r5 is the bit position of the way size increment */ - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */ -loop2: - mov r9, r4 /* r9 working copy of the max way size (right aligned) */ -loop3: - orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */ - orr r11, r11, r7, lsl r2 /* factor in the index number */ - mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */ - subs r9, r9, #1 /* decrement the way number */ - bge loop3 - subs r7, r7, #1 /* decrement the index */ - bge loop2 -skip: - add r10, r10, #2 /* increment the cache number */ - cmp r3, r10 - bgt loop1 - -finished: - mov r10, #0 /* switch back to cache level 0 */ - mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */ - dsb - isb - - bx lr - -.end -/** -* @} End of "addtogroup a53_32_boot_code". +#include "sdkconfig.h" + +.equ MODE_USR, 0x10 +.equ MODE_FIQ, 0x11 +.equ MODE_IRQ, 0x12 +.equ MODE_SVC, 0x13 +.equ MODE_ABT, 0x17 +.equ MODE_UND, 0x1B +.equ MODE_SYS, 0x1f + +.section .text /* The code segment, RD, program’s executable code */ +/******************************************************************************* +* +* sysInit - start after boot +* +* This routine is the system start-up entry point for VxWorks in RAM, the +* first code executed after booting. It disables interrupts, sets up +* the stack, and jumps to the C routine usrInit() in usrConfig.c. +* +* The initial stack is set to grow down from the address of sysInit(). This +* stack is used only by usrInit() and is never used again. Memory for the +* stack must be accounted for when determining the system load address. +* +* NOTE: This routine should not be called by the user. +* +* RETURNS: N/A +* +* void sysInit (UINT32 startType) /@ THIS IS NOT A CALLABLE ROUTINE @/ +* +*/ +#include "sdkconfig.h" + +/* Qemu no need to switch from aarch64 to aarch32 */ +.section .Startup_Aarch32, "a" +.global Startup_Aarch32 +Startup_Aarch32: +#ifndef CONFIG_TARGET_AARCH32_QEMU + .long 0xd5384240 /* mrs x0, currentel */ + .long 0xd342fc00 /* lsr x0, x0, #2 */ + .long 0x92400400 /* and x0, x0, #0x3 */ + .long 0xf1000c1f /* cmp x0, #0x3 */ + .long 0x540003a1 /* b.ne 1d0080c4 */ + +el3_mode: + .long 0xd53ecca0 /* mrs x0, s3_6_c12_c12_5 - ICC_SRE_EL3 */ + .long 0xb2400c00 /* orr x0, x0, #0xf */ + .long 0xd51ecca0 /* msr s3_6_c12_c12_5, x0 */ + .long 0xd5033fdf /* isb */ + .long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */ + .long 0xb2400c00 /* orr x0, x0, #0xf */ + .long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */ + .long 0xd5033fdf /* isb */ + .long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */ + .long 0xb2400000 /* orr x0, x0, #0x1 */ + .long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */ + .long 0xd5033fdf /* isb */ + + .long 0xd2803620 /* mov x0, #0x1b1 */ + .long 0xd51e1100 /* msr scr_el3, x0 */ + .long 0xd2867fe0 /* mov x0, #0x33ff */ + .long 0xd51c1140 /* msr cptr_el2, x0 */ + .long 0xd2810000 /* mov x0, #0x800 */ + .long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */ + .long 0xd5181000 /* msr sctlr_el1, x0 */ + .long 0x910003e0 /* mov x0, sp */ + .long 0xd51c4100 /* msr sp_el1, x0 */ + .long 0xd53ec000 /* mrs x0, vbar_el3 */ + .long 0xd518c000 /* msr vbar_el1, x0 */ + .long 0xd2803a60 /* mov x0, #0x1d3 */ + .long 0xd51e4000 /* msr spsr_el3, x0 */ + .long 0x10000500 /* adr x0, 1d008158 */ + .long 0xd51e4020 /* msr elr_el3, x0 */ + .long 0xd69f03e0 /* eret */ + +el2_mode: + .long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */ + .long 0xb2400c00 /* orr x0, x0, #0xf */ + .long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */ + .long 0xd5033fdf /* isb */ + .long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */ + .long 0xb2400000 /* orr x0, x0, #0x1 */ + .long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */ + .long 0xd5033fdf /* isb */ + .long 0xd53ce100 /* mrs x0, cnthctl_el2 */ + .long 0xb2400400 /* orr x0, x0, #0x3 */ + .long 0xd51ce100 /* msr cnthctl_el2, x0 */ + .long 0xd51ce07f /* msr cntvoff_el2, xzr */ + .long 0xd5380000 /* mrs x0, midr_el1 */ + .long 0xd53800a1 /* mrs x1, mpidr_el1 */ + .long 0xd51c0000 /* msr vpidr_el2, x0 */ + .long 0xd51c00a1 /* msr vmpidr_el2, x1 */ + .long 0xd2867fe0 /* mov x0, #0x33ff */ + .long 0xd51c1140 /* msr cptr_el2, x0 */ + .long 0xd51c117f /* msr hstr_el2, xzr */ + .long 0xd2a00600 /* mov x0, #0x300000 */ + .long 0xd5181040 /* msr cpacr_el1, x0 */ + .long 0xd2800000 /* mov x0, #0x0 */ + .long 0xb2630000 /* orr x0, x0, #0x20000000 */ + .long 0xd51c1100 /* msr hcr_el2, x0 */ + .long 0xd53c1100 /* mrs x0, hcr_el2 */ + .long 0xd2810000 /* mov x0, #0x800 */ + .long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */ + .long 0xd5181000 /* msr sctlr_el1, x0 */ + .long 0x910003e0 /* mov x0, sp */ + .long 0xd51c4100 /* msr sp_el1, x0 */ + .long 0xd53cc000 /* mrs x0, vbar_el2 */ + .long 0xd518c000 /* msr vbar_el1, x0 */ + .long 0xd2803a60 /* mov x0, #0x1d3 */ + .long 0xd51c4000 /* msr spsr_el2, x0 */ + .long 0x10000060 /* adr x0, 1d008158 */ + .long 0xd51c4020 /* msr elr_el2, x0 */ + .long 0xd69f03e0 /* eret */ +el1_mode: +#endif + +.global RST_Handler +RST_Handler: + cpsid i /* Mask interrupts */ + + @mrc p15, 0, r0, c1, c0, 0 + ldr r0, =#0x0 + mcr p15, 0, r0, c1, c0, 0 /* reset control register */ + isb + + /* set VBAR to the system_vectors address in linker script */ + ldr r0, =system_vectors + mcr p15, 0, r0, c12, c0, 0 + +/* from ARMv8 */ +/* Check for HYP mode */ + mrs r0, cpsr_all + and r0, r0, #0x1F + mov r8, #0x1A + cmp r0, r8 + beq overHyped + b continue + +/* Get out of HYP mode */ +overHyped: + adr r1, continue + msr ELR_hyp, r1 + mrs r1, cpsr_all + and r1, r1, #0x1f ;@ CPSR_MODE_MASK + orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR + msr SPSR_hyp, r1 + eret + +continue: + cps MODE_SVC + +invalidate_caches_tlb: + mov r0,#0 /* r0 = 0 */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */ + bl invalidate_dcache /* invalidate dcache */ + +disable_cache_mmu: + @ Disable MMU + mrc p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data + bic r1, r1, #0x1 + mcr p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data + @ Disable L1 Caches + mrc p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data + bic r1, r1, #(0x1 << 12) @ Disable I Cache + bic r1, r1, #(0x1 << 2) @ Disable D Cache + mcr p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data + + /* disable the data alignment check */ + mrc p15, 0, r1, c1, c0, 0 + bic r1, #(1<<1) + mcr p15, 0, r1, c1, c0, 0 + + /* FIQ stack */ + /* Current Program Status Register, + change cpsr without affacting the + condition flags */ + msr cpsr_c, MODE_FIQ /* switch the processor to FIQ mode */ + ldr r1, =_fiq_stack_start /* load start address into R1 */ + ldr sp, =_fiq_stack_end /* load the end address of the FIQ stack into SP */ + movw r0, #0xFEFE + movt r0, #0xFEFE /* corresponds to loading x << 16 | y into r0 */ + +/* This is the loop that actually fills the stack with 0xFEFEFEFE */ +fiq_loop: + cmp r1, sp /* compares the value in R1 to the value in SP */ + strlt r0, [r1], #4 /* If R1 is less than SP, + the value in R0 will be written to the + address stored in R1, + and R1 gets increased by 4 */ + blt fiq_loop /* the loop continues as long as R1 is less than SP */ + + /* IRQ stack */ + msr cpsr_c, MODE_IRQ + ldr r1, =_irq_stack_start + ldr sp, =_irq_stack_end + +/* fill irq stack */ +irq_loop: + cmp r1, sp + strlt r0, [r1], #4 + blt irq_loop + + /* System mode */ + msr cpsr_c, MODE_SYS + ldr r1, =_sys_stack_start + ldr sp, =_sys_stack_end + +sys_loop: + cmp r1, sp + strlt r0, [r1], #4 + blt sys_loop + +/* PUT SVC IN THE END, START UP WITH SVC MODE!!! */ + /* Supervisor mode */ + msr cpsr_c, MODE_SVC + ldr r1, =_svc_stack_start + ldr sp, =_svc_stack_end + +/* fill the supervisor mode stack */ +svc_loop: + cmp r1, sp + strlt r0, [r1], #4 + blt svc_loop + + /* Start copying data */ + ldr r0, =_text_end /* section address has been defined in ld script */ + ldr r1, =_data_start + ldr r2, =_data_end + +/* loop continues over the entirety of .data in ROM */ +data_loop: + cmp r1, r2 + ldrlt r3, [r0], #4 /* t load 4 bytes of data from ROM into R3 */ + strlt r3, [r1], #4 + blt data_loop + +/* Initialize .bss */ +clear_bss: + mov r0, #0 + ldr r1, =_bss_start + ldr r2, =_bss_end + +/* loop over memory between the addresses _bss_start and _bss_end */ +/* there is no ROM address, and zeros just take up space */ +bss_loop: + cmp r1, r2 + strlt r0, [r1], #4 + blt bss_loop + +@ using fpu +mov r4, #0xfffffff +mcr p15, 0, r4, c1, c0, 2 + +#ifdef CONFIG_USE_CACHE +enable_branch_pred: + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #(1<<11) + mcr p15, 0, r0, c1, c0, 0 + +init_cache_mmu: + ldr r0, =platform_mem_desc + ldr r1, =platform_mem_desc_size + ldr r1, [r1] + bl InitMMUTable + bl InitCache +#endif + +extra_init: + @ Enable access to FP registers. + mov r1, #(0xF << 20) + mcr p15, 0, r1, c1, c0, 2 // CPACR full access to cp11 and cp10. + @ Enable Floating point and Neon unit. + mov r1, #(0x1 << 30) + vmsr FPEXC, r1 + ISB @Ensure the enable operation takes effect. + +start_up: + cpsie i /* enable irq */ + b c_startup /* jump to C startup code */ + b Abort_Exception + +/* + ************************************************************************* + * + * invalidate_dcache - invalidate the entire d-cache by set/way + * + * Note: for Cortex-A53, there is no cp instruction for invalidating + * the whole D-cache. Need to invalidate each line. + * + ************************************************************************* + */ +invalidate_dcache: + mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */ + ands r3, r0, #0x7000000 + mov r3, r3, lsr #23 /* cache level value (naturally aligned) */ + beq finished + mov r10, #0 /* start with level 0 */ +loop1: + add r2, r10, r10, lsr #1 /* work out 3xcachelevel */ + mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */ + and r1, r1, #7 /* get those 3 bits alone */ + cmp r1, #2 + blt skip /* no cache or only instruction cache at this level */ + mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */ + isb /* isb to sync the change to the CacheSizeID reg */ + mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */ + and r2, r1, #7 /* extract the line length field */ + add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */ + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */ + clz r5, r4 /* r5 is the bit position of the way size increment */ + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */ +loop2: + mov r9, r4 /* r9 working copy of the max way size (right aligned) */ +loop3: + orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */ + orr r11, r11, r7, lsl r2 /* factor in the index number */ + mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */ + subs r9, r9, #1 /* decrement the way number */ + bge loop3 + subs r7, r7, #1 /* decrement the index */ + bge loop2 +skip: + add r10, r10, #2 /* increment the cache number */ + cmp r3, r10 + bgt loop1 + +finished: + mov r10, #0 /* switch back to cache level 0 */ + mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */ + dsb + isb + + bx lr + +.end +/** +* @} End of "addtogroup a53_32_boot_code". */ \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/gcc/vector.S b/bsp/arch/armv8/aarch32/gcc/vector.S index 5425378f9..1309a643c 100644 --- a/bsp/arch/armv8/aarch32/gcc/vector.S +++ b/bsp/arch/armv8/aarch32/gcc/vector.S @@ -1,124 +1,124 @@ -#include "sdkconfig.h" -.equ MODE_SVC, 0x13 - -/* allocatable and executable */ -.section .vector_table, "ax" - -.balign 2048 -.global system_vectors -system_vectors: - b RST_Handler - b UDF_Handler /* 0x4 Undefined Instruction */ - b SWI_Handler /* 0x8 Software Interrupt */ - b PRF_Handler /* 0xC Prefetch Abort */ - b DAT_Handler /* 0x10 Data Abort */ - b . /* 0x14 Reserved */ - b IRQ_Handler /* 0x18 IRQ */ - b FIQ_Handler /* 0x1C FIQ */ - -.global Abort_Exception -Abort_Exception: - swi 0xFF - -.macro PushSVCRegisters - sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ - stmia sp, {r0 - r12} @/* Calling r0-r12 */ - mov r0, sp - mrs r6, spsr @/* Save CPSR */ - str lr, [r0, #15*4] @/* Push PC */ - str r6, [r0, #16*4] @/* Push CPSR */ - cps #MODE_SVC - str sp, [r0, #13*4] @/* Save calling SP */ - str lr, [r0, #14*4] @/* Save calling PC */ -.endm - -.align 4 -.arm -.weak IRQ_Handler -.type IRQ_Handler, %function -@.global IRQ_Handler -IRQ_Handler: /* 0x18 IRQ */ - push {lr} /* Save return address+4 */ - push {r0-r3, r12} /* Push caller save registers */ - - mrs r0, spsr /* Save SPRS to allow interrupt reentry */ - push {r0} - - /* Get GIC base address MRC P15, 4, r1, C15, C0, 0 */ - // current) - { - current = GenericTimerRead(); - } -} - -void Aarch32Udelay(u32 us) -{ - u64 current = GenericTimerRead(); - u64 condition = current + GENERIC_TIMER_CLK_FREQ_MHZ * us; - - while (condition > current) - { - current = GenericTimerRead(); - } +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-21 14:11:09 + * @LastEditTime: 2021-06-24 13:41:24 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "parameters.h" +#include "generic_timer.h" +#include "aarch32.h" +#include "sdkconfig.h" +#include "ft_debug.h" + +//#define ENABLE_A32GT_DEBUG +#define A32GT_DEBUG_TAG "A32GT" +#ifdef ENABLE_A32GT_DEBUG +#define A32GT_ERROR(format, ...) FT_DEBUG_PRINT_E(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) +#define A32GT_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) +#define A32GT_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) +#else +#define A32GT_ERROR(format, ...) +#define A32GT_DEBUG_I(format, ...) +#define A32GT_DEBUG_W(format, ...) +#endif + +#define AARCH32_CNTP_CTL_ENABLE_MASK (1ul << 0) +#define AARCH32_CNTP_CTL_INTERRUPT_MASK (1ul << 1) + +void GenericTimerStart(void) +{ + u32 ctrl = aarch32_cntp_ctl_get(); + + if (!(ctrl & AARCH32_CNTP_CTL_ENABLE_MASK)) + { + ctrl |= AARCH32_CNTP_CTL_ENABLE_MASK; + aarch32_cntp_ctl_set(ctrl); + } + + A32GT_DEBUG_I("ctrl: 0x%x", aarch32_cntp_ctl_get()); +} + +void GenericTimerStop(void) +{ + u32 ctrl = aarch32_cntp_ctl_get(); + if ((ctrl & AARCH32_CNTP_CTL_ENABLE_MASK)) + { + ctrl &= ~AARCH32_CNTP_CTL_ENABLE_MASK; + aarch32_cntp_ctl_set(ctrl); + } +} + +void GenericTimerInterruptEnable(void) +{ + u32 ctrl = aarch32_cntp_ctl_get(); + if (ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK) + { + ctrl &= ~AARCH32_CNTP_CTL_INTERRUPT_MASK; + aarch32_cntp_ctl_set(ctrl); + } + A32GT_DEBUG_I("i mask: 0x%x", aarch32_cntp_ctl_get()); +} + +void GenericTimerInterruptDisable(void) +{ + u64 ctrl = aarch32_cntp_ctl_get(); + if (!(ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK)) + { + ctrl |= AARCH32_CNTP_CTL_INTERRUPT_MASK; + aarch32_cntp_ctl_set(ctrl); + } +} + +u32 GenericTimerFrequecy(void) +{ + u32 rate = aarch32_cntfrq_get(); + return (rate != 0) ? rate : 1000000; +} + +u64 GenericTimerRead(void) +{ + return aarch32_cntpct_get(); +} + +void GenericTimerCompare(u32 interval) +{ + aarch32_cntp_tval_set(interval); +} + +void Aarch32Delay(u32 ms) +{ + u64 current = GenericTimerRead(); + u64 condition = current + GENERIC_TIMER_CLK_FREQ_KHZ * ms; + + while (condition > current) + { + current = GenericTimerRead(); + } +} + +void Aarch32Udelay(u32 us) +{ + u64 current = GenericTimerRead(); + u64 condition = current + GENERIC_TIMER_CLK_FREQ_MHZ * us; + + while (condition > current) + { + current = GenericTimerRead(); + } } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/generic_timer.h b/bsp/arch/armv8/aarch32/generic_timer.h index 3143089fe..2edad7c05 100644 --- a/bsp/arch/armv8/aarch32/generic_timer.h +++ b/bsp/arch/armv8/aarch32/generic_timer.h @@ -1,39 +1,39 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-21 14:10:59 - * @LastEditTime: 2021-06-24 13:26:56 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H -#define BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - void GenericTimerStart(void); - void GenericTimerStop(void); - void GenericTimerInterruptEnable(void); - void GenericTimerInterruptDisable(void); - u32 GenericTimerFrequecy(void); - u64 GenericTimerRead(void); - void GenericTimerCompare(u32 interval); - void Aarch32Delay(u32 ms); - void Aarch32Udelay(u32 us); - -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-21 14:10:59 + * @LastEditTime: 2021-06-24 13:26:56 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H +#define BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + void GenericTimerStart(void); + void GenericTimerStop(void); + void GenericTimerInterruptEnable(void); + void GenericTimerInterruptDisable(void); + u32 GenericTimerFrequecy(void); + u64 GenericTimerRead(void); + void GenericTimerCompare(u32 interval); + void Aarch32Delay(u32 ms); + void Aarch32Udelay(u32 us); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/E2000/early_uart.c b/bsp/arch/armv8/aarch32/platform/E2000/early_uart.c index 2e552d8ec..0e3e5f118 100644 --- a/bsp/arch/armv8/aarch32/platform/E2000/early_uart.c +++ b/bsp/arch/armv8/aarch32/platform/E2000/early_uart.c @@ -1,32 +1,32 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 13:19:37 - * @LastEditTime: 2021-07-01 17:21:03 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#include "early_uart.h" - -void OutByte(s8 byte) -{ - - while ((FtIn32(0x2800d018) & 0x20) == 0x20) - { - } - - FtOut32(0x2800d000, (u32)byte); -} - -char GetByte(void) -{ - while ((FtIn32(0x2800d018) & 0x10) == 0x10) - ; - - return (char)FtIn32(0x2800d000); -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 13:19:37 + * @LastEditTime: 2021-07-01 17:21:03 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#include "early_uart.h" + +void OutByte(s8 byte) +{ + + while ((FtIn32(0x2800d018) & 0x20) == 0x20) + { + } + + FtOut32(0x2800d000, (u32)byte); +} + +char GetByte(void) +{ + while ((FtIn32(0x2800d018) & 0x10) == 0x10) + ; + + return (char)FtIn32(0x2800d000); +} diff --git a/bsp/arch/armv8/aarch32/platform/E2000/early_uart.h b/bsp/arch/armv8/aarch32/platform/E2000/early_uart.h index 47ab7bb20..059c2a6f6 100644 --- a/bsp/arch/armv8/aarch32/platform/E2000/early_uart.h +++ b/bsp/arch/armv8/aarch32/platform/E2000/early_uart.h @@ -1,31 +1,31 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 13:19:37 - * @LastEditTime: 2021-06-25 16:26:47 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - -void OutByte(s8 byte); -char GetByte(void); -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 13:19:37 + * @LastEditTime: 2021-06-25 16:26:47 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + +void OutByte(s8 byte); +char GetByte(void); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/E2000/parameters.c b/bsp/arch/armv8/aarch32/platform/E2000/parameters.c index e84e31195..0187f8aab 100644 --- a/bsp/arch/armv8/aarch32/platform/E2000/parameters.c +++ b/bsp/arch/armv8/aarch32/platform/E2000/parameters.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0. * * @Date: 2021-06-29 15:13:47 - * @LastEditTime: 2021-07-01 17:34:02 + * @LastEditTime: 2021-07-13 16:16:30 * @Description:  This files is for * * @Modify History: @@ -15,24 +15,24 @@ #include "parameters.h" #include "mmu.h" -#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWT | DESC_SEC) +#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC) struct mem_desc platform_mem_desc[] = { - {0X00, - 0x40000000, - 0X00, + {0X00U, + 0X00U + 0x40000000U, + 0X00U, DEVICE_MEM}, - {0x40000000, - 0x10000000, - 0x40000000, + {0x40000000U, + 0x40000000U + 0x10000000U, + 0x40000000U, DEVICE_MEM}, - {0x50000000, - 0x30000000, - 0x50000000, + {0x50000000U, + 0x50000000U + 0x30000000U, + 0x50000000U, DEVICE_MEM}, - {0x80000000, - 0x80000000, - 0x80000000, + {0x80000000U, + 0xffffffffU, + 0x80000000U, DDR_MEM}, }; diff --git a/bsp/arch/armv8/aarch32/platform/E2000/parameters.h b/bsp/arch/armv8/aarch32/platform/E2000/parameters.h index 66103cf97..8948c85e5 100644 --- a/bsp/arch/armv8/aarch32/platform/E2000/parameters.h +++ b/bsp/arch/armv8/aarch32/platform/E2000/parameters.h @@ -1,94 +1,94 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#define CORE0_AFF 0x0 -#define CORE1_AFF 0x100 -#define CORE2_AFF 0x200 -#define CORE3_AFF 0x201 - -/* Device register address */ -#define FT_DEV_BASE_ADDR 0x28000000 -#define FT_DEV_END_ADDR 0x2FFFFFFF - -/* PCI */ -#define FT_PCI_CONFIG_BASEADDR 0x40000000 -#define FT_PCI_CONFIG_REG_LENGTH 0x10000000 - -#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 -#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 - -#define FT_PCI_MEM32_BASEADDR 0x58000000 -#define FT_PCI_MEM32_REG_LENGTH 0x27000000 - - // timer - -#define GENERIC_TIMER_CLK_FREQ 2000000 -#define GENERIC_TIMER_CLK_FREQ_KHZ 2000 -#define GENERIC_TIMER_CLK_FREQ_MHZ 48 -#define GENERIC_TIMER_NS_IRQ_NUM 30 -#define GENERIC_TIMER_NS_CLK_FREQ 2000000 -#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ - - // UART - -#define FT_UART_NUM 4 -#define FT_UART_REG_LENGTH 0x18000 - -#define FT_UART0_ID 0 -#define FT_UART0_IRQ_NUM (85 + 30) -#define FT_UART0_BASE_ADDR 0x2800c000 -#define FT_UART0_CLK_FREQ_HZ 100000000 - -#define FT_UART1_ID 1 -#define FT_UART1_IRQ_NUM (86 + 30) -#define FT_UART1_BASE_ADDR 0x2800d000 -#define FT_UART1_CLK_FREQ_HZ 100000000 - -#define FT_UART2_ID 2 -#define FT_UART2_IRQ_NUM (87 + 30) -#define FT_UART2_BASE_ADDR 0x2800e000 -#define FT_UART2_CLK_FREQ_HZ 100000000 - -#define FT_UART3_BASE_ADDR 0x2800f000 -#define FT_UART3_ID 3 -#define FT_UART3_IRQ_NUM (88 + 30) -#define FT_UART3_CLK_FREQ_HZ 100000000 - -#define FT_STDOUT_base_address FT_UART1_BASE_ADDR -#define FT_STDIN_base_address FT_UART1_BASE_ADDR - -/****** GIC v3 *****/ -#define FT_GICV3_INSTANCES_NUM 1U -#define GICV3_REG_LENGTH 0x00009000 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define GICV3_MAX_INTR_PRIO_VAL 240U -#define GICV3_INTR_PRIO_MASK 0x000000f0U - -#define ARM_GIC_NR_IRQS 160 -#define ARM_GIC_IRQ_START 0 - -#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ -#define SGI_INT_MAX 16 -#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ -#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ -#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ - -#define GICV3_BASEADDRESS 0x30800000U -#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) -#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) - -#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define CORE0_AFF 0x0 +#define CORE1_AFF 0x100 +#define CORE2_AFF 0x200 +#define CORE3_AFF 0x201 + +/* Device register address */ +#define FT_DEV_BASE_ADDR 0x28000000 +#define FT_DEV_END_ADDR 0x2FFFFFFF + +/* PCI */ +#define FT_PCI_CONFIG_BASEADDR 0x40000000 +#define FT_PCI_CONFIG_REG_LENGTH 0x10000000 + +#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 +#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 + +#define FT_PCI_MEM32_BASEADDR 0x58000000 +#define FT_PCI_MEM32_REG_LENGTH 0x27000000 + + // timer + +#define GENERIC_TIMER_CLK_FREQ 2000000 +#define GENERIC_TIMER_CLK_FREQ_KHZ 2000 +#define GENERIC_TIMER_CLK_FREQ_MHZ 48 +#define GENERIC_TIMER_NS_IRQ_NUM 30 +#define GENERIC_TIMER_NS_CLK_FREQ 2000000 +#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ + + // UART + +#define FT_UART_NUM 4 +#define FT_UART_REG_LENGTH 0x18000 + +#define FT_UART0_ID 0 +#define FT_UART0_IRQ_NUM (85 + 30) +#define FT_UART0_BASE_ADDR 0x2800c000 +#define FT_UART0_CLK_FREQ_HZ 100000000 + +#define FT_UART1_ID 1 +#define FT_UART1_IRQ_NUM (86 + 30) +#define FT_UART1_BASE_ADDR 0x2800d000 +#define FT_UART1_CLK_FREQ_HZ 100000000 + +#define FT_UART2_ID 2 +#define FT_UART2_IRQ_NUM (87 + 30) +#define FT_UART2_BASE_ADDR 0x2800e000 +#define FT_UART2_CLK_FREQ_HZ 100000000 + +#define FT_UART3_BASE_ADDR 0x2800f000 +#define FT_UART3_ID 3 +#define FT_UART3_IRQ_NUM (88 + 30) +#define FT_UART3_CLK_FREQ_HZ 100000000 + +#define FT_STDOUT_base_address FT_UART1_BASE_ADDR +#define FT_STDIN_base_address FT_UART1_BASE_ADDR + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000 + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_NR_IRQS 160 +#define ARM_GIC_IRQ_START 0 + +#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ +#define SGI_INT_MAX 16 +#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ + +#define GICV3_BASEADDRESS 0x30800000U +#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) +#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) + +#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.c b/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.c index e830f3ca8..5bfc57c79 100644 --- a/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.c +++ b/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.c @@ -1,32 +1,32 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 13:19:37 - * @LastEditTime: 2021-06-25 16:26:59 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#include "early_uart.h" - -void OutByte(s8 byte) -{ - - while ((FtIn32(0x28001018) & 0x20) == 0x20) - { - } - - FtOut32(0x28001000, (u32)byte); -} - -char GetByte(void) -{ - while ((FtIn32(0x28001018) & 0x10) == 0x10) - ; - - return (char)FtIn32(0x28001000); -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 13:19:37 + * @LastEditTime: 2021-06-25 16:26:59 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#include "early_uart.h" + +void OutByte(s8 byte) +{ + + while ((FtIn32(0x28001018) & 0x20) == 0x20) + { + } + + FtOut32(0x28001000, (u32)byte); +} + +char GetByte(void) +{ + while ((FtIn32(0x28001018) & 0x10) == 0x10) + ; + + return (char)FtIn32(0x28001000); +} diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.h b/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.h index 47ab7bb20..059c2a6f6 100644 --- a/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.h +++ b/bsp/arch/armv8/aarch32/platform/ft2004/early_uart.h @@ -1,31 +1,31 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 13:19:37 - * @LastEditTime: 2021-06-25 16:26:47 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - -void OutByte(s8 byte); -char GetByte(void); -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 13:19:37 + * @LastEditTime: 2021-06-25 16:26:47 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + +void OutByte(s8 byte); +char GetByte(void); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h b/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h index 3cfc80294..07a2852c8 100644 --- a/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h +++ b/bsp/arch/armv8/aarch32/platform/ft2004/parameters.h @@ -1,108 +1,108 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-15 15:15:14 - * @LastEditTime: 2021-06-29 15:16:15 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_ARCH_ARMV8_AARCH32_FT2004_PARAMETER_H -#define BSP_ARCH_ARMV8_AARCH32_FT2004_PARAMETER_H - -#include "ft_types.h" - -#define CORE0_AFF 0x0 -#define CORE1_AFF 0x1 -#define CORE2_AFF 0x100 -#define CORE3_AFF 0x101 - -/* Device register address */ -#define FT_DEV_BASE_ADDR 0x28000000 -#define FT_DEV_END_ADDR 0x2FFFFFFF - -/* PCI */ -#define FT_PCI_CONFIG_BASEADDR 0x40000000 -#define FT_PCI_CONFIG_REG_LENGTH 0x10000000 - -#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 -#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 - -#define FT_PCI_MEM32_BASEADDR 0x58000000 -#define FT_PCI_MEM32_REG_LENGTH 0x27000000 - - - -#define GENERIC_TIMER_CLK_FREQ 48000000 -#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ - -// Gic -#define ARM_GIC_NR_IRQS 160 -#define ARM_GIC_IRQ_START 0 - -/****** GIC v3 *****/ -#define FT_GICV3_INSTANCES_NUM 1U -#define GICV3_REG_LENGTH 0x00009000 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define GICV3_MAX_INTR_PRIO_VAL 240U -#define GICV3_INTR_PRIO_MASK 0x000000f0U - -#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ -#define SGI_INT_MAX 16 -#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ -#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ -#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ - -#define GICV3_BASEADDRESS 0x29900000U -#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) -#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) - -#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM - -// Timer -#define GENERIC_TIMER_CLK_FREQ 48000000 -#define GENERIC_TIMER_CLK_FREQ_KHZ 48000 -#define GENERIC_TIMER_CLK_FREQ_MHZ 48 -#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ - -#define GEN_TIMER_VIRTUAL_IRQN 27 /**< Virtual Timer Interrupt */ -#define GEN_TIMER_VIRTUAL_NOSECURE_IRQN 28 -#define GEN_TIMER_PHYSICAL_IRQn 29 -#define GEN_TIMER_PHYSICAL_NOSECURE_IRQN 30 /**< Secure Physical Timer Interrupt */ - -// UART -#define FT_UART_NUM 4 -#define FT_UART_REG_LENGTH 0x18000 - -#define FT_UART0_ID 0 -#define FT_UART0_IRQ_NUM 38 -#define FT_UART0_BASE_ADDR 0x28000000 -#define FT_UART0_CLK_FREQ_HZ 48000000 - -#define FT_UART1_ID 1 -#define FT_UART1_IRQ_NUM 39 -#define FT_UART1_BASE_ADDR 0x28001000 -#define FT_UART1_CLK_FREQ_HZ 48000000 - -#define FT_UART2_ID 2 -#define FT_UART2_IRQ_NUM 40 -#define FT_UART2_BASE_ADDR 0x28002000 -#define FT_UART2_CLK_FREQ_HZ 48000000 - -#define FT_UART3_ID 3 -#define FT_UART3_IRQ_NUM 41 -#define FT_UART3_BASE_ADDR 0x28003000 -#define FT_UART3_CLK_FREQ_HZ 48000000 - -#define FT_STDOUT_base_address FT_UART1_BASE_ADDR -#define FT_STDIN_base_address FT_UART1_BASE_ADDR - -#endif +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-15 15:15:14 + * @LastEditTime: 2021-06-29 15:16:15 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_FT2004_PARAMETER_H +#define BSP_ARCH_ARMV8_AARCH32_FT2004_PARAMETER_H + +#include "ft_types.h" + +#define CORE0_AFF 0x0 +#define CORE1_AFF 0x1 +#define CORE2_AFF 0x100 +#define CORE3_AFF 0x101 + +/* Device register address */ +#define FT_DEV_BASE_ADDR 0x28000000 +#define FT_DEV_END_ADDR 0x2FFFFFFF + +/* PCI */ +#define FT_PCI_CONFIG_BASEADDR 0x40000000 +#define FT_PCI_CONFIG_REG_LENGTH 0x10000000 + +#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 +#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 + +#define FT_PCI_MEM32_BASEADDR 0x58000000 +#define FT_PCI_MEM32_REG_LENGTH 0x27000000 + + + +#define GENERIC_TIMER_CLK_FREQ 48000000 +#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ + +// Gic +#define ARM_GIC_NR_IRQS 160 +#define ARM_GIC_IRQ_START 0 + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000 + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ +#define SGI_INT_MAX 16 +#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ + +#define GICV3_BASEADDRESS 0x29900000U +#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) +#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) + +#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM + +// Timer +#define GENERIC_TIMER_CLK_FREQ 48000000 +#define GENERIC_TIMER_CLK_FREQ_KHZ 48000 +#define GENERIC_TIMER_CLK_FREQ_MHZ 48 +#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ + +#define GEN_TIMER_VIRTUAL_IRQN 27 /**< Virtual Timer Interrupt */ +#define GEN_TIMER_VIRTUAL_NOSECURE_IRQN 28 +#define GEN_TIMER_PHYSICAL_IRQn 29 +#define GEN_TIMER_PHYSICAL_NOSECURE_IRQN 30 /**< Secure Physical Timer Interrupt */ + +// UART +#define FT_UART_NUM 4 +#define FT_UART_REG_LENGTH 0x18000 + +#define FT_UART0_ID 0 +#define FT_UART0_IRQ_NUM 38 +#define FT_UART0_BASE_ADDR 0x28000000 +#define FT_UART0_CLK_FREQ_HZ 48000000 + +#define FT_UART1_ID 1 +#define FT_UART1_IRQ_NUM 39 +#define FT_UART1_BASE_ADDR 0x28001000 +#define FT_UART1_CLK_FREQ_HZ 48000000 + +#define FT_UART2_ID 2 +#define FT_UART2_IRQ_NUM 40 +#define FT_UART2_BASE_ADDR 0x28002000 +#define FT_UART2_CLK_FREQ_HZ 48000000 + +#define FT_UART3_ID 3 +#define FT_UART3_IRQ_NUM 41 +#define FT_UART3_BASE_ADDR 0x28003000 +#define FT_UART3_CLK_FREQ_HZ 48000000 + +#define FT_STDOUT_base_address FT_UART1_BASE_ADDR +#define FT_STDIN_base_address FT_UART1_BASE_ADDR + +#endif diff --git a/bsp/arch/armv8/aarch32/platform/qemu/early_uart.c b/bsp/arch/armv8/aarch32/platform/qemu/early_uart.c index a5308b35c..e28883206 100644 --- a/bsp/arch/armv8/aarch32/platform/qemu/early_uart.c +++ b/bsp/arch/armv8/aarch32/platform/qemu/early_uart.c @@ -1,34 +1,34 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 16:07:31 - * @LastEditTime: 2021-06-29 11:48:58 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#include "early_uart.h" - -volatile unsigned int *const UART0DR = (unsigned int *)0x10009000u; -volatile unsigned int *const UART0FR = (unsigned int *)0x10009018u; - -void OutByte(s8 byte) -{ - while ((*UART0FR) & (1 << 5)) - { - } - *UART0DR = byte; /* Transmit char */ -} - -char GetByte(void) -{ - while ((*UART0FR) & (1 << 4)) - { - - } - return *UART0DR & 0xff; +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 16:07:31 + * @LastEditTime: 2021-06-29 11:48:58 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#include "early_uart.h" + +volatile unsigned int *const UART0DR = (unsigned int *)0x10009000u; +volatile unsigned int *const UART0FR = (unsigned int *)0x10009018u; + +void OutByte(s8 byte) +{ + while ((*UART0FR) & (1 << 5)) + { + } + *UART0DR = byte; /* Transmit char */ +} + +char GetByte(void) +{ + while ((*UART0FR) & (1 << 4)) + { + + } + return *UART0DR & 0xff; } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/platform/qemu/early_uart.h b/bsp/arch/armv8/aarch32/platform/qemu/early_uart.h index af74f6b95..17a7e2eaf 100644 --- a/bsp/arch/armv8/aarch32/platform/qemu/early_uart.h +++ b/bsp/arch/armv8/aarch32/platform/qemu/early_uart.h @@ -1,32 +1,32 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-17 13:19:37 - * @LastEditTime: 2021-06-29 11:20:07 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#ifndef BSP_ARCH_ARMV8_AARCH32_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH32_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - -void OutByte(s8 byte); -char GetByte(void); - -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-17 13:19:37 + * @LastEditTime: 2021-06-29 11:20:07 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#ifndef BSP_ARCH_ARMV8_AARCH32_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH32_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + +void OutByte(s8 byte); +char GetByte(void); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch32/psci.c b/bsp/arch/armv8/aarch32/psci.c index 20974d514..b9bacffaa 100644 --- a/bsp/arch/armv8/aarch32/psci.c +++ b/bsp/arch/armv8/aarch32/psci.c @@ -1,77 +1,77 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-21 10:43:52 - * @LastEditTime: 2021-07-02 15:51:01 - * @Description:  Description of file - * @Modify History: - * * * Ver   Who        Date         Changes - * * ----- ------     --------    -------------------------------------- - */ - -#include "psci.h" -#include "smc.h" -#include "parameters.h" - -#define PSCI_CPUON_NUM 0x84000003 -#define PSCI_RESET_NUM 0x84000009 -const u32 SoftAffiTable[4] = {CORE0_AFF, CORE1_AFF, CORE2_AFF, CORE3_AFF}; -/** - * @name: FPsci_CpuOn - * @msg: Power up a core - * @in param CpuList: Bits[24:31]: Must be zero. - * Bits[16:23] Aff2: Match Aff2 of target core MPIDR - * Bits[8:15] Aff1: Match Aff1 of target core MPIDR - * Bits[0:7] Aff0: Match Aff0 of target core MPIDR - * @in param BootAddr: a 32-bit entry point physical address (or IPA). - * @return {None} - */ -void PsciCpuOn(s32 CpuIdMask, u32 BootAddr) -{ - - FSmc_Data_t Input = {0}; - FSmc_Data_t Output = {0}; - Input.FunctionIdentifier = PSCI_CPUON_NUM; - - if ((1 << 0) == CpuIdMask) - { - Input.a1 = SoftAffiTable[0]; - } - else if ((1 << 1) == CpuIdMask) - { - Input.a1 = SoftAffiTable[1]; - } - else if ((1 << 2) == CpuIdMask) - { - Input.a1 = SoftAffiTable[2]; - } - else if ((1 << 3) == CpuIdMask) - { - Input.a1 = SoftAffiTable[3]; - } - else - { - return; - } - - /*input.a2 = (u32)(BootAddr >> 32);*/ - Input.a2 = (u32)(BootAddr & 0xFFFFFFFF); - FSmc_Call(&Input, &Output); - __asm__ volatile("NOP"); -} - -void PsciCpuReset(void) -{ - - FSmc_Data_t Input = {0}; - FSmc_Data_t Output = {0}; - - Input.FunctionIdentifier = PSCI_RESET_NUM; - FSmc_Call(&Input, &Output); - - __asm__ volatile("NOP"); - while (1) - ; -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-21 10:43:52 + * @LastEditTime: 2021-07-02 15:51:01 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include "psci.h" +#include "smc.h" +#include "parameters.h" + +#define PSCI_CPUON_NUM 0x84000003 +#define PSCI_RESET_NUM 0x84000009 +const u32 SoftAffiTable[4] = {CORE0_AFF, CORE1_AFF, CORE2_AFF, CORE3_AFF}; +/** + * @name: FPsci_CpuOn + * @msg: Power up a core + * @in param CpuList: Bits[24:31]: Must be zero. + * Bits[16:23] Aff2: Match Aff2 of target core MPIDR + * Bits[8:15] Aff1: Match Aff1 of target core MPIDR + * Bits[0:7] Aff0: Match Aff0 of target core MPIDR + * @in param BootAddr: a 32-bit entry point physical address (or IPA). + * @return {None} + */ +void PsciCpuOn(s32 CpuIdMask, u32 BootAddr) +{ + + FSmc_Data_t Input = {0}; + FSmc_Data_t Output = {0}; + Input.FunctionIdentifier = PSCI_CPUON_NUM; + + if ((1 << 0) == CpuIdMask) + { + Input.a1 = SoftAffiTable[0]; + } + else if ((1 << 1) == CpuIdMask) + { + Input.a1 = SoftAffiTable[1]; + } + else if ((1 << 2) == CpuIdMask) + { + Input.a1 = SoftAffiTable[2]; + } + else if ((1 << 3) == CpuIdMask) + { + Input.a1 = SoftAffiTable[3]; + } + else + { + return; + } + + /*input.a2 = (u32)(BootAddr >> 32);*/ + Input.a2 = (u32)(BootAddr & 0xFFFFFFFF); + FSmc_Call(&Input, &Output); + __asm__ volatile("NOP"); +} + +void PsciCpuReset(void) +{ + + FSmc_Data_t Input = {0}; + FSmc_Data_t Output = {0}; + + Input.FunctionIdentifier = PSCI_RESET_NUM; + FSmc_Call(&Input, &Output); + + __asm__ volatile("NOP"); + while (1) + ; +} diff --git a/bsp/arch/armv8/aarch32/psci.h b/bsp/arch/armv8/aarch32/psci.h index 798fef1dc..a793329e8 100644 --- a/bsp/arch/armv8/aarch32/psci.h +++ b/bsp/arch/armv8/aarch32/psci.h @@ -1,31 +1,31 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-21 10:43:59 - * @LastEditTime: 2021-07-01 18:42:35 - * @Description:  Description of file - * @Modify History: - * * * Ver   Who        Date         Changes - * * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_ARCH_ARMV8_AARCH32_PSCI_H -#define BSP_ARCH_ARMV8_AARCH32_PSCI_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - void PsciCpuOn(s32 CpuIdMask, u32 BootAddr); - void PsciCpuReset(void); - -#ifdef __cplusplus -} -#endif - -#endif // ! +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-21 10:43:59 + * @LastEditTime: 2021-07-01 18:42:35 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_PSCI_H +#define BSP_ARCH_ARMV8_AARCH32_PSCI_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + void PsciCpuOn(s32 CpuIdMask, u32 BootAddr); + void PsciCpuReset(void); + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/arch/armv8/aarch32/smc.h b/bsp/arch/armv8/aarch32/smc.h index 334d1e7ca..fa2cb1fbf 100644 --- a/bsp/arch/armv8/aarch32/smc.h +++ b/bsp/arch/armv8/aarch32/smc.h @@ -1,42 +1,42 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-21 11:53:38 - * @LastEditTime: 2021-07-01 18:43:29 - * @Description:  Description of file - * @Modify History: - * * * Ver   Who        Date         Changes - * * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_ARCH_ARMV8_AARCH32_SMC_H -#define BSP_ARCH_ARMV8_AARCH32_SMC_H - -#ifdef __cplusplus -extern "C" -{ -#endif -#include "ft_types.h" - - typedef struct - { - /* data */ - u32 FunctionIdentifier; - u32 a1; - u32 a2; - u32 a3; - u32 a4; - u32 a5; - u32 a6; - - } FSmc_Data_t; - - void FSmc_Call(FSmc_Data_t *Input, FSmc_Data_t *Output); - -#ifdef __cplusplus -} -#endif - -#endif // !FT_SMC_H +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-21 11:53:38 + * @LastEditTime: 2021-07-01 18:43:29 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_ARCH_ARMV8_AARCH32_SMC_H +#define BSP_ARCH_ARMV8_AARCH32_SMC_H + +#ifdef __cplusplus +extern "C" +{ +#endif +#include "ft_types.h" + + typedef struct + { + /* data */ + u32 FunctionIdentifier; + u32 a1; + u32 a2; + u32 a3; + u32 a4; + u32 a5; + u32 a6; + + } FSmc_Data_t; + + void FSmc_Call(FSmc_Data_t *Input, FSmc_Data_t *Output); + +#ifdef __cplusplus +} +#endif + +#endif // !FT_SMC_H diff --git a/bsp/arch/armv8/aarch64/aarch64.c b/bsp/arch/armv8/aarch64/aarch64.c index df70d81c2..b99b8bdce 100644 --- a/bsp/arch/armv8/aarch64/aarch64.c +++ b/bsp/arch/armv8/aarch64/aarch64.c @@ -1,313 +1,313 @@ -/* - * Reference: ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile - */ -#include -#include "aarch64.h" - -/* CurrentEL, Current Exception Level - EL, bits [3:2] - Current exception level. Possible values of this field are: - 00 EL0 - 01 EL1 - 10 EL2 - 11 EL3 -*/ -u32 raw_read_current_el(void) -{ - u32 current_el; - - __asm__ __volatile__("mrs %0, CurrentEL\n\t" - : "=r"(current_el) - : - : "memory"); - return current_el; -} - -u32 get_current_el(void) -{ - u32 current_el = raw_read_current_el(); - return ((current_el >> CURRENT_EL_SHIFT) & CURRENT_EL_MASK); -} - -u64 get_hcr_el2(void) -{ - u64 hcr_el2; - __asm__ __volatile__("mrs %0, hcr_el2\n\t" - : "=r"(hcr_el2) - : - : "memory"); - return hcr_el2; -} - -u32 get_esr_el1(void) -{ - u32 esr_el1; - __asm__ __volatile__("mrs %0, ESR_EL1\n\t" - : "=r"(esr_el1) - : - : "memory"); - return esr_el1; -} - -/* DAIF, Interrupt Mask Bits - Allows access to the interrupt mask bits. - - D, bit [9]: Debug exceptions. - A, bit [8]: SError (System Error) mask bit. - I, bit [7]: IRQ mask bit. - F, bit [6]: FIQ mask bit. - value: - 0 Exception not masked. - 1 Exception masked. -*/ -u32 raw_read_daif(void) -{ - u32 daif; - - __asm__ __volatile__("mrs %0, DAIF\n\t" - : "=r"(daif) - : - : "memory"); - return daif; -} - -void raw_write_daif(u32 daif) -{ - __asm__ __volatile__("msr DAIF, %0\n\t" - : - : "r"(daif) - : "memory"); -} - -void enable_debug_exceptions(void) -{ - __asm__ __volatile__("msr DAIFClr, %0\n\t" - : - : "i"(DAIF_DBG_BIT) - : "memory"); -} - -void enable_serror_exceptions(void) -{ - __asm__ __volatile__("msr DAIFClr, %0\n\t" - : - : "i"(DAIF_ABT_BIT) - : "memory"); -} - -void disable_debug_exceptions(void) -{ - __asm__ __volatile__("msr DAIFSet, %0\n\t" - : - : "i"(DAIF_DBG_BIT) - : "memory"); -} - -void disable_serror_exceptions(void) -{ - __asm__ __volatile__("msr DAIFSet, %0\n\t" - : - : "i"(DAIF_ABT_BIT) - : "memory"); -} - -void disable_irq(void) -{ - __asm__ __volatile__("msr DAIFSet, %0\n\t" - : - : "i"(DAIF_IRQ_BIT) - : "memory"); -} - -void disable_fiq(void) -{ - __asm__ __volatile__("msr DAIFSet, %0\n\t" - : - : "i"(DAIF_FIQ_BIT) - : "memory"); -} - -/* SPSR_EL1, Saved Program Status Register (EL1) - Holds the saved processor state when an exception is taken to EL1. -*/ -u32 raw_read_spsr_el1(void) -{ - u32 spsr_el1; - - __asm__ __volatile__("mrs %0, SPSR_EL1\n\t" - : "=r"(spsr_el1) - : - : "memory"); - return spsr_el1; -} - -void raw_write_spsr_el1(u32 spsr_el1) -{ - __asm__ __volatile__("msr SPSR_EL1, %0\n\t" - : - : "r"(spsr_el1) - : "memory"); -} - -/* -ISR_EL1, Interrupt Status Register - Shows whether an IRQ, FIQ, or SError interrupt is pending. -*/ -u32 raw_read_isr_el1(void) -{ - u32 isr_el1; - - __asm__ __volatile__("mrs %0, ISR_EL1\n\t" - : "=r"(isr_el1) - : - : "memory"); - return isr_el1; -} - -/* -RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not implemented) - If EL1 is the highest exception level implemented, contains the - IMPLEMENTATION DEFINED address that execution starts from after reset when - executing in AArch64 state. -*/ -uint64_t raw_read_rvbar_el1(void) -{ - uint64_t rvbar_el1; - - __asm__ __volatile__("mrs %0, RVBAR_EL1\n\t" - : "=r"(rvbar_el1) - : - : "memory"); - return rvbar_el1; -} - -void raw_write_rvbar_el1(uint64_t rvbar_el1) -{ - __asm__ __volatile__("msr RVBAR_EL1, %0\n\t" - : - : "r"(rvbar_el1) - : "memory"); -} - -/* VBAR_EL1, Vector Base Address Register (EL1) - Holds the exception base address for any exception that is taken to EL1. -*/ -uint64_t raw_read_vbar_el1(void) -{ - uint64_t vbar_el1; - - __asm__ __volatile__("mrs %0, VBAR_EL1\n\t" - : "=r"(vbar_el1) - : - : "memory"); - return vbar_el1; -} - -void raw_write_vbar_el1(uint64_t vbar_el1) -{ - __asm__ __volatile__("msr VBAR_EL1, %0\n\t" - : - : "r"(vbar_el1) - : "memory"); -} - -/* CNTV_CTL_EL0, Counter-timer Virtual Timer Control register - Control register for the virtual timer. - - ISTATUS, bit [2]: The status of the timer interrupt. - IMASK, bit [1]: Timer interrupt mask bit. - ENABLE, bit [0]: Enables the timer. -*/ -u32 raw_read_cntv_ctl(void) -{ - u32 cntv_ctl; - - __asm__ __volatile__("mrs %0, CNTV_CTL_EL0\n\t" - : "=r"(cntv_ctl) - : - : "memory"); - return cntv_ctl; -} - -void disable_cntv(void) -{ - u32 cntv_ctl; - - cntv_ctl = raw_read_cntv_ctl(); - cntv_ctl &= ~CNTV_CTL_ENABLE; - __asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" - : - : "r"(cntv_ctl) - : "memory"); -} - -void enable_cntv(void) -{ - u32 cntv_ctl; - - cntv_ctl = raw_read_cntv_ctl(); - cntv_ctl |= CNTV_CTL_ENABLE; - __asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" - : - : "r"(cntv_ctl) - : "memory"); -} - -/* -CNTFRQ_EL0, Counter-timer Frequency register - Holds the clock frequency of the system counter. -*/ -u32 raw_read_cntfrq_el0(void) -{ - u32 cntfrq_el0; - - __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" - : "=r"(cntfrq_el0) - : - : "memory"); - return cntfrq_el0; -} - -void raw_write_cntfrq_el0(u32 cntfrq_el0) -{ - __asm__ __volatile__("msr CNTFRQ_EL0, %0\n\t" - : - : "r"(cntfrq_el0) - : "memory"); -} - -/* CNTVCT_EL0, Counter-timer Virtual Count register - Holds the 64-bit virtual count value. -*/ -uint64_t raw_read_cntvct_el0(void) -{ - uint64_t cntvct_el0; - - __asm__ __volatile__("mrs %0, CNTVCT_EL0\n\t" - : "=r"(cntvct_el0) - : - : "memory"); - return cntvct_el0; -} - -/* CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register - Holds the compare value for the virtual timer. -*/ -uint64_t raw_read_cntv_cval_el0(void) -{ - uint64_t cntv_cval_el0; - - __asm__ __volatile__("mrs %0, CNTV_CVAL_EL0\n\t" - : "=r"(cntv_cval_el0) - : - : "memory"); - return cntv_cval_el0; -} - -void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0) -{ - __asm__ __volatile__("msr CNTV_CVAL_EL0, %0\n\t" - : - : "r"(cntv_cval_el0) - : "memory"); -} +/* + * Reference: ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile + */ +#include +#include "aarch64.h" + +/* CurrentEL, Current Exception Level + EL, bits [3:2] + Current exception level. Possible values of this field are: + 00 EL0 + 01 EL1 + 10 EL2 + 11 EL3 +*/ +u32 raw_read_current_el(void) +{ + u32 current_el; + + __asm__ __volatile__("mrs %0, CurrentEL\n\t" + : "=r"(current_el) + : + : "memory"); + return current_el; +} + +u32 get_current_el(void) +{ + u32 current_el = raw_read_current_el(); + return ((current_el >> CURRENT_EL_SHIFT) & CURRENT_EL_MASK); +} + +u64 get_hcr_el2(void) +{ + u64 hcr_el2; + __asm__ __volatile__("mrs %0, hcr_el2\n\t" + : "=r"(hcr_el2) + : + : "memory"); + return hcr_el2; +} + +u32 get_esr_el1(void) +{ + u32 esr_el1; + __asm__ __volatile__("mrs %0, ESR_EL1\n\t" + : "=r"(esr_el1) + : + : "memory"); + return esr_el1; +} + +/* DAIF, Interrupt Mask Bits + Allows access to the interrupt mask bits. + + D, bit [9]: Debug exceptions. + A, bit [8]: SError (System Error) mask bit. + I, bit [7]: IRQ mask bit. + F, bit [6]: FIQ mask bit. + value: + 0 Exception not masked. + 1 Exception masked. +*/ +u32 raw_read_daif(void) +{ + u32 daif; + + __asm__ __volatile__("mrs %0, DAIF\n\t" + : "=r"(daif) + : + : "memory"); + return daif; +} + +void raw_write_daif(u32 daif) +{ + __asm__ __volatile__("msr DAIF, %0\n\t" + : + : "r"(daif) + : "memory"); +} + +void enable_debug_exceptions(void) +{ + __asm__ __volatile__("msr DAIFClr, %0\n\t" + : + : "i"(DAIF_DBG_BIT) + : "memory"); +} + +void enable_serror_exceptions(void) +{ + __asm__ __volatile__("msr DAIFClr, %0\n\t" + : + : "i"(DAIF_ABT_BIT) + : "memory"); +} + +void disable_debug_exceptions(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" + : + : "i"(DAIF_DBG_BIT) + : "memory"); +} + +void disable_serror_exceptions(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" + : + : "i"(DAIF_ABT_BIT) + : "memory"); +} + +void disable_irq(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" + : + : "i"(DAIF_IRQ_BIT) + : "memory"); +} + +void disable_fiq(void) +{ + __asm__ __volatile__("msr DAIFSet, %0\n\t" + : + : "i"(DAIF_FIQ_BIT) + : "memory"); +} + +/* SPSR_EL1, Saved Program Status Register (EL1) + Holds the saved processor state when an exception is taken to EL1. +*/ +u32 raw_read_spsr_el1(void) +{ + u32 spsr_el1; + + __asm__ __volatile__("mrs %0, SPSR_EL1\n\t" + : "=r"(spsr_el1) + : + : "memory"); + return spsr_el1; +} + +void raw_write_spsr_el1(u32 spsr_el1) +{ + __asm__ __volatile__("msr SPSR_EL1, %0\n\t" + : + : "r"(spsr_el1) + : "memory"); +} + +/* +ISR_EL1, Interrupt Status Register + Shows whether an IRQ, FIQ, or SError interrupt is pending. +*/ +u32 raw_read_isr_el1(void) +{ + u32 isr_el1; + + __asm__ __volatile__("mrs %0, ISR_EL1\n\t" + : "=r"(isr_el1) + : + : "memory"); + return isr_el1; +} + +/* +RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not implemented) + If EL1 is the highest exception level implemented, contains the + IMPLEMENTATION DEFINED address that execution starts from after reset when + executing in AArch64 state. +*/ +uint64_t raw_read_rvbar_el1(void) +{ + uint64_t rvbar_el1; + + __asm__ __volatile__("mrs %0, RVBAR_EL1\n\t" + : "=r"(rvbar_el1) + : + : "memory"); + return rvbar_el1; +} + +void raw_write_rvbar_el1(uint64_t rvbar_el1) +{ + __asm__ __volatile__("msr RVBAR_EL1, %0\n\t" + : + : "r"(rvbar_el1) + : "memory"); +} + +/* VBAR_EL1, Vector Base Address Register (EL1) + Holds the exception base address for any exception that is taken to EL1. +*/ +uint64_t raw_read_vbar_el1(void) +{ + uint64_t vbar_el1; + + __asm__ __volatile__("mrs %0, VBAR_EL1\n\t" + : "=r"(vbar_el1) + : + : "memory"); + return vbar_el1; +} + +void raw_write_vbar_el1(uint64_t vbar_el1) +{ + __asm__ __volatile__("msr VBAR_EL1, %0\n\t" + : + : "r"(vbar_el1) + : "memory"); +} + +/* CNTV_CTL_EL0, Counter-timer Virtual Timer Control register + Control register for the virtual timer. + + ISTATUS, bit [2]: The status of the timer interrupt. + IMASK, bit [1]: Timer interrupt mask bit. + ENABLE, bit [0]: Enables the timer. +*/ +u32 raw_read_cntv_ctl(void) +{ + u32 cntv_ctl; + + __asm__ __volatile__("mrs %0, CNTV_CTL_EL0\n\t" + : "=r"(cntv_ctl) + : + : "memory"); + return cntv_ctl; +} + +void disable_cntv(void) +{ + u32 cntv_ctl; + + cntv_ctl = raw_read_cntv_ctl(); + cntv_ctl &= ~CNTV_CTL_ENABLE; + __asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" + : + : "r"(cntv_ctl) + : "memory"); +} + +void enable_cntv(void) +{ + u32 cntv_ctl; + + cntv_ctl = raw_read_cntv_ctl(); + cntv_ctl |= CNTV_CTL_ENABLE; + __asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" + : + : "r"(cntv_ctl) + : "memory"); +} + +/* +CNTFRQ_EL0, Counter-timer Frequency register + Holds the clock frequency of the system counter. +*/ +u32 raw_read_cntfrq_el0(void) +{ + u32 cntfrq_el0; + + __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" + : "=r"(cntfrq_el0) + : + : "memory"); + return cntfrq_el0; +} + +void raw_write_cntfrq_el0(u32 cntfrq_el0) +{ + __asm__ __volatile__("msr CNTFRQ_EL0, %0\n\t" + : + : "r"(cntfrq_el0) + : "memory"); +} + +/* CNTVCT_EL0, Counter-timer Virtual Count register + Holds the 64-bit virtual count value. +*/ +uint64_t raw_read_cntvct_el0(void) +{ + uint64_t cntvct_el0; + + __asm__ __volatile__("mrs %0, CNTVCT_EL0\n\t" + : "=r"(cntvct_el0) + : + : "memory"); + return cntvct_el0; +} + +/* CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register + Holds the compare value for the virtual timer. +*/ +uint64_t raw_read_cntv_cval_el0(void) +{ + uint64_t cntv_cval_el0; + + __asm__ __volatile__("mrs %0, CNTV_CVAL_EL0\n\t" + : "=r"(cntv_cval_el0) + : + : "memory"); + return cntv_cval_el0; +} + +void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0) +{ + __asm__ __volatile__("msr CNTV_CVAL_EL0, %0\n\t" + : + : "r"(cntv_cval_el0) + : "memory"); +} diff --git a/bsp/arch/armv8/aarch64/aarch64.h b/bsp/arch/armv8/aarch64/aarch64.h index 5f089881b..2b998453e 100644 --- a/bsp/arch/armv8/aarch64/aarch64.h +++ b/bsp/arch/armv8/aarch64/aarch64.h @@ -1,236 +1,236 @@ - - -#ifndef BSP_ARCH_ARMV8 -#define BSP_ARCH_ARMV8 - -#include -#include "ft_types.h" - -/* CurrentEL, Current Exception Level */ -#define CURRENT_EL_MASK 0x3 -#define CURRENT_EL_SHIFT 2 - -/* DAIF, Interrupt Mask Bits */ -#define DAIF_DBG_BIT (1 << 3) /* Debug mask bit */ -#define DAIF_ABT_BIT (1 << 2) /* Asynchronous abort mask bit */ -#define DAIF_IRQ_BIT (1 << 1) /* IRQ mask bit */ -#define DAIF_FIQ_BIT (1 << 0) /* FIQ mask bit */ - -/* - * Interrupt flags - */ -#define AARCH64_DAIF_FIQ (1) /* FIQ */ -#define AARCH64_DAIF_IRQ (2) /* IRQ */ - -/* Timer */ -#define CNTV_CTL_ENABLE (1 << 0) /* Enables the timer */ -#define CNTV_CTL_IMASK (1 << 1) /* Timer interrupt mask bit */ -#define CNTV_CTL_ISTATUS (1 << 2) /* The status of the timer interrupt. This bit is read-only */ - -// -// AArch64 SPSR -// -#define AARCH64_SPSR_EL3h 0b1101 -#define AARCH64_SPSR_EL3t 0b1100 -#define AARCH64_SPSR_EL2h 0b1001 -#define AARCH64_SPSR_EL2t 0b1000 -#define AARCH64_SPSR_EL1h 0b0101 -#define AARCH64_SPSR_EL1t 0b0100 -#define AARCH64_SPSR_EL0t 0b0000 -#define AARCH64_SPSR_RW (1 << 4) -#define AARCH64_SPSR_F (1 << 6) -#define AARCH64_SPSR_I (1 << 7) -#define AARCH64_SPSR_A (1 << 8) -#define AARCH64_SPSR_D (1 << 9) -#define AARCH64_SPSR_IL (1 << 20) -#define AARCH64_SPSR_SS (1 << 21) -#define AARCH64_SPSR_V (1 << 28) -#define AARCH64_SPSR_C (1 << 29) -#define AARCH64_SPSR_Z (1 << 30) -#define AARCH64_SPSR_N (1 << 31) - -// -// Multiprocessor Affinity Register -// -#define MPIDR_EL1_AFF3_LSB 32 -#define MPIDR_EL1_U (1 << 30) -#define MPIDR_EL1_MT (1 << 24) -#define MPIDR_EL1_AFF2_LSB 16 -#define MPIDR_EL1_AFF1_LSB 8 -#define MPIDR_EL1_AFF0_LSB 0 -#define MPIDR_EL1_AFF_WIDTH 8 - -// -// Data Cache Zero ID Register -// -#define DCZID_EL0_BS_LSB 0 -#define DCZID_EL0_BS_WIDTH 4 -#define DCZID_EL0_DZP_LSB 5 -#define DCZID_EL0_DZP (1 << 5) - -// -// System Control Register -// -#define SCTLR_EL1_UCI (1 << 26) -#define SCTLR_ELx_EE (1 << 25) -#define SCTLR_EL1_E0E (1 << 24) -#define SCTLR_ELx_WXN (1 << 19) -#define SCTLR_EL1_nTWE (1 << 18) -#define SCTLR_EL1_nTWI (1 << 16) -#define SCTLR_EL1_UCT (1 << 15) -#define SCTLR_EL1_DZE (1 << 14) -#define SCTLR_ELx_I (1 << 12) -#define SCTLR_EL1_UMA (1 << 9) -#define SCTLR_EL1_SED (1 << 8) -#define SCTLR_EL1_ITD (1 << 7) -#define SCTLR_EL1_THEE (1 << 6) -#define SCTLR_EL1_CP15BEN (1 << 5) -#define SCTLR_EL1_SA0 (1 << 4) -#define SCTLR_ELx_SA (1 << 3) -#define SCTLR_ELx_C (1 << 2) -#define SCTLR_ELx_A (1 << 1) -#define SCTLR_ELx_M (1 << 0) - -// -// Architectural Feature Access Control Register -// -#define CPACR_EL1_TTA (1 << 28) -#define CPACR_EL1_FPEN (3 << 20) - -// -// Architectural Feature Trap Register -// -#define CPTR_ELx_TCPAC (1 << 31) -#define CPTR_ELx_TTA (1 << 20) -#define CPTR_ELx_TFP (1 << 10) - -// -// Secure Configuration Register -// -#define SCR_EL3_TWE (1 << 13) -#define SCR_EL3_TWI (1 << 12) -#define SCR_EL3_ST (1 << 11) -#define SCR_EL3_RW (1 << 10) -#define SCR_EL3_SIF (1 << 9) -#define SCR_EL3_HCE (1 << 8) -#define SCR_EL3_SMD (1 << 7) -#define SCR_EL3_EA (1 << 3) -#define SCR_EL3_FIQ (1 << 2) -#define SCR_EL3_IRQ (1 << 1) -#define SCR_EL3_NS (1 << 0) - -// -// Hypervisor Configuration Register -// -#define HCR_EL2_ID (1 << 33) -#define HCR_EL2_CD (1 << 32) -#define HCR_EL2_RW (1 << 31) -#define HCR_EL2_TRVM (1 << 30) -#define HCR_EL2_HVC (1 << 29) -#define HCR_EL2_TDZ (1 << 28) - -#define INTERRUPT_ENABLE() __asm__ __volatile__("msr daifclr, #2" :: \ - : "memory") - -#define INTERRUPT_DISABLE() __asm__ __volatile__("msr daifset, #2" :: \ - : "memory") - -#define MODE_EL_SHIFT (0x2) -#define MODE_EL_MASK (0x3) - -#define MODE_EL3 (0x3) -#define MODE_EL2 (0x2) -#define MODE_EL1 (0x1) -#define MODE_EL0 (0x0) - -#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) - -/* memory synchronization operations */ - -/* Instruction Synchronization Barrier */ -#define ISB() __asm__ __volatile__("isb sy") - -/* Data Synchronization Barrier */ -#define DSB() __asm__ __volatile__("dsb sy") - -/* Data Memory Barrier */ -#define DMB() __asm__ __volatile__("dmb sy") - -/* Wait For Interrupt */ -#define wfi() asm volatile("wfi" \ - : \ - : \ - : "memory") - -/* Count leading zeroes (clz) */ -#define clz(arg) ( \ - { \ - uint32_t rval; \ - __asm__ __volatile__( \ - "clz %0,%1" \ - : "=r"(rval) \ - : "r"(arg)); \ - rval; \ - }) - -#define MTCPDC(reg, val) __asm__ __volatile__("dc " #reg ",%0" \ - : \ - : "r"(val)) -#define MTCPIC(reg, val) __asm__ __volatile__("ic " #reg ",%0" \ - : \ - : "r"(val)) - -#define MTCPICALL(reg) __asm__ __volatile__("ic " #reg) -#define MTCPTLBI(reg) __asm__ __volatile__("tlbi " #reg) -#define MTCPAT(reg, val) __asm__ __volatile__("at " #reg ",%0" \ - : \ - : "r"(val)) - -#define AARCH64_READ_SYSREG(reg) ( \ - { \ - uint64_t val; \ - __asm__ __volatile__("mrs %0," #reg \ - : "=r"(val)); \ - val; \ - }) -#define AARCH64_WRITE_SYSREG(reg, val) __asm__ __volatile__("msr " #reg ", %0\n\tdsb sy\n\tisb" ::"r"(val)); - -/* PSTATE and special purpose register access functions */ -uint32_t raw_read_current_el(void); -uint32_t get_current_el(void); -uint32_t raw_read_daif(void); -void raw_write_daif(uint32_t daif); -void enable_debug_exceptions(void); -void enable_serror_exceptions(void); -void enable_irq(void); -void enable_fiq(void); -void disable_debug_exceptions(void); -void disable_serror_exceptions(void); -void disable_irq(void); -void disable_fiq(void); -/* SPSR_EL1, Saved Program Status Register (EL1) */ -uint32_t raw_read_spsr_el1(void); -void raw_write_spsr_el1(uint32_t spsr_el1); -/* ISR_EL1, Interrupt Status Register */ -uint32_t raw_read_isr_el1(void); -uint64_t raw_read_rvbar_el1(void); -void raw_write_rvbar_el1(uint64_t rvbar_el1); -uint64_t raw_read_vbar_el1(void); -void raw_write_vbar_el1(uint64_t vbar_el1); - -/* CNTV_CTL_EL0, Counter-timer Virtual Timer Control register */ -uint32_t raw_read_cntv_ctl(void); -void disable_cntv(void); -void enable_cntv(void); -/* CNTFRQ_EL0, Counter-timer Frequency register */ -uint32_t raw_read_cntfrq_el0(void); -void raw_write_cntfrq_el0(uint32_t cntfrq_el0); -/* CNTVCT_EL0, Counter-timer Virtual Count register */ -uint64_t raw_read_cntvct_el0(void); -/* CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register */ -uint64_t raw_read_cntv_cval_el0(void); -void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0); - -u64 get_hcr_el2(void); -u32 get_esr_el1(void); -#endif // V8_SYSTEM_H + + +#ifndef BSP_ARCH_ARMV8 +#define BSP_ARCH_ARMV8 + +#include +#include "ft_types.h" + +/* CurrentEL, Current Exception Level */ +#define CURRENT_EL_MASK 0x3 +#define CURRENT_EL_SHIFT 2 + +/* DAIF, Interrupt Mask Bits */ +#define DAIF_DBG_BIT (1 << 3) /* Debug mask bit */ +#define DAIF_ABT_BIT (1 << 2) /* Asynchronous abort mask bit */ +#define DAIF_IRQ_BIT (1 << 1) /* IRQ mask bit */ +#define DAIF_FIQ_BIT (1 << 0) /* FIQ mask bit */ + +/* + * Interrupt flags + */ +#define AARCH64_DAIF_FIQ (1) /* FIQ */ +#define AARCH64_DAIF_IRQ (2) /* IRQ */ + +/* Timer */ +#define CNTV_CTL_ENABLE (1 << 0) /* Enables the timer */ +#define CNTV_CTL_IMASK (1 << 1) /* Timer interrupt mask bit */ +#define CNTV_CTL_ISTATUS (1 << 2) /* The status of the timer interrupt. This bit is read-only */ + +// +// AArch64 SPSR +// +#define AARCH64_SPSR_EL3h 0b1101 +#define AARCH64_SPSR_EL3t 0b1100 +#define AARCH64_SPSR_EL2h 0b1001 +#define AARCH64_SPSR_EL2t 0b1000 +#define AARCH64_SPSR_EL1h 0b0101 +#define AARCH64_SPSR_EL1t 0b0100 +#define AARCH64_SPSR_EL0t 0b0000 +#define AARCH64_SPSR_RW (1 << 4) +#define AARCH64_SPSR_F (1 << 6) +#define AARCH64_SPSR_I (1 << 7) +#define AARCH64_SPSR_A (1 << 8) +#define AARCH64_SPSR_D (1 << 9) +#define AARCH64_SPSR_IL (1 << 20) +#define AARCH64_SPSR_SS (1 << 21) +#define AARCH64_SPSR_V (1 << 28) +#define AARCH64_SPSR_C (1 << 29) +#define AARCH64_SPSR_Z (1 << 30) +#define AARCH64_SPSR_N (1 << 31) + +// +// Multiprocessor Affinity Register +// +#define MPIDR_EL1_AFF3_LSB 32 +#define MPIDR_EL1_U (1 << 30) +#define MPIDR_EL1_MT (1 << 24) +#define MPIDR_EL1_AFF2_LSB 16 +#define MPIDR_EL1_AFF1_LSB 8 +#define MPIDR_EL1_AFF0_LSB 0 +#define MPIDR_EL1_AFF_WIDTH 8 + +// +// Data Cache Zero ID Register +// +#define DCZID_EL0_BS_LSB 0 +#define DCZID_EL0_BS_WIDTH 4 +#define DCZID_EL0_DZP_LSB 5 +#define DCZID_EL0_DZP (1 << 5) + +// +// System Control Register +// +#define SCTLR_EL1_UCI (1 << 26) +#define SCTLR_ELx_EE (1 << 25) +#define SCTLR_EL1_E0E (1 << 24) +#define SCTLR_ELx_WXN (1 << 19) +#define SCTLR_EL1_nTWE (1 << 18) +#define SCTLR_EL1_nTWI (1 << 16) +#define SCTLR_EL1_UCT (1 << 15) +#define SCTLR_EL1_DZE (1 << 14) +#define SCTLR_ELx_I (1 << 12) +#define SCTLR_EL1_UMA (1 << 9) +#define SCTLR_EL1_SED (1 << 8) +#define SCTLR_EL1_ITD (1 << 7) +#define SCTLR_EL1_THEE (1 << 6) +#define SCTLR_EL1_CP15BEN (1 << 5) +#define SCTLR_EL1_SA0 (1 << 4) +#define SCTLR_ELx_SA (1 << 3) +#define SCTLR_ELx_C (1 << 2) +#define SCTLR_ELx_A (1 << 1) +#define SCTLR_ELx_M (1 << 0) + +// +// Architectural Feature Access Control Register +// +#define CPACR_EL1_TTA (1 << 28) +#define CPACR_EL1_FPEN (3 << 20) + +// +// Architectural Feature Trap Register +// +#define CPTR_ELx_TCPAC (1 << 31) +#define CPTR_ELx_TTA (1 << 20) +#define CPTR_ELx_TFP (1 << 10) + +// +// Secure Configuration Register +// +#define SCR_EL3_TWE (1 << 13) +#define SCR_EL3_TWI (1 << 12) +#define SCR_EL3_ST (1 << 11) +#define SCR_EL3_RW (1 << 10) +#define SCR_EL3_SIF (1 << 9) +#define SCR_EL3_HCE (1 << 8) +#define SCR_EL3_SMD (1 << 7) +#define SCR_EL3_EA (1 << 3) +#define SCR_EL3_FIQ (1 << 2) +#define SCR_EL3_IRQ (1 << 1) +#define SCR_EL3_NS (1 << 0) + +// +// Hypervisor Configuration Register +// +#define HCR_EL2_ID (1 << 33) +#define HCR_EL2_CD (1 << 32) +#define HCR_EL2_RW (1 << 31) +#define HCR_EL2_TRVM (1 << 30) +#define HCR_EL2_HVC (1 << 29) +#define HCR_EL2_TDZ (1 << 28) + +#define INTERRUPT_ENABLE() __asm__ __volatile__("msr daifclr, #2" :: \ + : "memory") + +#define INTERRUPT_DISABLE() __asm__ __volatile__("msr daifset, #2" :: \ + : "memory") + +#define MODE_EL_SHIFT (0x2) +#define MODE_EL_MASK (0x3) + +#define MODE_EL3 (0x3) +#define MODE_EL2 (0x2) +#define MODE_EL1 (0x1) +#define MODE_EL0 (0x0) + +#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define ISB() __asm__ __volatile__("isb sy") + +/* Data Synchronization Barrier */ +#define DSB() __asm__ __volatile__("dsb sy") + +/* Data Memory Barrier */ +#define DMB() __asm__ __volatile__("dmb sy") + +/* Wait For Interrupt */ +#define wfi() asm volatile("wfi" \ + : \ + : \ + : "memory") + +/* Count leading zeroes (clz) */ +#define clz(arg) ( \ + { \ + uint32_t rval; \ + __asm__ __volatile__( \ + "clz %0,%1" \ + : "=r"(rval) \ + : "r"(arg)); \ + rval; \ + }) + +#define MTCPDC(reg, val) __asm__ __volatile__("dc " #reg ",%0" \ + : \ + : "r"(val)) +#define MTCPIC(reg, val) __asm__ __volatile__("ic " #reg ",%0" \ + : \ + : "r"(val)) + +#define MTCPICALL(reg) __asm__ __volatile__("ic " #reg) +#define MTCPTLBI(reg) __asm__ __volatile__("tlbi " #reg) +#define MTCPAT(reg, val) __asm__ __volatile__("at " #reg ",%0" \ + : \ + : "r"(val)) + +#define AARCH64_READ_SYSREG(reg) ( \ + { \ + uint64_t val; \ + __asm__ __volatile__("mrs %0," #reg \ + : "=r"(val)); \ + val; \ + }) +#define AARCH64_WRITE_SYSREG(reg, val) __asm__ __volatile__("msr " #reg ", %0\n\tdsb sy\n\tisb" ::"r"(val)); + +/* PSTATE and special purpose register access functions */ +uint32_t raw_read_current_el(void); +uint32_t get_current_el(void); +uint32_t raw_read_daif(void); +void raw_write_daif(uint32_t daif); +void enable_debug_exceptions(void); +void enable_serror_exceptions(void); +void enable_irq(void); +void enable_fiq(void); +void disable_debug_exceptions(void); +void disable_serror_exceptions(void); +void disable_irq(void); +void disable_fiq(void); +/* SPSR_EL1, Saved Program Status Register (EL1) */ +uint32_t raw_read_spsr_el1(void); +void raw_write_spsr_el1(uint32_t spsr_el1); +/* ISR_EL1, Interrupt Status Register */ +uint32_t raw_read_isr_el1(void); +uint64_t raw_read_rvbar_el1(void); +void raw_write_rvbar_el1(uint64_t rvbar_el1); +uint64_t raw_read_vbar_el1(void); +void raw_write_vbar_el1(uint64_t vbar_el1); + +/* CNTV_CTL_EL0, Counter-timer Virtual Timer Control register */ +uint32_t raw_read_cntv_ctl(void); +void disable_cntv(void); +void enable_cntv(void); +/* CNTFRQ_EL0, Counter-timer Frequency register */ +uint32_t raw_read_cntfrq_el0(void); +void raw_write_cntfrq_el0(uint32_t cntfrq_el0); +/* CNTVCT_EL0, Counter-timer Virtual Count register */ +uint64_t raw_read_cntvct_el0(void); +/* CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register */ +uint64_t raw_read_cntv_cval_el0(void); +void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0); + +u64 get_hcr_el2(void); +u32 get_esr_el1(void); +#endif // V8_SYSTEM_H diff --git a/bsp/arch/armv8/aarch64/arm-smccc.h b/bsp/arch/armv8/aarch64/arm-smccc.h index 5cedd4113..4f90577e5 100644 --- a/bsp/arch/armv8/aarch64/arm-smccc.h +++ b/bsp/arch/armv8/aarch64/arm-smccc.h @@ -1,106 +1,106 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2015, Linaro Limited - */ -#ifndef __LINUX_ARM_SMCCC_H -#define __LINUX_ARM_SMCCC_H - -/* - * This file provides common defines for ARM SMC Calling Convention as - * specified in - * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html - */ - -#define ARM_SMCCC_STD_CALL 0 -#define ARM_SMCCC_FAST_CALL 1 -#define ARM_SMCCC_TYPE_SHIFT 31 - -#define ARM_SMCCC_SMC_32 0 -#define ARM_SMCCC_SMC_64 1 -#define ARM_SMCCC_CALL_CONV_SHIFT 30 - -#define ARM_SMCCC_OWNER_MASK 0x3F -#define ARM_SMCCC_OWNER_SHIFT 24 - -#define ARM_SMCCC_FUNC_MASK 0xFFFF - -#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ - ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) -#define ARM_SMCCC_IS_64(smc_val) \ - ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) -#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val)&ARM_SMCCC_FUNC_MASK) -#define ARM_SMCCC_OWNER_NUM(smc_val) \ - (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) - -#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ - (((type) << ARM_SMCCC_TYPE_SHIFT) | \ - ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ - (((owner)&ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ - ((func_num)&ARM_SMCCC_FUNC_MASK)) - -#define ARM_SMCCC_OWNER_ARCH 0 -#define ARM_SMCCC_OWNER_CPU 1 -#define ARM_SMCCC_OWNER_SIP 2 -#define ARM_SMCCC_OWNER_OEM 3 -#define ARM_SMCCC_OWNER_STANDARD 4 -#define ARM_SMCCC_OWNER_TRUSTED_APP 48 -#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 -#define ARM_SMCCC_OWNER_TRUSTED_OS 50 -#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 - -#define ARM_SMCCC_QUIRK_NONE 0 -#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ - -#ifndef __ASSEMBLY__ - -#include -/** - * struct arm_smccc_res - Result from SMC/HVC call - * @a0-a3 result values from registers 0 to 3 - */ -struct arm_smccc_res -{ - unsigned long a0; - unsigned long a1; - unsigned long a2; - unsigned long a3; -}; - -/** - * struct arm_smccc_quirk - Contains quirk information - * @id: quirk identification - * @state: quirk specific information - * @a6: Qualcomm quirk entry for returning post-smc call contents of a6 - */ -struct arm_smccc_quirk -{ - int id; - union - { - unsigned long a6; - } state; -}; - -/** - * __arm_smccc_smc() - make SMC calls - * @a0-a7: arguments passed in registers 0 to 7 - * @res: result values from registers 0 to 3 - * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. - * - * This function is used to make SMC calls following SMC Calling Convention. - * The content of the supplied param are copied to registers 0 to 7 prior - * to the SMC instruction. The return values are updated with the content - * from register 0 to 3 on return from the SMC instruction. An optional - * quirk structure provides vendor specific behavior. - */ -void __arm_smccc_smc(unsigned long a0, unsigned long a1, - unsigned long a2, unsigned long a3, unsigned long a4, - unsigned long a5, unsigned long a6, unsigned long a7, - struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); - -#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL) - -#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__) - -#endif /*__ASSEMBLY__*/ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2015, Linaro Limited + */ +#ifndef __LINUX_ARM_SMCCC_H +#define __LINUX_ARM_SMCCC_H + +/* + * This file provides common defines for ARM SMC Calling Convention as + * specified in + * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html + */ + +#define ARM_SMCCC_STD_CALL 0 +#define ARM_SMCCC_FAST_CALL 1 +#define ARM_SMCCC_TYPE_SHIFT 31 + +#define ARM_SMCCC_SMC_32 0 +#define ARM_SMCCC_SMC_64 1 +#define ARM_SMCCC_CALL_CONV_SHIFT 30 + +#define ARM_SMCCC_OWNER_MASK 0x3F +#define ARM_SMCCC_OWNER_SHIFT 24 + +#define ARM_SMCCC_FUNC_MASK 0xFFFF + +#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ + ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) +#define ARM_SMCCC_IS_64(smc_val) \ + ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) +#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val)&ARM_SMCCC_FUNC_MASK) +#define ARM_SMCCC_OWNER_NUM(smc_val) \ + (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) + +#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ + (((type) << ARM_SMCCC_TYPE_SHIFT) | \ + ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ + (((owner)&ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ + ((func_num)&ARM_SMCCC_FUNC_MASK)) + +#define ARM_SMCCC_OWNER_ARCH 0 +#define ARM_SMCCC_OWNER_CPU 1 +#define ARM_SMCCC_OWNER_SIP 2 +#define ARM_SMCCC_OWNER_OEM 3 +#define ARM_SMCCC_OWNER_STANDARD 4 +#define ARM_SMCCC_OWNER_TRUSTED_APP 48 +#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 +#define ARM_SMCCC_OWNER_TRUSTED_OS 50 +#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 + +#define ARM_SMCCC_QUIRK_NONE 0 +#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ + +#ifndef __ASSEMBLY__ + +#include +/** + * struct arm_smccc_res - Result from SMC/HVC call + * @a0-a3 result values from registers 0 to 3 + */ +struct arm_smccc_res +{ + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/** + * struct arm_smccc_quirk - Contains quirk information + * @id: quirk identification + * @state: quirk specific information + * @a6: Qualcomm quirk entry for returning post-smc call contents of a6 + */ +struct arm_smccc_quirk +{ + int id; + union + { + unsigned long a6; + } state; +}; + +/** + * __arm_smccc_smc() - make SMC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. + * + * This function is used to make SMC calls following SMC Calling Convention. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction. An optional + * quirk structure provides vendor specific behavior. + */ +void __arm_smccc_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); + +#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL) + +#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__) + +#endif /*__ASSEMBLY__*/ #endif /*__LINUX_ARM_SMCCC_H*/ \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/cache.c b/bsp/arch/armv8/aarch64/cache.c index 4629d01b8..ed9592cd3 100644 --- a/bsp/arch/armv8/aarch64/cache.c +++ b/bsp/arch/armv8/aarch64/cache.c @@ -1,193 +1,193 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 - * David Feng - * - * (C) Copyright 2016 - * Alexander Graf - */ - -#include -#include -#include -#include -#include -#include "ft_io.h" -#include "cache.h" - -extern int AsmInvaliDateL3dcache(); -extern void __asm_invalidate_dcache_all(); -extern void __asm_invalidate_dcache_range(uint64_t start, uint64_t end); -extern void __asm_flush_dcache_all(); -extern void __asm_flush_dcache_range(uint64_t start, uint64_t end); -extern void __asm_invalidate_icache_all(); -extern void __asm_invalidate_l3_icache(); -extern void __asm_invalidate_tlb_all(); - -/* FLUSH L3 CASHE */ -#ifdef CONFIG_USE_L3CACHE -#define HNF_BASE (unsigned long)(0x3A200000) -#define HNF_COUNT 0x8 -#define HNF_PSTATE_REQ (HNF_BASE + 0x10) -#define HNF_PSTATE_STAT (HNF_BASE + 0x18) -#define HNF_PSTATE_OFF 0x0 -#define HNF_PSTATE_SFONLY 0x1 -#define HNF_PSTATE_HALF 0x2 -#define HNF_PSTATE_FULL 0x3 -#define HNF_STRIDE 0x10000 -#endif - -int AsmFlushL3Dcache(void) -{ - -#ifdef CONFIG_USE_L3CACHE - int i, pstate; - - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); - for (i = 0; i < HNF_COUNT; i++) - { - do - { - pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); - } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); - } - - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); - -#endif - return 0; -} - -int AsmInvaliDateL3dcache(void) -{ -#ifdef CONFIG_USE_L3CACHE - int i, pstate; - - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); - - for (i = 0; i < HNF_COUNT; i++) - { - do - { - pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); - } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); - } - - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); -#endif - return 0; -} - -void DcacheEnable(void) -{ - uint64_t reg; - - reg = AARCH64_READ_SYSREG(sctlr_el1); - - if (!(reg & SCTLR_ELx_C)) - { - DcacheInvalidate(); - __asm_invalidate_tlb_all(); - reg |= SCTLR_ELx_C; - AARCH64_WRITE_SYSREG(sctlr_el1, reg); - } -} - -void DcacheDisable(void) -{ - uint64_t reg; - reg = AARCH64_READ_SYSREG(sctlr_el1); - - if (!(reg & SCTLR_ELx_C)) - return; - - reg &= (~SCTLR_ELx_C); - AARCH64_WRITE_SYSREG(sctlr_el1, reg); - INTERRUPT_DISABLE(); - - __asm_flush_dcache_all(); - -#ifdef CONFIG_USE_L3CACHE - int i, pstate; - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); - for (i = 0; i < HNF_COUNT; i++) - { - do - { - pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); - } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); - } - - for (i = 0; i < HNF_COUNT; i++) - FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); -#endif - - __asm_invalidate_tlb_all(); - INTERRUPT_ENABLE(); -} - -void DcacheInvalidate(void) -{ - INTERRUPT_DISABLE(); - __asm_invalidate_dcache_all(); - AsmInvaliDateL3dcache(); - INTERRUPT_ENABLE(); -} - -void DcacheInvalidateRange(intptr adr, intptr len) -{ - INTERRUPT_DISABLE(); - __asm_invalidate_dcache_range(adr, adr + len); - INTERRUPT_ENABLE(); -} - -void DcacheFlush(void) -{ - INTERRUPT_DISABLE(); - __asm_flush_dcache_all(); - AsmFlushL3Dcache(); - INTERRUPT_ENABLE(); -} - -void DcacheFlushRange(intptr adr, intptr len) -{ - INTERRUPT_DISABLE(); - __asm_flush_dcache_range(adr, adr + len); - INTERRUPT_ENABLE(); -} - -void IcacheEnable(void) -{ - uint64_t reg; - - reg = AARCH64_READ_SYSREG(sctlr_el1); - - if (!(reg & SCTLR_ELx_I)) - { - IcacheInvalidate(); - reg |= SCTLR_ELx_I; - AARCH64_WRITE_SYSREG(sctlr_el1, reg); - } -} - -void IcacheDisable(void) -{ - uint64_t reg; - - reg = AARCH64_READ_SYSREG(sctlr_el1); - reg &= ~SCTLR_ELx_I; - AARCH64_WRITE_SYSREG(sctlr_el1, reg); -} - -void IcacheInvalidate(void) -{ - INTERRUPT_DISABLE(); - __asm_invalidate_icache_all(); - __asm_invalidate_l3_icache(); - INTERRUPT_ENABLE(); +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2016 + * Alexander Graf + */ + +#include +#include +#include +#include +#include +#include "ft_io.h" +#include "cache.h" + +extern int AsmInvaliDateL3dcache(); +extern void __asm_invalidate_dcache_all(); +extern void __asm_invalidate_dcache_range(uint64_t start, uint64_t end); +extern void __asm_flush_dcache_all(); +extern void __asm_flush_dcache_range(uint64_t start, uint64_t end); +extern void __asm_invalidate_icache_all(); +extern void __asm_invalidate_l3_icache(); +extern void __asm_invalidate_tlb_all(); + +/* FLUSH L3 CASHE */ +#ifdef CONFIG_USE_L3CACHE +#define HNF_BASE (unsigned long)(0x3A200000) +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#endif + +int AsmFlushL3Dcache(void) +{ + +#ifdef CONFIG_USE_L3CACHE + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); + for (i = 0; i < HNF_COUNT; i++) + { + do + { + pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); + +#endif + return 0; +} + +int AsmInvaliDateL3dcache(void) +{ +#ifdef CONFIG_USE_L3CACHE + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); + + for (i = 0; i < HNF_COUNT; i++) + { + do + { + pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); +#endif + return 0; +} + +void DcacheEnable(void) +{ + uint64_t reg; + + reg = AARCH64_READ_SYSREG(sctlr_el1); + + if (!(reg & SCTLR_ELx_C)) + { + DcacheInvalidate(); + __asm_invalidate_tlb_all(); + reg |= SCTLR_ELx_C; + AARCH64_WRITE_SYSREG(sctlr_el1, reg); + } +} + +void DcacheDisable(void) +{ + uint64_t reg; + reg = AARCH64_READ_SYSREG(sctlr_el1); + + if (!(reg & SCTLR_ELx_C)) + return; + + reg &= (~SCTLR_ELx_C); + AARCH64_WRITE_SYSREG(sctlr_el1, reg); + INTERRUPT_DISABLE(); + + __asm_flush_dcache_all(); + +#ifdef CONFIG_USE_L3CACHE + int i, pstate; + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); + for (i = 0; i < HNF_COUNT; i++) + { + do + { + pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); +#endif + + __asm_invalidate_tlb_all(); + INTERRUPT_ENABLE(); +} + +void DcacheInvalidate(void) +{ + INTERRUPT_DISABLE(); + __asm_invalidate_dcache_all(); + AsmInvaliDateL3dcache(); + INTERRUPT_ENABLE(); +} + +void DcacheInvalidateRange(intptr adr, intptr len) +{ + INTERRUPT_DISABLE(); + __asm_invalidate_dcache_range(adr, adr + len); + INTERRUPT_ENABLE(); +} + +void DcacheFlush(void) +{ + INTERRUPT_DISABLE(); + __asm_flush_dcache_all(); + AsmFlushL3Dcache(); + INTERRUPT_ENABLE(); +} + +void DcacheFlushRange(intptr adr, intptr len) +{ + INTERRUPT_DISABLE(); + __asm_flush_dcache_range(adr, adr + len); + INTERRUPT_ENABLE(); +} + +void IcacheEnable(void) +{ + uint64_t reg; + + reg = AARCH64_READ_SYSREG(sctlr_el1); + + if (!(reg & SCTLR_ELx_I)) + { + IcacheInvalidate(); + reg |= SCTLR_ELx_I; + AARCH64_WRITE_SYSREG(sctlr_el1, reg); + } +} + +void IcacheDisable(void) +{ + uint64_t reg; + + reg = AARCH64_READ_SYSREG(sctlr_el1); + reg &= ~SCTLR_ELx_I; + AARCH64_WRITE_SYSREG(sctlr_el1, reg); +} + +void IcacheInvalidate(void) +{ + INTERRUPT_DISABLE(); + __asm_invalidate_icache_all(); + __asm_invalidate_l3_icache(); + INTERRUPT_ENABLE(); } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/cache.h b/bsp/arch/armv8/aarch64/cache.h index cea36cd86..2d0c3afd1 100644 --- a/bsp/arch/armv8/aarch64/cache.h +++ b/bsp/arch/armv8/aarch64/cache.h @@ -1,56 +1,56 @@ -#ifndef BSP_ARCH_AARCH64_CACHE_H -#define BSP_ARCH_AARCH64_CACHE_H - -#include "ft_types.h" - -/************************************************************** - * - * MMU Define - * - * *************************************************************/ - -/* Memory type */ -#define NORM_NONCACHE 0x401 /* normal non-cacheable */ -#define STRONG_ORDERED 0x409 /* stronly ordered (Device-nGnRnE) */ -#define DEVICE_MEMORY 0x40D /* device memory (Device-nGnRE) */ -#define RESERVED 0X00 /* reserved memory */ - -/* normal write-through cacheable inner shareable */ -#define NORM_WT_CACHE 0x711 - -/* normal write back cacheable inner-shareable */ -#define NORM_WB_CACHE 0x705 - -/* - * shareability arrtibute only applicable to - * normal cacheable memory - */ -#define INNER_SHAREABLE (0x3 << 8) -#define OUTER_SHAREABLE (0x2 << 8) -#define NON_SHAREABLE (~(0x3 << 8)) - -/* execution type */ -#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54)) - -/* secure type */ -#define NON_SECURE (0x1 << 5) - -/************************************************************** - * - * Cache Define - * - * *************************************************************/ - -/************************** Function Prototypes ******************************/ -void DcacheEnable(void); -void DcacheDisable(void); -void DcacheInvalidate(void); -void DcacheInvalidateRange(intptr adr, intptr len); -void DcacheFlush(void); -void DcacheFlushRange(intptr adr, intptr len); - -void IcacheEnable(void); -void IcacheDisable(void); -void IcacheInvalidate(void); - +#ifndef BSP_ARCH_AARCH64_CACHE_H +#define BSP_ARCH_AARCH64_CACHE_H + +#include "ft_types.h" + +/************************************************************** + * + * MMU Define + * + * *************************************************************/ + +/* Memory type */ +#define NORM_NONCACHE 0x401 /* normal non-cacheable */ +#define STRONG_ORDERED 0x409 /* stronly ordered (Device-nGnRnE) */ +#define DEVICE_MEMORY 0x40D /* device memory (Device-nGnRE) */ +#define RESERVED 0X00 /* reserved memory */ + +/* normal write-through cacheable inner shareable */ +#define NORM_WT_CACHE 0x711 + +/* normal write back cacheable inner-shareable */ +#define NORM_WB_CACHE 0x705 + +/* + * shareability arrtibute only applicable to + * normal cacheable memory + */ +#define INNER_SHAREABLE (0x3 << 8) +#define OUTER_SHAREABLE (0x2 << 8) +#define NON_SHAREABLE (~(0x3 << 8)) + +/* execution type */ +#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54)) + +/* secure type */ +#define NON_SECURE (0x1 << 5) + +/************************************************************** + * + * Cache Define + * + * *************************************************************/ + +/************************** Function Prototypes ******************************/ +void DcacheEnable(void); +void DcacheDisable(void); +void DcacheInvalidate(void); +void DcacheInvalidateRange(intptr adr, intptr len); +void DcacheFlush(void); +void DcacheFlushRange(intptr adr, intptr len); + +void IcacheEnable(void); +void IcacheDisable(void); +void IcacheInvalidate(void); + #endif \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/exception.c b/bsp/arch/armv8/aarch64/exception.c index cd9fa4b2a..323d0606a 100644 --- a/bsp/arch/armv8/aarch64/exception.c +++ b/bsp/arch/armv8/aarch64/exception.c @@ -1,32 +1,32 @@ -#include "exception.h" -#include "ft_types.h" -#include - -_WEAK void SystemIrqHandler(exception_frame *exc) -{ -} - -_WEAK void SerrHandle(exception_frame *exc) -{ - while (1) - { - } -} - -_WEAK void common_trap_handler(exception_frame *exc) -{ - printf("exc_type %x \r\n ", exc->exc_type); - if ((exc->exc_type & 0xff) == AARCH64_EXC_SYNC_SPX) - { - printf("AARCH64_EXC_SYNC_SPX)\r\n"); - SerrHandle(exc); - } - - if ((exc->exc_type & 0xff) == AARCH64_EXC_IRQ_SPX) - { - printf("AARCH64_EXC_IRQ_SPX)\r\n"); - SystemIrqHandler(exc); - } - - return; -} +#include "exception.h" +#include "ft_types.h" +#include + +_WEAK void SystemIrqHandler(exception_frame *exc) +{ +} + +_WEAK void SerrHandle(exception_frame *exc) +{ + while (1) + { + } +} + +_WEAK void common_trap_handler(exception_frame *exc) +{ + printf("exc_type %x \r\n ", exc->exc_type); + if ((exc->exc_type & 0xff) == AARCH64_EXC_SYNC_SPX) + { + printf("AARCH64_EXC_SYNC_SPX)\r\n"); + SerrHandle(exc); + } + + if ((exc->exc_type & 0xff) == AARCH64_EXC_IRQ_SPX) + { + printf("AARCH64_EXC_IRQ_SPX)\r\n"); + SystemIrqHandler(exc); + } + + return; +} diff --git a/bsp/arch/armv8/aarch64/exception.h b/bsp/arch/armv8/aarch64/exception.h index 77136bdf9..883eb4433 100644 --- a/bsp/arch/armv8/aarch64/exception.h +++ b/bsp/arch/armv8/aarch64/exception.h @@ -1,106 +1,106 @@ -/* -*- mode: asm; coding:utf-8 -*- */ -/************************************************************************/ -/* OS kernel sample */ -/* Copyright 2014 Takeharu KATO */ -/* */ -/************************************************************************/ - -#if !defined(_EXCEPTION_H) -#define _EXCEPTION_H - -/* Vector Table - * see 5.1.1 Setting up a vector table in - * Application Note Bare-metal Boot Code for ARMv8-A Processors Version 1.0 - */ - -/* - * AArch64 exception types - */ -/* Current EL with SP0 */ -#define AARCH64_EXC_SYNC_SP0 (0x1) /* Synchronous */ -#define AARCH64_EXC_IRQ_SP0 (0x2) /* IRQ/vIRQ */ -#define AARCH64_EXC_FIQ_SP0 (0x3) /* FIQ/vFIQ */ -#define AARCH64_EXC_SERR_SP0 (0x4) /* SError/vSError */ -/* Current EL with SPx */ -#define AARCH64_EXC_SYNC_SPX (0x11) -#define AARCH64_EXC_IRQ_SPX (0x12) -#define AARCH64_EXC_FIQ_SPX (0x13) -#define AARCH64_EXC_SERR_SPX (0x14) -/* Lower EL using AArch64 */ -#define AARCH64_EXC_SYNC_AARCH64 (0x21) -#define AARCH64_EXC_IRQ_AARCH64 (0x22) -#define AARCH64_EXC_FIQ_AARCH64 (0x23) -#define AARCH64_EXC_SERR_AARCH64 (0x24) -/* Lower EL using AArch32 */ -#define AARCH64_EXC_SYNC_AARCH32 (0x31) -#define AARCH64_EXC_IRQ_AARCH32 (0x32) -#define AARCH64_EXC_FIQ_AARCH32 (0x33) -#define AARCH64_EXC_SERR_AARCH32 (0x34) - -#if defined(ASM_FILE) -#define vector_table_align .align 11 /* Vector tables must be placed at a 2KB-aligned address */ -#define vector_entry_align .align 7 /* Each entry is 128B in size*/ -#define text_align .align 2 /* Text alignment */ -#endif /* ASM_FILE */ - -/* - * exception_frame offset definitions - */ -#define EXC_FRAME_SIZE (288) /* sizeof(struct _exception_frame) */ -#define EXC_EXC_TYPE_OFFSET (0) /* __asm_offsetof(struct _exception_frame, exc_type) */ -#define EXC_EXC_ESR_OFFSET (8) /* __asm_offsetof(struct _exception_frame, exc_esr) */ -#define EXC_EXC_SP_OFFSET (16) /* __asm_offsetof(struct _exception_frame, exc_sp) */ -#define EXC_EXC_ELR_OFFSET (24) /* __asm_offsetof(struct _exception_frame, exc_elr) */ -#define EXC_EXC_SPSR_OFFSET (32) /* __asm_offsetof(struct _exception_frame, exc_spsr) */ - -/* - * IRQ - */ -#define IRQ_FOUND (0) -#define IRQ_NOT_FOUND (1) - -#if !defined(ASM_FILE) -#include -typedef struct _exception_frame -{ - uint64_t exc_type; - uint64_t exc_esr; - uint64_t exc_sp; - uint64_t exc_elr; - uint64_t exc_spsr; - uint64_t x0; - uint64_t x1; - uint64_t x2; - uint64_t x3; - uint64_t x4; - uint64_t x5; - uint64_t x6; - uint64_t x7; - uint64_t x8; - uint64_t x9; - uint64_t x10; - uint64_t x11; - uint64_t x12; - uint64_t x13; - uint64_t x14; - uint64_t x15; - uint64_t x16; - uint64_t x17; - uint64_t x18; - uint64_t x19; - uint64_t x20; - uint64_t x21; - uint64_t x22; - uint64_t x23; - uint64_t x24; - uint64_t x25; - uint64_t x26; - uint64_t x27; - uint64_t x28; - uint64_t x29; - uint64_t x30; -} exception_frame; - -void common_trap_handler(exception_frame *_exc); -#endif /* !ASM_FILE */ -#endif /* _EXCEPTION_H */ +/* -*- mode: asm; coding:utf-8 -*- */ +/************************************************************************/ +/* OS kernel sample */ +/* Copyright 2014 Takeharu KATO */ +/* */ +/************************************************************************/ + +#if !defined(_EXCEPTION_H) +#define _EXCEPTION_H + +/* Vector Table + * see 5.1.1 Setting up a vector table in + * Application Note Bare-metal Boot Code for ARMv8-A Processors Version 1.0 + */ + +/* + * AArch64 exception types + */ +/* Current EL with SP0 */ +#define AARCH64_EXC_SYNC_SP0 (0x1) /* Synchronous */ +#define AARCH64_EXC_IRQ_SP0 (0x2) /* IRQ/vIRQ */ +#define AARCH64_EXC_FIQ_SP0 (0x3) /* FIQ/vFIQ */ +#define AARCH64_EXC_SERR_SP0 (0x4) /* SError/vSError */ +/* Current EL with SPx */ +#define AARCH64_EXC_SYNC_SPX (0x11) +#define AARCH64_EXC_IRQ_SPX (0x12) +#define AARCH64_EXC_FIQ_SPX (0x13) +#define AARCH64_EXC_SERR_SPX (0x14) +/* Lower EL using AArch64 */ +#define AARCH64_EXC_SYNC_AARCH64 (0x21) +#define AARCH64_EXC_IRQ_AARCH64 (0x22) +#define AARCH64_EXC_FIQ_AARCH64 (0x23) +#define AARCH64_EXC_SERR_AARCH64 (0x24) +/* Lower EL using AArch32 */ +#define AARCH64_EXC_SYNC_AARCH32 (0x31) +#define AARCH64_EXC_IRQ_AARCH32 (0x32) +#define AARCH64_EXC_FIQ_AARCH32 (0x33) +#define AARCH64_EXC_SERR_AARCH32 (0x34) + +#if defined(ASM_FILE) +#define vector_table_align .align 11 /* Vector tables must be placed at a 2KB-aligned address */ +#define vector_entry_align .align 7 /* Each entry is 128B in size*/ +#define text_align .align 2 /* Text alignment */ +#endif /* ASM_FILE */ + +/* + * exception_frame offset definitions + */ +#define EXC_FRAME_SIZE (288) /* sizeof(struct _exception_frame) */ +#define EXC_EXC_TYPE_OFFSET (0) /* __asm_offsetof(struct _exception_frame, exc_type) */ +#define EXC_EXC_ESR_OFFSET (8) /* __asm_offsetof(struct _exception_frame, exc_esr) */ +#define EXC_EXC_SP_OFFSET (16) /* __asm_offsetof(struct _exception_frame, exc_sp) */ +#define EXC_EXC_ELR_OFFSET (24) /* __asm_offsetof(struct _exception_frame, exc_elr) */ +#define EXC_EXC_SPSR_OFFSET (32) /* __asm_offsetof(struct _exception_frame, exc_spsr) */ + +/* + * IRQ + */ +#define IRQ_FOUND (0) +#define IRQ_NOT_FOUND (1) + +#if !defined(ASM_FILE) +#include +typedef struct _exception_frame +{ + uint64_t exc_type; + uint64_t exc_esr; + uint64_t exc_sp; + uint64_t exc_elr; + uint64_t exc_spsr; + uint64_t x0; + uint64_t x1; + uint64_t x2; + uint64_t x3; + uint64_t x4; + uint64_t x5; + uint64_t x6; + uint64_t x7; + uint64_t x8; + uint64_t x9; + uint64_t x10; + uint64_t x11; + uint64_t x12; + uint64_t x13; + uint64_t x14; + uint64_t x15; + uint64_t x16; + uint64_t x17; + uint64_t x18; + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; + uint64_t x30; +} exception_frame; + +void common_trap_handler(exception_frame *_exc); +#endif /* !ASM_FILE */ +#endif /* _EXCEPTION_H */ diff --git a/bsp/arch/armv8/aarch64/fsleep.c b/bsp/arch/armv8/aarch64/fsleep.c index 11f126ffa..17c74492c 100644 --- a/bsp/arch/armv8/aarch64/fsleep.c +++ b/bsp/arch/armv8/aarch64/fsleep.c @@ -1,35 +1,35 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-28 08:48:36 - * @LastEditTime: 2021-07-01 17:39:58 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "fsleep.h" -#include "generic_timer.h" -#include "parameters.h" -#include "ft_types.h" -#include - -u32 fsleep_seconds(u32 seconds) -{ - u64 end_time; - u64 cur_time; - GenericTimerStart(); - cur_time = GenericTimerRead(); - end_time = cur_time + ((u64)seconds * GenericTimerFrequecy()); - printf("%d \r\n", GenericTimerFrequecy()); - do - { - cur_time = GenericTimerRead(); - } while (cur_time < end_time); - - return 0; +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-28 08:48:36 + * @LastEditTime: 2021-07-01 17:39:58 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "fsleep.h" +#include "generic_timer.h" +#include "parameters.h" +#include "ft_types.h" +#include + +u32 fsleep_seconds(u32 seconds) +{ + u64 end_time; + u64 cur_time; + GenericTimerStart(); + cur_time = GenericTimerRead(); + end_time = cur_time + ((u64)seconds * GenericTimerFrequecy()); + printf("%d \r\n", GenericTimerFrequecy()); + do + { + cur_time = GenericTimerRead(); + } while (cur_time < end_time); + + return 0; } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/fsleep.h b/bsp/arch/armv8/aarch64/fsleep.h index 5edc9ce94..e0665eb14 100644 --- a/bsp/arch/armv8/aarch64/fsleep.h +++ b/bsp/arch/armv8/aarch64/fsleep.h @@ -1,22 +1,22 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-28 08:48:40 - * @LastEditTime: 2021-05-28 09:28:55 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _BSP_ARCH_ARMV8_FSLEEP_H -#define _BSP_ARCH_ARMV8_FSLEEP_H - -#include "ft_types.h" - -u32 fsleep_seconds(u32 seconds); - +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-28 08:48:40 + * @LastEditTime: 2021-05-28 09:28:55 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _BSP_ARCH_ARMV8_FSLEEP_H +#define _BSP_ARCH_ARMV8_FSLEEP_H + +#include "ft_types.h" + +u32 fsleep_seconds(u32 seconds); + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/gcc/_uart_test.c b/bsp/arch/armv8/aarch64/gcc/_uart_test.c index eef36994c..3fa6b98b4 100644 --- a/bsp/arch/armv8/aarch64/gcc/_uart_test.c +++ b/bsp/arch/armv8/aarch64/gcc/_uart_test.c @@ -1,80 +1,80 @@ -#include "ft_types.h" -#include "ft_io.h" -#include "aarch64.h" -#include - -extern void OutByte(s8 byte); - -u32 raw_read_cpacr_el1(void) -{ - u32 cpacr_el1; - - __asm__ __volatile__("mrs %0, cpacr_el1\n\t" - : "=r"(cpacr_el1) - : - : "memory"); - - return cpacr_el1; -} - -void reg_check(void) -{ - printf("cpacr_el1 %x \r\n", raw_read_cpacr_el1()); - while (1) - { - /* code */ - } -} - -void hcr_el2_printf(void) -{ - printf("hcr_el2 %x \r\n", get_hcr_el2()); - while (1) - { - /* code */ - } -} - -void print_xregs(u64 x0, u64 x1, u64 x2) -{ - printf("x0 %x \r\n", x0); - printf("x1 %x \r\n", x1); - printf("x2 %x \r\n", x2); -} - -void asm_pos_print(void) -{ - OutByte('2'); - OutByte('3'); - OutByte('3'); - OutByte('\n'); -} - -void asnyc_error_print(void) -{ - OutByte('a'); - OutByte('s'); - OutByte('s'); - OutByte('e'); - OutByte('\n'); - - while (1) - { - /* code */ - } -} - -void check_error_print(void) -{ - OutByte('c'); - OutByte('h'); - OutByte('e'); - OutByte('c'); - OutByte('k'); - OutByte('\n'); - - while (1) - { - /* code */ - } -} +#include "ft_types.h" +#include "ft_io.h" +#include "aarch64.h" +#include + +extern void OutByte(s8 byte); + +u32 raw_read_cpacr_el1(void) +{ + u32 cpacr_el1; + + __asm__ __volatile__("mrs %0, cpacr_el1\n\t" + : "=r"(cpacr_el1) + : + : "memory"); + + return cpacr_el1; +} + +void reg_check(void) +{ + printf("cpacr_el1 %x \r\n", raw_read_cpacr_el1()); + while (1) + { + /* code */ + } +} + +void hcr_el2_printf(void) +{ + printf("hcr_el2 %x \r\n", get_hcr_el2()); + while (1) + { + /* code */ + } +} + +void print_xregs(u64 x0, u64 x1, u64 x2) +{ + printf("x0 %x \r\n", x0); + printf("x1 %x \r\n", x1); + printf("x2 %x \r\n", x2); +} + +void asm_pos_print(void) +{ + OutByte('2'); + OutByte('3'); + OutByte('3'); + OutByte('\n'); +} + +void asnyc_error_print(void) +{ + OutByte('a'); + OutByte('s'); + OutByte('s'); + OutByte('e'); + OutByte('\n'); + + while (1) + { + /* code */ + } +} + +void check_error_print(void) +{ + OutByte('c'); + OutByte('h'); + OutByte('e'); + OutByte('c'); + OutByte('k'); + OutByte('\n'); + + while (1) + { + /* code */ + } +} diff --git a/bsp/arch/armv8/aarch64/gcc/cache.S b/bsp/arch/armv8/aarch64/gcc/cache.S index d1b95f276..7fe0df688 100644 --- a/bsp/arch/armv8/aarch64/gcc/cache.S +++ b/bsp/arch/armv8/aarch64/gcc/cache.S @@ -1,264 +1,264 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * David Feng - * - * This file is based on sample code from ARMv8 ARM. - */ - -#include -#include - -/* - * void __asm_dcache_level(level) - * - * flush or invalidate one level cache. - * - * x0: cache level - * x1: 0 clean & invalidate, 1 invalidate only - * x2~x9: clobbered - */ -.pushsection .text.__asm_dcache_level, "ax" -ENTRY(__asm_dcache_level) - lsl x12, x0, #1 - msr csselr_el1, x12 /* select cache level */ - isb /* sync change of cssidr_el1 */ - mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ - and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ - add x2, x2, #4 /* x2 <- log2(cache line size) */ - mov x3, #0x3ff - and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ - clz w5, w3 /* bit position of #ways */ - mov x4, #0x7fff - and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ - /* x12 <- cache level << 1 */ - /* x2 <- line length offset */ - /* x3 <- number of cache ways - 1 */ - /* x4 <- number of cache sets - 1 */ - /* x5 <- bit position of #ways */ - -loop_set: - mov x6, x3 /* x6 <- working copy of #ways */ -loop_way: - lsl x7, x6, x5 - orr x9, x12, x7 /* map way and level to cisw value */ - lsl x7, x4, x2 - orr x9, x9, x7 /* map set number to cisw value */ - tbz w1, #0, 1f - dc isw, x9 - b 2f -1: dc cisw, x9 /* clean & invalidate by set/way */ -2: subs x6, x6, #1 /* decrement the way */ - b.ge loop_way - subs x4, x4, #1 /* decrement the set */ - b.ge loop_set - - ret -ENDPROC(__asm_dcache_level) -.popsection - -/* - * void __asm_flush_dcache_all(int invalidate_only) - * - * x0: 0 clean & invalidate, 1 invalidate only - * - * flush or invalidate all data cache by SET/WAY. - */ -.pushsection .text.__asm_dcache_all, "ax" -ENTRY(__asm_dcache_all) - mov x1, x0 - dsb sy - mrs x10, clidr_el1 /* read clidr_el1 */ - lsr x11, x10, #24 - and x11, x11, #0x7 /* x11 <- loc */ - cbz x11, finished /* if loc is 0, exit */ - mov x15, lr - mov x0, #0 /* start flush at cache level 0 */ - /* x0 <- cache level */ - /* x10 <- clidr_el1 */ - /* x11 <- loc */ - /* x15 <- return address */ - -loop_level: - lsl x12, x0, #1 - add x12, x12, x0 /* x0 <- tripled cache level */ - lsr x12, x10, x12 - and x12, x12, #7 /* x12 <- cache type */ - cmp x12, #2 - b.lt skip /* skip if no cache or icache */ - bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ -skip: - add x0, x0, #1 /* increment cache level */ - cmp x11, x0 - b.gt loop_level - - mov x0, #0 - msr csselr_el1, x0 /* restore csselr_el1 */ - dsb sy - isb - mov lr, x15 - -finished: - ret -ENDPROC(__asm_dcache_all) -.popsection - -.pushsection .text.__asm_flush_dcache_all, "ax" -ENTRY(__asm_flush_dcache_all) - mov x0, #0 - b __asm_dcache_all -ENDPROC(__asm_flush_dcache_all) -.popsection - -.pushsection .text.__asm_invalidate_dcache_all, "ax" -ENTRY(__asm_invalidate_dcache_all) - mov x0, #0x1 - b __asm_dcache_all -ENDPROC(__asm_invalidate_dcache_all) -.popsection - -/* - * void __asm_flush_dcache_range(start, end) - * - * clean & invalidate data cache in the range - * - * x0: start address - * x1: end address - */ -.pushsection .text.__asm_flush_dcache_range, "ax" -ENTRY(__asm_flush_dcache_range) - mrs x3, ctr_el0 - lsr x3, x3, #16 - and x3, x3, #0xf - mov x2, #4 - lsl x2, x2, x3 /* cache line size */ - - /* x2 <- minimal cache line size in cache system */ - sub x3, x2, #1 - bic x0, x0, x3 -1: dc civac, x0 /* clean & invalidate data or unified cache */ - add x0, x0, x2 - cmp x0, x1 - b.lo 1b - dsb sy - ret -ENDPROC(__asm_flush_dcache_range) -.popsection -/* - * void __asm_invalidate_dcache_range(start, end) - * - * invalidate data cache in the range - * - * x0: start address - * x1: end address - */ -.pushsection .text.__asm_invalidate_dcache_range, "ax" -ENTRY(__asm_invalidate_dcache_range) - mrs x3, ctr_el0 - ubfm x3, x3, #16, #19 - mov x2, #4 - lsl x2, x2, x3 /* cache line size */ - - /* x2 <- minimal cache line size in cache system */ - sub x3, x2, #1 - bic x0, x0, x3 -1: dc ivac, x0 /* invalidate data or unified cache */ - add x0, x0, x2 - cmp x0, x1 - b.lo 1b - dsb sy - ret -ENDPROC(__asm_invalidate_dcache_range) -.popsection - -/* - * void __asm_invalidate_icache_all(void) - * - * invalidate all tlb entries. - */ -.pushsection .text.__asm_invalidate_icache_all, "ax" -ENTRY(__asm_invalidate_icache_all) - ic ialluis - isb sy - ret -ENDPROC(__asm_invalidate_icache_all) -.popsection - -.pushsection .text.AsmInvaliDateL3dcache, "ax" -ENTRY(AsmInvaliDateL3dcache) - mov x0, #0 /* return status as success */ - ret -ENDPROC(AsmInvaliDateL3dcache) - .weak AsmInvaliDateL3dcache -.popsection - -.pushsection .text.AsmFlushL3Dcache, "ax" -ENTRY(AsmFlushL3Dcache) - mov x0, #0 /* return status as success */ - ret -ENDPROC(AsmFlushL3Dcache) - .weak AsmFlushL3Dcache -.popsection - -.pushsection .text.__asm_invalidate_l3_icache, "ax" -ENTRY(__asm_invalidate_l3_icache) - mov x0, #0 /* return status as success */ - ret -ENDPROC(__asm_invalidate_l3_icache) - .weak __asm_invalidate_l3_icache -.popsection - -/* - * void __asm_switch_ttbr(ulong new_ttbr) - * - * Safely switches to a new page table. - */ -.pushsection .text.__asm_switch_ttbr, "ax" -ENTRY(__asm_switch_ttbr) - /* x2 = SCTLR (alive throghout the function) */ - switch_el x4, 3f, 2f, 1f -3: mrs x2, sctlr_el3 - b 0f -2: mrs x2, sctlr_el2 - b 0f -1: mrs x2, sctlr_el1 -0: - - /* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */ - movn x1, #(1<<0 | 1<<2 | 1<<12) - and x1, x2, x1 - switch_el x4, 3f, 2f, 1f -3: msr sctlr_el3, x1 - b 0f -2: msr sctlr_el2, x1 - b 0f -1: msr sctlr_el1, x1 -0: isb - - /* This call only clobbers x30 (lr) and x9 (unused) */ - mov x3, x30 - bl __asm_invalidate_tlb_all - - /* From here on we're running safely with caches disabled */ - - /* Set TTBR to our first argument */ - switch_el x4, 3f, 2f, 1f -3: msr ttbr0_el3, x0 - b 0f -2: msr ttbr0_el2, x0 - b 0f -1: msr ttbr0_el1, x0 -0: isb - - /* Restore original SCTLR and thus enable caches again */ - switch_el x4, 3f, 2f, 1f -3: msr sctlr_el3, x2 - b 0f -2: msr sctlr_el2, x2 - b 0f -1: msr sctlr_el1, x2 -0: isb - - ret x3 -ENDPROC(__asm_switch_ttbr) -.popsection +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2013 + * David Feng + * + * This file is based on sample code from ARMv8 ARM. + */ + +#include +#include + +/* + * void __asm_dcache_level(level) + * + * flush or invalidate one level cache. + * + * x0: cache level + * x1: 0 clean & invalidate, 1 invalidate only + * x2~x9: clobbered + */ +.pushsection .text.__asm_dcache_level, "ax" +ENTRY(__asm_dcache_level) + lsl x12, x0, #1 + msr csselr_el1, x12 /* select cache level */ + isb /* sync change of cssidr_el1 */ + mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ + and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ + add x2, x2, #4 /* x2 <- log2(cache line size) */ + mov x3, #0x3ff + and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ + clz w5, w3 /* bit position of #ways */ + mov x4, #0x7fff + and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ + /* x12 <- cache level << 1 */ + /* x2 <- line length offset */ + /* x3 <- number of cache ways - 1 */ + /* x4 <- number of cache sets - 1 */ + /* x5 <- bit position of #ways */ + +loop_set: + mov x6, x3 /* x6 <- working copy of #ways */ +loop_way: + lsl x7, x6, x5 + orr x9, x12, x7 /* map way and level to cisw value */ + lsl x7, x4, x2 + orr x9, x9, x7 /* map set number to cisw value */ + tbz w1, #0, 1f + dc isw, x9 + b 2f +1: dc cisw, x9 /* clean & invalidate by set/way */ +2: subs x6, x6, #1 /* decrement the way */ + b.ge loop_way + subs x4, x4, #1 /* decrement the set */ + b.ge loop_set + + ret +ENDPROC(__asm_dcache_level) +.popsection + +/* + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 clean & invalidate, 1 invalidate only + * + * flush or invalidate all data cache by SET/WAY. + */ +.pushsection .text.__asm_dcache_all, "ax" +ENTRY(__asm_dcache_all) + mov x1, x0 + dsb sy + mrs x10, clidr_el1 /* read clidr_el1 */ + lsr x11, x10, #24 + and x11, x11, #0x7 /* x11 <- loc */ + cbz x11, finished /* if loc is 0, exit */ + mov x15, lr + mov x0, #0 /* start flush at cache level 0 */ + /* x0 <- cache level */ + /* x10 <- clidr_el1 */ + /* x11 <- loc */ + /* x15 <- return address */ + +loop_level: + lsl x12, x0, #1 + add x12, x12, x0 /* x0 <- tripled cache level */ + lsr x12, x10, x12 + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 + b.lt skip /* skip if no cache or icache */ + bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ +skip: + add x0, x0, #1 /* increment cache level */ + cmp x11, x0 + b.gt loop_level + + mov x0, #0 + msr csselr_el1, x0 /* restore csselr_el1 */ + dsb sy + isb + mov lr, x15 + +finished: + ret +ENDPROC(__asm_dcache_all) +.popsection + +.pushsection .text.__asm_flush_dcache_all, "ax" +ENTRY(__asm_flush_dcache_all) + mov x0, #0 + b __asm_dcache_all +ENDPROC(__asm_flush_dcache_all) +.popsection + +.pushsection .text.__asm_invalidate_dcache_all, "ax" +ENTRY(__asm_invalidate_dcache_all) + mov x0, #0x1 + b __asm_dcache_all +ENDPROC(__asm_invalidate_dcache_all) +.popsection + +/* + * void __asm_flush_dcache_range(start, end) + * + * clean & invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +.pushsection .text.__asm_flush_dcache_range, "ax" +ENTRY(__asm_flush_dcache_range) + mrs x3, ctr_el0 + lsr x3, x3, #16 + and x3, x3, #0xf + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc civac, x0 /* clean & invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret +ENDPROC(__asm_flush_dcache_range) +.popsection +/* + * void __asm_invalidate_dcache_range(start, end) + * + * invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +.pushsection .text.__asm_invalidate_dcache_range, "ax" +ENTRY(__asm_invalidate_dcache_range) + mrs x3, ctr_el0 + ubfm x3, x3, #16, #19 + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc ivac, x0 /* invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret +ENDPROC(__asm_invalidate_dcache_range) +.popsection + +/* + * void __asm_invalidate_icache_all(void) + * + * invalidate all tlb entries. + */ +.pushsection .text.__asm_invalidate_icache_all, "ax" +ENTRY(__asm_invalidate_icache_all) + ic ialluis + isb sy + ret +ENDPROC(__asm_invalidate_icache_all) +.popsection + +.pushsection .text.AsmInvaliDateL3dcache, "ax" +ENTRY(AsmInvaliDateL3dcache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(AsmInvaliDateL3dcache) + .weak AsmInvaliDateL3dcache +.popsection + +.pushsection .text.AsmFlushL3Dcache, "ax" +ENTRY(AsmFlushL3Dcache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(AsmFlushL3Dcache) + .weak AsmFlushL3Dcache +.popsection + +.pushsection .text.__asm_invalidate_l3_icache, "ax" +ENTRY(__asm_invalidate_l3_icache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_invalidate_l3_icache) + .weak __asm_invalidate_l3_icache +.popsection + +/* + * void __asm_switch_ttbr(ulong new_ttbr) + * + * Safely switches to a new page table. + */ +.pushsection .text.__asm_switch_ttbr, "ax" +ENTRY(__asm_switch_ttbr) + /* x2 = SCTLR (alive throghout the function) */ + switch_el x4, 3f, 2f, 1f +3: mrs x2, sctlr_el3 + b 0f +2: mrs x2, sctlr_el2 + b 0f +1: mrs x2, sctlr_el1 +0: + + /* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */ + movn x1, #(1<<0 | 1<<2 | 1<<12) + and x1, x2, x1 + switch_el x4, 3f, 2f, 1f +3: msr sctlr_el3, x1 + b 0f +2: msr sctlr_el2, x1 + b 0f +1: msr sctlr_el1, x1 +0: isb + + /* This call only clobbers x30 (lr) and x9 (unused) */ + mov x3, x30 + bl __asm_invalidate_tlb_all + + /* From here on we're running safely with caches disabled */ + + /* Set TTBR to our first argument */ + switch_el x4, 3f, 2f, 1f +3: msr ttbr0_el3, x0 + b 0f +2: msr ttbr0_el2, x0 + b 0f +1: msr ttbr0_el1, x0 +0: isb + + /* Restore original SCTLR and thus enable caches again */ + switch_el x4, 3f, 2f, 1f +3: msr sctlr_el3, x2 + b 0f +2: msr sctlr_el2, x2 + b 0f +1: msr sctlr_el1, x2 +0: isb + + ret x3 +ENDPROC(__asm_switch_ttbr) +.popsection diff --git a/bsp/arch/armv8/aarch64/gcc/smccc-call.S b/bsp/arch/armv8/aarch64/gcc/smccc-call.S index da83893af..71c9200c3 100644 --- a/bsp/arch/armv8/aarch64/gcc/smccc-call.S +++ b/bsp/arch/armv8/aarch64/gcc/smccc-call.S @@ -1,26 +1,26 @@ -.macro SMCCC instr - \instr #0 - ldr x4, [sp] - stp x0, x1, [x4, #0] - stp x2, x3, [x4, #16] - ldr x4, [sp, #8] - cbz x4, 1f /* no quirk structure */ - ldr x9, [x4, #0] - cmp x9, #1 - b.ne 1f - str x6, [x4, 4] -1: ret -.endm SMCCC instr - -/* - * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, - * unsigned long a3, unsigned long a4, unsigned long a5, - * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, - * struct arm_smccc_quirk *quirk) - */ - .globl __arm_smccc_smc -.type __arm_smccc_smc, "function" - .cfi_startproc -__arm_smccc_smc: - SMCCC smc - .cfi_endproc +.macro SMCCC instr + \instr #0 + ldr x4, [sp] + stp x0, x1, [x4, #0] + stp x2, x3, [x4, #16] + ldr x4, [sp, #8] + cbz x4, 1f /* no quirk structure */ + ldr x9, [x4, #0] + cmp x9, #1 + b.ne 1f + str x6, [x4, 4] +1: ret +.endm SMCCC instr + +/* + * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, + * unsigned long a3, unsigned long a4, unsigned long a5, + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, + * struct arm_smccc_quirk *quirk) + */ + .globl __arm_smccc_smc +.type __arm_smccc_smc, "function" + .cfi_startproc +__arm_smccc_smc: + SMCCC smc + .cfi_endproc diff --git a/bsp/arch/armv8/aarch64/gcc/start.S b/bsp/arch/armv8/aarch64/gcc/start.S index a87ec1db4..3c7ac1608 100644 --- a/bsp/arch/armv8/aarch64/gcc/start.S +++ b/bsp/arch/armv8/aarch64/gcc/start.S @@ -1,142 +1,142 @@ -/* - * Branch according to exception level - */ -#include "macro.h" -#include "sdkconfig.h" - -.section StartUp, "ax" -.section .vectors -.globl _boot -.global _boot -.type _boot, "function" -_boot: - mrs x0, CurrentEL - cmp x0, 0xc - b.eq el3_entry - cmp x0, 0x8 - b.eq el2_entry - cmp x0, 0x4 - b.eq el1_entry - bne hang -el3_entry: - // initialize sctlr_el2 and hcr_el2 to save values before entering el2. - msr sctlr_el2, xzr - msr hcr_el2, xzr - // determine the el2 execution state. - mrs x0, scr_el3 - orr x0, x0, #(1<<10) // rw el2 execution state is aarch64. - orr x0, x0, #(1<<0) // ns el1 is non-secure world. - msr scr_el3, x0 - mov x0, #0b01001 // daif=0000 - msr spsr_el3, x0 // m[4:0]=01001 el2h must match scr_el3.rw - // determine el2 entry. - adr x0, el2_entry // el2_entry points to the first instruction of - msr elr_el3, x0 // el2 code. - eret -el2_entry: - // initialize the sctlr_el1 register before entering el1. - msr sctlr_el1, xzr - mrs x0, hcr_el2 - orr x0, x0, #(1<<31) // rw=1 el1 execution state is aarch64. - msr hcr_el2, x0 - mov x0, #0b00101 // daif=0000 - msr spsr_el2, x0 // m[4:0]=00101 el1h must match hcr_el2.rw. - adr x0, el1_entry // el1_entry points to the first instruction of - msr elr_el2, x0 // el1 code. - eret -el1_entry: - adr x0, _vector_table - msr vbar_el1, x0 - mov x0, #3 << 20 - msr cpacr_el1, x0 /* Enable FP/SIMD */ - /* check CPU ID = 0x0, or jump to hang */ - mrs x0, mpidr_el1 - and x0, x0, #3 - cmp x0, #0 - bne hang - -master_cpu: - mov x1,#0x0 - orr x1, x1, #(1 << 18) // ; Set WFE non trapping - orr x1, x1, #(1 << 17) // ; Set WFI non trapping - orr x1, x1, #(1 << 5) // ; Set CP15 barrier enabled - msr SCTLR_EL1, x1 - isb - - msr DAIFclr, 0xF - /* configure stack */ - adrp x0, stack_top // Address of 4KB page at a PC-relative offset -magic_label: // Why do we need this label to let GDB step continually? - mov sp, x0 // sp = stack_top (align with 4KB page) - - /* Start copying data */ - ldr x0, =_rom_end - ldr x1, =__data_start - ldr x2, =__data_end - -data_loop: - cmp x1, x2 - ldp x10, x11, [x0], #16 /* copy from source address [x1] */ - stp x10, x11, [x1], #16 /* copy to target address [x0] */ - blt data_loop - - /* clear bss. */ - ldr x1, =__bss_start__ /* A 64-bit general-purpose register named X0 to X30 */ - ldr w2, =__bss_size /* A 32-bit general-purpose register named W0 to W30 */ -1: cbz w2, 2f /* Compare and Branch on Zero */ - str xzr, [x1], #8 - sub w2, w2, #1 - cbnz w2, 1b - -#ifdef CONFIG_USE_LIBC - // Set up _fini and fini_array to be called at exit - ldr x0, =__libc_fini_array - bl atexit - // Call preinit_array, _init and init_array - bl __libc_init_array -#endif - -#ifdef CONFIG_USE_CACHE -TLBI VMALLE1 //; TLBI VMALLE1, TLB Invalidate by VMID, All at stage 1, EL1 -ic IALLU //; Invalidate I cache to PoU - -#ifdef CONFIG_USE_MMU -bl MmuInit -#endif -bl DcacheInvalidate - -// Enable caches and the MMU. -MRS X0, SCTLR_EL1 -ORR X0, X0, #(0x1 << 2) // The C bit (data cache). -ORR X0, X0, #(0x1 << 12) // The I bit (instruction cache). -#ifdef CONFIG_USE_MMU -ORR X0, X0, #0x1 // The M bit (MMU). -#endif -MSR SCTLR_EL1, X0 -DSB SY -ISB - -dsb ish // ensure all previous stores have completed before invalidating -ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) -dsb ish // ensure completion on inner shareable domain (which includes secondary cores) -isb - -#endif - -#ifdef CONFIG_USE_LIBC - // Set up the standard file handles - bl initialise_monitor_handles -#endif -2: - bl main - -hang: - wfi - b hang - - - - - - -# ========================================= +/* + * Branch according to exception level + */ +#include "macro.h" +#include "sdkconfig.h" + +.section StartUp, "ax" +.section .vectors +.globl _boot +.global _boot +.type _boot, "function" +_boot: + mrs x0, CurrentEL + cmp x0, 0xc + b.eq el3_entry + cmp x0, 0x8 + b.eq el2_entry + cmp x0, 0x4 + b.eq el1_entry + bne hang +el3_entry: + // initialize sctlr_el2 and hcr_el2 to save values before entering el2. + msr sctlr_el2, xzr + msr hcr_el2, xzr + // determine the el2 execution state. + mrs x0, scr_el3 + orr x0, x0, #(1<<10) // rw el2 execution state is aarch64. + orr x0, x0, #(1<<0) // ns el1 is non-secure world. + msr scr_el3, x0 + mov x0, #0b01001 // daif=0000 + msr spsr_el3, x0 // m[4:0]=01001 el2h must match scr_el3.rw + // determine el2 entry. + adr x0, el2_entry // el2_entry points to the first instruction of + msr elr_el3, x0 // el2 code. + eret +el2_entry: + // initialize the sctlr_el1 register before entering el1. + msr sctlr_el1, xzr + mrs x0, hcr_el2 + orr x0, x0, #(1<<31) // rw=1 el1 execution state is aarch64. + msr hcr_el2, x0 + mov x0, #0b00101 // daif=0000 + msr spsr_el2, x0 // m[4:0]=00101 el1h must match hcr_el2.rw. + adr x0, el1_entry // el1_entry points to the first instruction of + msr elr_el2, x0 // el1 code. + eret +el1_entry: + adr x0, _vector_table + msr vbar_el1, x0 + mov x0, #3 << 20 + msr cpacr_el1, x0 /* Enable FP/SIMD */ + /* check CPU ID = 0x0, or jump to hang */ + mrs x0, mpidr_el1 + and x0, x0, #3 + cmp x0, #0 + bne hang + +master_cpu: + mov x1,#0x0 + orr x1, x1, #(1 << 18) // ; Set WFE non trapping + orr x1, x1, #(1 << 17) // ; Set WFI non trapping + orr x1, x1, #(1 << 5) // ; Set CP15 barrier enabled + msr SCTLR_EL1, x1 + isb + + msr DAIFclr, 0xF + /* configure stack */ + adrp x0, stack_top // Address of 4KB page at a PC-relative offset +magic_label: // Why do we need this label to let GDB step continually? + mov sp, x0 // sp = stack_top (align with 4KB page) + + /* Start copying data */ + ldr x0, =_rom_end + ldr x1, =__data_start + ldr x2, =__data_end + +data_loop: + cmp x1, x2 + ldp x10, x11, [x0], #16 /* copy from source address [x1] */ + stp x10, x11, [x1], #16 /* copy to target address [x0] */ + blt data_loop + + /* clear bss. */ + ldr x1, =__bss_start__ /* A 64-bit general-purpose register named X0 to X30 */ + ldr w2, =__bss_size /* A 32-bit general-purpose register named W0 to W30 */ +1: cbz w2, 2f /* Compare and Branch on Zero */ + str xzr, [x1], #8 + sub w2, w2, #1 + cbnz w2, 1b + +#ifdef CONFIG_USE_LIBC + // Set up _fini and fini_array to be called at exit + ldr x0, =__libc_fini_array + bl atexit + // Call preinit_array, _init and init_array + bl __libc_init_array +#endif + +#ifdef CONFIG_USE_CACHE +TLBI VMALLE1 //; TLBI VMALLE1, TLB Invalidate by VMID, All at stage 1, EL1 +ic IALLU //; Invalidate I cache to PoU + +#ifdef CONFIG_USE_MMU +bl MmuInit +#endif +bl DcacheInvalidate + +// Enable caches and the MMU. +MRS X0, SCTLR_EL1 +ORR X0, X0, #(0x1 << 2) // The C bit (data cache). +ORR X0, X0, #(0x1 << 12) // The I bit (instruction cache). +#ifdef CONFIG_USE_MMU +ORR X0, X0, #0x1 // The M bit (MMU). +#endif +MSR SCTLR_EL1, X0 +DSB SY +ISB + +dsb ish // ensure all previous stores have completed before invalidating +ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) +dsb ish // ensure completion on inner shareable domain (which includes secondary cores) +isb + +#endif + +#ifdef CONFIG_USE_LIBC + // Set up the standard file handles + bl initialise_monitor_handles +#endif +2: + bl main + +hang: + wfi + b hang + + + + + + +# ========================================= diff --git a/bsp/arch/armv8/aarch64/gcc/tlb.S b/bsp/arch/armv8/aarch64/gcc/tlb.S index de37c9f6e..ffceecfbf 100644 --- a/bsp/arch/armv8/aarch64/gcc/tlb.S +++ b/bsp/arch/armv8/aarch64/gcc/tlb.S @@ -1,26 +1,26 @@ -#include -#include - -/* - * void __asm_invalidate_tlb_all(void) - * - * invalidate all tlb entries. -*/ -.pushsection .text.__asm_invalidate_tlb_all, "ax" -ENTRY(__asm_invalidate_tlb_all) - switch_el x9, 3f, 2f, 1f -3: tlbi alle3 - dsb sy - isb - b 0f -2: tlbi alle2 - dsb sy - isb - b 0f -1: tlbi vmalle1 - dsb sy - isb -0: - ret -ENDPROC(__asm_invalidate_tlb_all) -.popsection +#include +#include + +/* + * void __asm_invalidate_tlb_all(void) + * + * invalidate all tlb entries. +*/ +.pushsection .text.__asm_invalidate_tlb_all, "ax" +ENTRY(__asm_invalidate_tlb_all) + switch_el x9, 3f, 2f, 1f +3: tlbi alle3 + dsb sy + isb + b 0f +2: tlbi alle2 + dsb sy + isb + b 0f +1: tlbi vmalle1 + dsb sy + isb +0: + ret +ENDPROC(__asm_invalidate_tlb_all) +.popsection diff --git a/bsp/arch/armv8/aarch64/gcc/vector.S b/bsp/arch/armv8/aarch64/gcc/vector.S index 59a4bffd3..c44dab5f1 100644 --- a/bsp/arch/armv8/aarch64/gcc/vector.S +++ b/bsp/arch/armv8/aarch64/gcc/vector.S @@ -1,445 +1,445 @@ -/* -*- mode: asm; coding:utf-8 -*- */ -/************************************************************************/ -/* OS kernel sample */ -/* Copyright 2014 Takeharu KATO */ -/* */ -/* Exception vector */ -/* */ -/************************************************************************/ -#define ASM_FILE 1 - -#include "exception.h" -#include "sdkconfig.h" - -.section ".text.boot" - - -.globl _boot -.globl _vector_table -.globl _freertos_vector_table - - -.macro saveregister - stp X0,X1, [sp,#-0x10]! - stp X2,X3, [sp,#-0x10]! - stp X4,X5, [sp,#-0x10]! - stp X6,X7, [sp,#-0x10]! - stp X8,X9, [sp,#-0x10]! - stp X10,X11, [sp,#-0x10]! - stp X12,X13, [sp,#-0x10]! - stp X14,X15, [sp,#-0x10]! - stp X16,X17, [sp,#-0x10]! - stp X18,X19, [sp,#-0x10]! - stp X29,X30, [sp,#-0x10]! - - mrs x0, CPACR_EL1 - mrs x1, ELR_EL1 - mrs x2, SPSR_EL1 - stp x0, x1, [sp,#-0x10]! - str x2, [sp,#-0x10]! -.endm - -.macro savefloatregister - -/* Save all the floating point register to the stack */ - stp q0,q1, [sp, #-0x20]! - stp q2,q3, [sp, #-0x20]! - stp q4,q5, [sp, #-0x20]! - stp q6,q7, [sp, #-0x20]! - stp q8,q9, [sp, #-0x20]! - stp q10,q11, [sp, #-0x20]! - stp q12,q13, [sp, #-0x20]! - stp q14,q15, [sp, #-0x20]! - stp q16,q17, [sp, #-0x20]! - stp q18,q19, [sp, #-0x20]! - stp q20,q21, [sp, #-0x20]! - stp q22,q23, [sp, #-0x20]! - stp q24,q25, [sp, #-0x20]! - stp q26,q27, [sp, #-0x20]! - stp q28,q29, [sp, #-0x20]! - stp q30,q31, [sp, #-0x20]! - mrs x2, FPCR - mrs x3, FPSR - stp x2, x3, [sp, #-0x10]! -.endm - -.macro restorefloatregister - -/* Restore all the floating point register from the stack */ - ldp x2, x3, [sp] ,#0x10 - msr FPCR, x2 - msr FPSR, x3 - - ldp q30,q31, [sp] ,#0x20 - ldp q28,q29, [sp] ,#0x20 - ldp q26,q27, [sp] ,#0x20 - ldp q24,q25, [sp] ,#0x20 - ldp q22,q23, [sp] ,#0x20 - ldp q20,q21, [sp] ,#0x20 - ldp q18,q19, [sp] ,#0x20 - ldp q16,q17, [sp] ,#0x20 - ldp q14,q15, [sp] ,#0x20 - ldp q12,q13, [sp] ,#0x20 - ldp q10,q11, [sp] ,#0x20 - ldp q8,q9, [sp] ,#0x20 - ldp q6,q7, [sp] ,#0x20 - ldp q4,q5, [sp] ,#0x20 - ldp q2,q3, [sp] ,#0x20 - ldp q0,q1, [sp] ,#0x20 -.endm - -.macro build_trapframe exc_type - /* - * store generic registers from (x29,x30) pair to (x1,x2) pair. - */ - stp x29, x30, [sp, #-16]! - stp x27, x28, [sp, #-16]! - stp x25, x26, [sp, #-16]! - stp x23, x24, [sp, #-16]! - stp x21, x22, [sp, #-16]! - stp x19, x20, [sp, #-16]! - stp x17, x18, [sp, #-16]! - stp x15, x16, [sp, #-16]! - stp x13, x14, [sp, #-16]! - stp x11, x12, [sp, #-16]! - stp x9, x10, [sp, #-16]! - stp x7, x8, [sp, #-16]! - stp x5, x6, [sp, #-16]! - stp x3, x4, [sp, #-16]! - stp x1, x2, [sp, #-16]! - - savefloatregister - - /* - * Store (spsr, x0) - */ - mrs x21, spsr_el1 - stp x21, x0, [sp, #-16]! - /* - * Allocate a room for sp_el0 and store elr - */ - mrs x21, elr_el1 - stp xzr, x21, [sp, #-16]! - /* - * store exception type and esr - */ - mov x21, #(\exc_type) - mrs x22, esr_el1 - stp x21, x22, [sp, #-16]! -.endm - -.macro store_traped_sp - mrs x21, sp_el0 - str x21, [sp, #EXC_EXC_SP_OFFSET] -.endm - - - -.macro call_common_trap_handler - mov x0, sp - bl common_trap_handler -.endm - -.macro store_nested_sp - mov x21, sp - add x21, x21, #EXC_FRAME_SIZE - str x21, [sp, #EXC_EXC_SP_OFFSET] -.endm - -.macro restore_traped_sp - ldr x21, [sp, #EXC_EXC_SP_OFFSET] - msr sp_el0, x21 -.endm - -.macro restore_trapframe - - /* - * Drop exception type, esr, - */ - add sp, sp, #16 - /* - * Drop exception stack pointer and restore elr_el1 - */ - ldp x21, x22, [sp], #16 - msr elr_el1, x22 - - /* - * Retore spsr and x0 - */ - ldp x21, x0, [sp], #16 - msr spsr_el1, x21 - - restorefloatregister - - /* - * Restore generic registers from (x29,x30) pair to (x1,x2) pair. - */ - ldp x1, x2, [sp], #16 - ldp x3, x4, [sp], #16 - ldp x5, x6, [sp], #16 - ldp x7, x8, [sp], #16 - ldp x9, x10, [sp], #16 - ldp x11, x12, [sp], #16 - ldp x13, x14, [sp], #16 - ldp x15, x16, [sp], #16 - ldp x17, x18, [sp], #16 - ldp x19, x20, [sp], #16 - ldp x21, x22, [sp], #16 - ldp x23, x24, [sp], #16 - ldp x25, x26, [sp], #16 - ldp x27, x28, [sp], #16 - ldp x29, x30, [sp], #16 - - eret -.endm - - -/* - * Exception vectors. -*/ -.balign 2048 -_vector_table: - -.set VBAR, _vector_table - - -/* - * Current EL with SP0 - */ -.org VBAR - /* b _boot */ - b _curr_el_sp0_sync /* Synchronous */ -.org (VBAR + 0x80) - b _curr_el_sp0_irq /* IRQ/vIRQ */ -.org (VBAR + 0x100) - b _curr_el_sp0_fiq /* FIQ/vFIQ */ -.org (VBAR + 0x180) - b _curr_el_sp0_serror /* SError/vSError */ - - /* - * Current EL with SPx - */ -.org (VBAR + 0x200) - b _curr_el_spx_sync /* Synchronous */ -.org (VBAR + 0x280) - b _curr_el_spx_irq /* IRQ/vIRQ */ -.org (VBAR + 0x300) - b _curr_el_spx_fiq /* FIQ/vFIQ */ -.org (VBAR + 0x380) - b _curr_el_spx_serror /* SError/vSError */ - - /* - * Lower EL using AArch64 - */ -.org (VBAR + 0x400) - b _lower_el_aarch64_sync -.org (VBAR + 0x480) - b _lower_el_aarch64_irq -.org (VBAR + 0x500) - b _lower_el_aarch64_fiq -.org (VBAR + 0x580) - b _lower_el_aarch64_serror - - /* - * Lower EL using AArch32 - */ -.org (VBAR + 0x600) - b _lower_el_aarch32_sync -.org (VBAR + 0x680) - b _lower_el_aarch32_irq -.org (VBAR + 0x700) - b _lower_el_aarch32_fiq -.org (VBAR + 0x780) - b _lower_el_aarch32_serror - - text_align -_curr_el_sp0_sync: - build_trapframe AARCH64_EXC_SYNC_SP0 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_curr_el_sp0_irq: - build_trapframe AARCH64_EXC_IRQ_SP0 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_curr_el_sp0_fiq: - build_trapframe AARCH64_EXC_FIQ_SP0 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_curr_el_sp0_serror: - build_trapframe AARCH64_EXC_SERR_SP0 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - - text_align -_curr_el_spx_sync: - build_trapframe AARCH64_EXC_SYNC_SPX - store_nested_sp - call_common_trap_handler - restore_trapframe - - text_align -_curr_el_spx_irq: - build_trapframe AARCH64_EXC_IRQ_SPX - store_nested_sp - call_common_trap_handler - restore_trapframe - - text_align -_curr_el_spx_fiq: - build_trapframe AARCH64_EXC_FIQ_SPX - store_nested_sp - call_common_trap_handler - restore_trapframe - - text_align -_curr_el_spx_serror: - build_trapframe AARCH64_EXC_SERR_SPX - store_nested_sp - call_common_trap_handler - restore_trapframe - - - text_align -_lower_el_aarch64_sync: - build_trapframe AARCH64_EXC_SYNC_AARCH64 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch64_irq: - build_trapframe AARCH64_EXC_IRQ_AARCH64 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch64_fiq: - build_trapframe AARCH64_EXC_FIQ_AARCH64 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch64_serror: - build_trapframe AARCH64_EXC_SERR_AARCH64 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - - text_align -_lower_el_aarch32_sync: - build_trapframe AARCH64_EXC_SYNC_AARCH32 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch32_irq: - build_trapframe AARCH64_EXC_IRQ_AARCH32 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch32_fiq: - build_trapframe AARCH64_EXC_FIQ_AARCH32 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - text_align -_lower_el_aarch32_serror: - build_trapframe AARCH64_EXC_SERR_AARCH32 - store_traped_sp - call_common_trap_handler - restore_traped_sp - restore_trapframe - - -/****************************************************************************** - * Vector table to use when FreeRTOS is running. - *****************************************************************************/ - -#ifdef CONFIG_USE_FREERTOS - -.set FREERTOS_VBAR, (VBAR+0x2000) - -.org(FREERTOS_VBAR) -_freertos_vector_table: - b FreeRTOS_SWI_Handler - -.org (FREERTOS_VBAR + 0x80) - b FreeRTOS_IRQ_Handler - -.org (FREERTOS_VBAR + 0x100) - b . - -.org (FREERTOS_VBAR + 0x180) - b . - -.org (FREERTOS_VBAR + 0x200) - b FreeRTOS_SWI_Handler - -.org (FREERTOS_VBAR + 0x280) - b FreeRTOS_IRQ_Handler - -.org (FREERTOS_VBAR + 0x300) - b . - -.org (FREERTOS_VBAR + 0x380) - b _curr_el_spx_serror /* SError/vSError */ - -.org (FREERTOS_VBAR + 0x400) - b . - -.org (FREERTOS_VBAR + 0x480) - b . - -.org (FREERTOS_VBAR + 0x500) - b . - -.org (FREERTOS_VBAR + 0x580) - b . - -.org (FREERTOS_VBAR + 0x600) - b . - -.org (FREERTOS_VBAR + 0x680) - b . - -.org (FREERTOS_VBAR + 0x700) - b . - -.org (FREERTOS_VBAR + 0x780) - b . - -.org (FREERTOS_VBAR + 0x800) - - -#endif - -.end +/* -*- mode: asm; coding:utf-8 -*- */ +/************************************************************************/ +/* OS kernel sample */ +/* Copyright 2014 Takeharu KATO */ +/* */ +/* Exception vector */ +/* */ +/************************************************************************/ +#define ASM_FILE 1 + +#include "exception.h" +#include "sdkconfig.h" + +.section ".text.boot" + + +.globl _boot +.globl _vector_table +.globl _freertos_vector_table + + +.macro saveregister + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! + + mrs x0, CPACR_EL1 + mrs x1, ELR_EL1 + mrs x2, SPSR_EL1 + stp x0, x1, [sp,#-0x10]! + str x2, [sp,#-0x10]! +.endm + +.macro savefloatregister + +/* Save all the floating point register to the stack */ + stp q0,q1, [sp, #-0x20]! + stp q2,q3, [sp, #-0x20]! + stp q4,q5, [sp, #-0x20]! + stp q6,q7, [sp, #-0x20]! + stp q8,q9, [sp, #-0x20]! + stp q10,q11, [sp, #-0x20]! + stp q12,q13, [sp, #-0x20]! + stp q14,q15, [sp, #-0x20]! + stp q16,q17, [sp, #-0x20]! + stp q18,q19, [sp, #-0x20]! + stp q20,q21, [sp, #-0x20]! + stp q22,q23, [sp, #-0x20]! + stp q24,q25, [sp, #-0x20]! + stp q26,q27, [sp, #-0x20]! + stp q28,q29, [sp, #-0x20]! + stp q30,q31, [sp, #-0x20]! + mrs x2, FPCR + mrs x3, FPSR + stp x2, x3, [sp, #-0x10]! +.endm + +.macro restorefloatregister + +/* Restore all the floating point register from the stack */ + ldp x2, x3, [sp] ,#0x10 + msr FPCR, x2 + msr FPSR, x3 + + ldp q30,q31, [sp] ,#0x20 + ldp q28,q29, [sp] ,#0x20 + ldp q26,q27, [sp] ,#0x20 + ldp q24,q25, [sp] ,#0x20 + ldp q22,q23, [sp] ,#0x20 + ldp q20,q21, [sp] ,#0x20 + ldp q18,q19, [sp] ,#0x20 + ldp q16,q17, [sp] ,#0x20 + ldp q14,q15, [sp] ,#0x20 + ldp q12,q13, [sp] ,#0x20 + ldp q10,q11, [sp] ,#0x20 + ldp q8,q9, [sp] ,#0x20 + ldp q6,q7, [sp] ,#0x20 + ldp q4,q5, [sp] ,#0x20 + ldp q2,q3, [sp] ,#0x20 + ldp q0,q1, [sp] ,#0x20 +.endm + +.macro build_trapframe exc_type + /* + * store generic registers from (x29,x30) pair to (x1,x2) pair. + */ + stp x29, x30, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + stp x17, x18, [sp, #-16]! + stp x15, x16, [sp, #-16]! + stp x13, x14, [sp, #-16]! + stp x11, x12, [sp, #-16]! + stp x9, x10, [sp, #-16]! + stp x7, x8, [sp, #-16]! + stp x5, x6, [sp, #-16]! + stp x3, x4, [sp, #-16]! + stp x1, x2, [sp, #-16]! + + savefloatregister + + /* + * Store (spsr, x0) + */ + mrs x21, spsr_el1 + stp x21, x0, [sp, #-16]! + /* + * Allocate a room for sp_el0 and store elr + */ + mrs x21, elr_el1 + stp xzr, x21, [sp, #-16]! + /* + * store exception type and esr + */ + mov x21, #(\exc_type) + mrs x22, esr_el1 + stp x21, x22, [sp, #-16]! +.endm + +.macro store_traped_sp + mrs x21, sp_el0 + str x21, [sp, #EXC_EXC_SP_OFFSET] +.endm + + + +.macro call_common_trap_handler + mov x0, sp + bl common_trap_handler +.endm + +.macro store_nested_sp + mov x21, sp + add x21, x21, #EXC_FRAME_SIZE + str x21, [sp, #EXC_EXC_SP_OFFSET] +.endm + +.macro restore_traped_sp + ldr x21, [sp, #EXC_EXC_SP_OFFSET] + msr sp_el0, x21 +.endm + +.macro restore_trapframe + + /* + * Drop exception type, esr, + */ + add sp, sp, #16 + /* + * Drop exception stack pointer and restore elr_el1 + */ + ldp x21, x22, [sp], #16 + msr elr_el1, x22 + + /* + * Retore spsr and x0 + */ + ldp x21, x0, [sp], #16 + msr spsr_el1, x21 + + restorefloatregister + + /* + * Restore generic registers from (x29,x30) pair to (x1,x2) pair. + */ + ldp x1, x2, [sp], #16 + ldp x3, x4, [sp], #16 + ldp x5, x6, [sp], #16 + ldp x7, x8, [sp], #16 + ldp x9, x10, [sp], #16 + ldp x11, x12, [sp], #16 + ldp x13, x14, [sp], #16 + ldp x15, x16, [sp], #16 + ldp x17, x18, [sp], #16 + ldp x19, x20, [sp], #16 + ldp x21, x22, [sp], #16 + ldp x23, x24, [sp], #16 + ldp x25, x26, [sp], #16 + ldp x27, x28, [sp], #16 + ldp x29, x30, [sp], #16 + + eret +.endm + + +/* + * Exception vectors. +*/ +.balign 2048 +_vector_table: + +.set VBAR, _vector_table + + +/* + * Current EL with SP0 + */ +.org VBAR + /* b _boot */ + b _curr_el_sp0_sync /* Synchronous */ +.org (VBAR + 0x80) + b _curr_el_sp0_irq /* IRQ/vIRQ */ +.org (VBAR + 0x100) + b _curr_el_sp0_fiq /* FIQ/vFIQ */ +.org (VBAR + 0x180) + b _curr_el_sp0_serror /* SError/vSError */ + + /* + * Current EL with SPx + */ +.org (VBAR + 0x200) + b _curr_el_spx_sync /* Synchronous */ +.org (VBAR + 0x280) + b _curr_el_spx_irq /* IRQ/vIRQ */ +.org (VBAR + 0x300) + b _curr_el_spx_fiq /* FIQ/vFIQ */ +.org (VBAR + 0x380) + b _curr_el_spx_serror /* SError/vSError */ + + /* + * Lower EL using AArch64 + */ +.org (VBAR + 0x400) + b _lower_el_aarch64_sync +.org (VBAR + 0x480) + b _lower_el_aarch64_irq +.org (VBAR + 0x500) + b _lower_el_aarch64_fiq +.org (VBAR + 0x580) + b _lower_el_aarch64_serror + + /* + * Lower EL using AArch32 + */ +.org (VBAR + 0x600) + b _lower_el_aarch32_sync +.org (VBAR + 0x680) + b _lower_el_aarch32_irq +.org (VBAR + 0x700) + b _lower_el_aarch32_fiq +.org (VBAR + 0x780) + b _lower_el_aarch32_serror + + text_align +_curr_el_sp0_sync: + build_trapframe AARCH64_EXC_SYNC_SP0 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_curr_el_sp0_irq: + build_trapframe AARCH64_EXC_IRQ_SP0 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_curr_el_sp0_fiq: + build_trapframe AARCH64_EXC_FIQ_SP0 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_curr_el_sp0_serror: + build_trapframe AARCH64_EXC_SERR_SP0 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + + text_align +_curr_el_spx_sync: + build_trapframe AARCH64_EXC_SYNC_SPX + store_nested_sp + call_common_trap_handler + restore_trapframe + + text_align +_curr_el_spx_irq: + build_trapframe AARCH64_EXC_IRQ_SPX + store_nested_sp + call_common_trap_handler + restore_trapframe + + text_align +_curr_el_spx_fiq: + build_trapframe AARCH64_EXC_FIQ_SPX + store_nested_sp + call_common_trap_handler + restore_trapframe + + text_align +_curr_el_spx_serror: + build_trapframe AARCH64_EXC_SERR_SPX + store_nested_sp + call_common_trap_handler + restore_trapframe + + + text_align +_lower_el_aarch64_sync: + build_trapframe AARCH64_EXC_SYNC_AARCH64 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch64_irq: + build_trapframe AARCH64_EXC_IRQ_AARCH64 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch64_fiq: + build_trapframe AARCH64_EXC_FIQ_AARCH64 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch64_serror: + build_trapframe AARCH64_EXC_SERR_AARCH64 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + + text_align +_lower_el_aarch32_sync: + build_trapframe AARCH64_EXC_SYNC_AARCH32 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch32_irq: + build_trapframe AARCH64_EXC_IRQ_AARCH32 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch32_fiq: + build_trapframe AARCH64_EXC_FIQ_AARCH32 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + text_align +_lower_el_aarch32_serror: + build_trapframe AARCH64_EXC_SERR_AARCH32 + store_traped_sp + call_common_trap_handler + restore_traped_sp + restore_trapframe + + +/****************************************************************************** + * Vector table to use when FreeRTOS is running. + *****************************************************************************/ + +#ifdef CONFIG_USE_FREERTOS + +.set FREERTOS_VBAR, (VBAR+0x2000) + +.org(FREERTOS_VBAR) +_freertos_vector_table: + b FreeRTOS_SWI_Handler + +.org (FREERTOS_VBAR + 0x80) + b FreeRTOS_IRQ_Handler + +.org (FREERTOS_VBAR + 0x100) + b . + +.org (FREERTOS_VBAR + 0x180) + b . + +.org (FREERTOS_VBAR + 0x200) + b FreeRTOS_SWI_Handler + +.org (FREERTOS_VBAR + 0x280) + b FreeRTOS_IRQ_Handler + +.org (FREERTOS_VBAR + 0x300) + b . + +.org (FREERTOS_VBAR + 0x380) + b _curr_el_spx_serror /* SError/vSError */ + +.org (FREERTOS_VBAR + 0x400) + b . + +.org (FREERTOS_VBAR + 0x480) + b . + +.org (FREERTOS_VBAR + 0x500) + b . + +.org (FREERTOS_VBAR + 0x580) + b . + +.org (FREERTOS_VBAR + 0x600) + b . + +.org (FREERTOS_VBAR + 0x680) + b . + +.org (FREERTOS_VBAR + 0x700) + b . + +.org (FREERTOS_VBAR + 0x780) + b . + +.org (FREERTOS_VBAR + 0x800) + + +#endif + +.end diff --git a/bsp/arch/armv8/aarch64/generic_timer.c b/bsp/arch/armv8/aarch64/generic_timer.c index d024923b8..7b207c013 100644 --- a/bsp/arch/armv8/aarch64/generic_timer.c +++ b/bsp/arch/armv8/aarch64/generic_timer.c @@ -1,61 +1,61 @@ -#include "generic_timer.h" -#include "aarch64.h" - -void GenericTimerStart(void) -{ - u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); - - if (!(ctrl & (1 << 0))) - { - ctrl |= (1 << 0); - AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); - // printf("GenericTimerStart \r\n"); - } -} - -void GenericTimerStop(void) -{ - u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); - if ((ctrl & (1 << 0))) - { - ctrl &= ~(1 << 0); - AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); - } -} - -void GenericTimerInterruptEnable(void) -{ - u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); - // printf(" TimerInterruptEnable ctrl is %x \r\n", ctrl); - if (ctrl & (1 << 1)) - { - ctrl &= ~(1 << 1); - AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); - } -} - -void GenericTimerInterruptDisable(void) -{ - u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); - if (!(ctrl & (1 << 1))) - { - ctrl |= (1 << 1); - AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); - } -} - -u64 GenericTimerFrequecy(void) -{ - u64 rate = AARCH64_READ_SYSREG(cntfrq_el0); - return (rate != 0) ? rate : 1000000; -} - -u64 GenericTimerRead(void) -{ - return AARCH64_READ_SYSREG(cntpct_el0); -} - -void GenericTimerCompare(u64 interval) -{ - AARCH64_WRITE_SYSREG(cntp_tval_el0, interval); -} +#include "generic_timer.h" +#include "aarch64.h" + +void GenericTimerStart(void) +{ + u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); + + if (!(ctrl & (1 << 0))) + { + ctrl |= (1 << 0); + AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); + // printf("GenericTimerStart \r\n"); + } +} + +void GenericTimerStop(void) +{ + u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); + if ((ctrl & (1 << 0))) + { + ctrl &= ~(1 << 0); + AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); + } +} + +void GenericTimerInterruptEnable(void) +{ + u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); + // printf(" TimerInterruptEnable ctrl is %x \r\n", ctrl); + if (ctrl & (1 << 1)) + { + ctrl &= ~(1 << 1); + AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); + } +} + +void GenericTimerInterruptDisable(void) +{ + u64 ctrl = AARCH64_READ_SYSREG(cntp_ctl_el0); + if (!(ctrl & (1 << 1))) + { + ctrl |= (1 << 1); + AARCH64_WRITE_SYSREG(cntp_ctl_el0, ctrl); + } +} + +u64 GenericTimerFrequecy(void) +{ + u64 rate = AARCH64_READ_SYSREG(cntfrq_el0); + return (rate != 0) ? rate : 1000000; +} + +u64 GenericTimerRead(void) +{ + return AARCH64_READ_SYSREG(cntpct_el0); +} + +void GenericTimerCompare(u64 interval) +{ + AARCH64_WRITE_SYSREG(cntp_tval_el0, interval); +} diff --git a/bsp/arch/armv8/aarch64/generic_timer.h b/bsp/arch/armv8/aarch64/generic_timer.h index 684978f80..160ec40aa 100644 --- a/bsp/arch/armv8/aarch64/generic_timer.h +++ b/bsp/arch/armv8/aarch64/generic_timer.h @@ -1,29 +1,29 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_GENERIC_TIMER_H -#define BSP_ARCH_ARMV8_AARCH64_GENERIC_TIMER_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - void GenericTimerStart(void); - - void GenericTimerStop(void); - - void GenericTimerInterruptEnable(void); - - void GenericTimerInterruptDisable(void); - - u64 GenericTimerFrequecy(void); - - u64 GenericTimerRead(void); - - void GenericTimerCompare(u64 interval); - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_GENERIC_TIMER_H +#define BSP_ARCH_ARMV8_AARCH64_GENERIC_TIMER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + void GenericTimerStart(void); + + void GenericTimerStop(void); + + void GenericTimerInterruptEnable(void); + + void GenericTimerInterruptDisable(void); + + u64 GenericTimerFrequecy(void); + + u64 GenericTimerRead(void); + + void GenericTimerCompare(u64 interval); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/mmu.c b/bsp/arch/armv8/aarch64/mmu.c index 3cc9bf2f3..220cb45a9 100644 --- a/bsp/arch/armv8/aarch64/mmu.c +++ b/bsp/arch/armv8/aarch64/mmu.c @@ -1,381 +1,381 @@ -#include -#include -#include "ft_assert.h" -#include -#include "mmu.h" - -#define assert FT_ASSERTNONERETURN -/****************************** - * mmu config define - ******************************/ -#define CONFIG_ARM64_VA_BITS 42 -#define CONFIG_ARM64_PA_BITS 42 -#define CONFIG_MAX_XLAT_TABLES 8 -/****************************** - * mmu config define - ******************************/ - -// extern const struct arm_mmu_region *mmu_regions; -// extern const uint32_t mmu_regions_size; -extern const struct arm_mmu_config mmu_config; - -/* We support only 4kB translation granule */ -#define PAGE_SIZE_SHIFT 12U -#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT) -#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ -#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT) - -#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */ -#define XLAT_TABLE_LEVEL_MAX 3U - -#define XLAT_TABLE_ENTRIES_SHIFT \ - (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT) -#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT) - -/* Address size covered by each entry at given translation table level */ -#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT -#define L2_XLAT_VA_SIZE_SHIFT \ - (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) -#define L1_XLAT_VA_SIZE_SHIFT \ - (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) -#define L0_XLAT_VA_SIZE_SHIFT \ - (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) - -#define LEVEL_TO_VA_SIZE_SHIFT(level) \ - (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \ - (XLAT_TABLE_LEVEL_MAX - (level)))) - -/* Virtual Address Index within given translation table level */ -#define XLAT_TABLE_VA_IDX(va_addr, level) \ - ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1)) - -/* - * Calculate the initial translation table level from CONFIG_ARM64_VA_BITS - * For a 4 KB page size, - * (va_bits <= 21) - base level 3 - * (22 <= va_bits <= 30) - base level 2 - * (31 <= va_bits <= 39) - base level 1 - * (40 <= va_bits <= 48) - base level 0 - */ -#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \ - ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \ - ? 0U \ - : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \ - ? 1U \ - : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \ - ? 2U \ - : 3U) - -#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS) - -#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \ - (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL))) - -#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES(CONFIG_ARM64_VA_BITS) - -static u64 base_xlat_table[NUM_BASE_LEVEL_ENTRIES] __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(u64)); - -static u64 xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] __aligned(XLAT_TABLE_ENTRIES * sizeof(u64)); - -/* Translation table control register settings */ -static u64 get_tcr(int el) -{ - u64 tcr; - u64 pa_bits = CONFIG_ARM64_PA_BITS; - u64 va_bits = CONFIG_ARM64_VA_BITS; - u64 tcr_ps_bits; - - switch (pa_bits) - { - case 48: - tcr_ps_bits = TCR_PS_BITS_256TB; - break; - case 44: - tcr_ps_bits = TCR_PS_BITS_16TB; - break; - case 42: - tcr_ps_bits = TCR_PS_BITS_4TB; - break; - case 40: - tcr_ps_bits = TCR_PS_BITS_1TB; - break; - case 36: - tcr_ps_bits = TCR_PS_BITS_64GB; - break; - default: - tcr_ps_bits = TCR_PS_BITS_4GB; - break; - } - - if (el == 1) - { - tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT); - /* - * TCR_EL1.EPD1: Disable translation table walk for addresses - * that are translated using TTBR1_EL1. - */ - tcr |= TCR_EPD1_DISABLE; - } - else - tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT); - - tcr |= TCR_T0SZ(va_bits); - /* - * Translation table walk is cacheable, inner/outer WBWA and - * inner shareable - */ - tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA; - - return tcr; -} - -static int PteDescType(u64 *pte) -{ - return *pte & PTE_DESC_TYPE_MASK; -} - -static u64 *CalculatePteIndex(u64 addr, unsigned int level) -{ - u32 base_level = XLAT_TABLE_BASE_LEVEL; - u64 *pte; - u64 idx; - unsigned int i; - - /* Walk through all translation tables to find pte index */ - pte = (u64 *)base_xlat_table; - for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++) - { - idx = XLAT_TABLE_VA_IDX(addr, i); - pte += idx; - /* Found pte index */ - if (i == level) - return pte; - /* if PTE is not table desc, can't traverse */ - if (PteDescType(pte) != PTE_TABLE_DESC) - return NULL; - /* Move to the next translation table level */ - pte = (u64 *)(*pte & 0x0000fffffffff000ULL); - } - - return NULL; -} - -static void SetPteTableDesc(u64 *pte, u64 *table, unsigned int level) -{ - /* Point pte to new table */ - *pte = PTE_TABLE_DESC | (u64)table; -} - -static void SetPteBlockDesc(u64 *pte, u64 addr_pa, - unsigned int attrs, unsigned int level) -{ - u64 desc = addr_pa; - unsigned int mem_type; - - desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC; - - /* NS bit for security memory access from secure state */ - desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0; - - /* AP bits for Data access permission */ - desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO; - - /* the access flag */ - desc |= PTE_BLOCK_DESC_AF; - - /* memory attribute index field */ - mem_type = MT_TYPE(attrs); - desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type); - - switch (mem_type) - { - case MT_DEVICE_nGnRnE: - case MT_DEVICE_nGnRE: - case MT_DEVICE_GRE: - /* Access to Device memory and non-cacheable memory are coherent - * for all observers in the system and are treated as - * Outer shareable, so, for these 2 types of memory, - * it is not strictly needed to set shareability field - */ - desc |= PTE_BLOCK_DESC_OUTER_SHARE; - /* Map device memory as execute-never */ - desc |= PTE_BLOCK_DESC_PXN; - desc |= PTE_BLOCK_DESC_UXN; - break; - case MT_NORMAL_NC: - case MT_NORMAL: - if (mem_type == MT_NORMAL) - desc |= PTE_BLOCK_DESC_INNER_SHARE; - else - desc |= PTE_BLOCK_DESC_OUTER_SHARE; - } - - *pte = desc; -} - -/* Returns a new reallocated table */ -static u64 *NewPreallocTable(void) -{ - static unsigned int table_idx; - - assert(table_idx < CONFIG_MAX_XLAT_TABLES); - - return (u64 *)(xlat_tables[table_idx++]); -} - -/* Splits a block into table with entries spanning the old block */ -static void SplitPteBlockDesc(u64 *pte, int level) -{ - u64 old_block_desc = *pte; - u64 *new_table; - unsigned int i = 0; - /* get address size shift bits for next level */ - int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1); - - new_table = NewPreallocTable(); - - for (i = 0; i < XLAT_TABLE_ENTRIES; i++) - { - new_table[i] = old_block_desc | (i << levelshift); - - if ((level + 1) == 3) - new_table[i] |= PTE_PAGE_DESC; - } - - /* Overwrite existing PTE set the new table into effect */ - SetPteTableDesc(pte, new_table, level); -} - -/* Create/Populate translation table(s) for given region */ -static void InitXlatTables(const struct arm_mmu_region *region) -{ - u64 *pte; - u64 virt = region->base_va; - u64 phys = region->base_pa; - u64 size = region->size; - u64 attrs = region->attrs; - u64 level_size; - u64 *new_table; - unsigned int level = XLAT_TABLE_BASE_LEVEL; - - /* check minimum alignment requirement for given mmap region */ - assert(((virt & (PAGE_SIZE - 1)) == 0) && - ((size & (PAGE_SIZE - 1)) == 0)); - - while (size) - { - assert(level <= XLAT_TABLE_LEVEL_MAX); - - /* Locate PTE for given virtual address and page table level */ - pte = CalculatePteIndex(virt, level); - assert(pte != NULL); - - level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level); - - if (size >= level_size && !(virt & (level_size - 1))) - { - /* Given range fits into level size, - * create block/page descriptor - */ - SetPteBlockDesc(pte, phys, attrs, level); - virt += level_size; - phys += level_size; - size -= level_size; - /* Range is mapped, start again for next range */ - level = XLAT_TABLE_BASE_LEVEL; - } - else if (PteDescType(pte) == PTE_INVALID_DESC) - { - /* Range doesn't fit, create subtable */ - new_table = NewPreallocTable(); - SetPteTableDesc(pte, new_table, level); - level++; - } - else if (PteDescType(pte) == PTE_BLOCK_DESC) - { - SplitPteBlockDesc(pte, level); - level++; - } - else if (PteDescType(pte) == PTE_TABLE_DESC) - level++; - } -} - -static void SetupPageTables(void) -{ - unsigned int index; - const struct arm_mmu_region *region; - u64 max_va = 0, max_pa = 0; - - for (index = 0; index < mmu_config.num_regions; index++) - { - region = &mmu_config.mmu_regions[index]; - max_va = max(max_va, region->base_va + region->size); - max_pa = max(max_pa, region->base_pa + region->size); - } - - assert(max_va <= (1ULL << CONFIG_ARM64_VA_BITS)); - assert(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS)); - - /* create translation tables for user provided platform regions */ - for (index = 0; index < mmu_config.num_regions; index++) - { - region = &mmu_config.mmu_regions[index]; - if (region->size || region->attrs) - InitXlatTables(region); - } -} - -static void EnableMmuEl1() -{ - u64 val; - - /* Set MAIR, TCR and TBBR registers */ - __asm__ volatile("msr mair_el1, %0" - : - : "r"(MEMORY_ATTRIBUTES) - : "memory", "cc"); - __asm__ volatile("msr tcr_el1, %0" - : - : "r"(get_tcr(1)) - : "memory", "cc"); - __asm__ volatile("msr ttbr0_el1, %0" - : - : "r"((u64)base_xlat_table) - : "memory", "cc"); - - /* Ensure these changes are seen before MMU is enabled */ - ISB(); -} - -/* ARM MMU Driver Initial Setup */ - -/* - * @brief MMU default configuration - * - * This function provides the default configuration mechanism for the Memory - * Management Unit (MMU). - */ -int MmuInit() -{ - u64 val; - unsigned int idx, flags = 0; - - /* Current MMU code supports only EL1 */ - __asm__ volatile("mrs %0, CurrentEL" - : "=r"(val)); - - assert(GET_EL(val) == MODE_EL1); - - /* Ensure that MMU is already not enabled */ - __asm__ volatile("mrs %0, sctlr_el1" - : "=r"(val)); - assert((val & SCTLR_ELx_M) == 0); - - SetupPageTables(); - - /* currently only EL1 is supported */ - EnableMmuEl1(); - - return 0; -} +#include +#include +#include "ft_assert.h" +#include +#include "mmu.h" + +#define assert FT_ASSERTNONERETURN +/****************************** + * mmu config define + ******************************/ +#define CONFIG_ARM64_VA_BITS 42 +#define CONFIG_ARM64_PA_BITS 42 +#define CONFIG_MAX_XLAT_TABLES 8 +/****************************** + * mmu config define + ******************************/ + +// extern const struct arm_mmu_region *mmu_regions; +// extern const uint32_t mmu_regions_size; +extern const struct arm_mmu_config mmu_config; + +/* We support only 4kB translation granule */ +#define PAGE_SIZE_SHIFT 12U +#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT) +#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ +#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT) + +#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */ +#define XLAT_TABLE_LEVEL_MAX 3U + +#define XLAT_TABLE_ENTRIES_SHIFT \ + (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT) +#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT) + +/* Address size covered by each entry at given translation table level */ +#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT +#define L2_XLAT_VA_SIZE_SHIFT \ + (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L1_XLAT_VA_SIZE_SHIFT \ + (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L0_XLAT_VA_SIZE_SHIFT \ + (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) + +#define LEVEL_TO_VA_SIZE_SHIFT(level) \ + (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \ + (XLAT_TABLE_LEVEL_MAX - (level)))) + +/* Virtual Address Index within given translation table level */ +#define XLAT_TABLE_VA_IDX(va_addr, level) \ + ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1)) + +/* + * Calculate the initial translation table level from CONFIG_ARM64_VA_BITS + * For a 4 KB page size, + * (va_bits <= 21) - base level 3 + * (22 <= va_bits <= 30) - base level 2 + * (31 <= va_bits <= 39) - base level 1 + * (40 <= va_bits <= 48) - base level 0 + */ +#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \ + ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \ + ? 0U \ + : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \ + ? 1U \ + : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \ + ? 2U \ + : 3U) + +#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS) + +#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \ + (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL))) + +#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES(CONFIG_ARM64_VA_BITS) + +static u64 base_xlat_table[NUM_BASE_LEVEL_ENTRIES] __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(u64)); + +static u64 xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] __aligned(XLAT_TABLE_ENTRIES * sizeof(u64)); + +/* Translation table control register settings */ +static u64 get_tcr(int el) +{ + u64 tcr; + u64 pa_bits = CONFIG_ARM64_PA_BITS; + u64 va_bits = CONFIG_ARM64_VA_BITS; + u64 tcr_ps_bits; + + switch (pa_bits) + { + case 48: + tcr_ps_bits = TCR_PS_BITS_256TB; + break; + case 44: + tcr_ps_bits = TCR_PS_BITS_16TB; + break; + case 42: + tcr_ps_bits = TCR_PS_BITS_4TB; + break; + case 40: + tcr_ps_bits = TCR_PS_BITS_1TB; + break; + case 36: + tcr_ps_bits = TCR_PS_BITS_64GB; + break; + default: + tcr_ps_bits = TCR_PS_BITS_4GB; + break; + } + + if (el == 1) + { + tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT); + /* + * TCR_EL1.EPD1: Disable translation table walk for addresses + * that are translated using TTBR1_EL1. + */ + tcr |= TCR_EPD1_DISABLE; + } + else + tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT); + + tcr |= TCR_T0SZ(va_bits); + /* + * Translation table walk is cacheable, inner/outer WBWA and + * inner shareable + */ + tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA; + + return tcr; +} + +static int PteDescType(u64 *pte) +{ + return *pte & PTE_DESC_TYPE_MASK; +} + +static u64 *CalculatePteIndex(u64 addr, unsigned int level) +{ + u32 base_level = XLAT_TABLE_BASE_LEVEL; + u64 *pte; + u64 idx; + unsigned int i; + + /* Walk through all translation tables to find pte index */ + pte = (u64 *)base_xlat_table; + for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++) + { + idx = XLAT_TABLE_VA_IDX(addr, i); + pte += idx; + /* Found pte index */ + if (i == level) + return pte; + /* if PTE is not table desc, can't traverse */ + if (PteDescType(pte) != PTE_TABLE_DESC) + return NULL; + /* Move to the next translation table level */ + pte = (u64 *)(*pte & 0x0000fffffffff000ULL); + } + + return NULL; +} + +static void SetPteTableDesc(u64 *pte, u64 *table, unsigned int level) +{ + /* Point pte to new table */ + *pte = PTE_TABLE_DESC | (u64)table; +} + +static void SetPteBlockDesc(u64 *pte, u64 addr_pa, + unsigned int attrs, unsigned int level) +{ + u64 desc = addr_pa; + unsigned int mem_type; + + desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC; + + /* NS bit for security memory access from secure state */ + desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0; + + /* AP bits for Data access permission */ + desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO; + + /* the access flag */ + desc |= PTE_BLOCK_DESC_AF; + + /* memory attribute index field */ + mem_type = MT_TYPE(attrs); + desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type); + + switch (mem_type) + { + case MT_DEVICE_nGnRnE: + case MT_DEVICE_nGnRE: + case MT_DEVICE_GRE: + /* Access to Device memory and non-cacheable memory are coherent + * for all observers in the system and are treated as + * Outer shareable, so, for these 2 types of memory, + * it is not strictly needed to set shareability field + */ + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + /* Map device memory as execute-never */ + desc |= PTE_BLOCK_DESC_PXN; + desc |= PTE_BLOCK_DESC_UXN; + break; + case MT_NORMAL_NC: + case MT_NORMAL: + if (mem_type == MT_NORMAL) + desc |= PTE_BLOCK_DESC_INNER_SHARE; + else + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + } + + *pte = desc; +} + +/* Returns a new reallocated table */ +static u64 *NewPreallocTable(void) +{ + static unsigned int table_idx; + + assert(table_idx < CONFIG_MAX_XLAT_TABLES); + + return (u64 *)(xlat_tables[table_idx++]); +} + +/* Splits a block into table with entries spanning the old block */ +static void SplitPteBlockDesc(u64 *pte, int level) +{ + u64 old_block_desc = *pte; + u64 *new_table; + unsigned int i = 0; + /* get address size shift bits for next level */ + int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1); + + new_table = NewPreallocTable(); + + for (i = 0; i < XLAT_TABLE_ENTRIES; i++) + { + new_table[i] = old_block_desc | (i << levelshift); + + if ((level + 1) == 3) + new_table[i] |= PTE_PAGE_DESC; + } + + /* Overwrite existing PTE set the new table into effect */ + SetPteTableDesc(pte, new_table, level); +} + +/* Create/Populate translation table(s) for given region */ +static void InitXlatTables(const struct arm_mmu_region *region) +{ + u64 *pte; + u64 virt = region->base_va; + u64 phys = region->base_pa; + u64 size = region->size; + u64 attrs = region->attrs; + u64 level_size; + u64 *new_table; + unsigned int level = XLAT_TABLE_BASE_LEVEL; + + /* check minimum alignment requirement for given mmap region */ + assert(((virt & (PAGE_SIZE - 1)) == 0) && + ((size & (PAGE_SIZE - 1)) == 0)); + + while (size) + { + assert(level <= XLAT_TABLE_LEVEL_MAX); + + /* Locate PTE for given virtual address and page table level */ + pte = CalculatePteIndex(virt, level); + assert(pte != NULL); + + level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level); + + if (size >= level_size && !(virt & (level_size - 1))) + { + /* Given range fits into level size, + * create block/page descriptor + */ + SetPteBlockDesc(pte, phys, attrs, level); + virt += level_size; + phys += level_size; + size -= level_size; + /* Range is mapped, start again for next range */ + level = XLAT_TABLE_BASE_LEVEL; + } + else if (PteDescType(pte) == PTE_INVALID_DESC) + { + /* Range doesn't fit, create subtable */ + new_table = NewPreallocTable(); + SetPteTableDesc(pte, new_table, level); + level++; + } + else if (PteDescType(pte) == PTE_BLOCK_DESC) + { + SplitPteBlockDesc(pte, level); + level++; + } + else if (PteDescType(pte) == PTE_TABLE_DESC) + level++; + } +} + +static void SetupPageTables(void) +{ + unsigned int index; + const struct arm_mmu_region *region; + u64 max_va = 0, max_pa = 0; + + for (index = 0; index < mmu_config.num_regions; index++) + { + region = &mmu_config.mmu_regions[index]; + max_va = max(max_va, region->base_va + region->size); + max_pa = max(max_pa, region->base_pa + region->size); + } + + assert(max_va <= (1ULL << CONFIG_ARM64_VA_BITS)); + assert(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS)); + + /* create translation tables for user provided platform regions */ + for (index = 0; index < mmu_config.num_regions; index++) + { + region = &mmu_config.mmu_regions[index]; + if (region->size || region->attrs) + InitXlatTables(region); + } +} + +static void EnableMmuEl1() +{ + u64 val; + + /* Set MAIR, TCR and TBBR registers */ + __asm__ volatile("msr mair_el1, %0" + : + : "r"(MEMORY_ATTRIBUTES) + : "memory", "cc"); + __asm__ volatile("msr tcr_el1, %0" + : + : "r"(get_tcr(1)) + : "memory", "cc"); + __asm__ volatile("msr ttbr0_el1, %0" + : + : "r"((u64)base_xlat_table) + : "memory", "cc"); + + /* Ensure these changes are seen before MMU is enabled */ + ISB(); +} + +/* ARM MMU Driver Initial Setup */ + +/* + * @brief MMU default configuration + * + * This function provides the default configuration mechanism for the Memory + * Management Unit (MMU). + */ +int MmuInit() +{ + u64 val; + unsigned int idx, flags = 0; + + /* Current MMU code supports only EL1 */ + __asm__ volatile("mrs %0, CurrentEL" + : "=r"(val)); + + assert(GET_EL(val) == MODE_EL1); + + /* Ensure that MMU is already not enabled */ + __asm__ volatile("mrs %0, sctlr_el1" + : "=r"(val)); + assert((val & SCTLR_ELx_M) == 0); + + SetupPageTables(); + + /* currently only EL1 is supported */ + EnableMmuEl1(); + + return 0; +} diff --git a/bsp/arch/armv8/aarch64/mmu.h b/bsp/arch/armv8/aarch64/mmu.h index 43db9460b..bf0e5df59 100644 --- a/bsp/arch/armv8/aarch64/mmu.h +++ b/bsp/arch/armv8/aarch64/mmu.h @@ -1,176 +1,176 @@ -/* - * Copyright 2019 Broadcom - * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef MMU_H_ -#define MMU_H_ - -#include "ft_types.h" - -/* Following Memory types supported through MAIR encodings can be passed - * by user through "attrs"(attributes) field of specified memory region. - * As MAIR supports such 8 encodings, we will reserve attrs[2:0]; - * so that we can provide encodings upto 7 if needed in future. - */ -#define MT_TYPE_MASK 0x7U -#define MT_TYPE(attr) (attr & MT_TYPE_MASK) -#define MT_DEVICE_nGnRnE 0U -#define MT_DEVICE_nGnRE 1U -#define MT_DEVICE_GRE 2U -#define MT_NORMAL_NC 3U -#define MT_NORMAL 4U - -#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_nGnRnE * 8)) | \ - (0x04 << (MT_DEVICE_nGnRE * 8)) | \ - (0x0c << (MT_DEVICE_GRE * 8)) | \ - (0x44 << (MT_NORMAL_NC * 8)) | \ - (0xffUL << (MT_NORMAL * 8))) - -/* More flags from user's perpective are supported using remaining bits - * of "attrs" field, i.e. attrs[31:3], underlying code will take care - * of setting PTE fields correctly. - * - * current usage of attrs[31:3] is: - * attrs[3] : Access Permissions - * attrs[4] : Memory access from secure/ns state - * attrs[5] : Execute Permissions - * - */ -#define MT_PERM_SHIFT 3U -#define MT_SEC_SHIFT 4U -#define MT_EXECUTE_SHIFT 5U - -#define MT_RO (0U << MT_PERM_SHIFT) -#define MT_RW (1U << MT_PERM_SHIFT) - -#define MT_SECURE (0U << MT_SEC_SHIFT) -#define MT_NS (1U << MT_SEC_SHIFT) - -#define MT_EXECUTE (0U << MT_EXECUTE_SHIFT) -#define MT_EXECUTE_NEVER (1U << MT_EXECUTE_SHIFT) - -/* Some compound attributes for most common usages */ -#define MT_CODE (MT_NORMAL | MT_RO | MT_EXECUTE) -#define MT_RODATA (MT_NORMAL | MT_RO | MT_EXECUTE_NEVER) - -/* - * PTE descriptor can be Block descriptor or Table descriptor - * or Page descriptor. - */ -#define PTE_DESC_TYPE_MASK 3U -#define PTE_BLOCK_DESC 1U -#define PTE_TABLE_DESC 3U -#define PTE_PAGE_DESC 3U -#define PTE_INVALID_DESC 0U - -/* - * Block and Page descriptor attributes fields - */ -#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2) -#define PTE_BLOCK_DESC_NS (1ULL << 5) -#define PTE_BLOCK_DESC_AP_RO (1ULL << 7) -#define PTE_BLOCK_DESC_AP_RW (0ULL << 7) -#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8) -#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8) -#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8) -#define PTE_BLOCK_DESC_AF (1ULL << 10) -#define PTE_BLOCK_DESC_NG (1ULL << 11) -#define PTE_BLOCK_DESC_PXN (1ULL << 53) -#define PTE_BLOCK_DESC_UXN (1ULL << 54) - -/* - * TCR definitions. - */ -#define TCR_EL1_IPS_SHIFT 32U -#define TCR_EL2_PS_SHIFT 16U -#define TCR_EL3_PS_SHIFT 16U - -#define TCR_T0SZ_SHIFT 0U -#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT) - -#define TCR_IRGN_NC (0ULL << 8) -#define TCR_IRGN_WBWA (1ULL << 8) -#define TCR_IRGN_WT (2ULL << 8) -#define TCR_IRGN_WBNWA (3ULL << 8) -#define TCR_IRGN_MASK (3ULL << 8) -#define TCR_ORGN_NC (0ULL << 10) -#define TCR_ORGN_WBWA (1ULL << 10) -#define TCR_ORGN_WT (2ULL << 10) -#define TCR_ORGN_WBNWA (3ULL << 10) -#define TCR_ORGN_MASK (3ULL << 10) -#define TCR_SHARED_NON (0ULL << 12) -#define TCR_SHARED_OUTER (2ULL << 12) -#define TCR_SHARED_INNER (3ULL << 12) -#define TCR_TG0_4K (0ULL << 14) -#define TCR_TG0_64K (1ULL << 14) -#define TCR_TG0_16K (2ULL << 14) -#define TCR_EPD1_DISABLE (1ULL << 23) - -#define TCR_PS_BITS_4GB 0x0ULL -#define TCR_PS_BITS_64GB 0x1ULL -#define TCR_PS_BITS_1TB 0x2ULL -#define TCR_PS_BITS_4TB 0x3ULL -#define TCR_PS_BITS_16TB 0x4ULL -#define TCR_PS_BITS_256TB 0x5ULL - -/* Region definition data structure */ -struct arm_mmu_region -{ - /* Region Base Physical Address */ - u64 base_pa; - /* Region Base Virtual Address */ - u64 base_va; - /* Region size */ - u64 size; - /* Region Name */ - const char *name; - /* Region Attributes */ - unsigned int attrs; -}; - -/* MMU configuration data structure */ -struct arm_mmu_config -{ - /* Number of regions */ - uint32_t num_regions; - /* Regions */ - const struct arm_mmu_region *mmu_regions; -}; - -/* Convenience macros to represent the ARMv8-A-specific - * configuration for memory access permission and - * cache-ability attribution. - */ - -#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \ - { \ - .name = _name, \ - .base_pa = _base_pa, \ - .base_va = _base_va, \ - .size = _size, \ - .attrs = _attrs, \ - } - -#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \ - MMU_REGION_ENTRY(name, adr, adr, sz, attrs) - -#define ARRAY_SIZE(array) \ - ((long)((sizeof(array) / sizeof((array)[0])))) - -/* KB, MB, GB */ -#define KB(x) ((x) << 10) -#define MB(x) (KB(x) << 10) -#define GB(x) (MB(x) << 10) - -/* Reference to the MMU configuration. - * - * This struct is defined and populated for each SoC (in the SoC definition), - * and holds the build-time configuration information for the fixed MMU - * regions enabled during kernel initialization. - */ - -int MmuInit(); - +/* + * Copyright 2019 Broadcom + * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef MMU_H_ +#define MMU_H_ + +#include "ft_types.h" + +/* Following Memory types supported through MAIR encodings can be passed + * by user through "attrs"(attributes) field of specified memory region. + * As MAIR supports such 8 encodings, we will reserve attrs[2:0]; + * so that we can provide encodings upto 7 if needed in future. + */ +#define MT_TYPE_MASK 0x7U +#define MT_TYPE(attr) (attr & MT_TYPE_MASK) +#define MT_DEVICE_nGnRnE 0U +#define MT_DEVICE_nGnRE 1U +#define MT_DEVICE_GRE 2U +#define MT_NORMAL_NC 3U +#define MT_NORMAL 4U + +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_nGnRnE * 8)) | \ + (0x04 << (MT_DEVICE_nGnRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (0xffUL << (MT_NORMAL * 8))) + +/* More flags from user's perpective are supported using remaining bits + * of "attrs" field, i.e. attrs[31:3], underlying code will take care + * of setting PTE fields correctly. + * + * current usage of attrs[31:3] is: + * attrs[3] : Access Permissions + * attrs[4] : Memory access from secure/ns state + * attrs[5] : Execute Permissions + * + */ +#define MT_PERM_SHIFT 3U +#define MT_SEC_SHIFT 4U +#define MT_EXECUTE_SHIFT 5U + +#define MT_RO (0U << MT_PERM_SHIFT) +#define MT_RW (1U << MT_PERM_SHIFT) + +#define MT_SECURE (0U << MT_SEC_SHIFT) +#define MT_NS (1U << MT_SEC_SHIFT) + +#define MT_EXECUTE (0U << MT_EXECUTE_SHIFT) +#define MT_EXECUTE_NEVER (1U << MT_EXECUTE_SHIFT) + +/* Some compound attributes for most common usages */ +#define MT_CODE (MT_NORMAL | MT_RO | MT_EXECUTE) +#define MT_RODATA (MT_NORMAL | MT_RO | MT_EXECUTE_NEVER) + +/* + * PTE descriptor can be Block descriptor or Table descriptor + * or Page descriptor. + */ +#define PTE_DESC_TYPE_MASK 3U +#define PTE_BLOCK_DESC 1U +#define PTE_TABLE_DESC 3U +#define PTE_PAGE_DESC 3U +#define PTE_INVALID_DESC 0U + +/* + * Block and Page descriptor attributes fields + */ +#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2) +#define PTE_BLOCK_DESC_NS (1ULL << 5) +#define PTE_BLOCK_DESC_AP_RO (1ULL << 7) +#define PTE_BLOCK_DESC_AP_RW (0ULL << 7) +#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8) +#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8) +#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8) +#define PTE_BLOCK_DESC_AF (1ULL << 10) +#define PTE_BLOCK_DESC_NG (1ULL << 11) +#define PTE_BLOCK_DESC_PXN (1ULL << 53) +#define PTE_BLOCK_DESC_UXN (1ULL << 54) + +/* + * TCR definitions. + */ +#define TCR_EL1_IPS_SHIFT 32U +#define TCR_EL2_PS_SHIFT 16U +#define TCR_EL3_PS_SHIFT 16U + +#define TCR_T0SZ_SHIFT 0U +#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT) + +#define TCR_IRGN_NC (0ULL << 8) +#define TCR_IRGN_WBWA (1ULL << 8) +#define TCR_IRGN_WT (2ULL << 8) +#define TCR_IRGN_WBNWA (3ULL << 8) +#define TCR_IRGN_MASK (3ULL << 8) +#define TCR_ORGN_NC (0ULL << 10) +#define TCR_ORGN_WBWA (1ULL << 10) +#define TCR_ORGN_WT (2ULL << 10) +#define TCR_ORGN_WBNWA (3ULL << 10) +#define TCR_ORGN_MASK (3ULL << 10) +#define TCR_SHARED_NON (0ULL << 12) +#define TCR_SHARED_OUTER (2ULL << 12) +#define TCR_SHARED_INNER (3ULL << 12) +#define TCR_TG0_4K (0ULL << 14) +#define TCR_TG0_64K (1ULL << 14) +#define TCR_TG0_16K (2ULL << 14) +#define TCR_EPD1_DISABLE (1ULL << 23) + +#define TCR_PS_BITS_4GB 0x0ULL +#define TCR_PS_BITS_64GB 0x1ULL +#define TCR_PS_BITS_1TB 0x2ULL +#define TCR_PS_BITS_4TB 0x3ULL +#define TCR_PS_BITS_16TB 0x4ULL +#define TCR_PS_BITS_256TB 0x5ULL + +/* Region definition data structure */ +struct arm_mmu_region +{ + /* Region Base Physical Address */ + u64 base_pa; + /* Region Base Virtual Address */ + u64 base_va; + /* Region size */ + u64 size; + /* Region Name */ + const char *name; + /* Region Attributes */ + unsigned int attrs; +}; + +/* MMU configuration data structure */ +struct arm_mmu_config +{ + /* Number of regions */ + uint32_t num_regions; + /* Regions */ + const struct arm_mmu_region *mmu_regions; +}; + +/* Convenience macros to represent the ARMv8-A-specific + * configuration for memory access permission and + * cache-ability attribution. + */ + +#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \ + { \ + .name = _name, \ + .base_pa = _base_pa, \ + .base_va = _base_va, \ + .size = _size, \ + .attrs = _attrs, \ + } + +#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \ + MMU_REGION_ENTRY(name, adr, adr, sz, attrs) + +#define ARRAY_SIZE(array) \ + ((long)((sizeof(array) / sizeof((array)[0])))) + +/* KB, MB, GB */ +#define KB(x) ((x) << 10) +#define MB(x) (KB(x) << 10) +#define GB(x) (MB(x) << 10) + +/* Reference to the MMU configuration. + * + * This struct is defined and populated for each SoC (in the SoC definition), + * and holds the build-time configuration information for the fixed MMU + * regions enabled during kernel initialization. + */ + +int MmuInit(); + #endif /* MMU_H_ */ \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/e2000/_cpu.c b/bsp/arch/armv8/aarch64/platform/e2000/_cpu.c index 804e06b78..0b42d82d8 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/_cpu.c +++ b/bsp/arch/armv8/aarch64/platform/e2000/_cpu.c @@ -1,38 +1,38 @@ -#include "_cpu.h" - -u32 GetCpuId(void) -{ - u32 affinity = GetAffinity(); - - switch (affinity & 0xfff) - { - case 0: - return 0; - case 1: - return 1; - case 0x100: - return 2; - case 0x101: - return 3; - default: - return 0; - } - return 0; -} - -u64 GetCpuCluster(u32 cpu_id) -{ - switch (cpu_id) - { - case 0: - return 0; - case 1: - return 1; - case 2: - return 0x100; - case 3: - return 0x101; - default: - return 0; - } -} +#include "_cpu.h" + +u32 GetCpuId(void) +{ + u32 affinity = GetAffinity(); + + switch (affinity & 0xfff) + { + case 0: + return 0; + case 1: + return 1; + case 0x100: + return 2; + case 0x101: + return 3; + default: + return 0; + } + return 0; +} + +u64 GetCpuCluster(u32 cpu_id) +{ + switch (cpu_id) + { + case 0: + return 0; + case 1: + return 1; + case 2: + return 0x100; + case 3: + return 0x101; + default: + return 0; + } +} diff --git a/bsp/arch/armv8/aarch64/platform/e2000/_cpu.h b/bsp/arch/armv8/aarch64/platform/e2000/_cpu.h index 9ca1bb806..e5b5203ad 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/_cpu.h +++ b/bsp/arch/armv8/aarch64/platform/e2000/_cpu.h @@ -1,17 +1,17 @@ -#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H -#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - u32 GetAffinity(void); - u32 GetCpuId(void); -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H +#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + u32 GetAffinity(void); + u32 GetCpuId(void); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/e2000/_cpu_asm.S b/bsp/arch/armv8/aarch64/platform/e2000/_cpu_asm.S index d86b82cf8..0ad74640f 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/_cpu_asm.S +++ b/bsp/arch/armv8/aarch64/platform/e2000/_cpu_asm.S @@ -1,10 +1,10 @@ - -// ------------------------------------------------------------ - .global GetAffinity - //uint32_t GetAffinity(void); - .type GetAffinity, @function -GetAffinity: - MRS x0, MPIDR_EL1 - UBFX x1, x0, #32, #8 - BFI w0, w1, #24, #8 - RET + +// ------------------------------------------------------------ + .global GetAffinity + //uint32_t GetAffinity(void); + .type GetAffinity, @function +GetAffinity: + MRS x0, MPIDR_EL1 + UBFX x1, x0, #32, #8 + BFI w0, w1, #24, #8 + RET diff --git a/bsp/arch/armv8/aarch64/platform/e2000/early_uart.c b/bsp/arch/armv8/aarch64/platform/e2000/early_uart.c index 15172c646..75cb02bc7 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/early_uart.c +++ b/bsp/arch/armv8/aarch64/platform/e2000/early_uart.c @@ -1,13 +1,13 @@ -#include "early_uart.h" - -void OutByte(s8 byte) -{ - // FtOut32(0x28001000, (u32)byte); - while ((FtIn32(0x2800d018) & 0x20) == 0x20) - { - /* code */ - } - - FtOut32(0x2800d000, (u32)byte); -} +#include "early_uart.h" + +void OutByte(s8 byte) +{ + // FtOut32(0x28001000, (u32)byte); + while ((FtIn32(0x2800d018) & 0x20) == 0x20) + { + /* code */ + } + + FtOut32(0x2800d000, (u32)byte); +} \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/e2000/early_uart.h b/bsp/arch/armv8/aarch64/platform/e2000/early_uart.h index c717c9758..97d38fb62 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/early_uart.h +++ b/bsp/arch/armv8/aarch64/platform/e2000/early_uart.h @@ -1,18 +1,18 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - - void OutByte(s8 byte); - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + + void OutByte(s8 byte); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/e2000/parameters.c b/bsp/arch/armv8/aarch64/platform/e2000/parameters.c index bb0a0b154..ceaec8694 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/parameters.c +++ b/bsp/arch/armv8/aarch64/platform/e2000/parameters.c @@ -1,35 +1,35 @@ -#include "mmu.h" -#include "ft_types.h" - -const struct arm_mmu_region mmu_regions[] = { - MMU_REGION_FLAT_ENTRY("DEVICE_REGION", - 0X00, 0x40000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", - 0x40000000, 0x10000000, - MT_DEVICE_nGnRnE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0x50000000, 0x30000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0x80000000, 0x80000000, - MT_NORMAL | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0X1000000000, 0X1000000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0X2000000000, 0X2000000000, - MT_NORMAL | MT_RW | MT_NS), -}; - -const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); - -const struct arm_mmu_config mmu_config = { - .num_regions = mmu_regions_size, - .mmu_regions = mmu_regions, +#include "mmu.h" +#include "ft_types.h" + +const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("DEVICE_REGION", + 0X00, 0x40000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", + 0x40000000, 0x10000000, + MT_DEVICE_nGnRnE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0x50000000, 0x30000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0x80000000, 0x80000000, + MT_NORMAL | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0X1000000000, 0X1000000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0X2000000000, 0X2000000000, + MT_NORMAL | MT_RW | MT_NS), +}; + +const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); + +const struct arm_mmu_config mmu_config = { + .num_regions = mmu_regions_size, + .mmu_regions = mmu_regions, }; \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/e2000/parameters.h b/bsp/arch/armv8/aarch64/platform/e2000/parameters.h index e6c56c74d..d156aeccc 100644 --- a/bsp/arch/armv8/aarch64/platform/e2000/parameters.h +++ b/bsp/arch/armv8/aarch64/platform/e2000/parameters.h @@ -1,68 +1,68 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - // timer -#define GENERIC_TIMER_NS_IRQ_NUM 30 -#define GENERIC_TIMER_NS_CLK_FREQ 2000000 -#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ - - // UART - -#define FT_UART_NUM 4 -#define FT_UART_REG_LENGTH 0x18000 - -#define FT_UART0_ID 0 -#define FT_UART0_IRQ_NUM (85 + 30) -#define FT_UART0_BASE_ADDR 0x2800c000 -#define FT_UART0_CLK_FREQ_HZ 100000000 - -#define FT_UART1_ID 1 -#define FT_UART1_IRQ_NUM (86 + 30) -#define FT_UART1_BASE_ADDR 0x2800d000 -#define FT_UART1_CLK_FREQ_HZ 100000000 - -#define FT_UART2_ID 2 -#define FT_UART2_IRQ_NUM (87 + 30) -#define FT_UART2_BASE_ADDR 0x2800e000 -#define FT_UART2_CLK_FREQ_HZ 100000000 - -#define FT_UART3_BASE_ADDR 0x2800f000 -#define FT_UART3_ID 3 -#define FT_UART3_IRQ_NUM (88 + 30) -#define FT_UART3_CLK_FREQ_HZ 100000000 - -#define FT_STDOUT_base_address FT_UART1_BASE_ADDR -#define FT_STDIN_base_address FT_UART1_BASE_ADDR - -/****** GIC v3 *****/ -#define FT_GICV3_INSTANCES_NUM 1U -#define GICV3_REG_LENGTH 0x00009000 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define GICV3_MAX_INTR_PRIO_VAL 240U -#define GICV3_INTR_PRIO_MASK 0x000000f0U - -#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ -#define SGI_INT_MAX 16 -#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ -#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ -#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ - -#define GICV3_BASEADDRESS 0x30800000U -#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) -#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) - -#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + // timer +#define GENERIC_TIMER_NS_IRQ_NUM 30 +#define GENERIC_TIMER_NS_CLK_FREQ 2000000 +#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ + + // UART + +#define FT_UART_NUM 4 +#define FT_UART_REG_LENGTH 0x18000 + +#define FT_UART0_ID 0 +#define FT_UART0_IRQ_NUM (85 + 30) +#define FT_UART0_BASE_ADDR 0x2800c000 +#define FT_UART0_CLK_FREQ_HZ 100000000 + +#define FT_UART1_ID 1 +#define FT_UART1_IRQ_NUM (86 + 30) +#define FT_UART1_BASE_ADDR 0x2800d000 +#define FT_UART1_CLK_FREQ_HZ 100000000 + +#define FT_UART2_ID 2 +#define FT_UART2_IRQ_NUM (87 + 30) +#define FT_UART2_BASE_ADDR 0x2800e000 +#define FT_UART2_CLK_FREQ_HZ 100000000 + +#define FT_UART3_BASE_ADDR 0x2800f000 +#define FT_UART3_ID 3 +#define FT_UART3_IRQ_NUM (88 + 30) +#define FT_UART3_CLK_FREQ_HZ 100000000 + +#define FT_STDOUT_base_address FT_UART1_BASE_ADDR +#define FT_STDIN_base_address FT_UART1_BASE_ADDR + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000 + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ +#define SGI_INT_MAX 16 +#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ + +#define GICV3_BASEADDRESS 0x30800000U +#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) +#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) + +#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.c b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.c index 804e06b78..0b42d82d8 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.c +++ b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.c @@ -1,38 +1,38 @@ -#include "_cpu.h" - -u32 GetCpuId(void) -{ - u32 affinity = GetAffinity(); - - switch (affinity & 0xfff) - { - case 0: - return 0; - case 1: - return 1; - case 0x100: - return 2; - case 0x101: - return 3; - default: - return 0; - } - return 0; -} - -u64 GetCpuCluster(u32 cpu_id) -{ - switch (cpu_id) - { - case 0: - return 0; - case 1: - return 1; - case 2: - return 0x100; - case 3: - return 0x101; - default: - return 0; - } -} +#include "_cpu.h" + +u32 GetCpuId(void) +{ + u32 affinity = GetAffinity(); + + switch (affinity & 0xfff) + { + case 0: + return 0; + case 1: + return 1; + case 0x100: + return 2; + case 0x101: + return 3; + default: + return 0; + } + return 0; +} + +u64 GetCpuCluster(u32 cpu_id) +{ + switch (cpu_id) + { + case 0: + return 0; + case 1: + return 1; + case 2: + return 0x100; + case 3: + return 0x101; + default: + return 0; + } +} diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.h b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.h index 8c871b15a..f398e12fa 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.h +++ b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu.h @@ -1,18 +1,18 @@ -#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H -#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - u32 GetAffinity(void); - u32 GetCpuId(void); - u64 GetCpuCluster(u32 cpu_id); -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H +#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + u32 GetAffinity(void); + u32 GetCpuId(void); + u64 GetCpuCluster(u32 cpu_id); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu_asm.S b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu_asm.S index d86b82cf8..0ad74640f 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/_cpu_asm.S +++ b/bsp/arch/armv8/aarch64/platform/ft2004/_cpu_asm.S @@ -1,10 +1,10 @@ - -// ------------------------------------------------------------ - .global GetAffinity - //uint32_t GetAffinity(void); - .type GetAffinity, @function -GetAffinity: - MRS x0, MPIDR_EL1 - UBFX x1, x0, #32, #8 - BFI w0, w1, #24, #8 - RET + +// ------------------------------------------------------------ + .global GetAffinity + //uint32_t GetAffinity(void); + .type GetAffinity, @function +GetAffinity: + MRS x0, MPIDR_EL1 + UBFX x1, x0, #32, #8 + BFI w0, w1, #24, #8 + RET diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.c b/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.c index c0eba7c57..93ba81388 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.c +++ b/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.c @@ -1,20 +1,20 @@ -#include "early_uart.h" - -void OutByte(s8 byte) -{ - // FtOut32(0x28001000, (u32)byte); - while ((FtIn32(0x28001018) & 0x20) == 0x20) - { - /* code */ - } - - FtOut32(0x28001000, (u32)byte); -} - -char GetByte(void) -{ - while ((FtIn32(0x28001018) & 0x10) == 0x10) - ; - - return (char)FtIn32(0x28001000); -} +#include "early_uart.h" + +void OutByte(s8 byte) +{ + // FtOut32(0x28001000, (u32)byte); + while ((FtIn32(0x28001018) & 0x20) == 0x20) + { + /* code */ + } + + FtOut32(0x28001000, (u32)byte); +} + +char GetByte(void) +{ + while ((FtIn32(0x28001018) & 0x10) == 0x10) + ; + + return (char)FtIn32(0x28001000); +} diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.h b/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.h index 52989dcde..c4b5462b1 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.h +++ b/bsp/arch/armv8/aarch64/platform/ft2004/early_uart.h @@ -1,18 +1,18 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - - void OutByte(s8 byte); - char GetByte(void); -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + + void OutByte(s8 byte); + char GetByte(void); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/parameters.c b/bsp/arch/armv8/aarch64/platform/ft2004/parameters.c index bb0a0b154..ceaec8694 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/parameters.c +++ b/bsp/arch/armv8/aarch64/platform/ft2004/parameters.c @@ -1,35 +1,35 @@ -#include "mmu.h" -#include "ft_types.h" - -const struct arm_mmu_region mmu_regions[] = { - MMU_REGION_FLAT_ENTRY("DEVICE_REGION", - 0X00, 0x40000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", - 0x40000000, 0x10000000, - MT_DEVICE_nGnRnE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0x50000000, 0x30000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0x80000000, 0x80000000, - MT_NORMAL | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0X1000000000, 0X1000000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0X2000000000, 0X2000000000, - MT_NORMAL | MT_RW | MT_NS), -}; - -const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); - -const struct arm_mmu_config mmu_config = { - .num_regions = mmu_regions_size, - .mmu_regions = mmu_regions, +#include "mmu.h" +#include "ft_types.h" + +const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("DEVICE_REGION", + 0X00, 0x40000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", + 0x40000000, 0x10000000, + MT_DEVICE_nGnRnE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0x50000000, 0x30000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0x80000000, 0x80000000, + MT_NORMAL | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0X1000000000, 0X1000000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0X2000000000, 0X2000000000, + MT_NORMAL | MT_RW | MT_NS), +}; + +const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); + +const struct arm_mmu_config mmu_config = { + .num_regions = mmu_regions_size, + .mmu_regions = mmu_regions, }; \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/ft2004/parameters.h b/bsp/arch/armv8/aarch64/platform/ft2004/parameters.h index f3c65f863..8c5cd62e3 100644 --- a/bsp/arch/armv8/aarch64/platform/ft2004/parameters.h +++ b/bsp/arch/armv8/aarch64/platform/ft2004/parameters.h @@ -1,69 +1,83 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - // timer - // timer -#define GENERIC_TIMER_NS_IRQ_NUM 30 -#define GENERIC_TIMER_CLK_FREQ 48000000 -#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ - - // UART - -#define FT_UART_NUM 4 -#define FT_UART_REG_LENGTH 0x18000 - -#define FT_UART0_ID 0 -#define FT_UART0_IRQ_NUM 38 -#define FT_UART0_BASE_ADDR 0x28000000 -#define FT_UART0_CLK_FREQ_HZ 48000000 - -#define FT_UART1_ID 1 -#define FT_UART1_IRQ_NUM 39 -#define FT_UART1_BASE_ADDR 0x28001000 -#define FT_UART1_CLK_FREQ_HZ 48000000 - -#define FT_UART2_ID 2 -#define FT_UART2_IRQ_NUM 40 -#define FT_UART2_BASE_ADDR 0x28002000 -#define FT_UART2_CLK_FREQ_HZ 48000000 - -#define FT_UART3_BASE_ADDR 0x28003000 -#define FT_UART3_ID 3 -#define FT_UART3_IRQ_NUM 41 -#define FT_UART3_CLK_FREQ_HZ 48000000 - -#define FT_STDOUT_base_address FT_UART1_BASE_ADDR -#define FT_STDIN_base_address FT_UART1_BASE_ADDR - -/****** GIC v3 *****/ -#define FT_GICV3_INSTANCES_NUM 1U -#define GICV3_REG_LENGTH 0x00009000 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define GICV3_MAX_INTR_PRIO_VAL 240U -#define GICV3_INTR_PRIO_MASK 0x000000f0U - -#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ -#define SGI_INT_MAX 16 -#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ -#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ -#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ - -#define GICV3_BASEADDRESS 0x29900000U -#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) -#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) - -#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + // timer + // timer +#define GENERIC_TIMER_NS_IRQ_NUM 30 +#define GENERIC_TIMER_CLK_FREQ 48000000 +#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ + + // UART + +#define FT_UART_NUM 4 +#define FT_UART_REG_LENGTH 0x18000 + +#define FT_UART0_ID 0 +#define FT_UART0_IRQ_NUM 38 +#define FT_UART0_BASE_ADDR 0x28000000 +#define FT_UART0_CLK_FREQ_HZ 48000000 + +#define FT_UART1_ID 1 +#define FT_UART1_IRQ_NUM 39 +#define FT_UART1_BASE_ADDR 0x28001000 +#define FT_UART1_CLK_FREQ_HZ 48000000 + +#define FT_UART2_ID 2 +#define FT_UART2_IRQ_NUM 40 +#define FT_UART2_BASE_ADDR 0x28002000 +#define FT_UART2_CLK_FREQ_HZ 48000000 + +#define FT_UART3_BASE_ADDR 0x28003000 +#define FT_UART3_ID 3 +#define FT_UART3_IRQ_NUM 41 +#define FT_UART3_CLK_FREQ_HZ 48000000 + +#define FT_STDOUT_base_address FT_UART1_BASE_ADDR +#define FT_STDIN_base_address FT_UART1_BASE_ADDR + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000 + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ +#define SGI_INT_MAX 16 +#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ + +#define GICV3_BASEADDRESS 0x29900000U +#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) +#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) + +#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM + + // gpio + +#define GPIO0_BASE (0X28004000) +#define GPIO1_BASE (0X28005000) + +#define F_GPIO_TOTAL_LINE (16) +#define F_GPIO_GROUP_NUM (2) + +#define F_GPIO_PORT_MAX_NUM (2) +#define F_GPIO_PIN_MAX_NUM (16) + +#define F_GPIO0_INTR_IRQ (42) // gpio0 irq number +#define F_GPIO1_INTR_IRQ (43) // gpio1 irq number + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.c b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.c index ce93d6d11..92b9996a9 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.c +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.c @@ -1,21 +1,21 @@ -#include "_cpu.h" - -u32 GetCpuId(void) -{ - u32 affinity = GetAffinity(); - - switch (affinity & 0xfff) - { - case 0: - return 0; - case 1: - return 1; - case 2: - return 2; - case 3: - return 3; - default: - return 0; - } - return 0; +#include "_cpu.h" + +u32 GetCpuId(void) +{ + u32 affinity = GetAffinity(); + + switch (affinity & 0xfff) + { + case 0: + return 0; + case 1: + return 1; + case 2: + return 2; + case 3: + return 3; + default: + return 0; + } + return 0; } \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.h b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.h index 9ca1bb806..e5b5203ad 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.h +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu.h @@ -1,17 +1,17 @@ -#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H -#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - u32 GetAffinity(void); - u32 GetCpuId(void); -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H +#define BSP_ARCH_ARMV8_ARRCH64_PLATFORM_FT2004_CPU_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + u32 GetAffinity(void); + u32 GetCpuId(void); +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu_asm.S b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu_asm.S index d86b82cf8..0ad74640f 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu_asm.S +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_cpu_asm.S @@ -1,10 +1,10 @@ - -// ------------------------------------------------------------ - .global GetAffinity - //uint32_t GetAffinity(void); - .type GetAffinity, @function -GetAffinity: - MRS x0, MPIDR_EL1 - UBFX x1, x0, #32, #8 - BFI w0, w1, #24, #8 - RET + +// ------------------------------------------------------------ + .global GetAffinity + //uint32_t GetAffinity(void); + .type GetAffinity, @function +GetAffinity: + MRS x0, MPIDR_EL1 + UBFX x1, x0, #32, #8 + BFI w0, w1, #24, #8 + RET diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_mmu_global.c b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_mmu_global.c index bb0a0b154..ceaec8694 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_mmu_global.c +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_mmu_global.c @@ -1,35 +1,35 @@ -#include "mmu.h" -#include "ft_types.h" - -const struct arm_mmu_region mmu_regions[] = { - MMU_REGION_FLAT_ENTRY("DEVICE_REGION", - 0X00, 0x40000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", - 0x40000000, 0x10000000, - MT_DEVICE_nGnRnE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0x50000000, 0x30000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0x80000000, 0x80000000, - MT_NORMAL | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("PCIE_REGION", - 0X1000000000, 0X1000000000, - MT_DEVICE_nGnRE | MT_RW | MT_NS), - - MMU_REGION_FLAT_ENTRY("DDR_REGION", - 0X2000000000, 0X2000000000, - MT_NORMAL | MT_RW | MT_NS), -}; - -const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); - -const struct arm_mmu_config mmu_config = { - .num_regions = mmu_regions_size, - .mmu_regions = mmu_regions, +#include "mmu.h" +#include "ft_types.h" + +const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("DEVICE_REGION", + 0X00, 0x40000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_CONFIG_REGION", + 0x40000000, 0x10000000, + MT_DEVICE_nGnRnE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0x50000000, 0x30000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0x80000000, 0x80000000, + MT_NORMAL | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("PCIE_REGION", + 0X1000000000, 0X1000000000, + MT_DEVICE_nGnRE | MT_RW | MT_NS), + + MMU_REGION_FLAT_ENTRY("DDR_REGION", + 0X2000000000, 0X2000000000, + MT_NORMAL | MT_RW | MT_NS), +}; + +const uint32_t mmu_regions_size = ARRAY_SIZE(mmu_regions); + +const struct arm_mmu_config mmu_config = { + .num_regions = mmu_regions_size, + .mmu_regions = mmu_regions, }; \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_parameters.h b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_parameters.h index 13eee60a0..5046e4b4e 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_parameters.h +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/_parameters.h @@ -1,22 +1,22 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -// timer -#define GENERIC_TIMER_CLK_FREQ 48000000 -#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ - - // gicv3 -#define GICV3_BASEADDRESS 0x08000000 -#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) -#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x10000) - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +// timer +#define GENERIC_TIMER_CLK_FREQ 48000000 +#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ + + // gicv3 +#define GICV3_BASEADDRESS 0x08000000 +#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) +#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x10000) + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.c b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.c index fc2b66bd6..0d8f6d3de 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.c +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.c @@ -1,41 +1,41 @@ -#include "early_uart.h" - -volatile unsigned int *const UART0DR = (unsigned int *)0x09000000; -volatile unsigned int *const UART0FR = (unsigned int *)0x09000018; - -void OutByte(s8 c) -{ - while ((*UART0FR) & (1 << 5)) - { - } - *UART0DR = c; /* Transmit char */ -} - -void uart_putc(const char c) -{ - // Wait for UART to become ready to transmit. - while ((*UART0FR) & (1 << 5)) - { - } - *UART0DR = c; /* Transmit char */ -} - -void uart_puthex(uint64_t n) -{ - const char *hexdigits = "0123456789ABCDEF"; - - uart_putc('0'); - uart_putc('x'); - for (int i = 60; i >= 0; i -= 4) - { - uart_putc(hexdigits[(n >> i) & 0xf]); - if (i == 32) - uart_putc(' '); - } -} - -void uart_puts(const char *s) -{ - for (int i = 0; s[i] != '\0'; i++) - uart_putc((unsigned char)s[i]); -} +#include "early_uart.h" + +volatile unsigned int *const UART0DR = (unsigned int *)0x09000000; +volatile unsigned int *const UART0FR = (unsigned int *)0x09000018; + +void OutByte(s8 c) +{ + while ((*UART0FR) & (1 << 5)) + { + } + *UART0DR = c; /* Transmit char */ +} + +void uart_putc(const char c) +{ + // Wait for UART to become ready to transmit. + while ((*UART0FR) & (1 << 5)) + { + } + *UART0DR = c; /* Transmit char */ +} + +void uart_puthex(uint64_t n) +{ + const char *hexdigits = "0123456789ABCDEF"; + + uart_putc('0'); + uart_putc('x'); + for (int i = 60; i >= 0; i -= 4) + { + uart_putc(hexdigits[(n >> i) & 0xf]); + if (i == 32) + uart_putc(' '); + } +} + +void uart_puts(const char *s) +{ + for (int i = 0; s[i] != '\0'; i++) + uart_putc((unsigned char)s[i]); +} diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.h b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.h index c717c9758..97d38fb62 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.h +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/early_uart.h @@ -1,18 +1,18 @@ -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - - void OutByte(s8 byte); - -#ifdef __cplusplus -} -#endif - +#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H +#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + + void OutByte(s8 byte); + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/monitor_uart.c_old b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/monitor_uart.c_old index 7c38722d6..6282f8f75 100644 --- a/bsp/arch/armv8/aarch64/platform/qemu_aarch64/monitor_uart.c_old +++ b/bsp/arch/armv8/aarch64/platform/qemu_aarch64/monitor_uart.c_old @@ -1,55 +1,55 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-31 18:50:49 - * @LastEditTime: 2021-05-31 18:59:05 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include -#include -#include -#include "ft_types.h" - -volatile unsigned int *const UART0DR = (unsigned int *)0x09000000; -volatile unsigned int *const UART0FR = (unsigned int *)0x09000018; - -void OutByte(char c) -{ - while ((*UART0FR) & (1 << 5)) - { - } - *UART0DR = c; /* Transmit char */ -} - -void _putc(const char c) -{ - // Wait for UART to become ready to transmit. - while ((*UART0FR) & (1 << 5)) - { - } - *UART0DR = c; /* Transmit char */ -} - -void putc_polled(const char *s) -{ - for (int i = 0; s[i] != '\0'; i++) - _putc((unsigned char)s[i]); -} - -char getchar_polled(void) -{ - return 0; -} - -void UartInit(void) -{ - setvbuf(stdout, NULL, _IONBF, 0); - setvbuf(stdin, NULL, _IONBF, 0); -} +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-31 18:50:49 + * @LastEditTime: 2021-05-31 18:59:05 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include +#include +#include +#include "ft_types.h" + +volatile unsigned int *const UART0DR = (unsigned int *)0x09000000; +volatile unsigned int *const UART0FR = (unsigned int *)0x09000018; + +void OutByte(char c) +{ + while ((*UART0FR) & (1 << 5)) + { + } + *UART0DR = c; /* Transmit char */ +} + +void _putc(const char c) +{ + // Wait for UART to become ready to transmit. + while ((*UART0FR) & (1 << 5)) + { + } + *UART0DR = c; /* Transmit char */ +} + +void putc_polled(const char *s) +{ + for (int i = 0; s[i] != '\0'; i++) + _putc((unsigned char)s[i]); +} + +char getchar_polled(void) +{ + return 0; +} + +void UartInit(void) +{ + setvbuf(stdout, NULL, _IONBF, 0); + setvbuf(stdin, NULL, _IONBF, 0); +} diff --git a/bsp/arch/armv8/aarch64/psw.c b/bsp/arch/armv8/aarch64/psw.c index 3d060a241..3fdf4a02d 100644 --- a/bsp/arch/armv8/aarch64/psw.c +++ b/bsp/arch/armv8/aarch64/psw.c @@ -1,34 +1,34 @@ -/* -*- mode: c; coding:utf-8 -*- */ -/**********************************************************************/ -/* OS kernel sample */ -/* Copyright 2014 Takeharu KATO */ -/* */ -/* Processor Status Word */ -/* */ -/**********************************************************************/ -#include -#include "aarch64.h" -#include "psw.h" - -/** Disable interrupt at CPU level -    @ param [in] pswp Processor status word return area before interrupt disabled - */ -void psw_disable_and_save_interrupt(psw_t *pswp) -{ - psw_t psw; - - __save_psw(psw); - psw_disable_interrupt(); - *pswp = psw; -} - -/** Restore interrupt status at CPU level - @ param [in] pswp Processor status word return area - */ -void psw_restore_interrupt(psw_t *pswp) -{ - psw_t psw; - - psw = *pswp; - __restore_psw(psw); -} +/* -*- mode: c; coding:utf-8 -*- */ +/**********************************************************************/ +/* OS kernel sample */ +/* Copyright 2014 Takeharu KATO */ +/* */ +/* Processor Status Word */ +/* */ +/**********************************************************************/ +#include +#include "aarch64.h" +#include "psw.h" + +/** Disable interrupt at CPU level +    @ param [in] pswp Processor status word return area before interrupt disabled + */ +void psw_disable_and_save_interrupt(psw_t *pswp) +{ + psw_t psw; + + __save_psw(psw); + psw_disable_interrupt(); + *pswp = psw; +} + +/** Restore interrupt status at CPU level + @ param [in] pswp Processor status word return area + */ +void psw_restore_interrupt(psw_t *pswp) +{ + psw_t psw; + + psw = *pswp; + __restore_psw(psw); +} diff --git a/bsp/arch/armv8/aarch64/psw.h b/bsp/arch/armv8/aarch64/psw.h index 59c2fa91d..fdcd0a91b 100644 --- a/bsp/arch/armv8/aarch64/psw.h +++ b/bsp/arch/armv8/aarch64/psw.h @@ -1,41 +1,41 @@ -/**********************************************************************/ -/* OS kernel sample */ -/* Copyright 2014 Takeharu KATO */ -/* */ -/* Processor Status Word */ -/* */ -/**********************************************************************/ -#if !defined(_PSW_H) -#define _PSW_H - -#include "aarch64.h" - -typedef uint64_t psw_t; /* Processor status word */ - -/* Allow interrupt to CPU unconditionally */ -#define psw_enable_interrupt() INTERRUPT_ENABLE() - -/* Unconditionally prohibit interrupt to CPU 锟�*/ -#define psw_disable_interrupt() INTERRUPT_DISABLE() - -/** Save the PSW -锟斤拷锟� @ param [in] psw PSW storage variable -锟�*/ -#define __save_psw(psw) \ - do \ - { \ - psw = raw_read_daif(); \ - } while (0) - -/** Restore PSW -锟斤拷锟� @ param [in] psw PSW storage variable - */ -#define __restore_psw(psw) \ - do \ - { \ - raw_write_daif(psw); \ - } while (0) - -void psw_disable_and_save_interrupt(psw_t *); -void psw_restore_interrupt(psw_t *); -#endif /* _PSW_H */ +/**********************************************************************/ +/* OS kernel sample */ +/* Copyright 2014 Takeharu KATO */ +/* */ +/* Processor Status Word */ +/* */ +/**********************************************************************/ +#if !defined(_PSW_H) +#define _PSW_H + +#include "aarch64.h" + +typedef uint64_t psw_t; /* Processor status word */ + +/* Allow interrupt to CPU unconditionally */ +#define psw_enable_interrupt() INTERRUPT_ENABLE() + +/* Unconditionally prohibit interrupt to CPU 锟�*/ +#define psw_disable_interrupt() INTERRUPT_DISABLE() + +/** Save the PSW +锟斤拷锟� @ param [in] psw PSW storage variable +锟�*/ +#define __save_psw(psw) \ + do \ + { \ + psw = raw_read_daif(); \ + } while (0) + +/** Restore PSW +锟斤拷锟� @ param [in] psw PSW storage variable + */ +#define __restore_psw(psw) \ + do \ + { \ + raw_write_daif(psw); \ + } while (0) + +void psw_disable_and_save_interrupt(psw_t *); +void psw_restore_interrupt(psw_t *); +#endif /* _PSW_H */ diff --git a/bsp/arch/common/kernel.h b/bsp/arch/common/kernel.h index 0e2a2a3fc..8d247f033 100644 --- a/bsp/arch/common/kernel.h +++ b/bsp/arch/common/kernel.h @@ -1,164 +1,164 @@ -#ifndef KERNEL_H -#define KERNEL_H - -#ifdef __ASSEMBLY__ -#define _AC(X, Y) X -#define _AT(T, X) X -#else -#define __AC(X, Y) (X##Y) -#define _AC(X, Y) __AC(X, Y) -#define _AT(T, X) ((T)(X)) -#endif - -#define _UL(x) (_AC(x, UL)) -#define _ULL(x) (_AC(x, ULL)) - -#define _BITUL(x) (_UL(1) << (x)) -#define _BITULL(x) (_ULL(1) << (x)) - -#define UL(x) (_UL(x)) -#define ULL(x) (_ULL(x)) - -#define min(x, y) ( \ - { \ - typeof(x) _min1 = (x); \ - typeof(y) _min2 = (y); \ - (void)(&_min1 == &_min2); \ - _min1 < _min2 ? _min1 : _min2; \ - }) - -#define max(x, y) ( \ - { \ - typeof(x) _max1 = (x); \ - typeof(y) _max2 = (y); \ - (void)(&_max1 == &_max2); \ - _max1 > _max2 ? _max1 : _max2; \ - }) - -#define min3(x, y, z) min((typeof(x))min(x, y), z) -#define max3(x, y, z) max((typeof(x))max(x, y), z) - -/** - * clamp - return a value clamped to a given range with strict typechecking - * @val: current value - * @lo: lowest allowable value - * @hi: highest allowable value - * - * This macro does strict typechecking of @lo/@hi to make sure they are of the - * same type as @val. See the unnecessary pointer comparisons. - */ -#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi) - -/** - * do_div - returns 2 values: calculate remainder and update new dividend - * @n: uint64_t dividend (will be updated) - * @base: uint32_t divisor - * - * Summary: - * ``uint32_t remainder = n % base;`` - * ``n = n / base;`` - * - * Return: (uint32_t)remainder - * - * NOTE: macro parameter @n is evaluated multiple times, - * beware of side effects! - */ -#define do_div(n, base) ( \ - { \ - uint32_t __base = (base); \ - uint32_t __rem; \ - __rem = ((uint64_t)(n)) % __base; \ - (n) = ((uint64_t)(n)) / __base; \ - __rem; \ - }) - -/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */ -#define roundup(x, y) ( \ - { \ - const typeof(y) __y = y; \ - (((x) + (__y - 1)) / __y) * __y; \ - }) -#define rounddown(x, y) ( \ - { \ - typeof(x) __x = (x); \ - __x - (__x % (y)); \ - }) - -#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) - -#define BIT(nr) (1UL << (nr)) -#define BIT_ULL(nr) (1ULL << (nr)) -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) -#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) -#define BITS_PER_BYTE 8 -#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) -#define BITS_PER_LONG 32 - -/* - * Create a contiguous bitmask starting at bit position @l and ending at - * position @h. For example - * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. - */ -#define GENMASK(h, l) \ - (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) - -#define SZ_1 0x00000001 -#define SZ_2 0x00000002 -#define SZ_4 0x00000004 -#define SZ_8 0x00000008 -#define SZ_16 0x00000010 -#define SZ_32 0x00000020 -#define SZ_64 0x00000040 -#define SZ_128 0x00000080 -#define SZ_256 0x00000100 -#define SZ_512 0x00000200 - -#define SZ_1K 0x00000400 -#define SZ_2K 0x00000800 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -/** - * upper_32_bits - return bits 32-63 of a number - * @n: the number we're accessing - * - * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress - * the "right shift count >= width of type" warning when that quantity is - * 32-bits. - */ -#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) - -/** - * lower_32_bits - return bits 0-31 of a number - * @n: the number we're accessing - */ -#define lower_32_bits(n) ((uint32_t)((n)&0xffffffff)) -#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a)-1)) == 0) - -#ifndef __aligned -#define __aligned(x) __attribute__((__aligned__(x))) -#endif - +#ifndef KERNEL_H +#define KERNEL_H + +#ifdef __ASSEMBLY__ +#define _AC(X, Y) X +#define _AT(T, X) X +#else +#define __AC(X, Y) (X##Y) +#define _AC(X, Y) __AC(X, Y) +#define _AT(T, X) ((T)(X)) +#endif + +#define _UL(x) (_AC(x, UL)) +#define _ULL(x) (_AC(x, ULL)) + +#define _BITUL(x) (_UL(1) << (x)) +#define _BITULL(x) (_ULL(1) << (x)) + +#define UL(x) (_UL(x)) +#define ULL(x) (_ULL(x)) + +#define min(x, y) ( \ + { \ + typeof(x) _min1 = (x); \ + typeof(y) _min2 = (y); \ + (void)(&_min1 == &_min2); \ + _min1 < _min2 ? _min1 : _min2; \ + }) + +#define max(x, y) ( \ + { \ + typeof(x) _max1 = (x); \ + typeof(y) _max2 = (y); \ + (void)(&_max1 == &_max2); \ + _max1 > _max2 ? _max1 : _max2; \ + }) + +#define min3(x, y, z) min((typeof(x))min(x, y), z) +#define max3(x, y, z) max((typeof(x))max(x, y), z) + +/** + * clamp - return a value clamped to a given range with strict typechecking + * @val: current value + * @lo: lowest allowable value + * @hi: highest allowable value + * + * This macro does strict typechecking of @lo/@hi to make sure they are of the + * same type as @val. See the unnecessary pointer comparisons. + */ +#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi) + +/** + * do_div - returns 2 values: calculate remainder and update new dividend + * @n: uint64_t dividend (will be updated) + * @base: uint32_t divisor + * + * Summary: + * ``uint32_t remainder = n % base;`` + * ``n = n / base;`` + * + * Return: (uint32_t)remainder + * + * NOTE: macro parameter @n is evaluated multiple times, + * beware of side effects! + */ +#define do_div(n, base) ( \ + { \ + uint32_t __base = (base); \ + uint32_t __rem; \ + __rem = ((uint64_t)(n)) % __base; \ + (n) = ((uint64_t)(n)) / __base; \ + __rem; \ + }) + +/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */ +#define roundup(x, y) ( \ + { \ + const typeof(y) __y = y; \ + (((x) + (__y - 1)) / __y) * __y; \ + }) +#define rounddown(x, y) ( \ + { \ + typeof(x) __x = (x); \ + __x - (__x % (y)); \ + }) + +#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) + +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) +#define BITS_PER_BYTE 8 +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) +#define BITS_PER_LONG 32 + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define SZ_1 0x00000001 +#define SZ_2 0x00000002 +#define SZ_4 0x00000004 +#define SZ_8 0x00000008 +#define SZ_16 0x00000010 +#define SZ_32 0x00000020 +#define SZ_64 0x00000040 +#define SZ_128 0x00000080 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + +#define SZ_1K 0x00000400 +#define SZ_2K 0x00000800 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +/** + * upper_32_bits - return bits 32-63 of a number + * @n: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >= width of type" warning when that quantity is + * 32-bits. + */ +#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) + +/** + * lower_32_bits - return bits 0-31 of a number + * @n: the number we're accessing + */ +#define lower_32_bits(n) ((uint32_t)((n)&0xffffffff)) +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a)-1)) == 0) + +#ifndef __aligned +#define __aligned(x) __attribute__((__aligned__(x))) +#endif + #endif \ No newline at end of file diff --git a/bsp/arch/common/linkage.h b/bsp/arch/common/linkage.h index e3608e738..edc4141cc 100644 --- a/bsp/arch/common/linkage.h +++ b/bsp/arch/common/linkage.h @@ -1,68 +1,68 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * U-Boot - linkage.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - */ - -#ifndef _LINUX_LINKAGE_H -#define _LINUX_LINKAGE_H - -/* Some toolchains use other characters (e.g. '`') to mark new line in macro */ -#ifndef ASM_NL -#define ASM_NL ; -#endif - -#ifdef __cplusplus -#define CPP_ASMLINKAGE extern "C" -#else -#define CPP_ASMLINKAGE -#endif - -#ifndef asmlinkage -#define asmlinkage CPP_ASMLINKAGE -#endif - -#define SYMBOL_NAME_STR(X) #X -#define SYMBOL_NAME(X) X -#ifdef __STDC__ -#define SYMBOL_NAME_LABEL(X) X##: -#else -#define SYMBOL_NAME_LABEL(X) X: -#endif - -#ifndef __ALIGN -#define __ALIGN .align 4 -#endif - -#ifndef __ALIGN_STR -#define __ALIGN_STR ".align 4" -#endif - -#define ALIGN __ALIGN -#define ALIGN_STR __ALIGN_STR - -#define LENTRY(name) \ - ALIGN ASM_NL \ - SYMBOL_NAME_LABEL(name) - -#define ENTRY(name) \ - .globl SYMBOL_NAME(name) ASM_NL \ - LENTRY(name) - -#define WEAK(name) \ - .weak SYMBOL_NAME(name) ASM_NL \ - LENTRY(name) - -#ifndef END -#define END(name) \ - .size name, .-name -#endif - -#ifndef ENDPROC -#define ENDPROC(name) \ - .type name STT_FUNC ASM_NL \ - END(name) -#endif - -#endif +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * U-Boot - linkage.h + * + * Copyright (c) 2005-2007 Analog Devices Inc. + */ + +#ifndef _LINUX_LINKAGE_H +#define _LINUX_LINKAGE_H + +/* Some toolchains use other characters (e.g. '`') to mark new line in macro */ +#ifndef ASM_NL +#define ASM_NL ; +#endif + +#ifdef __cplusplus +#define CPP_ASMLINKAGE extern "C" +#else +#define CPP_ASMLINKAGE +#endif + +#ifndef asmlinkage +#define asmlinkage CPP_ASMLINKAGE +#endif + +#define SYMBOL_NAME_STR(X) #X +#define SYMBOL_NAME(X) X +#ifdef __STDC__ +#define SYMBOL_NAME_LABEL(X) X##: +#else +#define SYMBOL_NAME_LABEL(X) X: +#endif + +#ifndef __ALIGN +#define __ALIGN .align 4 +#endif + +#ifndef __ALIGN_STR +#define __ALIGN_STR ".align 4" +#endif + +#define ALIGN __ALIGN +#define ALIGN_STR __ALIGN_STR + +#define LENTRY(name) \ + ALIGN ASM_NL \ + SYMBOL_NAME_LABEL(name) + +#define ENTRY(name) \ + .globl SYMBOL_NAME(name) ASM_NL \ + LENTRY(name) + +#define WEAK(name) \ + .weak SYMBOL_NAME(name) ASM_NL \ + LENTRY(name) + +#ifndef END +#define END(name) \ + .size name, .-name +#endif + +#ifndef ENDPROC +#define ENDPROC(name) \ + .type name STT_FUNC ASM_NL \ + END(name) +#endif + +#endif diff --git a/bsp/arch/common/macro.h b/bsp/arch/common/macro.h index 1ab6ea046..baf014d9f 100644 --- a/bsp/arch/common/macro.h +++ b/bsp/arch/common/macro.h @@ -1,24 +1,24 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/asm-arm/macro.h - * - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - */ - -#ifndef __ASM_ARM_MACRO_H__ -#define __ASM_ARM_MACRO_H__ - -/* - * Branch according to exception level - */ -.macro switch_el, xreg, el3_label, el2_label, el1_label - mrs \xreg, CurrentEL - cmp \xreg, 0xc - b.eq \el3_label - cmp \xreg, 0x8 - b.eq \el2_label - cmp \xreg, 0x4 - b.eq \el1_label -.endm - -#endif /* __ASM_ARM_MACRO_H__ */ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/asm-arm/macro.h + * + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + */ + +#ifndef __ASM_ARM_MACRO_H__ +#define __ASM_ARM_MACRO_H__ + +/* + * Branch according to exception level + */ +.macro switch_el, xreg, el3_label, el2_label, el1_label + mrs \xreg, CurrentEL + cmp \xreg, 0xc + b.eq \el3_label + cmp \xreg, 0x8 + b.eq \el2_label + cmp \xreg, 0x4 + b.eq \el1_label +.endm + +#endif /* __ASM_ARM_MACRO_H__ */ diff --git a/bsp/bsp.mk b/bsp/bsp.mk index 3dbe7b323..d46206e68 100644 --- a/bsp/bsp.mk +++ b/bsp/bsp.mk @@ -1,111 +1,119 @@ -CUR_DIR := $(SDK_ROOT)/bsp - -SRC_DIR += $(CUR_DIR)/common \ - $(CUR_DIR)/arch/common -INC_DIR += $(CUR_DIR)/common \ - $(CUR_DIR)/arch/common - -ifndef CONFIG_USE_CACHE - EXCL_SRC += $(CUR_DIR)/common/cache.c -endif - -ifndef CONFIG_USE_MMU - EXCL_SRC += $(CUR_DIR)/common/mmu.c -endif - -##########################arch#################################### -ifdef CONFIG_TARGET_ARMV8_AARCH64 - - -ifdef CONFIG_TARGET_AARCH64_QEMU -SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/qemu_aarch64 -INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/qemu_aarch64 -endif - -ifdef CONFIG_TARGET_F2000_4 -SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/ft2004 -INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/ft2004 -endif - -ifdef CONFIG_TARGET_E2000 -SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/e2000 -INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/e2000 -endif - -SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64 \ - $(CUR_DIR)/arch/armv8/aarch64/gcc -INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/gcc \ - $(CUR_DIR)/arch/armv8/aarch64 -endif #CONFIG_TARGET_ARMV8_AARCH64 - -ifdef CONFIG_TARGET_ARMV8_AARCH32 - SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32 \ - $(CUR_DIR)/arch/armv8/aarch32/gcc - INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/gcc \ - $(CUR_DIR)/arch/armv8/aarch32 - - ifdef CONFIG_TARGET_F2000_4 - SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/ft2004 - INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/ft2004 - endif #CONFIG_TARGET_F2000_4 - - ifdef CONFIG_TARGET_E2000 - SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/e2000 - INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/e2000 - endif #CONFIG_TARGET_E2000 - - ifdef CONFIG_TARGET_AARCH32_QEMU - SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/qemu - INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/qemu - endif #CONFIG_TARGET_AARCH32_QEMU - -endif #CONFIG_TARGET_ARMV8_AARCH32 - -ifdef CONFIG_TARGET_ARMV7 - SRC_DIR += $(CUR_DIR)/arch/armv7/gcc -endif #CONFIG_TARGET_ARMV7 - -##########################drivers#################################### -# gic - -ifdef CONFIG_EBABLE_GICV3 - -ifdef CONFIG_TARGET_ARMV8_AARCH64 - SRC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch64 - INC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch64 -endif - -ifdef CONFIG_TARGET_ARMV8_AARCH32 - SRC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch32 - INC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch32 -endif #CONFIG_TARGET_ARMV8_AARCH32 - -endif - -# timer -INC_DIR += $(CUR_DIR)/drivers/timer -ifdef CONFIG_ENABLE_QEMU_GTIMER -SRC_DIR += $(CUR_DIR)/drivers/timer/qemu_gtimer -endif - -# spi -ifdef CONFIG_USE_SPI -SRC_DIR += $(CUR_DIR)/drivers/spi -endif #CONFIG_USE_SPI - -# qspi -ifdef CONFIG_USE_QSPI -SRC_DIR += $(CUR_DIR)/drivers/qspi -endif #CONFIG_USE_QSPI - -# usart - -ifdef CONFIG_ENABLE_Pl011_UART -SRC_DIR += $(CUR_DIR)/drivers/usart/pl011_uart -INC_DIR += $(CUR_DIR)/drivers/usart/pl011_uart -endif #CONFIG_ENABLE_Pl011_UART - -ifdef CONFIG_ENABLE_QEMU_UART - SRC_DIR += $(CUR_DIR)/drivers/usart/qemu_uart - INC_DIR += $(CUR_DIR)/drivers/usart/qemu_uart -endif #CONFIG_ENABLE_QEMU_UART \ No newline at end of file +CUR_DIR := $(SDK_ROOT)/bsp + +SRC_DIR += $(CUR_DIR)/common \ + $(CUR_DIR)/arch/common +INC_DIR += $(CUR_DIR)/common \ + $(CUR_DIR)/arch/common + +ifndef CONFIG_USE_CACHE + EXCL_SRC += $(CUR_DIR)/common/cache.c +endif + +ifndef CONFIG_USE_MMU + EXCL_SRC += $(CUR_DIR)/common/mmu.c +endif + +##########################arch#################################### +ifdef CONFIG_TARGET_ARMV8_AARCH64 + + +ifdef CONFIG_TARGET_AARCH64_QEMU +SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/qemu_aarch64 +INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/qemu_aarch64 +endif + +ifdef CONFIG_TARGET_F2000_4 +SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/ft2004 +INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/ft2004 +endif + +ifdef CONFIG_TARGET_E2000 +SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/e2000 +INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/platform/e2000 +endif + +SRC_DIR += $(CUR_DIR)/arch/armv8/aarch64 \ + $(CUR_DIR)/arch/armv8/aarch64/gcc +INC_DIR += $(CUR_DIR)/arch/armv8/aarch64/gcc \ + $(CUR_DIR)/arch/armv8/aarch64 +endif #CONFIG_TARGET_ARMV8_AARCH64 + +ifdef CONFIG_TARGET_ARMV8_AARCH32 + SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32 \ + $(CUR_DIR)/arch/armv8/aarch32/gcc + INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/gcc \ + $(CUR_DIR)/arch/armv8/aarch32 + + ifdef CONFIG_TARGET_F2000_4 + SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/ft2004 + INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/ft2004 + endif #CONFIG_TARGET_F2000_4 + + ifdef CONFIG_TARGET_E2000 + SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/e2000 + INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/e2000 + endif #CONFIG_TARGET_E2000 + + ifdef CONFIG_TARGET_AARCH32_QEMU + SRC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/qemu + INC_DIR += $(CUR_DIR)/arch/armv8/aarch32/platform/qemu + endif #CONFIG_TARGET_AARCH32_QEMU + +endif #CONFIG_TARGET_ARMV8_AARCH32 + +ifdef CONFIG_TARGET_ARMV7 + SRC_DIR += $(CUR_DIR)/arch/armv7/gcc +endif #CONFIG_TARGET_ARMV7 + +##########################drivers#################################### +# gic + +ifdef CONFIG_EBABLE_GICV3 + +ifdef CONFIG_TARGET_ARMV8_AARCH64 + SRC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch64 + INC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch64 +endif + +ifdef CONFIG_TARGET_ARMV8_AARCH32 + SRC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch32 + INC_DIR += $(CUR_DIR)/drivers/gic/gicv3_arrch32 +endif #CONFIG_TARGET_ARMV8_AARCH32 + +endif + +# timer +INC_DIR += $(CUR_DIR)/drivers/timer +ifdef CONFIG_ENABLE_QEMU_GTIMER +SRC_DIR += $(CUR_DIR)/drivers/timer/qemu_gtimer +endif + +# spi +ifdef CONFIG_USE_SPI +SRC_DIR += $(CUR_DIR)/drivers/spi +endif #CONFIG_USE_SPI + +# qspi +ifdef CONFIG_USE_QSPI +SRC_DIR += $(CUR_DIR)/drivers/qspi +endif #CONFIG_USE_QSPI + +# usart + +ifdef CONFIG_ENABLE_Pl011_UART +SRC_DIR += $(CUR_DIR)/drivers/usart/pl011_uart +INC_DIR += $(CUR_DIR)/drivers/usart/pl011_uart +endif #CONFIG_ENABLE_Pl011_UART + +ifdef CONFIG_ENABLE_QEMU_UART + SRC_DIR += $(CUR_DIR)/drivers/usart/qemu_uart + INC_DIR += $(CUR_DIR)/drivers/usart/qemu_uart +endif #CONFIG_ENABLE_QEMU_UART + + +# gpio + +ifdef ENABLE_F_GPIO_UART + SRC_DIR += $(CUR_DIR)/drivers/gpio/f_gpio + INC_DIR += $(CUR_DIR)/drivers/gpio/f_gpio +endif \ No newline at end of file diff --git a/bsp/common/Kconfig b/bsp/common/Kconfig index d074d8650..f0354270b 100644 --- a/bsp/common/Kconfig +++ b/bsp/common/Kconfig @@ -1,28 +1,28 @@ -menu "Common Configuration" - -choice DEBUG_LOG_LEVEL - prompt "Debug Log Level" - default LOG_ERROR - help - VERBOS: Print bigger chunks of debugging information - DEBUG: Print extra information for debugging - INFO: Print necessary information messages - WARN: Print error conditions from which recovery measures have been taken - ERROR: Print critical errors, software module can not recover on its own - - config LOG_VERBOS - bool "VERBOS" - config LOG_DEBUG - bool "DEBUG" - config LOG_INFO - bool "INFO" - config LOG_WARN - bool "WARN" - config LOG_ERROR - bool "ERROR" - config LOG_NONE - bool "NONE" - -endchoice # DEBUG_LOG_LEVEL - +menu "Common Configuration" + +choice DEBUG_LOG_LEVEL + prompt "Debug Log Level" + default LOG_ERROR + help + VERBOS: Print bigger chunks of debugging information + DEBUG: Print extra information for debugging + INFO: Print necessary information messages + WARN: Print error conditions from which recovery measures have been taken + ERROR: Print critical errors, software module can not recover on its own + + config LOG_VERBOS + bool "VERBOS" + config LOG_DEBUG + bool "DEBUG" + config LOG_INFO + bool "INFO" + config LOG_WARN + bool "WARN" + config LOG_ERROR + bool "ERROR" + config LOG_NONE + bool "NONE" + +endchoice # DEBUG_LOG_LEVEL + endmenu \ No newline at end of file diff --git a/bsp/common/ft_assert.c b/bsp/common/ft_assert.c index bb00c5672..125912515 100644 --- a/bsp/common/ft_assert.c +++ b/bsp/common/ft_assert.c @@ -1,43 +1,43 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-05-28 16:15:28 - * @Description:  This files is for type definition - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "ft_types.h" -#include "ft_assert.h" - -/************* 全局变量 用于判断驱动是否出现断言 *****************/ -u32 ft_assert_status; - -/************** 断言是否需要无限等待，1 等待，0不等待 ******************/ -s32 ft_assert_wait = 1; - -/* 当断言发生时，将会调用此函数 */ -static FtAssertCallback ft_assert_cb = NULL; - -/************************** Function Prototypes ******************************/ -void FtAssert(char *file, s32 Line) -{ - if (ft_assert_cb != NULL) - { - ft_assert_cb(file, Line); - } - - while (ft_assert_wait != 0) - { - } -} - -void FtAssertSetCb(FtAssertCallback routine) -{ - ft_assert_cb = routine; -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-05-28 16:15:28 + * @Description:  This files is for type definition + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "ft_types.h" +#include "ft_assert.h" + +/************* 全局变量 用于判断驱动是否出现断言 *****************/ +u32 ft_assert_status; + +/************** 断言是否需要无限等待，1 等待，0不等待 ******************/ +s32 ft_assert_wait = 1; + +/* 当断言发生时，将会调用此函数 */ +static FtAssertCallback ft_assert_cb = NULL; + +/************************** Function Prototypes ******************************/ +void FtAssert(char *file, s32 Line) +{ + if (ft_assert_cb != NULL) + { + ft_assert_cb(file, Line); + } + + while (ft_assert_wait != 0) + { + } +} + +void FtAssertSetCb(FtAssertCallback routine) +{ + ft_assert_cb = routine; +} diff --git a/bsp/common/ft_assert.h b/bsp/common/ft_assert.h index cfc003183..e4311ddc9 100644 --- a/bsp/common/ft_assert.h +++ b/bsp/common/ft_assert.h @@ -1,160 +1,160 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-05-28 16:18:54 - * @Description:  This files is for assert function - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef Ft_assert_H -#define Ft_assert_H - -#include "ft_types.h" -#include "ft_error_code.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -#define FASSERT_NONE 0U -#define FASSERT_OCCURRED 1U -#define FT_ASSERT_APPEAR_BYTE 0xffU -#define FT_ASSERT_APPEAR FT_MAKE_ERRCODE(ErrModAssert, ErrBspGeneral, 1) - - extern u32 ft_assert_status; - extern s32 ft_assert_wait; - extern void FtAssert(char *file, s32 Line); - - typedef void (*FtAssertCallback)(char *File, s32 Line); - -#define FT_ASSERTVOID(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return; \ - } \ - } - -#define FT_ASSERTBOOL(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return FALSE; \ - } \ - } - -/** - * @name: Ft_assertZeroNum - * @msg: 断言函数带返回值0 - * @param {*} - * @return {*} - */ -#define FT_ASSERTZERONUM(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return FT_ASSERT_APPEAR; \ - } \ - } - -/** - * @name: FT_ASSERTNONVOID - * @msg: 断言函数带返回值FT_ASSERT_APPEAR - * @param {*} - * @return {*} - */ -#define FT_ASSERTNONVOID(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return FT_ASSERT_APPEAR; \ - } \ - } - -#define FT_ASSERTBYTE(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return FT_ASSERT_APPEAR_BYTE; \ - } \ - } - -/** - * @name: Ft_assertNoneReturn - * @msg: 断言函数不返回 - * @param {*} - * @return {*} - */ -#define FT_ASSERTNONERETURN(expression) \ - { \ - if (expression) \ - { \ - ft_assert_status = FASSERT_NONE; \ - } \ - else \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - while (1) \ - { \ - } \ - } \ - } - -#define FT_ASSERTVOIDALWAYS() \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return; \ - } - -#define FT_ASSERTNONVOIDALWAYS() \ - { \ - FtAssert(__FILE__, __LINE__); \ - ft_assert_status = FASSERT_OCCURRED; \ - return FT_ASSERT_APPEAR; \ - } - - void FtAssertSetCb(FtAssertCallback routine); -#ifdef __cplusplus -} -#endif - -#endif // ! +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-05-28 16:18:54 + * @Description:  This files is for assert function + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef Ft_assert_H +#define Ft_assert_H + +#include "ft_types.h" +#include "ft_error_code.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define FASSERT_NONE 0U +#define FASSERT_OCCURRED 1U +#define FT_ASSERT_APPEAR_BYTE 0xffU +#define FT_ASSERT_APPEAR FT_MAKE_ERRCODE(ErrModAssert, ErrBspGeneral, 1) + + extern u32 ft_assert_status; + extern s32 ft_assert_wait; + extern void FtAssert(char *file, s32 Line); + + typedef void (*FtAssertCallback)(char *File, s32 Line); + +#define FT_ASSERTVOID(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return; \ + } \ + } + +#define FT_ASSERTBOOL(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return FALSE; \ + } \ + } + +/** + * @name: Ft_assertZeroNum + * @msg: 断言函数带返回值0 + * @param {*} + * @return {*} + */ +#define FT_ASSERTZERONUM(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return FT_ASSERT_APPEAR; \ + } \ + } + +/** + * @name: FT_ASSERTNONVOID + * @msg: 断言函数带返回值FT_ASSERT_APPEAR + * @param {*} + * @return {*} + */ +#define FT_ASSERTNONVOID(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return FT_ASSERT_APPEAR; \ + } \ + } + +#define FT_ASSERTBYTE(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return FT_ASSERT_APPEAR_BYTE; \ + } \ + } + +/** + * @name: Ft_assertNoneReturn + * @msg: 断言函数不返回 + * @param {*} + * @return {*} + */ +#define FT_ASSERTNONERETURN(expression) \ + { \ + if (expression) \ + { \ + ft_assert_status = FASSERT_NONE; \ + } \ + else \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + while (1) \ + { \ + } \ + } \ + } + +#define FT_ASSERTVOIDALWAYS() \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return; \ + } + +#define FT_ASSERTNONVOIDALWAYS() \ + { \ + FtAssert(__FILE__, __LINE__); \ + ft_assert_status = FASSERT_OCCURRED; \ + return FT_ASSERT_APPEAR; \ + } + + void FtAssertSetCb(FtAssertCallback routine); +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/common/ft_debug.c b/bsp/common/ft_debug.c index bb99987d9..26079fce6 100644 --- a/bsp/common/ft_debug.c +++ b/bsp/common/ft_debug.c @@ -1,67 +1,67 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-25 16:44:23 - * @LastEditTime: 2021-07-12 14:34:13 - * @Description:  Description of file - * @Modify History: - * * * Ver   Who        Date         Changes - * * ----- ------     --------    -------------------------------------- - */ -#include "ft_debug.h" - -#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') -void FtDumpHexByte(const u8 *ptr, u32 buflen) -{ - unsigned char *buf = (unsigned char *)ptr; - fsize_t i, j; - - for (i = 0; i < buflen; i += 16) - { - printf("0x%lX: ", (fsize_t)ptr + i); - - for (j = 0; j < 16; j++) - if (i + j < buflen) - printf("%02X ", buf[i + j]); - else - printf(" "); - printf(" "); - - for (j = 0; j < 16; j++) - if (i + j < buflen) - printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); - printf("\r\n"); - } -} - -void FtDumpHexWord(const u32 *ptr, u32 buflen) -{ - u32 *buf = (u32 *)ptr; - fsize_t i, j; - buflen = buflen / 4; - for (i = 0; i < buflen; i += 4) - { - printf("0x%lX: ", (fsize_t)ptr + i); - - for (j = 0; j < 4; j++) - { - if (i + j < buflen) - { - printf("%08X ", buf[i + j]); - } - else - { - printf(" "); - } - } - - printf(" "); - - for (j = 0; j < 16; j++) - if (i + j < buflen) - printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); - printf("\r\n"); - } -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-25 16:44:23 + * @LastEditTime: 2021-07-12 14:34:13 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ +#include "ft_debug.h" + +#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +void FtDumpHexByte(const u8 *ptr, u32 buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + fsize_t i, j; + + for (i = 0; i < buflen; i += 16) + { + printf("0x%lX: ", (fsize_t)ptr + i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + printf("%02X ", buf[i + j]); + else + printf(" "); + printf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + printf("\r\n"); + } +} + +void FtDumpHexWord(const u32 *ptr, u32 buflen) +{ + u32 *buf = (u32 *)ptr; + fsize_t i, j; + buflen = buflen / 4; + for (i = 0; i < buflen; i += 4) + { + printf("0x%lX: ", (fsize_t)ptr + i); + + for (j = 0; j < 4; j++) + { + if (i + j < buflen) + { + printf("%08X ", buf[i + j]); + } + else + { + printf(" "); + } + } + + printf(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.'); + printf("\r\n"); + } +} diff --git a/bsp/common/ft_debug.h b/bsp/common/ft_debug.h index 012e6a449..0b09d91ca 100644 --- a/bsp/common/ft_debug.h +++ b/bsp/common/ft_debug.h @@ -1,99 +1,99 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-07-12 14:35:56 - * @Description:  This files is for debug functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_COMMON_FT_DEBUG_H -#define BSP_COMMON_FT_DEBUG_H -#include -#include "ft_types.h" -typedef enum -{ - FT_LOG_NONE, /*!< No log output */ - FT_LOG_ERROR, /*!< Critical errors, software module can not recover on its own */ - FT_LOG_WARN, /*!< Error conditions from which recovery measures have been taken */ - FT_LOG_INFO, /*!< Information messages which describe normal flow of events */ - FT_LOG_DEBUG, /*!< Extra information which is not necessary for normal use (values, pointers, sizes, etc). */ - FT_LOG_VERBOSE /*!< Bigger chunks of debugging information, or frequent messages which can potentially flood the output. */ -} ft_log_level_t; - -#define LOG_COLOR_BLACK "30" -#define LOG_COLOR_RED "31" -#define LOG_COLOR_GREEN "32" -#define LOG_COLOR_BROWN "33" -#define LOG_COLOR_BLUE "34" -#define LOG_COLOR_PURPLE "35" -#define LOG_COLOR_CYAN "36" -#define LOG_COLOR(COLOR) "\033[0;" COLOR "m" -#define LOG_BOLD(COLOR) "\033[1;" COLOR "m" -#define LOG_RESET_COLOR "\033[0m" -#define LOG_COLOR_E LOG_COLOR(LOG_COLOR_RED) -#define LOG_COLOR_W LOG_COLOR(LOG_COLOR_BROWN) -#define LOG_COLOR_I LOG_COLOR(LOG_COLOR_GREEN) -#define LOG_COLOR_D -#define LOG_COLOR_V - -/* select debug log level */ -#ifdef CONFIG_LOG_ERROR -#define LOG_LOCAL_LEVEL FT_LOG_ERROR -#endif - -#ifdef CONFIG_LOG_WARN -#define LOG_LOCAL_LEVEL FT_LOG_WARN -#endif - -#ifdef CONFIG_LOG_INFO -#define LOG_LOCAL_LEVEL FT_LOG_INFO -#endif - -#ifdef CONFIG_LOG_DEBUG -#define LOG_LOCAL_LEVEL FT_LOG_DEBUG -#endif - -#define LOG_FORMAT(letter, format) LOG_COLOR_##letter " %s: " format LOG_RESET_COLOR "\r\n" - -#define PORT_KPRINTF printf - -#define LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) \ - do \ - { \ - if (LOG_LOCAL_LEVEL < log_level) \ - break; \ - PORT_KPRINTF(LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \ - } while (0) - -#define EARLY_LOGE(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_ERROR, E, ##__VA_ARGS__) -#define EARLY_LOGI(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_INFO, I, ##__VA_ARGS__) -#define EARLY_LOGD(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_DEBUG, D, ##__VA_ARGS__) -#define EARLY_LOGW(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_WARN, W, ##__VA_ARGS__) -#define EARLY_LOGV(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_VERBOSE, W, ##__VA_ARGS__) - -/* do not compile log if define CONFIG_LOG_NONE */ -#ifndef CONFIG_LOG_NONE -#define FT_DEBUG_PRINT_I(TAG, format, ...) EARLY_LOGI(TAG, format, ##__VA_ARGS__) -#define FT_DEBUG_PRINT_E(TAG, format, ...) EARLY_LOGE(TAG, format, ##__VA_ARGS__) -#define FT_DEBUG_PRINT_D(TAG, format, ...) EARLY_LOGD(TAG, format, ##__VA_ARGS__) -#define FT_DEBUG_PRINT_W(TAG, format, ...) EARLY_LOGW(TAG, format, ##__VA_ARGS__) -#define FT_DEBUG_PRINT_V(TAG, format, ...) EARLY_LOGV(TAG, format, ##__VA_ARGS__) -#else -#define FT_DEBUG_PRINT_I(TAG, format, ...) -#define FT_DEBUG_PRINT_E(TAG, format, ...) -#define FT_DEBUG_PRINT_D(TAG, format, ...) -#define FT_DEBUG_PRINT_W(TAG, format, ...) -#define FT_DEBUG_PRINT_V(TAG, format, ...) -#endif - -#define FT_RAW_PRINTF(format, ...) PORT_KPRINTF(format, ##__VA_ARGS__) - -void FtDumpHexWord(const u32 *ptr, u32 buflen); -void FtDumpHexByte(const u8 *ptr, u32 buflen); -#endif // ! +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-07-12 14:35:56 + * @Description:  This files is for debug functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_COMMON_FT_DEBUG_H +#define BSP_COMMON_FT_DEBUG_H +#include +#include "ft_types.h" +typedef enum +{ + FT_LOG_NONE, /*!< No log output */ + FT_LOG_ERROR, /*!< Critical errors, software module can not recover on its own */ + FT_LOG_WARN, /*!< Error conditions from which recovery measures have been taken */ + FT_LOG_INFO, /*!< Information messages which describe normal flow of events */ + FT_LOG_DEBUG, /*!< Extra information which is not necessary for normal use (values, pointers, sizes, etc). */ + FT_LOG_VERBOSE /*!< Bigger chunks of debugging information, or frequent messages which can potentially flood the output. */ +} ft_log_level_t; + +#define LOG_COLOR_BLACK "30" +#define LOG_COLOR_RED "31" +#define LOG_COLOR_GREEN "32" +#define LOG_COLOR_BROWN "33" +#define LOG_COLOR_BLUE "34" +#define LOG_COLOR_PURPLE "35" +#define LOG_COLOR_CYAN "36" +#define LOG_COLOR(COLOR) "\033[0;" COLOR "m" +#define LOG_BOLD(COLOR) "\033[1;" COLOR "m" +#define LOG_RESET_COLOR "\033[0m" +#define LOG_COLOR_E LOG_COLOR(LOG_COLOR_RED) +#define LOG_COLOR_W LOG_COLOR(LOG_COLOR_BROWN) +#define LOG_COLOR_I LOG_COLOR(LOG_COLOR_GREEN) +#define LOG_COLOR_D +#define LOG_COLOR_V + +/* select debug log level */ +#ifdef CONFIG_LOG_ERROR +#define LOG_LOCAL_LEVEL FT_LOG_ERROR +#endif + +#ifdef CONFIG_LOG_WARN +#define LOG_LOCAL_LEVEL FT_LOG_WARN +#endif + +#ifdef CONFIG_LOG_INFO +#define LOG_LOCAL_LEVEL FT_LOG_INFO +#endif + +#ifdef CONFIG_LOG_DEBUG +#define LOG_LOCAL_LEVEL FT_LOG_DEBUG +#endif + +#define LOG_FORMAT(letter, format) LOG_COLOR_##letter " %s: " format LOG_RESET_COLOR "\r\n" + +#define PORT_KPRINTF printf + +#define LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) \ + do \ + { \ + if (LOG_LOCAL_LEVEL < log_level) \ + break; \ + PORT_KPRINTF(LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \ + } while (0) + +#define EARLY_LOGE(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_ERROR, E, ##__VA_ARGS__) +#define EARLY_LOGI(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_INFO, I, ##__VA_ARGS__) +#define EARLY_LOGD(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_DEBUG, D, ##__VA_ARGS__) +#define EARLY_LOGW(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_WARN, W, ##__VA_ARGS__) +#define EARLY_LOGV(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_VERBOSE, W, ##__VA_ARGS__) + +/* do not compile log if define CONFIG_LOG_NONE */ +#ifndef CONFIG_LOG_NONE +#define FT_DEBUG_PRINT_I(TAG, format, ...) EARLY_LOGI(TAG, format, ##__VA_ARGS__) +#define FT_DEBUG_PRINT_E(TAG, format, ...) EARLY_LOGE(TAG, format, ##__VA_ARGS__) +#define FT_DEBUG_PRINT_D(TAG, format, ...) EARLY_LOGD(TAG, format, ##__VA_ARGS__) +#define FT_DEBUG_PRINT_W(TAG, format, ...) EARLY_LOGW(TAG, format, ##__VA_ARGS__) +#define FT_DEBUG_PRINT_V(TAG, format, ...) EARLY_LOGV(TAG, format, ##__VA_ARGS__) +#else +#define FT_DEBUG_PRINT_I(TAG, format, ...) +#define FT_DEBUG_PRINT_E(TAG, format, ...) +#define FT_DEBUG_PRINT_D(TAG, format, ...) +#define FT_DEBUG_PRINT_W(TAG, format, ...) +#define FT_DEBUG_PRINT_V(TAG, format, ...) +#endif + +#define FT_RAW_PRINTF(format, ...) PORT_KPRINTF(format, ##__VA_ARGS__) + +void FtDumpHexWord(const u32 *ptr, u32 buflen); +void FtDumpHexByte(const u8 *ptr, u32 buflen); +#endif // ! diff --git a/bsp/common/ft_error_code.h b/bsp/common/ft_error_code.h index 0f7cb642c..37063661a 100644 --- a/bsp/common/ft_error_code.h +++ b/bsp/common/ft_error_code.h @@ -1,67 +1,68 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:30 - * @LastEditTime: 2021-05-31 17:19:21 - * @Description:  This files is for error code functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _FT_ERROR_CODE_H -#define _FT_ERROR_CODE_H - -#include "ft_types.h" - -typedef s32 ft_error_t; - -#define FT_SUCCESS 0 - -/* 系统错误码模块定义 */ -typedef enum -{ - ErrorModGeneral = 0, - ErrModBsp, - ErrModAssert, - ErrModPort, - ErrModMaxMask = 255, - -} FtErrorCodeModuleMask; - -/* BSP模块的错误子模块定义 */ -typedef enum -{ - ErrBspGeneral = 0, - ErrBspClk, - ErrBspRtc, - ErrBspTimer, - ErrBspUart, - ErrBspModMaxMask = 255 -} FtErrCodeBspMask; - -#define FT_ERRCODE_SYS_MODULE_OFFSET (u32)24 -#define FT_ERRCODE_SUB_MODULE_OFFSET (u32)16 - -#define FT_ERRCODE_SYS_MODULE_MASK ((u32)0xff << FT_ERRCODE_SYS_MODULE_OFFSET) /* bit 24 .. 31 */ -#define FT_ERRCODE_SUB_MODULE_MASK ((u32)0xff << FT_ERRCODE_SUB_MODULE_OFFSET) /* bit 16 .. 23 */ -#define FT_ERRCODE_TAIL_VALUE_MASK ((u32)0xffff) /* bit 1 .. 15 */ - -/* Offset error code */ -#define FT_ERRCODE_OFFSET(code, offset, mask) \ - (((code) << (offset)) & (mask)) - -/* Assembly error code */ -#define FT_MAKE_ERRCODE(sys_mode, sub_mode, tail) \ - ((FT_ERRCODE_OFFSET((u32)sys_mode, FT_ERRCODE_SYS_MODULE_OFFSET, FT_ERRCODE_SYS_MODULE_MASK)) | \ - (FT_ERRCODE_OFFSET((u32)sub_mode, FT_ERRCODE_SUB_MODULE_OFFSET, FT_ERRCODE_SUB_MODULE_MASK)) | \ - ((u32)tail & FT_ERRCODE_TAIL_VALUE_MASK)) -#define FT_CODE_ERR FT_MAKE_ERRCODE - -#define ERR_SUCCESS FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 0) /* 成功 */ -#define ERR_GENERAL FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 1) /* 一般错误 */ - -#endif +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:30 + * @LastEditTime: 2021-07-12 22:31:39 + * @Description:  This files is for error code functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _FT_ERROR_CODE_H +#define _FT_ERROR_CODE_H + +#include "ft_types.h" + +typedef s32 ft_error_t; + +#define FT_SUCCESS 0 + +/* 系统错误码模块定义 */ +typedef enum +{ + ErrorModGeneral = 0, + ErrModBsp, + ErrModAssert, + ErrModPort, + ErrModMaxMask = 255, + +} FtErrorCodeModuleMask; + +/* BSP模块的错误子模块定义 */ +typedef enum +{ + ErrBspGeneral = 0, + ErrBspClk, + ErrBspRtc, + ErrBspTimer, + ErrBspUart, + ErrBspGpio, + ErrBspModMaxMask = 255 +} FtErrCodeBspMask; + +#define FT_ERRCODE_SYS_MODULE_OFFSET (u32)24 +#define FT_ERRCODE_SUB_MODULE_OFFSET (u32)16 + +#define FT_ERRCODE_SYS_MODULE_MASK ((u32)0xff << FT_ERRCODE_SYS_MODULE_OFFSET) /* bit 24 .. 31 */ +#define FT_ERRCODE_SUB_MODULE_MASK ((u32)0xff << FT_ERRCODE_SUB_MODULE_OFFSET) /* bit 16 .. 23 */ +#define FT_ERRCODE_TAIL_VALUE_MASK ((u32)0xffff) /* bit 1 .. 15 */ + +/* Offset error code */ +#define FT_ERRCODE_OFFSET(code, offset, mask) \ + (((code) << (offset)) & (mask)) + +/* Assembly error code */ +#define FT_MAKE_ERRCODE(sys_mode, sub_mode, tail) \ + ((FT_ERRCODE_OFFSET((u32)sys_mode, FT_ERRCODE_SYS_MODULE_OFFSET, FT_ERRCODE_SYS_MODULE_MASK)) | \ + (FT_ERRCODE_OFFSET((u32)sub_mode, FT_ERRCODE_SUB_MODULE_OFFSET, FT_ERRCODE_SUB_MODULE_MASK)) | \ + ((u32)tail & FT_ERRCODE_TAIL_VALUE_MASK)) +#define FT_CODE_ERR FT_MAKE_ERRCODE + +#define ERR_SUCCESS FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 0) /* 成功 */ +#define ERR_GENERAL FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 1) /* 一般错误 */ + +#endif diff --git a/bsp/common/ft_io.h b/bsp/common/ft_io.h index 15041a566..eb1b6f932 100644 --- a/bsp/common/ft_io.h +++ b/bsp/common/ft_io.h @@ -1,100 +1,100 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-05-28 17:25:54 - * @Description:  This files is for general reigster io functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef FT_IO_H -#define FT_IO_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" - - static _INLINE u8 FtIn8(uintptr addr) - { - return *(volatile u8 *)addr; - } - - static _INLINE u16 FtIn16(uintptr addr) - { - return *(volatile u16 *)addr; - } - - static _INLINE u32 FtIn32(uintptr addr) - { - return *(volatile u32 *)addr; - } - - static _INLINE u64 FtIn64(uintptr addr) - { - return *(volatile u64 *)addr; - } - - static _INLINE void FtOut8(uintptr addr, u8 value) - { - volatile u8 *local_addr = (volatile u8 *)addr; - *local_addr = value; - } - - static _INLINE void FtOut16(uintptr addr, u16 value) - { - volatile u16 *local_addr = (volatile u16 *)addr; - *local_addr = value; - } - - static _INLINE void FtOut32(uintptr addr, u32 value) - { - volatile u32 *local_addr = (volatile u32 *)addr; - *local_addr = value; - } - - static _INLINE void FtOut64(uintptr addr, u64 value) - { - volatile u64 *local_addr = (volatile u64 *)addr; - *local_addr = value; - } - - static _INLINE void FtSetBit32(uintptr addr, u32 value) - { - volatile u32 last_value; - last_value = FtIn32(addr); - last_value |= value; - FtOut32(addr, value); - } - - static _INLINE void FtClearBit32(uintptr addr, u32 value) - { - volatile u32 last_value; - last_value = FtIn32(addr); - last_value &= ~value; - FtOut32(addr, value); - } - - static _INLINE void FtToggleBit32(uintptr addr, u32 toggle_pos) - { - volatile u32 value; - value = FtIn32(addr); - value ^= (1 << toggle_pos); - FtOut32(addr, value); - } - -#define FT_WRITE32(_reg, _val) (*(volatile uint32_t *)&_reg = _val) -#define FT_READ32(_reg) (*(volatile uint32_t *)&_reg) - -#ifdef __cplusplus -} -#endif - -#endif // ! +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-05-28 17:25:54 + * @Description:  This files is for general reigster io functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef FT_IO_H +#define FT_IO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" + + static _INLINE u8 FtIn8(uintptr addr) + { + return *(volatile u8 *)addr; + } + + static _INLINE u16 FtIn16(uintptr addr) + { + return *(volatile u16 *)addr; + } + + static _INLINE u32 FtIn32(uintptr addr) + { + return *(volatile u32 *)addr; + } + + static _INLINE u64 FtIn64(uintptr addr) + { + return *(volatile u64 *)addr; + } + + static _INLINE void FtOut8(uintptr addr, u8 value) + { + volatile u8 *local_addr = (volatile u8 *)addr; + *local_addr = value; + } + + static _INLINE void FtOut16(uintptr addr, u16 value) + { + volatile u16 *local_addr = (volatile u16 *)addr; + *local_addr = value; + } + + static _INLINE void FtOut32(uintptr addr, u32 value) + { + volatile u32 *local_addr = (volatile u32 *)addr; + *local_addr = value; + } + + static _INLINE void FtOut64(uintptr addr, u64 value) + { + volatile u64 *local_addr = (volatile u64 *)addr; + *local_addr = value; + } + + static _INLINE void FtSetBit32(uintptr addr, u32 value) + { + volatile u32 last_value; + last_value = FtIn32(addr); + last_value |= value; + FtOut32(addr, value); + } + + static _INLINE void FtClearBit32(uintptr addr, u32 value) + { + volatile u32 last_value; + last_value = FtIn32(addr); + last_value &= ~value; + FtOut32(addr, value); + } + + static _INLINE void FtToggleBit32(uintptr addr, u32 toggle_pos) + { + volatile u32 value; + value = FtIn32(addr); + value ^= (1 << toggle_pos); + FtOut32(addr, value); + } + +#define FT_WRITE32(_reg, _val) (*(volatile uint32_t *)&_reg = _val) +#define FT_READ32(_reg) (*(volatile uint32_t *)&_reg) + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/common/ft_types.h b/bsp/common/ft_types.h index 948a4e66f..bd514df00 100644 --- a/bsp/common/ft_types.h +++ b/bsp/common/ft_types.h @@ -1,72 +1,72 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-27 13:30:03 - * @LastEditTime: 2021-06-25 15:33:16 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _BSP_COMMON_FT_TYPE_H -#define _BSP_COMMON_FT_TYPE_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#define FT_COMPONENT_IS_READLY 0x11111111U - - typedef uint8_t u8; // unsigned 8-bit - typedef char s8; // signed 8-bit - typedef uint16_t u16; // unsigned 16-bit - typedef short s16; // signed 16-bit - typedef uint32_t u32; // unsigned 32-bit - typedef long s32; // signed 32-bit - typedef uint64_t u64; // unsigned 64-bit - typedef int64_t s64; // unsigned - typedef float f32; // 32-bit floating point - typedef double f64; // 64-bit double precision FP - typedef unsigned long boolean; // boolean (XTRUE or XFALSE) - typedef uint64_t _time_t; - typedef size_t fsize_t; - - typedef intptr_t intptr; - typedef uintptr_t uintptr; - typedef ptrdiff_t ptrdiff; - -#define ULONG64_HI_MASK 0xFFFFFFFF00000000U -#define ULONG64_LO_MASK ~ULONG64_HI_MASK - -#ifndef TRUE -#define TRUE 1U -#endif - -#ifndef FALSE -#define FALSE 0U -#endif - -#ifndef NULL -#define NULL 0U -#endif - -#define _INLINE inline -#define _WEAK __attribute__((weak)) - - typedef void (*FIrqHandler)(void *InstancePtr); - - typedef void (*FExceptionHandler)(void *InstancePtr); - -#ifdef __cplusplus -} -#endif - -#endif // ! +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-27 13:30:03 + * @LastEditTime: 2021-06-25 15:33:16 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _BSP_COMMON_FT_TYPE_H +#define _BSP_COMMON_FT_TYPE_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +#define FT_COMPONENT_IS_READLY 0x11111111U + + typedef uint8_t u8; // unsigned 8-bit + typedef char s8; // signed 8-bit + typedef uint16_t u16; // unsigned 16-bit + typedef short s16; // signed 16-bit + typedef uint32_t u32; // unsigned 32-bit + typedef long s32; // signed 32-bit + typedef uint64_t u64; // unsigned 64-bit + typedef int64_t s64; // unsigned + typedef float f32; // 32-bit floating point + typedef double f64; // 64-bit double precision FP + typedef unsigned long boolean; // boolean (XTRUE or XFALSE) + typedef uint64_t _time_t; + typedef size_t fsize_t; + + typedef intptr_t intptr; + typedef uintptr_t uintptr; + typedef ptrdiff_t ptrdiff; + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define _INLINE inline +#define _WEAK __attribute__((weak)) + + typedef void (*FIrqHandler)(void *InstancePtr); + + typedef void (*FExceptionHandler)(void *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/common/interrupt.c b/bsp/common/interrupt.c index 3db1650ea..76ab82964 100644 --- a/bsp/common/interrupt.c +++ b/bsp/common/interrupt.c @@ -1,313 +1,313 @@ - - -#include -#include "interrupt.h" -#include "sdkconfig.h" - -#ifdef CONFIG_USE_GIC -#ifdef CONFIG_EBABLE_GICV3 -#include "gicv3.h" -#else -#include "gic.h" -#endif -#endif - -#define MAX_HANDLERS 160 - -/* exception and interrupt handler table */ -struct IrqDesc isr_table[MAX_HANDLERS]; - -#ifndef FT_USING_SMP -/* Those varibles will be accessed in ISR, so we need to share them. */ -u32 rt_interrupt_from_thread = 0; -u32 rt_interrupt_to_thread = 0; -u32 rt_thread_switch_interrupt_flag = 0; -#endif - -const unsigned int VECTOR_BASE = 0x00; - -_WEAK u32 PlatformGetIrqStartNum(void) -{ - return 0; -} - -_WEAK u32 PlatformGetGicDistBase(void) -{ - return 0; -} - -#ifdef RT_USING_GIC_V2 -/** - * This function will initialize hardware interrupt - */ -void InterruptInit(void) -{ - u32 gic_cpu_base; - u32 gic_dist_base; - u32 gic_irq_start; - - /* initialize vector table */ - // rt_hw_vector_init(); - - /* initialize exceptions table */ - memset(isr_table, 0x00, sizeof(isr_table)); - - /* initialize ARM GIC */ - gic_dist_base = platform_get_gic_dist_base(); - gic_cpu_base = platform_get_gic_cpu_base(); - - gic_irq_start = GIC_IRQ_START; - - arm_gic_dist_init(0, gic_dist_base, gic_irq_start); - arm_gic_cpu_init(0, gic_cpu_base); -} -#else -/** - * This function will initialize hardware interrupt - * Called by the primary cpu(cpu0) - */ -void InterruptInit(void) -{ - u32 gic_dist_base; - u32 gic_irq_start; - - /* initialize exceptions table */ - memset(isr_table, 0x00, sizeof(isr_table)); - - /* initialize ARM GIC */ - gic_dist_base = PlatformGetGicDistBase(); - gic_irq_start = PlatformGetIrqStartNum(); - - /* per cpu core need to run */ - ArmGicDistInit(0, gic_dist_base, gic_irq_start); - - ArmGicCpuInit(0); - - ArmGicRedistInit(0); -} - -#endif - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void InterruptMask(int vector) -{ - ArmGicMask(0, vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void InterruptUmask(int vector) -{ - ArmGicUmask(0, vector); -} - -/** - * This function returns the active interrupt number. - * @param none - */ -int InterruptGetIrq(void) -{ - return ArmGicGetActiveIrq(0); -} - -/** - * This function acknowledges the interrupt. - * @param vector the interrupt number - */ -void InterruptAck(int vector) -{ - ArmGicAck(0, vector); -} - -/** - * This function set interrupt CPU targets. - * @param vector: the interrupt number - * cpu_mask: target cpus mask, one bit for one core - */ -void InterruptSetTargetCpus(int vector, unsigned int cpu_mask) -{ - ArmGicSetCpu(0, vector, cpu_mask); -} - -/** - * This function get interrupt CPU targets. - * @param vector: the interrupt number - * @return target cpus mask, one bit for one core - */ -unsigned int InterruptGetTargetCpus(int vector) -{ - return ArmGicGetTargetCpu(0, vector); -} - -/** - * This function set interrupt triger mode. - * @param vector: the interrupt number - * mode: interrupt triger mode; 0: level triger, 1: edge triger - */ -void InterruptSetTrigerMode(int vector, unsigned int mode) -{ - ArmGicSetConfiguration(0, vector, mode); -} - -/** - * This function get interrupt triger mode. - * @param vector: the interrupt number - * @return interrupt triger mode; 0: level triger, 1: edge triger - */ -unsigned int InterruptGetTrigerMode(int vector) -{ - return ArmGicGetConfiguration(0, vector); -} - -/** - * This function set interrupt pending flag. - * @param vector: the interrupt number - */ -void InterruptSetPending(int vector) -{ - ArmGicSetPendingIrq(0, vector); -} - -/** - * This function get interrupt pending flag. - * @param vector: the interrupt number - * @return interrupt pending flag, 0: not pending; 1: pending - */ -unsigned int InterruptGetPending(int vector) -{ - return ArmGicGetPendingIrq(0, vector); -} - -/** - * This function clear interrupt pending flag. - * @param vector: the interrupt number - */ -void InterruptClearPending(int vector) -{ - // arm_gic_clear_pending_irq(0, vector); - ArmGicClearPendingIrq(0, vector); -} - -/** - * This function set interrupt priority value. - * @param vector: the interrupt number - * priority: the priority of interrupt to set - */ -void InterruptSetPriority(int vector, unsigned int priority) -{ - // arm_gic_set_priority(0, vector, priority); - ArmGicSetPriority(0, vector, priority); -} - -/** - * This function get interrupt priority. - * @param vector: the interrupt number - * @return interrupt priority value - */ -unsigned int InterruptGetPriority(int vector) -{ - // return arm_gic_get_priority(0, vector); - return ArmGicGetPriority(0, vector); -} - -/** - * This function set priority masking threshold. - * @param priority: priority masking threshold - */ -void InterruptSetPriorityMask(unsigned int priority) -{ - ArmGicSetInterfacePriorMask(0, priority); -} - -/** - * This function get priority masking threshold. - * @param none - * @return priority masking threshold - */ -unsigned int InterruptGetPriorityMask(void) -{ - return ArmGicGetInterfacePriorMask(0); -} - -/** - * This function set priority grouping field split point. - * @param bits: priority grouping field split point - * @return 0: success; -1: failed - */ -int InterruptSetPriorGroupBits(unsigned int bits) -{ - int status; - - if (bits < 8) - { - ArmGicSetBinaryPoint(0, (7 - bits)); - status = 0; - } - else - { - status = -1; - } - - return (status); -} - -/** - * This function get priority grouping field split point. - * @param none - * @return priority grouping field split point - */ -unsigned int InterruptGetPriorGroupBits(void) -{ - unsigned int bp; - - bp = ArmGicGetBinaryPoint(0) & 0x07; - - return (7 - bp); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -IrqHandler InterruptInstall(int vector, IrqHandler handler, - void *param, const char *name) -{ - IrqHandler old_handler = NULL; - - if (vector < MAX_HANDLERS) - { - old_handler = isr_table[vector].handler; - - if (handler != NULL) - { - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - } - - return old_handler; -} - -#ifdef FT_USING_SMP -void IpiSend(int ipi_vector, unsigned int cpu_mask) -{ -#ifdef RT_USING_GIC_V2 - arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0); -#else - ArmGicSendAffinitySgi(0, ipi_vector, cpu_mask, ROUTED_TO_SPEC); -#endif -} - -void IpiHandlerInstall(int ipi_vector, IrqHandler ipi_isr_handler) -{ - /* note: ipi_vector maybe different with irq_vector */ - InterruptInstall(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); -} -#endif + + +#include +#include "interrupt.h" +#include "sdkconfig.h" + +#ifdef CONFIG_USE_GIC +#ifdef CONFIG_EBABLE_GICV3 +#include "gicv3.h" +#else +#include "gic.h" +#endif +#endif + +#define MAX_HANDLERS 160 + +/* exception and interrupt handler table */ +struct IrqDesc isr_table[MAX_HANDLERS]; + +#ifndef FT_USING_SMP +/* Those varibles will be accessed in ISR, so we need to share them. */ +u32 rt_interrupt_from_thread = 0; +u32 rt_interrupt_to_thread = 0; +u32 rt_thread_switch_interrupt_flag = 0; +#endif + +const unsigned int VECTOR_BASE = 0x00; + +_WEAK u32 PlatformGetIrqStartNum(void) +{ + return 0; +} + +_WEAK u32 PlatformGetGicDistBase(void) +{ + return 0; +} + +#ifdef RT_USING_GIC_V2 +/** + * This function will initialize hardware interrupt + */ +void InterruptInit(void) +{ + u32 gic_cpu_base; + u32 gic_dist_base; + u32 gic_irq_start; + + /* initialize vector table */ + // rt_hw_vector_init(); + + /* initialize exceptions table */ + memset(isr_table, 0x00, sizeof(isr_table)); + + /* initialize ARM GIC */ + gic_dist_base = platform_get_gic_dist_base(); + gic_cpu_base = platform_get_gic_cpu_base(); + + gic_irq_start = GIC_IRQ_START; + + arm_gic_dist_init(0, gic_dist_base, gic_irq_start); + arm_gic_cpu_init(0, gic_cpu_base); +} +#else +/** + * This function will initialize hardware interrupt + * Called by the primary cpu(cpu0) + */ +void InterruptInit(void) +{ + u32 gic_dist_base; + u32 gic_irq_start; + + /* initialize exceptions table */ + memset(isr_table, 0x00, sizeof(isr_table)); + + /* initialize ARM GIC */ + gic_dist_base = PlatformGetGicDistBase(); + gic_irq_start = PlatformGetIrqStartNum(); + + /* per cpu core need to run */ + ArmGicDistInit(0, gic_dist_base, gic_irq_start); + + ArmGicCpuInit(0); + + ArmGicRedistInit(0); +} + +#endif + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void InterruptMask(int vector) +{ + ArmGicMask(0, vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void InterruptUmask(int vector) +{ + ArmGicUmask(0, vector); +} + +/** + * This function returns the active interrupt number. + * @param none + */ +int InterruptGetIrq(void) +{ + return ArmGicGetActiveIrq(0); +} + +/** + * This function acknowledges the interrupt. + * @param vector the interrupt number + */ +void InterruptAck(int vector) +{ + ArmGicAck(0, vector); +} + +/** + * This function set interrupt CPU targets. + * @param vector: the interrupt number + * cpu_mask: target cpus mask, one bit for one core + */ +void InterruptSetTargetCpus(int vector, unsigned int cpu_mask) +{ + ArmGicSetCpu(0, vector, cpu_mask); +} + +/** + * This function get interrupt CPU targets. + * @param vector: the interrupt number + * @return target cpus mask, one bit for one core + */ +unsigned int InterruptGetTargetCpus(int vector) +{ + return ArmGicGetTargetCpu(0, vector); +} + +/** + * This function set interrupt triger mode. + * @param vector: the interrupt number + * mode: interrupt triger mode; 0: level triger, 1: edge triger + */ +void InterruptSetTrigerMode(int vector, unsigned int mode) +{ + ArmGicSetConfiguration(0, vector, mode); +} + +/** + * This function get interrupt triger mode. + * @param vector: the interrupt number + * @return interrupt triger mode; 0: level triger, 1: edge triger + */ +unsigned int InterruptGetTrigerMode(int vector) +{ + return ArmGicGetConfiguration(0, vector); +} + +/** + * This function set interrupt pending flag. + * @param vector: the interrupt number + */ +void InterruptSetPending(int vector) +{ + ArmGicSetPendingIrq(0, vector); +} + +/** + * This function get interrupt pending flag. + * @param vector: the interrupt number + * @return interrupt pending flag, 0: not pending; 1: pending + */ +unsigned int InterruptGetPending(int vector) +{ + return ArmGicGetPendingIrq(0, vector); +} + +/** + * This function clear interrupt pending flag. + * @param vector: the interrupt number + */ +void InterruptClearPending(int vector) +{ + // arm_gic_clear_pending_irq(0, vector); + ArmGicClearPendingIrq(0, vector); +} + +/** + * This function set interrupt priority value. + * @param vector: the interrupt number + * priority: the priority of interrupt to set + */ +void InterruptSetPriority(int vector, unsigned int priority) +{ + // arm_gic_set_priority(0, vector, priority); + ArmGicSetPriority(0, vector, priority); +} + +/** + * This function get interrupt priority. + * @param vector: the interrupt number + * @return interrupt priority value + */ +unsigned int InterruptGetPriority(int vector) +{ + // return arm_gic_get_priority(0, vector); + return ArmGicGetPriority(0, vector); +} + +/** + * This function set priority masking threshold. + * @param priority: priority masking threshold + */ +void InterruptSetPriorityMask(unsigned int priority) +{ + ArmGicSetInterfacePriorMask(0, priority); +} + +/** + * This function get priority masking threshold. + * @param none + * @return priority masking threshold + */ +unsigned int InterruptGetPriorityMask(void) +{ + return ArmGicGetInterfacePriorMask(0); +} + +/** + * This function set priority grouping field split point. + * @param bits: priority grouping field split point + * @return 0: success; -1: failed + */ +int InterruptSetPriorGroupBits(unsigned int bits) +{ + int status; + + if (bits < 8) + { + ArmGicSetBinaryPoint(0, (7 - bits)); + status = 0; + } + else + { + status = -1; + } + + return (status); +} + +/** + * This function get priority grouping field split point. + * @param none + * @return priority grouping field split point + */ +unsigned int InterruptGetPriorGroupBits(void) +{ + unsigned int bp; + + bp = ArmGicGetBinaryPoint(0) & 0x07; + + return (7 - bp); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +IrqHandler InterruptInstall(int vector, IrqHandler handler, + void *param, const char *name) +{ + IrqHandler old_handler = NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != NULL) + { + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} + +#ifdef FT_USING_SMP +void IpiSend(int ipi_vector, unsigned int cpu_mask) +{ +#ifdef RT_USING_GIC_V2 + arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0); +#else + ArmGicSendAffinitySgi(0, ipi_vector, cpu_mask, ROUTED_TO_SPEC); +#endif +} + +void IpiHandlerInstall(int ipi_vector, IrqHandler ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + InterruptInstall(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif diff --git a/bsp/common/interrupt.h b/bsp/common/interrupt.h index a1a4f7d49..bb100dada 100644 --- a/bsp/common/interrupt.h +++ b/bsp/common/interrupt.h @@ -1,73 +1,73 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-25 14:31:02 - * @LastEditTime: 2021-06-25 15:33:03 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#include "ft_types.h" - -/* - * Interrupt handler definition - */ -typedef void (*IrqHandler)(s32 vector, void *param); - -struct IrqDesc -{ - IrqHandler handler; - void *param; -}; - -#define INT_IRQ 0x00 -#define INT_FIQ 0x01 - -#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */ -#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */ - -void rt_hw_vector_init(void); - -void InterruptInit(void); -void InterruptMask(int vector); -void InterruptUmask(int vector); - -int InterruptGetIrq(void); -void InterruptAck(int vector); - -void InterruptSetTargetCpus(int vector, unsigned int cpu_mask); -unsigned int InterruptGetTargetCpus(int vector); - -void InterruptSetTrigerMode(int vector, unsigned int mode); -unsigned int InterruptGetTrigerMode(int vector); - -void InterruptSetPending(int vector); -unsigned int InterruptGetPending(int vector); -void InterruptClearPending(int vector); - -void InterruptSetPriority(int vector, unsigned int priority); -unsigned int InterruptGetPriority(int vector); - -void InterruptSetPriorityMask(unsigned int priority); -unsigned int InterruptGetPriorityMask(void); - -int InterruptSetPriorGroupBits(unsigned int bits); -unsigned int InterruptGetPriorGroupBits(void); - -IrqHandler InterruptInstall(int vector, IrqHandler handler, - void *param, const char *name); - -#ifdef FT_USING_SMP -void IpiSend(int ipi_vector, unsigned int cpu_mask); -void IpiHandlerInstall(int ipi_vector, IrqHandler ipi_isr_handler); -#endif - -#endif +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-25 14:31:02 + * @LastEditTime: 2021-06-25 15:33:03 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include "ft_types.h" + +/* + * Interrupt handler definition + */ +typedef void (*IrqHandler)(s32 vector, void *param); + +struct IrqDesc +{ + IrqHandler handler; + void *param; +}; + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +#define IRQ_MODE_TRIG_LEVEL (0x00) /* Trigger: level triggered interrupt */ +#define IRQ_MODE_TRIG_EDGE (0x01) /* Trigger: edge triggered interrupt */ + +void rt_hw_vector_init(void); + +void InterruptInit(void); +void InterruptMask(int vector); +void InterruptUmask(int vector); + +int InterruptGetIrq(void); +void InterruptAck(int vector); + +void InterruptSetTargetCpus(int vector, unsigned int cpu_mask); +unsigned int InterruptGetTargetCpus(int vector); + +void InterruptSetTrigerMode(int vector, unsigned int mode); +unsigned int InterruptGetTrigerMode(int vector); + +void InterruptSetPending(int vector); +unsigned int InterruptGetPending(int vector); +void InterruptClearPending(int vector); + +void InterruptSetPriority(int vector, unsigned int priority); +unsigned int InterruptGetPriority(int vector); + +void InterruptSetPriorityMask(unsigned int priority); +unsigned int InterruptGetPriorityMask(void); + +int InterruptSetPriorGroupBits(unsigned int bits); +unsigned int InterruptGetPriorGroupBits(void); + +IrqHandler InterruptInstall(int vector, IrqHandler handler, + void *param, const char *name); + +#ifdef FT_USING_SMP +void IpiSend(int ipi_vector, unsigned int cpu_mask); +void IpiHandlerInstall(int ipi_vector, IrqHandler ipi_isr_handler); +#endif + +#endif diff --git a/bsp/common/trap.c b/bsp/common/trap.c index 8b80048ea..e5c316df9 100644 --- a/bsp/common/trap.c +++ b/bsp/common/trap.c @@ -1,278 +1,278 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-25 14:31:02 - * @LastEditTime: 2021-07-01 11:24:51 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#include "trap.h" -#include "interrupt.h" -#include "exception.h" -#include - -#ifdef CONFIG_TARGET_ARMV8_AARCH64 -#define aarch64_read_sysreg(reg) ( \ - { \ - uint64_t val; \ - __asm__ __volatile__("mrs %0," #reg \ - : "=r"(val)); \ - val; \ - }) - -static void print_EC_cause(uint64_t esr) -{ - uint32_t EC = (uint32_t)esr >> 26; - - switch (EC) - { - case 0b000000: - printf("Unknown reason"); - break; - case 0b000001: - printf("Trapped WFI or WFE instruction execution"); - break; - case 0b000011: - printf("Trapped MCR or MRC access with (coproc==0b1111) that " - "is not reported using EC 0b000000"); - break; - case 0b000100: - printf("Trapped MCRR or MRRC access with (coproc==0b1111) " - "that is not reported using EC 0b000000"); - break; - case 0b000101: - printf("Trapped MCR or MRC access with (coproc==0b1110)"); - break; - case 0b000110: - printf("Trapped LDC or STC access"); - break; - case 0b000111: - printf("Trapped access to SVE, Advanced SIMD, or " - "floating-point functionality"); - break; - case 0b001100: - printf("Trapped MRRC access with (coproc==0b1110)"); - break; - case 0b001101: - printf("Branch Target Exception"); - break; - case 0b001110: - printf("Illegal Execution state"); - break; - case 0b010001: - printf("SVC instruction execution in AArch32 state"); - break; - case 0b011000: - printf("Trapped MSR, MRS or System instruction execution in " - "AArch64 state, that is not reported using EC " - "0b000000, 0b000001 or 0b000111"); - break; - case 0b011001: - printf("Trapped access to SVE functionality"); - break; - case 0b100000: - printf("Instruction Abort from a lower Exception level, that " - "might be using AArch32 or AArch64"); - break; - case 0b100001: - printf("Instruction Abort taken without a change in Exception " - "level."); - break; - case 0b100010: - printf("PC alignment fault exception."); - break; - case 0b100100: - printf("Data Abort from a lower Exception level, that might " - "be using AArch32 or AArch64"); - break; - case 0b100101: - printf("Data Abort taken without a change in Exception level"); - break; - case 0b100110: - printf("SP alignment fault exception"); - break; - case 0b101000: - printf("Trapped floating-point exception taken from AArch32 " - "state"); - break; - case 0b101100: - printf("Trapped floating-point exception taken from AArch64 " - "state."); - break; - case 0b101111: - printf("SError interrupt"); - break; - case 0b110000: - printf("Breakpoint exception from a lower Exception level, " - "that might be using AArch32 or AArch64"); - break; - case 0b110001: - printf("Breakpoint exception taken without a change in " - "Exception level"); - break; - case 0b110010: - printf("Software Step exception from a lower Exception level, " - "that might be using AArch32 or AArch64"); - break; - case 0b110011: - printf("Software Step exception taken without a change in " - "Exception level"); - break; - case 0b110100: - printf("Watchpoint exception from a lower Exception level, " - "that might be using AArch32 or AArch64"); - break; - case 0b110101: - printf("Watchpoint exception taken without a change in " - "Exception level."); - break; - case 0b111000: - printf("BKPT instruction execution in AArch32 state"); - break; - case 0b111100: - printf("BRK instruction execution in AArch64 state."); - break; - } - printf("\n"); -} - -void ShowRegister(exception_frame *regs) -{ - printf("Execption:\n"); - printf("r00:0x%x r01:0x%x r02:0x%x r03:0x%x\r\n", regs->x0, regs->x1, regs->x2, regs->x3); - printf("r04:0x%x r05:0x%x r06:0x%x r07:0x%x\r\n", regs->x4, regs->x5, regs->x6, regs->x7); - printf("r08:0x%x r09:0x%x r10:0x%x r11:0x%x\r\n", regs->x8, regs->x9, regs->x10, regs->x11); - printf("r12:0x%x r13:0x%x r14:0x%x r15:0x%x\r\n", regs->x12, regs->x13, regs->x14, regs->x15); - printf("r16:0x%x r17:0x%x r18:0x%x r19:0x%x\r\n", regs->x16, regs->x17, regs->x18, regs->x19); - printf("r20:0x%x r21:0x%x r22:0x%x r23:0x%x\r\n", regs->x20, regs->x21, regs->x22, regs->x23); - printf("r24:0x%x r25:0x%x r26:0x%x r27:0x%x\r\n", regs->x24, regs->x25, regs->x26, regs->x27); - printf("r28:0x%x r29:0x%x r30:0x%x\r\n", regs->x28, regs->x29, regs->x30); - printf("exc_type 0x%x\r\n", regs->exc_type); - printf("exc_esr 0x%x\r\n", regs->exc_esr); - printf("exc_sp 0x%x\r\n", regs->exc_sp); - printf("exc_spsr 0x%x\r\n", regs->exc_spsr); - printf("exc_elr 0x%x\r\n", regs->exc_elr); -} - -/** - * When comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void SerrHandle(exception_frame *regs) -{ - uint64_t esr, far; - uint64_t ec, iss; - - printf("error exception:\n"); - esr = aarch64_read_sysreg(esr_el1); - far = aarch64_read_sysreg(far_el1); - ec = (esr >> 26) & 0x3f; - iss = (esr >> 0) & 0x1ffffff; - printf("\nSError exception detected, ec:0x%x iss:0x%x far:0x%x\r\n", ec, iss, far); - print_EC_cause(esr); - ShowRegister(regs); - while (1) - { - /* code */ - } -} -#endif - -#ifdef CONFIG_TARGET_ARMV8_AARCH32 -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void ShowExceptionRegisters(struct ExceptionStack *regs) -{ - printf("Execption:\r\n"); - printf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\r\n", regs->r0, regs->r1, regs->r2, regs->r3); - printf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\r\n", regs->r4, regs->r5, regs->r6, regs->r7); - printf("r08:0x%08x r09:0x%08x r10:0x%08x\r\n", regs->r8, regs->r9, regs->r10); - printf("fp :0x%08x ip :0x%08x\r\n", regs->fp, regs->ip); - printf("sp :0x%08x lr :0x%08x pc :0x%08x\r\n", regs->sp, regs->lr, regs->pc); - printf("cpsr:0x%08x\r\n", regs->cpsr); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void PrfTrap(struct ExceptionStack *regs) -{ - printf("prefetch abort:\r\n"); - ShowExceptionRegisters(regs); -} -#endif - -#define GIC_ACK_INTID_MASK 0x000003ff - -int InterruptGetIrq(void); -void InterruptAck(int fiq_irq); - -void SystemIrqHandler(int ir) -{ - void *param; - IrqHandler isr_func; - extern struct IrqDesc isr_table[]; - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - if (isr_func) - { - /* Interrupt for myself. */ - param = isr_table[ir].param; - /* turn to interrupt service routine */ - isr_func(ir, param); - } - - /* end of interrupt */ - InterruptAck(ir); -} - -void IrqHandleException(void *value) -{ - void *param; - int ir; - IrqHandler isr_func; - extern struct IrqDesc isr_table[]; - - ir = InterruptGetIrq(); - if (ir == 1023) - { - /* Spurious interrupt */ - return; - } - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - - if (isr_func) - { - /* Interrupt for myself. */ - param = isr_table[ir].param; - /* turn to interrupt service routine */ - isr_func(ir, param); - } - - /* end of interrupt */ - InterruptAck(ir); -} - -void fiq_handle(void) -{ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-25 14:31:02 + * @LastEditTime: 2021-07-01 11:24:51 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#include "trap.h" +#include "interrupt.h" +#include "exception.h" +#include + +#ifdef CONFIG_TARGET_ARMV8_AARCH64 +#define aarch64_read_sysreg(reg) ( \ + { \ + uint64_t val; \ + __asm__ __volatile__("mrs %0," #reg \ + : "=r"(val)); \ + val; \ + }) + +static void print_EC_cause(uint64_t esr) +{ + uint32_t EC = (uint32_t)esr >> 26; + + switch (EC) + { + case 0b000000: + printf("Unknown reason"); + break; + case 0b000001: + printf("Trapped WFI or WFE instruction execution"); + break; + case 0b000011: + printf("Trapped MCR or MRC access with (coproc==0b1111) that " + "is not reported using EC 0b000000"); + break; + case 0b000100: + printf("Trapped MCRR or MRRC access with (coproc==0b1111) " + "that is not reported using EC 0b000000"); + break; + case 0b000101: + printf("Trapped MCR or MRC access with (coproc==0b1110)"); + break; + case 0b000110: + printf("Trapped LDC or STC access"); + break; + case 0b000111: + printf("Trapped access to SVE, Advanced SIMD, or " + "floating-point functionality"); + break; + case 0b001100: + printf("Trapped MRRC access with (coproc==0b1110)"); + break; + case 0b001101: + printf("Branch Target Exception"); + break; + case 0b001110: + printf("Illegal Execution state"); + break; + case 0b010001: + printf("SVC instruction execution in AArch32 state"); + break; + case 0b011000: + printf("Trapped MSR, MRS or System instruction execution in " + "AArch64 state, that is not reported using EC " + "0b000000, 0b000001 or 0b000111"); + break; + case 0b011001: + printf("Trapped access to SVE functionality"); + break; + case 0b100000: + printf("Instruction Abort from a lower Exception level, that " + "might be using AArch32 or AArch64"); + break; + case 0b100001: + printf("Instruction Abort taken without a change in Exception " + "level."); + break; + case 0b100010: + printf("PC alignment fault exception."); + break; + case 0b100100: + printf("Data Abort from a lower Exception level, that might " + "be using AArch32 or AArch64"); + break; + case 0b100101: + printf("Data Abort taken without a change in Exception level"); + break; + case 0b100110: + printf("SP alignment fault exception"); + break; + case 0b101000: + printf("Trapped floating-point exception taken from AArch32 " + "state"); + break; + case 0b101100: + printf("Trapped floating-point exception taken from AArch64 " + "state."); + break; + case 0b101111: + printf("SError interrupt"); + break; + case 0b110000: + printf("Breakpoint exception from a lower Exception level, " + "that might be using AArch32 or AArch64"); + break; + case 0b110001: + printf("Breakpoint exception taken without a change in " + "Exception level"); + break; + case 0b110010: + printf("Software Step exception from a lower Exception level, " + "that might be using AArch32 or AArch64"); + break; + case 0b110011: + printf("Software Step exception taken without a change in " + "Exception level"); + break; + case 0b110100: + printf("Watchpoint exception from a lower Exception level, " + "that might be using AArch32 or AArch64"); + break; + case 0b110101: + printf("Watchpoint exception taken without a change in " + "Exception level."); + break; + case 0b111000: + printf("BKPT instruction execution in AArch32 state"); + break; + case 0b111100: + printf("BRK instruction execution in AArch64 state."); + break; + } + printf("\n"); +} + +void ShowRegister(exception_frame *regs) +{ + printf("Execption:\n"); + printf("r00:0x%x r01:0x%x r02:0x%x r03:0x%x\r\n", regs->x0, regs->x1, regs->x2, regs->x3); + printf("r04:0x%x r05:0x%x r06:0x%x r07:0x%x\r\n", regs->x4, regs->x5, regs->x6, regs->x7); + printf("r08:0x%x r09:0x%x r10:0x%x r11:0x%x\r\n", regs->x8, regs->x9, regs->x10, regs->x11); + printf("r12:0x%x r13:0x%x r14:0x%x r15:0x%x\r\n", regs->x12, regs->x13, regs->x14, regs->x15); + printf("r16:0x%x r17:0x%x r18:0x%x r19:0x%x\r\n", regs->x16, regs->x17, regs->x18, regs->x19); + printf("r20:0x%x r21:0x%x r22:0x%x r23:0x%x\r\n", regs->x20, regs->x21, regs->x22, regs->x23); + printf("r24:0x%x r25:0x%x r26:0x%x r27:0x%x\r\n", regs->x24, regs->x25, regs->x26, regs->x27); + printf("r28:0x%x r29:0x%x r30:0x%x\r\n", regs->x28, regs->x29, regs->x30); + printf("exc_type 0x%x\r\n", regs->exc_type); + printf("exc_esr 0x%x\r\n", regs->exc_esr); + printf("exc_sp 0x%x\r\n", regs->exc_sp); + printf("exc_spsr 0x%x\r\n", regs->exc_spsr); + printf("exc_elr 0x%x\r\n", regs->exc_elr); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void SerrHandle(exception_frame *regs) +{ + uint64_t esr, far; + uint64_t ec, iss; + + printf("error exception:\n"); + esr = aarch64_read_sysreg(esr_el1); + far = aarch64_read_sysreg(far_el1); + ec = (esr >> 26) & 0x3f; + iss = (esr >> 0) & 0x1ffffff; + printf("\nSError exception detected, ec:0x%x iss:0x%x far:0x%x\r\n", ec, iss, far); + print_EC_cause(esr); + ShowRegister(regs); + while (1) + { + /* code */ + } +} +#endif + +#ifdef CONFIG_TARGET_ARMV8_AARCH32 +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void ShowExceptionRegisters(struct ExceptionStack *regs) +{ + printf("Execption:\r\n"); + printf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\r\n", regs->r0, regs->r1, regs->r2, regs->r3); + printf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\r\n", regs->r4, regs->r5, regs->r6, regs->r7); + printf("r08:0x%08x r09:0x%08x r10:0x%08x\r\n", regs->r8, regs->r9, regs->r10); + printf("fp :0x%08x ip :0x%08x\r\n", regs->fp, regs->ip); + printf("sp :0x%08x lr :0x%08x pc :0x%08x\r\n", regs->sp, regs->lr, regs->pc); + printf("cpsr:0x%08x\r\n", regs->cpsr); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void PrfTrap(struct ExceptionStack *regs) +{ + printf("prefetch abort:\r\n"); + ShowExceptionRegisters(regs); +} +#endif + +#define GIC_ACK_INTID_MASK 0x000003ff + +int InterruptGetIrq(void); +void InterruptAck(int fiq_irq); + +void SystemIrqHandler(int ir) +{ + void *param; + IrqHandler isr_func; + extern struct IrqDesc isr_table[]; + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); + } + + /* end of interrupt */ + InterruptAck(ir); +} + +void IrqHandleException(void *value) +{ + void *param; + int ir; + IrqHandler isr_func; + extern struct IrqDesc isr_table[]; + + ir = InterruptGetIrq(); + if (ir == 1023) + { + /* Spurious interrupt */ + return; + } + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); + } + + /* end of interrupt */ + InterruptAck(ir); +} + +void fiq_handle(void) +{ } \ No newline at end of file diff --git a/bsp/common/trap.h b/bsp/common/trap.h index ae9e4f6cd..6fc97c4ca 100644 --- a/bsp/common/trap.h +++ b/bsp/common/trap.h @@ -1,63 +1,63 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-30 16:51:57 - * @LastEditTime: 2021-07-01 11:24:10 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ -#ifndef BSP_COMMON_TRAP_H -#define BSP_COMMON_TRAP_H -#include "sdkconfig.h" -#include "exception.h" - -#ifdef CONFIG_TARGET_ARMV8_AARCH64 -void ShowRegister(exception_frame *regs); - -/** - * When comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void SerrHandle(exception_frame *regs); -#endif - -#ifdef CONFIG_TARGET_ARMV8_AARCH32 -struct ExceptionStack -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; -}; -#endif - -int InterruptGetIrq(void); -void InterruptAck(int fiq_irq); - -void SystemIrqHandler(int ir); -void IrqHandleException(void *value); -void fiq_handle(void); - -#endif // ! +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-30 16:51:57 + * @LastEditTime: 2021-07-01 11:24:10 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ +#ifndef BSP_COMMON_TRAP_H +#define BSP_COMMON_TRAP_H +#include "sdkconfig.h" +#include "exception.h" + +#ifdef CONFIG_TARGET_ARMV8_AARCH64 +void ShowRegister(exception_frame *regs); + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void SerrHandle(exception_frame *regs); +#endif + +#ifdef CONFIG_TARGET_ARMV8_AARCH32 +struct ExceptionStack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; +#endif + +int InterruptGetIrq(void); +void InterruptAck(int fiq_irq); + +void SystemIrqHandler(int ir); +void IrqHandleException(void *value); +void fiq_handle(void); + +#endif // ! diff --git a/bsp/drivers/Kconfig b/bsp/drivers/Kconfig index d6300c2f9..6dcf1b7ef 100644 --- a/bsp/drivers/Kconfig +++ b/bsp/drivers/Kconfig @@ -1,47 +1,60 @@ -menu "Components Configuration" - -config USE_SPI - bool - prompt "Use Spi" - default n - help - Include SPI modules and enable SPI - - if USE_SPI - source "$(SDK_ROOT)/bsp/drivers/spi/Kconfig" - endif - -config USE_QSPI - bool - prompt "Use QSpi" - default n - help - Include QSPI modules and enable QSPI - - if USE_QSPI - source "$(SDK_ROOT)/bsp/drivers/qspi/Kconfig" - endif - -config USE_GIC - bool - prompt "Use Gic" - default y - help - Include Generic Interrupt Controllor - - if USE_GIC - source "$(SDK_ROOT)/bsp/drivers/gic/Kconfig" - endif - -config USE_USART - bool - prompt "Use Usart" - default n - help - Include USART modules and enable USART - - if USE_USART - source "$(SDK_ROOT)/bsp/drivers/usart/Kconfig" - endif - +menu "Components Configuration" + +config USE_SPI + bool + prompt "Use Spi" + default n + help + Include SPI modules and enable SPI + + if USE_SPI + source "$(SDK_ROOT)/bsp/drivers/spi/Kconfig" + endif + +config USE_QSPI + bool + prompt "Use QSpi" + default n + help + Include QSPI modules and enable QSPI + + if USE_QSPI + source "$(SDK_ROOT)/bsp/drivers/qspi/Kconfig" + endif + +config USE_GIC + bool + prompt "Use Gic" + default y + help + Include Generic Interrupt Controllor + + if USE_GIC + source "$(SDK_ROOT)/bsp/drivers/gic/Kconfig" + endif + +config USE_USART + bool + prompt "Use Usart" + default n + help + Include USART modules and enable USART + + if USE_USART + source "$(SDK_ROOT)/bsp/drivers/usart/Kconfig" + endif + + +config USE_GPIO + bool + prompt "Use Gpio" + default n + help + Include GPIO modules and enable GPIO + + if USE_GPIO + source "$(SDK_ROOT)/bsp/drivers/gpio/Kconfig" + endif + + endmenu \ No newline at end of file diff --git a/bsp/drivers/gic/Kconfig b/bsp/drivers/gic/Kconfig index cd4485941..c384e0c2b 100644 --- a/bsp/drivers/gic/Kconfig +++ b/bsp/drivers/gic/Kconfig @@ -1,6 +1,6 @@ -menu "Gic Configuration" - config EBABLE_GICV3 - bool - prompt "Use Generic Interrupt Controller v3" - default y +menu "Gic Configuration" + config EBABLE_GICV3 + bool + prompt "Use Generic Interrupt Controller v3" + default y endmenu \ No newline at end of file diff --git a/bsp/drivers/gic/gicv3_arrch32/gicv3.c b/bsp/drivers/gic/gicv3_arrch32/gicv3.c index 206285a59..2a41db211 100644 --- a/bsp/drivers/gic/gicv3_arrch32/gicv3.c +++ b/bsp/drivers/gic/gicv3_arrch32/gicv3.c @@ -1,735 +1,735 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-22 13:21:52 - * @LastEditTime: 2021-06-25 16:25:17 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "sdkconfig.h" -#include "ft_types.h" -#include "ft_assert.h" -#include "parameters.h" -#include "gicv3.h" -#include "cp15.h" -#include -#include "sdkconfig.h" -#include "ft_debug.h" - -#ifndef RT_CPUS_NR -#define RT_CPUS_NR 1 -#define GIC_MAX_NR RT_CPUS_NR -#endif - -struct ArmGicv3 -{ - u32 offset; /* the first interrupt index in the vector table */ - u32 redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ - u32 dist_hw_base; /* the base address of the gic distributor */ - u32 cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ -}; - -/* 'GIC_MAX_NR' is the number of cores */ -static struct ArmGicv3 _gic_table[GIC_MAX_NR]; -static unsigned int _gic_max_irq; - -/** - * @name: ArmGicCpuMaskToAffval - * @msg: - * @in param cpu_mask: - * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] - * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the - * PE within a cluster with an Affinity 0 value equal to the bit number. - * @return {u32} 0 is finish , 1 is data valid - */ -_WEAK u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list) -{ - return 0; -} - -_WEAK u64 GetMainCpuAffval(void) -{ - return 0; -} - -/* get next active irq */ -int ArmGicGetActiveIrq(u32 index) -{ - int irq; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - __get_gicv3_reg(ICC_IAR1, irq); - - irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; - return irq; -} - -void ArmGicAck(u32 index, int irq) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - FT_ASSERTVOID(irq >= 0); - - __asm__ volatile("dsb 0xF" :: - : "memory"); - __set_gicv3_reg(ICC_EOIR1, irq); -} - -void ArmGicMask(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - s32 cpu_id = cp15_get_cpu_id(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; - } - else - { - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void ArmGicUmask(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - s32 cpu_id = cp15_get_cpu_id(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; - } - else - { - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -u32 ArmGicGetPendingIrq(u32 index, int irq) -{ - u32 pend; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - if (irq >= 16) - { - pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - /* No CPU identification offered */ - if (pend != 0U) - { - pend = 1U; - } - else - { - pend = 0U; - } - } - - return (pend); -} - -void ArmGicSetPendingIrq(u32 index, int irq) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - if (irq >= 16) - { - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - /* Forward the interrupt to the CPU interface that requested it */ - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); - } -} - -void ArmGicClearPendingIrq(u32 index, int irq) -{ - u32 mask; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - if (irq >= 16) - { - mask = 1U << (irq % 32U); - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } - else - { - mask = 1U << ((irq % 4U) * 8U); - GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void ArmGicSetConfiguration(u32 index, int irq, uint32_t config) -{ - u32 icfgr; - u32 shift; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); - shift = (irq % 16U) << 1U; - - icfgr &= (~(3U << shift)); - icfgr |= (config << shift); - - GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; -} - -u32 ArmGicGetConfiguration(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); -} - -void ArmGicClearActive(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -/* Set up the cpu mask for the specific interrupt */ -void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask) -{ - u32 old_tgt; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); - old_tgt |= cpumask << ((irq % 4U) * 8U); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -u32 ArmGicGetTargetCpu(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; -} - -void ArmGicSetPriority(u32 index, int irq, u32 priority) -{ - u32 mask; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - s32 cpu_id = cp15_get_cpu_id(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - - mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; - } - else - { - mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -u32 ArmGicGetPriority(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - if (irq < 32) - { - s32 cpu_id = cp15_get_cpu_id(); - - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - } - else - { - return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - } -} - -void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - value &= 0xFFUL; - /* enable irq and fiq */ - __set_gicv3_reg(ICC_SRE, value); - __asm__ volatile("isb 0xF" :: - : "memory"); -} - -u32 ArmGicGetSystemRegisterEnableMask(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - u32 value; - - __get_gicv3_reg(ICC_SRE, value); - return value; -} - -void ArmGicSetInterfacePriorMask(u32 index, u32 priority) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - priority &= 0xFFUL; - /* set priority mask */ - __set_gicv3_reg(ICC_PMR, priority); -} - -u32 ArmGicGetInterfacePriorMask(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - u32 priority; - - __get_gicv3_reg(ICC_PMR, priority); - return priority; -} - -void ArmGicSetBinaryPoint(u32 index, u32 binary_point) -{ - index = index; - binary_point &= 0x7U; - - __set_gicv3_reg(ICC_BPR1, binary_point); -} - -u32 ArmGicGetBinaryPoint(u32 index) -{ - u32 binary_point; - - index = index; - __get_gicv3_reg(ICC_BPR1, binary_point); - return binary_point; -} - -u32 ArmGicGetIrqStatus(u32 index, int irq) -{ - u32 pending; - u32 active; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - - return ((active << 1U) | pending); -} - -void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode) -{ - u64 sgi_val; - - if (routing_mode) - { - sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". - /* Write the ICC_SGI1R registers */ - __asm__ volatile("dsb 0xF" :: - : "memory"); - __set_cp64(15, 0, sgi_val, 12); - __asm__ volatile("isb 0xF" :: - : "memory"); - } - else - { - u32 cluster_id, target_list; - while (ArmGicCpuMaskToAffval(&cpu_mask, &cluster_id, &target_list)) - { - sgi_val = ((irq & 0x0FULL) << 24 | - target_list | - ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | - ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | - ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); - - __asm__ volatile("dsb 0xF" :: - : "memory"); - __set_cp64(15, 0, sgi_val, 12); - __asm__ volatile("isb 0xF" :: - : "memory"); - } - } -} - -u32 ArmGicGetHighPendingIrq(u32 index) -{ - u32 irq; - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - index = index; - __get_gicv3_reg(ICC_HPPIR1, irq); - return irq; -} - -u32 ArmGicGetInterfaceId(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); -} - -void ArmGicSetGroup(u32 index, int irq, u32 group) -{ - uint32_t igroupr; - uint32_t shift; - - FT_ASSERTVOID(index < GIC_MAX_NR); - FT_ASSERTVOID(group <= 1U); - - irq = irq - _gic_table[index].offset; - FT_ASSERTVOID(irq >= 0); - - igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); - shift = (irq % 32U); - igroupr &= (~(1U << shift)); - igroupr |= ((group & 0x1U) << shift); - - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; -} - -u32 ArmGicGetGroup(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; -} - -static int arm_gicv3_wait_rwp(u32 index, u32 irq) -{ - u32 rwp_bit; - u32 base; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - if (irq < 32) - { - s32 cpu_id = cp15_get_cpu_id(); - - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - base = _gic_table[index].redist_hw_base[cpu_id]; - rwp_bit = GICR_CTLR_RWP; - } - else - { - base = _gic_table[index].dist_hw_base; - rwp_bit = GICD_CTLR_RWP; - } - - while (__REG32(base) & rwp_bit) - { - ; - } - - return 0; -} - -int ArmGicDistInit(u32 index, u32 dist_base, int irq_start) -{ - u64 cpu0_affval; - unsigned int gic_type, i; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - // printf("index: %d, offset: 0x%x, redist_hw_base: 0x%x, dist_hw_base: 0x%x, cpu_hw_base: 0x%x\r\n", - // index, - // _gic_table[index].offset, - // _gic_table[index].redist_hw_base[0], - // _gic_table[index].dist_hw_base, - // _gic_table[index].cpu_hw_base[0] - // ); - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020U) - _gic_max_irq = 1020U; - if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ - _gic_max_irq = ARM_GIC_NR_IRQS; - - GIC_DIST_CTRL(dist_base) = 0x0U; - /* Wait for register write pending */ - arm_gicv3_wait_rwp(0, 32); - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32U; i < _gic_max_irq; i += 16U) - GIC_DIST_CONFIG(dist_base, i) = 0x0U; - - arm_gicv3_wait_rwp(0, 32); - - cpu0_affval = GetMainCpuAffval(); - /* Set all global interrupts to this CPU only. */ - for (i = 32U; i < _gic_max_irq; i++) - { - GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; - GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; - } - - arm_gicv3_wait_rwp(0, 32); - - /* Set priority on spi interrupts. */ - for (i = 32U; i < _gic_max_irq; i += 4U) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; - - arm_gicv3_wait_rwp(0, 32); - /* Disable all interrupts. */ - for (i = 0U; i < _gic_max_irq; i += 32U) - { - GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; - } - - arm_gicv3_wait_rwp(0, 32); - /* All interrupts defaults to IGROUP1(IRQ). */ - for (i = 0U; i < _gic_max_irq; i += 32U) - GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; - - arm_gicv3_wait_rwp(0, 32); - - /* - The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. - Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. - If affinity routing is not enabled, GICv3 can be configured for legacy operation. - Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. - Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: - GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. - GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. - GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. - */ - GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; - - return 0; -} - -int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - _gic_table[index].redist_hw_base[cpu_id] = redist_addr; - - return 0; -} - -int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; - - return 0; -} - -int ArmGicRedistInit(u32 index) -{ - unsigned int i; - u32 base; - s32 cpu_id = cp15_get_cpu_id(); - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - - base = _gic_table[index].redist_hw_base[cpu_id]; - /* redistributor enable */ - GIC_RDIST_WAKER(base) &= ~(1U << 1); - while (GIC_RDIST_WAKER(base) & (1 << 2)) - { - ; - } - - /* Disable all sgi and ppi interrupt */ - GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; - arm_gicv3_wait_rwp(0, 0); - - /* Clear all inetrrupt pending */ - GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; - - /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ - GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; - GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; - - /* Configure default priorities for SGI 0:15 and PPI 16:31. */ - for (i = 0; i < 32; i += 4) - { - GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; - } - - /* Trigger level for PPI interrupts*/ - GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. - return 0; -} - -int ArmGicCpuInit(u32 index) -{ - u32 value; - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - /* Enable System register interface */ - value = ArmGicGetSystemRegisterEnableMask(index); - value |= (1U << 0); - ArmGicSetSystemRegisterEnableMask(index, value); - - __set_gicv3_reg(ICC_CTLR, 0); - - ArmGicSetInterfacePriorMask(index, 0xFFU); - - /* Enable group1 interrupt */ - value = 0x1U; - __set_gicv3_reg(ICC_IGRPEN1, value); - - ArmGicSetBinaryPoint(0, 0); - - /* ICC_BPR0_EL1 determines the preemption group for both - Group 0 and Group 1 interrupts. - */ - value = 0x1U; - __set_gicv3_reg(ICC_CTLR, value); - - return 0; -} - -#ifdef RT_USING_SMP -void ArmGicSecondaryCpuInit(void) -{ - ArmGicRedistInit(0); - - ArmGicCpuInit(0); -} -#endif - -void ArmGicDumpType(u32 index) -{ - unsigned int gic_type; - - // printf("GIC distributor base addr 0x%x\r\n", _gic_table[index].dist_hw_base); - // printf("GIC redistributor base addr 0x%x\r\n", _gic_table[index].redist_hw_base[0]); - // printf("GIC cpu interface base addr 0x%x\r\n", _gic_table[index].cpu_hw_base[0]); - // printf("GIC offset 0x%x\r\n", _gic_table[index].offset); - - // GIC_DIST_CTRL(_gic_table[index].dist_hw_base) |= GICD_CTLR_ARE_NS; - // printf("GIC distributor CTRL: 0x%x\r\n", GIC_DIST_CTRL(_gic_table[index].dist_hw_base)); - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - printf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\r\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1U << 10U) ? "has" : "no", - gic_type); -} - -void ArmGicDump(u32 index) -{ - unsigned int i, k; - - k = ArmGicGetHighPendingIrq(0); - printf("--- high pending priority: %d(%08x)\r\n", k, k); - printf("--- hw mask ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - - printf("\r\n--- hw pending ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - - printf("\r\n--- hw active ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - - printf("\r\n"); -} - -long gic_dump(void) -{ - ArmGicDumpType(0); - ArmGicDump(0); - - return 0; +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-22 13:21:52 + * @LastEditTime: 2021-06-25 16:25:17 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "sdkconfig.h" +#include "ft_types.h" +#include "ft_assert.h" +#include "parameters.h" +#include "gicv3.h" +#include "cp15.h" +#include +#include "sdkconfig.h" +#include "ft_debug.h" + +#ifndef RT_CPUS_NR +#define RT_CPUS_NR 1 +#define GIC_MAX_NR RT_CPUS_NR +#endif + +struct ArmGicv3 +{ + u32 offset; /* the first interrupt index in the vector table */ + u32 redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ + u32 dist_hw_base; /* the base address of the gic distributor */ + u32 cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ +}; + +/* 'GIC_MAX_NR' is the number of cores */ +static struct ArmGicv3 _gic_table[GIC_MAX_NR]; +static unsigned int _gic_max_irq; + +/** + * @name: ArmGicCpuMaskToAffval + * @msg: + * @in param cpu_mask: + * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] + * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the + * PE within a cluster with an Affinity 0 value equal to the bit number. + * @return {u32} 0 is finish , 1 is data valid + */ +_WEAK u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list) +{ + return 0; +} + +_WEAK u64 GetMainCpuAffval(void) +{ + return 0; +} + +/* get next active irq */ +int ArmGicGetActiveIrq(u32 index) +{ + int irq; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + __get_gicv3_reg(ICC_IAR1, irq); + + irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; + return irq; +} + +void ArmGicAck(u32 index, int irq) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + FT_ASSERTVOID(irq >= 0); + + __asm__ volatile("dsb 0xF" :: + : "memory"); + __set_gicv3_reg(ICC_EOIR1, irq); +} + +void ArmGicMask(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + s32 cpu_id = cp15_get_cpu_id(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void ArmGicUmask(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + s32 cpu_id = cp15_get_cpu_id(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +u32 ArmGicGetPendingIrq(u32 index, int irq) +{ + u32 pend; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + if (irq >= 16) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void ArmGicSetPendingIrq(u32 index, int irq) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + if (irq >= 16) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void ArmGicClearPendingIrq(u32 index, int irq) +{ + u32 mask; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + if (irq >= 16) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void ArmGicSetConfiguration(u32 index, int irq, uint32_t config) +{ + u32 icfgr; + u32 shift; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +u32 ArmGicGetConfiguration(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); +} + +void ArmGicClearActive(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask) +{ + u32 old_tgt; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); + old_tgt |= cpumask << ((irq % 4U) * 8U); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +u32 ArmGicGetTargetCpu(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void ArmGicSetPriority(u32 index, int irq, u32 priority) +{ + u32 mask; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + s32 cpu_id = cp15_get_cpu_id(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + + mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; + } + else + { + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +u32 ArmGicGetPriority(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + if (irq < 32) + { + s32 cpu_id = cp15_get_cpu_id(); + + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } + else + { + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } +} + +void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + value &= 0xFFUL; + /* enable irq and fiq */ + __set_gicv3_reg(ICC_SRE, value); + __asm__ volatile("isb 0xF" :: + : "memory"); +} + +u32 ArmGicGetSystemRegisterEnableMask(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + u32 value; + + __get_gicv3_reg(ICC_SRE, value); + return value; +} + +void ArmGicSetInterfacePriorMask(u32 index, u32 priority) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + priority &= 0xFFUL; + /* set priority mask */ + __set_gicv3_reg(ICC_PMR, priority); +} + +u32 ArmGicGetInterfacePriorMask(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + u32 priority; + + __get_gicv3_reg(ICC_PMR, priority); + return priority; +} + +void ArmGicSetBinaryPoint(u32 index, u32 binary_point) +{ + index = index; + binary_point &= 0x7U; + + __set_gicv3_reg(ICC_BPR1, binary_point); +} + +u32 ArmGicGetBinaryPoint(u32 index) +{ + u32 binary_point; + + index = index; + __get_gicv3_reg(ICC_BPR1, binary_point); + return binary_point; +} + +u32 ArmGicGetIrqStatus(u32 index, int irq) +{ + u32 pending; + u32 active; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode) +{ + u64 sgi_val; + + if (routing_mode) + { + sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". + /* Write the ICC_SGI1R registers */ + __asm__ volatile("dsb 0xF" :: + : "memory"); + __set_cp64(15, 0, sgi_val, 12); + __asm__ volatile("isb 0xF" :: + : "memory"); + } + else + { + u32 cluster_id, target_list; + while (ArmGicCpuMaskToAffval(&cpu_mask, &cluster_id, &target_list)) + { + sgi_val = ((irq & 0x0FULL) << 24 | + target_list | + ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | + ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | + ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); + + __asm__ volatile("dsb 0xF" :: + : "memory"); + __set_cp64(15, 0, sgi_val, 12); + __asm__ volatile("isb 0xF" :: + : "memory"); + } + } +} + +u32 ArmGicGetHighPendingIrq(u32 index) +{ + u32 irq; + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + index = index; + __get_gicv3_reg(ICC_HPPIR1, irq); + return irq; +} + +u32 ArmGicGetInterfaceId(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void ArmGicSetGroup(u32 index, int irq, u32 group) +{ + uint32_t igroupr; + uint32_t shift; + + FT_ASSERTVOID(index < GIC_MAX_NR); + FT_ASSERTVOID(group <= 1U); + + irq = irq - _gic_table[index].offset; + FT_ASSERTVOID(irq >= 0); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ((group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +u32 ArmGicGetGroup(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; +} + +static int arm_gicv3_wait_rwp(u32 index, u32 irq) +{ + u32 rwp_bit; + u32 base; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + if (irq < 32) + { + s32 cpu_id = cp15_get_cpu_id(); + + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + base = _gic_table[index].redist_hw_base[cpu_id]; + rwp_bit = GICR_CTLR_RWP; + } + else + { + base = _gic_table[index].dist_hw_base; + rwp_bit = GICD_CTLR_RWP; + } + + while (__REG32(base) & rwp_bit) + { + ; + } + + return 0; +} + +int ArmGicDistInit(u32 index, u32 dist_base, int irq_start) +{ + u64 cpu0_affval; + unsigned int gic_type, i; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + // printf("index: %d, offset: 0x%x, redist_hw_base: 0x%x, dist_hw_base: 0x%x, cpu_hw_base: 0x%x\r\n", + // index, + // _gic_table[index].offset, + // _gic_table[index].redist_hw_base[0], + // _gic_table[index].dist_hw_base, + // _gic_table[index].cpu_hw_base[0] + // ); + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020U) + _gic_max_irq = 1020U; + if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = ARM_GIC_NR_IRQS; + + GIC_DIST_CTRL(dist_base) = 0x0U; + /* Wait for register write pending */ + arm_gicv3_wait_rwp(0, 32); + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32U; i < _gic_max_irq; i += 16U) + GIC_DIST_CONFIG(dist_base, i) = 0x0U; + + arm_gicv3_wait_rwp(0, 32); + + cpu0_affval = GetMainCpuAffval(); + /* Set all global interrupts to this CPU only. */ + for (i = 32U; i < _gic_max_irq; i++) + { + GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; + GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; + } + + arm_gicv3_wait_rwp(0, 32); + + /* Set priority on spi interrupts. */ + for (i = 32U; i < _gic_max_irq; i += 4U) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; + + arm_gicv3_wait_rwp(0, 32); + /* Disable all interrupts. */ + for (i = 0U; i < _gic_max_irq; i += 32U) + { + GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; + } + + arm_gicv3_wait_rwp(0, 32); + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; + + arm_gicv3_wait_rwp(0, 32); + + /* + The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. + Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. + If affinity routing is not enabled, GICv3 can be configured for legacy operation. + Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. + Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: + GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. + GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. + GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. + */ + GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; + + return 0; +} + +int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + _gic_table[index].redist_hw_base[cpu_id] = redist_addr; + + return 0; +} + +int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; + + return 0; +} + +int ArmGicRedistInit(u32 index) +{ + unsigned int i; + u32 base; + s32 cpu_id = cp15_get_cpu_id(); + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + + base = _gic_table[index].redist_hw_base[cpu_id]; + /* redistributor enable */ + GIC_RDIST_WAKER(base) &= ~(1U << 1); + while (GIC_RDIST_WAKER(base) & (1 << 2)) + { + ; + } + + /* Disable all sgi and ppi interrupt */ + GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; + arm_gicv3_wait_rwp(0, 0); + + /* Clear all inetrrupt pending */ + GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; + + /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ + GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; + GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; + + /* Configure default priorities for SGI 0:15 and PPI 16:31. */ + for (i = 0; i < 32; i += 4) + { + GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; + } + + /* Trigger level for PPI interrupts*/ + GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. + return 0; +} + +int ArmGicCpuInit(u32 index) +{ + u32 value; + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + /* Enable System register interface */ + value = ArmGicGetSystemRegisterEnableMask(index); + value |= (1U << 0); + ArmGicSetSystemRegisterEnableMask(index, value); + + __set_gicv3_reg(ICC_CTLR, 0); + + ArmGicSetInterfacePriorMask(index, 0xFFU); + + /* Enable group1 interrupt */ + value = 0x1U; + __set_gicv3_reg(ICC_IGRPEN1, value); + + ArmGicSetBinaryPoint(0, 0); + + /* ICC_BPR0_EL1 determines the preemption group for both + Group 0 and Group 1 interrupts. + */ + value = 0x1U; + __set_gicv3_reg(ICC_CTLR, value); + + return 0; +} + +#ifdef RT_USING_SMP +void ArmGicSecondaryCpuInit(void) +{ + ArmGicRedistInit(0); + + ArmGicCpuInit(0); +} +#endif + +void ArmGicDumpType(u32 index) +{ + unsigned int gic_type; + + // printf("GIC distributor base addr 0x%x\r\n", _gic_table[index].dist_hw_base); + // printf("GIC redistributor base addr 0x%x\r\n", _gic_table[index].redist_hw_base[0]); + // printf("GIC cpu interface base addr 0x%x\r\n", _gic_table[index].cpu_hw_base[0]); + // printf("GIC offset 0x%x\r\n", _gic_table[index].offset); + + // GIC_DIST_CTRL(_gic_table[index].dist_hw_base) |= GICD_CTLR_ARE_NS; + // printf("GIC distributor CTRL: 0x%x\r\n", GIC_DIST_CTRL(_gic_table[index].dist_hw_base)); + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + printf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\r\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); +} + +void ArmGicDump(u32 index) +{ + unsigned int i, k; + + k = ArmGicGetHighPendingIrq(0); + printf("--- high pending priority: %d(%08x)\r\n", k, k); + printf("--- hw mask ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + + printf("\r\n--- hw pending ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + + printf("\r\n--- hw active ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + + printf("\r\n"); +} + +long gic_dump(void) +{ + ArmGicDumpType(0); + ArmGicDump(0); + + return 0; } \ No newline at end of file diff --git a/bsp/drivers/gic/gicv3_arrch32/gicv3.h b/bsp/drivers/gic/gicv3_arrch32/gicv3.h index 4ff30efca..c41616805 100644 --- a/bsp/drivers/gic/gicv3_arrch32/gicv3.h +++ b/bsp/drivers/gic/gicv3_arrch32/gicv3.h @@ -1,220 +1,220 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-06-22 13:21:45 - * @LastEditTime: 2021-06-23 13:17:31 - * @Description:  This files is for - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _BSP_DRIVERS_GIC_AARCH32_GICV3_H -#define _BSP_DRIVERS_GIC_AARCH32_GICV3_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* For AArch32 state, - accesses to GIC registers that are visible in the System register */ -#define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR \ - : "=r"(Rt) \ - : \ - : "memory") -#define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \ - : \ - : "r"(Rt) \ - : "memory") - -/* AArch32 System register interface to GICv3 */ -/* Group 0, reads this register to obtain the INTID, acts as -an acknowledge for the interrupt */ -#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" -/* Group 1 */ -#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" -/* writes to this register to inform the CPU interface -that it has completed the processing */ -#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" -#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" -/* GET the INTID of highest priority pending interrupt */ -#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2" -#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2" -#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" -#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" -#define ICC_DIR "p15, 0, %0, c12, c11, 1" -#define ICC_PMR "p15, 0, %0, c4, c6, 0" -#define ICC_RPR "p15, 0, %0, c12, c11, 3" -#define ICC_CTLR "p15, 0, %0, c12, c12, 4" -#define ICC_MCTLR "p15, 6, %0, c12, c12, 4" -#define ICC_SRE "p15, 0, %0, c12, c12, 5" -#define ICC_HSRE "p15, 4, %0, c12, c9, 5" -#define ICC_MSRE "p15, 6, %0, c12, c12, 5" -#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" -#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" -#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7" - -#define __REG32(x) (*((volatile unsigned int *)((u32)x))) - -#define ROUTED_TO_ALL (1) -#define ROUTED_TO_SPEC (0) - -/** Macro to access the Distributor Control Register (GICD_CTLR) -*/ -#define GICD_CTLR_RWP (1 << 31) -#define GICD_CTLR_E1NWF (1 << 7) -#define GICD_CTLR_DS (1 << 6) -#define GICD_CTLR_ARE_NS (1 << 5) -#define GICD_CTLR_ARE_S (1 << 4) -#define GICD_CTLR_ENGRP1S (1 << 2) -#define GICD_CTLR_ENGRP1NS (1 << 1) -#define GICD_CTLR_ENGRP0 (1 << 0) - -/** Macro to access the Redistributor Control Register (GICR_CTLR) -*/ -#define GICR_CTLR_UWP (1 << 31) -#define GICR_CTLR_DPG1S (1 << 26) -#define GICR_CTLR_DPG1NS (1 << 25) -#define GICR_CTLR_DPG0 (1 << 24) -#define GICR_CTLR_RWP (1 << 3) -#define GICR_CTLR_IR (1 << 2) -#define GICR_CTLR_CES (1 << 1) -#define GICR_CTLR_EnableLPI (1 << 0) - -/** Macro to access the Generic Interrupt Controller Interface (GICC) -*/ -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) -#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) - -/** Macro to access the Generic Interrupt Controller Distributor (GICD) -*/ -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n) / 32U) * 4U) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n) / 32U) * 4U) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n) / 32U) * 4U) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n) / 32U) * 4U) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n) / 32U) * 4U) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n) / 32U) * 4U) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n) / 32U) * 4U) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n) / 4U) * 4U) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n) / 4U) * 4U) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) -#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) -#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) -#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) - -/* SGI base address is at 64K offset from Redistributor base address */ -#define GIC_RSGI_OFFSET 0x10000 - -/** Macro to access the Generic Interrupt Controller Redistributor (GICD) -*/ -#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) -#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) -#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) -#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) -#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) -#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) -#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) -#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) -#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) -#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) - -#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) -#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) -#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) -#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) -#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) -#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) -#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) -#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) -#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) -#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) -#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) -#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) - -#define GIC_RSGI_AFF1_OFFSET 16 -#define GIC_RSGI_AFF2_OFFSET 32 -#define GIC_RSGI_AFF3_OFFSET 48 - - u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list); - u64 GetMainCpuAffval(void); - int ArmGicGetActiveIrq(u32 index); - void ArmGicAck(u32 index, int irq); - - void ArmGicMask(u32 index, int irq); - void ArmGicUmask(u32 index, int irq); - - u32 ArmGicGetPendingIrq(u32 index, int irq); - void ArmGicSetPendingIrq(u32 index, int irq); - void ArmGicClearPendingIrq(u32 index, int irq); - - void ArmGicSetConfiguration(u32 index, int irq, uint32_t config); - u32 ArmGicGetConfiguration(u32 index, int irq); - - void ArmGicClearActive(u32 index, int irq); - - void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask); - u32 ArmGicGetTargetCpu(u32 index, int irq); - - void ArmGicSetPriority(u32 index, int irq, u32 priority); - u32 ArmGicGetPriority(u32 index, int irq); - - void ArmGicSetInterfacePriorMask(u32 index, u32 priority); - u32 ArmGicGetInterfacePriorMask(u32 index); - - void ArmGicSetBinaryPoint(u32 index, u32 binary_point); - u32 ArmGicGetBinaryPoint(u32 index); - - u32 ArmGicGetIrqStatus(u32 index, int irq); - - void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode); - u32 ArmGicGetHighPendingIrq(u32 index); - - u32 ArmGicGetInterfaceId(u32 index); - - void ArmGicSetGroup(u32 index, int irq, u32 group); - u32 ArmGicGetGroup(u32 index, int irq); - - int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id); - int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id); - int ArmGicDistInit(u32 index, u32 dist_base, int irq_start); - int ArmGicCpuInit(u32 index); - int ArmGicRedistInit(u32 index); - - void ArmGicDumpType(u32 index); - void ArmGicDump(u32 index); - - void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value); - u32 ArmGicGetSystemRegisterEnableMask(u32 index); - void ArmGicSecondaryCpuInit(void); - -/* for Gic trace */ -#include "ft_debug.h" - -#define GicV3_DEBUG_TAG "Gicv3" -#define GicV3_ERROR(format, ...) FT_DEBUG_PRINT_E(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) -#define GicV3_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) -#define GicV3_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) -#define GicV3_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) - -#ifdef __cplusplus -} -#endif - +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-06-22 13:21:45 + * @LastEditTime: 2021-06-23 13:17:31 + * @Description:  This files is for + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _BSP_DRIVERS_GIC_AARCH32_GICV3_H +#define _BSP_DRIVERS_GIC_AARCH32_GICV3_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* For AArch32 state, + accesses to GIC registers that are visible in the System register */ +#define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR \ + : "=r"(Rt) \ + : \ + : "memory") +#define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \ + : \ + : "r"(Rt) \ + : "memory") + +/* AArch32 System register interface to GICv3 */ +/* Group 0, reads this register to obtain the INTID, acts as +an acknowledge for the interrupt */ +#define ICC_IAR0 "p15, 0, %0, c12, c8, 0" +/* Group 1 */ +#define ICC_IAR1 "p15, 0, %0, c12, c12, 0" +/* writes to this register to inform the CPU interface +that it has completed the processing */ +#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1" +#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1" +/* GET the INTID of highest priority pending interrupt */ +#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2" +#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2" +#define ICC_BPR0 "p15, 0, %0, c12, c8, 3" +#define ICC_BPR1 "p15, 0, %0, c12, c12, 3" +#define ICC_DIR "p15, 0, %0, c12, c11, 1" +#define ICC_PMR "p15, 0, %0, c4, c6, 0" +#define ICC_RPR "p15, 0, %0, c12, c11, 3" +#define ICC_CTLR "p15, 0, %0, c12, c12, 4" +#define ICC_MCTLR "p15, 6, %0, c12, c12, 4" +#define ICC_SRE "p15, 0, %0, c12, c12, 5" +#define ICC_HSRE "p15, 4, %0, c12, c9, 5" +#define ICC_MSRE "p15, 6, %0, c12, c12, 5" +#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6" +#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7" +#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7" + +#define __REG32(x) (*((volatile unsigned int *)((u32)x))) + +#define ROUTED_TO_ALL (1) +#define ROUTED_TO_SPEC (0) + +/** Macro to access the Distributor Control Register (GICD_CTLR) +*/ +#define GICD_CTLR_RWP (1 << 31) +#define GICD_CTLR_E1NWF (1 << 7) +#define GICD_CTLR_DS (1 << 6) +#define GICD_CTLR_ARE_NS (1 << 5) +#define GICD_CTLR_ARE_S (1 << 4) +#define GICD_CTLR_ENGRP1S (1 << 2) +#define GICD_CTLR_ENGRP1NS (1 << 1) +#define GICD_CTLR_ENGRP0 (1 << 0) + +/** Macro to access the Redistributor Control Register (GICR_CTLR) +*/ +#define GICR_CTLR_UWP (1 << 31) +#define GICR_CTLR_DPG1S (1 << 26) +#define GICR_CTLR_DPG1NS (1 << 25) +#define GICR_CTLR_DPG0 (1 << 24) +#define GICR_CTLR_RWP (1 << 3) +#define GICR_CTLR_IR (1 << 2) +#define GICR_CTLR_CES (1 << 1) +#define GICR_CTLR_EnableLPI (1 << 0) + +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) + +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n) / 32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n) / 4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n) / 4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) +#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) +#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) + +/* SGI base address is at 64K offset from Redistributor base address */ +#define GIC_RSGI_OFFSET 0x10000 + +/** Macro to access the Generic Interrupt Controller Redistributor (GICD) +*/ +#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) +#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) +#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) +#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) +#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) +#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) +#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) +#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) +#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) +#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) + +#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) +#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) +#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) +#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) +#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) +#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) +#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) +#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) +#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) +#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) +#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) +#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) + +#define GIC_RSGI_AFF1_OFFSET 16 +#define GIC_RSGI_AFF2_OFFSET 32 +#define GIC_RSGI_AFF3_OFFSET 48 + + u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list); + u64 GetMainCpuAffval(void); + int ArmGicGetActiveIrq(u32 index); + void ArmGicAck(u32 index, int irq); + + void ArmGicMask(u32 index, int irq); + void ArmGicUmask(u32 index, int irq); + + u32 ArmGicGetPendingIrq(u32 index, int irq); + void ArmGicSetPendingIrq(u32 index, int irq); + void ArmGicClearPendingIrq(u32 index, int irq); + + void ArmGicSetConfiguration(u32 index, int irq, uint32_t config); + u32 ArmGicGetConfiguration(u32 index, int irq); + + void ArmGicClearActive(u32 index, int irq); + + void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask); + u32 ArmGicGetTargetCpu(u32 index, int irq); + + void ArmGicSetPriority(u32 index, int irq, u32 priority); + u32 ArmGicGetPriority(u32 index, int irq); + + void ArmGicSetInterfacePriorMask(u32 index, u32 priority); + u32 ArmGicGetInterfacePriorMask(u32 index); + + void ArmGicSetBinaryPoint(u32 index, u32 binary_point); + u32 ArmGicGetBinaryPoint(u32 index); + + u32 ArmGicGetIrqStatus(u32 index, int irq); + + void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode); + u32 ArmGicGetHighPendingIrq(u32 index); + + u32 ArmGicGetInterfaceId(u32 index); + + void ArmGicSetGroup(u32 index, int irq, u32 group); + u32 ArmGicGetGroup(u32 index, int irq); + + int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id); + int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id); + int ArmGicDistInit(u32 index, u32 dist_base, int irq_start); + int ArmGicCpuInit(u32 index); + int ArmGicRedistInit(u32 index); + + void ArmGicDumpType(u32 index); + void ArmGicDump(u32 index); + + void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value); + u32 ArmGicGetSystemRegisterEnableMask(u32 index); + void ArmGicSecondaryCpuInit(void); + +/* for Gic trace */ +#include "ft_debug.h" + +#define GicV3_DEBUG_TAG "Gicv3" +#define GicV3_ERROR(format, ...) FT_DEBUG_PRINT_E(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) +#define GicV3_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) +#define GicV3_DEBUG_D(format, ...) FT_DEBUG_PRINT_D(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) +#define GicV3_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(GicV3_DEBUG_TAG, format, ##__VA_ARGS__) + +#ifdef __cplusplus +} +#endif + #endif // ! \ No newline at end of file diff --git a/bsp/drivers/gic/gicv3_arrch64/gicv3.c b/bsp/drivers/gic/gicv3_arrch64/gicv3.c index 2ca01d42c..92632c11b 100644 --- a/bsp/drivers/gic/gicv3_arrch64/gicv3.c +++ b/bsp/drivers/gic/gicv3_arrch64/gicv3.c @@ -1,725 +1,725 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-27 14:12:51 - * @LastEditTime: 2021-05-27 14:12:51 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "gicv3.h" -#include "gicv3_cpuif.h" -#include "ft_types.h" -#include "ft_assert.h" -#include "_cpu.h" -#include - -#ifndef RT_CPUS_NR -#define RT_CPUS_NR 1 -#define GIC_MAX_NR RT_CPUS_NR -#define GIC_NR_IRQS 1500 -#endif - -struct ArmGicv3 -{ - s32 offset; /* the first interrupt index in the vector table */ - u32 redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ - u32 dist_hw_base; /* the base address of the gic distributor */ - u32 cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ -}; - -/* 'GIC_MAX_NR' is the number of cores */ -static struct ArmGicv3 _gic_table[GIC_MAX_NR]; -static u32 _gic_max_irq; - -/** - * @name: ArmGicCpuMaskToAffval - * @msg: - * @in param cpu_mask: - * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] - * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the - * PE within a cluster with an Affinity 0 value equal to the bit number. - * @return {u32} 0 is finish , 1 is data valid - */ -_WEAK u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list) -{ - return 0; -} - -_WEAK u64 GetMainCpuAffval(void) -{ - return 0; -} - -int ArmGicGetActiveIrq(u32 index) -{ - int irq; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - // __GET_GICV3_REG(ICC_IAR1, irq); - irq = readIARGrp1(); - - irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; - return irq; -} - -void ArmGicAck(u32 index, int irq) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - FT_ASSERTVOID(irq >= 0); - - __asm__ volatile("dsb 0xF" :: - : "memory"); - writeEOIGrp1(irq); - // __SET_GICV3_REG(ICC_EOIR1, irq); -} - -void ArmGicMask(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - u32 cpu_id = GetCpuId(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; - } - else - { - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void ArmGicUmask(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - u32 cpu_id = GetCpuId(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; - } - else - { - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -u32 ArmGicGetPendingIrq(u32 index, int irq) -{ - u32 pend; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - if (irq >= 16) - { - pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - /* No CPU identification offered */ - if (pend != 0U) - { - pend = 1U; - } - else - { - pend = 0U; - } - } - - return (pend); -} - -void ArmGicSetPendingIrq(u32 index, int irq) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - if (irq >= 16) - { - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); - } - else - { - /* INTID 0-15 Software Generated Interrupt */ - /* Forward the interrupt to the CPU interface that requested it */ - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); - } -} - -void ArmGicClearPendingIrq(u32 index, int irq) -{ - u32 mask; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - if (irq >= 16) - { - mask = 1U << (irq % 32U); - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - } - else - { - mask = 1U << ((irq % 4U) * 8U); - GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -void ArmGicSetConfiguration(u32 index, int irq, u32 config) -{ - u32 icfgr; - u32 shift; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); - shift = (irq % 16U) << 1U; - - icfgr &= (~(3U << shift)); - icfgr |= (config << shift); - - GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; -} - -u32 ArmGicGetConfiguration(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); -} - -void ArmGicClearActive(u32 index, int irq) -{ - u32 mask = 1U << (irq % 32U); - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -/* Set up the cpu mask for the specific interrupt */ -void ArmGicSetCpu(u32 index, int irq, u32 cpumask) -{ - u32 old_tgt; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); - old_tgt |= cpumask << ((irq % 4U) * 8U); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -u32 ArmGicGetTargetCpu(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; -} - -void ArmGicSetPriority(u32 index, int irq, u32 priority) -{ - u32 mask; - - FT_ASSERTVOID(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - if (irq < 32) - { - u32 cpu_id = GetCpuId(); - FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); - - mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; - } - else - { - mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); - mask &= ~(0xFFUL << ((irq % 4U) * 8U)); - mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); - GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; - } -} - -u32 ArmGicGetPriority(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - if (irq < 32) - { - u32 cpu_id = GetCpuId(); - - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - } - else - { - return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; - } -} - -void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - value &= 0xFFUL; - /* set priority mask */ - setICC_SRE_EL1(value); - // __SET_GICV3_REG(ICC_SRE, value); - __asm__ volatile("isb 0xF" :: - : "memory"); -} - -u32 ArmGicGetSystemRegisterEnableMask(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - u32 value; - - // __GET_GICV3_REG(ICC_SRE, value); - value = getICC_SRE_EL1(); - return value; -} - -void ArmGicSetInterfacePriorMask(u32 index, u32 priority) -{ - FT_ASSERTVOID(index < GIC_MAX_NR); - - priority &= 0xFFUL; - /* set priority mask */ - setPriorityMask(priority); - // __SET_GICV3_REG(ICC_PMR, priority); -} - -u32 ArmGicGetInterfacePriorMask(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - u32 priority; - priority = getPriorityMask(); - // __GET_GICV3_REG(ICC_PMR, priority); - return priority; -} - -void ArmGicSetBinaryPoint(u32 index, u32 binary_point) -{ - index = index; - binary_point &= 0x7U; - setBPR1(binary_point); - // __SET_GICV3_REG(ICC_BPR1, binary_point); -} - -u32 ArmGicGetBinaryPoint(u32 index) -{ - u32 binary_point; - - index = index; - // __GET_GICV3_REG(ICC_BPR1, binary_point); - binary_point = getBPR1(); - return binary_point; -} - -u32 ArmGicGetIrqStatus(u32 index, int irq) -{ - u32 pending; - u32 active; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; - - return ((active << 1U) | pending); -} - -void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode) -{ - // u64 sgi_val; - - if (routing_mode) - { - // sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". - /* Write the ICC_SGI1R registers */ - __asm__ volatile("dsb 0xF" :: - : "memory"); - // __set_cp64(15, 0, sgi_val, 12); - - sendGroup1SGI((irq & 0x0FULL) << 24, 1ULL << 40, 0); - __asm__ volatile("isb 0xF" :: - : "memory"); - } - else - { - u32 cluster_id, target_list; - while (ArmGicCpuMaskToAffval(&cpu_mask, &cluster_id, &target_list)) - { - // sgi_val = ((irq & 0x0FULL) << 24 | - // target_list | - // ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | - // ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | - // ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); - - __asm__ volatile("dsb 0xF" :: - : "memory"); - sendGroup1SGI((irq & 0x0FULL) << 24, 0, target_list | ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); - // __set_cp64(15, 0, sgi_val, 12); - __asm__ volatile("isb 0xF" :: - : "memory"); - } - } -} - -u32 ArmGicGetHighPendingIrq(u32 index) -{ - u32 irq; - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - index = index; - irq = getHPPIR1(); - // __GET_GICV3_REG(ICC_HPPIR1, irq); - return irq; -} - -u32 ArmGicGetInterfaceId(u32 index) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); -} - -void ArmGicSetGroup(u32 index, int irq, u32 group) -{ - u32 igroupr; - u32 shift; - - FT_ASSERTVOID(index < GIC_MAX_NR); - FT_ASSERTVOID(group <= 1U); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTVOID(irq >= 0); - - igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); - shift = (irq % 32U); - igroupr &= (~(1U << shift)); - igroupr |= ((group & 0x1U) << shift); - - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; -} - -u32 ArmGicGetGroup(u32 index, int irq) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - irq = (irq - _gic_table[index].offset); - FT_ASSERTZERONUM(irq >= 0); - - return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; -} - -static int ArmGicWaitRwp(u32 index, u32 irq) -{ - u32 rwp_bit; - u32 base; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - - if (irq < 32) - { - u32 cpu_id = GetCpuId(); - - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - base = _gic_table[index].redist_hw_base[cpu_id]; - rwp_bit = GICR_CTLR_RWP; - } - else - { - base = _gic_table[index].dist_hw_base; - rwp_bit = GICD_CTLR_RWP; - } - - while (__REG32(base) & rwp_bit) - { - ; - } - - return 0; -} - -int ArmGicDistInit(u32 index, u32 dist_base, int irq_start) -{ - u64 cpu0_affval; - u32 gic_type, i; - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020U) - _gic_max_irq = 1020U; - if (_gic_max_irq > GIC_NR_IRQS) /* the platform maximum interrupts */ - _gic_max_irq = GIC_NR_IRQS; - - GIC_DIST_CTRL(dist_base) = 0x0U; - /* Wait for register write pending */ - ArmGicWaitRwp(0, 32); - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32U; i < _gic_max_irq; i += 16U) - GIC_DIST_CONFIG(dist_base, i) = 0x0U; - - ArmGicWaitRwp(0, 32); - - cpu0_affval = GetMainCpuAffval(); - /* Set all global interrupts to this CPU only. */ - for (i = 32U; i < _gic_max_irq; i++) - { - GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; - GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; - } - - ArmGicWaitRwp(0, 32); - - /* Set priority on spi interrupts. */ - for (i = 32U; i < _gic_max_irq; i += 4U) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; - - ArmGicWaitRwp(0, 32); - /* Disable all interrupts. */ - for (i = 0U; i < _gic_max_irq; i += 32U) - { - GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; - } - - ArmGicWaitRwp(0, 32); - /* All interrupts defaults to IGROUP1(IRQ). */ - for (i = 0U; i < _gic_max_irq; i += 32U) - GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; - - ArmGicWaitRwp(0, 32); - - /* - The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. - Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. - If affinity routing is not enabled, GICv3 can be configured for legacy operation. - Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. - Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: - GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. - GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. - GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. - */ - GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; - - enableGroup1Ints(); - return 0; -} - -int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - _gic_table[index].redist_hw_base[cpu_id] = redist_addr; - - return 0; -} - -int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id) -{ - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; - - return 0; -} - -int ArmGicRedistInit(u32 index) -{ - u32 i; - u32 base; - u32 reg_value; - u32 cpu_id = GetCpuId(); - - FT_ASSERTZERONUM(index < GIC_MAX_NR); - FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); - - base = _gic_table[index].redist_hw_base[cpu_id]; - // printf("redist base %x \r\n", base); - /* redistributor enable */ - reg_value = GIC_RDIST_WAKER(base); - reg_value &= ~(1U << 1); - GIC_RDIST_WAKER(base) = reg_value; - - do - { - reg_value = GIC_RDIST_WAKER(base); - } while ((reg_value & 0x4) != 0); - - /* Disable all sgi and ppi interrupt */ - GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; - ArmGicWaitRwp(0, 0); - - /* Clear all inetrrupt pending */ - GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; - - /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ - GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; - GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; - - /* Configure default priorities for SGI 0:15 and PPI 16:31. */ - for (i = 0; i < 32; i += 4) - { - GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; - } - - /* Trigger level for PPI interrupts*/ - GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. - return 0; -} - -int ArmGicCpuInit(u32 index) -{ - u32 value; - FT_ASSERTZERONUM(index < GIC_MAX_NR); - value = ArmGicGetSystemRegisterEnableMask(index); - value |= (1U << 0); - ArmGicSetSystemRegisterEnableMask(index, value); - setICC_CTLR_EL1(0); - // __SET_GICV3_REG(ICC_CTLR, 0); - ArmGicSetInterfacePriorMask(index, 0xFFU); - /* Enable group1 interrupt */ - enableGroup1Ints(); - // __SET_GICV3_REG(ICC_IGRPEN1, value); - ArmGicSetBinaryPoint(0, 0); - - /* ICC_BPR0_EL1 determines the preemption group for both - Group 0 and Group 1 interrupts. - */ - value = 0x1U; - setICC_CTLR_EL1(value); - - // __SET_GICV3_REG(ICC_CTLR, value); - - return 0; -} - -#ifdef FT_USING_SMP -void ArmGicSecondaryCpuInit(void) -{ - ArmGicRedistInit(0); - - ArmGicCpuInit(0); -} -#endif - -void ArmGicDumpType(u32 index) -{ - u32 gic_type; - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - printf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\r\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1U << 10U) ? "has" : "no", - gic_type); -} - -void ArmGicDump(u32 index) -{ - u32 i, k; - - k = ArmGicGetHighPendingIrq(0); - printf("--- high pending priority: %d(%08x)\r\n", k, k); - printf("--- hw mask ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - printf("\r\n--- hw pending ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - printf("\r\n--- hw active ---\r\n"); - for (i = 0U; i < _gic_max_irq / 32U; i++) - { - printf("0x%08x, ", - GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, - i * 32U)); - } - printf("\r\n"); -} - -long gic_dump(void) -{ - ArmGicDumpType(0); - ArmGicDump(0); - - return 0; -} +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-27 14:12:51 + * @LastEditTime: 2021-05-27 14:12:51 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "gicv3.h" +#include "gicv3_cpuif.h" +#include "ft_types.h" +#include "ft_assert.h" +#include "_cpu.h" +#include + +#ifndef RT_CPUS_NR +#define RT_CPUS_NR 1 +#define GIC_MAX_NR RT_CPUS_NR +#define GIC_NR_IRQS 1500 +#endif + +struct ArmGicv3 +{ + s32 offset; /* the first interrupt index in the vector table */ + u32 redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */ + u32 dist_hw_base; /* the base address of the gic distributor */ + u32 cpu_hw_base[RT_CPUS_NR]; /* the base addrees of the gic cpu interface */ +}; + +/* 'GIC_MAX_NR' is the number of cores */ +static struct ArmGicv3 _gic_table[GIC_MAX_NR]; +static u32 _gic_max_irq; + +/** + * @name: ArmGicCpuMaskToAffval + * @msg: + * @in param cpu_mask: + * @out param cluster_id: aff1 [0:7],aff2 [8:15],aff3 [16:23] + * @out param target_list: Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the + * PE within a cluster with an Affinity 0 value equal to the bit number. + * @return {u32} 0 is finish , 1 is data valid + */ +_WEAK u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list) +{ + return 0; +} + +_WEAK u64 GetMainCpuAffval(void) +{ + return 0; +} + +int ArmGicGetActiveIrq(u32 index) +{ + int irq; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + // __GET_GICV3_REG(ICC_IAR1, irq); + irq = readIARGrp1(); + + irq = (irq & 0x1FFFFFF) + _gic_table[index].offset; + return irq; +} + +void ArmGicAck(u32 index, int irq) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + FT_ASSERTVOID(irq >= 0); + + __asm__ volatile("dsb 0xF" :: + : "memory"); + writeEOIGrp1(irq); + // __SET_GICV3_REG(ICC_EOIR1, irq); +} + +void ArmGicMask(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + u32 cpu_id = GetCpuId(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void ArmGicUmask(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + u32 cpu_id = GetCpuId(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + GIC_RDISTSGI_ISENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; + } + else + { + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +u32 ArmGicGetPendingIrq(u32 index, int irq) +{ + u32 pend; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + if (irq >= 16) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void ArmGicSetPendingIrq(u32 index, int irq) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + if (irq >= 16) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void ArmGicClearPendingIrq(u32 index, int irq) +{ + u32 mask; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + if (irq >= 16) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void ArmGicSetConfiguration(u32 index, int irq, u32 config) +{ + u32 icfgr; + u32 shift; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +u32 ArmGicGetConfiguration(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); +} + +void ArmGicClearActive(u32 index, int irq) +{ + u32 mask = 1U << (irq % 32U); + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void ArmGicSetCpu(u32 index, int irq, u32 cpumask) +{ + u32 old_tgt; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); + old_tgt |= cpumask << ((irq % 4U) * 8U); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +u32 ArmGicGetTargetCpu(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void ArmGicSetPriority(u32 index, int irq, u32 priority) +{ + u32 mask; + + FT_ASSERTVOID(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + if (irq < 32) + { + u32 cpu_id = GetCpuId(); + FT_ASSERTVOID((cpu_id) < RT_CPUS_NR); + + mask = GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) = mask; + } + else + { + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +u32 ArmGicGetPriority(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + if (irq < 32) + { + u32 cpu_id = GetCpuId(); + + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + return (GIC_RDISTSGI_IPRIORITYR(_gic_table[index].redist_hw_base[cpu_id], irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } + else + { + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + } +} + +void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + value &= 0xFFUL; + /* set priority mask */ + setICC_SRE_EL1(value); + // __SET_GICV3_REG(ICC_SRE, value); + __asm__ volatile("isb 0xF" :: + : "memory"); +} + +u32 ArmGicGetSystemRegisterEnableMask(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + u32 value; + + // __GET_GICV3_REG(ICC_SRE, value); + value = getICC_SRE_EL1(); + return value; +} + +void ArmGicSetInterfacePriorMask(u32 index, u32 priority) +{ + FT_ASSERTVOID(index < GIC_MAX_NR); + + priority &= 0xFFUL; + /* set priority mask */ + setPriorityMask(priority); + // __SET_GICV3_REG(ICC_PMR, priority); +} + +u32 ArmGicGetInterfacePriorMask(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + u32 priority; + priority = getPriorityMask(); + // __GET_GICV3_REG(ICC_PMR, priority); + return priority; +} + +void ArmGicSetBinaryPoint(u32 index, u32 binary_point) +{ + index = index; + binary_point &= 0x7U; + setBPR1(binary_point); + // __SET_GICV3_REG(ICC_BPR1, binary_point); +} + +u32 ArmGicGetBinaryPoint(u32 index) +{ + u32 binary_point; + + index = index; + // __GET_GICV3_REG(ICC_BPR1, binary_point); + binary_point = getBPR1(); + return binary_point; +} + +u32 ArmGicGetIrqStatus(u32 index, int irq) +{ + u32 pending; + u32 active; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode) +{ + // u64 sgi_val; + + if (routing_mode) + { + // sgi_val = (1ULL << 40) | ((irq & 0x0FULL) << 24); //Interrupts routed to all PEs in the system, excluding "self". + /* Write the ICC_SGI1R registers */ + __asm__ volatile("dsb 0xF" :: + : "memory"); + // __set_cp64(15, 0, sgi_val, 12); + + sendGroup1SGI((irq & 0x0FULL) << 24, 1ULL << 40, 0); + __asm__ volatile("isb 0xF" :: + : "memory"); + } + else + { + u32 cluster_id, target_list; + while (ArmGicCpuMaskToAffval(&cpu_mask, &cluster_id, &target_list)) + { + // sgi_val = ((irq & 0x0FULL) << 24 | + // target_list | + // ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | + // ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | + // ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); + + __asm__ volatile("dsb 0xF" :: + : "memory"); + sendGroup1SGI((irq & 0x0FULL) << 24, 0, target_list | ((cluster_id >> 8) & 0xFFULL) << GIC_RSGI_AFF1_OFFSET | ((cluster_id >> 16) & 0xFFULL) << GIC_RSGI_AFF2_OFFSET | ((cluster_id >> 24) & 0xFFull) << GIC_RSGI_AFF3_OFFSET); + // __set_cp64(15, 0, sgi_val, 12); + __asm__ volatile("isb 0xF" :: + : "memory"); + } + } +} + +u32 ArmGicGetHighPendingIrq(u32 index) +{ + u32 irq; + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + index = index; + irq = getHPPIR1(); + // __GET_GICV3_REG(ICC_HPPIR1, irq); + return irq; +} + +u32 ArmGicGetInterfaceId(u32 index) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void ArmGicSetGroup(u32 index, int irq, u32 group) +{ + u32 igroupr; + u32 shift; + + FT_ASSERTVOID(index < GIC_MAX_NR); + FT_ASSERTVOID(group <= 1U); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTVOID(irq >= 0); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ((group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +u32 ArmGicGetGroup(u32 index, int irq) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + irq = (irq - _gic_table[index].offset); + FT_ASSERTZERONUM(irq >= 0); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; +} + +static int ArmGicWaitRwp(u32 index, u32 irq) +{ + u32 rwp_bit; + u32 base; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + + if (irq < 32) + { + u32 cpu_id = GetCpuId(); + + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + base = _gic_table[index].redist_hw_base[cpu_id]; + rwp_bit = GICR_CTLR_RWP; + } + else + { + base = _gic_table[index].dist_hw_base; + rwp_bit = GICD_CTLR_RWP; + } + + while (__REG32(base) & rwp_bit) + { + ; + } + + return 0; +} + +int ArmGicDistInit(u32 index, u32 dist_base, int irq_start) +{ + u64 cpu0_affval; + u32 gic_type, i; + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020U) + _gic_max_irq = 1020U; + if (_gic_max_irq > GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = GIC_NR_IRQS; + + GIC_DIST_CTRL(dist_base) = 0x0U; + /* Wait for register write pending */ + ArmGicWaitRwp(0, 32); + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32U; i < _gic_max_irq; i += 16U) + GIC_DIST_CONFIG(dist_base, i) = 0x0U; + + ArmGicWaitRwp(0, 32); + + cpu0_affval = GetMainCpuAffval(); + /* Set all global interrupts to this CPU only. */ + for (i = 32U; i < _gic_max_irq; i++) + { + GIC_DIST_IROUTER_LOW(dist_base, i) = cpu0_affval; + GIC_DIST_IROUTER_HIGH(dist_base, i) = cpu0_affval >> 32; + } + + ArmGicWaitRwp(0, 32); + + /* Set priority on spi interrupts. */ + for (i = 32U; i < _gic_max_irq; i += 4U) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; + + ArmGicWaitRwp(0, 32); + /* Disable all interrupts. */ + for (i = 0U; i < _gic_max_irq; i += 32U) + { + GIC_DIST_PENDING_CLEAR(dist_base, i) = 0xffffffffU; + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; + } + + ArmGicWaitRwp(0, 32); + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; + + ArmGicWaitRwp(0, 32); + + /* + The Distributor control register (GICD_CTLR) must be configured to enable the interrupt groups and to set the routing mode. + Enable Affinity routing (ARE bits) The ARE bits in GICD_CTLR control whether affinity routing is enabled. + If affinity routing is not enabled, GICv3 can be configured for legacy operation. + Whether affinity routing is enabled or not can be controlled separately for Secure and Non-secure state. + Enables GICD_CTLR contains separate enable bits for Group 0, Secure Group 1 and Non-secure Group 1: + GICD_CTLR.EnableGrp1S enables distribution of Secure Group 1 interrupts. + GICD_CTLR.EnableGrp1NS enables distribution of Non-secure Group 1 interrupts. + GICD_CTLR.EnableGrp0 enables distribution of Group 0 interrupts. + */ + GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; + + enableGroup1Ints(); + return 0; +} + +int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + _gic_table[index].redist_hw_base[cpu_id] = redist_addr; + + return 0; +} + +int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id) +{ + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + _gic_table[index].cpu_hw_base[cpu_id] = interface_addr; + + return 0; +} + +int ArmGicRedistInit(u32 index) +{ + u32 i; + u32 base; + u32 reg_value; + u32 cpu_id = GetCpuId(); + + FT_ASSERTZERONUM(index < GIC_MAX_NR); + FT_ASSERTZERONUM((cpu_id) < RT_CPUS_NR); + + base = _gic_table[index].redist_hw_base[cpu_id]; + // printf("redist base %x \r\n", base); + /* redistributor enable */ + reg_value = GIC_RDIST_WAKER(base); + reg_value &= ~(1U << 1); + GIC_RDIST_WAKER(base) = reg_value; + + do + { + reg_value = GIC_RDIST_WAKER(base); + } while ((reg_value & 0x4) != 0); + + /* Disable all sgi and ppi interrupt */ + GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; + ArmGicWaitRwp(0, 0); + + /* Clear all inetrrupt pending */ + GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; + + /* the corresponding interrupt is Group 1 or Non-secure Group 1. */ + GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; + GIC_RDISTSGI_IGRPMODR0(base, 0) = 0xFFFFFFFF; + + /* Configure default priorities for SGI 0:15 and PPI 16:31. */ + for (i = 0; i < 32; i += 4) + { + GIC_RDISTSGI_IPRIORITYR(base, i) = 0xa0a0a0a0U; + } + + /* Trigger level for PPI interrupts*/ + GIC_RDISTSGI_ICFGR1(base) = 0x0U; // PPI is level-sensitive. + return 0; +} + +int ArmGicCpuInit(u32 index) +{ + u32 value; + FT_ASSERTZERONUM(index < GIC_MAX_NR); + value = ArmGicGetSystemRegisterEnableMask(index); + value |= (1U << 0); + ArmGicSetSystemRegisterEnableMask(index, value); + setICC_CTLR_EL1(0); + // __SET_GICV3_REG(ICC_CTLR, 0); + ArmGicSetInterfacePriorMask(index, 0xFFU); + /* Enable group1 interrupt */ + enableGroup1Ints(); + // __SET_GICV3_REG(ICC_IGRPEN1, value); + ArmGicSetBinaryPoint(0, 0); + + /* ICC_BPR0_EL1 determines the preemption group for both + Group 0 and Group 1 interrupts. + */ + value = 0x1U; + setICC_CTLR_EL1(value); + + // __SET_GICV3_REG(ICC_CTLR, value); + + return 0; +} + +#ifdef FT_USING_SMP +void ArmGicSecondaryCpuInit(void) +{ + ArmGicRedistInit(0); + + ArmGicCpuInit(0); +} +#endif + +void ArmGicDumpType(u32 index) +{ + u32 gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + printf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\r\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); +} + +void ArmGicDump(u32 index) +{ + u32 i, k; + + k = ArmGicGetHighPendingIrq(0); + printf("--- high pending priority: %d(%08x)\r\n", k, k); + printf("--- hw mask ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + printf("\r\n--- hw pending ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + printf("\r\n--- hw active ---\r\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + printf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + printf("\r\n"); +} + +long gic_dump(void) +{ + ArmGicDumpType(0); + ArmGicDump(0); + + return 0; +} diff --git a/bsp/drivers/gic/gicv3_arrch64/gicv3.h b/bsp/drivers/gic/gicv3_arrch64/gicv3.h index 3548a3526..8e752bd26 100644 --- a/bsp/drivers/gic/gicv3_arrch64/gicv3.h +++ b/bsp/drivers/gic/gicv3_arrch64/gicv3.h @@ -1,175 +1,175 @@ -/* - * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - *   - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-05-27 14:12:56 - * @LastEditTime: 2021-05-27 14:12:56 - * @Description:  This files is for  - * - * @Modify History: - *  Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef _BSP_DRIVERS_GIC_GICV3_H -#define _BSP_DRIVERS_GIC_GICV3_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_io.h" - -#define __REG32(x) (*((volatile u32 *)((u64)x))) - -#define ROUTED_TO_ALL (1) -#define ROUTED_TO_SPEC (0) - -/** Macro to access the Distributor Control Register (GICD_CTLR) -*/ -#define GICD_CTLR_RWP (1 << 31) -#define GICD_CTLR_E1NWF (1 << 7) -#define GICD_CTLR_DS (1 << 6) -#define GICD_CTLR_ARE_NS (1 << 5) -#define GICD_CTLR_ARE_S (1 << 4) -#define GICD_CTLR_ENGRP1S (1 << 2) -#define GICD_CTLR_ENGRP1NS (1 << 1) -#define GICD_CTLR_ENGRP0 (1 << 0) - -/** Macro to access the Redistributor Control Register (GICR_CTLR) -*/ -#define GICR_CTLR_UWP (1 << 31) -#define GICR_CTLR_DPG1S (1 << 26) -#define GICR_CTLR_DPG1NS (1 << 25) -#define GICR_CTLR_DPG0 (1 << 24) -#define GICR_CTLR_RWP (1 << 3) -#define GICR_CTLR_IR (1 << 2) -#define GICR_CTLR_CES (1 << 1) -#define GICR_CTLR_EnableLPI (1 << 0) - -/** Macro to access the Generic Interrupt Controller Interface (GICC) -*/ -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) -#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) - -/** Macro to access the Generic Interrupt Controller Distributor (GICD) -*/ -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n) / 32U) * 4U) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n) / 32U) * 4U) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n) / 32U) * 4U) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n) / 32U) * 4U) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n) / 32U) * 4U) -#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n) / 32U) * 4U) -#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n) / 32U) * 4U) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n) / 4U) * 4U) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n) / 4U) * 4U) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) -#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) -#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) -#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) - -/* SGI base address is at 64K offset from Redistributor base address */ -#define GIC_RSGI_OFFSET 0x10000 - -/** Macro to access the Generic Interrupt Controller Redistributor (GICD) -*/ -#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) -#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) -#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) -#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) -#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) -#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) -#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) -#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) -#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) -#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) -#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) -#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) - -#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) -#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) -#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) -#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) -#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) -#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) -#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) -#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) -#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) -#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) -#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) -#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) - -#define GIC_RSGI_AFF1_OFFSET 16 -#define GIC_RSGI_AFF2_OFFSET 32 -#define GIC_RSGI_AFF3_OFFSET 48 - - u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list); - u64 GetMainCpuAffval(void); - int ArmGicGetActiveIrq(u32 index); - void ArmGicAck(u32 index, int irq); - void ArmGicMask(u32 index, int irq); - void ArmGicUmask(u32 index, int irq); - - u32 ArmGicGetPendingIrq(u32 index, int irq); - void ArmGicSetPendingIrq(u32 index, int irq); - void ArmGicClearPendingIrq(u32 index, int irq); - - void ArmGicSetConfiguration(u32 index, int irq, uint32_t config); - u32 ArmGicGetConfiguration(u32 index, int irq); - - void ArmGicClearActive(u32 index, int irq); - - void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask); - u32 ArmGicGetTargetCpu(u32 index, int irq); - - void ArmGicSetPriority(u32 index, int irq, u32 priority); - u32 ArmGicGetPriority(u32 index, int irq); - - void ArmGicSetInterfacePriorMask(u32 index, u32 priority); - u32 ArmGicGetInterfacePriorMask(u32 index); - - void ArmGicSetBinaryPoint(u32 index, u32 binary_point); - u32 ArmGicGetBinaryPoint(u32 index); - - u32 ArmGicGetIrqStatus(u32 index, int irq); - - void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode); - u32 ArmGicGetHighPendingIrq(u32 index); - - u32 ArmGicGetInterfaceId(u32 index); - - void ArmGicSetGroup(u32 index, int irq, u32 group); - u32 ArmGicGetGroup(u32 index, int irq); - - int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id); - int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id); - int ArmGicDistInit(u32 index, u32 dist_base, int irq_start); - int ArmGicCpuInit(u32 index); - int ArmGicRedistInit(u32 index); - - void ArmGicDumpType(u32 index); - void ArmGicDump(u32 index); - - void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value); - u32 ArmGicGetSystemRegisterEnableMask(u32 index); - void ArmGicSecondaryCpuInit(void); - -#ifdef __cplusplus -} -#endif - -#endif // ! +/* + * @ : Copyright (c) 2020 Phytium Information Technology, Inc.  + *   + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-05-27 14:12:56 + * @LastEditTime: 2021-05-27 14:12:56 + * @Description:  This files is for  + * + * @Modify History: + *  Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef _BSP_DRIVERS_GIC_GICV3_H +#define _BSP_DRIVERS_GIC_GICV3_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_io.h" + +#define __REG32(x) (*((volatile u32 *)((u64)x))) + +#define ROUTED_TO_ALL (1) +#define ROUTED_TO_SPEC (0) + +/** Macro to access the Distributor Control Register (GICD_CTLR) +*/ +#define GICD_CTLR_RWP (1 << 31) +#define GICD_CTLR_E1NWF (1 << 7) +#define GICD_CTLR_DS (1 << 6) +#define GICD_CTLR_ARE_NS (1 << 5) +#define GICD_CTLR_ARE_S (1 << 4) +#define GICD_CTLR_ENGRP1S (1 << 2) +#define GICD_CTLR_ENGRP1NS (1 << 1) +#define GICD_CTLR_ENGRP0 (1 << 0) + +/** Macro to access the Redistributor Control Register (GICR_CTLR) +*/ +#define GICR_CTLR_UWP (1 << 31) +#define GICR_CTLR_DPG1S (1 << 26) +#define GICR_CTLR_DPG1NS (1 << 25) +#define GICR_CTLR_DPG0 (1 << 24) +#define GICR_CTLR_RWP (1 << 3) +#define GICR_CTLR_IR (1 << 2) +#define GICR_CTLR_CES (1 << 1) +#define GICR_CTLR_EnableLPI (1 << 0) + +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) + +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n) / 32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n) / 32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n) / 32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n) / 32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n) / 4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n) / 4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) +#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) +#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4) + +/* SGI base address is at 64K offset from Redistributor base address */ +#define GIC_RSGI_OFFSET 0x10000 + +/** Macro to access the Generic Interrupt Controller Redistributor (GICD) +*/ +#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U) +#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U) +#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U) +#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U) +#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U) +#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U) +#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U) +#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U) +#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U) +#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U) + +#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U) +#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U) +#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) +#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U) +#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U) +#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U) +#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U) +#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U) +#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U) +#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U) +#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4) +#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U) + +#define GIC_RSGI_AFF1_OFFSET 16 +#define GIC_RSGI_AFF2_OFFSET 32 +#define GIC_RSGI_AFF3_OFFSET 48 + + u32 ArmGicCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list); + u64 GetMainCpuAffval(void); + int ArmGicGetActiveIrq(u32 index); + void ArmGicAck(u32 index, int irq); + void ArmGicMask(u32 index, int irq); + void ArmGicUmask(u32 index, int irq); + + u32 ArmGicGetPendingIrq(u32 index, int irq); + void ArmGicSetPendingIrq(u32 index, int irq); + void ArmGicClearPendingIrq(u32 index, int irq); + + void ArmGicSetConfiguration(u32 index, int irq, uint32_t config); + u32 ArmGicGetConfiguration(u32 index, int irq); + + void ArmGicClearActive(u32 index, int irq); + + void ArmGicSetCpu(u32 index, int irq, unsigned int cpumask); + u32 ArmGicGetTargetCpu(u32 index, int irq); + + void ArmGicSetPriority(u32 index, int irq, u32 priority); + u32 ArmGicGetPriority(u32 index, int irq); + + void ArmGicSetInterfacePriorMask(u32 index, u32 priority); + u32 ArmGicGetInterfacePriorMask(u32 index); + + void ArmGicSetBinaryPoint(u32 index, u32 binary_point); + u32 ArmGicGetBinaryPoint(u32 index); + + u32 ArmGicGetIrqStatus(u32 index, int irq); + + void ArmGicSendAffinitySgi(u32 index, int irq, u32 cpu_mask, u32 routing_mode); + u32 ArmGicGetHighPendingIrq(u32 index); + + u32 ArmGicGetInterfaceId(u32 index); + + void ArmGicSetGroup(u32 index, int irq, u32 group); + u32 ArmGicGetGroup(u32 index, int irq); + + int ArmGicRedistAddressSet(u32 index, u32 redist_addr, u32 cpu_id); + int ArmGicCpuInterfaceAddressSet(u32 index, u32 interface_addr, u32 cpu_id); + int ArmGicDistInit(u32 index, u32 dist_base, int irq_start); + int ArmGicCpuInit(u32 index); + int ArmGicRedistInit(u32 index); + + void ArmGicDumpType(u32 index); + void ArmGicDump(u32 index); + + void ArmGicSetSystemRegisterEnableMask(u32 index, u32 value); + u32 ArmGicGetSystemRegisterEnableMask(u32 index); + void ArmGicSecondaryCpuInit(void); + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/drivers/gic/gicv3_arrch64/gicv3_aliases.h b/bsp/drivers/gic/gicv3_arrch64/gicv3_aliases.h index 2f0348287..e63c700f9 100644 --- a/bsp/drivers/gic/gicv3_arrch64/gicv3_aliases.h +++ b/bsp/drivers/gic/gicv3_arrch64/gicv3_aliases.h @@ -1,102 +1,102 @@ -#ifndef BSP_DRIVER_GICV3_GICV3_ALIASES_H -#define BSP_DRIVER_GICV3_GICV3_ALIASES_H - - - -/* - * Mapping of MSR and MRS to physical and virtual CPU interface registers - * - * ARM Generic Interrupt Controller Architecture Specification - * GIC architecture version 3.0 and version 4.0 - * Table 8-5 - */ -#define ICC_AP0R0_EL1 S3_0_C12_C8_4 -#define ICC_AP0R1_EL1 S3_0_C12_C8_5 -#define ICC_AP0R2_EL1 S3_0_C12_C8_6 -#define ICC_AP0R3_EL1 S3_0_C12_C8_7 - -#define ICC_AP1R0_EL1 S3_0_C12_C9_0 -#define ICC_AP1R1_EL1 S3_0_C12_C9_1 -#define ICC_AP1R2_EL1 S3_0_C12_C9_2 -#define ICC_AP1R3_EL1 S3_0_C12_C9_3 - -#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 - -#define ICC_BPR0_EL1 S3_0_C12_C8_3 -#define ICC_BPR1_EL1 S3_0_C12_C12_3 - -#define ICC_CTLR_EL1 S3_0_C12_C12_4 -#define ICC_CTLR_EL3 S3_6_C12_C12_4 - -#define ICC_DIR_EL1 S3_0_C12_C11_1 - -#define ICC_EOIR0_EL1 S3_0_C12_C8_1 -#define ICC_EOIR1_EL1 S3_0_C12_C12_1 - -#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 -#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 - -#define ICC_IAR0_EL1 S3_0_C12_C8_0 -#define ICC_IAR1_EL1 S3_0_C12_C12_0 - -#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 -#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 -#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 - -#define ICC_PMR_EL1 S3_0_C4_C6_0 -#define ICC_RPR_EL1 S3_0_C12_C11_3 - -#define ICC_SGI0R_EL1 S3_0_C12_C11_7 -#define ICC_SGI1R_EL1 S3_0_C12_C11_5 - -#define ICC_SRE_EL1 S3_0_C12_C12_5 -#define ICC_SRE_EL2 S3_4_C12_C9_5 -#define ICC_SRE_EL3 S3_6_C12_C12_5 - -/* - * Mapping of MSR and MRS to virtual interface control registers - * - * ARM Generic Interrupt Controller Architecture Specification - * GIC architecture version 3.0 and version 4.0 - * Table 8-6 - */ -#define ICH_AP0R0_EL2 S3_4_C12_C8_0 -#define ICH_AP0R1_EL2 S3_4_C12_C8_1 -#define ICH_AP0R2_EL2 S3_4_C12_C8_2 -#define ICH_AP0R3_EL2 S3_4_C12_C8_3 - -#define ICH_AP1R0_EL2 S3_4_C12_C9_0 -#define ICH_AP1R1_EL2 S3_4_C12_C9_1 -#define ICH_AP1R2_EL2 S3_4_C12_C9_2 -#define ICH_AP1R3_EL2 S3_4_C12_C9_3 - -#define ICH_HCR_EL2 S3_4_C12_C11_0 - -#define ICH_VTR_EL2 S3_4_C12_C11_1 - -#define ICH_MISR_EL2 S3_4_C12_C11_2 - -#define ICH_EISR_EL2 S3_4_C12_C11_3 - -#define ICH_ELRSR_EL2 S3_4_C12_C11_5 - -#define ICH_VMCR_EL2 S3_4_C12_C11_7 - -#define ICH_LR0_EL2 S3_4_C12_C12_0 -#define ICH_LR1_EL2 S3_4_C12_C12_1 -#define ICH_LR2_EL2 S3_4_C12_C12_2 -#define ICH_LR3_EL2 S3_4_C12_C12_3 -#define ICH_LR4_EL2 S3_4_C12_C12_4 -#define ICH_LR5_EL2 S3_4_C12_C12_5 -#define ICH_LR6_EL2 S3_4_C12_C12_6 -#define ICH_LR7_EL2 S3_4_C12_C12_7 -#define ICH_LR8_EL2 S3_4_C12_C13_0 -#define ICH_LR9_EL2 S3_4_C12_C13_1 -#define ICH_LR10_EL2 S3_4_C12_C13_2 -#define ICH_LR11_EL2 S3_4_C12_C13_3 -#define ICH_LR12_EL2 S3_4_C12_C13_4 -#define ICH_LR13_EL2 S3_4_C12_C13_5 -#define ICH_LR14_EL2 S3_4_C12_C13_6 -#define ICH_LR15_EL2 S3_4_C12_C13_7 - -#endif /* GICV3_ALIASES */ +#ifndef BSP_DRIVER_GICV3_GICV3_ALIASES_H +#define BSP_DRIVER_GICV3_GICV3_ALIASES_H + + + +/* + * Mapping of MSR and MRS to physical and virtual CPU interface registers + * + * ARM Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-5 + */ +#define ICC_AP0R0_EL1 S3_0_C12_C8_4 +#define ICC_AP0R1_EL1 S3_0_C12_C8_5 +#define ICC_AP0R2_EL1 S3_0_C12_C8_6 +#define ICC_AP0R3_EL1 S3_0_C12_C8_7 + +#define ICC_AP1R0_EL1 S3_0_C12_C9_0 +#define ICC_AP1R1_EL1 S3_0_C12_C9_1 +#define ICC_AP1R2_EL1 S3_0_C12_C9_2 +#define ICC_AP1R3_EL1 S3_0_C12_C9_3 + +#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 + +#define ICC_BPR0_EL1 S3_0_C12_C8_3 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 + +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 + +#define ICC_DIR_EL1 S3_0_C12_C11_1 + +#define ICC_EOIR0_EL1 S3_0_C12_C8_1 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 + +#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 +#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 + +#define ICC_IAR0_EL1 S3_0_C12_C8_0 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 + +#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 + +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_RPR_EL1 S3_0_C12_C11_3 + +#define ICC_SGI0R_EL1 S3_0_C12_C11_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 + +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 + +/* + * Mapping of MSR and MRS to virtual interface control registers + * + * ARM Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-6 + */ +#define ICH_AP0R0_EL2 S3_4_C12_C8_0 +#define ICH_AP0R1_EL2 S3_4_C12_C8_1 +#define ICH_AP0R2_EL2 S3_4_C12_C8_2 +#define ICH_AP0R3_EL2 S3_4_C12_C8_3 + +#define ICH_AP1R0_EL2 S3_4_C12_C9_0 +#define ICH_AP1R1_EL2 S3_4_C12_C9_1 +#define ICH_AP1R2_EL2 S3_4_C12_C9_2 +#define ICH_AP1R3_EL2 S3_4_C12_C9_3 + +#define ICH_HCR_EL2 S3_4_C12_C11_0 + +#define ICH_VTR_EL2 S3_4_C12_C11_1 + +#define ICH_MISR_EL2 S3_4_C12_C11_2 + +#define ICH_EISR_EL2 S3_4_C12_C11_3 + +#define ICH_ELRSR_EL2 S3_4_C12_C11_5 + +#define ICH_VMCR_EL2 S3_4_C12_C11_7 + +#define ICH_LR0_EL2 S3_4_C12_C12_0 +#define ICH_LR1_EL2 S3_4_C12_C12_1 +#define ICH_LR2_EL2 S3_4_C12_C12_2 +#define ICH_LR3_EL2 S3_4_C12_C12_3 +#define ICH_LR4_EL2 S3_4_C12_C12_4 +#define ICH_LR5_EL2 S3_4_C12_C12_5 +#define ICH_LR6_EL2 S3_4_C12_C12_6 +#define ICH_LR7_EL2 S3_4_C12_C12_7 +#define ICH_LR8_EL2 S3_4_C12_C13_0 +#define ICH_LR9_EL2 S3_4_C12_C13_1 +#define ICH_LR10_EL2 S3_4_C12_C13_2 +#define ICH_LR11_EL2 S3_4_C12_C13_3 +#define ICH_LR12_EL2 S3_4_C12_C13_4 +#define ICH_LR13_EL2 S3_4_C12_C13_5 +#define ICH_LR14_EL2 S3_4_C12_C13_6 +#define ICH_LR15_EL2 S3_4_C12_C13_7 + +#endif /* GICV3_ALIASES */ diff --git a/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.S b/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.S index 42b04c6b8..ad16e1619 100644 --- a/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.S +++ b/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.S @@ -1,410 +1,410 @@ -// ------------------------------------------------------------ -// ARMv8-A AArch64 - GICv3 CPU interface functions -// -// Copyright (C) Arm Limited, 2019 All rights reserved. -// -// The example code is provided to you as an aid to learning when working -// with Arm-based technology, including but not limited to programming tutorials. -// Arm hereby grants to you, subject to the terms and conditions of this Licence, -// a non-exclusive, non-transferable, non-sub-licensable, free-of-charge licence, -// to use and copy the Software solely for the purpose of demonstration and -// evaluation. -// -// You accept that the Software has not been tested by Arm therefore the Software -// is provided 閿熺禈s is閿燂拷, without warranty of any kind, express or implied. In no -// event shall the authors or copyright holders be liable for any claim, damages -// or other liability, whether in action or contract, tort or otherwise, arising -// from, out of or in connection with the Software or the use of Software. -// -// ------------------------------------------------------------ - -#include "gicv3_aliases.h" - - .section v8_aarch64_gicv3_cpuif,"ax" - -// ------------------------------------------------------------ - - .global setICC_SRE_EL1 - // void setICC_SRE_EL1(u32 value) - .type setICC_SRE_EL1, @function -setICC_SRE_EL1: - MSR ICC_SRE_EL1, x0 - ISB - RET - -// ------------------------------------------------------------ - - .global getICC_SRE_EL1 - // u32 getICC_SRE_EL1(void) - .type getICC_SRE_EL1, @function -getICC_SRE_EL1: - MRS x0, ICC_SRE_EL1 - RET - - - -// ------------------------------------------------------------ - - .global setICC_SRE_EL2 - // void setICC_SRE_EL2(u32 value) - .type setICC_SRE_EL2, @function -setICC_SRE_EL2: - MSR ICC_SRE_EL2, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global getICC_SRE_EL2 - // u32 getICC_SRE_EL2(void) - .type getICC_SRE_EL2, @function -getICC_SRE_EL2: - MRS x0, ICC_SRE_EL2 - RET - - - -// ------------------------------------------------------------ - - .global setICC_SRE_EL3 - // void setICC_SRE_EL3(u32 value) - .type setICC_SRE_EL3, @function -setICC_SRE_EL3: - MSR ICC_SRE_EL3, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global getICC_SRE_EL3 - // u32 getICC_SRE_EL3(void) - .type getICC_SRE_EL3, @function -getICC_SRE_EL3: - MRS x0, ICC_SRE_EL3 - RET - - - -// ------------------------------------------------------------ - - .global enableGroup0Ints - // void enableGroup0Ints(void) - .type enableGroup0Ints, @function -enableGroup0Ints: - MOV w0, #1 - MSR ICC_IGRPEN0_EL1, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global disableGroup0Ints - // void disableGroup0Ints(void) - .type disableGroup0Ints, @function -disableGroup0Ints: - - MOV w0, #0 - MSR ICC_IGRPEN0_EL1, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global enableGroup1Ints - // void enableGroup1Ints((void)// - .type enableGroup1Ints, @function -enableGroup1Ints: - MRS x0, ICC_IGRPEN1_EL1 - ORR w0, w0, #1 - MSR ICC_IGRPEN1_EL1, x0 - ISB - RET - - -// ------------------------------------------------------------ - - .global disableGroup1Ints - // void disableGroup1Ints(void)// - .type disableGroup1Ints, @function -disableGroup1Ints: - MOV w1, #1 - MRS x0, ICC_IGRPEN1_EL1 - BIC x0, x0, x1 - MSR ICC_IGRPEN1_EL1, x0 - ISB - RET - - -// ------------------------------------------------------------ - - .global enableNSGroup1Ints - // void enableNSGroup1Ints(void) - .type enableNSGroup1Ints, @function -enableNSGroup1Ints: - MRS x0, ICC_IGRPEN1_EL3 - ORR w0, w0, #1 - MSR ICC_IGRPEN1_EL3, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global disableNSGroup1Ints - // void disableNSGroup1Ints(void) - .type disableNSGroup1Ints, @function -disableNSGroup1Ints: - MOV w1, #0x1 - MRS x0, ICC_IGRPEN1_EL3 - BIC x0, x0, x1 - MSR ICC_IGRPEN1_EL3, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global getICC_CTLR_EL3 - // u32 getICC_CTLR_EL3(void)// - .type getICC_CTLR_EL3, @function -getICC_CTLR_EL3: - MRS x0, ICC_CTLR_EL3 - RET - - -// ------------------------------------------------------------ - .global setICC_CTLR_EL3 - // void setICC_CTLR_EL3(u32 value) - .type setICC_CTLR_EL3, @function -setICC_CTLR_EL3: - MSR ICC_CTLR_EL3, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global getICC_CTLR_EL1 - // u32 getICC_CTLR_EL1(void)// - .type getICC_CTLR_EL1, @function -getICC_CTLR_EL1: - MRS x0, ICC_CTLR_EL1 - RET - - -// ------------------------------------------------------------ - - .global setICC_CTLR_EL1 - // void setICC_CTLR_EL1(u32 value) - .type setICC_CTLR_EL1, @function -setICC_CTLR_EL1: - MSR ICC_CTLR_EL1, x0 - ISB - RET - - - -// ------------------------------------------------------------ - - .global readIARGrp0 - // u32 readIARGrp0(void)// - .type readIARGrp0, @function -readIARGrp0: - MRS x0, ICC_IAR0_EL1 - RET - - -// ------------------------------------------------------------ - - .global writeEOIGrp0 - // void writeEOIGrp0(u32 ID)// - .type writeEOIGrp0, @function -writeEOIGrp0: - MSR ICC_EOIR0_EL1, x0 - ISB - RET - - -// ------------------------------------------------------------ - - .global writeDIR - // void writeDIR(u32 ID)// - .type writeDIR, @function -writeDIR: - MSR ICC_DIR_EL1, x0 - ISB - RET - - -// ------------------------------------------------------------ - - .global readIARGrp1 - // u32 readIARGrp1(void)// - .type readIARGrp1, @function -readIARGrp1: - MRS x0, ICC_IAR1_EL1 - RET - - -// ------------------------------------------------------------ - - .global writeEOIGrp1 - // void writeEOIGrp1(u32 ID)// - .type writeEOIGrp1, @function -writeEOIGrp1: - MSR ICC_EOIR1_EL1, x0 - DSB SY - RET - - -// ------------------------------------------------------------ - - .global setPriorityMask - // void setPriorityMask(u32 ID)// - .type setPriorityMask, @function -setPriorityMask: - MSR ICC_PMR_EL1, x0 - RET - -// ------------------------------------------------------------ - - .global getPriorityMask - // u32 getPriorityMask(void)// - .type getPriorityMask, @function -getPriorityMask: - MRS x0,ICC_PMR_EL1 - RET - - -// ------------------------------------------------------------ - - .global getBPR0 - // u32 getBPR0(void)// - .type getBPR0, @function -getBPR0: - MRS x0, ICC_BPR0_EL1 - RET - - -// ------------------------------------------------------------ - - .global setBPR0 - // void setBPR0(u32 INTID)// - .type setBPR0, @function -setBPR0: - MSR ICC_BPR0_EL1, x0 - ISB - RET - - -// ------------------------------------------------------------ - - .global getBPR1 - // u32 getBPR1(void)// - .type getBPR1, @function -getBPR1: - MRS x0, ICC_BPR1_EL1 - RET - - -// ------------------------------------------------------------ - - .global setBPR1 - // void setBPR1(u32 ID)// - .type setBPR1, @function -setBPR1: - MSR ICC_BPR1_EL1, x0 - ISB - RET - - - - -// ------------------------------------------------------------ - - .global getHPPIR1 - // u32 getHPPIR1(void)// - .type getHPPIR1, @function -getHPPIR1: - MRS x0, ICC_HPPIR1_EL1 - RET - - -// ------------------------------------------------------------ - - .global setHPPIR1 - // void setHPPIR1(u32 ID)// - .type setHPPIR1, @function -setHPPIR1: - MSR ICC_HPPIR1_EL1, x0 - ISB - RET - -// ------------------------------------------------------------ - - .global getRunningPriority - // u32 getRunningPriority(void)// - .type getRunningPriority, @function -getRunningPriority: - MRS x0, ICC_RPR_EL1 - RET - - -// ------------------------------------------------------------ -// SGIs -// ------------------------------------------------------------ - - .global sendGroup0SGI - // void sendGroup0SGI(u32 ID, u32 mode, unsigned target_list)// - .type sendGroup0SGI, @function -sendGroup0SGI: - ORR x0, x0, x1 - ORR x0, x0, x2 - MSR ICC_SGI0R_EL1, x0 - RET - - -// ------------------------------------------------------------ - - .global sendGroup1SGI - // void sendGroup1SGI(u64 ID, u64 mode, u64 target_list)// - .type sendGroup1SGI, @function -sendGroup1SGI: - ORR x0, x0, x1 - ORR x0, x0, x2 - MSR ICC_SGI1R_EL1, x0 - RET - - -// ------------------------------------------------------------ - - .global sendOtherGroup1SGI - // void sendOtherGroup1SGI(u32 ID, u32 mode, unsigned target_list)// - .type sendOtherGroup1SGI, @function -sendOtherGroup1SGI: - ORR x0, x0, x1 - ORR x0, x0, x2 - MSR ICC_ASGI1R_EL1, x0 - RET - - - -// ------------------------------------------------------------ -// End of code -// ------------------------------------------------------------ - - -// ------------------------------------------------------------ -// End of v8_aarch64_gicv3_cpuif.s -// ------------------------------------------------------------ +// ------------------------------------------------------------ +// ARMv8-A AArch64 - GICv3 CPU interface functions +// +// Copyright (C) Arm Limited, 2019 All rights reserved. +// +// The example code is provided to you as an aid to learning when working +// with Arm-based technology, including but not limited to programming tutorials. +// Arm hereby grants to you, subject to the terms and conditions of this Licence, +// a non-exclusive, non-transferable, non-sub-licensable, free-of-charge licence, +// to use and copy the Software solely for the purpose of demonstration and +// evaluation. +// +// You accept that the Software has not been tested by Arm therefore the Software +// is provided 閿熺禈s is閿燂拷, without warranty of any kind, express or implied. In no +// event shall the authors or copyright holders be liable for any claim, damages +// or other liability, whether in action or contract, tort or otherwise, arising +// from, out of or in connection with the Software or the use of Software. +// +// ------------------------------------------------------------ + +#include "gicv3_aliases.h" + + .section v8_aarch64_gicv3_cpuif,"ax" + +// ------------------------------------------------------------ + + .global setICC_SRE_EL1 + // void setICC_SRE_EL1(u32 value) + .type setICC_SRE_EL1, @function +setICC_SRE_EL1: + MSR ICC_SRE_EL1, x0 + ISB + RET + +// ------------------------------------------------------------ + + .global getICC_SRE_EL1 + // u32 getICC_SRE_EL1(void) + .type getICC_SRE_EL1, @function +getICC_SRE_EL1: + MRS x0, ICC_SRE_EL1 + RET + + + +// ------------------------------------------------------------ + + .global setICC_SRE_EL2 + // void setICC_SRE_EL2(u32 value) + .type setICC_SRE_EL2, @function +setICC_SRE_EL2: + MSR ICC_SRE_EL2, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global getICC_SRE_EL2 + // u32 getICC_SRE_EL2(void) + .type getICC_SRE_EL2, @function +getICC_SRE_EL2: + MRS x0, ICC_SRE_EL2 + RET + + + +// ------------------------------------------------------------ + + .global setICC_SRE_EL3 + // void setICC_SRE_EL3(u32 value) + .type setICC_SRE_EL3, @function +setICC_SRE_EL3: + MSR ICC_SRE_EL3, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global getICC_SRE_EL3 + // u32 getICC_SRE_EL3(void) + .type getICC_SRE_EL3, @function +getICC_SRE_EL3: + MRS x0, ICC_SRE_EL3 + RET + + + +// ------------------------------------------------------------ + + .global enableGroup0Ints + // void enableGroup0Ints(void) + .type enableGroup0Ints, @function +enableGroup0Ints: + MOV w0, #1 + MSR ICC_IGRPEN0_EL1, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global disableGroup0Ints + // void disableGroup0Ints(void) + .type disableGroup0Ints, @function +disableGroup0Ints: + + MOV w0, #0 + MSR ICC_IGRPEN0_EL1, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global enableGroup1Ints + // void enableGroup1Ints((void)// + .type enableGroup1Ints, @function +enableGroup1Ints: + MRS x0, ICC_IGRPEN1_EL1 + ORR w0, w0, #1 + MSR ICC_IGRPEN1_EL1, x0 + ISB + RET + + +// ------------------------------------------------------------ + + .global disableGroup1Ints + // void disableGroup1Ints(void)// + .type disableGroup1Ints, @function +disableGroup1Ints: + MOV w1, #1 + MRS x0, ICC_IGRPEN1_EL1 + BIC x0, x0, x1 + MSR ICC_IGRPEN1_EL1, x0 + ISB + RET + + +// ------------------------------------------------------------ + + .global enableNSGroup1Ints + // void enableNSGroup1Ints(void) + .type enableNSGroup1Ints, @function +enableNSGroup1Ints: + MRS x0, ICC_IGRPEN1_EL3 + ORR w0, w0, #1 + MSR ICC_IGRPEN1_EL3, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global disableNSGroup1Ints + // void disableNSGroup1Ints(void) + .type disableNSGroup1Ints, @function +disableNSGroup1Ints: + MOV w1, #0x1 + MRS x0, ICC_IGRPEN1_EL3 + BIC x0, x0, x1 + MSR ICC_IGRPEN1_EL3, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global getICC_CTLR_EL3 + // u32 getICC_CTLR_EL3(void)// + .type getICC_CTLR_EL3, @function +getICC_CTLR_EL3: + MRS x0, ICC_CTLR_EL3 + RET + + +// ------------------------------------------------------------ + .global setICC_CTLR_EL3 + // void setICC_CTLR_EL3(u32 value) + .type setICC_CTLR_EL3, @function +setICC_CTLR_EL3: + MSR ICC_CTLR_EL3, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global getICC_CTLR_EL1 + // u32 getICC_CTLR_EL1(void)// + .type getICC_CTLR_EL1, @function +getICC_CTLR_EL1: + MRS x0, ICC_CTLR_EL1 + RET + + +// ------------------------------------------------------------ + + .global setICC_CTLR_EL1 + // void setICC_CTLR_EL1(u32 value) + .type setICC_CTLR_EL1, @function +setICC_CTLR_EL1: + MSR ICC_CTLR_EL1, x0 + ISB + RET + + + +// ------------------------------------------------------------ + + .global readIARGrp0 + // u32 readIARGrp0(void)// + .type readIARGrp0, @function +readIARGrp0: + MRS x0, ICC_IAR0_EL1 + RET + + +// ------------------------------------------------------------ + + .global writeEOIGrp0 + // void writeEOIGrp0(u32 ID)// + .type writeEOIGrp0, @function +writeEOIGrp0: + MSR ICC_EOIR0_EL1, x0 + ISB + RET + + +// ------------------------------------------------------------ + + .global writeDIR + // void writeDIR(u32 ID)// + .type writeDIR, @function +writeDIR: + MSR ICC_DIR_EL1, x0 + ISB + RET + + +// ------------------------------------------------------------ + + .global readIARGrp1 + // u32 readIARGrp1(void)// + .type readIARGrp1, @function +readIARGrp1: + MRS x0, ICC_IAR1_EL1 + RET + + +// ------------------------------------------------------------ + + .global writeEOIGrp1 + // void writeEOIGrp1(u32 ID)// + .type writeEOIGrp1, @function +writeEOIGrp1: + MSR ICC_EOIR1_EL1, x0 + DSB SY + RET + + +// ------------------------------------------------------------ + + .global setPriorityMask + // void setPriorityMask(u32 ID)// + .type setPriorityMask, @function +setPriorityMask: + MSR ICC_PMR_EL1, x0 + RET + +// ------------------------------------------------------------ + + .global getPriorityMask + // u32 getPriorityMask(void)// + .type getPriorityMask, @function +getPriorityMask: + MRS x0,ICC_PMR_EL1 + RET + + +// ------------------------------------------------------------ + + .global getBPR0 + // u32 getBPR0(void)// + .type getBPR0, @function +getBPR0: + MRS x0, ICC_BPR0_EL1 + RET + + +// ------------------------------------------------------------ + + .global setBPR0 + // void setBPR0(u32 INTID)// + .type setBPR0, @function +setBPR0: + MSR ICC_BPR0_EL1, x0 + ISB + RET + + +// ------------------------------------------------------------ + + .global getBPR1 + // u32 getBPR1(void)// + .type getBPR1, @function +getBPR1: + MRS x0, ICC_BPR1_EL1 + RET + + +// ------------------------------------------------------------ + + .global setBPR1 + // void setBPR1(u32 ID)// + .type setBPR1, @function +setBPR1: + MSR ICC_BPR1_EL1, x0 + ISB + RET + + + + +// ------------------------------------------------------------ + + .global getHPPIR1 + // u32 getHPPIR1(void)// + .type getHPPIR1, @function +getHPPIR1: + MRS x0, ICC_HPPIR1_EL1 + RET + + +// ------------------------------------------------------------ + + .global setHPPIR1 + // void setHPPIR1(u32 ID)// + .type setHPPIR1, @function +setHPPIR1: + MSR ICC_HPPIR1_EL1, x0 + ISB + RET + +// ------------------------------------------------------------ + + .global getRunningPriority + // u32 getRunningPriority(void)// + .type getRunningPriority, @function +getRunningPriority: + MRS x0, ICC_RPR_EL1 + RET + + +// ------------------------------------------------------------ +// SGIs +// ------------------------------------------------------------ + + .global sendGroup0SGI + // void sendGroup0SGI(u32 ID, u32 mode, unsigned target_list)// + .type sendGroup0SGI, @function +sendGroup0SGI: + ORR x0, x0, x1 + ORR x0, x0, x2 + MSR ICC_SGI0R_EL1, x0 + RET + + +// ------------------------------------------------------------ + + .global sendGroup1SGI + // void sendGroup1SGI(u64 ID, u64 mode, u64 target_list)// + .type sendGroup1SGI, @function +sendGroup1SGI: + ORR x0, x0, x1 + ORR x0, x0, x2 + MSR ICC_SGI1R_EL1, x0 + RET + + +// ------------------------------------------------------------ + + .global sendOtherGroup1SGI + // void sendOtherGroup1SGI(u32 ID, u32 mode, unsigned target_list)// + .type sendOtherGroup1SGI, @function +sendOtherGroup1SGI: + ORR x0, x0, x1 + ORR x0, x0, x2 + MSR ICC_ASGI1R_EL1, x0 + RET + + + +// ------------------------------------------------------------ +// End of code +// ------------------------------------------------------------ + + +// ------------------------------------------------------------ +// End of v8_aarch64_gicv3_cpuif.s +// ------------------------------------------------------------ diff --git a/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.h b/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.h index f09475e87..baeacbf94 100644 --- a/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.h +++ b/bsp/drivers/gic/gicv3_arrch64/gicv3_cpuif.h @@ -1,88 +1,88 @@ -#ifndef BSP_DRIVER_GICV3_GICV3_CPUIF_H -#define BSP_DRIVER_GICV3_GICV3_CPUIF_H - -// ------------------------------------------------------------ -// CPU Interface functions -// ------------------------------------------------------------ - -// Enables group 0 interrupts -// The lowest EL that access the ICC_IGRPEN0_EL1 is determined -// by the routine of the FIQ exception. -void enableGroup0Ints(void); - -// Disables group 0 interrupts -// The lowest EL that access the ICC_IGRPEN0_EL1 is determined -// by the routine of the FIQ exception. -void disableGroup0Ints(void); - -// Enables group 1 interrupts for current security state -// The lowest EL that access the ICC_IGRPEN1_EL1 is determined -// by the routine of the IRQ exception. -void enableGroup1Ints(void); - -// Disables group 1 interrupts for current security state -// The lowest EL that access the ICC_IGRPEN1_EL1 is determined -// by the routine of the IRQ exception. -void disableGroup1Ints(void); - -// Enables group 1 interrupts for non-secure state -// -// Used by EL3 to enable non-secure group 1 interrupts -void enableNSGroup1Ints(void); - -// Disables group 1 interrupts for non-secure state -// -// Used by EL3 to disable non-secure group 1 interrupts -void disableNSGroup1Ints(void); - -// Returns the value of the ICC_IAR0_EL1 (Group 0 Interrupt Acknowledge) -u32 readIARGrp0(void); - -// Writes INTID to the End Of Interrupt register -void writeEOIGrp0(u32 INTID); - -// Writes INTID to the De-active Interrupt register -void writeDIR(u32 INTID); - -// Returns the value of the ICC_IAR1_EL1 (Group 1 Interrupt Acknowledge) -u32 readIARGrp1(void); - -// Writes INTID to the Aliased End Of Interrupt register -void writeEOIGrp1(u32 INTID); - -// Sets the Priority mask register for the core run on -// priority - mask value (8-bit unsigned value). -// -// NOTE: An interrupt must be high priority (lower numeric value) than the mask to be sent -void setPriorityMask(u32 priority); - -u32 getPriorityMask(void); - -// Sets ICC_BPR0_EL1 for the core run on -// priority - Binary piont value -void setBPR0(u32 priority); - -// Sets ICC_BPR1_EL1 for the core run on -// priority - Binary piont value -void setBPR1(u32 priority); - -u32 getBPR1(void); - -// Returns the priority of the current active interrupt -u32 getRunningPriority(void); - -void setICC_SRE_EL1(u32 value); - -u32 getICC_SRE_EL1(void); - -u32 getHPPIR1(void); - -void setHPPIR1(u32 ID); - -u32 getICC_CTLR_EL1(void); - -void setICC_CTLR_EL1(u32 value); - -void sendGroup1SGI(u64 ID, u64 mode, u64 target_list); - -#endif +#ifndef BSP_DRIVER_GICV3_GICV3_CPUIF_H +#define BSP_DRIVER_GICV3_GICV3_CPUIF_H + +// ------------------------------------------------------------ +// CPU Interface functions +// ------------------------------------------------------------ + +// Enables group 0 interrupts +// The lowest EL that access the ICC_IGRPEN0_EL1 is determined +// by the routine of the FIQ exception. +void enableGroup0Ints(void); + +// Disables group 0 interrupts +// The lowest EL that access the ICC_IGRPEN0_EL1 is determined +// by the routine of the FIQ exception. +void disableGroup0Ints(void); + +// Enables group 1 interrupts for current security state +// The lowest EL that access the ICC_IGRPEN1_EL1 is determined +// by the routine of the IRQ exception. +void enableGroup1Ints(void); + +// Disables group 1 interrupts for current security state +// The lowest EL that access the ICC_IGRPEN1_EL1 is determined +// by the routine of the IRQ exception. +void disableGroup1Ints(void); + +// Enables group 1 interrupts for non-secure state +// +// Used by EL3 to enable non-secure group 1 interrupts +void enableNSGroup1Ints(void); + +// Disables group 1 interrupts for non-secure state +// +// Used by EL3 to disable non-secure group 1 interrupts +void disableNSGroup1Ints(void); + +// Returns the value of the ICC_IAR0_EL1 (Group 0 Interrupt Acknowledge) +u32 readIARGrp0(void); + +// Writes INTID to the End Of Interrupt register +void writeEOIGrp0(u32 INTID); + +// Writes INTID to the De-active Interrupt register +void writeDIR(u32 INTID); + +// Returns the value of the ICC_IAR1_EL1 (Group 1 Interrupt Acknowledge) +u32 readIARGrp1(void); + +// Writes INTID to the Aliased End Of Interrupt register +void writeEOIGrp1(u32 INTID); + +// Sets the Priority mask register for the core run on +// priority - mask value (8-bit unsigned value). +// +// NOTE: An interrupt must be high priority (lower numeric value) than the mask to be sent +void setPriorityMask(u32 priority); + +u32 getPriorityMask(void); + +// Sets ICC_BPR0_EL1 for the core run on +// priority - Binary piont value +void setBPR0(u32 priority); + +// Sets ICC_BPR1_EL1 for the core run on +// priority - Binary piont value +void setBPR1(u32 priority); + +u32 getBPR1(void); + +// Returns the priority of the current active interrupt +u32 getRunningPriority(void); + +void setICC_SRE_EL1(u32 value); + +u32 getICC_SRE_EL1(void); + +u32 getHPPIR1(void); + +void setHPPIR1(u32 ID); + +u32 getICC_CTLR_EL1(void); + +void setICC_CTLR_EL1(u32 value); + +void sendGroup1SGI(u64 ID, u64 mode, u64 target_list); + +#endif diff --git a/bsp/drivers/gpio/Kconfig b/bsp/drivers/gpio/Kconfig new file mode 100644 index 000000000..430da3f87 --- /dev/null +++ b/bsp/drivers/gpio/Kconfig @@ -0,0 +1,8 @@ + +menu "Gpio Configuration" + config ENABLE_F_GPIO_UART + bool + prompt "Use F_GPIO uart" + default n + +endmenu \ No newline at end of file diff --git a/bsp/drivers/gpio/f_gpio/f_gpio.c b/bsp/drivers/gpio/f_gpio/f_gpio.c new file mode 100644 index 000000000..cb68a1a7b --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio.c @@ -0,0 +1,137 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-12 18:43:00 + * @LastEditTime: 2021-07-13 10:02:44 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include "f_gpio.h" +#include "f_gpio_hw.h" + +void FGpioSetDirection(FGpio *instance_p, u32 pin, fsize_t direction) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_PIN_MAX_NUM); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + if (pin < F_GPIO_B_PIN0) + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTA_DDR_OFFSET); + } + else + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTB_DDR_OFFSET); + } + + switch (direction) + { + case F_GPIO_DIRECTION_INPUT: + val &= ~(1 << (pin % 8)); + break; + case F_GPIO_DIRECTION_OUTPUT: + val |= (1 << (pin % 8)); + break; + default: + return; + } + + if (pin < 8) + { + F_GPIO_WRITEREG32(config_p->base_address, GPIO_SWPORTA_DDR_OFFSET, val); + } + else + { + F_GPIO_WRITEREG32(config_p->base_address, GPIO_SWPORTB_DDR_OFFSET, val); + } +} + +fsize_t FGpioGetDirection(FGpio *instance_p, u32 pin) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_PIN_MAX_NUM); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + if (pin < F_GPIO_B_PIN0) + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTA_DDR_OFFSET); + } + else + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTB_DDR_OFFSET); + } + + return (val & (1 << (pin % 8))) ? F_GPIO_DIRECTION_OUTPUT : F_GPIO_DIRECTION_INPUT; +} + +void FGpioSetValue(FGpio *instance_p, u32 pin, FGpioOutLevel Level) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_PIN_MAX_NUM); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + if (pin < F_GPIO_B_PIN0) + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTA_DR_OFFSET); + } + else + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTB_DR_OFFSET); + } + + switch (Level) + { + case F_GPIO_OUTPUT_LOW: + val &= ~(1 << (pin % 8)); + break; + case F_GPIO_OUTPUT_HIGH: + val |= (1 << (pin % 8)); + break; + default: + return; + } + + if (pin < F_GPIO_B_PIN0) + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTA_DR_OFFSET); + } + else + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_SWPORTB_DR_OFFSET); + } +} + +fsize_t FGpioGetValue(FGpio *instance_p, u32 pin) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_PIN_MAX_NUM); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + if (pin < F_GPIO_B_PIN0) + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_EXT_PORTA_OFFSET); + } + else + { + val = F_GPIO_READREG32(config_p->base_address, GPIO_EXT_PORTB_OFFSET); + } + + return (val >> (pin % 8)) & 0x01; +} \ No newline at end of file diff --git a/bsp/drivers/gpio/f_gpio/f_gpio.h b/bsp/drivers/gpio/f_gpio/f_gpio.h new file mode 100644 index 000000000..aca24e94d --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio.h @@ -0,0 +1,91 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-12 18:43:06 + * @LastEditTime: 2021-07-13 13:52:01 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_DRIVER_GPIO_F_GPIO_H +#define BSP_DRIVER_GPIO_F_GPIO_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "parameters.h" +#include "ft_assert.h" + + // #define ERR_INPUT_BAUD_NO_SUPPORT FT_CODE_ERR(ErrModBsp, ErrBspGpio, 0x1u) + +#define F_GPIO_DIRECTION_INPUT 0 +#define F_GPIO_DIRECTION_OUTPUT 1 + +#define F_GPIO_A_PIN0 0 +#define F_GPIO_A_PIN1 1 +#define F_GPIO_A_PIN2 2 +#define F_GPIO_A_PIN3 3 +#define F_GPIO_A_PIN4 4 +#define F_GPIO_A_PIN5 5 +#define F_GPIO_A_PIN6 6 +#define F_GPIO_A_PIN7 7 +#define F_GPIO_B_PIN0 8 +#define F_GPIO_B_PIN1 9 +#define F_GPIO_B_PIN2 10 +#define F_GPIO_B_PIN3 11 +#define F_GPIO_B_PIN4 12 +#define F_GPIO_B_PIN5 13 +#define F_GPIO_B_PIN6 14 +#define F_GPIO_B_PIN7 15 + + typedef enum + { + F_GPIO_OUTPUT_LOW = 0, + F_GPIO_OUTPUT_HIGH = 1, + } FGpioOutLevel; + + typedef enum + { + F_GPIO_IRQ_TYPE_EDGE_FALLING = 0, + F_GPIO_IRQ_TYPE_EDGE_RISING, + F_GPIO_IRQ_TYPE_LEVEL_LOW, + F_GPIO_IRQ_TYPE_LEVEL_HIGH + } FGpioIrqType; + + typedef struct + { + u32 instance_id; /* Id of device*/ + uintptr_t base_address; + u32 irq_num; + u8 gpio_group[F_GPIO_GROUP_NUM]; + } FGpioConfig; + + typedef struct + { + u32 is_ready; /* Device is ininitialized and ready*/ + FGpioConfig config; + } FGpio; + + void FGpioPinIrqMask(FGpio *instance_p, u32 pin); + void FGpioPinIrqUnmask(FGpio *instance_p, u32 pin); + void FGpioPinIrqSetType(FGpio *instance_p, u32 pin, FGpioIrqType type); + void FGpioPinIrqAck(FGpio *instance_p, u32 pin); + u32 FGpioPinIrqStatusGet(FGpio *instance_p); + + void FGpioSetDirection(FGpio *instance_p, u32 pin, fsize_t direction); + fsize_t FGpioGetDirection(FGpio *instance_p, u32 pin); + void FGpioSetValue(FGpio *instance_p, u32 pin, FGpioOutLevel Level); + fsize_t FGpioGetValue(FGpio *instance_p, u32 pin); + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/drivers/gpio/f_gpio/f_gpio_g.c b/bsp/drivers/gpio/f_gpio/f_gpio_g.c new file mode 100644 index 000000000..bb6868c55 --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio_g.c @@ -0,0 +1,31 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-13 08:25:16 + * @LastEditTime: 2021-07-13 08:44:47 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include "f_gpio.h" +#include "parameters.h" + +FGpioConfig f_gpio_config[F_GPIO_GROUP_NUM] = + { + { + .instance_id = 0, + .base_address = GPIO0_BASE, + .irq_num = F_GPIO0_INTR_IRQ, + .gpio_group = {0}, + }, + { + .instance_id = 1, + .base_address = GPIO1_BASE, + .irq_num = F_GPIO1_INTR_IRQ, + .gpio_group = {0}, + }, +}; diff --git a/bsp/drivers/gpio/f_gpio/f_gpio_hw.h b/bsp/drivers/gpio/f_gpio/f_gpio_hw.h new file mode 100644 index 000000000..e9dc12a73 --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio_hw.h @@ -0,0 +1,52 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-12 17:20:40 + * @LastEditTime: 2021-07-13 10:31:15 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_DRIVER_GPIO_F_GPIO_HW_H +#define BSP_DRIVER_GPIO_F_GPIO_HW_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "parameters.h" +#include "ft_io.h" + +#define GPIO_SWPORTA_DR_OFFSET 0x00 /* WR Port A Output Data Register */ +#define GPIO_SWPORTA_DDR_OFFSET 0x04 /* WR Port A Data Direction Register */ +#define GPIO_EXT_PORTA_OFFSET 0x08 /* RO Port A Input Data Register */ +#define GPIO_SWPORTB_DR_OFFSET 0x0c /* WR Port B Output Data Register */ +#define GPIO_SWPORTB_DDR_OFFSET 0x10 /* WR Port B Data Direction Register */ +#define GPIO_EXT_PORTB_OFFSET 0x14 /* RO Port B Input Data Register */ + +#define GPIO_INTEN_OFFSET 0x18 /* WR Port A Interrput Enable Register */ +#define GPIO_INTMASK_OFFSET 0x1c /* WR Port A Interrupt Mask Register */ +#define GPIO_INTTYPE_LEVEL_OFFSET 0x20 /* WR Port A Interrupt Level Register */ +#define GPIO_INT_POLARITY_OFFSET 0x24 /* WR Port A Interrupt Polarity Register */ +#define GPIO_INTSTATUS_OFFSET 0x28 /* RO Port A Interrupt Status Register */ +#define GPIO_RAW_INTSTATUS_OFFSET 0x2c /* RO Port A Raw Interrupt Status Register */ +#define GPIO_LS_SYNC_OFFSET 0x30 /* WR Level-sensitive Synchronization Enable Register */ +#define GPIO_DEBOUNCE_OFFSET 0x34 /* WR Debounce Enable Register */ +#define GPIO_PORTA_EOI_OFFSET 0x38 /* WO Port A Clear Interrupt Register */ + + /***************** Macros (Inline Functions) Definitions *********************/ + +#define F_GPIO_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset) + +#define F_GPIO_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value) + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/drivers/gpio/f_gpio/f_gpio_intr.c b/bsp/drivers/gpio/f_gpio/f_gpio_intr.c new file mode 100644 index 000000000..8fa608dbd --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio_intr.c @@ -0,0 +1,103 @@ + +#include "f_gpio.h" +#include "f_gpio_hw.h" + +void FGpioPinIrqMask(FGpio *instance_p, u32 pin) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_B_PIN0); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + /* set irq mask */ + val = F_GPIO_READREG32(config_p->base_address, GPIO_INTMASK_OFFSET); + val |= (1 << pin); + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INTMASK_OFFSET, val); + + /* disable pin irq */ + val = F_GPIO_READREG32(config_p->base_address, GPIO_INTEN_OFFSET); + val &= ~(1 << pin); + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INTEN_OFFSET, val); +} + +void FGpioPinIrqUnmask(FGpio *instance_p, u32 pin) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_B_PIN0); + u32 val; + FGpioConfig *config_p; + config_p = &instance_p->config; + + /* clear irq mask */ + val = F_GPIO_READREG32(config_p->base_address, GPIO_INTMASK_OFFSET); + val &= ~(1 << pin); + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INTMASK_OFFSET, val); + + /* enable pin irq */ + val = F_GPIO_READREG32(config_p->base_address, GPIO_INTEN_OFFSET); + val |= (1 << pin); + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INTEN_OFFSET, val); +} + +void FGpioPinIrqSetType(FGpio *instance_p, u32 pin, FGpioIrqType type) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_B_PIN0); + u32 level, polarity; + FGpioConfig *config_p; + config_p = &instance_p->config; + + // read trriger and polarity + level = F_GPIO_READREG32(config_p->base_address, GPIO_INTTYPE_LEVEL_OFFSET); + polarity = F_GPIO_READREG32(config_p->base_address, GPIO_INT_POLARITY_OFFSET); + + switch (type) + { + case F_GPIO_IRQ_TYPE_EDGE_FALLING: + level |= (1 << pin); + polarity &= ~(1 << pin); + break; + case F_GPIO_IRQ_TYPE_EDGE_RISING: + level |= (1 << pin); + polarity |= (1 << pin); + break; + case F_GPIO_IRQ_TYPE_LEVEL_LOW: + level &= ~(1 << pin); + polarity &= ~(1 << pin); + break; + case F_GPIO_IRQ_TYPE_LEVEL_HIGH: + level &= ~(1 << pin); + polarity |= (1 << pin); + break; + default: + return; + } + + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INTTYPE_LEVEL_OFFSET, level); + F_GPIO_WRITEREG32(config_p->base_address, GPIO_INT_POLARITY_OFFSET, polarity); +} + +void FGpioPinIrqAck(FGpio *instance_p, u32 pin) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FT_ASSERTVOID(pin < F_GPIO_B_PIN0); + FGpioConfig *config_p; + config_p = &instance_p->config; + + F_GPIO_WRITEREG32(config_p->base_address, GPIO_PORTA_EOI_OFFSET, (1 << pin)); +} + +u32 FGpioPinIrqStatusGet(FGpio *instance_p) +{ + FT_ASSERTVOID(instance_p != NULL); + FT_ASSERTVOID(instance_p->is_ready == FT_COMPONENT_IS_READLY); + FGpioConfig *config_p; + config_p = &instance_p->config; + + return F_GPIO_READREG32(config_p->base_address, GPIO_INTSTATUS_OFFSET); +} \ No newline at end of file diff --git a/bsp/drivers/gpio/f_gpio/f_gpio_sinit.c b/bsp/drivers/gpio/f_gpio/f_gpio_sinit.c new file mode 100644 index 000000000..ecd68b07a --- /dev/null +++ b/bsp/drivers/gpio/f_gpio/f_gpio_sinit.c @@ -0,0 +1,40 @@ +/* + * @[H]: Copyright (c) 2021 Phytium Information Technology, Inc. + * + *  SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-07-12 22:36:34 + * @LastEditTime: 2021-07-13 08:48:06 + * @Description:  Description of file + * @Modify History: + * * * Ver   Who        Date         Changes + * * ----- ------     --------    -------------------------------------- + */ + +#include "f_gpio.h" +#include "parameters.h" + +extern FGpioConfig f_gpio_config[F_GPIO_GROUP_NUM]; + +/** + * @name: Ft_Uart_LookupConfig + * @msg: 获取串口的基本配置 + * @param {u16} instance_id FT_UARTX_ID + * @return {*} + */ +FGpioConfig *FGpioLookupConfig(u32 instance_id) +{ + FGpioConfig *ptr = NULL; + u32 index; + + for (index = 0; index < (u32)F_GPIO_GROUP_NUM; index++) + { + if (f_gpio_config[index].instance_id == instance_id) + { + ptr = &f_gpio_config[index]; + break; + } + } + + return (FGpioConfig *)ptr; +} diff --git a/bsp/drivers/qspi/Kconfig b/bsp/drivers/qspi/Kconfig index 868a0af4e..b402f5edb 100644 --- a/bsp/drivers/qspi/Kconfig +++ b/bsp/drivers/qspi/Kconfig @@ -1,15 +1,15 @@ -menu "QSPI Configuration" -depends on USE_QSPI - -choice QSPI_WORK_MODE - prompt "QSPI Work Mode Selection" - default QSPI_POLLING_MODE - help - Select QSPI Work Mode as Polling or Intrrupt - - config QSPI_POLLING_MODE - bool "Polling" - config QSPI_IRQ_MODE - bool "Interrupt" -endchoice #QSPI_WORK_MODE +menu "QSPI Configuration" +depends on USE_QSPI + +choice QSPI_WORK_MODE + prompt "QSPI Work Mode Selection" + default QSPI_POLLING_MODE + help + Select QSPI Work Mode as Polling or Intrrupt + + config QSPI_POLLING_MODE + bool "Polling" + config QSPI_IRQ_MODE + bool "Interrupt" +endchoice #QSPI_WORK_MODE endmenu \ No newline at end of file diff --git a/bsp/drivers/spi/Kconfig b/bsp/drivers/spi/Kconfig index 6629eb363..7cd760586 100644 --- a/bsp/drivers/spi/Kconfig +++ b/bsp/drivers/spi/Kconfig @@ -1,17 +1,17 @@ -menu "SPI Configuration" -depends on USE_SPI - - -choice SPI_WORK_MODE - prompt "SPI Work Mode Selection" - default SPI_POLLING_MODE - help - Select SPI Work Mode as Polling or Interrupt - - config SPI_POLLING_MODE - bool "Polling" - config SPI_IRQ_MODE - bool "Interrupt" - -endchoice #SPI_WORK_MODE +menu "SPI Configuration" +depends on USE_SPI + + +choice SPI_WORK_MODE + prompt "SPI Work Mode Selection" + default SPI_POLLING_MODE + help + Select SPI Work Mode as Polling or Interrupt + + config SPI_POLLING_MODE + bool "Polling" + config SPI_IRQ_MODE + bool "Interrupt" + +endchoice #SPI_WORK_MODE endmenu \ No newline at end of file diff --git a/bsp/drivers/usart/Kconfig b/bsp/drivers/usart/Kconfig index f6ec3ad6c..db84bf442 100644 --- a/bsp/drivers/usart/Kconfig +++ b/bsp/drivers/usart/Kconfig @@ -1,8 +1,8 @@ - -menu "Usart Configuration" - config ENABLE_Pl011_UART - bool - prompt "Use Pl011 uart" - default n - + +menu "Usart Configuration" + config ENABLE_Pl011_UART + bool + prompt "Use Pl011 uart" + default n + endmenu \ No newline at end of file diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart.c b/bsp/drivers/usart/pl011_uart/pl011_uart.c index fbc8849c5..75fed2019 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart.c @@ -1,345 +1,345 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-06-30 19:16:24 - * @Description:  This files is for uart functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -/***************************** Include Files ********************************/ - -#include "pl011_uart.h" -#include "ft_io.h" -#include "ft_error_code.h" - -u32 Pl011SendBuffer(Pl011 *uart_p); -u32 Pl011ReceiveBuffer(Pl011 *uart_p); - -static void Pl011StubHandler(void *Args, u32 Event, - u32 ByteCount); - -/** - * @name: Pl011CfgInitialize - * @msg: initalize uart configure - * @return {*} - * @param {Ft_Uart} *uart_p - * @param {Pl011Config} *Config - */ -s32 Pl011CfgInitialize(Pl011 *uart_p, Pl011Config *Config) -{ - u32 RegValue = 0; - - FT_ASSERTNONVOID(uart_p != NULL); - FT_ASSERTNONVOID(Config != NULL); - - uart_p->config.instance_id = Config->instance_id; - uart_p->config.base_address = Config->base_address; - uart_p->config.ref_clock_hz = Config->ref_clock_hz; - uart_p->config.irq_num = Config->irq_num; - - uart_p->handler = Pl011StubHandler; - - uart_p->send_buffer.byte_p = NULL; - uart_p->send_buffer.requested_bytes = 0; - uart_p->send_buffer.remaining_bytes = 0; - - uart_p->receive_buffer.byte_p = NULL; - uart_p->receive_buffer.requested_bytes = 0; - uart_p->receive_buffer.remaining_bytes = 0; - uart_p->rxbs_error = 0; - uart_p->is_ready = FT_COMPONENT_IS_READLY; - //config.base_address, UARTLCR_H_OFFSET, RegValue); - - /* Set the RX FIFO trigger at 8 data bytes.Tx FIFO trigger is 8 data bytes*/ - RegValue = (1 << 3) | (1 << 0); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIFLS_OFFSET, RegValue); - - /* Disable all interrupts, polled mode is the default */ - RegValue = 0; - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); - - return FT_SUCCESS; -} - -/** - * @name: Pl011Send - * @msg: - * @param {Ft_Uart} *uart_p - * @param {u8} *Buffer - * @param {u32} Length - * @return {u32} The Number of bytes actully sent. - */ -u32 Pl011Send(Pl011 *uart_p, u8 *byte_p, u32 Length) -{ - u32 RegValue = 0; - u32 SentCount = 0; - FT_ASSERTNONVOID(uart_p != NULL); - FT_ASSERTNONVOID(byte_p != NULL); - FT_ASSERTNONVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - /* - * Disable the UART transmit interrupts to allow this call to stop a - * previous operation that may be interrupt driven. - */ - RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); - RegValue &= ~(UARTIMSC_TXIM); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); - - uart_p->send_buffer.byte_p = byte_p; - uart_p->send_buffer.requested_bytes = Length; - uart_p->send_buffer.remaining_bytes = Length; - - SentCount = Pl011SendBuffer(uart_p); - - return SentCount; -} - -/** - * @name: Pl011PutChar - * @msg: send a char through uart - * @return {*} - * @param {Ft_Uart} *uart_p - * @param {s8} Data - */ -void Pl011PutChar(Pl011 *uart_p, s8 Data) -{ - FT_ASSERTVOID(uart_p != NULL); - FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - while (!FT_UART_ISTRANSMITFULL(uart_p->config.base_address)) - { - FT_UART_WRITEREG32(uart_p->config.base_address, UARTDR_OFFSET, Data); - break; - } -} - -static void Pl011StubHandler(void *Args, u32 Event, - u32 ByteCount) -{ - (void)Args; - (void)Event; - (void)ByteCount; - - FT_ASSERTVOIDALWAYS(); -} - -/** - * @name: Pl011SendBuffer - * @msg: send data buffer through uart - * @return {*} - * @param {Ft_Uart} *uart_p - */ -u32 Pl011SendBuffer(Pl011 *uart_p) -{ - u32 SentCount = 0U; - u32 RegValue; - - /* - * If the TX FIFO is full, send nothing. - * Otherwise put bytes into the TX FIFO unil it is full, or all of the - * data has been put into the FIFO. - */ - while ((!FT_UART_ISTRANSMITFULL(uart_p->config.base_address)) && (uart_p->send_buffer.remaining_bytes > SentCount)) - { - FT_UART_WRITEREG32(uart_p->config.base_address, UARTDR_OFFSET, (u32)uart_p->send_buffer.byte_p[SentCount]); - SentCount++; - } - - /* Update the buffer to reflect the bytes that were sent from it */ - uart_p->send_buffer.byte_p += SentCount; - uart_p->send_buffer.remaining_bytes -= SentCount; - - RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); - RegValue |= (UARTIMSC_TXIM); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); - - return SentCount; -} - -/** - * @name: Pl011Receive - * @msg: receive data through uart - * @return {*} - * @param {Ft_Uart} *uart_p - * @param {u8} *byte_p - * @param {u32} Length - */ -u32 Pl011Receive(Pl011 *uart_p, u8 *byte_p, u32 Length) -{ - u32 Received; - u32 BackRegValue; - - FT_ASSERTNONVOID(uart_p != NULL); - FT_ASSERTNONVOID(byte_p != NULL); - FT_ASSERTNONVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - /* - * Disable all the interrupts. - * This stops a previous operation that may be interrupt driven - */ - BackRegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, 0); - - uart_p->receive_buffer.byte_p = byte_p; - uart_p->receive_buffer.requested_bytes = Length; - uart_p->receive_buffer.remaining_bytes = Length; - - Received = Pl011ReceiveBuffer(uart_p); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, BackRegValue); - - return Received; -} - -/** - * @name: Ft_Uart_ReceiveBuffer - * @msg: handling uart receive buffer - * @return {*} - * @param {Ft_Uart} *uart_p - */ -u32 Pl011ReceiveBuffer(Pl011 *uart_p) -{ - - u32 ReceivedCount = 0U; - u32 Event; - u32 EventData; - u32 ByteValue; - - while ((ReceivedCount < uart_p->receive_buffer.remaining_bytes) && !FT_UART_ISRECEIVEDATA(uart_p->config.base_address)) - { - ByteValue = FT_UART_READREG32(uart_p->config.base_address, UARTDR_OFFSET); - - if (uart_p->rxbs_error) - { - if ((ByteValue & UARTDR_ALLE) != 0) - { - EventData = ByteValue; - Event = FUART_EVENT_PARE_FRAME_BRKE; - - if (uart_p->handler) - { - uart_p->handler(uart_p->args, Event, EventData); - } - } - } - uart_p->receive_buffer.byte_p[ReceivedCount] = (u8)(ByteValue & 0xff); - ReceivedCount++; - } - - uart_p->rxbs_error = 0; - - if (uart_p->receive_buffer.byte_p != NULL) - { - uart_p->receive_buffer.byte_p += ReceivedCount; - } - uart_p->receive_buffer.remaining_bytes -= ReceivedCount; - - return ReceivedCount; -} - -/** - * @name: Pl011BlockSend - * @msg: initiate uart block send - * @return {*} - * @param {Ft_Uart} *uart_p - * @param {u8} *byte_p - * @param {u32} Length - */ -void Pl011BlockSend(Pl011 *uart_p, u8 *byte_p, u32 Length) -{ - u32 index; - - FT_ASSERTVOID(uart_p != NULL); - FT_ASSERTVOID(byte_p != NULL); - FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - for (index = 0; index < Length; index++) - { - Pl011SendByte(uart_p->config.base_address, byte_p[index]); - } -} - -/** - * @name: Pl011BlockReceive - * @msg: initiate uart block receive - * @return {*} - * @param {Ft_Uart} *uart_p - */ -u8 Pl011BlockReceive(Pl011 *uart_p) -{ - FT_ASSERTBYTE(uart_p != NULL); - FT_ASSERTBYTE(uart_p->is_ready == FT_COMPONENT_IS_READLY); - return Pl011RecvByte(uart_p->config.base_address); -} - -/** - * @name: Pl011SetBaudRate - * @msg: set baudrate of UART trans - * @return {*} - * @param {Ft_Uart} *uart_p - * @param {u32} BaudRate - */ -u32 Pl011SetBaudRate(Pl011 *uart_p, u32 baudrate) -{ - u32 temp; - u32 divider; - u32 remainder; - u32 fraction; - - FT_ASSERTNONVOID(NULL != uart_p); - if ((baudrate * 2) > uart_p->config.ref_clock_hz) - { - return ERR_INPUT_BAUD_NO_SUPPORT; - } - - /* calculate baud rate divisor */ - temp = 16 * baudrate; - divider = uart_p->config.ref_clock_hz / temp; - remainder = uart_p->config.ref_clock_hz % temp; - temp = (128 * remainder) / temp; - fraction = temp / 2; - - if (0 != (temp & 1)) - { - fraction++; - } - - Pl011ClearSpecificOptions(uart_p, FUART_OPTION_RXEN | FUART_OPTION_TXEN); - /* set baud register */ - FT_UART_WRITEREG32(uart_p->config.base_address, UARTIBRD_OFFSET, divider); - FT_UART_WRITEREG32(uart_p->config.base_address, UARTFBRD_OFFSET, fraction); - Pl011SetSpecificOptions(uart_p, FUART_OPTION_RXEN | FUART_OPTION_TXEN); - - return ERR_SUCCESS; -} - -void Pl011IrqClearReciveTimeOut(Pl011 *uart_p) -{ - u32 reg_temp; - reg_temp = Pl011GetInterruptMask(uart_p); - reg_temp &= ~UARTMIS_RTMIS; - Pl011SetInterruptMask(uart_p, reg_temp); -} - -void Pl011IrqEnableReciveTimeOut(Pl011 *uart_p) -{ - u32 reg_temp; - reg_temp = Pl011GetInterruptMask(uart_p); - reg_temp |= UARTMIS_RTMIS; - Pl011SetInterruptMask(uart_p, reg_temp); -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-06-30 19:16:24 + * @Description:  This files is for uart functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +/***************************** Include Files ********************************/ + +#include "pl011_uart.h" +#include "ft_io.h" +#include "ft_error_code.h" + +u32 Pl011SendBuffer(Pl011 *uart_p); +u32 Pl011ReceiveBuffer(Pl011 *uart_p); + +static void Pl011StubHandler(void *Args, u32 Event, + u32 ByteCount); + +/** + * @name: Pl011CfgInitialize + * @msg: initalize uart configure + * @return {*} + * @param {Ft_Uart} *uart_p + * @param {Pl011Config} *Config + */ +s32 Pl011CfgInitialize(Pl011 *uart_p, Pl011Config *Config) +{ + u32 RegValue = 0; + + FT_ASSERTNONVOID(uart_p != NULL); + FT_ASSERTNONVOID(Config != NULL); + + uart_p->config.instance_id = Config->instance_id; + uart_p->config.base_address = Config->base_address; + uart_p->config.ref_clock_hz = Config->ref_clock_hz; + uart_p->config.irq_num = Config->irq_num; + + uart_p->handler = Pl011StubHandler; + + uart_p->send_buffer.byte_p = NULL; + uart_p->send_buffer.requested_bytes = 0; + uart_p->send_buffer.remaining_bytes = 0; + + uart_p->receive_buffer.byte_p = NULL; + uart_p->receive_buffer.requested_bytes = 0; + uart_p->receive_buffer.remaining_bytes = 0; + uart_p->rxbs_error = 0; + uart_p->is_ready = FT_COMPONENT_IS_READLY; + //config.base_address, UARTLCR_H_OFFSET, RegValue); + + /* Set the RX FIFO trigger at 8 data bytes.Tx FIFO trigger is 8 data bytes*/ + RegValue = (1 << 3) | (1 << 0); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIFLS_OFFSET, RegValue); + + /* Disable all interrupts, polled mode is the default */ + RegValue = 0; + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); + + return FT_SUCCESS; +} + +/** + * @name: Pl011Send + * @msg: + * @param {Ft_Uart} *uart_p + * @param {u8} *Buffer + * @param {u32} Length + * @return {u32} The Number of bytes actully sent. + */ +u32 Pl011Send(Pl011 *uart_p, u8 *byte_p, u32 Length) +{ + u32 RegValue = 0; + u32 SentCount = 0; + FT_ASSERTNONVOID(uart_p != NULL); + FT_ASSERTNONVOID(byte_p != NULL); + FT_ASSERTNONVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + /* + * Disable the UART transmit interrupts to allow this call to stop a + * previous operation that may be interrupt driven. + */ + RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); + RegValue &= ~(UARTIMSC_TXIM); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); + + uart_p->send_buffer.byte_p = byte_p; + uart_p->send_buffer.requested_bytes = Length; + uart_p->send_buffer.remaining_bytes = Length; + + SentCount = Pl011SendBuffer(uart_p); + + return SentCount; +} + +/** + * @name: Pl011PutChar + * @msg: send a char through uart + * @return {*} + * @param {Ft_Uart} *uart_p + * @param {s8} Data + */ +void Pl011PutChar(Pl011 *uart_p, s8 Data) +{ + FT_ASSERTVOID(uart_p != NULL); + FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + while (!FT_UART_ISTRANSMITFULL(uart_p->config.base_address)) + { + FT_UART_WRITEREG32(uart_p->config.base_address, UARTDR_OFFSET, Data); + break; + } +} + +static void Pl011StubHandler(void *Args, u32 Event, + u32 ByteCount) +{ + (void)Args; + (void)Event; + (void)ByteCount; + + FT_ASSERTVOIDALWAYS(); +} + +/** + * @name: Pl011SendBuffer + * @msg: send data buffer through uart + * @return {*} + * @param {Ft_Uart} *uart_p + */ +u32 Pl011SendBuffer(Pl011 *uart_p) +{ + u32 SentCount = 0U; + u32 RegValue; + + /* + * If the TX FIFO is full, send nothing. + * Otherwise put bytes into the TX FIFO unil it is full, or all of the + * data has been put into the FIFO. + */ + while ((!FT_UART_ISTRANSMITFULL(uart_p->config.base_address)) && (uart_p->send_buffer.remaining_bytes > SentCount)) + { + FT_UART_WRITEREG32(uart_p->config.base_address, UARTDR_OFFSET, (u32)uart_p->send_buffer.byte_p[SentCount]); + SentCount++; + } + + /* Update the buffer to reflect the bytes that were sent from it */ + uart_p->send_buffer.byte_p += SentCount; + uart_p->send_buffer.remaining_bytes -= SentCount; + + RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); + RegValue |= (UARTIMSC_TXIM); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, RegValue); + + return SentCount; +} + +/** + * @name: Pl011Receive + * @msg: receive data through uart + * @return {*} + * @param {Ft_Uart} *uart_p + * @param {u8} *byte_p + * @param {u32} Length + */ +u32 Pl011Receive(Pl011 *uart_p, u8 *byte_p, u32 Length) +{ + u32 Received; + u32 BackRegValue; + + FT_ASSERTNONVOID(uart_p != NULL); + FT_ASSERTNONVOID(byte_p != NULL); + FT_ASSERTNONVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + /* + * Disable all the interrupts. + * This stops a previous operation that may be interrupt driven + */ + BackRegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, 0); + + uart_p->receive_buffer.byte_p = byte_p; + uart_p->receive_buffer.requested_bytes = Length; + uart_p->receive_buffer.remaining_bytes = Length; + + Received = Pl011ReceiveBuffer(uart_p); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIMSC_OFFSET, BackRegValue); + + return Received; +} + +/** + * @name: Ft_Uart_ReceiveBuffer + * @msg: handling uart receive buffer + * @return {*} + * @param {Ft_Uart} *uart_p + */ +u32 Pl011ReceiveBuffer(Pl011 *uart_p) +{ + + u32 ReceivedCount = 0U; + u32 Event; + u32 EventData; + u32 ByteValue; + + while ((ReceivedCount < uart_p->receive_buffer.remaining_bytes) && !FT_UART_ISRECEIVEDATA(uart_p->config.base_address)) + { + ByteValue = FT_UART_READREG32(uart_p->config.base_address, UARTDR_OFFSET); + + if (uart_p->rxbs_error) + { + if ((ByteValue & UARTDR_ALLE) != 0) + { + EventData = ByteValue; + Event = FUART_EVENT_PARE_FRAME_BRKE; + + if (uart_p->handler) + { + uart_p->handler(uart_p->args, Event, EventData); + } + } + } + uart_p->receive_buffer.byte_p[ReceivedCount] = (u8)(ByteValue & 0xff); + ReceivedCount++; + } + + uart_p->rxbs_error = 0; + + if (uart_p->receive_buffer.byte_p != NULL) + { + uart_p->receive_buffer.byte_p += ReceivedCount; + } + uart_p->receive_buffer.remaining_bytes -= ReceivedCount; + + return ReceivedCount; +} + +/** + * @name: Pl011BlockSend + * @msg: initiate uart block send + * @return {*} + * @param {Ft_Uart} *uart_p + * @param {u8} *byte_p + * @param {u32} Length + */ +void Pl011BlockSend(Pl011 *uart_p, u8 *byte_p, u32 Length) +{ + u32 index; + + FT_ASSERTVOID(uart_p != NULL); + FT_ASSERTVOID(byte_p != NULL); + FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + for (index = 0; index < Length; index++) + { + Pl011SendByte(uart_p->config.base_address, byte_p[index]); + } +} + +/** + * @name: Pl011BlockReceive + * @msg: initiate uart block receive + * @return {*} + * @param {Ft_Uart} *uart_p + */ +u8 Pl011BlockReceive(Pl011 *uart_p) +{ + FT_ASSERTBYTE(uart_p != NULL); + FT_ASSERTBYTE(uart_p->is_ready == FT_COMPONENT_IS_READLY); + return Pl011RecvByte(uart_p->config.base_address); +} + +/** + * @name: Pl011SetBaudRate + * @msg: set baudrate of UART trans + * @return {*} + * @param {Ft_Uart} *uart_p + * @param {u32} BaudRate + */ +u32 Pl011SetBaudRate(Pl011 *uart_p, u32 baudrate) +{ + u32 temp; + u32 divider; + u32 remainder; + u32 fraction; + + FT_ASSERTNONVOID(NULL != uart_p); + if ((baudrate * 2) > uart_p->config.ref_clock_hz) + { + return ERR_INPUT_BAUD_NO_SUPPORT; + } + + /* calculate baud rate divisor */ + temp = 16 * baudrate; + divider = uart_p->config.ref_clock_hz / temp; + remainder = uart_p->config.ref_clock_hz % temp; + temp = (128 * remainder) / temp; + fraction = temp / 2; + + if (0 != (temp & 1)) + { + fraction++; + } + + Pl011ClearSpecificOptions(uart_p, FUART_OPTION_RXEN | FUART_OPTION_TXEN); + /* set baud register */ + FT_UART_WRITEREG32(uart_p->config.base_address, UARTIBRD_OFFSET, divider); + FT_UART_WRITEREG32(uart_p->config.base_address, UARTFBRD_OFFSET, fraction); + Pl011SetSpecificOptions(uart_p, FUART_OPTION_RXEN | FUART_OPTION_TXEN); + + return ERR_SUCCESS; +} + +void Pl011IrqClearReciveTimeOut(Pl011 *uart_p) +{ + u32 reg_temp; + reg_temp = Pl011GetInterruptMask(uart_p); + reg_temp &= ~UARTMIS_RTMIS; + Pl011SetInterruptMask(uart_p, reg_temp); +} + +void Pl011IrqEnableReciveTimeOut(Pl011 *uart_p) +{ + u32 reg_temp; + reg_temp = Pl011GetInterruptMask(uart_p); + reg_temp |= UARTMIS_RTMIS; + Pl011SetInterruptMask(uart_p, reg_temp); +} diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart.h b/bsp/drivers/usart/pl011_uart/pl011_uart.h index a9f6a091f..5d2e640a5 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart.h +++ b/bsp/drivers/usart/pl011_uart/pl011_uart.h @@ -1,110 +1,110 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-07-02 16:56:15 - * @Description:  This files is for uart functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_DRIVERS_USART_PL011_UART_H -#define BSP_DRIVERS_USART_PL011_UART_H - -#include "ft_types.h" -#include "ft_assert.h" - -#include "pl011_uart_hw.h" - -#define ERR_INPUT_BAUD_NO_SUPPORT FT_CODE_ERR(ErrModBsp, ErrBspUart, 0x1u) - -#define FUART_BAUDRATE 115200U - -/* Config options */ -#define FUART_OPTION_UARTEN 0x1U -#define FUART_OPTION_RXEN 0x2U -#define FUART_OPTION_TXEN 0x4U -#define FUART_OPTION_FIFOEN 0x8U - -/* Data format values */ -#define FUART_FORMAT_WORDLENGTH_8BIT 0x3 -#define FUART_FORMAT_WORDLENGTH_7BIT 0x2 -#define FUART_FORMAT_WORDLENGTH_6BIT 0x1 -#define FUART_FORMAT_WORDLENGTH_5BIT 0x0 - -#define FUART_FORMAT_NO_PARITY 0U -#define FUART_FORMAT_MARK_PARITY 1U -#define FUART_FORMAT_SPACE_PARITY 2U -#define FUART_FORMAT_ODD_PARTY 3U -#define FUART_FORMAT_EVEN_PARITY 4U - -#define FUART_FORMAT_2_STOP_BIT 0U -#define FUART_FORMAT_1_STOP_BIT 1U - -/* Callback events */ - -#define FUART_EVENT_RECV_DATA 1U /**< Data receiving done */ -#define FUART_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */ -#define FUART_EVENT_SENT_DATA 3U /**< Data transmission done */ -#define FUART_EVENT_RECV_ERROR 4U /**< A receive error detected */ -#define FUART_EVENT_MODEM 5U /**< Modem status changed */ -#define FUART_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break \ - * error detected */ -#define FUART_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */ - -/**************************** Type Definitions ******************************/ -typedef struct -{ - u32 instance_id; /* Id of device*/ - u32 base_address; - u32 ref_clock_hz; - u32 irq_num; -} Pl011Config; - -typedef struct -{ - u8 *byte_p; - u32 requested_bytes; - u32 remaining_bytes; -} Pl011Buffer; - -typedef void (*Pl011EventHandler)(void *args, u32 event, u32 event_data); - -typedef struct -{ - Pl011Config config; /* Configuration data structure */ - u32 is_ready; /* Device is ininitialized and ready*/ - u32 baudrate; - - Pl011Buffer send_buffer; - Pl011Buffer receive_buffer; - - Pl011EventHandler handler; - void *args; - uint8_t rxbs_error; /* 接收过程中出现错误 ，0 无错误，1 存在错误*/ - -} Pl011; - -void Pl011PutChar(Pl011 *uart_p, s8 Data); -u32 Pl011Send(Pl011 *uart_p, u8 *Buffer, u32 Length); -u32 Pl011Receive(Pl011 *uart_p, u8 *byte_p, u32 Length); -u8 Pl011BlockReceive(Pl011 *uart_p); -s32 Pl011CfgInitialize(Pl011 *uart_p, Pl011Config *Config); -Pl011Config *Pl011LookupConfig(u32 instance_id); -void Pl011SetOptions(Pl011 *uart_p, u32 options); -void Pl011SetSpecificOptions(Pl011 *uart_p, u32 options); -void Pl011ClearSpecificOptions(Pl011 *uart_p, u32 options); -void Pl011InterruptHandler(Pl011 *uart_p); -void Pl011SetHandler(Pl011 *uart_p, Pl011EventHandler fun_p, void *args); -void Pl011SetInterruptMask(Pl011 *uart_p, u32 Mask); -u32 Pl011SetBaudRate(Pl011 *uart_p, u32 baudrate); -void Pl011IrqClearReciveTimeOut(Pl011 *uart_p); -void Pl011IrqEnableReciveTimeOut(Pl011 *uart_p); -u32 Pl011GetInterruptMask(Pl011 *uart_p); -void Pl011BlockSend(Pl011 *uart_p, u8 *byte_p, u32 Length); - -#endif // ! +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-07-02 16:56:15 + * @Description:  This files is for uart functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_DRIVERS_USART_PL011_UART_H +#define BSP_DRIVERS_USART_PL011_UART_H + +#include "ft_types.h" +#include "ft_assert.h" + +#include "pl011_uart_hw.h" + +#define ERR_INPUT_BAUD_NO_SUPPORT FT_CODE_ERR(ErrModBsp, ErrBspUart, 0x1u) + +#define FUART_BAUDRATE 115200U + +/* Config options */ +#define FUART_OPTION_UARTEN 0x1U +#define FUART_OPTION_RXEN 0x2U +#define FUART_OPTION_TXEN 0x4U +#define FUART_OPTION_FIFOEN 0x8U + +/* Data format values */ +#define FUART_FORMAT_WORDLENGTH_8BIT 0x3 +#define FUART_FORMAT_WORDLENGTH_7BIT 0x2 +#define FUART_FORMAT_WORDLENGTH_6BIT 0x1 +#define FUART_FORMAT_WORDLENGTH_5BIT 0x0 + +#define FUART_FORMAT_NO_PARITY 0U +#define FUART_FORMAT_MARK_PARITY 1U +#define FUART_FORMAT_SPACE_PARITY 2U +#define FUART_FORMAT_ODD_PARTY 3U +#define FUART_FORMAT_EVEN_PARITY 4U + +#define FUART_FORMAT_2_STOP_BIT 0U +#define FUART_FORMAT_1_STOP_BIT 1U + +/* Callback events */ + +#define FUART_EVENT_RECV_DATA 1U /**< Data receiving done */ +#define FUART_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */ +#define FUART_EVENT_SENT_DATA 3U /**< Data transmission done */ +#define FUART_EVENT_RECV_ERROR 4U /**< A receive error detected */ +#define FUART_EVENT_MODEM 5U /**< Modem status changed */ +#define FUART_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break \ + * error detected */ +#define FUART_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */ + +/**************************** Type Definitions ******************************/ +typedef struct +{ + u32 instance_id; /* Id of device*/ + u32 base_address; + u32 ref_clock_hz; + u32 irq_num; +} Pl011Config; + +typedef struct +{ + u8 *byte_p; + u32 requested_bytes; + u32 remaining_bytes; +} Pl011Buffer; + +typedef void (*Pl011EventHandler)(void *args, u32 event, u32 event_data); + +typedef struct +{ + Pl011Config config; /* Configuration data structure */ + u32 is_ready; /* Device is ininitialized and ready*/ + u32 baudrate; + + Pl011Buffer send_buffer; + Pl011Buffer receive_buffer; + + Pl011EventHandler handler; + void *args; + uint8_t rxbs_error; /* 接收过程中出现错误 ，0 无错误，1 存在错误*/ + +} Pl011; + +void Pl011PutChar(Pl011 *uart_p, s8 Data); +u32 Pl011Send(Pl011 *uart_p, u8 *Buffer, u32 Length); +u32 Pl011Receive(Pl011 *uart_p, u8 *byte_p, u32 Length); +u8 Pl011BlockReceive(Pl011 *uart_p); +s32 Pl011CfgInitialize(Pl011 *uart_p, Pl011Config *Config); +Pl011Config *Pl011LookupConfig(u32 instance_id); +void Pl011SetOptions(Pl011 *uart_p, u32 options); +void Pl011SetSpecificOptions(Pl011 *uart_p, u32 options); +void Pl011ClearSpecificOptions(Pl011 *uart_p, u32 options); +void Pl011InterruptHandler(Pl011 *uart_p); +void Pl011SetHandler(Pl011 *uart_p, Pl011EventHandler fun_p, void *args); +void Pl011SetInterruptMask(Pl011 *uart_p, u32 Mask); +u32 Pl011SetBaudRate(Pl011 *uart_p, u32 baudrate); +void Pl011IrqClearReciveTimeOut(Pl011 *uart_p); +void Pl011IrqEnableReciveTimeOut(Pl011 *uart_p); +u32 Pl011GetInterruptMask(Pl011 *uart_p); +void Pl011BlockSend(Pl011 *uart_p, u8 *byte_p, u32 Length); + +#endif // ! diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_g.c b/bsp/drivers/usart/pl011_uart/pl011_uart_g.c index 0a0bd64a0..785fef7d0 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_g.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_g.c @@ -1,34 +1,34 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-04-07 13:42:30 - * @Description:  This files is for uart config - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart.h" -#include "parameters.h" - -Pl011Config Pl011ConfigTable[FT_UART_NUM] = { - {FT_UART0_ID, - FT_UART0_BASE_ADDR, - FT_UART0_CLK_FREQ_HZ, - FT_UART0_IRQ_NUM}, - {FT_UART1_ID, - FT_UART1_BASE_ADDR, - FT_UART1_CLK_FREQ_HZ, - FT_UART1_IRQ_NUM}, - {FT_UART2_ID, - FT_UART2_BASE_ADDR, - FT_UART2_CLK_FREQ_HZ, - FT_UART2_IRQ_NUM}, - {FT_UART3_ID, - FT_UART3_BASE_ADDR, - FT_UART3_CLK_FREQ_HZ, - FT_UART3_IRQ_NUM}}; +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-04-07 13:42:30 + * @Description:  This files is for uart config + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart.h" +#include "parameters.h" + +Pl011Config Pl011ConfigTable[FT_UART_NUM] = { + {FT_UART0_ID, + FT_UART0_BASE_ADDR, + FT_UART0_CLK_FREQ_HZ, + FT_UART0_IRQ_NUM}, + {FT_UART1_ID, + FT_UART1_BASE_ADDR, + FT_UART1_CLK_FREQ_HZ, + FT_UART1_IRQ_NUM}, + {FT_UART2_ID, + FT_UART2_BASE_ADDR, + FT_UART2_CLK_FREQ_HZ, + FT_UART2_IRQ_NUM}, + {FT_UART3_ID, + FT_UART3_BASE_ADDR, + FT_UART3_CLK_FREQ_HZ, + FT_UART3_IRQ_NUM}}; diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_hw.c b/bsp/drivers/usart/pl011_uart/pl011_uart_hw.c index 5bba2ed51..4860ad90b 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_hw.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_hw.c @@ -1,65 +1,65 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-04-07 17:54:21 - * @Description:  This files is for uart register function - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart_hw.h" - -/** - * @name: Pl011SendByte - * @msg: - * @return {*} - * @param {u32} addr - * @param {u8} Byte - */ -void Pl011SendByte(u32 addr, u8 byte) -{ - while (FT_UART_ISTRANSMITFULL(addr)) - { - ; - } - FT_UART_WRITEREG32(addr, UARTDR_OFFSET, (u32)byte); -} - -/** - * @name: Pl011RecvByte - * @msg: - * @return {*} - * @param {u32} addr - */ -u8 Pl011RecvByte(u32 addr) -{ - u32 RecievedByte; - while (FT_UART_ISRECEIVEDATA(addr)) - { - ; - } - RecievedByte = FT_UART_READREG32(addr, UARTDR_OFFSET); - return RecievedByte; -} - -/** - * @name: Pl011GetChar - * @msg: - * @return {*} - * @param {u32} addr - */ -u8 Pl011GetChar(u32 addr) -{ - u32 RecievedByte; - if (FT_UART_ISRECEIVEDATA(addr)) - { - return 0xff; - } - RecievedByte = FT_UART_READREG32(addr, UARTDR_OFFSET); - return RecievedByte; -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-04-07 17:54:21 + * @Description:  This files is for uart register function + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart_hw.h" + +/** + * @name: Pl011SendByte + * @msg: + * @return {*} + * @param {u32} addr + * @param {u8} Byte + */ +void Pl011SendByte(u32 addr, u8 byte) +{ + while (FT_UART_ISTRANSMITFULL(addr)) + { + ; + } + FT_UART_WRITEREG32(addr, UARTDR_OFFSET, (u32)byte); +} + +/** + * @name: Pl011RecvByte + * @msg: + * @return {*} + * @param {u32} addr + */ +u8 Pl011RecvByte(u32 addr) +{ + u32 RecievedByte; + while (FT_UART_ISRECEIVEDATA(addr)) + { + ; + } + RecievedByte = FT_UART_READREG32(addr, UARTDR_OFFSET); + return RecievedByte; +} + +/** + * @name: Pl011GetChar + * @msg: + * @return {*} + * @param {u32} addr + */ +u8 Pl011GetChar(u32 addr) +{ + u32 RecievedByte; + if (FT_UART_ISRECEIVEDATA(addr)) + { + return 0xff; + } + RecievedByte = FT_UART_READREG32(addr, UARTDR_OFFSET); + return RecievedByte; +} diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_hw.h b/bsp/drivers/usart/pl011_uart/pl011_uart_hw.h index e2eff8fe1..3e7afc24c 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_hw.h +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_hw.h @@ -1,221 +1,221 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-03-31 14:59:20 - * @LastEditTime: 2021-05-28 11:59:51 - * @Description:  This files is for definition of uart register - * - * @Modify History: * * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_DRIVERS_USART_PL011_UART_HW_H -#define BSP_DRIVERS_USART_PL011_UART_HW_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "ft_types.h" -#include "ft_assert.h" -#include "ft_io.h" - - /************************** Constant Definitions *****************************/ - - /** @name Register Map - * - * Register offsets for the UART. - * @{ - */ - -#define UARTDR_OFFSET 0U /* 数据寄存器 */ -#define UARTRSR_OFFSET 4U /* 接收状态寄存器/错误清除寄存器 */ -#define UARTECR_OFFSET UARTRSR_OFFSET -#define UARTFTR_OFFSET 0x18U /* 标志寄存器 */ -#define UARTILPR_OFFSET 0x020U /* 低功耗计数寄存器 */ -#define UARTIBRD_OFFSET 0x024U /* 波特率整数值配置寄存器 */ -#define UARTFBRD_OFFSET 0x028U /* 波特率小数值配置寄存器 */ -#define UARTLCR_H_OFFSET 0x02cU /* 线控寄存器 */ -#define UARTCR_OFFSET 0x030U /* 控制寄存器 */ -#define UARTIFLS_OFFSET 0x034U /* FIFO阈值选择寄存器 */ -#define UARTIMSC_OFFSET 0x038U /* 中断屏蔽选择清除寄存器 */ -#define UARTRIS_OFFSET 0x03cU /* 中断状态寄存器 */ -#define UARTMIS_OFFSET 0x040U /* 中断屏蔽状态寄存器 */ -#define UARTICR_OFFSET 0x044U /* 中断清除寄存器 */ -#define UARTDMACR_OFFSET 0x048U /* DMA控制寄存器 */ - - /* 数据寄存器 RW */ - -#define UARTDR_OE 0x800U /* 如果接收到数据并且接收的 FIFO 已满，该位设置为 1 */ -#define UARTDR_BE 0x400U /* 突发错误 */ -#define UARTDR_PE 0x200U /* 奇偶校验错误。 */ -#define UARTDR_FE 0x100U /* 帧错误。 */ -#define UARTDR_ALLE (UARTDR_OE | UARTDR_BE | UARTDR_PE | UARTDR_FE) -#define UARTDR_DATA 0xffU /* R 接收数据 ，W 传输数据 */ - - /* 接收状态寄存器 RW */ - -#define UARTRSR_OE 0x8U /* 溢出错误。 */ -#define UARTRSR_BE 0x4U /* 突发错误 */ -#define UARTRSR_PE 0x2U /* 奇偶校验错误。 */ -#define UARTRSR_FE 0x1U /* 帧错误 */ - -#define UARTECR_CLE 0xffU /* 清除 */ - -/* 标志寄存器 RO */ -#define UARTFTR_RI 0x100U /* Ring indicator */ -#define UARTFTR_TXFE 0x80U /* Transmit FIFO empty */ -#define UARTFTR_RXFF 0x40U /* Receive FIFO full */ -#define UARTFTR_TXFF 0x20U /* Transmit FIFO full. */ -#define UARTFTR_RXFE 0x10U /* Receive FIFO empty */ -#define UARTFTR_BUSY 0x08U /* UART busy */ -#define UARTFTR_DCD 0x04U /* Data carrier detect. */ -#define UARTFTR_DSR 0x02U /* Data set ready. */ -#define UARTFTR_CTS 0x1U /* Clear to send */ - -/* IrDA 低功耗计数寄存器 RW */ -#define UARTILPR_ILPDVSR 0xffU /* 8-bit low-power divisor value. These bits are cleared to 0 at reset */ - -/* 波特率整数值配置寄存器 RW */ -#define UARTIBRD_BAUD_DIVFRAC 0xffffU /* The fractional baud rate divisor. */ - -/* 波特率小数值配置寄存器 RW */ -#define UARTFBRD_BAUD_DIVFRAC 0x3fU /* The fractional baud rate divisor. */ - -/* 线控寄存器 RW */ -#define UARTLCR_H_SPS 0x80U /* Stick parity select. */ -#define UARTLCR_H_WLEN 0x60U /* Word length. */ -#define UARTLCR_H_FEN 0x10U /* Enable FIFOs. */ -#define UARTLCR_H_STP2 0x08U /* Two stop bits select. */ -#define UARTLCR_H_EPS 0x04U /* Even parity select. */ -#define UARTLCR_H_PEN 0x02U /* Parity enable. */ -#define UARTLCR_H_BRK 0x01U /* send break */ - -/* 控制寄存器 RW */ -#define UARTCR_CTSEN 0x8000U /* CTS hardware flow control enable. */ -#define UARTCR_RTSEN 0x4000U /* RTS hardware flow control enable. */ -#define UARTCR_OUT2 0x2000U /* This bit is the complement of the UART Out2 (nUARTOut2) modem status output. */ -#define UARTCR_Out1 0x1000U /* This bit is the complement of the UART Out1 (nUARTOut1) modem status output. */ -#define UARTCR_RTS 0x0800U /* Request to send. */ -#define UARTCR_DTR 0x0400U /* Data transmit ready */ -#define UARTCR_RXE 0x0200U /* Receive enable. */ -#define UARTCR_TXE 0x0100U /* Transmit enable. */ -#define UARTCR_LBE 0x0080U /* Loop back enable.*/ -#define UARTCR_SIRLP 0x4U /* IrDA SIR low power mode. */ -#define UARTCR_SIREN 0x2U /* SIR enable. */ -#define UARTCR_UARTEN 0x1U /* UART enable. */ - -/* FIFO阈值选择寄存器 RW */ -#define UARTIFLS_RXIFLSEL 0x38U /* Receive interrupt FIFO level select. */ -#define UARTIFLS_TXIFLSEL 0x7U /* Transmit interrupt FIFO level select. */ - -/* 中断屏蔽选择清除寄存器 RW */ -#define UARTIMSC_OEIM 0x400U /* Overrun error interrupt mask. */ -#define UARTIMSC_BEIM 0x200U /* Break error interrupt mask */ -#define UARTIMSC_PEIM 0x100U /* Parity error interrupt mask. */ -#define UARTIMSC_FEIM 0x80U /* Framing error interrupt mask. */ -#define UARTIMSC_RTIM 0x40U /* Receive timeout interrupt mask. */ -#define UARTIMSC_TXIM 0x20U /* Transmit interrupt mask. */ -#define UARTIMSC_RXIM 0x10U /* Receive interrupt mask. */ -#define UARTIMSC_DSRMIM 0x8U /* nUARTDSR modem interrupt mask. */ -#define UARTIMSC_DCDMIM 0x4U /* nUARTDCD modem interrupt mask. */ -#define UARTIMSC_CTSMIM 0x2U /* nUARTCTS modem interrupt mask. */ -#define UARTIMSC_RIMIM 0x1U /* nUARTRI modem interrupt mask. */ -#define UARTIMSC_ALLM 0x3ffU /* all interrupt mask */ - - /* 中断状态寄存器 RO */ - -#define UARTRIS_OEIS 0x400U /* Overrun error interrupt mask. */ -#define UARTRIS_BEIS 0x200U /* Break error interrupt mask */ -#define UARTRIS_PEIS 0x100U /* Parity error interrupt mask. */ -#define UARTRIS_FEIS 0x80U /* Framing error interrupt mask. */ -#define UARTRIS_RTIS 0x40U /* Receive timeout interrupt mask. */ -#define UARTRIS_TXIS 0x20U /* Transmit interrupt mask. */ -#define UARTRIS_RXIS 0x10U /* Receive interrupt mask. */ -#define UARTRIS_DSRMIS 0x8U /* nUARTDSR modem interrupt mask. */ -#define UARTRIS_DCDMIS 0x4U /* nUARTDCD modem interrupt mask. */ -#define UARTRIS_CTSMIS 0x2U /* nUARTCTS modem interrupt mask. */ -#define UARTRIS_RIMIS 0x1U /* nUARTRI modem interrupt mask. */ - - /* 中断屏蔽状态寄存器 R0 */ - -#define UARTMIS_OEMIS 0x400U /* Overrun error interrupt mask. */ -#define UARTMIS_BEMIS 0x200U /* Break error interrupt mask */ -#define UARTMIS_PEMIS 0x100U /* Parity error interrupt mask. */ -#define UARTMIS_FEMIS 0x80U /* Framing error interrupt mask. */ -#define UARTMIS_RTMIS 0x40U /* Receive timeout interrupt mask. */ -#define UARTMIS_TXMIS 0x20U /* Transmit interrupt mask. */ -#define UARTMIS_RXMIS 0x10U /* Receive interrupt mask. */ -#define UARTMIS_DSRMMIS 0x8U /* nUARTDSR modem interrupt mask. */ -#define UARTMIS_DCDMMIS 0x4U /* nUARTDCD modem interrupt mask. */ -#define UARTMIS_CTSMMIS 0x2U /* nUARTCTS modem interrupt mask. */ -#define UARTMIS_RIMMIS 0x1U /* nUARTRI modem interrupt mask. */ - -/* 中断清除寄存器 WO */ -#define UARTICR_OEIC 0x400U /* Overrun error interrupt mask. */ -#define UARTICR_BEIC 0x200U /* Break error interrupt mask */ -#define UARTICR_PEIC 0x100U /* Parity error interrupt mask. */ -#define UARTICR_FEIC 0x80U /* Framing error interrupt mask. */ -#define UARTICR_RTIC 0x40U /* Receive timeout interrupt mask. */ -#define UARTICR_TXIC 0x20U /* Transmit interrupt mask. */ -#define UARTICR_RXIC 0x10U /* Receive interrupt mask. */ -#define UARTICR_DSRMIC 0x8U /* nUARTDSR modem interrupt mask. */ -#define UARTICR_DCDMIC 0x4U /* nUARTDCD modem interrupt mask. */ -#define UARTICR_CTSMIC 0x2U /* nUARTCTS modem interrupt mask. */ -#define UARTICR_RIMIC 0x1U /* nUARTRI modem interrupt mask. */ - -/* DMA控制寄存器 RW */ -#define UARTDMACR_DMAONERR 0x4U /* DMA on error. */ -#define UARTDMACR_TXDMAE 0x2U /* Transmit DMA enable. */ -#define UARTDMACR_RXDMAE 0x1U /* Receive DMA enable. */ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/** - * @name: FT_UART_READREG32 - * @msg: 读取串口寄存器 - * @param {u32} addr 串口的基地址 - * @param {u32} reg_offset 串口的寄存器的偏移 - * @return {u32} 寄存器参数 - */ -#define FT_UART_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset) - -/** - * @name: FT_UART_WRITEREG32 - * @msg: 写入串口寄存器 - * @param {u32} addr 串口的基地址 - * @param {u32} reg_offset 串口的寄存器的偏移 - * @param {u32} reg_value 写入寄存器参数 - * @return {void} - */ -#define FT_UART_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value) - -/** - * @name: FT_UART_ISRECEIVEDATA - * @msg: 用于确认是否接收到数据 - * @param {u32} addr 串口的基地址 - * @return {bool} true 是存在数据 ， false 是不存在数据 - * - */ -#define FT_UART_ISRECEIVEDATA(addr) (FtIn32(addr + UARTFTR_OFFSET) & UARTFTR_RXFE) - -/** - * @name: FT_UART_ISTRANSMITFULL - * @msg: 用于确认是否能够发送数据 - * @param {u32} addr 串口的基地址 - * @return {bool} true 是数据已满 ， false 可以发送数据 - */ -#define FT_UART_ISTRANSMITFULL(addr) ((FtIn32(addr + UARTFTR_OFFSET) & (u32)UARTFTR_TXFF) == UARTFTR_TXFF) - - void Pl011SendByte(u32 addr, u8 byte); - u8 Pl011RecvByte(u32 addr); - u8 Pl011GetChar(u32 addr); - -#ifdef __cplusplus -} -#endif - -#endif +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-03-31 14:59:20 + * @LastEditTime: 2021-05-28 11:59:51 + * @Description:  This files is for definition of uart register + * + * @Modify History: * * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef BSP_DRIVERS_USART_PL011_UART_HW_H +#define BSP_DRIVERS_USART_PL011_UART_HW_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "ft_types.h" +#include "ft_assert.h" +#include "ft_io.h" + + /************************** Constant Definitions *****************************/ + + /** @name Register Map + * + * Register offsets for the UART. + * @{ + */ + +#define UARTDR_OFFSET 0U /* 数据寄存器 */ +#define UARTRSR_OFFSET 4U /* 接收状态寄存器/错误清除寄存器 */ +#define UARTECR_OFFSET UARTRSR_OFFSET +#define UARTFTR_OFFSET 0x18U /* 标志寄存器 */ +#define UARTILPR_OFFSET 0x020U /* 低功耗计数寄存器 */ +#define UARTIBRD_OFFSET 0x024U /* 波特率整数值配置寄存器 */ +#define UARTFBRD_OFFSET 0x028U /* 波特率小数值配置寄存器 */ +#define UARTLCR_H_OFFSET 0x02cU /* 线控寄存器 */ +#define UARTCR_OFFSET 0x030U /* 控制寄存器 */ +#define UARTIFLS_OFFSET 0x034U /* FIFO阈值选择寄存器 */ +#define UARTIMSC_OFFSET 0x038U /* 中断屏蔽选择清除寄存器 */ +#define UARTRIS_OFFSET 0x03cU /* 中断状态寄存器 */ +#define UARTMIS_OFFSET 0x040U /* 中断屏蔽状态寄存器 */ +#define UARTICR_OFFSET 0x044U /* 中断清除寄存器 */ +#define UARTDMACR_OFFSET 0x048U /* DMA控制寄存器 */ + + /* 数据寄存器 RW */ + +#define UARTDR_OE 0x800U /* 如果接收到数据并且接收的 FIFO 已满，该位设置为 1 */ +#define UARTDR_BE 0x400U /* 突发错误 */ +#define UARTDR_PE 0x200U /* 奇偶校验错误。 */ +#define UARTDR_FE 0x100U /* 帧错误。 */ +#define UARTDR_ALLE (UARTDR_OE | UARTDR_BE | UARTDR_PE | UARTDR_FE) +#define UARTDR_DATA 0xffU /* R 接收数据 ，W 传输数据 */ + + /* 接收状态寄存器 RW */ + +#define UARTRSR_OE 0x8U /* 溢出错误。 */ +#define UARTRSR_BE 0x4U /* 突发错误 */ +#define UARTRSR_PE 0x2U /* 奇偶校验错误。 */ +#define UARTRSR_FE 0x1U /* 帧错误 */ + +#define UARTECR_CLE 0xffU /* 清除 */ + +/* 标志寄存器 RO */ +#define UARTFTR_RI 0x100U /* Ring indicator */ +#define UARTFTR_TXFE 0x80U /* Transmit FIFO empty */ +#define UARTFTR_RXFF 0x40U /* Receive FIFO full */ +#define UARTFTR_TXFF 0x20U /* Transmit FIFO full. */ +#define UARTFTR_RXFE 0x10U /* Receive FIFO empty */ +#define UARTFTR_BUSY 0x08U /* UART busy */ +#define UARTFTR_DCD 0x04U /* Data carrier detect. */ +#define UARTFTR_DSR 0x02U /* Data set ready. */ +#define UARTFTR_CTS 0x1U /* Clear to send */ + +/* IrDA 低功耗计数寄存器 RW */ +#define UARTILPR_ILPDVSR 0xffU /* 8-bit low-power divisor value. These bits are cleared to 0 at reset */ + +/* 波特率整数值配置寄存器 RW */ +#define UARTIBRD_BAUD_DIVFRAC 0xffffU /* The fractional baud rate divisor. */ + +/* 波特率小数值配置寄存器 RW */ +#define UARTFBRD_BAUD_DIVFRAC 0x3fU /* The fractional baud rate divisor. */ + +/* 线控寄存器 RW */ +#define UARTLCR_H_SPS 0x80U /* Stick parity select. */ +#define UARTLCR_H_WLEN 0x60U /* Word length. */ +#define UARTLCR_H_FEN 0x10U /* Enable FIFOs. */ +#define UARTLCR_H_STP2 0x08U /* Two stop bits select. */ +#define UARTLCR_H_EPS 0x04U /* Even parity select. */ +#define UARTLCR_H_PEN 0x02U /* Parity enable. */ +#define UARTLCR_H_BRK 0x01U /* send break */ + +/* 控制寄存器 RW */ +#define UARTCR_CTSEN 0x8000U /* CTS hardware flow control enable. */ +#define UARTCR_RTSEN 0x4000U /* RTS hardware flow control enable. */ +#define UARTCR_OUT2 0x2000U /* This bit is the complement of the UART Out2 (nUARTOut2) modem status output. */ +#define UARTCR_Out1 0x1000U /* This bit is the complement of the UART Out1 (nUARTOut1) modem status output. */ +#define UARTCR_RTS 0x0800U /* Request to send. */ +#define UARTCR_DTR 0x0400U /* Data transmit ready */ +#define UARTCR_RXE 0x0200U /* Receive enable. */ +#define UARTCR_TXE 0x0100U /* Transmit enable. */ +#define UARTCR_LBE 0x0080U /* Loop back enable.*/ +#define UARTCR_SIRLP 0x4U /* IrDA SIR low power mode. */ +#define UARTCR_SIREN 0x2U /* SIR enable. */ +#define UARTCR_UARTEN 0x1U /* UART enable. */ + +/* FIFO阈值选择寄存器 RW */ +#define UARTIFLS_RXIFLSEL 0x38U /* Receive interrupt FIFO level select. */ +#define UARTIFLS_TXIFLSEL 0x7U /* Transmit interrupt FIFO level select. */ + +/* 中断屏蔽选择清除寄存器 RW */ +#define UARTIMSC_OEIM 0x400U /* Overrun error interrupt mask. */ +#define UARTIMSC_BEIM 0x200U /* Break error interrupt mask */ +#define UARTIMSC_PEIM 0x100U /* Parity error interrupt mask. */ +#define UARTIMSC_FEIM 0x80U /* Framing error interrupt mask. */ +#define UARTIMSC_RTIM 0x40U /* Receive timeout interrupt mask. */ +#define UARTIMSC_TXIM 0x20U /* Transmit interrupt mask. */ +#define UARTIMSC_RXIM 0x10U /* Receive interrupt mask. */ +#define UARTIMSC_DSRMIM 0x8U /* nUARTDSR modem interrupt mask. */ +#define UARTIMSC_DCDMIM 0x4U /* nUARTDCD modem interrupt mask. */ +#define UARTIMSC_CTSMIM 0x2U /* nUARTCTS modem interrupt mask. */ +#define UARTIMSC_RIMIM 0x1U /* nUARTRI modem interrupt mask. */ +#define UARTIMSC_ALLM 0x3ffU /* all interrupt mask */ + + /* 中断状态寄存器 RO */ + +#define UARTRIS_OEIS 0x400U /* Overrun error interrupt mask. */ +#define UARTRIS_BEIS 0x200U /* Break error interrupt mask */ +#define UARTRIS_PEIS 0x100U /* Parity error interrupt mask. */ +#define UARTRIS_FEIS 0x80U /* Framing error interrupt mask. */ +#define UARTRIS_RTIS 0x40U /* Receive timeout interrupt mask. */ +#define UARTRIS_TXIS 0x20U /* Transmit interrupt mask. */ +#define UARTRIS_RXIS 0x10U /* Receive interrupt mask. */ +#define UARTRIS_DSRMIS 0x8U /* nUARTDSR modem interrupt mask. */ +#define UARTRIS_DCDMIS 0x4U /* nUARTDCD modem interrupt mask. */ +#define UARTRIS_CTSMIS 0x2U /* nUARTCTS modem interrupt mask. */ +#define UARTRIS_RIMIS 0x1U /* nUARTRI modem interrupt mask. */ + + /* 中断屏蔽状态寄存器 R0 */ + +#define UARTMIS_OEMIS 0x400U /* Overrun error interrupt mask. */ +#define UARTMIS_BEMIS 0x200U /* Break error interrupt mask */ +#define UARTMIS_PEMIS 0x100U /* Parity error interrupt mask. */ +#define UARTMIS_FEMIS 0x80U /* Framing error interrupt mask. */ +#define UARTMIS_RTMIS 0x40U /* Receive timeout interrupt mask. */ +#define UARTMIS_TXMIS 0x20U /* Transmit interrupt mask. */ +#define UARTMIS_RXMIS 0x10U /* Receive interrupt mask. */ +#define UARTMIS_DSRMMIS 0x8U /* nUARTDSR modem interrupt mask. */ +#define UARTMIS_DCDMMIS 0x4U /* nUARTDCD modem interrupt mask. */ +#define UARTMIS_CTSMMIS 0x2U /* nUARTCTS modem interrupt mask. */ +#define UARTMIS_RIMMIS 0x1U /* nUARTRI modem interrupt mask. */ + +/* 中断清除寄存器 WO */ +#define UARTICR_OEIC 0x400U /* Overrun error interrupt mask. */ +#define UARTICR_BEIC 0x200U /* Break error interrupt mask */ +#define UARTICR_PEIC 0x100U /* Parity error interrupt mask. */ +#define UARTICR_FEIC 0x80U /* Framing error interrupt mask. */ +#define UARTICR_RTIC 0x40U /* Receive timeout interrupt mask. */ +#define UARTICR_TXIC 0x20U /* Transmit interrupt mask. */ +#define UARTICR_RXIC 0x10U /* Receive interrupt mask. */ +#define UARTICR_DSRMIC 0x8U /* nUARTDSR modem interrupt mask. */ +#define UARTICR_DCDMIC 0x4U /* nUARTDCD modem interrupt mask. */ +#define UARTICR_CTSMIC 0x2U /* nUARTCTS modem interrupt mask. */ +#define UARTICR_RIMIC 0x1U /* nUARTRI modem interrupt mask. */ + +/* DMA控制寄存器 RW */ +#define UARTDMACR_DMAONERR 0x4U /* DMA on error. */ +#define UARTDMACR_TXDMAE 0x2U /* Transmit DMA enable. */ +#define UARTDMACR_RXDMAE 0x1U /* Receive DMA enable. */ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/** + * @name: FT_UART_READREG32 + * @msg: 读取串口寄存器 + * @param {u32} addr 串口的基地址 + * @param {u32} reg_offset 串口的寄存器的偏移 + * @return {u32} 寄存器参数 + */ +#define FT_UART_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset) + +/** + * @name: FT_UART_WRITEREG32 + * @msg: 写入串口寄存器 + * @param {u32} addr 串口的基地址 + * @param {u32} reg_offset 串口的寄存器的偏移 + * @param {u32} reg_value 写入寄存器参数 + * @return {void} + */ +#define FT_UART_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value) + +/** + * @name: FT_UART_ISRECEIVEDATA + * @msg: 用于确认是否接收到数据 + * @param {u32} addr 串口的基地址 + * @return {bool} true 是存在数据 ， false 是不存在数据 + * + */ +#define FT_UART_ISRECEIVEDATA(addr) (FtIn32(addr + UARTFTR_OFFSET) & UARTFTR_RXFE) + +/** + * @name: FT_UART_ISTRANSMITFULL + * @msg: 用于确认是否能够发送数据 + * @param {u32} addr 串口的基地址 + * @return {bool} true 是数据已满 ， false 可以发送数据 + */ +#define FT_UART_ISTRANSMITFULL(addr) ((FtIn32(addr + UARTFTR_OFFSET) & (u32)UARTFTR_TXFF) == UARTFTR_TXFF) + + void Pl011SendByte(u32 addr, u8 byte); + u8 Pl011RecvByte(u32 addr); + u8 Pl011GetChar(u32 addr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c b/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c index 68ae6a3bc..854bf7b69 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_intr.c @@ -1,202 +1,202 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-07-07 17:55:12 - * @Description:  This files is for uart irq functions - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart.h" - -extern u32 Pl011SendBuffer(Pl011 *uart_p); -extern u32 Pl011ReceiveBuffer(Pl011 *uart_p); - -static void Pl011ReceiveErrorHandler(Pl011 *uart_p, u32 InterruptStatus); -static void Pl011ReceiveDataHandler(Pl011 *uart_p); -static void Pl011ReceiveTimeoutHandler(Pl011 *uart_p); -static void Pl011SendDataHandler(Pl011 *uart_p, u32 InterruptStatus); - -/** - * @name: Pl011GetInterruptMask - * @msg: 此函数获取所有串口中断的mask。 - * @param {Ft_Uart} *uart_p - * @return {u32} mask - */ -u32 Pl011GetInterruptMask(Pl011 *uart_p) -{ - FT_ASSERTNONVOID(uart_p != NULL); - return FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); -} - -/** - * @name: - * @msg: - * @param {Ft_Uart} *UartPtr - * @param {u32} Mask - * @return {*} - */ -void Pl011SetInterruptMask(Pl011 *UartPtr, u32 Mask) -{ - u32 temp_mask = Mask; - FT_ASSERTVOID(UartPtr != NULL); - - temp_mask &= UARTIMSC_ALLM; - - FT_UART_WRITEREG32(UartPtr->config.base_address, UARTIMSC_OFFSET, temp_mask); -} - -/** - * @name: Pl011SetHandler - * @msg: 设置中断回调函数 - * @param {*} - * @return {*} - */ -void Pl011SetHandler(Pl011 *UartPtr, Pl011EventHandler fun_p, - void *Args) -{ - FT_ASSERTVOID(UartPtr != NULL); - FT_ASSERTVOID(fun_p != NULL); - FT_ASSERTVOID(UartPtr->is_ready == FT_COMPONENT_IS_READLY); - - UartPtr->handler = fun_p; - UartPtr->args = Args; -} - -/** - * @name: Pl011InterruptHandler - * @msg: 串口中断函数入口 - * @param {Ft_Uart} *UartPtr - * @return {*} - */ -void Pl011InterruptHandler(Pl011 *uart_p) -{ - u32 RegValue = 0; - FT_ASSERTVOID(uart_p != NULL); - FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); - RegValue &= FT_UART_READREG32(uart_p->config.base_address, UARTMIS_OFFSET); - - if ((RegValue & ((u32)UARTMIS_RXMIS)) != (u32)0) - { - /* Received data interrupt */ - Pl011ReceiveDataHandler(uart_p); - } - - if ((RegValue & ((u32)UARTMIS_TXMIS)) != (u32)0) - { - /* Transmit data interrupt */ - Pl011SendDataHandler(uart_p, RegValue); - } - - if (((RegValue) & ((u32)UARTMIS_OEMIS | (u32)UARTMIS_BEMIS | (u32)UARTMIS_PEMIS | (u32)UARTMIS_FEMIS)) != (u32)0) - { - /* Received Error Status interrupt */ - Pl011ReceiveErrorHandler(uart_p, RegValue); - } - - if ((RegValue & ((u32)UARTMIS_RTMIS)) != (u32)0) - { - /* Received Timeout interrupt */ - Pl011ReceiveTimeoutHandler(uart_p); - } - - if (((RegValue) & ((u32)UARTMIS_DSRMMIS | (u32)UARTMIS_DCDMMIS | (u32)UARTMIS_CTSMMIS | (u32)UARTMIS_RIMMIS)) != (u32)0) - { - /* Modem status interrupt */ - } - - /* Clear the interrupt status. */ - FT_UART_WRITEREG32(uart_p->config.base_address, UARTICR_OFFSET, - RegValue); -} - -static void Pl011ReceiveErrorHandler(Pl011 *uart_p, u32 InterruptStatus) -{ - uart_p->rxbs_error = 0; - - if (((InterruptStatus) & ((u32)UARTMIS_OEMIS | (u32)UARTMIS_BEMIS | (u32)UARTMIS_PEMIS | (u32)UARTMIS_FEMIS)) != 0) - { - uart_p->rxbs_error = 1; - } - - (void)Pl011ReceiveBuffer(uart_p); - - if (0 == uart_p->rxbs_error) - { - if (uart_p->handler) - { - uart_p->handler(uart_p->args, FUART_EVENT_RECV_ERROR, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); - } - } -} - -/** - * @name: Pl011ReceiveDataHandler - * @msg: - * @param {*} - * @return {*} - */ -static void Pl011ReceiveDataHandler(Pl011 *uart_p) -{ - if ((u32)0 != uart_p->receive_buffer.remaining_bytes) - { - (void)Pl011ReceiveBuffer(uart_p); - } - - if ((u32)0 == uart_p->receive_buffer.remaining_bytes) - { - if (uart_p->handler) - { - uart_p->handler(uart_p->args, FUART_EVENT_RECV_DATA, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); - } - } -} - -static void Pl011ReceiveTimeoutHandler(Pl011 *uart_p) -{ - u32 Event; - - if ((u32)0 != uart_p->receive_buffer.remaining_bytes) - { - (void)Pl011ReceiveBuffer(uart_p); - } - - if ((u32)0 == uart_p->receive_buffer.remaining_bytes) - { - Event = FUART_EVENT_RECV_TOUT; - } - else - { - Event = FUART_EVENT_RECV_DATA; - } - - if (uart_p->handler) - { - uart_p->handler(uart_p->args, Event, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); - } -} - -static void Pl011SendDataHandler(Pl011 *uart_p, u32 InterruptStatus) -{ - if (uart_p->send_buffer.remaining_bytes == (u32)0) - { - if (uart_p->handler) - { - uart_p->handler(uart_p->args, FUART_EVENT_RECV_DATA, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); - } - } - else if (InterruptStatus & UARTMIS_TXMIS) - { - Pl011SendBuffer(uart_p); - } - else - { - } -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-07-07 17:55:12 + * @Description:  This files is for uart irq functions + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart.h" + +extern u32 Pl011SendBuffer(Pl011 *uart_p); +extern u32 Pl011ReceiveBuffer(Pl011 *uart_p); + +static void Pl011ReceiveErrorHandler(Pl011 *uart_p, u32 InterruptStatus); +static void Pl011ReceiveDataHandler(Pl011 *uart_p); +static void Pl011ReceiveTimeoutHandler(Pl011 *uart_p); +static void Pl011SendDataHandler(Pl011 *uart_p, u32 InterruptStatus); + +/** + * @name: Pl011GetInterruptMask + * @msg: 此函数获取所有串口中断的mask。 + * @param {Ft_Uart} *uart_p + * @return {u32} mask + */ +u32 Pl011GetInterruptMask(Pl011 *uart_p) +{ + FT_ASSERTNONVOID(uart_p != NULL); + return FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); +} + +/** + * @name: + * @msg: + * @param {Ft_Uart} *UartPtr + * @param {u32} Mask + * @return {*} + */ +void Pl011SetInterruptMask(Pl011 *UartPtr, u32 Mask) +{ + u32 temp_mask = Mask; + FT_ASSERTVOID(UartPtr != NULL); + + temp_mask &= UARTIMSC_ALLM; + + FT_UART_WRITEREG32(UartPtr->config.base_address, UARTIMSC_OFFSET, temp_mask); +} + +/** + * @name: Pl011SetHandler + * @msg: 设置中断回调函数 + * @param {*} + * @return {*} + */ +void Pl011SetHandler(Pl011 *UartPtr, Pl011EventHandler fun_p, + void *Args) +{ + FT_ASSERTVOID(UartPtr != NULL); + FT_ASSERTVOID(fun_p != NULL); + FT_ASSERTVOID(UartPtr->is_ready == FT_COMPONENT_IS_READLY); + + UartPtr->handler = fun_p; + UartPtr->args = Args; +} + +/** + * @name: Pl011InterruptHandler + * @msg: 串口中断函数入口 + * @param {Ft_Uart} *UartPtr + * @return {*} + */ +void Pl011InterruptHandler(Pl011 *uart_p) +{ + u32 RegValue = 0; + FT_ASSERTVOID(uart_p != NULL); + FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + RegValue = FT_UART_READREG32(uart_p->config.base_address, UARTIMSC_OFFSET); + RegValue &= FT_UART_READREG32(uart_p->config.base_address, UARTMIS_OFFSET); + + if ((RegValue & ((u32)UARTMIS_RXMIS)) != (u32)0) + { + /* Received data interrupt */ + Pl011ReceiveDataHandler(uart_p); + } + + if ((RegValue & ((u32)UARTMIS_TXMIS)) != (u32)0) + { + /* Transmit data interrupt */ + Pl011SendDataHandler(uart_p, RegValue); + } + + if (((RegValue) & ((u32)UARTMIS_OEMIS | (u32)UARTMIS_BEMIS | (u32)UARTMIS_PEMIS | (u32)UARTMIS_FEMIS)) != (u32)0) + { + /* Received Error Status interrupt */ + Pl011ReceiveErrorHandler(uart_p, RegValue); + } + + if ((RegValue & ((u32)UARTMIS_RTMIS)) != (u32)0) + { + /* Received Timeout interrupt */ + Pl011ReceiveTimeoutHandler(uart_p); + } + + if (((RegValue) & ((u32)UARTMIS_DSRMMIS | (u32)UARTMIS_DCDMMIS | (u32)UARTMIS_CTSMMIS | (u32)UARTMIS_RIMMIS)) != (u32)0) + { + /* Modem status interrupt */ + } + + /* Clear the interrupt status. */ + FT_UART_WRITEREG32(uart_p->config.base_address, UARTICR_OFFSET, + RegValue); +} + +static void Pl011ReceiveErrorHandler(Pl011 *uart_p, u32 InterruptStatus) +{ + uart_p->rxbs_error = 0; + + if (((InterruptStatus) & ((u32)UARTMIS_OEMIS | (u32)UARTMIS_BEMIS | (u32)UARTMIS_PEMIS | (u32)UARTMIS_FEMIS)) != 0) + { + uart_p->rxbs_error = 1; + } + + (void)Pl011ReceiveBuffer(uart_p); + + if (0 == uart_p->rxbs_error) + { + if (uart_p->handler) + { + uart_p->handler(uart_p->args, FUART_EVENT_RECV_ERROR, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); + } + } +} + +/** + * @name: Pl011ReceiveDataHandler + * @msg: + * @param {*} + * @return {*} + */ +static void Pl011ReceiveDataHandler(Pl011 *uart_p) +{ + if ((u32)0 != uart_p->receive_buffer.remaining_bytes) + { + (void)Pl011ReceiveBuffer(uart_p); + } + + if ((u32)0 == uart_p->receive_buffer.remaining_bytes) + { + if (uart_p->handler) + { + uart_p->handler(uart_p->args, FUART_EVENT_RECV_DATA, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); + } + } +} + +static void Pl011ReceiveTimeoutHandler(Pl011 *uart_p) +{ + u32 Event; + + if ((u32)0 != uart_p->receive_buffer.remaining_bytes) + { + (void)Pl011ReceiveBuffer(uart_p); + } + + if ((u32)0 == uart_p->receive_buffer.remaining_bytes) + { + Event = FUART_EVENT_RECV_TOUT; + } + else + { + Event = FUART_EVENT_RECV_DATA; + } + + if (uart_p->handler) + { + uart_p->handler(uart_p->args, Event, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); + } +} + +static void Pl011SendDataHandler(Pl011 *uart_p, u32 InterruptStatus) +{ + if (uart_p->send_buffer.remaining_bytes == (u32)0) + { + if (uart_p->handler) + { + uart_p->handler(uart_p->args, FUART_EVENT_RECV_DATA, uart_p->receive_buffer.requested_bytes - uart_p->receive_buffer.remaining_bytes); + } + } + else if (InterruptStatus & UARTMIS_TXMIS) + { + Pl011SendBuffer(uart_p); + } + else + { + } +} diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_options.c b/bsp/drivers/usart/pl011_uart/pl011_uart_options.c index 054455586..d7f8b3951 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_options.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_options.c @@ -1,102 +1,102 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-05-24 10:47:33 - * @Description:  This files is for uart option setting - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart.h" -#include "pl011_uart_hw.h" -#include "ft_types.h" -/************************** Variable Definitions ****************************/ -/* - * The following data type is a map from an option to the offset in the - * register to which it belongs as well as its bit mask in that register. - */ -typedef struct -{ - u32 Option; - u32 RegisterOffset; - u32 Mask; -} Mapping; - -static Mapping OptionTable[] = { - {FUART_OPTION_UARTEN, UARTCR_OFFSET, UARTCR_UARTEN}, - {FUART_OPTION_RXEN, UARTCR_OFFSET, UARTCR_RXE}, - {FUART_OPTION_TXEN, UARTCR_OFFSET, UARTCR_TXE}, - {FUART_OPTION_FIFOEN, UARTLCR_H_OFFSET, UARTLCR_H_FEN}}; - -#define FT_UART_NUM_OPITIONS (sizeof(OptionTable) / sizeof(Mapping)) - -void Pl011SetOptions(Pl011 *uart_p, u32 options) -{ - u32 index; - u32 reg_value; - FT_ASSERTVOID(uart_p != NULL); - FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); - - for (index = 0; index < FT_UART_NUM_OPITIONS; index++) - { - reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); - - if ((options & OptionTable[index].Option) != (u32)(0)) - { - reg_value |= OptionTable[index].Mask; - } - else - { - reg_value &= ~OptionTable[index].Mask; - } - - FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); - } -} - -void Pl011SetSpecificOptions(Pl011 *uart_p, u32 options) -{ - u32 index; - u32 reg_value; - FT_ASSERTVOID(uart_p != NULL); - - for (index = 0; index < FT_UART_NUM_OPITIONS; index++) - { - if ((options & OptionTable[index].Option) == (u32)(0)) - { - continue; - } - - reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); - - /* set specific options */ - reg_value |= OptionTable[index].Mask; - FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); - } -} - -void Pl011ClearSpecificOptions(Pl011 *uart_p, u32 options) -{ - u32 index; - u32 reg_value; - FT_ASSERTVOID(uart_p != NULL); - - for (index = 0; index < FT_UART_NUM_OPITIONS; index++) - { - if ((options & OptionTable[index].Option) == (u32)(0)) - { - continue; - } - - reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); - - /* remove specific options */ - reg_value &= ~OptionTable[index].Mask; - FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); - } -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-05-24 10:47:33 + * @Description:  This files is for uart option setting + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart.h" +#include "pl011_uart_hw.h" +#include "ft_types.h" +/************************** Variable Definitions ****************************/ +/* + * The following data type is a map from an option to the offset in the + * register to which it belongs as well as its bit mask in that register. + */ +typedef struct +{ + u32 Option; + u32 RegisterOffset; + u32 Mask; +} Mapping; + +static Mapping OptionTable[] = { + {FUART_OPTION_UARTEN, UARTCR_OFFSET, UARTCR_UARTEN}, + {FUART_OPTION_RXEN, UARTCR_OFFSET, UARTCR_RXE}, + {FUART_OPTION_TXEN, UARTCR_OFFSET, UARTCR_TXE}, + {FUART_OPTION_FIFOEN, UARTLCR_H_OFFSET, UARTLCR_H_FEN}}; + +#define FT_UART_NUM_OPITIONS (sizeof(OptionTable) / sizeof(Mapping)) + +void Pl011SetOptions(Pl011 *uart_p, u32 options) +{ + u32 index; + u32 reg_value; + FT_ASSERTVOID(uart_p != NULL); + FT_ASSERTVOID(uart_p->is_ready == FT_COMPONENT_IS_READLY); + + for (index = 0; index < FT_UART_NUM_OPITIONS; index++) + { + reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); + + if ((options & OptionTable[index].Option) != (u32)(0)) + { + reg_value |= OptionTable[index].Mask; + } + else + { + reg_value &= ~OptionTable[index].Mask; + } + + FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); + } +} + +void Pl011SetSpecificOptions(Pl011 *uart_p, u32 options) +{ + u32 index; + u32 reg_value; + FT_ASSERTVOID(uart_p != NULL); + + for (index = 0; index < FT_UART_NUM_OPITIONS; index++) + { + if ((options & OptionTable[index].Option) == (u32)(0)) + { + continue; + } + + reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); + + /* set specific options */ + reg_value |= OptionTable[index].Mask; + FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); + } +} + +void Pl011ClearSpecificOptions(Pl011 *uart_p, u32 options) +{ + u32 index; + u32 reg_value; + FT_ASSERTVOID(uart_p != NULL); + + for (index = 0; index < FT_UART_NUM_OPITIONS; index++) + { + if ((options & OptionTable[index].Option) == (u32)(0)) + { + continue; + } + + reg_value = FT_UART_READREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset); + + /* remove specific options */ + reg_value &= ~OptionTable[index].Mask; + FT_UART_WRITEREG32(uart_p->config.base_address, OptionTable[index].RegisterOffset, reg_value); + } +} diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.c b/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.c index b31a0e2ed..7cf91d0cd 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_selftest.c @@ -1,13 +1,13 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-04-07 13:44:41 - * @Description:  This files is for uart test cases - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-04-07 13:44:41 + * @Description:  This files is for uart test cases + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ diff --git a/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.c b/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.c index 05aab1f92..a8ff3b2db 100644 --- a/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.c +++ b/bsp/drivers/usart/pl011_uart/pl011_uart_sinit.c @@ -1,41 +1,41 @@ -/* - * @ : Copyright (c) 2021 Phytium Information Technology, Inc. - * - * SPDX-License-Identifier: Apache-2.0. - * - * @Date: 2021-04-07 09:53:07 - * @LastEditTime: 2021-04-07 13:44:56 - * @Description:  This files is for uart static init - * - * @Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#include "pl011_uart.h" -#include "parameters.h" - -extern Pl011Config Pl011ConfigTable[FT_UART_NUM]; - -/** - * @name: Ft_Uart_LookupConfig - * @msg: 获取串口的基本配置 - * @param {u16} instance_id FT_UARTX_ID - * @return {*} - */ -Pl011Config *Pl011LookupConfig(u32 instance_id) -{ - Pl011Config *CfgPtr = NULL; - u32 Index; - - for (Index = 0; Index < (u32)FT_UART_NUM; Index++) - { - if (Pl011ConfigTable[Index].instance_id == instance_id) - { - CfgPtr = &Pl011ConfigTable[Index]; - break; - } - } - - return (Pl011Config *)CfgPtr; -} +/* + * @ : Copyright (c) 2021 Phytium Information Technology, Inc. + * + * SPDX-License-Identifier: Apache-2.0. + * + * @Date: 2021-04-07 09:53:07 + * @LastEditTime: 2021-04-07 13:44:56 + * @Description:  This files is for uart static init + * + * @Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#include "pl011_uart.h" +#include "parameters.h" + +extern Pl011Config Pl011ConfigTable[FT_UART_NUM]; + +/** + * @name: Ft_Uart_LookupConfig + * @msg: 获取串口的基本配置 + * @param {u16} instance_id FT_UARTX_ID + * @return {*} + */ +Pl011Config *Pl011LookupConfig(u32 instance_id) +{ + Pl011Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0; Index < (u32)FT_UART_NUM; Index++) + { + if (Pl011ConfigTable[Index].instance_id == instance_id) + { + CfgPtr = &Pl011ConfigTable[Index]; + break; + } + } + + return (Pl011Config *)CfgPtr; +} diff --git a/configs/aarch32_defconfig b/configs/aarch32_defconfig index 5908f83fd..4ab0bef12 100644 --- a/configs/aarch32_defconfig +++ b/configs/aarch32_defconfig @@ -1,97 +1,97 @@ - -# -# Project Configuration -# - -# -# FT2000-4 AARCH32 Baremetal Configuration -# -CONFIG_TARGET_NAME="ft2004_baremetal" -# end of FT2000-4 AARCH32 Baremetal Configuration -# end of Project Configuration - -# -# Build Target -# -CONFIG_TARGET_ARMV8_AARCH32=y -# CONFIG_TARGET_ARMV8_AARCH64 is not set -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -CONFIG_E2000_FT2004_AARCH32_RAM_LD=y -# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set -# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set -# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -# CONFIG_USE_CACHE is not set -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration + +# +# Project Configuration +# + +# +# FT2000-4 AARCH32 Baremetal Configuration +# +CONFIG_TARGET_NAME="ft2004_baremetal" +# end of FT2000-4 AARCH32 Baremetal Configuration +# end of Project Configuration + +# +# Build Target +# +CONFIG_TARGET_ARMV8_AARCH32=y +# CONFIG_TARGET_ARMV8_AARCH64 is not set +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Build Target + +# +# General Setting +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +CONFIG_E2000_FT2004_AARCH32_RAM_LD=y +# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set +# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set +# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of General Setting + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +# CONFIG_USE_CACHE is not set +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration diff --git a/configs/aarch64_defconfig b/configs/aarch64_defconfig index 6adf3b568..2f36befa1 100644 --- a/configs/aarch64_defconfig +++ b/configs/aarch64_defconfig @@ -1,97 +1,97 @@ - -# -# Build Target -# -# CONFIG_TARGET_ARMV8_AARCH32 is not set -CONFIG_TARGET_ARMV8_AARCH64=y -# CONFIG_TARGET_ARMV7 is not set -CONFIG_TARGET_F2000_4=y -# CONFIG_TARGET_AARCH32_QEMU is not set -# CONFIG_TARGET_AARCH64_QEMU is not set -# CONFIG_TARGET_E2000 is not set -# end of Build Target - -# -# General Setting -# -CONFIG_ENVI_UBUNTU_20_04=y -# CONFIG_ENVI_WINDOWS10_MINGW is not set - -# -# Cross-Compiler Setting -# -CONFIG_COMPILER_NO_STD_STARUP=y -# CONFIG_USE_EXT_COMPILER is not set -# end of Cross-Compiler Setting - -# -# GNU linker -# -# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set -CONFIG_E2000_FT20004_AARCH64_RAM_LD=y -# CONFIG_QEMU_AARCH32_RAM_LD is not set -# end of GNU linker -# end of General Setting - -# -# Board Configuration -# - -# -# Common Configuration -# -# CONFIG_LOG_VERBOS is not set -# CONFIG_LOG_DEBUG is not set -# CONFIG_LOG_INFO is not set -# CONFIG_LOG_WARN is not set -CONFIG_LOG_ERROR=y -# end of Common Configuration - -# -# Components Configuration -# -# CONFIG_USE_SPI is not set -# CONFIG_USE_QSPI is not set -CONFIG_USE_GIC=y - -# -# Gic Configuration -# -CONFIG_EBABLE_GICV3=y -# end of Gic Configuration - -CONFIG_USE_USART=y - -# -# Usart Configuration -# -CONFIG_ENABLE_Pl011_UART=y -# end of Usart Configuration -# end of Components Configuration - -# -# Arch Configuration -# -CONFIG_USE_CACHE=y -CONFIG_USE_L3CACHE=y -CONFIG_USE_MMU=y -# end of Arch Configuration -# end of Board Configuration - -# -# Library Configuration -# -CONFIG_USE_NOSTD_LIBC=y -# CONFIG_USE_LIBC is not set -# end of Library Configuration - -# -# Project Configuration -# - -# -# Baremetal Configuration -# -CONFIG_TARGET_NAME="uart_irq_send" -# end of Baremetal Configuration -# end of Project Configuration + +# +# Build Target +# +# CONFIG_TARGET_ARMV8_AARCH32 is not set +CONFIG_TARGET_ARMV8_AARCH64=y +# CONFIG_TARGET_ARMV7 is not set +CONFIG_TARGET_F2000_4=y +# CONFIG_TARGET_AARCH32_QEMU is not set +# CONFIG_TARGET_AARCH64_QEMU is not set +# CONFIG_TARGET_E2000 is not set +# end of Build Target + +# +# General Setting +# +CONFIG_ENVI_UBUNTU_20_04=y +# CONFIG_ENVI_WINDOWS10_MINGW is not set + +# +# Cross-Compiler Setting +# +CONFIG_COMPILER_NO_STD_STARUP=y +# CONFIG_USE_EXT_COMPILER is not set +# end of Cross-Compiler Setting + +# +# GNU linker +# +# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set +CONFIG_E2000_FT20004_AARCH64_RAM_LD=y +# CONFIG_QEMU_AARCH32_RAM_LD is not set +# end of GNU linker +# end of General Setting + +# +# Board Configuration +# + +# +# Common Configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# end of Common Configuration + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y + +# +# Gic Configuration +# +CONFIG_EBABLE_GICV3=y +# end of Gic Configuration + +CONFIG_USE_USART=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration +# end of Components Configuration + +# +# Arch Configuration +# +CONFIG_USE_CACHE=y +CONFIG_USE_L3CACHE=y +CONFIG_USE_MMU=y +# end of Arch Configuration +# end of Board Configuration + +# +# Library Configuration +# +CONFIG_USE_NOSTD_LIBC=y +# CONFIG_USE_LIBC is not set +# end of Library Configuration + +# +# Project Configuration +# + +# +# Baremetal Configuration +# +CONFIG_TARGET_NAME="uart_irq_send" +# end of Baremetal Configuration +# end of Project Configuration diff --git a/doc/baremetal.dio b/doc/baremetal.dio index 34341657c..216d9fa15 100644 --- a/doc/baremetal.dio +++ b/doc/baremetal.dio @@ -1,109 +1,109 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/export.sh b/export.sh deleted file mode 100644 index 0dc6083c1..000000000 --- a/export.sh +++ /dev/null @@ -1,99 +0,0 @@ -### -### - # @ : Copyright (c) 2020 Phytium Information Technology, Inc.  - #   - # SPDX-License-Identifier: Apache-2.0. - # - # @Date: 2021-06-30 17:24:45 - # @LastEditTime: 2021-07-12 11:35:59 - # @Description:  This files is for  - # - # @Modify History: - #  Ver   Who        Date         Changes - # ----- ------     --------    -------------------------------------- - -#!/bin/sh -# online install would wget cc and install -# offline install need put cc package under folder 'tools' -if [ "$1" = "-online" ]; then - OFFLINE_INSTALL=0 -else - OFFLINE_INSTALL=1 -fi - -# setup u git -git config core.ignorecase false - -# make sure all src file ends with LF -#find . -type f -exec dos2unix {} \; - -# update -##################SET ROOT PATH############## -# profile to save environment variables -PROFILE_PATH=~/.profile - -# get absoulte path of sdk -export SDK_ROOT="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" - -# delete SDK_ROOT if exists -sed -i '/export SDK_ROOT=/d' $PROFILE_PATH -# append SDK_ROOT environment -echo "export SDK_ROOT=$SDK_ROOT" >> $PROFILE_PATH - -###################CHANGE FILE MODE############## -# make sure sdk scripts are executable -chmod +x $SDK_ROOT/*.sh --silent -chmod +x $SDK_ROOT/scripts/*.sh --silent -chmod +x $SDK_ROOT/make/*.mk --silent -chmod +x $SDK_ROOT/tools/Kconfiglib/*.py --silent - -# install gcc compiler -if [ ! -d $SDK_ROOT ]; then - echo "Please set the SDK Root Path first !!!" - exit 1 -fi - -# if define offline install, put aarch32 & aarch64 compiler package under dir tools -AARCH32_URL=https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz -AARCH32_CC_PACK=gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz -AARCH64_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.2-2020.11/binrel/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz -AARCH64_CC_PACK=gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz -INSTALL_PATH=$SDK_ROOT/tools -export AARCH32_CROSS_PATH=$INSTALL_PATH/gcc-arm-none-eabi-phytium-major -export AARCH64_CROSS_PATH=$INSTALL_PATH/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf - -if [ $OFFLINE_INSTALL -ne 1 ]; then -# do not download if package exists - [ ! -d $AARCH32_CROSS_PATH ] && [ ! -f $INSTALL_PATH/$AARCH32_CC_PACK ] && wget -P $INSTALL_PATH/ $AARCH32_URL - [ ! -d $AARCH64_CROSS_PATH ] && [ ! -f $INSTALL_PATH/$AARCH64_CC_PACK ] && wget -P $INSTALL_PATH/ $AARCH64_URL -fi - -if [ ! -f $INSTALL_PATH/$AARCH32_CC_PACK ] || [ ! -f $INSTALL_PATH/$AARCH64_CC_PACK ]; then - echo "Gcc compiler package non found !!!"$INSTALL_PATH/$AARCH64_CC_PACK - exit 1 -fi - -##################SET COMPILER PATH############## -## AARCH32 CC -[ ! -d $AARCH32_CROSS_PATH ] && sudo tar -C $INSTALL_PATH/ -jxvf $INSTALL_PATH/$AARCH32_CC_PACK -sed -i '/export AARCH32_CROSS_PATH=/d' $PROFILE_PATH -sed -i '/export PATH=\$PATH:\$AARCH32_CROSS_PATH/d' $PROFILE_PATH -echo "export AARCH32_CROSS_PATH=$AARCH32_CROSS_PATH" >> $PROFILE_PATH -echo "export PATH=\$PATH:\$AARCH32_CROSS_PATH/bin">> $PROFILE_PATH - -## AARCH64 CC -[ ! -d $AARCH64_CROSS_PATH ] && sudo tar -C $INSTALL_PATH/ -vxf $INSTALL_PATH/$AARCH64_CC_PACK -sed -i '/export AARCH64_CROSS_PATH=/d' $PROFILE_PATH -sed -i '/export PATH=\$PATH:\$AARCH64_CROSS_PATH/d' $PROFILE_PATH -echo "export AARCH64_CROSS_PATH=$AARCH64_CROSS_PATH" >> $PROFILE_PATH -echo "export PATH=\$PATH:\$AARCH64_CROSS_PATH/bin">> $PROFILE_PATH - -##################Show msg, Make Environment Variables works####### -source $PROFILE_PATH - -echo "Please type in 'source ./export.sh'" -echo "Phytium Embedded SDK Setup Done!!" -echo "Install AARCH32 Compiler at " $AARCH32_CROSS_PATH -echo "Install AARCH64 Compiler at " $AARCH64_CROSS_PATH -echo "Install AARCH32 Linux Compiler at " $AARCH32_LINUX_CROSS_PATH -echo "SDK Path is set as "$SDK_ROOT \ No newline at end of file diff --git a/install.sh b/install.sh index 3acfa4411..a650c5b98 100644 --- a/install.sh +++ b/install.sh @@ -5,7 +5,7 @@ # SPDX-License-Identifier: Apache-2.0. # # @Date: 2021-06-30 17:24:45 - # @LastEditTime: 2021-07-12 13:59:49 + # @LastEditTime: 2021-07-13 14:08:11 # @Description:  This files is for  # # @Modify History: diff --git a/lib/Kconfig b/lib/Kconfig index b0c13b7f4..b9fc7c26b 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1,15 +1,15 @@ -menu "Library Configuration" - - choice - prompt "Select use libc or nostdlib" - default USE_NOSTD_LIBC - - config USE_NOSTD_LIBC - bool "Use C Non Standard Library" - - config USE_LIBC - bool "Use C Standard Library" - - endchoice - -endmenu +menu "Library Configuration" + + choice + prompt "Select use libc or nostdlib" + default USE_NOSTD_LIBC + + config USE_NOSTD_LIBC + bool "Use C Non Standard Library" + + config USE_LIBC + bool "Use C Standard Library" + + endchoice + +endmenu diff --git a/lib/Kconfiglib/.config b/lib/Kconfiglib/.config index 737f5d25d..98d5e0d99 100644 --- a/lib/Kconfiglib/.config +++ b/lib/Kconfiglib/.config @@ -1,34 +1,34 @@ -CONFIG_MODULES=y - -# -# Bool and tristate symbols -# -CONFIG_BOOL=y -# CONFIG_BOOL_DEP is not set -# CONFIG_TRI_DEP is not set -# CONFIG_TWO_MENU_NODES is not set -# CONFIG_TRI is not set - -# -# These are selected by TRI_DEP -# -# CONFIG_SELECTED_BY_TRI_DEP is not set -# CONFIG_IMPLIED_BY_TRI_DEP is not set -# end of Bool and tristate symbols - -# -# String, int, and hex symbols -# -CONFIG_STRING="foo" -CONFIG_INT=747 -CONFIG_HEX=0xABC -# end of String, int, and hex symbols - -# -# Various choices -# -CONFIG_BOOL_CHOICE_SYM_1=y -# CONFIG_BOOL_CHOICE_SYM_2 is not set -# CONFIG_TRI_CHOICE_SYM_1 is not set -# CONFIG_TRI_CHOICE_SYM_2 is not set -# end of Various choices +CONFIG_MODULES=y + +# +# Bool and tristate symbols +# +CONFIG_BOOL=y +# CONFIG_BOOL_DEP is not set +# CONFIG_TRI_DEP is not set +# CONFIG_TWO_MENU_NODES is not set +# CONFIG_TRI is not set + +# +# These are selected by TRI_DEP +# +# CONFIG_SELECTED_BY_TRI_DEP is not set +# CONFIG_IMPLIED_BY_TRI_DEP is not set +# end of Bool and tristate symbols + +# +# String, int, and hex symbols +# +CONFIG_STRING="foo" +CONFIG_INT=747 +CONFIG_HEX=0xABC +# end of String, int, and hex symbols + +# +# Various choices +# +CONFIG_BOOL_CHOICE_SYM_1=y +# CONFIG_BOOL_CHOICE_SYM_2 is not set +# CONFIG_TRI_CHOICE_SYM_1 is not set +# CONFIG_TRI_CHOICE_SYM_2 is not set +# end of Various choices diff --git a/lib/Kconfiglib/.gitignore b/lib/Kconfiglib/.gitignore index 4a18d79f0..91a35a00f 100644 --- a/lib/Kconfiglib/.gitignore +++ b/lib/Kconfiglib/.gitignore @@ -1,4 +1,4 @@ -*.py[co] -build/ -*.egg-info/ -dist/ +*.py[co] +build/ +*.egg-info/ +dist/ diff --git a/lib/Kconfiglib/Kconfig b/lib/Kconfiglib/Kconfig index f1cb67bd4..c5eba7be0 100644 --- a/lib/Kconfiglib/Kconfig +++ b/lib/Kconfiglib/Kconfig @@ -1,102 +1,102 @@ -mainmenu "Example Kconfig configuration" - -config MODULES - bool "Enable loadable module support" - option modules - default y - -menu "Bool and tristate symbols" - -config BOOL - bool "Bool symbol" - default y - -config BOOL_DEP - bool "Dependent bool symbol" - depends on BOOL - -# Mix it up a bit with an 'if' instead of a 'depends on' -if BOOL - -config TRI_DEP - tristate "Dependent tristate symbol" - select SELECTED_BY_TRI_DEP - imply IMPLIED_BY_TRI_DEP - -endif - -config TWO_MENU_NODES - bool "First prompt" - depends on BOOL - -config TRI - tristate "Tristate symbol" - -config TWO_MENU_NODES - bool "Second prompt" - -comment "These are selected by TRI_DEP" - -config SELECTED_BY_TRI_DEP - tristate "Tristate selected by TRI_DEP" - -config IMPLIED_BY_TRI_DEP - tristate "Tristate implied by TRI_DEP" - -endmenu - - -menu "String, int, and hex symbols" - -config STRING - string "String symbol" - default "foo" - -config INT - int "Int symbol" - default 747 - -config HEX - hex "Hex symbol" - default 0xABC - -endmenu - - -menu "Various choices" - -choice BOOL_CHOICE - bool "Bool choice" - -config BOOL_CHOICE_SYM_1 - bool "Bool choice sym 1" - -config BOOL_CHOICE_SYM_2 - bool "Bool choice sym 2" - -endchoice - -choice TRI_CHOICE - tristate "Tristate choice" - -config TRI_CHOICE_SYM_1 - tristate "Tristate choice sym 1" - -config TRI_CHOICE_SYM_2 - tristate "Tristate choice sym 2" - -endchoice - -choice OPT_BOOL_CHOICE - bool "Optional bool choice" - optional - -config OPT_BOOL_CHOICE_SYM_1 - bool "Optional bool choice sym 1" - -config OPT_BOOL_CHOICE_SYM_2 - bool "Optional bool choice sym 2" - -endchoice - -endmenu +mainmenu "Example Kconfig configuration" + +config MODULES + bool "Enable loadable module support" + option modules + default y + +menu "Bool and tristate symbols" + +config BOOL + bool "Bool symbol" + default y + +config BOOL_DEP + bool "Dependent bool symbol" + depends on BOOL + +# Mix it up a bit with an 'if' instead of a 'depends on' +if BOOL + +config TRI_DEP + tristate "Dependent tristate symbol" + select SELECTED_BY_TRI_DEP + imply IMPLIED_BY_TRI_DEP + +endif + +config TWO_MENU_NODES + bool "First prompt" + depends on BOOL + +config TRI + tristate "Tristate symbol" + +config TWO_MENU_NODES + bool "Second prompt" + +comment "These are selected by TRI_DEP" + +config SELECTED_BY_TRI_DEP + tristate "Tristate selected by TRI_DEP" + +config IMPLIED_BY_TRI_DEP + tristate "Tristate implied by TRI_DEP" + +endmenu + + +menu "String, int, and hex symbols" + +config STRING + string "String symbol" + default "foo" + +config INT + int "Int symbol" + default 747 + +config HEX + hex "Hex symbol" + default 0xABC + +endmenu + + +menu "Various choices" + +choice BOOL_CHOICE + bool "Bool choice" + +config BOOL_CHOICE_SYM_1 + bool "Bool choice sym 1" + +config BOOL_CHOICE_SYM_2 + bool "Bool choice sym 2" + +endchoice + +choice TRI_CHOICE + tristate "Tristate choice" + +config TRI_CHOICE_SYM_1 + tristate "Tristate choice sym 1" + +config TRI_CHOICE_SYM_2 + tristate "Tristate choice sym 2" + +endchoice + +choice OPT_BOOL_CHOICE + bool "Optional bool choice" + optional + +config OPT_BOOL_CHOICE_SYM_1 + bool "Optional bool choice sym 1" + +config OPT_BOOL_CHOICE_SYM_2 + bool "Optional bool choice sym 2" + +endchoice + +endmenu diff --git a/lib/Kconfiglib/LICENSE.txt b/lib/Kconfiglib/LICENSE.txt index 8b31efca2..b76995320 100644 --- a/lib/Kconfiglib/LICENSE.txt +++ b/lib/Kconfiglib/LICENSE.txt @@ -1,5 +1,5 @@ -Copyright (c) 2011-2019, Ulf Magnusson - -Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. - -THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +Copyright (c) 2011-2019, Ulf Magnusson + +Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. diff --git a/lib/Kconfiglib/defconfig.py b/lib/Kconfiglib/defconfig.py index b1792731f..9a179fa7b 100644 --- a/lib/Kconfiglib/defconfig.py +++ b/lib/Kconfiglib/defconfig.py @@ -1,43 +1,43 @@ -#!/usr/bin/env python3 - -# Copyright (c) 2019, Ulf Magnusson -# SPDX-License-Identifier: ISC - -""" -Reads a specified configuration file, then writes a new configuration file. -This can be used to initialize the configuration from e.g. an arch-specific -configuration file. This input configuration file would usually be a minimal -configuration file, as generated by e.g. savedefconfig. - -The default output filename is '.config'. A different filename can be passed in -the KCONFIG_CONFIG environment variable. -""" -import argparse - -import kconfiglib - - -def main(): - parser = argparse.ArgumentParser( - formatter_class=argparse.RawDescriptionHelpFormatter, - description=__doc__) - - parser.add_argument( - "--kconfig", - default="Kconfig", - help="Top-level Kconfig file (default: Kconfig)") - - parser.add_argument( - "config", - metavar="CONFIGURATION", - help="Input configuration file") - - args = parser.parse_args() - - kconf = kconfiglib.Kconfig(args.kconfig, suppress_traceback=True) - print(kconf.load_config(args.config)) - print(kconf.write_config()) - - -if __name__ == "__main__": - main() +#!/usr/bin/env python3 + +# Copyright (c) 2019, Ulf Magnusson +# SPDX-License-Identifier: ISC + +""" +Reads a specified configuration file, then writes a new configuration file. +This can be used to initialize the configuration from e.g. an arch-specific +configuration file. This input configuration file would usually be a minimal +configuration file, as generated by e.g. savedefconfig. + +The default output filename is '.config'. A different filename can be passed in +the KCONFIG_CONFIG environment variable. +""" +import argparse + +import kconfiglib + + +def main(): + parser = argparse.ArgumentParser( + formatter_class=argparse.RawDescriptionHelpFormatter, + description=__doc__) + + parser.add_argument( + "--kconfig", + default="Kconfig", + help="Top-level Kconfig file (default: Kconfig)") + + parser.add_argument( + "config", + metavar="CONFIGURATION", + help="Input configuration file") + + args = parser.parse_args() + + kconf = kconfiglib.Kconfig(args.kconfig, suppress_traceback=True) + print(kconf.load_config(args.config)) + print(kconf.write_config()) + + +if __name__ == "__main__": + main() diff --git a/lib/Kconfiglib/genconfig.py b/lib/Kconfiglib/genconfig.py index cfe93606b..6eb3a35ba 100644 --- a/lib/Kconfiglib/genconfig.py +++ b/lib/Kconfiglib/genconfig.py @@ -1,221 +1,221 @@ -#!/usr/bin/env python3 - -# Copyright (c) 2018-2019, Ulf Magnusson -# SPDX-License-Identifier: ISC - -""" -Generates a header file with #defines from the configuration, matching the -format of include/generated/autoconf.h in the Linux kernel. - -Optionally, also writes the configuration output as a .config file. See ---config-out. - -The --sync-deps, --file-list, and --env-list options generate information that -can be used to avoid needless rebuilds/reconfigurations. - -Before writing a header or configuration file, Kconfiglib compares the old -contents of the file against the new contents. If there's no change, the write -is skipped. This avoids updating file metadata like the modification time, and -might save work depending on your build setup. - -By default, the configuration is generated from '.config'. A different -configuration file can be passed in the KCONFIG_CONFIG environment variable. - -A custom header string can be inserted at the beginning of generated -configuration and header files by setting the KCONFIG_CONFIG_HEADER and -KCONFIG_AUTOHEADER_HEADER environment variables, respectively (this also works -for other scripts). The string is not automatically made a comment (this is by -design, to allow anything to be added), and no trailing newline is added, so -add '/* */', '#', and newlines as appropriate. - -See https://www.gnu.org/software/make/manual/make.html#Multi_002dLine for a -handy way to define multi-line variables in makefiles, for use with custom -headers. Remember to export the variable to the environment. -""" -import argparse -import os -import sys -import re - -import kconfiglib - - -DEFAULT_SYNC_DEPS_PATH = "deps/" - -def is_pkg_special_config(config_str): - ''' judge if it's CONFIG_PKG_XX_PATH or CONFIG_PKG_XX_VER''' - - if type(config_str) == type('a'): - if config_str.startswith("PKG_") and (config_str.endswith('_PATH') or config_str.endswith('_VER')): - return True - return False - - -def mk_sdkconfig(filename): - try: - config = open(filename, 'r') - except: - print('open config:%s failed' % filename) - return - - sdkconfig = open('sdkconfig.h', 'w') - sdkconfig.write('#ifndef SDK_CONFIG_H__\n') - sdkconfig.write('#define SDK_CONFIG_H__\n\n') - - empty_line = 1 - - for line in config: - line = line.lstrip(' ').replace('\n', '').replace('\r', '') - - if len(line) == 0: - continue - - if line[0] == '#': - if len(line) == 1: - if empty_line: - continue - - sdkconfig.write('\n') - empty_line = 1 - continue - - # if line.startswith('# CONFIG_'): - # line = ' ' + line[9:] - # else: - line = line[1:] - sdkconfig.write('/*%s */\n' % line) - - empty_line = 0 - else: - empty_line = 0 - setting = line.split('=') - if len(setting) >= 2: - # if setting[0].startswith('CONFIG_'): - # setting[0] = setting[0][7:] - - # remove CONFIG_PKG_XX_PATH or CONFIG_PKG_XX_VER - if is_pkg_special_config(setting[0]): - continue - - if setting[1] == 'y': - sdkconfig.write('#define %s\n' % setting[0]) - else: - sdkconfig.write('#define %s %s\n' % (setting[0], re.findall(r"^.*?=(.*)$",line)[0])) - - if os.path.isfile('sdkconfig_project.h'): - sdkconfig.write('#include "sdkconfig_project.h"\n') - - sdkconfig.write('\n') - sdkconfig.write('#endif\n') - sdkconfig.close() - -def main(): - parser = argparse.ArgumentParser( - formatter_class=argparse.RawDescriptionHelpFormatter, - description=__doc__) - - parser.add_argument( - "--header-path", - metavar="HEADER_FILE", - help=""" -Path to write the generated header file to. If not specified, the path in the -environment variable KCONFIG_AUTOHEADER is used if it is set, and 'config.h' -otherwise. -""") - - parser.add_argument( - "--config-out", - metavar="CONFIG_FILE", - help=""" -Write the configuration to CONFIG_FILE. This is useful if you include .config -files in Makefiles, as the generated configuration file will be a full .config -file even if .config is outdated. The generated configuration matches what -olddefconfig would produce. If you use sync-deps, you can include -deps/auto.conf instead. --config-out is meant for cases where incremental build -information isn't needed. -""") - - parser.add_argument( - "--sync-deps", - metavar="OUTPUT_DIR", - nargs="?", - const=DEFAULT_SYNC_DEPS_PATH, - help=""" -Enable generation of symbol dependency information for incremental builds, -optionally specifying the output directory (default: {}). See the docstring of -Kconfig.sync_deps() in Kconfiglib for more information. -""".format(DEFAULT_SYNC_DEPS_PATH)) - - parser.add_argument( - "--file-list", - metavar="OUTPUT_FILE", - help=""" -Write a list of all Kconfig files to OUTPUT_FILE, with one file per line. The -paths are relative to $srctree (or to the current directory if $srctree is -unset). Files appear in the order they're 'source'd. -""") - - parser.add_argument( - "--env-list", - metavar="OUTPUT_FILE", - help=""" -Write a list of all environment variables referenced in Kconfig files to -OUTPUT_FILE, with one variable per line. Each line has the format NAME=VALUE. -Only environment variables referenced with the preprocessor $(VAR) syntax are -included, and not variables referenced with the older $VAR syntax (which is -only supported for backwards compatibility). -""") - - parser.add_argument( - "kconfig", - metavar="KCONFIG", - nargs="?", - default="Kconfig", - help="Top-level Kconfig file (default: Kconfig)") - - args = parser.parse_args() - - - kconf = kconfiglib.Kconfig(args.kconfig, suppress_traceback=True) - kconf.load_config() - - if args.header_path is None: - if "KCONFIG_AUTOHEADER" in os.environ: - kconf.write_autoconf() - else: - # Kconfiglib defaults to include/generated/autoconf.h to be - # compatible with the C tools. 'config.h' is used here instead for - # backwards compatibility. It's probably a saner default for tools - # as well. - kconf.write_autoconf("sdkconfig.h") - else: - kconf.write_autoconf(args.header_path) - - if args.config_out is not None: - kconf.write_config(args.config_out, save_old=False) - - if args.sync_deps is not None: - kconf.sync_deps(args.sync_deps) - - if args.file_list is not None: - with _open_write(args.file_list) as f: - for path in kconf.kconfig_filenames: - f.write(path + "\n") - - if args.env_list is not None: - with _open_write(args.env_list) as f: - for env_var in kconf.env_vars: - f.write("{}={}\n".format(env_var, os.environ[env_var])) - mk_sdkconfig('sdkconfig') - -def _open_write(path): - # Python 2/3 compatibility. io.open() is available on both, but makes - # write() expect 'unicode' strings on Python 2. - - if sys.version_info[0] < 3: - return open(path, "w") - return open(path, "w", encoding="utf-8") - - -if __name__ == "__main__": - main() +#!/usr/bin/env python3 + +# Copyright (c) 2018-2019, Ulf Magnusson +# SPDX-License-Identifier: ISC + +""" +Generates a header file with #defines from the configuration, matching the +format of include/generated/autoconf.h in the Linux kernel. + +Optionally, also writes the configuration output as a .config file. See +--config-out. + +The --sync-deps, --file-list, and --env-list options generate information that +can be used to avoid needless rebuilds/reconfigurations. + +Before writing a header or configuration file, Kconfiglib compares the old +contents of the file against the new contents. If there's no change, the write +is skipped. This avoids updating file metadata like the modification time, and +might save work depending on your build setup. + +By default, the configuration is generated from '.config'. A different +configuration file can be passed in the KCONFIG_CONFIG environment variable. + +A custom header string can be inserted at the beginning of generated +configuration and header files by setting the KCONFIG_CONFIG_HEADER and +KCONFIG_AUTOHEADER_HEADER environment variables, respectively (this also works +for other scripts). The string is not automatically made a comment (this is by +design, to allow anything to be added), and no trailing newline is added, so +add '/* */', '#', and newlines as appropriate. + +See https://www.gnu.org/software/make/manual/make.html#Multi_002dLine for a +handy way to define multi-line variables in makefiles, for use with custom +headers. Remember to export the variable to the environment. +""" +import argparse +import os +import sys +import re + +import kconfiglib + + +DEFAULT_SYNC_DEPS_PATH = "deps/" + +def is_pkg_special_config(config_str): + ''' judge if it's CONFIG_PKG_XX_PATH or CONFIG_PKG_XX_VER''' + + if type(config_str) == type('a'): + if config_str.startswith("PKG_") and (config_str.endswith('_PATH') or config_str.endswith('_VER')): + return True + return False + + +def mk_sdkconfig(filename): + try: + config = open(filename, 'r') + except: + print('open config:%s failed' % filename) + return + + sdkconfig = open('sdkconfig.h', 'w') + sdkconfig.write('#ifndef SDK_CONFIG_H__\n') + sdkconfig.write('#define SDK_CONFIG_H__\n\n') + + empty_line = 1 + + for line in config: + line = line.lstrip(' ').replace('\n', '').replace('\r', '') + + if len(line) == 0: + continue + + if line[0] == '#': + if len(line) == 1: + if empty_line: + continue + + sdkconfig.write('\n') + empty_line = 1 + continue + + # if line.startswith('# CONFIG_'): + # line = ' ' + line[9:] + # else: + line = line[1:] + sdkconfig.write('/*%s */\n' % line) + + empty_line = 0 + else: + empty_line = 0 + setting = line.split('=') + if len(setting) >= 2: + # if setting[0].startswith('CONFIG_'): + # setting[0] = setting[0][7:] + + # remove CONFIG_PKG_XX_PATH or CONFIG_PKG_XX_VER + if is_pkg_special_config(setting[0]): + continue + + if setting[1] == 'y': + sdkconfig.write('#define %s\n' % setting[0]) + else: + sdkconfig.write('#define %s %s\n' % (setting[0], re.findall(r"^.*?=(.*)$",line)[0])) + + if os.path.isfile('sdkconfig_project.h'): + sdkconfig.write('#include "sdkconfig_project.h"\n') + + sdkconfig.write('\n') + sdkconfig.write('#endif\n') + sdkconfig.close() + +def main(): + parser = argparse.ArgumentParser( + formatter_class=argparse.RawDescriptionHelpFormatter, + description=__doc__) + + parser.add_argument( + "--header-path", + metavar="HEADER_FILE", + help=""" +Path to write the generated header file to. If not specified, the path in the +environment variable KCONFIG_AUTOHEADER is used if it is set, and 'config.h' +otherwise. +""") + + parser.add_argument( + "--config-out", + metavar="CONFIG_FILE", + help=""" +Write the configuration to CONFIG_FILE. This is useful if you include .config +files in Makefiles, as the generated configuration file will be a full .config +file even if .config is outdated. The generated configuration matches what +olddefconfig would produce. If you use sync-deps, you can include +deps/auto.conf instead. --config-out is meant for cases where incremental build +information isn't needed. +""") + + parser.add_argument( + "--sync-deps", + metavar="OUTPUT_DIR", + nargs="?", + const=DEFAULT_SYNC_DEPS_PATH, + help=""" +Enable generation of symbol dependency information for incremental builds, +optionally specifying the output directory (default: {}). See the docstring of +Kconfig.sync_deps() in Kconfiglib for more information. +""".format(DEFAULT_SYNC_DEPS_PATH)) + + parser.add_argument( + "--file-list", + metavar="OUTPUT_FILE", + help=""" +Write a list of all Kconfig files to OUTPUT_FILE, with one file per line. The +paths are relative to $srctree (or to the current directory if $srctree is +unset). Files appear in the order they're 'source'd. +""") + + parser.add_argument( + "--env-list", + metavar="OUTPUT_FILE", + help=""" +Write a list of all environment variables referenced in Kconfig files to +OUTPUT_FILE, with one variable per line. Each line has the format NAME=VALUE. +Only environment variables referenced with the preprocessor $(VAR) syntax are +included, and not variables referenced with the older $VAR syntax (which is +only supported for backwards compatibility). +""") + + parser.add_argument( + "kconfig", + metavar="KCONFIG", + nargs="?", + default="Kconfig", + help="Top-level Kconfig file (default: Kconfig)") + + args = parser.parse_args() + + + kconf = kconfiglib.Kconfig(args.kconfig, suppress_traceback=True) + kconf.load_config() + + if args.header_path is None: + if "KCONFIG_AUTOHEADER" in os.environ: + kconf.write_autoconf() + else: + # Kconfiglib defaults to include/generated/autoconf.h to be + # compatible with the C tools. 'config.h' is used here instead for + # backwards compatibility. It's probably a saner default for tools + # as well. + kconf.write_autoconf("sdkconfig.h") + else: + kconf.write_autoconf(args.header_path) + + if args.config_out is not None: + kconf.write_config(args.config_out, save_old=False) + + if args.sync_deps is not None: + kconf.sync_deps(args.sync_deps) + + if args.file_list is not None: + with _open_write(args.file_list) as f: + for path in kconf.kconfig_filenames: + f.write(path + "\n") + + if args.env_list is not None: + with _open_write(args.env_list) as f: + for env_var in kconf.env_vars: + f.write("{}={}\n".format(env_var, os.environ[env_var])) + mk_sdkconfig('sdkconfig') + +def _open_write(path): + # Python 2/3 compatibility. io.open() is available on both, but makes + # write() expect 'unicode' strings on Python 2. + + if sys.version_info[0] < 3: + return open(path, "w") + return open(path, "w", encoding="utf-8") + + +if __name__ == "__main__": + main() diff --git a/lib/Kconfiglib/kconfiglib.py b/lib/Kconfiglib/kconfiglib.py index c67895ced..c6bffe24a 100644 --- a/lib/Kconfiglib/kconfiglib.py +++ b/lib/Kconfiglib/kconfiglib.py @@ -1,7160 +1,7160 @@ -# Copyright (c) 2011-2019, Ulf Magnusson -# SPDX-License-Identifier: ISC - -""" -Overview -======== - -Kconfiglib is a Python 2/3 library for scripting and extracting information -from Kconfig (https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt) -configuration systems. - -See the homepage at https://github.com/ulfalizer/Kconfiglib for a longer -overview. - -Since Kconfiglib 12.0.0, the library version is available in -kconfiglib.VERSION, which is a (, , ) tuple, e.g. -(12, 0, 0). - - -Using Kconfiglib on the Linux kernel with the Makefile targets -============================================================== - -For the Linux kernel, a handy interface is provided by the -scripts/kconfig/Makefile patch, which can be applied with either 'git am' or -the 'patch' utility: - - $ wget -qO- https://raw.githubusercontent.com/ulfalizer/Kconfiglib/master/makefile.patch | git am - $ wget -qO- https://raw.githubusercontent.com/ulfalizer/Kconfiglib/master/makefile.patch | patch -p1 - -Warning: Not passing -p1 to patch will cause the wrong file to be patched. - -Please tell me if the patch does not apply. It should be trivial to apply -manually, as it's just a block of text that needs to be inserted near the other -*conf: targets in scripts/kconfig/Makefile. - -Look further down for a motivation for the Makefile patch and for instructions -on how you can use Kconfiglib without it. - -If you do not wish to install Kconfiglib via pip, the Makefile patch is set up -so that you can also just clone Kconfiglib into the kernel root: - - $ git clone git://github.com/ulfalizer/Kconfiglib.git - $ git am Kconfiglib/makefile.patch (or 'patch -p1 < Kconfiglib/makefile.patch') - -Warning: The directory name Kconfiglib/ is significant in this case, because -it's added to PYTHONPATH by the new targets in makefile.patch. - -The targets added by the Makefile patch are described in the following -sections. - - -make kmenuconfig ----------------- - -This target runs the curses menuconfig interface with Python 3. As of -Kconfiglib 12.2.0, both Python 2 and Python 3 are supported (previously, only -Python 3 was supported, so this was a backport). - - -make guiconfig --------------- - -This target runs the Tkinter menuconfig interface. Both Python 2 and Python 3 -are supported. To change the Python interpreter used, pass -PYTHONCMD= to 'make'. The default is 'python'. - - -make [ARCH=] iscriptconfig --------------------------------- - -This target gives an interactive Python prompt where a Kconfig instance has -been preloaded and is available in 'kconf'. To change the Python interpreter -used, pass PYTHONCMD= to 'make'. The default is 'python'. - -To get a feel for the API, try evaluating and printing the symbols in -kconf.defined_syms, and explore the MenuNode menu tree starting at -kconf.top_node by following 'next' and 'list' pointers. - -The item contained in a menu node is found in MenuNode.item (note that this can -be one of the constants kconfiglib.MENU and kconfiglib.COMMENT), and all -symbols and choices have a 'nodes' attribute containing their menu nodes -(usually only one). Printing a menu node will print its item, in Kconfig -format. - -If you want to look up a symbol by name, use the kconf.syms dictionary. - - -make scriptconfig SCRIPT=