+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 ((q31_t)(0x100))
+#define DELTA_Q15 ((q15_t)0x5)
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macros for complex numbers
+ */
+
+ /* Dimension C vector space */
+ #define CMPLX_DIM 2
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief vector types
+ */
+#if defined(ARM_MATH_NEON) || defined (ARM_MATH_MVEI)
+ /**
+ * @brief 64-bit fractional 128-bit vector data type in 1.63 format
+ */
+ typedef int64x2_t q63x2_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector data type in 1.31 format.
+ */
+ typedef int32x4_t q31x4_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector data type with 16-bit alignement in 1.15 format.
+ */
+ typedef __ALIGNED(2) int16x8_t q15x8_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector data type with 8-bit alignement in 1.7 format.
+ */
+ typedef __ALIGNED(1) int8x16_t q7x16_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format.
+ */
+ typedef int32x4x2_t q31x4x2_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format.
+ */
+ typedef int32x4x4_t q31x4x4_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format.
+ */
+ typedef int16x8x2_t q15x8x2_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format.
+ */
+ typedef int16x8x4_t q15x8x4_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format.
+ */
+ typedef int8x16x2_t q7x16x2_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format.
+ */
+ typedef int8x16x4_t q7x16x4_t;
+
+ /**
+ * @brief 32-bit fractional data type in 9.23 format.
+ */
+ typedef int32_t q23_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector data type in 9.23 format.
+ */
+ typedef int32x4_t q23x4_t;
+
+ /**
+ * @brief 64-bit status 128-bit vector data type.
+ */
+ typedef int64x2_t status64x2_t;
+
+ /**
+ * @brief 32-bit status 128-bit vector data type.
+ */
+ typedef int32x4_t status32x4_t;
+
+ /**
+ * @brief 16-bit status 128-bit vector data type.
+ */
+ typedef int16x8_t status16x8_t;
+
+ /**
+ * @brief 8-bit status 128-bit vector data type.
+ */
+ typedef int8x16_t status8x16_t;
+
+
+#endif
+
+#if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/
+ /**
+ * @brief 32-bit floating-point 128-bit vector type
+ */
+ typedef float32x4_t f32x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 128-bit vector data type
+ */
+ typedef __ALIGNED(2) float16x8_t f16x8_t;
+#endif
+
+ /**
+ * @brief 32-bit floating-point 128-bit vector pair data type
+ */
+ typedef float32x4x2_t f32x4x2_t;
+
+ /**
+ * @brief 32-bit floating-point 128-bit vector quadruplet data type
+ */
+ typedef float32x4x4_t f32x4x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 128-bit vector pair data type
+ */
+ typedef float16x8x2_t f16x8x2_t;
+
+ /**
+ * @brief 16-bit floating-point 128-bit vector quadruplet data type
+ */
+ typedef float16x8x4_t f16x8x4_t;
+#endif
+
+ /**
+ * @brief 32-bit ubiquitous 128-bit vector data type
+ */
+ typedef union _any32x4_t
+ {
+ float32x4_t f;
+ int32x4_t i;
+ } any32x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit ubiquitous 128-bit vector data type
+ */
+ typedef union _any16x8_t
+ {
+ float16x8_t f;
+ int16x8_t i;
+ } any16x8_t;
+#endif
+
+#endif
+
+#if defined(ARM_MATH_NEON)
+ /**
+ * @brief 32-bit fractional 64-bit vector data type in 1.31 format.
+ */
+ typedef int32x2_t q31x2_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector data type in 1.15 format.
+ */
+ typedef __ALIGNED(2) int16x4_t q15x4_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector data type in 1.7 format.
+ */
+ typedef __ALIGNED(1) int8x8_t q7x8_t;
+
+ /**
+ * @brief 32-bit float 64-bit vector data type.
+ */
+ typedef float32x2_t f32x2_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit float 64-bit vector data type.
+ */
+ typedef __ALIGNED(2) float16x4_t f16x4_t;
+#endif
+
+ /**
+ * @brief 32-bit floating-point 128-bit vector triplet data type
+ */
+ typedef float32x4x3_t f32x4x3_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 128-bit vector triplet data type
+ */
+ typedef float16x8x3_t f16x8x3_t;
+#endif
+
+ /**
+ * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format
+ */
+ typedef int32x4x3_t q31x4x3_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format
+ */
+ typedef int16x8x3_t q15x8x3_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format
+ */
+ typedef int8x16x3_t q7x16x3_t;
+
+ /**
+ * @brief 32-bit floating-point 64-bit vector pair data type
+ */
+ typedef float32x2x2_t f32x2x2_t;
+
+ /**
+ * @brief 32-bit floating-point 64-bit vector triplet data type
+ */
+ typedef float32x2x3_t f32x2x3_t;
+
+ /**
+ * @brief 32-bit floating-point 64-bit vector quadruplet data type
+ */
+ typedef float32x2x4_t f32x2x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 64-bit vector pair data type
+ */
+ typedef float16x4x2_t f16x4x2_t;
+
+ /**
+ * @brief 16-bit floating-point 64-bit vector triplet data type
+ */
+ typedef float16x4x3_t f16x4x3_t;
+
+ /**
+ * @brief 16-bit floating-point 64-bit vector quadruplet data type
+ */
+ typedef float16x4x4_t f16x4x4_t;
+#endif
+
+ /**
+ * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format
+ */
+ typedef int32x2x2_t q31x2x2_t;
+
+ /**
+ * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format
+ */
+ typedef int32x2x3_t q31x2x3_t;
+
+ /**
+ * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format
+ */
+ typedef int32x4x3_t q31x2x4_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format
+ */
+ typedef int16x4x2_t q15x4x2_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format
+ */
+ typedef int16x4x2_t q15x4x3_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format
+ */
+ typedef int16x4x3_t q15x4x4_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format
+ */
+ typedef int8x8x2_t q7x8x2_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format
+ */
+ typedef int8x8x3_t q7x8x3_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format
+ */
+ typedef int8x8x4_t q7x8x4_t;
+
+ /**
+ * @brief 32-bit ubiquitous 64-bit vector data type
+ */
+ typedef union _any32x2_t
+ {
+ float32x2_t f;
+ int32x2_t i;
+ } any32x2_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit ubiquitous 64-bit vector data type
+ */
+ typedef union _any16x4_t
+ {
+ float16x4_t f;
+ int16x4_t i;
+ } any16x4_t;
+#endif
+
+ /**
+ * @brief 32-bit status 64-bit vector data type.
+ */
+ typedef int32x4_t status32x2_t;
+
+ /**
+ * @brief 16-bit status 64-bit vector data type.
+ */
+ typedef int16x8_t status16x4_t;
+
+ /**
+ * @brief 8-bit status 64-bit vector data type.
+ */
+ typedef int8x16_t status8x8_t;
+
+#endif
+
+
+
+/**
+ @brief definition to read/write two 16 bit values.
+ @deprecated
+ */
+#if defined ( __CC_ARM )
+ #define __SIMD32_TYPE int32_t __packed
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __GNUC__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __ICCARM__ )
+ #define __SIMD32_TYPE int32_t __packed
+#elif defined ( __TI_ARM__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __CSMC__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __TASKING__ )
+ #define __SIMD32_TYPE __un(aligned) int32_t
+#elif defined(_MSC_VER )
+ #define __SIMD32_TYPE int32_t
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
+#define __SIMD64(addr) (*( int64_t **) & (addr))
+
+#define STEP(x) (x) <= 0 ? 0 : 1
+#define SQ(x) ((x) * (x))
+
+/* SIMD replacement */
+
+
+/**
+ @brief Read 2 Q15 from Q15 pointer.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2 (
+ q15_t * pQ15)
+{
+ q31_t val;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, pQ15, 4);
+#else
+ val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
+#endif
+
+ return (val);
+}
+
+/**
+ @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2_ia (
+ q15_t ** pQ15)
+{
+ q31_t val;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ15, 4);
+#else
+ val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
+#endif
+
+ *pQ15 += 2;
+ return (val);
+}
+
+/**
+ @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2_da (
+ q15_t ** pQ15)
+{
+ q31_t val;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ15, 4);
+#else
+ val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
+#endif
+
+ *pQ15 -= 2;
+ return (val);
+}
+
+/**
+ @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
+ @param[in] pQ15 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q15x2_ia (
+ q15_t ** pQ15,
+ q31_t value)
+{
+ q31_t val = value;
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (*pQ15, &val, 4);
+#else
+ (*pQ15)[0] = (val & 0x0FFFF);
+ (*pQ15)[1] = (val >> 16) & 0x0FFFF;
+#endif
+
+ *pQ15 += 2;
+}
+
+/**
+ @brief Write 2 Q15 to Q15 pointer.
+ @param[in] pQ15 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q15x2 (
+ q15_t * pQ15,
+ q31_t value)
+{
+ q31_t val = value;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (pQ15, &val, 4);
+#else
+ pQ15[0] = val & 0x0FFFF;
+ pQ15[1] = val >> 16;
+#endif
+}
+
+
+/**
+ @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
+ @param[in] pQ7 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q7x4_ia (
+ q7_t ** pQ7)
+{
+ q31_t val;
+
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ7, 4);
+#else
+ val =(((*pQ7)[3] & 0x0FF) << 24) | (((*pQ7)[2] & 0x0FF) << 16) | (((*pQ7)[1] & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF);
+#endif
+
+ *pQ7 += 4;
+
+ return (val);
+}
+
+/**
+ @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
+ @param[in] pQ7 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q7x4_da (
+ q7_t ** pQ7)
+{
+ q31_t val;
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ7, 4);
+#else
+ val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16) | ((((*pQ7)[1]) & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF);
+#endif
+ *pQ7 -= 4;
+
+ return (val);
+}
+
+/**
+ @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
+ @param[in] pQ7 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q7x4_ia (
+ q7_t ** pQ7,
+ q31_t value)
+{
+ q31_t val = value;
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (*pQ7, &val, 4);
+#else
+ (*pQ7)[0] = val & 0x0FF;
+ (*pQ7)[1] = (val >> 8) & 0x0FF;
+ (*pQ7)[2] = (val >> 16) & 0x0FF;
+ (*pQ7)[3] = (val >> 24) & 0x0FF;
+
+#endif
+ *pQ7 += 4;
+}
+
+/*
+
+Normally those kind of definitions are in a compiler file
+in Core or Core_A.
+
+But for MSVC compiler it is a bit special. The goal is very specific
+to CMSIS-DSP and only to allow the use of this library from other
+systems like Python or Matlab.
+
+MSVC is not going to be used to cross-compile to ARM. So, having a MSVC
+compiler file in Core or Core_A would not make sense.
+
+*/
+#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
+ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#ifndef ARM_MATH_DSP
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+ #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+ #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+#endif
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ __STATIC_FORCEINLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ __STATIC_FORCEINLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ __STATIC_FORCEINLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ __STATIC_FORCEINLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+ __STATIC_FORCEINLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y) ) );
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+ __STATIC_FORCEINLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ const q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1U);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ __STATIC_FORCEINLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ const q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+/**
+ * @brief Integer exponentiation
+ * @param[in] x value
+ * @param[in] nb integer exponent >= 1
+ * @return x^nb
+ *
+ */
+__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb)
+{
+ float32_t r = x;
+ nb --;
+ while(nb > 0)
+ {
+ r = r * x;
+ nb--;
+ }
+ return(r);
+}
+
+/**
+ * @brief 64-bit to 32-bit unsigned normalization
+ * @param[in] in is input unsigned long long value
+ * @param[out] normalized is the 32-bit normalized value
+ * @param[out] norm is norm scale
+ */
+__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm)
+{
+ int32_t n1;
+ int32_t hi = (int32_t) (in >> 32);
+ int32_t lo = (int32_t) ((in << 32) >> 32);
+
+ n1 = __CLZ(hi) - 32;
+ if (!n1)
+ {
+ /*
+ * input fits in 32-bit
+ */
+ n1 = __CLZ(lo);
+ if (!n1)
+ {
+ /*
+ * MSB set, need to scale down by 1
+ */
+ *norm = -1;
+ *normalized = (((uint32_t) lo) >> 1);
+ } else
+ {
+ if (n1 == 32)
+ {
+ /*
+ * input is zero
+ */
+ *norm = 0;
+ *normalized = 0;
+ } else
+ {
+ /*
+ * 32-bit normalization
+ */
+ *norm = n1 - 1;
+ *normalized = lo << *norm;
+ }
+ }
+ } else
+ {
+ /*
+ * input fits in 64-bit
+ */
+ n1 = 1 - n1;
+ *norm = -n1;
+ /*
+ * 64 bit normalization
+ */
+ *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1));
+ }
+}
+
+__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den)
+{
+ q31_t result;
+ uint64_t absNum;
+ int32_t normalized;
+ int32_t norm;
+
+ /*
+ * if sum fits in 32bits
+ * avoid costly 64-bit division
+ */
+ absNum = num > 0 ? num : -num;
+ arm_norm_64_to_32u(absNum, &normalized, &norm);
+ if (norm > 0)
+ /*
+ * 32-bit division
+ */
+ result = (q31_t) num / den;
+ else
+ /*
+ * 64-bit division
+ */
+ result = (q31_t) (num / den);
+
+ return result;
+}
+
+
+/*
+ * @brief C custom defined intrinsic functions
+ */
+#if !defined (ARM_MATH_DSP)
+
+ /*
+ * @brief C custom defined QADD8
+ */
+ __STATIC_FORCEINLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8
+ */
+ __STATIC_FORCEINLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16
+ */
+ __STATIC_FORCEINLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16
+ */
+ __STATIC_FORCEINLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16
+ */
+ __STATIC_FORCEINLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16
+ */
+ __STATIC_FORCEINLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX
+ */
+ __STATIC_FORCEINLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX
+ */
+ __STATIC_FORCEINLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX
+ */
+ __STATIC_FORCEINLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX
+ */
+ __STATIC_FORCEINLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD
+ */
+ __STATIC_FORCEINLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB
+ */
+ __STATIC_FORCEINLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD
+ */
+ __STATIC_FORCEINLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX
+ */
+ __STATIC_FORCEINLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16
+ */
+ __STATIC_FORCEINLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA
+ */
+ __STATIC_FORCEINLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns either
+ * ARM_MATH_SUCCESS if initialization was successful or
+ * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ /**
+ * @brief Instance structure for the modified Biquad coefs required by vectorized code.
+ */
+ typedef struct
+ {
+ float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */
+ } arm_biquad_mod_coef_f32;
+#endif
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version).
+ * @param[in] pState points to the state buffer.
+ */
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ void arm_biquad_cascade_df1_mve_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ arm_biquad_mod_coef_f32 * pCoeffsMod,
+ float32_t * pState);
+#endif
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u16(
+ const uint16_t * pSrc,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u32(
+ const uint32_t * pSrc,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u8(
+ const uint8_t * pSrc,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Struct for specifying sorting algorithm
+ */
+ typedef enum
+ {
+ ARM_SORT_BITONIC = 0,
+ /**< Bitonic sort */
+ ARM_SORT_BUBBLE = 1,
+ /**< Bubble sort */
+ ARM_SORT_HEAP = 2,
+ /**< Heap sort */
+ ARM_SORT_INSERTION = 3,
+ /**< Insertion sort */
+ ARM_SORT_QUICK = 4,
+ /**< Quick sort */
+ ARM_SORT_SELECTION = 5
+ /**< Selection sort */
+ } arm_sort_alg;
+
+ /**
+ * @brief Struct for specifying sorting algorithm
+ */
+ typedef enum
+ {
+ ARM_SORT_DESCENDING = 0,
+ /**< Descending order (9 to 0) */
+ ARM_SORT_ASCENDING = 1
+ /**< Ascending order (0 to 9) */
+ } arm_sort_dir;
+
+ /**
+ * @brief Instance structure for the sorting algorithms.
+ */
+ typedef struct
+ {
+ arm_sort_alg alg; /**< Sorting algorithm selected */
+ arm_sort_dir dir; /**< Sorting order (direction) */
+ } arm_sort_instance_f32;
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in,out] S points to an instance of the sorting structure.
+ * @param[in] alg Selected algorithm.
+ * @param[in] dir Sorting order.
+ */
+ void arm_sort_init_f32(
+ arm_sort_instance_f32 * S,
+ arm_sort_alg alg,
+ arm_sort_dir dir);
+
+ /**
+ * @brief Instance structure for the sorting algorithms.
+ */
+ typedef struct
+ {
+ arm_sort_dir dir; /**< Sorting order (direction) */
+ float32_t * buffer; /**< Working buffer */
+ } arm_merge_sort_instance_f32;
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in,out] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_merge_sort_f32(
+ const arm_merge_sort_instance_f32 * S,
+ float32_t *pSrc,
+ float32_t *pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in,out] S points to an instance of the sorting structure.
+ * @param[in] dir Sorting order.
+ * @param[in] buffer Working buffer.
+ */
+ void arm_merge_sort_init_f32(
+ arm_merge_sort_instance_f32 * S,
+ arm_sort_dir dir,
+ float32_t * buffer);
+
+ /**
+ * @brief Struct for specifying cubic spline type
+ */
+ typedef enum
+ {
+ ARM_SPLINE_NATURAL = 0, /**< Natural spline */
+ ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */
+ } arm_spline_type;
+
+ /**
+ * @brief Instance structure for the floating-point cubic spline interpolation.
+ */
+ typedef struct
+ {
+ arm_spline_type type; /**< Type (boundary conditions) */
+ const float32_t * x; /**< x values */
+ const float32_t * y; /**< y values */
+ uint32_t n_x; /**< Number of known data points */
+ float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */
+ } arm_spline_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point cubic spline interpolation.
+ * @param[in] S points to an instance of the floating-point spline structure.
+ * @param[in] xq points to the x values ot the interpolated data points.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples of output data.
+ */
+ void arm_spline_f32(
+ arm_spline_instance_f32 * S,
+ const float32_t * xq,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point cubic spline interpolation.
+ * @param[in,out] S points to an instance of the floating-point spline structure.
+ * @param[in] type type of cubic spline interpolation (boundary conditions)
+ * @param[in] x points to the x values of the known data points.
+ * @param[in] y points to the y values of the known data points.
+ * @param[in] n number of known data points.
+ * @param[in] coeffs coefficients array for b, c, and d
+ * @param[in] tempBuffer buffer array for internal computations
+ */
+ void arm_spline_init_f32(
+ arm_spline_instance_f32 * S,
+ arm_spline_type type,
+ const float32_t * x,
+ const float32_t * y,
+ uint32_t n,
+ float32_t * coeffs,
+ float32_t * tempBuffer);
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEI)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const q15_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_q15;
+
+arm_status arm_cfft_init_q15(
+ arm_cfft_instance_q15 * S,
+ uint16_t fftLen);
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEI)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const q31_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_q31;
+
+arm_status arm_cfft_init_q31(
+ arm_cfft_instance_q31 * S,
+ uint16_t fftLen);
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const float32_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_f32;
+
+
+ arm_status arm_cfft_init_f32(
+ arm_cfft_instance_f32 * S,
+ uint16_t fftLen);
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+ /**
+ * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float64_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f64;
+
+ void arm_cfft_f64(
+ const arm_cfft_instance_f64 * S,
+ float64_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+#if defined(ARM_MATH_MVEI)
+ arm_cfft_instance_q15 cfftInst;
+#else
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+#endif
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+#if defined(ARM_MATH_MVEI)
+ arm_cfft_instance_q31 cfftInst;
+#else
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+#endif
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f64 ;
+
+arm_status arm_rfft_fast_init_f64 (
+ arm_rfft_fast_instance_f64 * S,
+ uint16_t fftLen);
+
+
+void arm_rfft_fast_f64(
+ arm_rfft_fast_instance_f64 * S,
+ float64_t * p, float64_t * pOut,
+ uint8_t ifftFlag);
+
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+
+ void arm_rfft_fast_f32(
+ const arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ const float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ const float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ const q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ const q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ const float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ const q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ const q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ const q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ const q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ const q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ const q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ const float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ const q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ const q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ const q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+/**
+ @brief Instance structure for floating-point FIR decimator.
+ */
+typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+/**
+ @brief Processing function for floating-point FIR decimator.
+ @param[in] S points to an instance of the floating-point FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ */
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ @brief Initialization function for the floating-point FIR decimator.
+ @param[in,out] S points to an instance of the floating-point FIR decimator structure
+ @param[in] numTaps number of coefficients in the filter
+ @param[in] M decimation factor
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process per call
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M
+ */
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+#if defined(ARM_MATH_NEON)
+void arm_biquad_cascade_df2T_compute_coefs_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs);
+#endif
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ const float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ const q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ const q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void arm_correlate_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+/**
+ @brief Correlation of Q15 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @return none
+ */
+void arm_correlate_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence.
+ @param[in] srcALen length of the first input sequence.
+ @param[in] pSrcB points to the second input sequence.
+ @param[in] srcBLen length of the second input sequence.
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void arm_correlate_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ @brief Correlation of Q31 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return processed output sample.
+ */
+ __STATIC_FORCEINLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+/**
+ @brief Process function for the Q31 PID Control.
+ @param[in,out] S points to an instance of the Q31 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+__STATIC_FORCEINLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+/**
+ @brief Process function for the Q15 PID Control.
+ @param[in,out] S points to an instance of the Q15 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+__STATIC_FORCEINLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+/**
+ @brief Clarke transform for Q31 version
+ @param[in] Ia input three-phase coordinate a
+ @param[in] Ib input three-phase coordinate b
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+/**
+ @brief Inverse Clarke transform for Q31 version
+ @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ @param[in] Ibeta input two-phase orthogonal vector axis beta
+ @param[out] pIa points to output three-phase coordinate a
+ @param[out] pIb points to output three-phase coordinate b
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ __STATIC_FORCEINLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+/**
+ @brief Park transform for Q31 version
+ @param[in] Ialpha input two-phase vector coordinate alpha
+ @param[in] Ibeta input two-phase vector coordinate beta
+ @param[out] pId points to output rotor reference frame d
+ @param[out] pIq points to output rotor reference frame q
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+/**
+ @brief Inverse Park transform for Q31 version
+ @param[in] Id input coordinate of rotor reference frame d
+ @param[in] Iq input coordinate of rotor reference frame q
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ __STATIC_FORCEINLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= (S->nValues - 1))
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ __STATIC_FORCEINLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1U);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ __STATIC_FORCEINLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ __STATIC_FORCEINLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+/**
+ @brief Floating-point vector of log values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vlog_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+/**
+ @brief Floating-point vector of exp values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vexp_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ @brief Floating-point square root function.
+ @param[in] in input value
+ @param[out] pOut square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+__STATIC_FORCEINLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ *pOut = __sqrtf(in);
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+/**
+ @brief Q31 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+/**
+ @brief Q15 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @brief Vector Floating-point square root function.
+ * @param[in] pIn input vector.
+ * @param[out] pOut vector of square roots of input elements.
+ * @param[in] len length of input vector.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ void arm_vsqrt_f32(
+ float32_t * pIn,
+ float32_t * pOut,
+ uint16_t len);
+
+ void arm_vsqrt_q31(
+ q31_t * pIn,
+ q31_t * pOut,
+ uint16_t len);
+
+ void arm_vsqrt_q15(
+ q15_t * pIn,
+ q15_t * pOut,
+ uint16_t len);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t rOffset;
+ int32_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset;
+ q15_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset;
+ q7_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ const q15_t * pSrcCmplx,
+ const q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ const q31_t * pSrcCmplx,
+ const q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ const float32_t * pSrcCmplx,
+ const float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ @brief Maximum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @return none
+ */
+ void arm_max_no_idx_f32(
+ const float32_t *pSrc,
+ uint32_t blockSize,
+ float32_t *pResult);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ const float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ const float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ const float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ const q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ const q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ const q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ const q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ const q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ const q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ const q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ const q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ const q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Struct for specifying SVM Kernel
+ */
+typedef enum
+{
+ ARM_ML_KERNEL_LINEAR = 0,
+ /**< Linear kernel */
+ ARM_ML_KERNEL_POLYNOMIAL = 1,
+ /**< Polynomial kernel */
+ ARM_ML_KERNEL_RBF = 2,
+ /**< Radial Basis Function kernel */
+ ARM_ML_KERNEL_SIGMOID = 3
+ /**< Sigmoid kernel */
+} arm_ml_kernel_type;
+
+
+/**
+ * @brief Instance structure for linear SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+} arm_svm_linear_instance_f32;
+
+
+/**
+ * @brief Instance structure for polynomial SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ int32_t degree; /**< Polynomial degree */
+ float32_t coef0; /**< Polynomial constant */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_polynomial_instance_f32;
+
+/**
+ * @brief Instance structure for rbf SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_rbf_instance_f32;
+
+/**
+ * @brief Instance structure for sigmoid SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ float32_t coef0; /**< Independant constant */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_sigmoid_instance_f32;
+
+/**
+ * @brief SVM linear instance init function
+ * @param[in] S Parameters for SVM functions
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @return none.
+ *
+ */
+
+
+void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes);
+
+/**
+ * @brief SVM linear prediction
+ * @param[in] S Pointer to an instance of the linear SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+
+void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM polynomial instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] degree Polynomial degree
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+
+void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ int32_t degree,
+ float32_t coef0,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM polynomial prediction
+ * @param[in] S Pointer to an instance of the polynomial SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM radial basis function instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM rbf prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult decision value
+ * @return none.
+ *
+ */
+void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+/**
+ * @brief SVM sigmoid instance init function
+ * @param[in] S points to an instance of the rbf SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ float32_t coef0,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM sigmoid prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+
+/**
+ * @brief Instance structure for Naive Gaussian Bayesian estimator.
+ */
+typedef struct
+{
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ uint32_t numberOfClasses; /**< Number of different classes */
+ const float32_t *theta; /**< Mean values for the Gaussians */
+ const float32_t *sigma; /**< Variances for the Gaussians */
+ const float32_t *classPriors; /**< Class prior probabilities */
+ float32_t epsilon; /**< Additive value to variances */
+} arm_gaussian_naive_bayes_instance_f32;
+
+/**
+ * @brief Naive Gaussian Bayesian Estimator
+ *
+ * @param[in] S points to a naive bayes instance structure
+ * @param[in] in points to the elements of the input vector.
+ * @param[in] pBuffer points to a buffer of length numberOfClasses
+ * @return The predicted class
+ *
+ */
+
+
+uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S,
+ const float32_t * in,
+ float32_t *pBuffer);
+
+/**
+ * @brief Computation of the LogSumExp
+ *
+ * In probabilistic computations, the dynamic of the probability values can be very
+ * wide because they come from gaussian functions.
+ * To avoid underflow and overflow issues, the values are represented by their log.
+ * In this representation, multiplying the original exp values is easy : their logs are added.
+ * But adding the original exp values is requiring some special handling and it is the
+ * goal of the LogSumExp function.
+ *
+ * If the values are x1...xn, the function is computing:
+ *
+ * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that
+ * rounding issues are minimised.
+ *
+ * The max xm of the values is extracted and the function is computing:
+ * xm + ln(exp(x1 - xm) + ... + exp(xn - xm))
+ *
+ * @param[in] *in Pointer to an array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return LogSumExp
+ *
+ */
+
+
+float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize);
+
+/**
+ * @brief Dot product with log arithmetic
+ *
+ * Vectors are containing the log of the samples
+ *
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[in] pTmpBuffer temporary buffer of length blockSize
+ * @return The log of the dot product .
+ *
+ */
+
+
+float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t *pTmpBuffer);
+
+/**
+ * @brief Entropy
+ *
+ * @param[in] pSrcA Array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Entropy -Sum(p ln p)
+ *
+ */
+
+
+float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize);
+
+
+/**
+ * @brief Entropy
+ *
+ * @param[in] pSrcA Array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Entropy -Sum(p ln p)
+ *
+ */
+
+
+float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize);
+
+
+/**
+ * @brief Kullback-Leibler
+ *
+ * @param[in] pSrcA Pointer to an array of input values for probability distribution A.
+ * @param[in] pSrcB Pointer to an array of input values for probability distribution B.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Kullback-Leibler Divergence D(A || B)
+ *
+ */
+float32_t arm_kullback_leibler_f32(const float32_t * pSrcA
+ ,const float32_t * pSrcB
+ ,uint32_t blockSize);
+
+
+/**
+ * @brief Kullback-Leibler
+ *
+ * @param[in] pSrcA Pointer to an array of input values for probability distribution A.
+ * @param[in] pSrcB Pointer to an array of input values for probability distribution B.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Kullback-Leibler Divergence D(A || B)
+ *
+ */
+float64_t arm_kullback_leibler_f64(const float64_t * pSrcA,
+ const float64_t * pSrcB,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Weighted sum
+ *
+ *
+ * @param[in] *in Array of input values.
+ * @param[in] *weigths Weights
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Weighted sum
+ *
+ */
+float32_t arm_weighted_sum_f32(const float32_t *in
+ , const float32_t *weigths
+ , uint32_t blockSize);
+
+
+/**
+ * @brief Barycenter
+ *
+ *
+ * @param[in] in List of vectors
+ * @param[in] weights Weights of the vectors
+ * @param[out] out Barycenter
+ * @param[in] nbVectors Number of vectors
+ * @param[in] vecDim Dimension of space (vector dimension)
+ * @return None
+ *
+ */
+void arm_barycenter_f32(const float32_t *in
+ , const float32_t *weights
+ , float32_t *out
+ , uint32_t nbVectors
+ , uint32_t vecDim);
+
+/**
+ * @brief Euclidean distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Bray-Curtis distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Canberra distance between two vectors
+ *
+ * This function may divide by zero when samples pA[i] and pB[i] are both zero.
+ * The result of the computation will be correct. So the division per zero may be
+ * ignored.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Chebyshev distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Cityblock (Manhattan) distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Correlation distance between two vectors
+ *
+ * The input vectors are modified in place !
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Cosine distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Jensen-Shannon distance between two vectors
+ *
+ * This function is assuming that elements of second vector are > 0
+ * and 0 only when the corresponding element of first vector is 0.
+ * Otherwise the result of the computation does not make sense
+ * and for speed reasons, the cases returning NaN or Infinity are not
+ * managed.
+ *
+ * When the function is computing x log (x / y) with x 0 and y 0,
+ * it will compute the right value (0) but a division per zero will occur
+ * and shoudl be ignored in client code.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize);
+
+/**
+ * @brief Minkowski distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] n Norm order (>= 2)
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+
+
+float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize);
+
+/**
+ * @brief Dice distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] order Distance order
+ * @param[in] blockSize Number of samples
+ * @return distance
+ *
+ */
+
+
+float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Hamming distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Jaccard distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Kulsinski distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Roger Stanimoto distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Russell-Rao distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Sokal-Michener distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Sokal-Sneath distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Yule distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex ) + (yIndex ) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex ) + (yIndex+1) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U);
+ acc = ((q63_t) out * (0x0FFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+#endif
+
+
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#elif defined ( _MSC_VER )
+
+#else
+ #error Unknown compiler
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/arm_mve_tables.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/arm_mve_tables.h
new file mode 100644
index 0000000000..4d2c135ac6
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/arm_mve_tables.h
@@ -0,0 +1,235 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mve_tables.h
+ * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
+ * used for MVE implementation only
+ *
+ * $Date: 08. January 2020
+ * $Revision: V1.7.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ #ifndef _ARM_MVE_TABLES_H
+ #define _ARM_MVE_TABLES_H
+
+ #include "arm_math.h"
+
+
+
+
+
+
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
+extern float32_t rearranged_twiddle_stride1_16_f32[8];
+extern float32_t rearranged_twiddle_stride2_16_f32[8];
+extern float32_t rearranged_twiddle_stride3_16_f32[8];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
+extern float32_t rearranged_twiddle_stride1_64_f32[40];
+extern float32_t rearranged_twiddle_stride2_64_f32[40];
+extern float32_t rearranged_twiddle_stride3_64_f32[40];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
+extern float32_t rearranged_twiddle_stride1_256_f32[168];
+extern float32_t rearranged_twiddle_stride2_256_f32[168];
+extern float32_t rearranged_twiddle_stride3_256_f32[168];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
+extern float32_t rearranged_twiddle_stride1_1024_f32[680];
+extern float32_t rearranged_twiddle_stride2_1024_f32[680];
+extern float32_t rearranged_twiddle_stride3_1024_f32[680];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
+extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
+extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
+extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
+#endif
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
+
+
+
+#if defined(ARM_MATH_MVEI)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
+extern q31_t rearranged_twiddle_stride1_16_q31[8];
+extern q31_t rearranged_twiddle_stride2_16_q31[8];
+extern q31_t rearranged_twiddle_stride3_16_q31[8];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
+extern q31_t rearranged_twiddle_stride1_64_q31[40];
+extern q31_t rearranged_twiddle_stride2_64_q31[40];
+extern q31_t rearranged_twiddle_stride3_64_q31[40];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
+extern q31_t rearranged_twiddle_stride1_256_q31[168];
+extern q31_t rearranged_twiddle_stride2_256_q31[168];
+extern q31_t rearranged_twiddle_stride3_256_q31[168];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
+extern q31_t rearranged_twiddle_stride1_1024_q31[680];
+extern q31_t rearranged_twiddle_stride2_1024_q31[680];
+extern q31_t rearranged_twiddle_stride3_1024_q31[680];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
+extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
+extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
+extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
+#endif
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEI) */
+
+
+
+#if defined(ARM_MATH_MVEI)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
+extern q15_t rearranged_twiddle_stride1_16_q15[8];
+extern q15_t rearranged_twiddle_stride2_16_q15[8];
+extern q15_t rearranged_twiddle_stride3_16_q15[8];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
+extern q15_t rearranged_twiddle_stride1_64_q15[40];
+extern q15_t rearranged_twiddle_stride2_64_q15[40];
+extern q15_t rearranged_twiddle_stride3_64_q15[40];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
+extern q15_t rearranged_twiddle_stride1_256_q15[168];
+extern q15_t rearranged_twiddle_stride2_256_q15[168];
+extern q15_t rearranged_twiddle_stride3_256_q15[168];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
+extern q15_t rearranged_twiddle_stride1_1024_q15[680];
+extern q15_t rearranged_twiddle_stride2_1024_q15[680];
+extern q15_t rearranged_twiddle_stride3_1024_q15[680];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
+extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
+extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
+extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
+#endif
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEI) */
+
+
+
+#if defined(ARM_MATH_MVEI)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEI) */
+
+
+
+#endif /*_ARM_MVE_TABLES_H*/
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/arm_vec_math.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/arm_vec_math.h
new file mode 100644
index 0000000000..0ce9464bcb
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/arm_vec_math.h
@@ -0,0 +1,372 @@
+/******************************************************************************
+ * @file arm_vec_math.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.7.0
+ * @date 15. October 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_VEC_MATH_H
+#define _ARM_VEC_MATH_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_helium_utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
+
+#define INV_NEWTON_INIT_F32 0x7EF127EA
+
+static const float32_t __logf_rng_f32=0.693147180f;
+
+
+/* fast inverse approximation (3x newton) */
+__STATIC_INLINE f32x4_t vrecip_medprec_f32(
+ f32x4_t x)
+{
+ q31x4_t m;
+ f32x4_t b;
+ any32x4_t xinv;
+ f32x4_t ax = vabsq(x);
+
+ xinv.f = ax;
+ m = 0x3F800000 - (xinv.i & 0x7F800000);
+ xinv.i = xinv.i + m;
+ xinv.f = 1.41176471f - 0.47058824f * xinv.f;
+ xinv.i = xinv.i + m;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
+ /*
+ * restore sign
+ */
+ xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
+
+ return xinv.f;
+}
+
+/* fast inverse approximation (4x newton) */
+__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
+ f32x4_t x)
+{
+ q31x4_t m;
+ f32x4_t b;
+ any32x4_t xinv;
+ f32x4_t ax = vabsq(x);
+
+ xinv.f = ax;
+
+ m = 0x3F800000 - (xinv.i & 0x7F800000);
+ xinv.i = xinv.i + m;
+ xinv.f = 1.41176471f - 0.47058824f * xinv.f;
+ xinv.i = xinv.i + m;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
+ /*
+ * restore sign
+ */
+ xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
+
+ return xinv.f;
+}
+
+__STATIC_INLINE f32x4_t vdiv_f32(
+ f32x4_t num, f32x4_t den)
+{
+ return vmulq(num, vrecip_hiprec_f32(den));
+}
+
+/**
+ @brief Single-precision taylor dev.
+ @param[in] x f32 quad vector input
+ @param[in] coeffs f32 quad vector coeffs
+ @return destination f32 quad vector
+ */
+
+__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
+ f32x4_t x,
+ const float32_t * coeffs)
+{
+ f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
+ f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
+ f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
+ f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]);
+ f32x4_t x2 = vmulq(x, x);
+ f32x4_t x4 = vmulq(x2, x2);
+ f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4);
+
+ return res;
+}
+
+__STATIC_INLINE f32x4_t vmant_exp_f32(
+ f32x4_t x,
+ int32x4_t * e)
+{
+ any32x4_t r;
+ int32x4_t n;
+
+ r.f = x;
+ n = r.i >> 23;
+ n = n - 127;
+ r.i = r.i - (n << 23);
+
+ *e = n;
+ return r.f;
+}
+
+
+__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
+{
+ q31x4_t vecExpUnBiased;
+ f32x4_t vecTmpFlt0, vecTmpFlt1;
+ f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
+ f32x4_t vecExpUnBiasedFlt;
+
+ /*
+ * extract exponent
+ */
+ vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased);
+
+ vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
+ /*
+ * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]);
+ */
+ vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]);
+ vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]);
+ /*
+ * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]);
+ */
+ vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]);
+ vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]);
+ /*
+ * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]);
+ */
+ vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]);
+ vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]);
+ /*
+ * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]);
+ */
+ vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]);
+ vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]);
+ /*
+ * a = a + b * xx;
+ */
+ vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
+ /*
+ * c = c + d * xx;
+ */
+ vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
+ /*
+ * xx = xx * xx;
+ */
+ vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
+ vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased);
+ /*
+ * r.f = a + c * xx;
+ */
+ vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
+ /*
+ * add exponent
+ * r.f = r.f + ((float32_t) m) * __logf_rng_f32;
+ */
+ vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32);
+ // set log0 down to -inf
+ vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f));
+ return vecAcc0;
+}
+
+__STATIC_INLINE f32x4_t vexpq_f32(
+ f32x4_t x)
+{
+ // Perform range reduction [-log(2),log(2)]
+ int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
+ f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
+
+ // Polynomial Approximation
+ f32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
+
+ // Reconstruct
+ poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23)));
+
+ poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126));
+ return poly;
+}
+
+__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
+{
+ f32x4_t r = x;
+ nb--;
+ while (nb > 0) {
+ r = vmulq(r, x);
+ nb--;
+ }
+ return (r);
+}
+
+__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
+{
+ f32x4_t vecSx, vecW, vecTmp;
+ any32x4_t v;
+
+ vecSx = vabsq(vecIn);
+
+ v.f = vecIn;
+ v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i);
+
+ vecW = vmulq(vecSx, v.f);
+
+ // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
+ vecTmp = vsubq(vdupq_n_f32(8.0f), vecW);
+ vecTmp = vfmasq(vecW, vecTmp, -28.0f);
+ vecTmp = vfmasq(vecW, vecTmp, 56.0f);
+ vecTmp = vfmasq(vecW, vecTmp, -70.0f);
+ vecTmp = vfmasq(vecW, vecTmp, 56.0f);
+ vecTmp = vfmasq(vecW, vecTmp, -28.0f);
+ vecTmp = vfmasq(vecW, vecTmp, 8.0f);
+ v.f = vmulq(v.f, vecTmp);
+
+ v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f));
+ /*
+ * restore sign
+ */
+ v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f));
+ return v.f;
+}
+
+__STATIC_INLINE f32x4_t vtanhq_f32(
+ f32x4_t val)
+{
+ f32x4_t x =
+ vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
+ f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
+ f32x4_t num = vsubq_n_f32(exp2x, 1.f);
+ f32x4_t den = vaddq_n_f32(exp2x, 1.f);
+ f32x4_t tanh = vmulq_f32(num, vrecip_f32(den));
+ return tanh;
+}
+
+__STATIC_INLINE f32x4_t vpowq_f32(
+ f32x4_t val,
+ f32x4_t n)
+{
+ return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
+}
+
+#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
+
+#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
+#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
+
+#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE)
+
+#include "NEMath.h"
+/**
+ * @brief Vectorized integer exponentiation
+ * @param[in] x value
+ * @param[in] nb integer exponent >= 1
+ * @return x^nb
+ *
+ */
+__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
+{
+ float32x4_t r = x;
+ nb --;
+ while(nb > 0)
+ {
+ r = vmulq_f32(r , x);
+ nb--;
+ }
+ return(r);
+}
+
+
+__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
+{
+ float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
+ float32x4_t e = vrsqrteq_f32(x1);
+ e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
+ e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
+ return vmulq_f32(x, e);
+}
+
+__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
+{
+ float32x4_t tempF;
+ int32x4_t tempHI,tempLO;
+
+ tempLO = vmovl_s16(vget_low_s16(vec));
+ tempF = vcvtq_n_f32_s32(tempLO,15);
+ tempF = __arm_vec_sqrt_f32_neon(tempF);
+ tempLO = vcvtq_n_s32_f32(tempF,15);
+
+ tempHI = vmovl_s16(vget_high_s16(vec));
+ tempF = vcvtq_n_f32_s32(tempHI,15);
+ tempF = __arm_vec_sqrt_f32_neon(tempF);
+ tempHI = vcvtq_n_s32_f32(tempF,15);
+
+ return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI)));
+}
+
+__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
+{
+ float32x4_t temp;
+
+ temp = vcvtq_n_f32_s32(vec,31);
+ temp = __arm_vec_sqrt_f32_neon(temp);
+ return(vcvtq_n_s32_f32(temp,31));
+}
+
+#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_VEC_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cachel1_armv7.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cachel1_armv7.h
new file mode 100644
index 0000000000..d2c3e2291f
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cachel1_armv7.h
@@ -0,0 +1,411 @@
+/******************************************************************************
+ * @file cachel1_armv7.h
+ * @brief CMSIS Level 1 Cache API for Armv7-M and later
+ * @version V1.0.0
+ * @date 03. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_CACHEL1_ARMV7_H
+#define ARM_CACHEL1_ARMV7_H
+
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+#ifndef __SCB_DCACHE_LINE_SIZE
+#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+#ifndef __SCB_ICACHE_LINE_SIZE
+#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
+
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief I-Cache Invalidate by address
+ \details Invalidates I-Cache for the given address.
+ I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ I-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] isize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if ( isize > 0 ) {
+ int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_ICACHE_LINE_SIZE;
+ op_size -= __SCB_ICACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address.
+ D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+#endif /* ARM_CACHEL1_ARMV7_H */
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_armcc.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 0000000000..237ff6ec3e
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,885 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.2.1
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+ /* __ARM_ARCH_8_1M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_armclang.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 0000000000..90de9dbf8f
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1467 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.3.1
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_armclang_ltm.h
new file mode 100644
index 0000000000..0e5c7349d3
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_armclang_ltm.h
@@ -0,0 +1,1893 @@
+/**************************************************************************//**
+ * @file cmsis_armclang_ltm.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.3.0
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_compiler.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 0000000000..adbf296f15
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_gcc.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 0000000000..a2778f58e8
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2177 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.3.0
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi":::"memory")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe":::"memory")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+ uint32_t result;
+
+ __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+
+ return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_iccarm.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 0000000000..7eeffca5c7
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,968 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.2.0
+ * @date 28. January 2020
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_version.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_version.h
new file mode 100644
index 0000000000..2f048e4552
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.4
+ * @date 23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/core_armv81mml.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/core_armv81mml.h
new file mode 100644
index 0000000000..1ad19e215a
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/CMSIS/Include/core_armv81mml.h
@@ -0,0 +1,4191 @@
+/**************************************************************************//**
+ * @file core_armv81mml.h
+ * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
+ * @version V1.3.1
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_ARMV81MML_H_GENERIC
+#define __CORE_ARMV81MML_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv81MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
+ uint32_t RESERVED4[14U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
+#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
+
+#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
+#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
+#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
+
+#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
+#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
+
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
+#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
+
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
+#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
+
+#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
+#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
+
+#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
+#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
+
+#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
+#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
+
+#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
+#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
+
+#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
+#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
+
+#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
+#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
+
+#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
+#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
+
+/* SCB Debug Feature Register 0 Definitions */
+#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
+#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
+
+#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
+#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB RAS Fault Status Register Definitions */
+#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
+#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
+
+#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
+#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
+
+#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
+#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[3U];
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */
+#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_PMU Performance Monitoring Unit (PMU)
+ \brief Type definitions for the Performance Monitoring Unit (PMU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Performance Monitoring Unit (PMU).
+ */
+typedef struct
+{
+ __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */
+ uint32_t RESERVED1[224];
+ __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */
+ uint32_t RESERVED3[480];
+ __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */
+ uint32_t RESERVED4[7];
+ __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */
+ uint32_t RESERVED5[7];
+ __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */
+ uint32_t RESERVED6[7];
+ __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */
+ uint32_t RESERVED7[7];
+ __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */
+ uint32_t RESERVED8[7];
+ __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */
+ uint32_t RESERVED9[7];
+ __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */
+ uint32_t RESERVED10[79];
+ __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */
+ uint32_t RESERVED11[108];
+ __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
+ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
+ uint32_t RESERVED12[4];
+ __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
+ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
+ uint32_t RESERVED13[3];
+ __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
+ __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
+ __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
+ __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
+ uint32_t RESERVED14[3];
+ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
+ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
+ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
+ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */
+} PMU_Type;
+
+/** \brief PMU Event Counter Registers (0-30) Definitions */
+
+#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
+#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
+
+/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
+
+#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
+#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
+
+/** \brief PMU Count Enable Set Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
+#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
+#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
+#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
+#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
+#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
+#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
+#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
+#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
+#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
+#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
+#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
+#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
+#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
+#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
+#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
+#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
+#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
+#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
+#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
+#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
+#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
+#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
+#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
+#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
+#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
+#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
+#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
+#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
+#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
+#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
+#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
+
+#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
+#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
+
+/** \brief PMU Count Enable Clear Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
+#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
+#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
+
+#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
+#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
+#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
+#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
+#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
+#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
+#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
+#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
+#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
+#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
+#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
+#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
+#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
+#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
+#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
+#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
+#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
+#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
+#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
+#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
+#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
+#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
+#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
+#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
+#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
+#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
+#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
+#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
+#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
+#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
+#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
+
+/** \brief PMU Interrupt Enable Set Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
+#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
+
+/** \brief PMU Interrupt Enable Clear Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
+
+#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
+
+/** \brief PMU Overflow Flag Status Set Register Definitions */
+
+#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
+#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
+#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
+#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
+#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
+#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
+#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
+#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
+#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
+#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
+#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
+#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
+#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
+#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
+#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
+#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
+#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
+#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
+#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
+#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
+#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
+#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
+#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
+#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
+#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
+#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
+#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
+#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
+#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
+#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
+#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
+#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
+
+#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
+#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
+
+/** \brief PMU Overflow Flag Status Clear Register Definitions */
+
+#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
+#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
+#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
+
+#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
+#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
+#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
+#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
+#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
+#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
+#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
+#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
+#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
+#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
+#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
+#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
+#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
+#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
+#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
+#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
+#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
+#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
+#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
+#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
+#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
+#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
+#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
+#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
+#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
+#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
+#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
+#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
+#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
+#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
+#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
+
+/** \brief PMU Software Increment Counter */
+
+#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */
+#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
+
+#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */
+#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
+
+#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */
+#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
+
+#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */
+#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
+
+#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */
+#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
+
+#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */
+#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
+
+#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */
+#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
+
+#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */
+#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
+
+#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */
+#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
+
+#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */
+#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
+
+#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */
+#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
+
+#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */
+#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
+
+#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */
+#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
+
+#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */
+#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
+
+#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */
+#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
+
+#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */
+#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
+
+#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */
+#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
+
+#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */
+#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
+
+#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */
+#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
+
+#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */
+#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
+
+#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */
+#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
+
+#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */
+#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
+
+#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */
+#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
+
+#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */
+#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
+
+#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */
+#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
+
+#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */
+#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
+
+#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */
+#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
+
+#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */
+#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
+
+#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */
+#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
+
+#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */
+#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
+
+#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */
+#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
+
+/** \brief PMU Control Register Definitions */
+
+#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */
+#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */
+
+#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */
+#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */
+#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */
+#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */
+
+#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */
+#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */
+
+#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */
+#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */
+
+/** \brief PMU Type Register Definitions */
+
+#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
+#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
+
+#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
+#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
+
+#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
+#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
+
+#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */
+#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */
+
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
+
+/*@} end of group CMSIS_PMU */
+#endif
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
+#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
+
+#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
+#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */
+#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */
+
+#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */
+#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */
+
+#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */
+#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */
+#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */
+
+#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */
+#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */
+
+#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */
+#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */
+#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */
+
+#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */
+#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */
+
+#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
+#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
+
+#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
+#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
+
+#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */
+#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */
+
+#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */
+#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */
+#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */
+
+#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */
+#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */
+
+#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */
+#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */
+
+#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */
+#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */
+#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Set Clear Exception and Monitor Control Register Definitions */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */
+#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */
+#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
+
+#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */
+#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
+#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */
+#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */
+
+#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */
+#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */
+
+#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */
+#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */
+
+#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */
+#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
+#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
+
+#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
+#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
+
+#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
+#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
+
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
+#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
+
+#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+ #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */
+ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## PMU functions and events #################################### */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+
+#include "pmu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+/* ########################## MVE functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_MveFunctions MVE Functions
+ \brief Function that provides MVE type.
+ @{
+ */
+
+/**
+ \brief get MVE type
+ \details returns the MVE type
+ \returns
+ - \b 0: No Vector Extension (MVE)
+ - \b 1: Integer Vector Extension (MVE-I)
+ - \b 2: Floating-point Vector Extension (MVE-F)
+ */
+__STATIC_INLINE uint32_t SCB_GetMVEType(void)
+{
+ const uint32_t mvfr1 = FPU->MVFR1;
+ if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
+ {
+ return 2U;
+ }
+ else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
+ {
+ return 1U;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+
+/*@} end of CMSIS_Core_MveFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
+ /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+#else
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
+#endif
+ /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+#else
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
+#endif
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M1 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+#endif
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M35P */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M55 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
+ uint32_t RESERVED4[14U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
+#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
+
+#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
+#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
+#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
+
+#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
+#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
+
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
+#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
+
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
+#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
+
+#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
+#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
+
+#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
+#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
+
+#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
+#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
+
+#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
+#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
+
+#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
+#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
+
+#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
+#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
+
+#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
+#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
+
+/* SCB Debug Feature Register 0 Definitions */
+#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
+#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
+
+#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
+#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB RAS Fault Status Register Definitions */
+#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
+#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
+
+#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
+#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
+
+#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
+#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[3U];
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */
+#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_PMU Performance Monitoring Unit (PMU)
+ \brief Type definitions for the Performance Monitoring Unit (PMU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Performance Monitoring Unit (PMU).
+ */
+typedef struct
+{
+ __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */
+ uint32_t RESERVED1[224];
+ __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */
+ uint32_t RESERVED3[480];
+ __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */
+ uint32_t RESERVED4[7];
+ __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */
+ uint32_t RESERVED5[7];
+ __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */
+ uint32_t RESERVED6[7];
+ __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */
+ uint32_t RESERVED7[7];
+ __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */
+ uint32_t RESERVED8[7];
+ __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */
+ uint32_t RESERVED9[7];
+ __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */
+ uint32_t RESERVED10[79];
+ __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */
+ uint32_t RESERVED11[108];
+ __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
+ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
+ uint32_t RESERVED12[4];
+ __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
+ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
+ uint32_t RESERVED13[3];
+ __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
+ __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
+ __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
+ __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
+ uint32_t RESERVED14[3];
+ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
+ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
+ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
+ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */
+} PMU_Type;
+
+/** \brief PMU Event Counter Registers (0-30) Definitions */
+
+#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
+#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
+
+/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
+
+#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
+#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
+
+/** \brief PMU Count Enable Set Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
+#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
+#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
+#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
+#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
+#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
+#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
+#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
+#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
+#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
+#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
+#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
+#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
+#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
+#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
+#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
+#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
+#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
+#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
+#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
+#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
+#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
+#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
+#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
+#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
+#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
+#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
+#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
+#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
+#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
+#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
+#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
+
+#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
+#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
+
+/** \brief PMU Count Enable Clear Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
+#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
+#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
+
+#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
+#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
+#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
+#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
+#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
+#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
+#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
+#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
+#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
+#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
+#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
+#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
+#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
+#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
+#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
+#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
+#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
+#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
+#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
+#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
+#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
+#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
+#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
+#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
+#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
+#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
+#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
+#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
+#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
+#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
+#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
+
+/** \brief PMU Interrupt Enable Set Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
+#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
+
+/** \brief PMU Interrupt Enable Clear Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
+
+#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
+
+/** \brief PMU Overflow Flag Status Set Register Definitions */
+
+#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
+#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
+#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
+#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
+#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
+#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
+#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
+#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
+#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
+#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
+#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
+#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
+#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
+#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
+#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
+#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
+#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
+#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
+#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
+#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
+#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
+#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
+#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
+#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
+#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
+#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
+#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
+#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
+#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
+#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
+#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
+#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
+
+#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
+#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
+
+/** \brief PMU Overflow Flag Status Clear Register Definitions */
+
+#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
+#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
+#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
+
+#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
+#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
+#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
+#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
+#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
+#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
+#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
+#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
+#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
+#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
+#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
+#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
+#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
+#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
+#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
+#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
+#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
+#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
+#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
+#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
+#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
+#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
+#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
+#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
+#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
+#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
+#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
+#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
+#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
+#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
+#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
+
+/** \brief PMU Software Increment Counter */
+
+#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */
+#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
+
+#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */
+#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
+
+#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */
+#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
+
+#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */
+#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
+
+#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */
+#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
+
+#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */
+#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
+
+#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */
+#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
+
+#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */
+#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
+
+#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */
+#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
+
+#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */
+#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
+
+#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */
+#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
+
+#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */
+#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
+
+#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */
+#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
+
+#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */
+#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
+
+#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */
+#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
+
+#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */
+#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
+
+#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */
+#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
+
+#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */
+#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
+
+#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */
+#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
+
+#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */
+#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
+
+#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */
+#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
+
+#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */
+#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
+
+#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */
+#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
+
+#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */
+#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
+
+#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */
+#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
+
+#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */
+#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
+
+#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */
+#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
+
+#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */
+#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
+
+#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */
+#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
+
+#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */
+#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
+
+#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */
+#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
+
+/** \brief PMU Control Register Definitions */
+
+#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */
+#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */
+
+#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */
+#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */
+#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */
+#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */
+
+#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */
+#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */
+
+#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */
+#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */
+
+/** \brief PMU Type Register Definitions */
+
+#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
+#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
+
+#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
+#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
+
+#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
+#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
+
+#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */
+#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */
+
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
+
+/*@} end of group CMSIS_PMU */
+#endif
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
+#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
+
+#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
+#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */
+#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */
+
+#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */
+#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */
+
+#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */
+#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */
+#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */
+
+#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */
+#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */
+
+#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */
+#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */
+#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */
+
+#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */
+#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */
+
+#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
+#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
+
+#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
+#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
+
+#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */
+#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */
+
+#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */
+#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */
+#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */
+
+#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */
+#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */
+
+#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */
+#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */
+
+#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */
+#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */
+#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Set Clear Exception and Monitor Control Register Definitions */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */
+#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */
+#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
+
+#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */
+#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
+#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */
+#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */
+
+#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */
+#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */
+
+#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */
+#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */
+
+#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */
+#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
+#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
+
+#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
+#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
+
+#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
+#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
+
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
+#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
+
+#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+ #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */
+ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## PMU functions and events #################################### */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+
+#include "pmu_armv8.h"
+
+/**
+ \brief Cortex-M55 PMU events
+ \note Architectural PMU events can be found in pmu_armv8.h
+*/
+
+#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */
+#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */
+#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */
+#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */
+#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */
+#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/
+#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */
+#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */
+#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */
+#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */
+#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */
+#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */
+#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */
+#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */
+#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
+#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */
+#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
+#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+/* ########################## MVE functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_MveFunctions MVE Functions
+ \brief Function that provides MVE type.
+ @{
+ */
+
+/**
+ \brief get MVE type
+ \details returns the MVE type
+ \returns
+ - \b 0: No Vector Extension (MVE)
+ - \b 1: Integer Vector Extension (MVE-I)
+ - \b 2: Floating-point Vector Extension (MVE-F)
+ */
+__STATIC_INLINE uint32_t SCB_GetMVEType(void)
+{
+ const uint32_t mvfr1 = FPU->MVFR1;
+ if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
+ {
+ return 2U;
+ }
+ else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
+ {
+ return 1U;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+
+/*@} end of CMSIS_Core_MveFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h__Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
+#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
+
+#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
+#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
+
+#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
+#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
+
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
+#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
+
+#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
+#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
+
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/SConscript b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/SConscript
new file mode 100644
index 0000000000..18a533a76c
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/SConscript
@@ -0,0 +1,41 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Split('''
+TAE32G58xx_Device/Src/system_tae32g58xx.c
+TAE32G58xx_Driver/Src/tae32g58xx_ll_rcu.c
+TAE32G58xx_Driver/Src/tae32g58xx_ll_cortex.c
+TAE32G58xx_Driver/Src/tae32g58xx_ll_sysctrl.c
+TAE32G58xx_Driver/Src/tae32g58xx_ll_dma.c
+TAE32G58xx_Driver/Src/tae32g58xx_ll_eflash.c
+TAE32G58xx_Driver/Src/tae32g58xx_ll.c
+TAE32G58xx_Driver/Src/tae32g58xx_ll_gpio.c
+''')
+
+if GetDepend(['RT_USING_GPIO']):
+ src += ['TAE32G58xx_Driver/Src/tae32g58xx_ll_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+ src += ['TAE32G58xx_Driver/Src/tae32g58xx_ll_uart.c']
+
+if GetDepend(['RT_USING_CAN']):
+ src += ['TAE32G58xx_Driver/Src/tae32g58xx_ll_can.c']
+
+if GetDepend(['RT_USING_WDT']):
+ src += ['TAE32G58xx_Driver/Src/tae32g58xx_ll_iwdg.c']
+
+path = [
+ cwd + '/CMSIS/Include',
+ cwd + '/TAE32G58xx_Device/Inc',
+ cwd + '/TAE32G58xx_Driver/Inc',]
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER']
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Inc/myChip.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Inc/myChip.h
new file mode 100644
index 0000000000..e8f4a2faad
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Inc/myChip.h
@@ -0,0 +1,24901 @@
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * @file myChip.h
+ * @brief CMSIS HeaderFile
+ * @version 1.2
+ * @date 02. November 2024
+ * @note Generated by SVDConv V3.3.35 on Saturday, 02.11.2024 11:59:19
+ * from File 'myChip.svd',
+ * last modified on Saturday, 02.11.2024 03:58:22
+ */
+
+
+
+/** @addtogroup ARM Ltd.
+ * @{
+ */
+
+
+/** @addtogroup myChip
+ * @{
+ */
+
+
+#ifndef MYCHIP_H
+#define MYCHIP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+typedef enum {
+/* ======================================= ARM Cortex-M3 Specific Interrupt Numbers ======================================== */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+/* =========================================== myChip Specific Interrupt Numbers =========================================== */
+ I2C0_IRQn = 0, /*!< 0 I2C0 */
+ I2C1_IRQn = 1, /*!< 1 I2C1 */
+ I2C2_IRQn = 2, /*!< 2 I2C2 */
+ UART0_IRQn = 3, /*!< 3 UART0 */
+ UART1_IRQn = 4, /*!< 4 UART1 */
+ UART2_IRQn = 5, /*!< 5 UART2 */
+ UART3_IRQn = 6, /*!< 6 UART3 */
+ UART4_IRQn = 7, /*!< 7 UART4 */
+ SPI0_IRQn = 8, /*!< 8 SPI0 */
+ SPI1_IRQn = 9, /*!< 9 SPI1 */
+ CAN0_IRQn = 10, /*!< 10 CAN0 */
+ CAN1_IRQn = 11, /*!< 11 CAN1 */
+ PDM0_IRQn = 12, /*!< 12 PDM0 */
+ PDM1_IRQn = 13, /*!< 13 PDM1 */
+ PDM2_IRQn = 14, /*!< 14 PDM2 */
+ PDM3_IRQn = 15, /*!< 15 PDM3 */
+ QEI0_IRQn = 16, /*!< 16 QEI0 */
+ QEI1_IRQn = 17, /*!< 17 QEI1 */
+ QEI2_IRQn = 18, /*!< 18 QEI2 */
+ DMA_CH0_IRQn = 19, /*!< 19 DMA_CH0 */
+ DMA_CH1_IRQn = 20, /*!< 20 DMA_CH1 */
+ DMA_CH2_IRQn = 21, /*!< 21 DMA_CH2 */
+ DMA_CH3_IRQn = 22, /*!< 22 DMA_CH3 */
+ DMA_CH4_IRQn = 23, /*!< 23 DMA_CH4 */
+ DMA_CH5_IRQn = 24, /*!< 24 DMA_CH5 */
+ TMR7_IRQn = 25, /*!< 25 TMR7 */
+ TMR8_IRQn = 26, /*!< 26 TMR8 */
+ TMR0_IRQn = 27, /*!< 27 TMR0 */
+ TMR1_IRQn = 28, /*!< 28 TMR1 */
+ TMR2_IRQn = 29, /*!< 29 TMR2 */
+ TMR3_IRQn = 30, /*!< 30 TMR3 */
+ TMR4_IRQn = 31, /*!< 31 TMR4 */
+ TMR9_BRK_IRQn = 32, /*!< 32 TMR9_BRK */
+ TMR9_UPD_IRQn = 33, /*!< 33 TMR9_UPD */
+ TMR9_TRG_IRQn = 34, /*!< 34 TMR9_TRG */
+ TMR9_CC_IRQn = 35, /*!< 35 TMR9_CC */
+ TMR10_BRK_IRQn = 36, /*!< 36 TMR10_BRK */
+ TMR10_UPD_IRQn = 37, /*!< 37 TMR10_UPD */
+ TMR10_TRG_IRQn = 38, /*!< 38 TMR10_TRG */
+ TMR10_CC_IRQn = 39, /*!< 39 TMR10_CC */
+ IWDG_IRQn = 40, /*!< 40 IWDG */
+ WWDG_IRQn = 41, /*!< 41 WWDG */
+ GPIOA_IRQn = 42, /*!< 42 GPIOA */
+ GPIOB_IRQn = 43, /*!< 43 GPIOB */
+ GPIOC_IRQn = 44, /*!< 44 GPIOC */
+ GPIOD_IRQn = 45, /*!< 45 GPIOD */
+ GPIOE_IRQn = 46, /*!< 46 GPIOE */
+ GPIOF_IRQn = 47, /*!< 47 GPIOF */
+ FLASH_IRQn = 48, /*!< 48 FLASH */
+ IIR_IRQn = 49, /*!< 49 IIR0_5 Interrupt Group */
+ CORDIC_IRQn = 50, /*!< 50 CORDIC */
+ CMPG0_IRQn = 51, /*!< 51 CMP0_2 Interrupt Group */
+ CMPG1_IRQn = 52, /*!< 52 CMP3_5 Interrupt Group */
+ CMPG2_IRQn = 53, /*!< 53 CMP6_8 Interrupt Group */
+ HRPWM_MST_IRQn = 54, /*!< 54 HRPWM_MST */
+ HRPWM_SLV0_IRQn = 55, /*!< 55 HRPWM_SLV0 */
+ HRPWM_SLV1_IRQn = 56, /*!< 56 HRPWM_SLV1 */
+ HRPWM_SLV2_IRQn = 57, /*!< 57 HRPWM_SLV2 */
+ HRPWM_SLV3_IRQn = 58, /*!< 58 HRPWM_SLV3 */
+ HRPWM_SLV4_IRQn = 59, /*!< 59 HRPWM_SLV4 */
+ HRPWM_SLV5_IRQn = 60, /*!< 60 HRPWM_SLV5 */
+ HRPWM_SLV6_IRQn = 61, /*!< 61 HRPWM_SLV6 */
+ HRPWM_SLV7_IRQn = 62, /*!< 62 HRPWM_SLV7 */
+ HRPWM_COM_IRQn = 63, /*!< 63 HRPWM_COM */
+ ADC0_NORM_IRQn = 64, /*!< 64 ADC0_NORM */
+ ADC0_SAMP_IRQn = 65, /*!< 65 ADC0_SAMP */
+ ADC0_HALF_IRQn = 66, /*!< 66 ADC0_HALF */
+ ADC0_FULL_IRQn = 67, /*!< 67 ADC0_FULL */
+ ADC1_NORM_IRQn = 68, /*!< 68 ADC1_NORM */
+ ADC1_SAMP_IRQn = 69, /*!< 69 ADC1_SAMP */
+ ADC1_HALF_IRQn = 70, /*!< 70 ADC1_HALF */
+ ADC1_FULL_IRQn = 71, /*!< 71 ADC1_FULL */
+ ADC2_NORM_IRQn = 72, /*!< 72 ADC2_NORM */
+ ADC2_SAMP_IRQn = 73, /*!< 73 ADC2_SAMP */
+ ADC2_HALF_IRQn = 74, /*!< 74 ADC2_HALF */
+ ADC2_FULL_IRQn = 75, /*!< 75 ADC2_FULL */
+ ADC3_NORM_IRQn = 76, /*!< 76 ADC3_NORM */
+ ADC3_SAMP_IRQn = 77, /*!< 77 ADC3_SAMP */
+ ADC3_HALF_IRQn = 78, /*!< 78 ADC3_HALF */
+ ADC3_FULL_IRQn = 79, /*!< 79 ADC3_FULL */
+ PMU_IRQn = 80, /*!< 80 PMU */
+ USB_PWR_IRQn = 81, /*!< 81 USB_PWR */
+ USB_DET_IRQn = 82, /*!< 82 USB_DET */
+ USB_EP_IRQn = 83, /*!< 83 USB_EP */
+ XIF_IRQn = 84, /*!< 84 XIF */
+ CAN0_INT1_IRQn = 85, /*!< 85 CAN0_INT1 */
+ CAN1_INT1_IRQn = 86, /*!< 86 CAN1_INT1 */
+ TMR6_IRQn = 87 /*!< 87 TMR6 */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
+#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 0 /*!< MPU present */
+#define __FPU_PRESENT 1 /*!< FPU present */
+#define __VTOR_PRESENT 1 /*!< VTOR present */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
+#include "system_myChip.h" /*!< myChip System */
+
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+#endif
+
+
+/* ======================================== Start of section using anonymous unions ======================================== */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+ #pragma clang diagnostic ignored "-Wnested-anon-types"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ XIF ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief XIF (XIF)
+ */
+
+typedef struct { /*!< (@ 0x40016000) XIF Structure */
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) XIF Enable Register */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) XIF Control Register */
+ __IOM uint32_t TIMING; /*!< (@ 0x00000008) XIF Timing Register */
+ __IOM uint32_t TO; /*!< (@ 0x0000000C) XIF Timeout Register */
+ __IOM uint32_t DATA; /*!< (@ 0x00000010) XIF Read Data Registers */
+ __IOM uint32_t ISR; /*!< (@ 0x00000014) XIF Interrupt And Status Register */
+ __IOM uint32_t WDATA; /*!< (@ 0x00000018) XIF Write Data Registers */
+} XIF_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ WWDG ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief WWDG (WWDG)
+ */
+
+typedef struct { /*!< (@ 0x4000D000) WWDG Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) WWDG Control Register */
+ __IOM uint32_t WVR; /*!< (@ 0x00000004) WWDG Window Register */
+ __IOM uint32_t CVR; /*!< (@ 0x00000008) WWDG Counter Register */
+ __IOM uint32_t PSCR; /*!< (@ 0x0000000C) WWDG Prescaler Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) WWDG Status Register */
+} WWDG_Type; /*!< Size = 20 (0x14) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ USB ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief USB (USB)
+ */
+
+typedef struct { /*!< (@ 0x40035000) USB Structure */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000000) USB Control Register Include Address And Power
+ Control */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t INDEX; /*!< (@ 0x0000000C) USB Index And Frame Number Register */
+
+ union {
+ __IOM uint32_t TX0CTRL; /*!< (@ 0x00000010) USB TX Endpoint 0 Control Register */
+ __IOM uint32_t TXnCTRL; /*!< (@ 0x00000010) USB TX Endpoint n Control Register */
+ };
+ __IOM uint32_t RXCTRL; /*!< (@ 0x00000014) USB RX Endpoint Control Register */
+ __IOM uint32_t RXCOUNT; /*!< (@ 0x00000018) USB Number of bytes to be read from RX endpoint
+ FIFO */
+ __IOM uint32_t FIFOSIZE; /*!< (@ 0x0000001C) USB Returns the configured size of the selected
+ RX FIFO and TX FIFOs */
+ __IM uint32_t RESERVED1[16];
+ __IOM uint32_t FIFOSZ; /*!< (@ 0x00000060) The Dynamic FIFO registers */
+ __IOM uint32_t FIFOAD; /*!< (@ 0x00000064) USB FIFO Start Address Register */
+ __IM uint32_t RESERVED2[230];
+ __IOM uint32_t PINCTRL; /*!< (@ 0x00000400) USB DP/DM PIN Control Register */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t IUINTREN; /*!< (@ 0x00000410) USB Insert/Unplug Detect Interrupt Enable Register */
+ __IOM uint32_t EPINTREN; /*!< (@ 0x00000414) USB Endpoint Tx/Rx Interrupt Enable Register */
+ __IOM uint32_t USBINTREN; /*!< (@ 0x00000418) USB Power Interrupt Enable Register */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t IUINTR; /*!< (@ 0x00000420) USB Insert/Unplug Detect Interrupt Register */
+ __IOM uint32_t EPINTR; /*!< (@ 0x00000424) USB Endpoint Tx/Rx Interrupt Register */
+ __IOM uint32_t USBINTR; /*!< (@ 0x00000428) USB Power Interrupt Register */
+ __IM uint32_t RESERVED5[5];
+ __IOM uint32_t FIFO0; /*!< (@ 0x00000440) FIFOs for Endpoints 0 */
+ __IOM uint32_t FIFO1; /*!< (@ 0x00000444) FIFOs for Endpoints 1 */
+ __IOM uint32_t FIFO2; /*!< (@ 0x00000448) FIFOs for Endpoints 2 */
+} USB_Type; /*!< Size = 1100 (0x44c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART0 (UART0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) UART0 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) UART Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) UART Control Register1 */
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) UART Baud Rate Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) UART FIFO Control Register */
+ __IOM uint32_t TIMING0; /*!< (@ 0x00000014) UART Timing Register0 */
+ __IOM uint32_t TIMING1; /*!< (@ 0x00000018) UART Timing Register1 */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t TDR; /*!< (@ 0x00000020) UART Transmit Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000024) UART Receive Data Register */
+ __IOM uint32_t TAR; /*!< (@ 0x00000028) UART Transmit Address Register */
+ __IOM uint32_t RAR; /*!< (@ 0x0000002C) UART Receive Address Register */
+ __IOM uint32_t RTO; /*!< (@ 0x00000030) UART Receiver Timeout Register */
+ __IOM uint32_t INTEN; /*!< (@ 0x00000034) UART Interrupt Enable Register */
+ __IOM uint32_t INT; /*!< (@ 0x00000038) UART Interrupt Register */
+ __IOM uint32_t STATUS; /*!< (@ 0x0000003C) UART Status Register */
+} UART0_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART1 (UART1)
+ */
+
+typedef struct { /*!< (@ 0x40004000) UART1 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) UART Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) UART Control Register1 */
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) UART Baud Rate Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) UART FIFO Control Register */
+ __IOM uint32_t TIMING0; /*!< (@ 0x00000014) UART Timing Register0 */
+ __IOM uint32_t TIMING1; /*!< (@ 0x00000018) UART Timing Register1 */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t TDR; /*!< (@ 0x00000020) UART Transmit Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000024) UART Receive Data Register */
+ __IOM uint32_t TAR; /*!< (@ 0x00000028) UART Transmit Address Register */
+ __IOM uint32_t RAR; /*!< (@ 0x0000002C) UART Receive Address Register */
+ __IOM uint32_t RTO; /*!< (@ 0x00000030) UART Receiver Timeout Register */
+ __IOM uint32_t INTEN; /*!< (@ 0x00000034) UART Interrupt Enable Register */
+ __IOM uint32_t INT; /*!< (@ 0x00000038) UART Interrupt Register */
+ __IOM uint32_t STATUS; /*!< (@ 0x0000003C) UART Status Register */
+} UART1_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART2 (UART2)
+ */
+
+typedef struct { /*!< (@ 0x40005000) UART2 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) UART Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) UART Control Register1 */
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) UART Baud Rate Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) UART FIFO Control Register */
+ __IOM uint32_t TIMING0; /*!< (@ 0x00000014) UART Timing Register0 */
+ __IOM uint32_t TIMING1; /*!< (@ 0x00000018) UART Timing Register1 */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t TDR; /*!< (@ 0x00000020) UART Transmit Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000024) UART Receive Data Register */
+ __IOM uint32_t TAR; /*!< (@ 0x00000028) UART Transmit Address Register */
+ __IOM uint32_t RAR; /*!< (@ 0x0000002C) UART Receive Address Register */
+ __IOM uint32_t RTO; /*!< (@ 0x00000030) UART Receiver Timeout Register */
+ __IOM uint32_t INTEN; /*!< (@ 0x00000034) UART Interrupt Enable Register */
+ __IOM uint32_t INT; /*!< (@ 0x00000038) UART Interrupt Register */
+ __IOM uint32_t STATUS; /*!< (@ 0x0000003C) UART Status Register */
+} UART2_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART3 (UART3)
+ */
+
+typedef struct { /*!< (@ 0x40010000) UART3 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) UART Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) UART Control Register1 */
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) UART Baud Rate Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) UART FIFO Control Register */
+ __IOM uint32_t TIMING0; /*!< (@ 0x00000014) UART Timing Register0 */
+ __IOM uint32_t TIMING1; /*!< (@ 0x00000018) UART Timing Register1 */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t TDR; /*!< (@ 0x00000020) UART Transmit Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000024) UART Receive Data Register */
+ __IOM uint32_t TAR; /*!< (@ 0x00000028) UART Transmit Address Register */
+ __IOM uint32_t RAR; /*!< (@ 0x0000002C) UART Receive Address Register */
+ __IOM uint32_t RTO; /*!< (@ 0x00000030) UART Receiver Timeout Register */
+ __IOM uint32_t INTEN; /*!< (@ 0x00000034) UART Interrupt Enable Register */
+ __IOM uint32_t INT; /*!< (@ 0x00000038) UART Interrupt Register */
+ __IOM uint32_t STATUS; /*!< (@ 0x0000003C) UART Status Register */
+} UART3_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART4 (UART4)
+ */
+
+typedef struct { /*!< (@ 0x40011000) UART4 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) UART Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) UART Control Register1 */
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) UART Baud Rate Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) UART FIFO Control Register */
+ __IOM uint32_t TIMING0; /*!< (@ 0x00000014) UART Timing Register0 */
+ __IOM uint32_t TIMING1; /*!< (@ 0x00000018) UART Timing Register1 */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t TDR; /*!< (@ 0x00000020) UART Transmit Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000024) UART Receive Data Register */
+ __IOM uint32_t TAR; /*!< (@ 0x00000028) UART Transmit Address Register */
+ __IOM uint32_t RAR; /*!< (@ 0x0000002C) UART Receive Address Register */
+ __IOM uint32_t RTO; /*!< (@ 0x00000030) UART Receiver Timeout Register */
+ __IOM uint32_t INTEN; /*!< (@ 0x00000034) UART Interrupt Enable Register */
+ __IOM uint32_t INT; /*!< (@ 0x00000038) UART Interrupt Register */
+ __IOM uint32_t STATUS; /*!< (@ 0x0000003C) UART Status Register */
+} UART4_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SYSCTRL ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SYSCTRL (SYSCTRL)
+ */
+
+typedef struct { /*!< (@ 0x40021000) SYSCTRL Structure */
+ __IOM uint32_t SYSDCR; /*!< (@ 0x00000000) System Debug Config Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t SYSCR; /*!< (@ 0x00000008) System Config Register */
+ __IOM uint32_t DMARCR; /*!< (@ 0x0000000C) DMA Request Config Register */
+ __IM uint32_t RESERVED1[4];
+ __IOM uint32_t SYSATR; /*!< (@ 0x00000020) System Analog Config Register */
+ __IOM uint32_t PWRCR; /*!< (@ 0x00000024) PMU Power Config Register */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t PLCR; /*!< (@ 0x00000030) Power Limit Config Register */
+ __IOM uint32_t PECR; /*!< (@ 0x00000034) Power Event Control Register */
+ __IOM uint32_t PSR; /*!< (@ 0x00000038) Power Status Register */
+ __IOM uint32_t PWRDR; /*!< (@ 0x0000003C) Power Debounce Register */
+ __IOM uint32_t CIDR; /*!< (@ 0x00000040) System ChipId Config Register */
+ __IOM uint32_t KEYR; /*!< (@ 0x00000044) LockKey Register */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t UID0; /*!< (@ 0x00000050) System UserID0 Register */
+ __IOM uint32_t UID1; /*!< (@ 0x00000054) System UserID1 Register */
+ __IOM uint32_t UID2; /*!< (@ 0x00000058) System UserID2 Register */
+ __IOM uint32_t UID3; /*!< (@ 0x0000005C) System UserID3 Register */
+ __IOM uint32_t ATCR; /*!< (@ 0x00000060) Analog Trim Config Register */
+ __IOM uint32_t FCR0; /*!< (@ 0x00000064) System AutoLoad Register0 */
+ __IOM uint32_t FCR1; /*!< (@ 0x00000068) System AutoLoad Register1 */
+ __IOM uint32_t FCR2; /*!< (@ 0x0000006C) System AutoLoad Register2 */
+ __IOM uint32_t FCR3; /*!< (@ 0x00000070) System AutoLoad Register3 */
+ __IOM uint32_t FCR4; /*!< (@ 0x00000074) System AutoLoad Register4 */
+ __IOM uint32_t FCR5; /*!< (@ 0x00000078) System AutoLoad Register5 */
+} SYSCTRL_Type; /*!< Size = 124 (0x7c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI0 (SPI0)
+ */
+
+typedef struct { /*!< (@ 0x40012000) SPI0 Structure */
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) SPI Enable Register */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) SPI Control Register */
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) SPI Baud Rate Registers */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) SPI FIFO Control Register */
+ __IOM uint32_t CNT; /*!< (@ 0x00000014) SPI Count Registers */
+ __IOM uint32_t RCNT; /*!< (@ 0x00000018) SPI Remain Count Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t START; /*!< (@ 0x00000020) SPI Count Start Register */
+ __IOM uint32_t TIMING; /*!< (@ 0x00000024) SPI Timing Register */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000030) SPI Interrupt Enable Registers */
+ __IOM uint32_t INT; /*!< (@ 0x00000034) SPI Interrupt Registers */
+ __IOM uint32_t STATUS; /*!< (@ 0x00000038) SPI Status Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t TDR; /*!< (@ 0x00000040) SPI TXFIFO Data Registers */
+ __IOM uint32_t RDR; /*!< (@ 0x00000044) SPI RXFIFO Data Registers */
+ __IOM uint32_t UDRDR; /*!< (@ 0x00000048) SPI Underrun Data Register */
+} SPI0_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI1 (SPI1)
+ */
+
+typedef struct { /*!< (@ 0x40013000) SPI1 Structure */
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) SPI Enable Register */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) SPI Control Register */
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) SPI Baud Rate Registers */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) SPI FIFO Control Register */
+ __IOM uint32_t CNT; /*!< (@ 0x00000014) SPI Count Registers */
+ __IOM uint32_t RCNT; /*!< (@ 0x00000018) SPI Remain Count Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t START; /*!< (@ 0x00000020) SPI Count Start Register */
+ __IOM uint32_t TIMING; /*!< (@ 0x00000024) SPI Timing Register */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000030) SPI Interrupt Enable Registers */
+ __IOM uint32_t INT; /*!< (@ 0x00000034) SPI Interrupt Registers */
+ __IOM uint32_t STATUS; /*!< (@ 0x00000038) SPI Status Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t TDR; /*!< (@ 0x00000040) SPI TXFIFO Data Registers */
+ __IOM uint32_t RDR; /*!< (@ 0x00000044) SPI RXFIFO Data Registers */
+ __IOM uint32_t UDRDR; /*!< (@ 0x00000048) SPI Underrun Data Register */
+} SPI1_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RCU ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief RCU (RCU)
+ */
+
+typedef struct { /*!< (@ 0x40020000) RCU Structure */
+ __IOM uint32_t PLL0CR; /*!< (@ 0x00000000) PLL0 Control Register */
+ __IOM uint32_t PLL0FR; /*!< (@ 0x00000004) PLL0 Fractional Register */
+ __IM uint32_t RESERVED[10];
+ __IOM uint32_t CCR; /*!< (@ 0x00000030) System Clock Config Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t PCSR; /*!< (@ 0x00000038) Peripheral Function Clock Source Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t PCDR0; /*!< (@ 0x00000040) Peripheral Function Clock Division Register0 */
+ __IOM uint32_t PCDR1; /*!< (@ 0x00000044) Peripheral Function Clock Division Register1 */
+ __IOM uint32_t PCDR2; /*!< (@ 0x00000048) Peripheral Function Clock Division Register2 */
+ __IOM uint32_t PCENR; /*!< (@ 0x0000004C) Peripheral Function Clock Enable Register */
+ __IOM uint32_t APB0ENR; /*!< (@ 0x00000050) APB0 Peripheral Clock Enable Register */
+ __IOM uint32_t APB1ENR; /*!< (@ 0x00000054) APB1 Peripheral Clock Enable Register */
+ __IOM uint32_t AHB0ENR; /*!< (@ 0x00000058) AHB0 Peripheral Clock Enable Register */
+ __IOM uint32_t AHB1ENR; /*!< (@ 0x0000005C) AHB1 Peripheral Clock Enable Register */
+ __IOM uint32_t APB0RSTR; /*!< (@ 0x00000060) APB0 Peripheral Reset Register */
+ __IOM uint32_t APB1RSTR; /*!< (@ 0x00000064) APB1 Peripheral Reset Register */
+ __IOM uint32_t AHB0RSTR; /*!< (@ 0x00000068) AHB0 Peripheral Reset Register */
+ __IOM uint32_t AHB1RSTR; /*!< (@ 0x0000006C) AHB1 Peripheral Reset Register */
+ __IOM uint32_t XOSCCR; /*!< (@ 0x00000070) XOSC Control Register */
+ __IOM uint32_t CSSCR; /*!< (@ 0x00000074) Clock Secure Control Register */
+ __IOM uint32_t DBGCR; /*!< (@ 0x00000078) Internal Clock Fanout Register */
+ __IOM uint32_t SRSTSR; /*!< (@ 0x0000007C) System RstStatus Register */
+ __IOM uint32_t KEYR; /*!< (@ 0x00000080) LockKey Register */
+ __IOM uint32_t SRSR; /*!< (@ 0x00000084) System Reset Status Register */
+} RCU_Type; /*!< Size = 136 (0x88) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ QEI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief QEI0 (QEI0)
+ */
+
+typedef struct { /*!< (@ 0x4002D000) QEI0 Structure */
+ __IOM uint32_t POSCNT; /*!< (@ 0x00000000) QEI Position Counter Register */
+ __IOM uint32_t POSINIT; /*!< (@ 0x00000004) QEI Position Counter Initial Register */
+ __IOM uint32_t POSMAX; /*!< (@ 0x00000008) QEI Position Counter Max Register */
+ __IOM uint32_t POSCMP; /*!< (@ 0x0000000C) QEI Position Counter Compare Register */
+ __IOM uint32_t POSILAT; /*!< (@ 0x00000010) QEI Position Counter Index Latch Register */
+ __IOM uint32_t POSLAT; /*!< (@ 0x00000014) QEI Position Counter Timer Latch Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t UTMR; /*!< (@ 0x00000020) QTIMER Counter Register */
+ __IOM uint32_t UPRD; /*!< (@ 0x00000024) QTIMER Counter Period Register */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t DECCTL; /*!< (@ 0x00000030) QEI Decoder Control Register */
+ __IOM uint32_t QEPCTL; /*!< (@ 0x00000034) QEI Contorl Register */
+ __IOM uint32_t POSCTL; /*!< (@ 0x00000038) QEI Position Contorl Register */
+ __IOM uint32_t CAPCTL; /*!< (@ 0x0000003C) QEI Capture Control Register */
+ __IOM uint32_t QCTMR; /*!< (@ 0x00000040) QEI Capture Counter Register */
+ __IOM uint32_t QCPRD; /*!< (@ 0x00000044) QEI Capture Period Register */
+ __IOM uint32_t CTMRLAT; /*!< (@ 0x00000048) QEI Capture Counter Latch Register */
+ __IOM uint32_t CPRDLAT; /*!< (@ 0x0000004C) QEI Capture Period Latch Register */
+ __IOM uint32_t IENR; /*!< (@ 0x00000050) QEI Interrupt Enable Register */
+ __IOM uint32_t STSR; /*!< (@ 0x00000054) QEI Interrupt Status Register */
+} QEI0_Type; /*!< Size = 88 (0x58) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ QEI1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief QEI1 (QEI1)
+ */
+
+typedef struct { /*!< (@ 0x4002E000) QEI1 Structure */
+ __IOM uint32_t POSCNT; /*!< (@ 0x00000000) QEI Position Counter Register */
+ __IOM uint32_t POSINIT; /*!< (@ 0x00000004) QEI Position Counter Initial Register */
+ __IOM uint32_t POSMAX; /*!< (@ 0x00000008) QEI Position Counter Max Register */
+ __IOM uint32_t POSCMP; /*!< (@ 0x0000000C) QEI Position Counter Compare Register */
+ __IOM uint32_t POSILAT; /*!< (@ 0x00000010) QEI Position Counter Index Latch Register */
+ __IOM uint32_t POSLAT; /*!< (@ 0x00000014) QEI Position Counter Timer Latch Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t UTMR; /*!< (@ 0x00000020) QTIMER Counter Register */
+ __IOM uint32_t UPRD; /*!< (@ 0x00000024) QTIMER Counter Period Register */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t DECCTL; /*!< (@ 0x00000030) QEI Decoder Control Register */
+ __IOM uint32_t QEPCTL; /*!< (@ 0x00000034) QEI Contorl Register */
+ __IOM uint32_t POSCTL; /*!< (@ 0x00000038) QEI Position Contorl Register */
+ __IOM uint32_t CAPCTL; /*!< (@ 0x0000003C) QEI Capture Control Register */
+ __IOM uint32_t QCTMR; /*!< (@ 0x00000040) QEI Capture Counter Register */
+ __IOM uint32_t QCPRD; /*!< (@ 0x00000044) QEI Capture Period Register */
+ __IOM uint32_t CTMRLAT; /*!< (@ 0x00000048) QEI Capture Counter Latch Register */
+ __IOM uint32_t CPRDLAT; /*!< (@ 0x0000004C) QEI Capture Period Latch Register */
+ __IOM uint32_t IENR; /*!< (@ 0x00000050) QEI Interrupt Enable Register */
+ __IOM uint32_t STSR; /*!< (@ 0x00000054) QEI Interrupt Status Register */
+} QEI1_Type; /*!< Size = 88 (0x58) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ QEI2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief QEI2 (QEI2)
+ */
+
+typedef struct { /*!< (@ 0x4002F000) QEI2 Structure */
+ __IOM uint32_t POSCNT; /*!< (@ 0x00000000) QEI Position Counter Register */
+ __IOM uint32_t POSINIT; /*!< (@ 0x00000004) QEI Position Counter Initial Register */
+ __IOM uint32_t POSMAX; /*!< (@ 0x00000008) QEI Position Counter Max Register */
+ __IOM uint32_t POSCMP; /*!< (@ 0x0000000C) QEI Position Counter Compare Register */
+ __IOM uint32_t POSILAT; /*!< (@ 0x00000010) QEI Position Counter Index Latch Register */
+ __IOM uint32_t POSLAT; /*!< (@ 0x00000014) QEI Position Counter Timer Latch Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t UTMR; /*!< (@ 0x00000020) QTIMER Counter Register */
+ __IOM uint32_t UPRD; /*!< (@ 0x00000024) QTIMER Counter Period Register */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t DECCTL; /*!< (@ 0x00000030) QEI Decoder Control Register */
+ __IOM uint32_t QEPCTL; /*!< (@ 0x00000034) QEI Contorl Register */
+ __IOM uint32_t POSCTL; /*!< (@ 0x00000038) QEI Position Contorl Register */
+ __IOM uint32_t CAPCTL; /*!< (@ 0x0000003C) QEI Capture Control Register */
+ __IOM uint32_t QCTMR; /*!< (@ 0x00000040) QEI Capture Counter Register */
+ __IOM uint32_t QCPRD; /*!< (@ 0x00000044) QEI Capture Period Register */
+ __IOM uint32_t CTMRLAT; /*!< (@ 0x00000048) QEI Capture Counter Latch Register */
+ __IOM uint32_t CPRDLAT; /*!< (@ 0x0000004C) QEI Capture Period Latch Register */
+ __IOM uint32_t IENR; /*!< (@ 0x00000050) QEI Interrupt Enable Register */
+ __IOM uint32_t STSR; /*!< (@ 0x00000054) QEI Interrupt Status Register */
+} QEI2_Type; /*!< Size = 88 (0x58) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief PDM0 (PDM0)
+ */
+
+typedef struct { /*!< (@ 0x40017000) PDM0 Structure */
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) PDM Enable Register */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) PDM Control Register */
+ __IOM uint32_t DFCR; /*!< (@ 0x00000008) PDM Main Filter Control Register */
+ __IOM uint32_t CFCR; /*!< (@ 0x0000000C) PDM Compare Filter Control Register */
+ __IOM uint32_t FCSR; /*!< (@ 0x00000010) PDM FIFO Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000014) PDM Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) PDM Interrupt State Register */
+ __IOM uint32_t DDAT; /*!< (@ 0x0000001C) PDM Main Filter Result Register */
+ __IOM uint32_t CDAT; /*!< (@ 0x00000020) PDM Compare Filter Result Register */
+ __IOM uint32_t FDAT; /*!< (@ 0x00000024) PDM FIFO Result Register */
+ __IOM uint32_t CMPH; /*!< (@ 0x00000028) PDM High-Level Compare Register */
+ __IOM uint32_t CMPL; /*!< (@ 0x0000002C) PDM Low-Level Compare Register */
+ __IOM uint32_t CLKTO; /*!< (@ 0x00000030) PDM Clock Timeout Register */
+ __IOM uint32_t SDSYNC; /*!< (@ 0x00000034) PDM Synchronization Control Register */
+ __IOM uint32_t IDAT; /*!< (@ 0x00000038) PDM Input Data Register */
+} PDM0_Type; /*!< Size = 60 (0x3c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief PDM1 (PDM1)
+ */
+
+typedef struct { /*!< (@ 0x40017100) PDM1 Structure */
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) PDM Enable Register */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) PDM Control Register */
+ __IOM uint32_t DFCR; /*!< (@ 0x00000008) PDM Main Filter Control Register */
+ __IOM uint32_t CFCR; /*!< (@ 0x0000000C) PDM Compare Filter Control Register */
+ __IOM uint32_t FCSR; /*!< (@ 0x00000010) PDM FIFO Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000014) PDM Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) PDM Interrupt State Register */
+ __IOM uint32_t DDAT; /*!< (@ 0x0000001C) PDM Main Filter Result Register */
+ __IOM uint32_t CDAT; /*!< (@ 0x00000020) PDM Compare Filter Result Register */
+ __IOM uint32_t FDAT; /*!< (@ 0x00000024) PDM FIFO Result Register */
+ __IOM uint32_t CMPH; /*!< (@ 0x00000028) PDM High-Level Compare Register */
+ __IOM uint32_t CMPL; /*!< (@ 0x0000002C) PDM Low-Level Compare Register */
+ __IOM uint32_t CLKTO; /*!< (@ 0x00000030) PDM Clock Timeout Register */
+ __IOM uint32_t SDSYNC; /*!< (@ 0x00000034) PDM Synchronization Control Register */
+ __IOM uint32_t IDAT; /*!< (@ 0x00000038) PDM Input Data Register */
+} PDM1_Type; /*!< Size = 60 (0x3c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief PDM2 (PDM2)
+ */
+
+typedef struct { /*!< (@ 0x40017200) PDM2 Structure */
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) PDM Enable Register */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) PDM Control Register */
+ __IOM uint32_t DFCR; /*!< (@ 0x00000008) PDM Main Filter Control Register */
+ __IOM uint32_t CFCR; /*!< (@ 0x0000000C) PDM Compare Filter Control Register */
+ __IOM uint32_t FCSR; /*!< (@ 0x00000010) PDM FIFO Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000014) PDM Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) PDM Interrupt State Register */
+ __IOM uint32_t DDAT; /*!< (@ 0x0000001C) PDM Main Filter Result Register */
+ __IOM uint32_t CDAT; /*!< (@ 0x00000020) PDM Compare Filter Result Register */
+ __IOM uint32_t FDAT; /*!< (@ 0x00000024) PDM FIFO Result Register */
+ __IOM uint32_t CMPH; /*!< (@ 0x00000028) PDM High-Level Compare Register */
+ __IOM uint32_t CMPL; /*!< (@ 0x0000002C) PDM Low-Level Compare Register */
+ __IOM uint32_t CLKTO; /*!< (@ 0x00000030) PDM Clock Timeout Register */
+ __IOM uint32_t SDSYNC; /*!< (@ 0x00000034) PDM Synchronization Control Register */
+ __IOM uint32_t IDAT; /*!< (@ 0x00000038) PDM Input Data Register */
+} PDM2_Type; /*!< Size = 60 (0x3c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief PDM3 (PDM3)
+ */
+
+typedef struct { /*!< (@ 0x40017300) PDM3 Structure */
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) PDM Enable Register */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) PDM Control Register */
+ __IOM uint32_t DFCR; /*!< (@ 0x00000008) PDM Main Filter Control Register */
+ __IOM uint32_t CFCR; /*!< (@ 0x0000000C) PDM Compare Filter Control Register */
+ __IOM uint32_t FCSR; /*!< (@ 0x00000010) PDM FIFO Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000014) PDM Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) PDM Interrupt State Register */
+ __IOM uint32_t DDAT; /*!< (@ 0x0000001C) PDM Main Filter Result Register */
+ __IOM uint32_t CDAT; /*!< (@ 0x00000020) PDM Compare Filter Result Register */
+ __IOM uint32_t FDAT; /*!< (@ 0x00000024) PDM FIFO Result Register */
+ __IOM uint32_t CMPH; /*!< (@ 0x00000028) PDM High-Level Compare Register */
+ __IOM uint32_t CMPL; /*!< (@ 0x0000002C) PDM Low-Level Compare Register */
+ __IOM uint32_t CLKTO; /*!< (@ 0x00000030) PDM Clock Timeout Register */
+ __IOM uint32_t SDSYNC; /*!< (@ 0x00000034) PDM Synchronization Control Register */
+ __IOM uint32_t IDAT; /*!< (@ 0x00000038) PDM Input Data Register */
+} PDM3_Type; /*!< Size = 60 (0x3c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IWDG ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IWDG (IWDG)
+ */
+
+typedef struct { /*!< (@ 0x4000C000) IWDG Structure */
+ __IOM uint32_t KEYR; /*!< (@ 0x00000000) IWDG Key Register */
+ __IOM uint32_t CR; /*!< (@ 0x00000004) IWDG Control Register */
+ __IOM uint32_t RLR; /*!< (@ 0x00000008) IWDG Reload Register */
+ __IOM uint32_t PSCR; /*!< (@ 0x0000000C) IWDG Prescaler Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) IWDG Status Register */
+} IWDG_Type; /*!< Size = 20 (0x14) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR0 (IIR0)
+ */
+
+typedef struct { /*!< (@ 0x4003E000) IIR0 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+} IIR0_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR1 (IIR1)
+ */
+
+typedef struct { /*!< (@ 0x4003E100) IIR1 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+} IIR1_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR2 (IIR2)
+ */
+
+typedef struct { /*!< (@ 0x4003E200) IIR2 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+} IIR2_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR3 (IIR3)
+ */
+
+typedef struct { /*!< (@ 0x4003E300) IIR3 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+} IIR3_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR4 (IIR4)
+ */
+
+typedef struct { /*!< (@ 0x4003E400) IIR4 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+} IIR4_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR5 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR5 (IIR5)
+ */
+
+typedef struct { /*!< (@ 0x4003E500) IIR5 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+ __IM uint32_t RESERVED[4];
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+ __IM uint32_t RESERVED1[3];
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+} IIR5_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2C0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C0 (I2C0)
+ */
+
+typedef struct { /*!< (@ 0x40000000) I2C0 Structure */
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) I2C Enable Register */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) I2C Transmission Control Register */
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) I2C Baud Rate Register */
+ __IOM uint32_t UDRDR; /*!< (@ 0x0000000C) I2C Underrun Data Register */
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) I2C FIFO Control Register */
+ __IOM uint32_t TAR; /*!< (@ 0x00000014) I2C Target Address Register */
+ __IOM uint32_t SAR; /*!< (@ 0x00000018) I2C Slave Address Register */
+ __IOM uint32_t OSAR; /*!< (@ 0x0000001C) I2C Optional Slave Address Register */
+ __IOM uint32_t PEC; /*!< (@ 0x00000020) I2C RX PEC Register */
+ __IOM uint32_t TIMING; /*!< (@ 0x00000024) I2C Timing Register */
+ __IOM uint32_t TIMEOUT; /*!< (@ 0x00000028) I2C Clock Extension Timeout Register */
+ __IOM uint32_t BUSTOUT; /*!< (@ 0x0000002C) I2C Bus Timeout Register */
+ __IOM uint32_t INTREN; /*!< (@ 0x00000030) I2C Interrupt Enable Register */
+ __IOM uint32_t INTR; /*!< (@ 0x00000034) I2C Interrupt Register */
+ __IOM uint32_t STATUS; /*!< (@ 0x00000038) I2C Status Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t TXDATA; /*!< (@ 0x00000040) I2C TXFIFO Data Registers */
+ __IOM uint32_t RXDATA; /*!< (@ 0x00000044) I2C RXFIFO Data Registers */
+ __IOM uint32_t RXADDR; /*!< (@ 0x00000048) I2C RX ADDR Register */
+} I2C0_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2C1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C1 (I2C1)
+ */
+
+typedef struct { /*!< (@ 0x40001000) I2C1 Structure */
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) I2C Enable Register */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) I2C Transmission Control Register */
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) I2C Baud Rate Register */
+ __IOM uint32_t UDRDR; /*!< (@ 0x0000000C) I2C Underrun Data Register */
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) I2C FIFO Control Register */
+ __IOM uint32_t TAR; /*!< (@ 0x00000014) I2C Target Address Register */
+ __IOM uint32_t SAR; /*!< (@ 0x00000018) I2C Slave Address Register */
+ __IOM uint32_t OSAR; /*!< (@ 0x0000001C) I2C Optional Slave Address Register */
+ __IOM uint32_t PEC; /*!< (@ 0x00000020) I2C RX PEC Register */
+ __IOM uint32_t TIMING; /*!< (@ 0x00000024) I2C Timing Register */
+ __IOM uint32_t TIMEOUT; /*!< (@ 0x00000028) I2C Clock Extension Timeout Register */
+ __IOM uint32_t BUSTOUT; /*!< (@ 0x0000002C) I2C Bus Timeout Register */
+ __IOM uint32_t INTREN; /*!< (@ 0x00000030) I2C Interrupt Enable Register */
+ __IOM uint32_t INTR; /*!< (@ 0x00000034) I2C Interrupt Register */
+ __IOM uint32_t STATUS; /*!< (@ 0x00000038) I2C Status Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t TXDATA; /*!< (@ 0x00000040) I2C TXFIFO Data Registers */
+ __IOM uint32_t RXDATA; /*!< (@ 0x00000044) I2C RXFIFO Data Registers */
+ __IOM uint32_t RXADDR; /*!< (@ 0x00000048) I2C RX ADDR Register */
+} I2C1_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2C2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C2 (I2C2)
+ */
+
+typedef struct { /*!< (@ 0x40002000) I2C2 Structure */
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) I2C Enable Register */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) I2C Transmission Control Register */
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) I2C Baud Rate Register */
+ __IOM uint32_t UDRDR; /*!< (@ 0x0000000C) I2C Underrun Data Register */
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) I2C FIFO Control Register */
+ __IOM uint32_t TAR; /*!< (@ 0x00000014) I2C Target Address Register */
+ __IOM uint32_t SAR; /*!< (@ 0x00000018) I2C Slave Address Register */
+ __IOM uint32_t OSAR; /*!< (@ 0x0000001C) I2C Optional Slave Address Register */
+ __IOM uint32_t PEC; /*!< (@ 0x00000020) I2C RX PEC Register */
+ __IOM uint32_t TIMING; /*!< (@ 0x00000024) I2C Timing Register */
+ __IOM uint32_t TIMEOUT; /*!< (@ 0x00000028) I2C Clock Extension Timeout Register */
+ __IOM uint32_t BUSTOUT; /*!< (@ 0x0000002C) I2C Bus Timeout Register */
+ __IOM uint32_t INTREN; /*!< (@ 0x00000030) I2C Interrupt Enable Register */
+ __IOM uint32_t INTR; /*!< (@ 0x00000034) I2C Interrupt Register */
+ __IOM uint32_t STATUS; /*!< (@ 0x00000038) I2C Status Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t TXDATA; /*!< (@ 0x00000040) I2C TXFIFO Data Registers */
+ __IOM uint32_t RXDATA; /*!< (@ 0x00000044) I2C RXFIFO Data Registers */
+ __IOM uint32_t RXADDR; /*!< (@ 0x00000048) I2C RX ADDR Register */
+} I2C2_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV0 (HRPWM_SLV0)
+ */
+
+typedef struct { /*!< (@ 0x4003B100) HRPWM_SLV0 Structure */
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+} HRPWM_SLV0_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV1 (HRPWM_SLV1)
+ */
+
+typedef struct { /*!< (@ 0x4003B200) HRPWM_SLV1 Structure */
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+} HRPWM_SLV1_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV2 (HRPWM_SLV2)
+ */
+
+typedef struct { /*!< (@ 0x4003B300) HRPWM_SLV2 Structure */
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+} HRPWM_SLV2_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV3 (HRPWM_SLV3)
+ */
+
+typedef struct { /*!< (@ 0x4003B400) HRPWM_SLV3 Structure */
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+} HRPWM_SLV3_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV4 (HRPWM_SLV4)
+ */
+
+typedef struct { /*!< (@ 0x4003B500) HRPWM_SLV4 Structure */
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+} HRPWM_SLV4_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV5 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV5 (HRPWM_SLV5)
+ */
+
+typedef struct { /*!< (@ 0x4003B600) HRPWM_SLV5 Structure */
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+} HRPWM_SLV5_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV6 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV6 (HRPWM_SLV6)
+ */
+
+typedef struct { /*!< (@ 0x4003B700) HRPWM_SLV6 Structure */
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+} HRPWM_SLV6_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV7 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV7 (HRPWM_SLV7)
+ */
+
+typedef struct { /*!< (@ 0x4003B800) HRPWM_SLV7 Structure */
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+} HRPWM_SLV7_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_COM ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_COM (HRPWM_COM)
+ */
+
+typedef struct { /*!< (@ 0x4003BF00) HRPWM_COM Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) HRPWM Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) HRPWM Control Register1 */
+ __IOM uint32_t CR2; /*!< (@ 0x00000008) HRPWM Control Register2 */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) HRPWM Interrupt Status Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000014) HRPWM Interrupt Enable Register */
+ __IOM uint32_t OENR; /*!< (@ 0x00000018) HRPWM Output Enable Register */
+ __IOM uint32_t ODISR; /*!< (@ 0x0000001C) HRPWM Output Disable Register */
+ __IOM uint32_t EECR0; /*!< (@ 0x00000020) HRPWM External Event Control Register0 */
+ __IOM uint32_t EECR1; /*!< (@ 0x00000024) HRPWM External Event Control Register1 */
+ __IOM uint32_t EECR2; /*!< (@ 0x00000028) HRPWM External Event Control Register2 */
+ __IOM uint32_t EECR3; /*!< (@ 0x0000002C) HRPWM External Event Control Register3 */
+ __IOM uint32_t ADC0R; /*!< (@ 0x00000030) HRPWM ADC Trigger Register 0 */
+ __IOM uint32_t ADC0ER; /*!< (@ 0x00000034) HRPWM ADC Trigger Extended Register 0 */
+ __IOM uint32_t ADC1R; /*!< (@ 0x00000038) HRPWM ADC Trigger Register 1 */
+ __IOM uint32_t ADC1ER; /*!< (@ 0x0000003C) HRPWM ADC Trigger Extended Register 1 */
+ __IOM uint32_t ADC2R; /*!< (@ 0x00000040) HRPWM ADC Trigger Register 2 */
+ __IOM uint32_t ADC2ER; /*!< (@ 0x00000044) HRPWM ADC Trigger Extended Register 2 */
+ __IOM uint32_t ADC3R; /*!< (@ 0x00000048) HRPWM ADC Trigger Register 3 */
+ __IOM uint32_t ADC3ER; /*!< (@ 0x0000004C) HRPWM ADC Trigger Extended Register 3 */
+ __IOM uint32_t ADC4R; /*!< (@ 0x00000050) HRPWM ADC Trigger Register 4 */
+ __IOM uint32_t ADC5R; /*!< (@ 0x00000054) HRPWM ADC Trigger Register 5 */
+ __IOM uint32_t ADCUR; /*!< (@ 0x00000058) HRPWM ADC Update Register */
+ __IOM uint32_t ADCLR; /*!< (@ 0x0000005C) HRPWM ADC Length Register */
+ __IOM uint32_t ADPSR0; /*!< (@ 0x00000060) HRPWM ADC Trigger Post Scaler Register0 */
+ __IOM uint32_t ADPSR1; /*!< (@ 0x00000064) HRPWM ADC Trigger Post Scaler Register1 */
+ __IOM uint32_t DLLCR; /*!< (@ 0x00000068) HRPWM DLL Control Register */
+ __IOM uint32_t EECER; /*!< (@ 0x0000006C) HRPWM External Event Control Extended Register */
+ __IOM uint32_t FLTINR0; /*!< (@ 0x00000070) HRPWM Fault Input Register0 */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t FLTINR1; /*!< (@ 0x00000078) HRPWM Fault Input Register1 */
+ __IOM uint32_t FLTINER; /*!< (@ 0x0000007C) HRPWM Fault Input Extend Register */
+ __IOM uint32_t FLTINR2; /*!< (@ 0x00000080) HRPWM Fault Input Register2 */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t FLTINR3; /*!< (@ 0x00000088) HRPWM Fault Input Register3 */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t BMCR; /*!< (@ 0x00000090) HRPWM Burst Mode Control Register */
+ __IOM uint32_t BMTRGR0; /*!< (@ 0x00000094) HRPWM Burst Mode Trigger Register 0 */
+ __IOM uint32_t BMTRGR1; /*!< (@ 0x00000098) HRPWM Burst Mode Trigger Register 1 */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t BMPER; /*!< (@ 0x000000A0) HRPWM Burst Mode Period Register */
+ __IOM uint32_t BMCMPR; /*!< (@ 0x000000A4) HRPWM Burst Mode Compare Register */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t BDMUPR; /*!< (@ 0x000000B0) HRPWM Burst DMA Master Update Register */
+ __IOM uint32_t BDUPR0; /*!< (@ 0x000000B4) HRPWM Burst DMA Update Register 0 */
+ __IOM uint32_t BDUPR1; /*!< (@ 0x000000B8) HRPWM Burst DMA Update Register 1 */
+ __IOM uint32_t BDUPR2; /*!< (@ 0x000000BC) HRPWM Burst DMA Update Register 2 */
+ __IOM uint32_t BDUPR3; /*!< (@ 0x000000C0) HRPWM Burst DMA Update Register 3 */
+ __IOM uint32_t BDUPR4; /*!< (@ 0x000000C4) HRPWM Burst DMA Update Register 4 */
+ __IOM uint32_t BDUPR5; /*!< (@ 0x000000C8) HRPWM Burst DMA Update Register 5 */
+ __IOM uint32_t BDUPR6; /*!< (@ 0x000000CC) HRPWM Burst DMA Update Register 6 */
+ __IOM uint32_t BDUPR7; /*!< (@ 0x000000D0) HRPWM Burst DMA Update Register 7 */
+ __IM uint32_t RESERVED6[3];
+ __IOM uint32_t BDMWADR; /*!< (@ 0x000000E0) HRPWM Burst DMA Write Address Register */
+ __IM uint32_t RESERVED7[3];
+ __IOM uint32_t BDMADR; /*!< (@ 0x000000F0) HRPWM Burst DMA Read Address Register */
+} HRPWM_COM_Type; /*!< Size = 244 (0xf4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_MST ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_MST (HRPWM_MST)
+ */
+
+typedef struct { /*!< (@ 0x4003B000) HRPWM_MST Structure */
+ __IOM uint32_t MCR0; /*!< (@ 0x00000000) HRPWM Master PWM Control Register0 */
+ __IOM uint32_t MCR1; /*!< (@ 0x00000004) HRPWM Master PWM Control Register1 */
+ __IOM uint32_t MISR; /*!< (@ 0x00000008) HRPWM Master PWM Interrupt Status Register */
+ __IOM uint32_t MDIER; /*!< (@ 0x0000000C) HRPWM Master PWM DMA Interrupt Enable Register */
+ __IOM uint32_t MCNTR; /*!< (@ 0x00000010) HRPWM Master PWM Counter Register */
+ __IOM uint32_t MPER; /*!< (@ 0x00000014) HRPWM Master PWM Period Register */
+ __IOM uint32_t MREP; /*!< (@ 0x00000018) HRPWM Master PWM Repetition Register */
+ __IOM uint32_t MCMPAR; /*!< (@ 0x0000001C) HRPWM Master PWM Compare A Register */
+ __IOM uint32_t MCMPBR; /*!< (@ 0x00000020) HRPWM Master PWM Compare B Register */
+ __IOM uint32_t MCMPCR; /*!< (@ 0x00000024) HRPWM Master PWM Compare C Register */
+ __IOM uint32_t MCMPDR; /*!< (@ 0x00000028) HRPWM Master PWM Compare D Register */
+ __IM uint32_t RESERVED[19];
+ __IOM uint32_t MDMAUR; /*!< (@ 0x00000078) HRPWM Master PWM System DMA Update Register */
+ __IOM uint32_t MDMADR; /*!< (@ 0x0000007C) HRPWM Master PWM System DMA Data Register */
+} HRPWM_MST_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR3 (TMR3)
+ */
+
+typedef struct { /*!< (@ 0x4002A000) TMR3 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+ __IM uint32_t RESERVED3[4];
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+ __IOM uint32_t CC2R; /*!< (@ 0x00000058) TMRx Capture Compare Register2 */
+ __IOM uint32_t CC3R; /*!< (@ 0x0000005C) TMRx Capture Compare Register3 */
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+} TMR3_Type; /*!< Size = 100 (0x64) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR4 (TMR4)
+ */
+
+typedef struct { /*!< (@ 0x4002B000) TMR4 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+ __IM uint32_t RESERVED3[4];
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+ __IOM uint32_t CC2R; /*!< (@ 0x00000058) TMRx Capture Compare Register2 */
+ __IOM uint32_t CC3R; /*!< (@ 0x0000005C) TMRx Capture Compare Register3 */
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+} TMR4_Type; /*!< Size = 100 (0x64) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR0 (TMR0)
+ */
+
+typedef struct { /*!< (@ 0x40018000) TMR0 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+ __IOM uint32_t DCR; /*!< (@ 0x00000028) TMRx Dead-Time Contorl Register */
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+ __IOM uint32_t CRR; /*!< (@ 0x00000040) TMRx Counter Repeat Register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+ __IOM uint32_t BPR; /*!< (@ 0x00000064) TMRx Break Polarity Register */
+ __IOM uint32_t BER; /*!< (@ 0x00000068) TMRx Break Enable Register */
+} TMR0_Type; /*!< Size = 108 (0x6c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR1 (TMR1)
+ */
+
+typedef struct { /*!< (@ 0x40019000) TMR1 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+ __IOM uint32_t DCR; /*!< (@ 0x00000028) TMRx Dead-Time Contorl Register */
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+ __IOM uint32_t CRR; /*!< (@ 0x00000040) TMRx Counter Repeat Register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+ __IOM uint32_t BPR; /*!< (@ 0x00000064) TMRx Break Polarity Register */
+ __IOM uint32_t BER; /*!< (@ 0x00000068) TMRx Break Enable Register */
+} TMR1_Type; /*!< Size = 108 (0x6c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR2 (TMR2)
+ */
+
+typedef struct { /*!< (@ 0x4001A000) TMR2 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+ __IOM uint32_t DCR; /*!< (@ 0x00000028) TMRx Dead-Time Contorl Register */
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+ __IOM uint32_t CRR; /*!< (@ 0x00000040) TMRx Counter Repeat Register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+ __IOM uint32_t BPR; /*!< (@ 0x00000064) TMRx Break Polarity Register */
+ __IOM uint32_t BER; /*!< (@ 0x00000068) TMRx Break Enable Register */
+} TMR2_Type; /*!< Size = 108 (0x6c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOA ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOA (GPIOA)
+ */
+
+typedef struct { /*!< (@ 0x40024000) GPIOA Structure */
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+} GPIOA_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOB ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOB (GPIOB)
+ */
+
+typedef struct { /*!< (@ 0x40025000) GPIOB Structure */
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+} GPIOB_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOC (GPIOC)
+ */
+
+typedef struct { /*!< (@ 0x40026000) GPIOC Structure */
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+} GPIOC_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOD ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOD (GPIOD)
+ */
+
+typedef struct { /*!< (@ 0x40027000) GPIOD Structure */
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+} GPIOD_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOE ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOE (GPIOE)
+ */
+
+typedef struct { /*!< (@ 0x40028000) GPIOE Structure */
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+} GPIOE_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOF ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOF (GPIOF)
+ */
+
+typedef struct { /*!< (@ 0x40029000) GPIOF Structure */
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+} GPIOF_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ FLASH ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief FLASH (FLASH)
+ */
+
+typedef struct { /*!< (@ 0x40023000) FLASH Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) Flash Control Register */
+ __IOM uint32_t LPR; /*!< (@ 0x00000004) Flash Lowpower Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000008) Flash Status Register */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t PDR0; /*!< (@ 0x00000010) Flash Data Register0 */
+ __IOM uint32_t PDR1; /*!< (@ 0x00000014) Flash Data Register1 */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t PAR; /*!< (@ 0x00000020) Flash Address Register */
+ __IOM uint32_t KR; /*!< (@ 0x00000024) Flash Key Register */
+ __IOM uint32_t RPR; /*!< (@ 0x00000028) Flash Read Protect Register */
+ __IOM uint32_t WPR; /*!< (@ 0x0000002C) Flash Write Protect Register */
+ __IOM uint32_t TR; /*!< (@ 0x00000030) Flash Timing Register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t OPDR; /*!< (@ 0x00000040) Flash Option Data Register */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t EAR0; /*!< (@ 0x00000050) Flash ECC 1Bit Addr Register */
+ __IOM uint32_t EAR1; /*!< (@ 0x00000054) Flash ECC nBit Addr Register */
+} FLASH_Type; /*!< Size = 88 (0x58) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA0 (DMA0)
+ */
+
+typedef struct { /*!< (@ 0x40022000) DMA0 Structure */
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+} DMA0_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA1 (DMA1)
+ */
+
+typedef struct { /*!< (@ 0x40022020) DMA1 Structure */
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+} DMA1_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA2 (DMA2)
+ */
+
+typedef struct { /*!< (@ 0x40022040) DMA2 Structure */
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+} DMA2_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA3 (DMA3)
+ */
+
+typedef struct { /*!< (@ 0x40022060) DMA3 Structure */
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+} DMA3_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA4 (DMA4)
+ */
+
+typedef struct { /*!< (@ 0x40022080) DMA4 Structure */
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+} DMA4_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA5 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA5 (DMA5)
+ */
+
+typedef struct { /*!< (@ 0x400220A0) DMA5 Structure */
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+} DMA5_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC0 (DAC0)
+ */
+
+typedef struct { /*!< (@ 0x40039000) DAC0 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+} DAC0_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC1 (DAC1)
+ */
+
+typedef struct { /*!< (@ 0x40039100) DAC1 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+} DAC1_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC2 (DAC2)
+ */
+
+typedef struct { /*!< (@ 0x40039200) DAC2 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+} DAC2_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC3 (DAC3)
+ */
+
+typedef struct { /*!< (@ 0x40039300) DAC3 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+} DAC3_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC4 (DAC4)
+ */
+
+typedef struct { /*!< (@ 0x40039400) DAC4 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+} DAC4_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC5 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC5 (DAC5)
+ */
+
+typedef struct { /*!< (@ 0x40039500) DAC5 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+} DAC5_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC6 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC6 (DAC6)
+ */
+
+typedef struct { /*!< (@ 0x40039600) DAC6 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+} DAC6_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC7 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC7 (DAC7)
+ */
+
+typedef struct { /*!< (@ 0x40039700) DAC7 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+} DAC7_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC8 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC8 (DAC8)
+ */
+
+typedef struct { /*!< (@ 0x40039800) DAC8 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+} DAC8_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CORDIC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CORDIC (CORDIC)
+ */
+
+typedef struct { /*!< (@ 0x4003F000) CORDIC Structure */
+ __IOM uint32_t CSR0; /*!< (@ 0x00000000) CORDIC Control / Status register0 */
+ __IOM uint32_t ARX0; /*!< (@ 0x00000004) CORDIC Argument / Result register0 */
+ __IOM uint32_t ARY0; /*!< (@ 0x00000008) CORDIC Argument / Result register0 */
+ __IM uint32_t RESERVED[5];
+ __IOM uint32_t CSR1; /*!< (@ 0x00000020) CORDIC Control / Status register1 */
+ __IOM uint32_t ARX1; /*!< (@ 0x00000024) CORDIC Argument / Result register1 */
+ __IOM uint32_t ARY1; /*!< (@ 0x00000028) CORDIC Argument / Result register1 */
+} CORDIC_Type; /*!< Size = 44 (0x2c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP0 (CMP0)
+ */
+
+typedef struct { /*!< (@ 0x4003A000) CMP0 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+} CMP0_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP1 (CMP1)
+ */
+
+typedef struct { /*!< (@ 0x4003A100) CMP1 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+} CMP1_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP2 (CMP2)
+ */
+
+typedef struct { /*!< (@ 0x4003A200) CMP2 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+} CMP2_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP3 (CMP3)
+ */
+
+typedef struct { /*!< (@ 0x4003A300) CMP3 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+} CMP3_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP4 (CMP4)
+ */
+
+typedef struct { /*!< (@ 0x4003A400) CMP4 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+} CMP4_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP5 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP5 (CMP5)
+ */
+
+typedef struct { /*!< (@ 0x4003A500) CMP5 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+} CMP5_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP6 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP6 (CMP6)
+ */
+
+typedef struct { /*!< (@ 0x4003A600) CMP6 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+} CMP6_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP7 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP7 (CMP7)
+ */
+
+typedef struct { /*!< (@ 0x4003A700) CMP7 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+} CMP7_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP8 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP8 (CMP8)
+ */
+
+typedef struct { /*!< (@ 0x4003A800) CMP8 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+} CMP8_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CAN0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CAN0 (CAN0)
+ */
+
+typedef struct { /*!< (@ 0x40014000) CAN0 Structure */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000000) CAN Control Register */
+ __IOM uint32_t STATUS; /*!< (@ 0x00000004) CAN Status Register */
+ __IOM uint32_t INTREN; /*!< (@ 0x00000008) CAN Interrupt Enable Register */
+ __IOM uint32_t INTRST; /*!< (@ 0x0000000C) CAN Interrupt Status Register */
+ __IOM uint32_t BITTIME; /*!< (@ 0x00000010) CAN Bittime Setting Register */
+ __IOM uint32_t PRESC; /*!< (@ 0x00000014) CAN Prescaler Registers */
+ __IOM uint32_t ERRST; /*!< (@ 0x00000018) CAN Error Status Register */
+ __IOM uint32_t PRTST; /*!< (@ 0x0000001C) CAN Protocol Status Register */
+ __IOM uint32_t INTRLS; /*!< (@ 0x00000020) CAN Interrupt Line Select Register */
+ __IOM uint32_t GFCR; /*!< (@ 0x00000024) CAN Global Filter Control Register */
+ __IOM uint32_t EMCR; /*!< (@ 0x00000028) CAN Extended Mask Control Register */
+ __IOM uint32_t PMST; /*!< (@ 0x0000002C) CAN Priority Message Status Register */
+ __IOM uint32_t ACFEN; /*!< (@ 0x00000030) CAN ACF Enable */
+ __IOM uint32_t ACFCTRL; /*!< (@ 0x00000034) CAN ACF Control Register */
+ __IOM uint32_t ACF; /*!< (@ 0x00000038) CAN ACF Data Register */
+ __IOM uint32_t ACFE; /*!< (@ 0x0000003C) CAN ACF Data Extended Register */
+ __IOM uint32_t RBUFID; /*!< (@ 0x00000040) CAN RX Buffer Read Register(ID) */
+ __IOM uint32_t RBUFCR; /*!< (@ 0x00000044) CAN RX Buffer Read Register(Control) */
+ __IOM uint32_t RBUFDT[16]; /*!< (@ 0x00000048) CAN RX Buffer Read Register(Data) */
+ __IOM uint32_t TBUFID; /*!< (@ 0x00000088) CAN TX Buffer Write Register(ID) */
+ __IOM uint32_t TBUFCR; /*!< (@ 0x0000008C) CAN TX Buffer Write Register(Control) */
+ __IOM uint32_t TBUFDT[16]; /*!< (@ 0x00000090) CAN TX Buffer Write Register(Data) */
+ __IM uint32_t RESERVED[26];
+ __IOM uint32_t EBUFID; /*!< (@ 0x00000138) CAN ETB Buffer Read Register(ID) */
+ __IOM uint32_t EBUFDT; /*!< (@ 0x0000013C) CAN ETB Buffer Read Register(Data) */
+ __IOM uint32_t SBUFID; /*!< (@ 0x00000140) CAN SRB Buffer Read Register(ID) */
+ __IOM uint32_t SBUFCR; /*!< (@ 0x00000144) CAN SRB Buffer Read Register(Control) */
+ __IOM uint32_t SBUFDT[16]; /*!< (@ 0x00000148) CAN SRB Buffer Read Register(Data) */
+ __IM uint32_t RESERVED1[158];
+ __IOM uint32_t TSCR; /*!< (@ 0x00000400) Timestamp Counter Control Register */
+ __IOM uint32_t TSC; /*!< (@ 0x00000404) Timestamp Counter Value Register */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t RTOP; /*!< (@ 0x00000410) PRB Timeout Counter Period Register */
+ __IOM uint32_t RTOC; /*!< (@ 0x00000414) PRB Timeout Counter Value Register */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t STOP; /*!< (@ 0x00000420) SRB Timeout Counter Period Register */
+ __IOM uint32_t STOC; /*!< (@ 0x00000424) SRB Timeout Counter Value Register */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t ETOP; /*!< (@ 0x00000430) ETB Timeout Counter Period Register */
+ __IOM uint32_t ETOC; /*!< (@ 0x00000434) ETB Timeout Counter Value Register */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t CTOP; /*!< (@ 0x00000440) Continuous Timeout Counter Period Register */
+ __IOM uint32_t CTOC; /*!< (@ 0x00000444) Continuous Timeout Counter Value Register */
+} CAN0_Type; /*!< Size = 1096 (0x448) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CAN1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CAN1 (CAN1)
+ */
+
+typedef struct { /*!< (@ 0x40015000) CAN1 Structure */
+ __IOM uint32_t CTRL; /*!< (@ 0x00000000) CAN Control Register */
+ __IOM uint32_t STATUS; /*!< (@ 0x00000004) CAN Status Register */
+ __IOM uint32_t INTREN; /*!< (@ 0x00000008) CAN Interrupt Enable Register */
+ __IOM uint32_t INTRST; /*!< (@ 0x0000000C) CAN Interrupt Status Register */
+ __IOM uint32_t BITTIME; /*!< (@ 0x00000010) CAN Bittime Setting Register */
+ __IOM uint32_t PRESC; /*!< (@ 0x00000014) CAN Prescaler Registers */
+ __IOM uint32_t ERRST; /*!< (@ 0x00000018) CAN Error Status Register */
+ __IOM uint32_t PRTST; /*!< (@ 0x0000001C) CAN Protocol Status Register */
+ __IOM uint32_t INTRLS; /*!< (@ 0x00000020) CAN Interrupt Line Select Register */
+ __IOM uint32_t GFCR; /*!< (@ 0x00000024) CAN Global Filter Control Register */
+ __IOM uint32_t EMCR; /*!< (@ 0x00000028) CAN Extended Mask Control Register */
+ __IOM uint32_t PMST; /*!< (@ 0x0000002C) CAN Priority Message Status Register */
+ __IOM uint32_t ACFEN; /*!< (@ 0x00000030) CAN ACF Enable */
+ __IOM uint32_t ACFCTRL; /*!< (@ 0x00000034) CAN ACF Control Register */
+ __IOM uint32_t ACF; /*!< (@ 0x00000038) CAN ACF Data Register */
+ __IOM uint32_t ACFE; /*!< (@ 0x0000003C) CAN ACF Data Extended Register */
+ __IOM uint32_t RBUFID; /*!< (@ 0x00000040) CAN RX Buffer Read Register(ID) */
+ __IOM uint32_t RBUFCR; /*!< (@ 0x00000044) CAN RX Buffer Read Register(Control) */
+ __IOM uint32_t RBUFDT[16]; /*!< (@ 0x00000048) CAN RX Buffer Read Register(Data) */
+ __IOM uint32_t TBUFID; /*!< (@ 0x00000088) CAN TX Buffer Write Register(ID) */
+ __IOM uint32_t TBUFCR; /*!< (@ 0x0000008C) CAN TX Buffer Write Register(Control) */
+ __IOM uint32_t TBUFDT[16]; /*!< (@ 0x00000090) CAN TX Buffer Write Register(Data) */
+ __IM uint32_t RESERVED[26];
+ __IOM uint32_t EBUFID; /*!< (@ 0x00000138) CAN ETB Buffer Read Register(ID) */
+ __IOM uint32_t EBUFDT; /*!< (@ 0x0000013C) CAN ETB Buffer Read Register(Data) */
+ __IOM uint32_t SBUFID; /*!< (@ 0x00000140) CAN SRB Buffer Read Register(ID) */
+ __IOM uint32_t SBUFCR; /*!< (@ 0x00000144) CAN SRB Buffer Read Register(Control) */
+ __IOM uint32_t SBUFDT[16]; /*!< (@ 0x00000148) CAN SRB Buffer Read Register(Data) */
+ __IM uint32_t RESERVED1[158];
+ __IOM uint32_t TSCR; /*!< (@ 0x00000400) Timestamp Counter Control Register */
+ __IOM uint32_t TSC; /*!< (@ 0x00000404) Timestamp Counter Value Register */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t RTOP; /*!< (@ 0x00000410) PRB Timeout Counter Period Register */
+ __IOM uint32_t RTOC; /*!< (@ 0x00000414) PRB Timeout Counter Value Register */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t STOP; /*!< (@ 0x00000420) SRB Timeout Counter Period Register */
+ __IOM uint32_t STOC; /*!< (@ 0x00000424) SRB Timeout Counter Value Register */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t ETOP; /*!< (@ 0x00000430) ETB Timeout Counter Period Register */
+ __IOM uint32_t ETOC; /*!< (@ 0x00000434) ETB Timeout Counter Value Register */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t CTOP; /*!< (@ 0x00000440) Continuous Timeout Counter Period Register */
+ __IOM uint32_t CTOC; /*!< (@ 0x00000444) Continuous Timeout Counter Value Register */
+} CAN1_Type; /*!< Size = 1096 (0x448) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR7 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR7 (TMR7)
+ */
+
+typedef struct { /*!< (@ 0x40008000) TMR7 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+ __IM uint32_t RESERVED1[5];
+ __IOM uint32_t TCR; /*!< (@ 0x0000002C) TMRx Trigger Control Register */
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+} TMR7_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR8 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR8 (TMR8)
+ */
+
+typedef struct { /*!< (@ 0x40009000) TMR8 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+ __IM uint32_t RESERVED1[5];
+ __IOM uint32_t TCR; /*!< (@ 0x0000002C) TMRx Trigger Control Register */
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+} TMR8_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR9 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR9 (TMR9)
+ */
+
+typedef struct { /*!< (@ 0x40030000) TMR9 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+ __IOM uint32_t DCR; /*!< (@ 0x00000028) TMRx Dead-Time Contorl Register */
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+ __IOM uint32_t CRR; /*!< (@ 0x00000040) TMRx Counter Repeat Register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+ __IOM uint32_t CC2R; /*!< (@ 0x00000058) TMRx Capture Compare Register2 */
+ __IOM uint32_t CC3R; /*!< (@ 0x0000005C) TMRx Capture Compare Register3 */
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+ __IOM uint32_t BPR; /*!< (@ 0x00000064) TMRx Break Polarity Register */
+ __IOM uint32_t BER; /*!< (@ 0x00000068) TMRx Break Enable Register */
+} TMR9_Type; /*!< Size = 108 (0x6c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR10 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR10 (TMR10)
+ */
+
+typedef struct { /*!< (@ 0x40031000) TMR10 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+ __IM uint32_t RESERVED[2];
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+ __IOM uint32_t DCR; /*!< (@ 0x00000028) TMRx Dead-Time Contorl Register */
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+ __IOM uint32_t CRR; /*!< (@ 0x00000040) TMRx Counter Repeat Register */
+ __IM uint32_t RESERVED2[3];
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+ __IOM uint32_t CC2R; /*!< (@ 0x00000058) TMRx Capture Compare Register2 */
+ __IOM uint32_t CC3R; /*!< (@ 0x0000005C) TMRx Capture Compare Register3 */
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+ __IOM uint32_t BPR; /*!< (@ 0x00000064) TMRx Break Polarity Register */
+ __IOM uint32_t BER; /*!< (@ 0x00000068) TMRx Break Enable Register */
+} TMR10_Type; /*!< Size = 108 (0x6c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ADC0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief ADC0 (ADC0)
+ */
+
+typedef struct { /*!< (@ 0x40038000) ADC0 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) ADC Control Register */
+ __IOM uint32_t CFGR0; /*!< (@ 0x00000004) ADC Configuration Register0 */
+ __IOM uint32_t CFGR1; /*!< (@ 0x00000008) ADC Configuration Register1 */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) ADC Interrupt Status Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000014) ADC Interrupt Enable Register */
+ __IOM uint32_t SIGSEL; /*!< (@ 0x00000018) ADC Single-End Select Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t SMPR0; /*!< (@ 0x00000020) ADC Sample Time Register 0 */
+ __IOM uint32_t SMPR1; /*!< (@ 0x00000024) ADC Sample Time Register 1 */
+ __IOM uint32_t SMPR2; /*!< (@ 0x00000028) ADC Sample Time Register 2 */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t CALR0; /*!< (@ 0x00000030) ADC Calibration Data Register 0 */
+ __IOM uint32_t CALR1; /*!< (@ 0x00000034) ADC Calibration Data Register 1 */
+ __IOM uint32_t CALR2; /*!< (@ 0x00000038) ADC Calibration Data Register 2 */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t SQR0; /*!< (@ 0x00000040) ADC Regular Sequence Register0 */
+ __IOM uint32_t SQR1; /*!< (@ 0x00000044) ADC Regular Sequence Register1 */
+ __IOM uint32_t SQR2; /*!< (@ 0x00000048) ADC Regular Sequence Register2 */
+ __IOM uint32_t SQR3; /*!< (@ 0x0000004C) ADC Regular Sequence Register3 */
+ __IOM uint32_t LR; /*!< (@ 0x00000050) ADC Regular Length Register */
+ __IOM uint32_t DR; /*!< (@ 0x00000054) ADC Regular Data Register */
+ __IOM uint32_t MAXDR; /*!< (@ 0x00000058) ADC Maximum Regular Data Register */
+ __IOM uint32_t MINDR; /*!< (@ 0x0000005C) ADC Minimum Regular Data Register */
+ __IOM uint32_t JSQR; /*!< (@ 0x00000060) ADC Injected Sequence Register */
+ __IOM uint32_t JLR; /*!< (@ 0x00000064) ADC Injected Length Register */
+ __IOM uint32_t MAXJDR; /*!< (@ 0x00000068) ADC Maximum Injected Data Register */
+ __IOM uint32_t MINJDR; /*!< (@ 0x0000006C) ADC Minimum Injected Data Register */
+ __IOM uint32_t JDR0; /*!< (@ 0x00000070) ADC Injected Data Register0 */
+ __IOM uint32_t JDR1; /*!< (@ 0x00000074) ADC Injected Data Register1 */
+ __IOM uint32_t JDR2; /*!< (@ 0x00000078) ADC Injected Data Register2 */
+ __IOM uint32_t JDR3; /*!< (@ 0x0000007C) ADC Injected Data Register3 */
+ __IOM uint32_t TR0; /*!< (@ 0x00000080) ADC Watchdog0 Threshold Register */
+ __IOM uint32_t TR1; /*!< (@ 0x00000084) ADC Watchdog1 Threshold Register */
+ __IOM uint32_t TR2; /*!< (@ 0x00000088) ADC Watchdog2 Threshold Register */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t AWD0CR; /*!< (@ 0x00000090) ADC Watchdog0 Control Register */
+ __IOM uint32_t AWD1CR; /*!< (@ 0x00000094) ADC Watchdog1 Control Register */
+ __IOM uint32_t AWD2CR; /*!< (@ 0x00000098) ADC Watchdog 2 Control Register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t OFR0; /*!< (@ 0x000000A0) ADC Offset Register0 */
+ __IOM uint32_t OFR1; /*!< (@ 0x000000A4) ADC Offset Register1 */
+ __IOM uint32_t OFR2; /*!< (@ 0x000000A8) ADC Offset Register2 */
+ __IOM uint32_t OFR3; /*!< (@ 0x000000AC) ADC Offset Register3 */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t GCR0; /*!< (@ 0x000000C0) ADC Gain Coeff Register0 */
+ __IOM uint32_t GCR1; /*!< (@ 0x000000C4) ADC Gain Coeff Register1 */
+ __IOM uint32_t GCR2; /*!< (@ 0x000000C8) ADC Gain Coeff Register2 */
+ __IOM uint32_t GCR3; /*!< (@ 0x000000CC) ADC Gain Coeff Register3 */
+ __IM uint32_t RESERVED7[12];
+ __IOM uint32_t DISR; /*!< (@ 0x00000100) ADC Data Interrupt Status Register */
+ __IOM uint32_t DIER; /*!< (@ 0x00000104) ADC Data Interrupt Enable Register */
+ __IM uint32_t RESERVED8[2];
+ __IOM uint32_t CDR0; /*!< (@ 0x00000110) ADC Channel Data Register0 */
+ __IOM uint32_t CDR1; /*!< (@ 0x00000114) ADC Channel Data Register1 */
+ __IOM uint32_t CDR2; /*!< (@ 0x00000118) ADC Channel Data Register2 */
+ __IOM uint32_t CDR3; /*!< (@ 0x0000011C) ADC Channel Data Register3 */
+ __IOM uint32_t CDR4; /*!< (@ 0x00000120) ADC Channel Data Register4 */
+ __IOM uint32_t CDR5; /*!< (@ 0x00000124) ADC Channel Data Register5 */
+ __IOM uint32_t CDR6; /*!< (@ 0x00000128) ADC Channel Data Register6 */
+ __IOM uint32_t CDR7; /*!< (@ 0x0000012C) ADC Channel Data Register7 */
+ __IOM uint32_t CDR8; /*!< (@ 0x00000130) ADC Channel Data Register8 */
+ __IOM uint32_t CDR9; /*!< (@ 0x00000134) ADC Channel Data Register9 */
+ __IOM uint32_t CDR10; /*!< (@ 0x00000138) ADC Channel Data Register10 */
+ __IOM uint32_t CDR11; /*!< (@ 0x0000013C) ADC Channel Data Register11 */
+ __IOM uint32_t CDR12; /*!< (@ 0x00000140) ADC Channel Data Register12 */
+ __IOM uint32_t CDR13; /*!< (@ 0x00000144) ADC Channel Data Register13 */
+ __IOM uint32_t CDR14; /*!< (@ 0x00000148) ADC Channel Data Register14 */
+ __IOM uint32_t CDR15; /*!< (@ 0x0000014C) ADC Channel Data Register15 */
+ __IOM uint32_t CDR16; /*!< (@ 0x00000150) ADC Channel Data Register16 */
+ __IOM uint32_t CDR17; /*!< (@ 0x00000154) ADC Channel Data Register17 */
+ __IOM uint32_t CDR18; /*!< (@ 0x00000158) ADC Channel Data Register18 */
+ __IOM uint32_t CDR19; /*!< (@ 0x0000015C) ADC Channel Data Register19 */
+ __IM uint32_t RESERVED9[8];
+ __IOM uint32_t HISR; /*!< (@ 0x00000180) ADC Half Interrupt Status Register */
+ __IOM uint32_t HIER; /*!< (@ 0x00000184) ADC Half Interrupt Enable Register */
+ __IOM uint32_t FISR; /*!< (@ 0x00000188) ADC Full Interrupt Status Register */
+ __IOM uint32_t FIER; /*!< (@ 0x0000018C) ADC Full Interrupt Enable Register */
+ __IOM uint32_t TCR0; /*!< (@ 0x00000190) ADC Transfer Control Register0 */
+ __IOM uint32_t TAR0; /*!< (@ 0x00000194) ADC Transfer Address Register0 */
+ __IOM uint32_t TLR0; /*!< (@ 0x00000198) ADC Transfer Length Register0 */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t TCR1; /*!< (@ 0x000001A0) ADC Transfer Control Register1 */
+ __IOM uint32_t TAR1; /*!< (@ 0x000001A4) ADC Transfer Address Register1 */
+ __IOM uint32_t TLR1; /*!< (@ 0x000001A8) ADC Transfer Length Register1 */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t TCR2; /*!< (@ 0x000001B0) ADC Transfer Control Register2 */
+ __IOM uint32_t TAR2; /*!< (@ 0x000001B4) ADC Transfer Address Register2 */
+ __IOM uint32_t TLR2; /*!< (@ 0x000001B8) ADC Transfer Length Register2 */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t TCR3; /*!< (@ 0x000001C0) ADC Transfer Control Register3 */
+ __IOM uint32_t TAR3; /*!< (@ 0x000001C4) ADC Transfer Address Register3 */
+ __IOM uint32_t TLR3; /*!< (@ 0x000001C8) ADC Transfer Length Register3 */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t TCR4; /*!< (@ 0x000001D0) ADC Transfer Control Register4 */
+ __IOM uint32_t TAR4; /*!< (@ 0x000001D4) ADC Transfer Address Register4 */
+ __IOM uint32_t TLR4; /*!< (@ 0x000001D8) ADC Transfer Length Register4 */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t TCR5; /*!< (@ 0x000001E0) ADC Transfer Control Register5 */
+ __IOM uint32_t TAR5; /*!< (@ 0x000001E4) ADC Transfer Address Register5 */
+ __IOM uint32_t TLR5; /*!< (@ 0x000001E8) ADC Transfer Length Register5 */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t TCR6; /*!< (@ 0x000001F0) ADC Transfer Control Register6 */
+ __IOM uint32_t TAR6; /*!< (@ 0x000001F4) ADC Transfer Address Register6 */
+ __IOM uint32_t TLR6; /*!< (@ 0x000001F8) ADC Transfer Length Register6 */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t TCR7; /*!< (@ 0x00000200) ADC Transfer Control Register7 */
+ __IOM uint32_t TAR7; /*!< (@ 0x00000204) ADC Transfer Address Register7 */
+ __IOM uint32_t TLR7; /*!< (@ 0x00000208) ADC Transfer Length Register7 */
+ __IM uint32_t RESERVED17;
+ __IOM uint32_t TCR8; /*!< (@ 0x00000210) ADC Transfer Control Register8 */
+ __IOM uint32_t TAR8; /*!< (@ 0x00000214) ADC Transfer Address Register8 */
+ __IOM uint32_t TLR8; /*!< (@ 0x00000218) ADC Transfer Length Register8 */
+ __IM uint32_t RESERVED18;
+ __IOM uint32_t TCR9; /*!< (@ 0x00000220) ADC Transfer Control Register9 */
+ __IOM uint32_t TAR9; /*!< (@ 0x00000224) ADC Transfer Address Register9 */
+ __IOM uint32_t TLR9; /*!< (@ 0x00000228) ADC Transfer Length Register9 */
+ __IM uint32_t RESERVED19;
+ __IOM uint32_t TCR10; /*!< (@ 0x00000230) ADC Transfer Control Register10 */
+ __IOM uint32_t TAR10; /*!< (@ 0x00000234) ADC Transfer Address Register10 */
+ __IOM uint32_t TLR10; /*!< (@ 0x00000238) ADC Transfer Length Register10 */
+ __IM uint32_t RESERVED20;
+ __IOM uint32_t TCR11; /*!< (@ 0x00000240) ADC Transfer Control Register11 */
+ __IOM uint32_t TAR11; /*!< (@ 0x00000244) ADC Transfer Address Register11 */
+ __IOM uint32_t TLR11; /*!< (@ 0x00000248) ADC Transfer Length Register11 */
+ __IM uint32_t RESERVED21;
+ __IOM uint32_t TCR12; /*!< (@ 0x00000250) ADC Transfer Control Register12 */
+ __IOM uint32_t TAR12; /*!< (@ 0x00000254) ADC Transfer Address Register12 */
+ __IOM uint32_t TLR12; /*!< (@ 0x00000258) ADC Transfer Length Register12 */
+ __IM uint32_t RESERVED22;
+ __IOM uint32_t TCR13; /*!< (@ 0x00000260) ADC Transfer Control Register13 */
+ __IOM uint32_t TAR13; /*!< (@ 0x00000264) ADC Transfer Address Register13 */
+ __IOM uint32_t TLR13; /*!< (@ 0x00000268) ADC Transfer Length Register13 */
+ __IM uint32_t RESERVED23;
+ __IOM uint32_t TCR14; /*!< (@ 0x00000270) ADC Transfer Control Register14 */
+ __IOM uint32_t TAR14; /*!< (@ 0x00000274) ADC Transfer Address Register14 */
+ __IOM uint32_t TLR14; /*!< (@ 0x00000278) ADC Transfer Length Register14 */
+ __IM uint32_t RESERVED24;
+ __IOM uint32_t TCR15; /*!< (@ 0x00000280) ADC Transfer Control Register15 */
+ __IOM uint32_t TAR15; /*!< (@ 0x00000284) ADC Transfer Address Register15 */
+ __IOM uint32_t TLR15; /*!< (@ 0x00000288) ADC Transfer Length Register15 */
+ __IM uint32_t RESERVED25;
+ __IOM uint32_t TCR16; /*!< (@ 0x00000290) ADC Transfer Control Register16 */
+ __IOM uint32_t TAR16; /*!< (@ 0x00000294) ADC Transfer Address Register16 */
+ __IOM uint32_t TLR16; /*!< (@ 0x00000298) ADC Transfer Length Register16 */
+ __IM uint32_t RESERVED26;
+ __IOM uint32_t TCR17; /*!< (@ 0x000002A0) ADC Transfer Control Register17 */
+ __IOM uint32_t TAR17; /*!< (@ 0x000002A4) ADC Transfer Address Register17 */
+ __IOM uint32_t TLR17; /*!< (@ 0x000002A8) ADC Transfer Length Register17 */
+ __IM uint32_t RESERVED27;
+ __IOM uint32_t TCR18; /*!< (@ 0x000002B0) ADC Transfer Control Register18 */
+ __IOM uint32_t TAR18; /*!< (@ 0x000002B4) ADC Transfer Address Register18 */
+ __IOM uint32_t TLR18; /*!< (@ 0x000002B8) ADC Transfer Length Register18 */
+ __IM uint32_t RESERVED28;
+ __IOM uint32_t TCR19; /*!< (@ 0x000002C0) ADC Transfer Control Register19 */
+ __IOM uint32_t TAR19; /*!< (@ 0x000002C4) ADC Transfer Address Register19 */
+ __IOM uint32_t TLR19; /*!< (@ 0x000002C8) ADC Transfer Length Register19 */
+ __IM uint32_t RESERVED29[13];
+ __IOM uint32_t CCR; /*!< (@ 0x00000300) ADC Common Control Registe */
+ __IOM uint32_t CSR; /*!< (@ 0x00000304) ADC Common Status Register */
+ __IOM uint32_t CDR; /*!< (@ 0x00000308) ADC Common Regular Data Register */
+} ADC0_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ADC1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief ADC1 (ADC1)
+ */
+
+typedef struct { /*!< (@ 0x40038400) ADC1 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) ADC Control Register */
+ __IOM uint32_t CFGR0; /*!< (@ 0x00000004) ADC Configuration Register0 */
+ __IOM uint32_t CFGR1; /*!< (@ 0x00000008) ADC Configuration Register1 */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) ADC Interrupt Status Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000014) ADC Interrupt Enable Register */
+ __IOM uint32_t SIGSEL; /*!< (@ 0x00000018) ADC Single-End Select Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t SMPR0; /*!< (@ 0x00000020) ADC Sample Time Register 0 */
+ __IOM uint32_t SMPR1; /*!< (@ 0x00000024) ADC Sample Time Register 1 */
+ __IOM uint32_t SMPR2; /*!< (@ 0x00000028) ADC Sample Time Register 2 */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t CALR0; /*!< (@ 0x00000030) ADC Calibration Data Register 0 */
+ __IOM uint32_t CALR1; /*!< (@ 0x00000034) ADC Calibration Data Register 1 */
+ __IOM uint32_t CALR2; /*!< (@ 0x00000038) ADC Calibration Data Register 2 */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t SQR0; /*!< (@ 0x00000040) ADC Regular Sequence Register0 */
+ __IOM uint32_t SQR1; /*!< (@ 0x00000044) ADC Regular Sequence Register1 */
+ __IOM uint32_t SQR2; /*!< (@ 0x00000048) ADC Regular Sequence Register2 */
+ __IOM uint32_t SQR3; /*!< (@ 0x0000004C) ADC Regular Sequence Register3 */
+ __IOM uint32_t LR; /*!< (@ 0x00000050) ADC Regular Length Register */
+ __IOM uint32_t DR; /*!< (@ 0x00000054) ADC Regular Data Register */
+ __IOM uint32_t MAXDR; /*!< (@ 0x00000058) ADC Maximum Regular Data Register */
+ __IOM uint32_t MINDR; /*!< (@ 0x0000005C) ADC Minimum Regular Data Register */
+ __IOM uint32_t JSQR; /*!< (@ 0x00000060) ADC Injected Sequence Register */
+ __IOM uint32_t JLR; /*!< (@ 0x00000064) ADC Injected Length Register */
+ __IOM uint32_t MAXJDR; /*!< (@ 0x00000068) ADC Maximum Injected Data Register */
+ __IOM uint32_t MINJDR; /*!< (@ 0x0000006C) ADC Minimum Injected Data Register */
+ __IOM uint32_t JDR0; /*!< (@ 0x00000070) ADC Injected Data Register0 */
+ __IOM uint32_t JDR1; /*!< (@ 0x00000074) ADC Injected Data Register1 */
+ __IOM uint32_t JDR2; /*!< (@ 0x00000078) ADC Injected Data Register2 */
+ __IOM uint32_t JDR3; /*!< (@ 0x0000007C) ADC Injected Data Register3 */
+ __IOM uint32_t TR0; /*!< (@ 0x00000080) ADC Watchdog0 Threshold Register */
+ __IOM uint32_t TR1; /*!< (@ 0x00000084) ADC Watchdog1 Threshold Register */
+ __IOM uint32_t TR2; /*!< (@ 0x00000088) ADC Watchdog2 Threshold Register */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t AWD0CR; /*!< (@ 0x00000090) ADC Watchdog0 Control Register */
+ __IOM uint32_t AWD1CR; /*!< (@ 0x00000094) ADC Watchdog1 Control Register */
+ __IOM uint32_t AWD2CR; /*!< (@ 0x00000098) ADC Watchdog 2 Control Register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t OFR0; /*!< (@ 0x000000A0) ADC Offset Register0 */
+ __IOM uint32_t OFR1; /*!< (@ 0x000000A4) ADC Offset Register1 */
+ __IOM uint32_t OFR2; /*!< (@ 0x000000A8) ADC Offset Register2 */
+ __IOM uint32_t OFR3; /*!< (@ 0x000000AC) ADC Offset Register3 */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t GCR0; /*!< (@ 0x000000C0) ADC Gain Coeff Register0 */
+ __IOM uint32_t GCR1; /*!< (@ 0x000000C4) ADC Gain Coeff Register1 */
+ __IOM uint32_t GCR2; /*!< (@ 0x000000C8) ADC Gain Coeff Register2 */
+ __IOM uint32_t GCR3; /*!< (@ 0x000000CC) ADC Gain Coeff Register3 */
+ __IM uint32_t RESERVED7[12];
+ __IOM uint32_t DISR; /*!< (@ 0x00000100) ADC Data Interrupt Status Register */
+ __IOM uint32_t DIER; /*!< (@ 0x00000104) ADC Data Interrupt Enable Register */
+ __IM uint32_t RESERVED8[2];
+ __IOM uint32_t CDR0; /*!< (@ 0x00000110) ADC Channel Data Register0 */
+ __IOM uint32_t CDR1; /*!< (@ 0x00000114) ADC Channel Data Register1 */
+ __IOM uint32_t CDR2; /*!< (@ 0x00000118) ADC Channel Data Register2 */
+ __IOM uint32_t CDR3; /*!< (@ 0x0000011C) ADC Channel Data Register3 */
+ __IOM uint32_t CDR4; /*!< (@ 0x00000120) ADC Channel Data Register4 */
+ __IOM uint32_t CDR5; /*!< (@ 0x00000124) ADC Channel Data Register5 */
+ __IOM uint32_t CDR6; /*!< (@ 0x00000128) ADC Channel Data Register6 */
+ __IOM uint32_t CDR7; /*!< (@ 0x0000012C) ADC Channel Data Register7 */
+ __IOM uint32_t CDR8; /*!< (@ 0x00000130) ADC Channel Data Register8 */
+ __IOM uint32_t CDR9; /*!< (@ 0x00000134) ADC Channel Data Register9 */
+ __IOM uint32_t CDR10; /*!< (@ 0x00000138) ADC Channel Data Register10 */
+ __IOM uint32_t CDR11; /*!< (@ 0x0000013C) ADC Channel Data Register11 */
+ __IOM uint32_t CDR12; /*!< (@ 0x00000140) ADC Channel Data Register12 */
+ __IOM uint32_t CDR13; /*!< (@ 0x00000144) ADC Channel Data Register13 */
+ __IOM uint32_t CDR14; /*!< (@ 0x00000148) ADC Channel Data Register14 */
+ __IOM uint32_t CDR15; /*!< (@ 0x0000014C) ADC Channel Data Register15 */
+ __IOM uint32_t CDR16; /*!< (@ 0x00000150) ADC Channel Data Register16 */
+ __IOM uint32_t CDR17; /*!< (@ 0x00000154) ADC Channel Data Register17 */
+ __IOM uint32_t CDR18; /*!< (@ 0x00000158) ADC Channel Data Register18 */
+ __IOM uint32_t CDR19; /*!< (@ 0x0000015C) ADC Channel Data Register19 */
+ __IM uint32_t RESERVED9[8];
+ __IOM uint32_t HISR; /*!< (@ 0x00000180) ADC Half Interrupt Status Register */
+ __IOM uint32_t HIER; /*!< (@ 0x00000184) ADC Half Interrupt Enable Register */
+ __IOM uint32_t FISR; /*!< (@ 0x00000188) ADC Full Interrupt Status Register */
+ __IOM uint32_t FIER; /*!< (@ 0x0000018C) ADC Full Interrupt Enable Register */
+ __IOM uint32_t TCR0; /*!< (@ 0x00000190) ADC Transfer Control Register0 */
+ __IOM uint32_t TAR0; /*!< (@ 0x00000194) ADC Transfer Address Register0 */
+ __IOM uint32_t TLR0; /*!< (@ 0x00000198) ADC Transfer Length Register0 */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t TCR1; /*!< (@ 0x000001A0) ADC Transfer Control Register1 */
+ __IOM uint32_t TAR1; /*!< (@ 0x000001A4) ADC Transfer Address Register1 */
+ __IOM uint32_t TLR1; /*!< (@ 0x000001A8) ADC Transfer Length Register1 */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t TCR2; /*!< (@ 0x000001B0) ADC Transfer Control Register2 */
+ __IOM uint32_t TAR2; /*!< (@ 0x000001B4) ADC Transfer Address Register2 */
+ __IOM uint32_t TLR2; /*!< (@ 0x000001B8) ADC Transfer Length Register2 */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t TCR3; /*!< (@ 0x000001C0) ADC Transfer Control Register3 */
+ __IOM uint32_t TAR3; /*!< (@ 0x000001C4) ADC Transfer Address Register3 */
+ __IOM uint32_t TLR3; /*!< (@ 0x000001C8) ADC Transfer Length Register3 */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t TCR4; /*!< (@ 0x000001D0) ADC Transfer Control Register4 */
+ __IOM uint32_t TAR4; /*!< (@ 0x000001D4) ADC Transfer Address Register4 */
+ __IOM uint32_t TLR4; /*!< (@ 0x000001D8) ADC Transfer Length Register4 */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t TCR5; /*!< (@ 0x000001E0) ADC Transfer Control Register5 */
+ __IOM uint32_t TAR5; /*!< (@ 0x000001E4) ADC Transfer Address Register5 */
+ __IOM uint32_t TLR5; /*!< (@ 0x000001E8) ADC Transfer Length Register5 */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t TCR6; /*!< (@ 0x000001F0) ADC Transfer Control Register6 */
+ __IOM uint32_t TAR6; /*!< (@ 0x000001F4) ADC Transfer Address Register6 */
+ __IOM uint32_t TLR6; /*!< (@ 0x000001F8) ADC Transfer Length Register6 */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t TCR7; /*!< (@ 0x00000200) ADC Transfer Control Register7 */
+ __IOM uint32_t TAR7; /*!< (@ 0x00000204) ADC Transfer Address Register7 */
+ __IOM uint32_t TLR7; /*!< (@ 0x00000208) ADC Transfer Length Register7 */
+ __IM uint32_t RESERVED17;
+ __IOM uint32_t TCR8; /*!< (@ 0x00000210) ADC Transfer Control Register8 */
+ __IOM uint32_t TAR8; /*!< (@ 0x00000214) ADC Transfer Address Register8 */
+ __IOM uint32_t TLR8; /*!< (@ 0x00000218) ADC Transfer Length Register8 */
+ __IM uint32_t RESERVED18;
+ __IOM uint32_t TCR9; /*!< (@ 0x00000220) ADC Transfer Control Register9 */
+ __IOM uint32_t TAR9; /*!< (@ 0x00000224) ADC Transfer Address Register9 */
+ __IOM uint32_t TLR9; /*!< (@ 0x00000228) ADC Transfer Length Register9 */
+ __IM uint32_t RESERVED19;
+ __IOM uint32_t TCR10; /*!< (@ 0x00000230) ADC Transfer Control Register10 */
+ __IOM uint32_t TAR10; /*!< (@ 0x00000234) ADC Transfer Address Register10 */
+ __IOM uint32_t TLR10; /*!< (@ 0x00000238) ADC Transfer Length Register10 */
+ __IM uint32_t RESERVED20;
+ __IOM uint32_t TCR11; /*!< (@ 0x00000240) ADC Transfer Control Register11 */
+ __IOM uint32_t TAR11; /*!< (@ 0x00000244) ADC Transfer Address Register11 */
+ __IOM uint32_t TLR11; /*!< (@ 0x00000248) ADC Transfer Length Register11 */
+ __IM uint32_t RESERVED21;
+ __IOM uint32_t TCR12; /*!< (@ 0x00000250) ADC Transfer Control Register12 */
+ __IOM uint32_t TAR12; /*!< (@ 0x00000254) ADC Transfer Address Register12 */
+ __IOM uint32_t TLR12; /*!< (@ 0x00000258) ADC Transfer Length Register12 */
+ __IM uint32_t RESERVED22;
+ __IOM uint32_t TCR13; /*!< (@ 0x00000260) ADC Transfer Control Register13 */
+ __IOM uint32_t TAR13; /*!< (@ 0x00000264) ADC Transfer Address Register13 */
+ __IOM uint32_t TLR13; /*!< (@ 0x00000268) ADC Transfer Length Register13 */
+ __IM uint32_t RESERVED23;
+ __IOM uint32_t TCR14; /*!< (@ 0x00000270) ADC Transfer Control Register14 */
+ __IOM uint32_t TAR14; /*!< (@ 0x00000274) ADC Transfer Address Register14 */
+ __IOM uint32_t TLR14; /*!< (@ 0x00000278) ADC Transfer Length Register14 */
+ __IM uint32_t RESERVED24;
+ __IOM uint32_t TCR15; /*!< (@ 0x00000280) ADC Transfer Control Register15 */
+ __IOM uint32_t TAR15; /*!< (@ 0x00000284) ADC Transfer Address Register15 */
+ __IOM uint32_t TLR15; /*!< (@ 0x00000288) ADC Transfer Length Register15 */
+ __IM uint32_t RESERVED25;
+ __IOM uint32_t TCR16; /*!< (@ 0x00000290) ADC Transfer Control Register16 */
+ __IOM uint32_t TAR16; /*!< (@ 0x00000294) ADC Transfer Address Register16 */
+ __IOM uint32_t TLR16; /*!< (@ 0x00000298) ADC Transfer Length Register16 */
+ __IM uint32_t RESERVED26;
+ __IOM uint32_t TCR17; /*!< (@ 0x000002A0) ADC Transfer Control Register17 */
+ __IOM uint32_t TAR17; /*!< (@ 0x000002A4) ADC Transfer Address Register17 */
+ __IOM uint32_t TLR17; /*!< (@ 0x000002A8) ADC Transfer Length Register17 */
+ __IM uint32_t RESERVED27;
+ __IOM uint32_t TCR18; /*!< (@ 0x000002B0) ADC Transfer Control Register18 */
+ __IOM uint32_t TAR18; /*!< (@ 0x000002B4) ADC Transfer Address Register18 */
+ __IOM uint32_t TLR18; /*!< (@ 0x000002B8) ADC Transfer Length Register18 */
+ __IM uint32_t RESERVED28;
+ __IOM uint32_t TCR19; /*!< (@ 0x000002C0) ADC Transfer Control Register19 */
+ __IOM uint32_t TAR19; /*!< (@ 0x000002C4) ADC Transfer Address Register19 */
+ __IOM uint32_t TLR19; /*!< (@ 0x000002C8) ADC Transfer Length Register19 */
+ __IM uint32_t RESERVED29[13];
+ __IOM uint32_t CCR; /*!< (@ 0x00000300) ADC Common Control Registe */
+ __IOM uint32_t CSR; /*!< (@ 0x00000304) ADC Common Status Register */
+ __IOM uint32_t CDR; /*!< (@ 0x00000308) ADC Common Regular Data Register */
+} ADC1_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ADC2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief ADC2 (ADC2)
+ */
+
+typedef struct { /*!< (@ 0x40038800) ADC2 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) ADC Control Register */
+ __IOM uint32_t CFGR0; /*!< (@ 0x00000004) ADC Configuration Register0 */
+ __IOM uint32_t CFGR1; /*!< (@ 0x00000008) ADC Configuration Register1 */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) ADC Interrupt Status Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000014) ADC Interrupt Enable Register */
+ __IOM uint32_t SIGSEL; /*!< (@ 0x00000018) ADC Single-End Select Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t SMPR0; /*!< (@ 0x00000020) ADC Sample Time Register 0 */
+ __IOM uint32_t SMPR1; /*!< (@ 0x00000024) ADC Sample Time Register 1 */
+ __IOM uint32_t SMPR2; /*!< (@ 0x00000028) ADC Sample Time Register 2 */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t CALR0; /*!< (@ 0x00000030) ADC Calibration Data Register 0 */
+ __IOM uint32_t CALR1; /*!< (@ 0x00000034) ADC Calibration Data Register 1 */
+ __IOM uint32_t CALR2; /*!< (@ 0x00000038) ADC Calibration Data Register 2 */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t SQR0; /*!< (@ 0x00000040) ADC Regular Sequence Register0 */
+ __IOM uint32_t SQR1; /*!< (@ 0x00000044) ADC Regular Sequence Register1 */
+ __IOM uint32_t SQR2; /*!< (@ 0x00000048) ADC Regular Sequence Register2 */
+ __IOM uint32_t SQR3; /*!< (@ 0x0000004C) ADC Regular Sequence Register3 */
+ __IOM uint32_t LR; /*!< (@ 0x00000050) ADC Regular Length Register */
+ __IOM uint32_t DR; /*!< (@ 0x00000054) ADC Regular Data Register */
+ __IOM uint32_t MAXDR; /*!< (@ 0x00000058) ADC Maximum Regular Data Register */
+ __IOM uint32_t MINDR; /*!< (@ 0x0000005C) ADC Minimum Regular Data Register */
+ __IOM uint32_t JSQR; /*!< (@ 0x00000060) ADC Injected Sequence Register */
+ __IOM uint32_t JLR; /*!< (@ 0x00000064) ADC Injected Length Register */
+ __IOM uint32_t MAXJDR; /*!< (@ 0x00000068) ADC Maximum Injected Data Register */
+ __IOM uint32_t MINJDR; /*!< (@ 0x0000006C) ADC Minimum Injected Data Register */
+ __IOM uint32_t JDR0; /*!< (@ 0x00000070) ADC Injected Data Register0 */
+ __IOM uint32_t JDR1; /*!< (@ 0x00000074) ADC Injected Data Register1 */
+ __IOM uint32_t JDR2; /*!< (@ 0x00000078) ADC Injected Data Register2 */
+ __IOM uint32_t JDR3; /*!< (@ 0x0000007C) ADC Injected Data Register3 */
+ __IOM uint32_t TR0; /*!< (@ 0x00000080) ADC Watchdog0 Threshold Register */
+ __IOM uint32_t TR1; /*!< (@ 0x00000084) ADC Watchdog1 Threshold Register */
+ __IOM uint32_t TR2; /*!< (@ 0x00000088) ADC Watchdog2 Threshold Register */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t AWD0CR; /*!< (@ 0x00000090) ADC Watchdog0 Control Register */
+ __IOM uint32_t AWD1CR; /*!< (@ 0x00000094) ADC Watchdog1 Control Register */
+ __IOM uint32_t AWD2CR; /*!< (@ 0x00000098) ADC Watchdog 2 Control Register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t OFR0; /*!< (@ 0x000000A0) ADC Offset Register0 */
+ __IOM uint32_t OFR1; /*!< (@ 0x000000A4) ADC Offset Register1 */
+ __IOM uint32_t OFR2; /*!< (@ 0x000000A8) ADC Offset Register2 */
+ __IOM uint32_t OFR3; /*!< (@ 0x000000AC) ADC Offset Register3 */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t GCR0; /*!< (@ 0x000000C0) ADC Gain Coeff Register0 */
+ __IOM uint32_t GCR1; /*!< (@ 0x000000C4) ADC Gain Coeff Register1 */
+ __IOM uint32_t GCR2; /*!< (@ 0x000000C8) ADC Gain Coeff Register2 */
+ __IOM uint32_t GCR3; /*!< (@ 0x000000CC) ADC Gain Coeff Register3 */
+ __IM uint32_t RESERVED7[12];
+ __IOM uint32_t DISR; /*!< (@ 0x00000100) ADC Data Interrupt Status Register */
+ __IOM uint32_t DIER; /*!< (@ 0x00000104) ADC Data Interrupt Enable Register */
+ __IM uint32_t RESERVED8[2];
+ __IOM uint32_t CDR0; /*!< (@ 0x00000110) ADC Channel Data Register0 */
+ __IOM uint32_t CDR1; /*!< (@ 0x00000114) ADC Channel Data Register1 */
+ __IOM uint32_t CDR2; /*!< (@ 0x00000118) ADC Channel Data Register2 */
+ __IOM uint32_t CDR3; /*!< (@ 0x0000011C) ADC Channel Data Register3 */
+ __IOM uint32_t CDR4; /*!< (@ 0x00000120) ADC Channel Data Register4 */
+ __IOM uint32_t CDR5; /*!< (@ 0x00000124) ADC Channel Data Register5 */
+ __IOM uint32_t CDR6; /*!< (@ 0x00000128) ADC Channel Data Register6 */
+ __IOM uint32_t CDR7; /*!< (@ 0x0000012C) ADC Channel Data Register7 */
+ __IOM uint32_t CDR8; /*!< (@ 0x00000130) ADC Channel Data Register8 */
+ __IOM uint32_t CDR9; /*!< (@ 0x00000134) ADC Channel Data Register9 */
+ __IOM uint32_t CDR10; /*!< (@ 0x00000138) ADC Channel Data Register10 */
+ __IOM uint32_t CDR11; /*!< (@ 0x0000013C) ADC Channel Data Register11 */
+ __IOM uint32_t CDR12; /*!< (@ 0x00000140) ADC Channel Data Register12 */
+ __IOM uint32_t CDR13; /*!< (@ 0x00000144) ADC Channel Data Register13 */
+ __IOM uint32_t CDR14; /*!< (@ 0x00000148) ADC Channel Data Register14 */
+ __IOM uint32_t CDR15; /*!< (@ 0x0000014C) ADC Channel Data Register15 */
+ __IOM uint32_t CDR16; /*!< (@ 0x00000150) ADC Channel Data Register16 */
+ __IOM uint32_t CDR17; /*!< (@ 0x00000154) ADC Channel Data Register17 */
+ __IOM uint32_t CDR18; /*!< (@ 0x00000158) ADC Channel Data Register18 */
+ __IOM uint32_t CDR19; /*!< (@ 0x0000015C) ADC Channel Data Register19 */
+ __IM uint32_t RESERVED9[8];
+ __IOM uint32_t HISR; /*!< (@ 0x00000180) ADC Half Interrupt Status Register */
+ __IOM uint32_t HIER; /*!< (@ 0x00000184) ADC Half Interrupt Enable Register */
+ __IOM uint32_t FISR; /*!< (@ 0x00000188) ADC Full Interrupt Status Register */
+ __IOM uint32_t FIER; /*!< (@ 0x0000018C) ADC Full Interrupt Enable Register */
+ __IOM uint32_t TCR0; /*!< (@ 0x00000190) ADC Transfer Control Register0 */
+ __IOM uint32_t TAR0; /*!< (@ 0x00000194) ADC Transfer Address Register0 */
+ __IOM uint32_t TLR0; /*!< (@ 0x00000198) ADC Transfer Length Register0 */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t TCR1; /*!< (@ 0x000001A0) ADC Transfer Control Register1 */
+ __IOM uint32_t TAR1; /*!< (@ 0x000001A4) ADC Transfer Address Register1 */
+ __IOM uint32_t TLR1; /*!< (@ 0x000001A8) ADC Transfer Length Register1 */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t TCR2; /*!< (@ 0x000001B0) ADC Transfer Control Register2 */
+ __IOM uint32_t TAR2; /*!< (@ 0x000001B4) ADC Transfer Address Register2 */
+ __IOM uint32_t TLR2; /*!< (@ 0x000001B8) ADC Transfer Length Register2 */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t TCR3; /*!< (@ 0x000001C0) ADC Transfer Control Register3 */
+ __IOM uint32_t TAR3; /*!< (@ 0x000001C4) ADC Transfer Address Register3 */
+ __IOM uint32_t TLR3; /*!< (@ 0x000001C8) ADC Transfer Length Register3 */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t TCR4; /*!< (@ 0x000001D0) ADC Transfer Control Register4 */
+ __IOM uint32_t TAR4; /*!< (@ 0x000001D4) ADC Transfer Address Register4 */
+ __IOM uint32_t TLR4; /*!< (@ 0x000001D8) ADC Transfer Length Register4 */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t TCR5; /*!< (@ 0x000001E0) ADC Transfer Control Register5 */
+ __IOM uint32_t TAR5; /*!< (@ 0x000001E4) ADC Transfer Address Register5 */
+ __IOM uint32_t TLR5; /*!< (@ 0x000001E8) ADC Transfer Length Register5 */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t TCR6; /*!< (@ 0x000001F0) ADC Transfer Control Register6 */
+ __IOM uint32_t TAR6; /*!< (@ 0x000001F4) ADC Transfer Address Register6 */
+ __IOM uint32_t TLR6; /*!< (@ 0x000001F8) ADC Transfer Length Register6 */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t TCR7; /*!< (@ 0x00000200) ADC Transfer Control Register7 */
+ __IOM uint32_t TAR7; /*!< (@ 0x00000204) ADC Transfer Address Register7 */
+ __IOM uint32_t TLR7; /*!< (@ 0x00000208) ADC Transfer Length Register7 */
+ __IM uint32_t RESERVED17;
+ __IOM uint32_t TCR8; /*!< (@ 0x00000210) ADC Transfer Control Register8 */
+ __IOM uint32_t TAR8; /*!< (@ 0x00000214) ADC Transfer Address Register8 */
+ __IOM uint32_t TLR8; /*!< (@ 0x00000218) ADC Transfer Length Register8 */
+ __IM uint32_t RESERVED18;
+ __IOM uint32_t TCR9; /*!< (@ 0x00000220) ADC Transfer Control Register9 */
+ __IOM uint32_t TAR9; /*!< (@ 0x00000224) ADC Transfer Address Register9 */
+ __IOM uint32_t TLR9; /*!< (@ 0x00000228) ADC Transfer Length Register9 */
+ __IM uint32_t RESERVED19;
+ __IOM uint32_t TCR10; /*!< (@ 0x00000230) ADC Transfer Control Register10 */
+ __IOM uint32_t TAR10; /*!< (@ 0x00000234) ADC Transfer Address Register10 */
+ __IOM uint32_t TLR10; /*!< (@ 0x00000238) ADC Transfer Length Register10 */
+ __IM uint32_t RESERVED20;
+ __IOM uint32_t TCR11; /*!< (@ 0x00000240) ADC Transfer Control Register11 */
+ __IOM uint32_t TAR11; /*!< (@ 0x00000244) ADC Transfer Address Register11 */
+ __IOM uint32_t TLR11; /*!< (@ 0x00000248) ADC Transfer Length Register11 */
+ __IM uint32_t RESERVED21;
+ __IOM uint32_t TCR12; /*!< (@ 0x00000250) ADC Transfer Control Register12 */
+ __IOM uint32_t TAR12; /*!< (@ 0x00000254) ADC Transfer Address Register12 */
+ __IOM uint32_t TLR12; /*!< (@ 0x00000258) ADC Transfer Length Register12 */
+ __IM uint32_t RESERVED22;
+ __IOM uint32_t TCR13; /*!< (@ 0x00000260) ADC Transfer Control Register13 */
+ __IOM uint32_t TAR13; /*!< (@ 0x00000264) ADC Transfer Address Register13 */
+ __IOM uint32_t TLR13; /*!< (@ 0x00000268) ADC Transfer Length Register13 */
+ __IM uint32_t RESERVED23;
+ __IOM uint32_t TCR14; /*!< (@ 0x00000270) ADC Transfer Control Register14 */
+ __IOM uint32_t TAR14; /*!< (@ 0x00000274) ADC Transfer Address Register14 */
+ __IOM uint32_t TLR14; /*!< (@ 0x00000278) ADC Transfer Length Register14 */
+ __IM uint32_t RESERVED24;
+ __IOM uint32_t TCR15; /*!< (@ 0x00000280) ADC Transfer Control Register15 */
+ __IOM uint32_t TAR15; /*!< (@ 0x00000284) ADC Transfer Address Register15 */
+ __IOM uint32_t TLR15; /*!< (@ 0x00000288) ADC Transfer Length Register15 */
+ __IM uint32_t RESERVED25;
+ __IOM uint32_t TCR16; /*!< (@ 0x00000290) ADC Transfer Control Register16 */
+ __IOM uint32_t TAR16; /*!< (@ 0x00000294) ADC Transfer Address Register16 */
+ __IOM uint32_t TLR16; /*!< (@ 0x00000298) ADC Transfer Length Register16 */
+ __IM uint32_t RESERVED26;
+ __IOM uint32_t TCR17; /*!< (@ 0x000002A0) ADC Transfer Control Register17 */
+ __IOM uint32_t TAR17; /*!< (@ 0x000002A4) ADC Transfer Address Register17 */
+ __IOM uint32_t TLR17; /*!< (@ 0x000002A8) ADC Transfer Length Register17 */
+ __IM uint32_t RESERVED27;
+ __IOM uint32_t TCR18; /*!< (@ 0x000002B0) ADC Transfer Control Register18 */
+ __IOM uint32_t TAR18; /*!< (@ 0x000002B4) ADC Transfer Address Register18 */
+ __IOM uint32_t TLR18; /*!< (@ 0x000002B8) ADC Transfer Length Register18 */
+ __IM uint32_t RESERVED28;
+ __IOM uint32_t TCR19; /*!< (@ 0x000002C0) ADC Transfer Control Register19 */
+ __IOM uint32_t TAR19; /*!< (@ 0x000002C4) ADC Transfer Address Register19 */
+ __IOM uint32_t TLR19; /*!< (@ 0x000002C8) ADC Transfer Length Register19 */
+ __IM uint32_t RESERVED29[13];
+ __IOM uint32_t CCR; /*!< (@ 0x00000300) ADC Common Control Registe */
+ __IOM uint32_t CSR; /*!< (@ 0x00000304) ADC Common Status Register */
+ __IOM uint32_t CDR; /*!< (@ 0x00000308) ADC Common Regular Data Register */
+} ADC2_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ADC3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief ADC3 (ADC3)
+ */
+
+typedef struct { /*!< (@ 0x40038C00) ADC3 Structure */
+ __IOM uint32_t CR; /*!< (@ 0x00000000) ADC Control Register */
+ __IOM uint32_t CFGR0; /*!< (@ 0x00000004) ADC Configuration Register0 */
+ __IOM uint32_t CFGR1; /*!< (@ 0x00000008) ADC Configuration Register1 */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) ADC Interrupt Status Register */
+ __IOM uint32_t IER; /*!< (@ 0x00000014) ADC Interrupt Enable Register */
+ __IOM uint32_t SIGSEL; /*!< (@ 0x00000018) ADC Single-End Select Register */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t SMPR0; /*!< (@ 0x00000020) ADC Sample Time Register 0 */
+ __IOM uint32_t SMPR1; /*!< (@ 0x00000024) ADC Sample Time Register 1 */
+ __IOM uint32_t SMPR2; /*!< (@ 0x00000028) ADC Sample Time Register 2 */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t CALR0; /*!< (@ 0x00000030) ADC Calibration Data Register 0 */
+ __IOM uint32_t CALR1; /*!< (@ 0x00000034) ADC Calibration Data Register 1 */
+ __IOM uint32_t CALR2; /*!< (@ 0x00000038) ADC Calibration Data Register 2 */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t SQR0; /*!< (@ 0x00000040) ADC Regular Sequence Register0 */
+ __IOM uint32_t SQR1; /*!< (@ 0x00000044) ADC Regular Sequence Register1 */
+ __IOM uint32_t SQR2; /*!< (@ 0x00000048) ADC Regular Sequence Register2 */
+ __IOM uint32_t SQR3; /*!< (@ 0x0000004C) ADC Regular Sequence Register3 */
+ __IOM uint32_t LR; /*!< (@ 0x00000050) ADC Regular Length Register */
+ __IOM uint32_t DR; /*!< (@ 0x00000054) ADC Regular Data Register */
+ __IOM uint32_t MAXDR; /*!< (@ 0x00000058) ADC Maximum Regular Data Register */
+ __IOM uint32_t MINDR; /*!< (@ 0x0000005C) ADC Minimum Regular Data Register */
+ __IOM uint32_t JSQR; /*!< (@ 0x00000060) ADC Injected Sequence Register */
+ __IOM uint32_t JLR; /*!< (@ 0x00000064) ADC Injected Length Register */
+ __IOM uint32_t MAXJDR; /*!< (@ 0x00000068) ADC Maximum Injected Data Register */
+ __IOM uint32_t MINJDR; /*!< (@ 0x0000006C) ADC Minimum Injected Data Register */
+ __IOM uint32_t JDR0; /*!< (@ 0x00000070) ADC Injected Data Register0 */
+ __IOM uint32_t JDR1; /*!< (@ 0x00000074) ADC Injected Data Register1 */
+ __IOM uint32_t JDR2; /*!< (@ 0x00000078) ADC Injected Data Register2 */
+ __IOM uint32_t JDR3; /*!< (@ 0x0000007C) ADC Injected Data Register3 */
+ __IOM uint32_t TR0; /*!< (@ 0x00000080) ADC Watchdog0 Threshold Register */
+ __IOM uint32_t TR1; /*!< (@ 0x00000084) ADC Watchdog1 Threshold Register */
+ __IOM uint32_t TR2; /*!< (@ 0x00000088) ADC Watchdog2 Threshold Register */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t AWD0CR; /*!< (@ 0x00000090) ADC Watchdog0 Control Register */
+ __IOM uint32_t AWD1CR; /*!< (@ 0x00000094) ADC Watchdog1 Control Register */
+ __IOM uint32_t AWD2CR; /*!< (@ 0x00000098) ADC Watchdog 2 Control Register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t OFR0; /*!< (@ 0x000000A0) ADC Offset Register0 */
+ __IOM uint32_t OFR1; /*!< (@ 0x000000A4) ADC Offset Register1 */
+ __IOM uint32_t OFR2; /*!< (@ 0x000000A8) ADC Offset Register2 */
+ __IOM uint32_t OFR3; /*!< (@ 0x000000AC) ADC Offset Register3 */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t GCR0; /*!< (@ 0x000000C0) ADC Gain Coeff Register0 */
+ __IOM uint32_t GCR1; /*!< (@ 0x000000C4) ADC Gain Coeff Register1 */
+ __IOM uint32_t GCR2; /*!< (@ 0x000000C8) ADC Gain Coeff Register2 */
+ __IOM uint32_t GCR3; /*!< (@ 0x000000CC) ADC Gain Coeff Register3 */
+ __IM uint32_t RESERVED7[12];
+ __IOM uint32_t DISR; /*!< (@ 0x00000100) ADC Data Interrupt Status Register */
+ __IOM uint32_t DIER; /*!< (@ 0x00000104) ADC Data Interrupt Enable Register */
+ __IM uint32_t RESERVED8[2];
+ __IOM uint32_t CDR0; /*!< (@ 0x00000110) ADC Channel Data Register0 */
+ __IOM uint32_t CDR1; /*!< (@ 0x00000114) ADC Channel Data Register1 */
+ __IOM uint32_t CDR2; /*!< (@ 0x00000118) ADC Channel Data Register2 */
+ __IOM uint32_t CDR3; /*!< (@ 0x0000011C) ADC Channel Data Register3 */
+ __IOM uint32_t CDR4; /*!< (@ 0x00000120) ADC Channel Data Register4 */
+ __IOM uint32_t CDR5; /*!< (@ 0x00000124) ADC Channel Data Register5 */
+ __IOM uint32_t CDR6; /*!< (@ 0x00000128) ADC Channel Data Register6 */
+ __IOM uint32_t CDR7; /*!< (@ 0x0000012C) ADC Channel Data Register7 */
+ __IOM uint32_t CDR8; /*!< (@ 0x00000130) ADC Channel Data Register8 */
+ __IOM uint32_t CDR9; /*!< (@ 0x00000134) ADC Channel Data Register9 */
+ __IOM uint32_t CDR10; /*!< (@ 0x00000138) ADC Channel Data Register10 */
+ __IOM uint32_t CDR11; /*!< (@ 0x0000013C) ADC Channel Data Register11 */
+ __IOM uint32_t CDR12; /*!< (@ 0x00000140) ADC Channel Data Register12 */
+ __IOM uint32_t CDR13; /*!< (@ 0x00000144) ADC Channel Data Register13 */
+ __IOM uint32_t CDR14; /*!< (@ 0x00000148) ADC Channel Data Register14 */
+ __IOM uint32_t CDR15; /*!< (@ 0x0000014C) ADC Channel Data Register15 */
+ __IOM uint32_t CDR16; /*!< (@ 0x00000150) ADC Channel Data Register16 */
+ __IOM uint32_t CDR17; /*!< (@ 0x00000154) ADC Channel Data Register17 */
+ __IOM uint32_t CDR18; /*!< (@ 0x00000158) ADC Channel Data Register18 */
+ __IOM uint32_t CDR19; /*!< (@ 0x0000015C) ADC Channel Data Register19 */
+ __IM uint32_t RESERVED9[8];
+ __IOM uint32_t HISR; /*!< (@ 0x00000180) ADC Half Interrupt Status Register */
+ __IOM uint32_t HIER; /*!< (@ 0x00000184) ADC Half Interrupt Enable Register */
+ __IOM uint32_t FISR; /*!< (@ 0x00000188) ADC Full Interrupt Status Register */
+ __IOM uint32_t FIER; /*!< (@ 0x0000018C) ADC Full Interrupt Enable Register */
+ __IOM uint32_t TCR0; /*!< (@ 0x00000190) ADC Transfer Control Register0 */
+ __IOM uint32_t TAR0; /*!< (@ 0x00000194) ADC Transfer Address Register0 */
+ __IOM uint32_t TLR0; /*!< (@ 0x00000198) ADC Transfer Length Register0 */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t TCR1; /*!< (@ 0x000001A0) ADC Transfer Control Register1 */
+ __IOM uint32_t TAR1; /*!< (@ 0x000001A4) ADC Transfer Address Register1 */
+ __IOM uint32_t TLR1; /*!< (@ 0x000001A8) ADC Transfer Length Register1 */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t TCR2; /*!< (@ 0x000001B0) ADC Transfer Control Register2 */
+ __IOM uint32_t TAR2; /*!< (@ 0x000001B4) ADC Transfer Address Register2 */
+ __IOM uint32_t TLR2; /*!< (@ 0x000001B8) ADC Transfer Length Register2 */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t TCR3; /*!< (@ 0x000001C0) ADC Transfer Control Register3 */
+ __IOM uint32_t TAR3; /*!< (@ 0x000001C4) ADC Transfer Address Register3 */
+ __IOM uint32_t TLR3; /*!< (@ 0x000001C8) ADC Transfer Length Register3 */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t TCR4; /*!< (@ 0x000001D0) ADC Transfer Control Register4 */
+ __IOM uint32_t TAR4; /*!< (@ 0x000001D4) ADC Transfer Address Register4 */
+ __IOM uint32_t TLR4; /*!< (@ 0x000001D8) ADC Transfer Length Register4 */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t TCR5; /*!< (@ 0x000001E0) ADC Transfer Control Register5 */
+ __IOM uint32_t TAR5; /*!< (@ 0x000001E4) ADC Transfer Address Register5 */
+ __IOM uint32_t TLR5; /*!< (@ 0x000001E8) ADC Transfer Length Register5 */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t TCR6; /*!< (@ 0x000001F0) ADC Transfer Control Register6 */
+ __IOM uint32_t TAR6; /*!< (@ 0x000001F4) ADC Transfer Address Register6 */
+ __IOM uint32_t TLR6; /*!< (@ 0x000001F8) ADC Transfer Length Register6 */
+ __IM uint32_t RESERVED16;
+ __IOM uint32_t TCR7; /*!< (@ 0x00000200) ADC Transfer Control Register7 */
+ __IOM uint32_t TAR7; /*!< (@ 0x00000204) ADC Transfer Address Register7 */
+ __IOM uint32_t TLR7; /*!< (@ 0x00000208) ADC Transfer Length Register7 */
+ __IM uint32_t RESERVED17;
+ __IOM uint32_t TCR8; /*!< (@ 0x00000210) ADC Transfer Control Register8 */
+ __IOM uint32_t TAR8; /*!< (@ 0x00000214) ADC Transfer Address Register8 */
+ __IOM uint32_t TLR8; /*!< (@ 0x00000218) ADC Transfer Length Register8 */
+ __IM uint32_t RESERVED18;
+ __IOM uint32_t TCR9; /*!< (@ 0x00000220) ADC Transfer Control Register9 */
+ __IOM uint32_t TAR9; /*!< (@ 0x00000224) ADC Transfer Address Register9 */
+ __IOM uint32_t TLR9; /*!< (@ 0x00000228) ADC Transfer Length Register9 */
+ __IM uint32_t RESERVED19;
+ __IOM uint32_t TCR10; /*!< (@ 0x00000230) ADC Transfer Control Register10 */
+ __IOM uint32_t TAR10; /*!< (@ 0x00000234) ADC Transfer Address Register10 */
+ __IOM uint32_t TLR10; /*!< (@ 0x00000238) ADC Transfer Length Register10 */
+ __IM uint32_t RESERVED20;
+ __IOM uint32_t TCR11; /*!< (@ 0x00000240) ADC Transfer Control Register11 */
+ __IOM uint32_t TAR11; /*!< (@ 0x00000244) ADC Transfer Address Register11 */
+ __IOM uint32_t TLR11; /*!< (@ 0x00000248) ADC Transfer Length Register11 */
+ __IM uint32_t RESERVED21;
+ __IOM uint32_t TCR12; /*!< (@ 0x00000250) ADC Transfer Control Register12 */
+ __IOM uint32_t TAR12; /*!< (@ 0x00000254) ADC Transfer Address Register12 */
+ __IOM uint32_t TLR12; /*!< (@ 0x00000258) ADC Transfer Length Register12 */
+ __IM uint32_t RESERVED22;
+ __IOM uint32_t TCR13; /*!< (@ 0x00000260) ADC Transfer Control Register13 */
+ __IOM uint32_t TAR13; /*!< (@ 0x00000264) ADC Transfer Address Register13 */
+ __IOM uint32_t TLR13; /*!< (@ 0x00000268) ADC Transfer Length Register13 */
+ __IM uint32_t RESERVED23;
+ __IOM uint32_t TCR14; /*!< (@ 0x00000270) ADC Transfer Control Register14 */
+ __IOM uint32_t TAR14; /*!< (@ 0x00000274) ADC Transfer Address Register14 */
+ __IOM uint32_t TLR14; /*!< (@ 0x00000278) ADC Transfer Length Register14 */
+ __IM uint32_t RESERVED24;
+ __IOM uint32_t TCR15; /*!< (@ 0x00000280) ADC Transfer Control Register15 */
+ __IOM uint32_t TAR15; /*!< (@ 0x00000284) ADC Transfer Address Register15 */
+ __IOM uint32_t TLR15; /*!< (@ 0x00000288) ADC Transfer Length Register15 */
+ __IM uint32_t RESERVED25;
+ __IOM uint32_t TCR16; /*!< (@ 0x00000290) ADC Transfer Control Register16 */
+ __IOM uint32_t TAR16; /*!< (@ 0x00000294) ADC Transfer Address Register16 */
+ __IOM uint32_t TLR16; /*!< (@ 0x00000298) ADC Transfer Length Register16 */
+ __IM uint32_t RESERVED26;
+ __IOM uint32_t TCR17; /*!< (@ 0x000002A0) ADC Transfer Control Register17 */
+ __IOM uint32_t TAR17; /*!< (@ 0x000002A4) ADC Transfer Address Register17 */
+ __IOM uint32_t TLR17; /*!< (@ 0x000002A8) ADC Transfer Length Register17 */
+ __IM uint32_t RESERVED27;
+ __IOM uint32_t TCR18; /*!< (@ 0x000002B0) ADC Transfer Control Register18 */
+ __IOM uint32_t TAR18; /*!< (@ 0x000002B4) ADC Transfer Address Register18 */
+ __IOM uint32_t TLR18; /*!< (@ 0x000002B8) ADC Transfer Length Register18 */
+ __IM uint32_t RESERVED28;
+ __IOM uint32_t TCR19; /*!< (@ 0x000002C0) ADC Transfer Control Register19 */
+ __IOM uint32_t TAR19; /*!< (@ 0x000002C4) ADC Transfer Address Register19 */
+ __IOM uint32_t TLR19; /*!< (@ 0x000002C8) ADC Transfer Length Register19 */
+ __IM uint32_t RESERVED29[13];
+ __IOM uint32_t CCR; /*!< (@ 0x00000300) ADC Common Control Registe */
+ __IOM uint32_t CSR; /*!< (@ 0x00000304) ADC Common Status Register */
+ __IOM uint32_t CDR; /*!< (@ 0x00000308) ADC Common Regular Data Register */
+} ADC3_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR6 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR6 (TMR6)
+ */
+
+typedef struct { /*!< (@ 0x4000E000) TMR6 Structure */
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Compare Mode Register */
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Compare Enable Register */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+ __IM uint32_t RESERVED4[4];
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Compare Register */
+} TMR6_Type; /*!< Size = 84 (0x54) */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+#define XIF_BASE 0x40016000UL
+#define WWDG_BASE 0x4000D000UL
+#define USB_BASE 0x40035000UL
+#define UART0_BASE 0x40003000UL
+#define UART1_BASE 0x40004000UL
+#define UART2_BASE 0x40005000UL
+#define UART3_BASE 0x40010000UL
+#define UART4_BASE 0x40011000UL
+#define SYSCTRL_BASE 0x40021000UL
+#define SPI0_BASE 0x40012000UL
+#define SPI1_BASE 0x40013000UL
+#define RCU_BASE 0x40020000UL
+#define QEI0_BASE 0x4002D000UL
+#define QEI1_BASE 0x4002E000UL
+#define QEI2_BASE 0x4002F000UL
+#define PDM0_BASE 0x40017000UL
+#define PDM1_BASE 0x40017100UL
+#define PDM2_BASE 0x40017200UL
+#define PDM3_BASE 0x40017300UL
+#define IWDG_BASE 0x4000C000UL
+#define IIR0_BASE 0x4003E000UL
+#define IIR1_BASE 0x4003E100UL
+#define IIR2_BASE 0x4003E200UL
+#define IIR3_BASE 0x4003E300UL
+#define IIR4_BASE 0x4003E400UL
+#define IIR5_BASE 0x4003E500UL
+#define I2C0_BASE 0x40000000UL
+#define I2C1_BASE 0x40001000UL
+#define I2C2_BASE 0x40002000UL
+#define HRPWM_SLV0_BASE 0x4003B100UL
+#define HRPWM_SLV1_BASE 0x4003B200UL
+#define HRPWM_SLV2_BASE 0x4003B300UL
+#define HRPWM_SLV3_BASE 0x4003B400UL
+#define HRPWM_SLV4_BASE 0x4003B500UL
+#define HRPWM_SLV5_BASE 0x4003B600UL
+#define HRPWM_SLV6_BASE 0x4003B700UL
+#define HRPWM_SLV7_BASE 0x4003B800UL
+#define HRPWM_COM_BASE 0x4003BF00UL
+#define HRPWM_MST_BASE 0x4003B000UL
+#define TMR3_BASE 0x4002A000UL
+#define TMR4_BASE 0x4002B000UL
+#define TMR0_BASE 0x40018000UL
+#define TMR1_BASE 0x40019000UL
+#define TMR2_BASE 0x4001A000UL
+#define GPIOA_BASE 0x40024000UL
+#define GPIOB_BASE 0x40025000UL
+#define GPIOC_BASE 0x40026000UL
+#define GPIOD_BASE 0x40027000UL
+#define GPIOE_BASE 0x40028000UL
+#define GPIOF_BASE 0x40029000UL
+#define FLASH_BASE 0x40023000UL
+#define DMA0_BASE 0x40022000UL
+#define DMA1_BASE 0x40022020UL
+#define DMA2_BASE 0x40022040UL
+#define DMA3_BASE 0x40022060UL
+#define DMA4_BASE 0x40022080UL
+#define DMA5_BASE 0x400220A0UL
+#define DAC0_BASE 0x40039000UL
+#define DAC1_BASE 0x40039100UL
+#define DAC2_BASE 0x40039200UL
+#define DAC3_BASE 0x40039300UL
+#define DAC4_BASE 0x40039400UL
+#define DAC5_BASE 0x40039500UL
+#define DAC6_BASE 0x40039600UL
+#define DAC7_BASE 0x40039700UL
+#define DAC8_BASE 0x40039800UL
+#define CORDIC_BASE 0x4003F000UL
+#define CMP0_BASE 0x4003A000UL
+#define CMP1_BASE 0x4003A100UL
+#define CMP2_BASE 0x4003A200UL
+#define CMP3_BASE 0x4003A300UL
+#define CMP4_BASE 0x4003A400UL
+#define CMP5_BASE 0x4003A500UL
+#define CMP6_BASE 0x4003A600UL
+#define CMP7_BASE 0x4003A700UL
+#define CMP8_BASE 0x4003A800UL
+#define CAN0_BASE 0x40014000UL
+#define CAN1_BASE 0x40015000UL
+#define TMR7_BASE 0x40008000UL
+#define TMR8_BASE 0x40009000UL
+#define TMR9_BASE 0x40030000UL
+#define TMR10_BASE 0x40031000UL
+#define ADC0_BASE 0x40038000UL
+#define ADC1_BASE 0x40038400UL
+#define ADC2_BASE 0x40038800UL
+#define ADC3_BASE 0x40038C00UL
+#define TMR6_BASE 0x4000E000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+#define XIF ((XIF_Type*) XIF_BASE)
+#define WWDG ((WWDG_Type*) WWDG_BASE)
+#define USB ((USB_Type*) USB_BASE)
+#define UART0 ((UART0_Type*) UART0_BASE)
+#define UART1 ((UART1_Type*) UART1_BASE)
+#define UART2 ((UART2_Type*) UART2_BASE)
+#define UART3 ((UART3_Type*) UART3_BASE)
+#define UART4 ((UART4_Type*) UART4_BASE)
+#define SYSCTRL ((SYSCTRL_Type*) SYSCTRL_BASE)
+#define SPI0 ((SPI0_Type*) SPI0_BASE)
+#define SPI1 ((SPI1_Type*) SPI1_BASE)
+#define RCU ((RCU_Type*) RCU_BASE)
+#define QEI0 ((QEI0_Type*) QEI0_BASE)
+#define QEI1 ((QEI1_Type*) QEI1_BASE)
+#define QEI2 ((QEI2_Type*) QEI2_BASE)
+#define PDM0 ((PDM0_Type*) PDM0_BASE)
+#define PDM1 ((PDM1_Type*) PDM1_BASE)
+#define PDM2 ((PDM2_Type*) PDM2_BASE)
+#define PDM3 ((PDM3_Type*) PDM3_BASE)
+#define IWDG ((IWDG_Type*) IWDG_BASE)
+#define IIR0 ((IIR0_Type*) IIR0_BASE)
+#define IIR1 ((IIR1_Type*) IIR1_BASE)
+#define IIR2 ((IIR2_Type*) IIR2_BASE)
+#define IIR3 ((IIR3_Type*) IIR3_BASE)
+#define IIR4 ((IIR4_Type*) IIR4_BASE)
+#define IIR5 ((IIR5_Type*) IIR5_BASE)
+#define I2C0 ((I2C0_Type*) I2C0_BASE)
+#define I2C1 ((I2C1_Type*) I2C1_BASE)
+#define I2C2 ((I2C2_Type*) I2C2_BASE)
+#define HRPWM_SLV0 ((HRPWM_SLV0_Type*) HRPWM_SLV0_BASE)
+#define HRPWM_SLV1 ((HRPWM_SLV1_Type*) HRPWM_SLV1_BASE)
+#define HRPWM_SLV2 ((HRPWM_SLV2_Type*) HRPWM_SLV2_BASE)
+#define HRPWM_SLV3 ((HRPWM_SLV3_Type*) HRPWM_SLV3_BASE)
+#define HRPWM_SLV4 ((HRPWM_SLV4_Type*) HRPWM_SLV4_BASE)
+#define HRPWM_SLV5 ((HRPWM_SLV5_Type*) HRPWM_SLV5_BASE)
+#define HRPWM_SLV6 ((HRPWM_SLV6_Type*) HRPWM_SLV6_BASE)
+#define HRPWM_SLV7 ((HRPWM_SLV7_Type*) HRPWM_SLV7_BASE)
+#define HRPWM_COM ((HRPWM_COM_Type*) HRPWM_COM_BASE)
+#define HRPWM_MST ((HRPWM_MST_Type*) HRPWM_MST_BASE)
+#define TMR3 ((TMR3_Type*) TMR3_BASE)
+#define TMR4 ((TMR4_Type*) TMR4_BASE)
+#define TMR0 ((TMR0_Type*) TMR0_BASE)
+#define TMR1 ((TMR1_Type*) TMR1_BASE)
+#define TMR2 ((TMR2_Type*) TMR2_BASE)
+#define GPIOA ((GPIOA_Type*) GPIOA_BASE)
+#define GPIOB ((GPIOB_Type*) GPIOB_BASE)
+#define GPIOC ((GPIOC_Type*) GPIOC_BASE)
+#define GPIOD ((GPIOD_Type*) GPIOD_BASE)
+#define GPIOE ((GPIOE_Type*) GPIOE_BASE)
+#define GPIOF ((GPIOF_Type*) GPIOF_BASE)
+#define FLASH ((FLASH_Type*) FLASH_BASE)
+#define DMA0 ((DMA0_Type*) DMA0_BASE)
+#define DMA1 ((DMA1_Type*) DMA1_BASE)
+#define DMA2 ((DMA2_Type*) DMA2_BASE)
+#define DMA3 ((DMA3_Type*) DMA3_BASE)
+#define DMA4 ((DMA4_Type*) DMA4_BASE)
+#define DMA5 ((DMA5_Type*) DMA5_BASE)
+#define DAC0 ((DAC0_Type*) DAC0_BASE)
+#define DAC1 ((DAC1_Type*) DAC1_BASE)
+#define DAC2 ((DAC2_Type*) DAC2_BASE)
+#define DAC3 ((DAC3_Type*) DAC3_BASE)
+#define DAC4 ((DAC4_Type*) DAC4_BASE)
+#define DAC5 ((DAC5_Type*) DAC5_BASE)
+#define DAC6 ((DAC6_Type*) DAC6_BASE)
+#define DAC7 ((DAC7_Type*) DAC7_BASE)
+#define DAC8 ((DAC8_Type*) DAC8_BASE)
+#define CORDIC ((CORDIC_Type*) CORDIC_BASE)
+#define CMP0 ((CMP0_Type*) CMP0_BASE)
+#define CMP1 ((CMP1_Type*) CMP1_BASE)
+#define CMP2 ((CMP2_Type*) CMP2_BASE)
+#define CMP3 ((CMP3_Type*) CMP3_BASE)
+#define CMP4 ((CMP4_Type*) CMP4_BASE)
+#define CMP5 ((CMP5_Type*) CMP5_BASE)
+#define CMP6 ((CMP6_Type*) CMP6_BASE)
+#define CMP7 ((CMP7_Type*) CMP7_BASE)
+#define CMP8 ((CMP8_Type*) CMP8_BASE)
+#define CAN0 ((CAN0_Type*) CAN0_BASE)
+#define CAN1 ((CAN1_Type*) CAN1_BASE)
+#define TMR7 ((TMR7_Type*) TMR7_BASE)
+#define TMR8 ((TMR8_Type*) TMR8_BASE)
+#define TMR9 ((TMR9_Type*) TMR9_BASE)
+#define TMR10 ((TMR10_Type*) TMR10_BASE)
+#define ADC0 ((ADC0_Type*) ADC0_BASE)
+#define ADC1 ((ADC1_Type*) ADC1_BASE)
+#define ADC2 ((ADC2_Type*) ADC2_BASE)
+#define ADC3 ((ADC3_Type*) ADC3_BASE)
+#define TMR6 ((TMR6_Type*) TMR6_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+
+/* ========================================= End of section using anonymous unions ========================================= */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Pos/Mask Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup PosMask_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ XIF ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define XIF_ENABLE_DIR_Pos (5UL) /*!< DIR (Bit 5) */
+#define XIF_ENABLE_DIR_Msk (0x20UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define XIF_ENABLE_TXDEN_Pos (4UL) /*!< TXDEN (Bit 4) */
+#define XIF_ENABLE_TXDEN_Msk (0x10UL) /*!< TXDEN (Bitfield-Mask: 0x01) */
+#define XIF_ENABLE_RELOAD_Pos (3UL) /*!< RELOAD (Bit 3) */
+#define XIF_ENABLE_RELOAD_Msk (0x8UL) /*!< RELOAD (Bitfield-Mask: 0x01) */
+#define XIF_ENABLE_SRST_Pos (2UL) /*!< SRST (Bit 2) */
+#define XIF_ENABLE_SRST_Msk (0x4UL) /*!< SRST (Bitfield-Mask: 0x01) */
+#define XIF_ENABLE_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */
+#define XIF_ENABLE_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+#define XIF_ENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
+#define XIF_ENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define XIF_CTRL_TXDIE_Pos (26UL) /*!< TXDIE (Bit 26) */
+#define XIF_CTRL_TXDIE_Msk (0x4000000UL) /*!< TXDIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_TXEIE_Pos (24UL) /*!< TXEIE (Bit 24) */
+#define XIF_CTRL_TXEIE_Msk (0x1000000UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_TXFTLR_Pos (20UL) /*!< TXFTLR (Bit 20) */
+#define XIF_CTRL_TXFTLR_Msk (0x700000UL) /*!< TXFTLR (Bitfield-Mask: 0x07) */
+#define XIF_CTRL_DCS_Pos (16UL) /*!< DCS (Bit 16) */
+#define XIF_CTRL_DCS_Msk (0x70000UL) /*!< DCS (Bitfield-Mask: 0x07) */
+#define XIF_CTRL_BTOIE_Pos (15UL) /*!< BTOIE (Bit 15) */
+#define XIF_CTRL_BTOIE_Msk (0x8000UL) /*!< BTOIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_RXDIE_Pos (14UL) /*!< RXDIE (Bit 14) */
+#define XIF_CTRL_RXDIE_Msk (0x4000UL) /*!< RXDIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_RXOFIE_Pos (13UL) /*!< RXOFIE (Bit 13) */
+#define XIF_CTRL_RXOFIE_Msk (0x2000UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_RXFIE_Pos (12UL) /*!< RXFIE (Bit 12) */
+#define XIF_CTRL_RXFIE_Msk (0x1000UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_RXFTLR_Pos (8UL) /*!< RXFTLR (Bit 8) */
+#define XIF_CTRL_RXFTLR_Msk (0x700UL) /*!< RXFTLR (Bitfield-Mask: 0x07) */
+#define XIF_CTRL_DCNT_Pos (0UL) /*!< DCNT (Bit 0) */
+#define XIF_CTRL_DCNT_Msk (0xffUL) /*!< DCNT (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMING ========================================================= */
+#define XIF_TIMING_RDHTIME_Pos (24UL) /*!< RDHTIME (Bit 24) */
+#define XIF_TIMING_RDHTIME_Msk (0xff000000UL) /*!< RDHTIME (Bitfield-Mask: 0xff) */
+#define XIF_TIMING_RDLTIME_Pos (16UL) /*!< RDLTIME (Bit 16) */
+#define XIF_TIMING_RDLTIME_Msk (0xff0000UL) /*!< RDLTIME (Bitfield-Mask: 0xff) */
+#define XIF_TIMING_CONLTIME_Pos (8UL) /*!< CONLTIME (Bit 8) */
+#define XIF_TIMING_CONLTIME_Msk (0xff00UL) /*!< CONLTIME (Bitfield-Mask: 0xff) */
+#define XIF_TIMING_RSTTIME_Pos (0UL) /*!< RSTTIME (Bit 0) */
+#define XIF_TIMING_RSTTIME_Msk (0xffUL) /*!< RSTTIME (Bitfield-Mask: 0xff) */
+/* ========================================================== TO =========================================================== */
+#define XIF_TO_PTOT_Pos (0UL) /*!< PTOT (Bit 0) */
+#define XIF_TO_PTOT_Msk (0xffffUL) /*!< PTOT (Bitfield-Mask: 0xffff) */
+/* ========================================================= DATA ========================================================== */
+#define XIF_DATA_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+#define XIF_DATA_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+/* ========================================================== ISR ========================================================== */
+#define XIF_ISR_TFF_Pos (21UL) /*!< TFF (Bit 21) */
+#define XIF_ISR_TFF_Msk (0x200000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define XIF_ISR_TFE_Pos (20UL) /*!< TFE (Bit 20) */
+#define XIF_ISR_TFE_Msk (0x100000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define XIF_ISR_TXDI_Pos (18UL) /*!< TXDI (Bit 18) */
+#define XIF_ISR_TXDI_Msk (0x40000UL) /*!< TXDI (Bitfield-Mask: 0x01) */
+#define XIF_ISR_TXEI_Pos (16UL) /*!< TXEI (Bit 16) */
+#define XIF_ISR_TXEI_Msk (0x10000UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define XIF_ISR_TXFLR_Pos (12UL) /*!< TXFLR (Bit 12) */
+#define XIF_ISR_TXFLR_Msk (0xf000UL) /*!< TXFLR (Bitfield-Mask: 0x0f) */
+#define XIF_ISR_RXFLR_Pos (8UL) /*!< RXFLR (Bit 8) */
+#define XIF_ISR_RXFLR_Msk (0xf00UL) /*!< RXFLR (Bitfield-Mask: 0x0f) */
+#define XIF_ISR_FF_Pos (5UL) /*!< FF (Bit 5) */
+#define XIF_ISR_FF_Msk (0x20UL) /*!< FF (Bitfield-Mask: 0x01) */
+#define XIF_ISR_FE_Pos (4UL) /*!< FE (Bit 4) */
+#define XIF_ISR_FE_Msk (0x10UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define XIF_ISR_BTOI_Pos (3UL) /*!< BTOI (Bit 3) */
+#define XIF_ISR_BTOI_Msk (0x8UL) /*!< BTOI (Bitfield-Mask: 0x01) */
+#define XIF_ISR_RXDI_Pos (2UL) /*!< RXDI (Bit 2) */
+#define XIF_ISR_RXDI_Msk (0x4UL) /*!< RXDI (Bitfield-Mask: 0x01) */
+#define XIF_ISR_RXOFI_Pos (1UL) /*!< RXOFI (Bit 1) */
+#define XIF_ISR_RXOFI_Msk (0x2UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define XIF_ISR_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define XIF_ISR_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ========================================================= WDATA ========================================================= */
+#define XIF_WDATA_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */
+#define XIF_WDATA_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ WWDG ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define WWDG_CR_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */
+#define WWDG_CR_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */
+#define WWDG_CR_WEN_Pos (0UL) /*!< WEN (Bit 0) */
+#define WWDG_CR_WEN_Msk (0x1UL) /*!< WEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WVR ========================================================== */
+#define WWDG_WVR_WV_Pos (0UL) /*!< WV (Bit 0) */
+#define WWDG_WVR_WV_Msk (0xffffUL) /*!< WV (Bitfield-Mask: 0xffff) */
+/* ========================================================== CVR ========================================================== */
+#define WWDG_CVR_CV_Pos (0UL) /*!< CV (Bit 0) */
+#define WWDG_CVR_CV_Msk (0xffffUL) /*!< CV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define WWDG_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define WWDG_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================== ISR ========================================================== */
+#define WWDG_ISR_EWIF_Pos (0UL) /*!< EWIF (Bit 0) */
+#define WWDG_ISR_EWIF_Msk (0x1UL) /*!< EWIF (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ USB ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CTRL ========================================================== */
+#define USB_CTRL_ISOUP_Pos (15UL) /*!< ISOUP (Bit 15) */
+#define USB_CTRL_ISOUP_Msk (0x8000UL) /*!< ISOUP (Bitfield-Mask: 0x01) */
+#define USB_CTRL_SCONN_Pos (14UL) /*!< SCONN (Bit 14) */
+#define USB_CTRL_SCONN_Msk (0x4000UL) /*!< SCONN (Bitfield-Mask: 0x01) */
+#define USB_CTRL_RESET_Pos (11UL) /*!< RESET (Bit 11) */
+#define USB_CTRL_RESET_Msk (0x800UL) /*!< RESET (Bitfield-Mask: 0x01) */
+#define USB_CTRL_RESUME_Pos (10UL) /*!< RESUME (Bit 10) */
+#define USB_CTRL_RESUME_Msk (0x400UL) /*!< RESUME (Bitfield-Mask: 0x01) */
+#define USB_CTRL_SUSMOD_Pos (9UL) /*!< SUSMOD (Bit 9) */
+#define USB_CTRL_SUSMOD_Msk (0x200UL) /*!< SUSMOD (Bitfield-Mask: 0x01) */
+#define USB_CTRL_FADDR_Pos (0UL) /*!< FADDR (Bit 0) */
+#define USB_CTRL_FADDR_Msk (0xffUL) /*!< FADDR (Bitfield-Mask: 0xff) */
+/* ========================================================= INDEX ========================================================= */
+#define USB_INDEX_INDEX_Pos (16UL) /*!< INDEX (Bit 16) */
+#define USB_INDEX_INDEX_Msk (0xf0000UL) /*!< INDEX (Bitfield-Mask: 0x0f) */
+#define USB_INDEX_FNUM_Pos (0UL) /*!< FNUM (Bit 0) */
+#define USB_INDEX_FNUM_Msk (0xffffUL) /*!< FNUM (Bitfield-Mask: 0xffff) */
+/* ======================================================== TX0CTRL ======================================================== */
+#define USB_TX0CTRL_FLFIFO_Pos (24UL) /*!< FLFIFO (Bit 24) */
+#define USB_TX0CTRL_FLFIFO_Msk (0x1000000UL) /*!< FLFIFO (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_SSECLR_Pos (23UL) /*!< SSECLR (Bit 23) */
+#define USB_TX0CTRL_SSECLR_Msk (0x800000UL) /*!< SSECLR (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_SRPCLR_Pos (22UL) /*!< SRPCLR (Bit 22) */
+#define USB_TX0CTRL_SRPCLR_Msk (0x400000UL) /*!< SRPCLR (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_SENDSTA_Pos (21UL) /*!< SENDSTA (Bit 21) */
+#define USB_TX0CTRL_SENDSTA_Msk (0x200000UL) /*!< SENDSTA (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_SETUPEND_Pos (20UL) /*!< SETUPEND (Bit 20) */
+#define USB_TX0CTRL_SETUPEND_Msk (0x100000UL) /*!< SETUPEND (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_DATAEND_Pos (19UL) /*!< DATAEND (Bit 19) */
+#define USB_TX0CTRL_DATAEND_Msk (0x80000UL) /*!< DATAEND (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_SENTSTA_Pos (18UL) /*!< SENTSTA (Bit 18) */
+#define USB_TX0CTRL_SENTSTA_Msk (0x40000UL) /*!< SENTSTA (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_TXPR_Pos (17UL) /*!< TXPR (Bit 17) */
+#define USB_TX0CTRL_TXPR_Msk (0x20000UL) /*!< TXPR (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_RXPR_Pos (16UL) /*!< RXPR (Bit 16) */
+#define USB_TX0CTRL_RXPR_Msk (0x10000UL) /*!< RXPR (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_TXMAXP_Pos (0UL) /*!< TXMAXP (Bit 0) */
+#define USB_TX0CTRL_TXMAXP_Msk (0xffffUL) /*!< TXMAXP (Bitfield-Mask: 0xffff) */
+/* ======================================================== TXnCTRL ======================================================== */
+#define USB_TXnCTRL_AUTOSET_Pos (31UL) /*!< AUTOSET (Bit 31) */
+#define USB_TXnCTRL_AUTOSET_Msk (0x80000000UL) /*!< AUTOSET (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_ISO_Pos (30UL) /*!< ISO (Bit 30) */
+#define USB_TXnCTRL_ISO_Msk (0x40000000UL) /*!< ISO (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_MODE_Pos (29UL) /*!< MODE (Bit 29) */
+#define USB_TXnCTRL_MODE_Msk (0x20000000UL) /*!< MODE (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_FRCDATTOG_Pos (27UL) /*!< FRCDATTOG (Bit 27) */
+#define USB_TXnCTRL_FRCDATTOG_Msk (0x8000000UL) /*!< FRCDATTOG (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_CLRDT_Pos (22UL) /*!< CLRDT (Bit 22) */
+#define USB_TXnCTRL_CLRDT_Msk (0x400000UL) /*!< CLRDT (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_SENTSTA_Pos (21UL) /*!< SENTSTA (Bit 21) */
+#define USB_TXnCTRL_SENTSTA_Msk (0x200000UL) /*!< SENTSTA (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_SENDSTA_Pos (20UL) /*!< SENDSTA (Bit 20) */
+#define USB_TXnCTRL_SENDSTA_Msk (0x100000UL) /*!< SENDSTA (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_FLFIFO_Pos (19UL) /*!< FLFIFO (Bit 19) */
+#define USB_TXnCTRL_FLFIFO_Msk (0x80000UL) /*!< FLFIFO (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_UNRUN_Pos (18UL) /*!< UNRUN (Bit 18) */
+#define USB_TXnCTRL_UNRUN_Msk (0x40000UL) /*!< UNRUN (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_FIFONE_Pos (17UL) /*!< FIFONE (Bit 17) */
+#define USB_TXnCTRL_FIFONE_Msk (0x20000UL) /*!< FIFONE (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_TXPR_Pos (16UL) /*!< TXPR (Bit 16) */
+#define USB_TXnCTRL_TXPR_Msk (0x10000UL) /*!< TXPR (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_TXMAXP_Pos (0UL) /*!< TXMAXP (Bit 0) */
+#define USB_TXnCTRL_TXMAXP_Msk (0xffffUL) /*!< TXMAXP (Bitfield-Mask: 0xffff) */
+/* ======================================================== RXCTRL ========================================================= */
+#define USB_RXCTRL_AUTOCLR_Pos (31UL) /*!< AUTOCLR (Bit 31) */
+#define USB_RXCTRL_AUTOCLR_Msk (0x80000000UL) /*!< AUTOCLR (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_ISO_Pos (30UL) /*!< ISO (Bit 30) */
+#define USB_RXCTRL_ISO_Msk (0x40000000UL) /*!< ISO (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_INCRX_Pos (24UL) /*!< INCRX (Bit 24) */
+#define USB_RXCTRL_INCRX_Msk (0x1000000UL) /*!< INCRX (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_CDATTOG_Pos (23UL) /*!< CDATTOG (Bit 23) */
+#define USB_RXCTRL_CDATTOG_Msk (0x800000UL) /*!< CDATTOG (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_SENTSTA_Pos (22UL) /*!< SENTSTA (Bit 22) */
+#define USB_RXCTRL_SENTSTA_Msk (0x400000UL) /*!< SENTSTA (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_SENDSTA_Pos (21UL) /*!< SENDSTA (Bit 21) */
+#define USB_RXCTRL_SENDSTA_Msk (0x200000UL) /*!< SENDSTA (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_FLFIFO_Pos (20UL) /*!< FLFIFO (Bit 20) */
+#define USB_RXCTRL_FLFIFO_Msk (0x100000UL) /*!< FLFIFO (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_DATAERR_Pos (19UL) /*!< DATAERR (Bit 19) */
+#define USB_RXCTRL_DATAERR_Msk (0x80000UL) /*!< DATAERR (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_OVERRUN_Pos (18UL) /*!< OVERRUN (Bit 18) */
+#define USB_RXCTRL_OVERRUN_Msk (0x40000UL) /*!< OVERRUN (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_FIFOFULL_Pos (17UL) /*!< FIFOFULL (Bit 17) */
+#define USB_RXCTRL_FIFOFULL_Msk (0x20000UL) /*!< FIFOFULL (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_RXPR_Pos (16UL) /*!< RXPR (Bit 16) */
+#define USB_RXCTRL_RXPR_Msk (0x10000UL) /*!< RXPR (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_RXMAXP_Pos (0UL) /*!< RXMAXP (Bit 0) */
+#define USB_RXCTRL_RXMAXP_Msk (0xffffUL) /*!< RXMAXP (Bitfield-Mask: 0xffff) */
+/* ======================================================== RXCOUNT ======================================================== */
+#define USB_RXCOUNT_RXCOUNT_Pos (0UL) /*!< RXCOUNT (Bit 0) */
+#define USB_RXCOUNT_RXCOUNT_Msk (0x3fffUL) /*!< RXCOUNT (Bitfield-Mask: 0x3fff) */
+/* ======================================================= FIFOSIZE ======================================================== */
+#define USB_FIFOSIZE_RXFIFOSIZE_Pos (28UL) /*!< RXFIFOSIZE (Bit 28) */
+#define USB_FIFOSIZE_RXFIFOSIZE_Msk (0xf0000000UL) /*!< RXFIFOSIZE (Bitfield-Mask: 0x0f) */
+#define USB_FIFOSIZE_TXFIFOSIZE_Pos (24UL) /*!< TXFIFOSIZE (Bit 24) */
+#define USB_FIFOSIZE_TXFIFOSIZE_Msk (0xf000000UL) /*!< TXFIFOSIZE (Bitfield-Mask: 0x0f) */
+/* ======================================================== FIFOSZ ========================================================= */
+#define USB_FIFOSZ_RXDPB_Pos (28UL) /*!< RXDPB (Bit 28) */
+#define USB_FIFOSZ_RXDPB_Msk (0x10000000UL) /*!< RXDPB (Bitfield-Mask: 0x01) */
+#define USB_FIFOSZ_RXSZ_Pos (24UL) /*!< RXSZ (Bit 24) */
+#define USB_FIFOSZ_RXSZ_Msk (0xf000000UL) /*!< RXSZ (Bitfield-Mask: 0x0f) */
+#define USB_FIFOSZ_TXDPB_Pos (20UL) /*!< TXDPB (Bit 20) */
+#define USB_FIFOSZ_TXDPB_Msk (0x100000UL) /*!< TXDPB (Bitfield-Mask: 0x01) */
+#define USB_FIFOSZ_TXSZ_Pos (16UL) /*!< TXSZ (Bit 16) */
+#define USB_FIFOSZ_TXSZ_Msk (0xf0000UL) /*!< TXSZ (Bitfield-Mask: 0x0f) */
+/* ======================================================== FIFOAD ========================================================= */
+#define USB_FIFOAD_RXAD_Pos (16UL) /*!< RXAD (Bit 16) */
+#define USB_FIFOAD_RXAD_Msk (0x1fff0000UL) /*!< RXAD (Bitfield-Mask: 0x1fff) */
+#define USB_FIFOAD_TXAD_Pos (0UL) /*!< TXAD (Bit 0) */
+#define USB_FIFOAD_TXAD_Msk (0x1fffUL) /*!< TXAD (Bitfield-Mask: 0x1fff) */
+/* ======================================================== PINCTRL ======================================================== */
+#define USB_PINCTRL_DMOE_Pos (31UL) /*!< DMOE (Bit 31) */
+#define USB_PINCTRL_DMOE_Msk (0x80000000UL) /*!< DMOE (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMOE_EN_Pos (30UL) /*!< DMOE_EN (Bit 30) */
+#define USB_PINCTRL_DMOE_EN_Msk (0x40000000UL) /*!< DMOE_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPOE_Pos (29UL) /*!< DPOE (Bit 29) */
+#define USB_PINCTRL_DPOE_Msk (0x20000000UL) /*!< DPOE (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPOE_EN_Pos (28UL) /*!< DPOE_EN (Bit 28) */
+#define USB_PINCTRL_DPOE_EN_Msk (0x10000000UL) /*!< DPOE_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMIE_Pos (27UL) /*!< DMIE (Bit 27) */
+#define USB_PINCTRL_DMIE_Msk (0x8000000UL) /*!< DMIE (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMIE_EN_Pos (26UL) /*!< DMIE_EN (Bit 26) */
+#define USB_PINCTRL_DMIE_EN_Msk (0x4000000UL) /*!< DMIE_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPIE_Pos (25UL) /*!< DPIE (Bit 25) */
+#define USB_PINCTRL_DPIE_Msk (0x2000000UL) /*!< DPIE (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPIE_EN_Pos (24UL) /*!< DPIE_EN (Bit 24) */
+#define USB_PINCTRL_DPIE_EN_Msk (0x1000000UL) /*!< DPIE_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMSR_Pos (23UL) /*!< DMSR (Bit 23) */
+#define USB_PINCTRL_DMSR_Msk (0x800000UL) /*!< DMSR (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMTRIM_Pos (20UL) /*!< DMTRIM (Bit 20) */
+#define USB_PINCTRL_DMTRIM_Msk (0x700000UL) /*!< DMTRIM (Bitfield-Mask: 0x07) */
+#define USB_PINCTRL_DPSR_Pos (19UL) /*!< DPSR (Bit 19) */
+#define USB_PINCTRL_DPSR_Msk (0x80000UL) /*!< DPSR (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPTRIM_Pos (16UL) /*!< DPTRIM (Bit 16) */
+#define USB_PINCTRL_DPTRIM_Msk (0x70000UL) /*!< DPTRIM (Bitfield-Mask: 0x07) */
+#define USB_PINCTRL_DMPD_Pos (15UL) /*!< DMPD (Bit 15) */
+#define USB_PINCTRL_DMPD_Msk (0x8000UL) /*!< DMPD (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMPD_EN_Pos (14UL) /*!< DMPD_EN (Bit 14) */
+#define USB_PINCTRL_DMPD_EN_Msk (0x4000UL) /*!< DMPD_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMPU_Pos (13UL) /*!< DMPU (Bit 13) */
+#define USB_PINCTRL_DMPU_Msk (0x2000UL) /*!< DMPU (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMPU_EN_Pos (12UL) /*!< DMPU_EN (Bit 12) */
+#define USB_PINCTRL_DMPU_EN_Msk (0x1000UL) /*!< DMPU_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPPD_Pos (11UL) /*!< DPPD (Bit 11) */
+#define USB_PINCTRL_DPPD_Msk (0x800UL) /*!< DPPD (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPPD_EN_Pos (10UL) /*!< DPPD_EN (Bit 10) */
+#define USB_PINCTRL_DPPD_EN_Msk (0x400UL) /*!< DPPD_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPPU_Pos (9UL) /*!< DPPU (Bit 9) */
+#define USB_PINCTRL_DPPU_Msk (0x200UL) /*!< DPPU (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPPU_EN_Pos (8UL) /*!< DPPU_EN (Bit 8) */
+#define USB_PINCTRL_DPPU_EN_Msk (0x100UL) /*!< DPPU_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_Test_En_Pos (6UL) /*!< Test_En (Bit 6) */
+#define USB_PINCTRL_Test_En_Msk (0x40UL) /*!< Test_En (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_VBUSVALID_Pos (5UL) /*!< VBUSVALID (Bit 5) */
+#define USB_PINCTRL_VBUSVALID_Msk (0x20UL) /*!< VBUSVALID (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_AVALID_Pos (4UL) /*!< AVALID (Bit 4) */
+#define USB_PINCTRL_AVALID_Msk (0x10UL) /*!< AVALID (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_VBUSLO_Pos (3UL) /*!< VBUSLO (Bit 3) */
+#define USB_PINCTRL_VBUSLO_Msk (0x8UL) /*!< VBUSLO (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_CID_Pos (2UL) /*!< CID (Bit 2) */
+#define USB_PINCTRL_CID_Msk (0x4UL) /*!< CID (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_TM1_Pos (1UL) /*!< TM1 (Bit 1) */
+#define USB_PINCTRL_TM1_Msk (0x2UL) /*!< TM1 (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_PHY_EN_Pos (0UL) /*!< PHY_EN (Bit 0) */
+#define USB_PINCTRL_PHY_EN_Msk (0x1UL) /*!< PHY_EN (Bitfield-Mask: 0x01) */
+/* ======================================================= IUINTREN ======================================================== */
+#define USB_IUINTREN_DETDB_Pos (4UL) /*!< DETDB (Bit 4) */
+#define USB_IUINTREN_DETDB_Msk (0xfff0UL) /*!< DETDB (Bitfield-Mask: 0xfff) */
+#define USB_IUINTREN_UPDETIEN_Pos (1UL) /*!< UPDETIEN (Bit 1) */
+#define USB_IUINTREN_UPDETIEN_Msk (0x2UL) /*!< UPDETIEN (Bitfield-Mask: 0x01) */
+#define USB_IUINTREN_ISDETIEN_Pos (0UL) /*!< ISDETIEN (Bit 0) */
+#define USB_IUINTREN_ISDETIEN_Msk (0x1UL) /*!< ISDETIEN (Bitfield-Mask: 0x01) */
+/* ======================================================= EPINTREN ======================================================== */
+#define USB_EPINTREN_EP2RXINTEN_Pos (18UL) /*!< EP2RXINTEN (Bit 18) */
+#define USB_EPINTREN_EP2RXINTEN_Msk (0x40000UL) /*!< EP2RXINTEN (Bitfield-Mask: 0x01) */
+#define USB_EPINTREN_EP1RXINTEN_Pos (17UL) /*!< EP1RXINTEN (Bit 17) */
+#define USB_EPINTREN_EP1RXINTEN_Msk (0x20000UL) /*!< EP1RXINTEN (Bitfield-Mask: 0x01) */
+#define USB_EPINTREN_EP2TXINTEN_Pos (2UL) /*!< EP2TXINTEN (Bit 2) */
+#define USB_EPINTREN_EP2TXINTEN_Msk (0x4UL) /*!< EP2TXINTEN (Bitfield-Mask: 0x01) */
+#define USB_EPINTREN_EP1TXINTEN_Pos (1UL) /*!< EP1TXINTEN (Bit 1) */
+#define USB_EPINTREN_EP1TXINTEN_Msk (0x2UL) /*!< EP1TXINTEN (Bitfield-Mask: 0x01) */
+#define USB_EPINTREN_EP0INTEN_Pos (0UL) /*!< EP0INTEN (Bit 0) */
+#define USB_EPINTREN_EP0INTEN_Msk (0x1UL) /*!< EP0INTEN (Bitfield-Mask: 0x01) */
+/* ======================================================= USBINTREN ======================================================= */
+#define USB_USBINTREN_DISCONINTEN_Pos (5UL) /*!< DISCONINTEN (Bit 5) */
+#define USB_USBINTREN_DISCONINTEN_Msk (0x20UL) /*!< DISCONINTEN (Bitfield-Mask: 0x01) */
+#define USB_USBINTREN_SOFINTEN_Pos (3UL) /*!< SOFINTEN (Bit 3) */
+#define USB_USBINTREN_SOFINTEN_Msk (0x8UL) /*!< SOFINTEN (Bitfield-Mask: 0x01) */
+#define USB_USBINTREN_RESETINTEN_Pos (2UL) /*!< RESETINTEN (Bit 2) */
+#define USB_USBINTREN_RESETINTEN_Msk (0x4UL) /*!< RESETINTEN (Bitfield-Mask: 0x01) */
+#define USB_USBINTREN_RESUMEINTEN_Pos (1UL) /*!< RESUMEINTEN (Bit 1) */
+#define USB_USBINTREN_RESUMEINTEN_Msk (0x2UL) /*!< RESUMEINTEN (Bitfield-Mask: 0x01) */
+#define USB_USBINTREN_SUSPENDINTEN_Pos (0UL) /*!< SUSPENDINTEN (Bit 0) */
+#define USB_USBINTREN_SUSPENDINTEN_Msk (0x1UL) /*!< SUSPENDINTEN (Bitfield-Mask: 0x01) */
+/* ======================================================== IUINTR ========================================================= */
+#define USB_IUINTR_UPDETI_Pos (1UL) /*!< UPDETI (Bit 1) */
+#define USB_IUINTR_UPDETI_Msk (0x2UL) /*!< UPDETI (Bitfield-Mask: 0x01) */
+#define USB_IUINTR_ISDETI_Pos (0UL) /*!< ISDETI (Bit 0) */
+#define USB_IUINTR_ISDETI_Msk (0x1UL) /*!< ISDETI (Bitfield-Mask: 0x01) */
+/* ======================================================== EPINTR ========================================================= */
+#define USB_EPINTR_EP2RXINT_Pos (18UL) /*!< EP2RXINT (Bit 18) */
+#define USB_EPINTR_EP2RXINT_Msk (0x40000UL) /*!< EP2RXINT (Bitfield-Mask: 0x01) */
+#define USB_EPINTR_EP1RXINT_Pos (17UL) /*!< EP1RXINT (Bit 17) */
+#define USB_EPINTR_EP1RXINT_Msk (0x20000UL) /*!< EP1RXINT (Bitfield-Mask: 0x01) */
+#define USB_EPINTR_EP2TXINT_Pos (2UL) /*!< EP2TXINT (Bit 2) */
+#define USB_EPINTR_EP2TXINT_Msk (0x4UL) /*!< EP2TXINT (Bitfield-Mask: 0x01) */
+#define USB_EPINTR_EP1TXINT_Pos (1UL) /*!< EP1TXINT (Bit 1) */
+#define USB_EPINTR_EP1TXINT_Msk (0x2UL) /*!< EP1TXINT (Bitfield-Mask: 0x01) */
+#define USB_EPINTR_EP0INT_Pos (0UL) /*!< EP0INT (Bit 0) */
+#define USB_EPINTR_EP0INT_Msk (0x1UL) /*!< EP0INT (Bitfield-Mask: 0x01) */
+/* ======================================================== USBINTR ======================================================== */
+#define USB_USBINTR_DISCON_Pos (5UL) /*!< DISCON (Bit 5) */
+#define USB_USBINTR_DISCON_Msk (0x20UL) /*!< DISCON (Bitfield-Mask: 0x01) */
+#define USB_USBINTR_SOF_Pos (3UL) /*!< SOF (Bit 3) */
+#define USB_USBINTR_SOF_Msk (0x8UL) /*!< SOF (Bitfield-Mask: 0x01) */
+#define USB_USBINTR_RESET_Pos (2UL) /*!< RESET (Bit 2) */
+#define USB_USBINTR_RESET_Msk (0x4UL) /*!< RESET (Bitfield-Mask: 0x01) */
+#define USB_USBINTR_RESUME_Pos (1UL) /*!< RESUME (Bit 1) */
+#define USB_USBINTR_RESUME_Msk (0x2UL) /*!< RESUME (Bitfield-Mask: 0x01) */
+#define USB_USBINTR_SUSPEND_Pos (0UL) /*!< SUSPEND (Bit 0) */
+#define USB_USBINTR_SUSPEND_Msk (0x1UL) /*!< SUSPEND (Bitfield-Mask: 0x01) */
+/* ========================================================= FIFO0 ========================================================= */
+#define USB_FIFO0_FIFO0_Pos (0UL) /*!< FIFO0 (Bit 0) */
+#define USB_FIFO0_FIFO0_Msk (0xffffffffUL) /*!< FIFO0 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= FIFO1 ========================================================= */
+#define USB_FIFO1_FIFO1_Pos (0UL) /*!< FIFO1 (Bit 0) */
+#define USB_FIFO1_FIFO1_Msk (0xffffffffUL) /*!< FIFO1 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= FIFO2 ========================================================= */
+#define USB_FIFO2_FIFO2_Pos (0UL) /*!< FIFO2 (Bit 0) */
+#define USB_FIFO2_FIFO2_Msk (0xffffffffUL) /*!< FIFO2 (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define UART0_CR0_ABRM_Pos (20UL) /*!< ABRM (Bit 20) */
+#define UART0_CR0_ABRM_Msk (0x300000UL) /*!< ABRM (Bitfield-Mask: 0x03) */
+#define UART0_CR0_OVDIS_Pos (17UL) /*!< OVDIS (Bit 17) */
+#define UART0_CR0_OVDIS_Msk (0x20000UL) /*!< OVDIS (Bitfield-Mask: 0x01) */
+#define UART0_CR0_LOOP_Pos (16UL) /*!< LOOP (Bit 16) */
+#define UART0_CR0_LOOP_Msk (0x10000UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define UART0_CR0_ONEBIT_Pos (15UL) /*!< ONEBIT (Bit 15) */
+#define UART0_CR0_ONEBIT_Msk (0x8000UL) /*!< ONEBIT (Bitfield-Mask: 0x01) */
+#define UART0_CR0_RTOM_Pos (14UL) /*!< RTOM (Bit 14) */
+#define UART0_CR0_RTOM_Msk (0x4000UL) /*!< RTOM (Bitfield-Mask: 0x01) */
+#define UART0_CR0_NFE_Pos (13UL) /*!< NFE (Bit 13) */
+#define UART0_CR0_NFE_Msk (0x2000UL) /*!< NFE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_OVER8_Pos (12UL) /*!< OVER8 (Bit 12) */
+#define UART0_CR0_OVER8_Msk (0x1000UL) /*!< OVER8 (Bitfield-Mask: 0x01) */
+#define UART0_CR0_RTOE_Pos (11UL) /*!< RTOE (Bit 11) */
+#define UART0_CR0_RTOE_Msk (0x800UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_TPOL_Pos (10UL) /*!< TPOL (Bit 10) */
+#define UART0_CR0_TPOL_Msk (0x400UL) /*!< TPOL (Bitfield-Mask: 0x01) */
+#define UART0_CR0_RPOL_Pos (9UL) /*!< RPOL (Bit 9) */
+#define UART0_CR0_RPOL_Msk (0x200UL) /*!< RPOL (Bitfield-Mask: 0x01) */
+#define UART0_CR0_SWAP_Pos (8UL) /*!< SWAP (Bit 8) */
+#define UART0_CR0_SWAP_Msk (0x100UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define UART0_CR0_OWE_Pos (7UL) /*!< OWE (Bit 7) */
+#define UART0_CR0_OWE_Msk (0x80UL) /*!< OWE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_DTE_Pos (6UL) /*!< DTE (Bit 6) */
+#define UART0_CR0_DTE_Msk (0x40UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_DRE_Pos (5UL) /*!< DRE (Bit 5) */
+#define UART0_CR0_DRE_Msk (0x20UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_TFR_Pos (4UL) /*!< TFR (Bit 4) */
+#define UART0_CR0_TFR_Msk (0x10UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define UART0_CR0_RFR_Pos (3UL) /*!< RFR (Bit 3) */
+#define UART0_CR0_RFR_Msk (0x8UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define UART0_CR0_TE_Pos (2UL) /*!< TE (Bit 2) */
+#define UART0_CR0_TE_Msk (0x4UL) /*!< TE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_RE_Pos (1UL) /*!< RE (Bit 1) */
+#define UART0_CR0_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_UE_Pos (0UL) /*!< UE (Bit 0) */
+#define UART0_CR0_UE_Msk (0x1UL) /*!< UE (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define UART0_CR1_ABR_Pos (21UL) /*!< ABR (Bit 21) */
+#define UART0_CR1_ABR_Msk (0x200000UL) /*!< ABR (Bitfield-Mask: 0x01) */
+#define UART0_CR1_IDR_Pos (20UL) /*!< IDR (Bit 20) */
+#define UART0_CR1_IDR_Msk (0x100000UL) /*!< IDR (Bitfield-Mask: 0x01) */
+#define UART0_CR1_BKR_Pos (19UL) /*!< BKR (Bit 19) */
+#define UART0_CR1_BKR_Msk (0x80000UL) /*!< BKR (Bitfield-Mask: 0x01) */
+#define UART0_CR1_TEM_Pos (18UL) /*!< TEM (Bit 18) */
+#define UART0_CR1_TEM_Msk (0x40000UL) /*!< TEM (Bitfield-Mask: 0x01) */
+#define UART0_CR1_REM_Pos (17UL) /*!< REM (Bit 17) */
+#define UART0_CR1_REM_Msk (0x20000UL) /*!< REM (Bitfield-Mask: 0x01) */
+#define UART0_CR1_EBE_Pos (16UL) /*!< EBE (Bit 16) */
+#define UART0_CR1_EBE_Msk (0x10000UL) /*!< EBE (Bitfield-Mask: 0x01) */
+#define UART0_CR1_DEP_Pos (10UL) /*!< DEP (Bit 10) */
+#define UART0_CR1_DEP_Msk (0x400UL) /*!< DEP (Bitfield-Mask: 0x01) */
+#define UART0_CR1_REP_Pos (9UL) /*!< REP (Bit 9) */
+#define UART0_CR1_REP_Msk (0x200UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define UART0_CR1_RS485E_Pos (8UL) /*!< RS485E (Bit 8) */
+#define UART0_CR1_RS485E_Msk (0x100UL) /*!< RS485E (Bitfield-Mask: 0x01) */
+#define UART0_CR1_MSB_Pos (7UL) /*!< MSB (Bit 7) */
+#define UART0_CR1_MSB_Msk (0x80UL) /*!< MSB (Bitfield-Mask: 0x01) */
+#define UART0_CR1_SPE_Pos (5UL) /*!< SPE (Bit 5) */
+#define UART0_CR1_SPE_Msk (0x20UL) /*!< SPE (Bitfield-Mask: 0x01) */
+#define UART0_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
+#define UART0_CR1_PSEL_Msk (0x10UL) /*!< PSEL (Bitfield-Mask: 0x01) */
+#define UART0_CR1_PEN_Pos (3UL) /*!< PEN (Bit 3) */
+#define UART0_CR1_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
+#define UART0_CR1_STP_Pos (2UL) /*!< STP (Bit 2) */
+#define UART0_CR1_STP_Msk (0x4UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define UART0_CR1_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+#define UART0_CR1_LEN_Msk (0x3UL) /*!< LEN (Bitfield-Mask: 0x03) */
+/* ========================================================= BAUD ========================================================== */
+#define UART0_BAUD_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define UART0_BAUD_BAUD_Msk (0xffffUL) /*!< BAUD (Bitfield-Mask: 0xffff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define UART0_FIFOCTRL_TXFT_Pos (4UL) /*!< TXFT (Bit 4) */
+#define UART0_FIFOCTRL_TXFT_Msk (0xf0UL) /*!< TXFT (Bitfield-Mask: 0x0f) */
+#define UART0_FIFOCTRL_RXFT_Pos (0UL) /*!< RXFT (Bit 0) */
+#define UART0_FIFOCTRL_RXFT_Msk (0xfUL) /*!< RXFT (Bitfield-Mask: 0x0f) */
+/* ======================================================== TIMING0 ======================================================== */
+#define UART0_TIMING0_DEDT_Pos (16UL) /*!< DEDT (Bit 16) */
+#define UART0_TIMING0_DEDT_Msk (0xffff0000UL) /*!< DEDT (Bitfield-Mask: 0xffff) */
+#define UART0_TIMING0_DEAT_Pos (0UL) /*!< DEAT (Bit 0) */
+#define UART0_TIMING0_DEAT_Msk (0xffffUL) /*!< DEAT (Bitfield-Mask: 0xffff) */
+/* ======================================================== TIMING1 ======================================================== */
+#define UART0_TIMING1_DRET_Pos (16UL) /*!< DRET (Bit 16) */
+#define UART0_TIMING1_DRET_Msk (0xffff0000UL) /*!< DRET (Bitfield-Mask: 0xffff) */
+#define UART0_TIMING1_RDET_Pos (0UL) /*!< RDET (Bit 0) */
+#define UART0_TIMING1_RDET_Msk (0xffffUL) /*!< RDET (Bitfield-Mask: 0xffff) */
+/* ========================================================== TDR ========================================================== */
+#define UART0_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define UART0_TDR_TD_Msk (0x1ffUL) /*!< TD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== RDR ========================================================== */
+#define UART0_RDR_OVDA_Pos (16UL) /*!< OVDA (Bit 16) */
+#define UART0_RDR_OVDA_Msk (0x7ff0000UL) /*!< OVDA (Bitfield-Mask: 0x7ff) */
+#define UART0_RDR_FMST_Pos (10UL) /*!< FMST (Bit 10) */
+#define UART0_RDR_FMST_Msk (0x400UL) /*!< FMST (Bitfield-Mask: 0x01) */
+#define UART0_RDR_PRST_Pos (9UL) /*!< PRST (Bit 9) */
+#define UART0_RDR_PRST_Msk (0x200UL) /*!< PRST (Bitfield-Mask: 0x01) */
+#define UART0_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define UART0_RDR_RD_Msk (0x1ffUL) /*!< RD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== TAR ========================================================== */
+#define UART0_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define UART0_TAR_TAR_Msk (0xffUL) /*!< TAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RAR ========================================================== */
+#define UART0_RAR_RAR_Pos (0UL) /*!< RAR (Bit 0) */
+#define UART0_RAR_RAR_Msk (0xffUL) /*!< RAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RTO ========================================================== */
+#define UART0_RTO_RTO_Pos (0UL) /*!< RTO (Bit 0) */
+#define UART0_RTO_RTO_Msk (0xffffUL) /*!< RTO (Bitfield-Mask: 0xffff) */
+/* ========================================================= INTEN ========================================================= */
+#define UART0_INTEN_ABRE_Pos (16UL) /*!< ABRE (Bit 16) */
+#define UART0_INTEN_ABRE_Msk (0x10000UL) /*!< ABRE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_AMIE_Pos (15UL) /*!< AMIE (Bit 15) */
+#define UART0_INTEN_AMIE_Msk (0x8000UL) /*!< AMIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_IDLE_Pos (14UL) /*!< IDLE (Bit 14) */
+#define UART0_INTEN_IDLE_Msk (0x4000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_TBIE_Pos (13UL) /*!< TBIE (Bit 13) */
+#define UART0_INTEN_TBIE_Msk (0x2000UL) /*!< TBIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_TDIE_Pos (12UL) /*!< TDIE (Bit 12) */
+#define UART0_INTEN_TDIE_Msk (0x1000UL) /*!< TDIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_RTIE_Pos (11UL) /*!< RTIE (Bit 11) */
+#define UART0_INTEN_RTIE_Msk (0x800UL) /*!< RTIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_BKIE_Pos (10UL) /*!< BKIE (Bit 10) */
+#define UART0_INTEN_BKIE_Msk (0x400UL) /*!< BKIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_FEIE_Pos (9UL) /*!< FEIE (Bit 9) */
+#define UART0_INTEN_FEIE_Msk (0x200UL) /*!< FEIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_PEIE_Pos (8UL) /*!< PEIE (Bit 8) */
+#define UART0_INTEN_PEIE_Msk (0x100UL) /*!< PEIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_NOIE_Pos (7UL) /*!< NOIE (Bit 7) */
+#define UART0_INTEN_NOIE_Msk (0x80UL) /*!< NOIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_IDIE_Pos (6UL) /*!< IDIE (Bit 6) */
+#define UART0_INTEN_IDIE_Msk (0x40UL) /*!< IDIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_TOIE_Pos (4UL) /*!< TOIE (Bit 4) */
+#define UART0_INTEN_TOIE_Msk (0x10UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_RUIE_Pos (3UL) /*!< RUIE (Bit 3) */
+#define UART0_INTEN_RUIE_Msk (0x8UL) /*!< RUIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_ROIE_Pos (2UL) /*!< ROIE (Bit 2) */
+#define UART0_INTEN_ROIE_Msk (0x4UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_TEIE_Pos (1UL) /*!< TEIE (Bit 1) */
+#define UART0_INTEN_TEIE_Msk (0x2UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_RFIE_Pos (0UL) /*!< RFIE (Bit 0) */
+#define UART0_INTEN_RFIE_Msk (0x1UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define UART0_INT_ABRF_Pos (16UL) /*!< ABRF (Bit 16) */
+#define UART0_INT_ABRF_Msk (0x10000UL) /*!< ABRF (Bitfield-Mask: 0x01) */
+#define UART0_INT_AMIF_Pos (15UL) /*!< AMIF (Bit 15) */
+#define UART0_INT_AMIF_Msk (0x8000UL) /*!< AMIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_IDLF_Pos (14UL) /*!< IDLF (Bit 14) */
+#define UART0_INT_IDLF_Msk (0x4000UL) /*!< IDLF (Bitfield-Mask: 0x01) */
+#define UART0_INT_TBIF_Pos (13UL) /*!< TBIF (Bit 13) */
+#define UART0_INT_TBIF_Msk (0x2000UL) /*!< TBIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_TDIF_Pos (12UL) /*!< TDIF (Bit 12) */
+#define UART0_INT_TDIF_Msk (0x1000UL) /*!< TDIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_RTOI_Pos (11UL) /*!< RTOI (Bit 11) */
+#define UART0_INT_RTOI_Msk (0x800UL) /*!< RTOI (Bitfield-Mask: 0x01) */
+#define UART0_INT_BKIF_Pos (10UL) /*!< BKIF (Bit 10) */
+#define UART0_INT_BKIF_Msk (0x400UL) /*!< BKIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_FEIF_Pos (9UL) /*!< FEIF (Bit 9) */
+#define UART0_INT_FEIF_Msk (0x200UL) /*!< FEIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_PEIF_Pos (8UL) /*!< PEIF (Bit 8) */
+#define UART0_INT_PEIF_Msk (0x100UL) /*!< PEIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_NOIF_Pos (7UL) /*!< NOIF (Bit 7) */
+#define UART0_INT_NOIF_Msk (0x80UL) /*!< NOIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_IDIF_Pos (6UL) /*!< IDIF (Bit 6) */
+#define UART0_INT_IDIF_Msk (0x40UL) /*!< IDIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_TOIF_Pos (4UL) /*!< TOIF (Bit 4) */
+#define UART0_INT_TOIF_Msk (0x10UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_RUIF_Pos (3UL) /*!< RUIF (Bit 3) */
+#define UART0_INT_RUIF_Msk (0x8UL) /*!< RUIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_ROIF_Pos (2UL) /*!< ROIF (Bit 2) */
+#define UART0_INT_ROIF_Msk (0x4UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define UART0_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define UART0_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define UART0_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define UART0_STATUS_RSE_Pos (16UL) /*!< RSE (Bit 16) */
+#define UART0_STATUS_RSE_Msk (0x10000UL) /*!< RSE (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_RFL_Pos (11UL) /*!< RFL (Bit 11) */
+#define UART0_STATUS_RFL_Msk (0xf800UL) /*!< RFL (Bitfield-Mask: 0x1f) */
+#define UART0_STATUS_RFF_Pos (10UL) /*!< RFF (Bit 10) */
+#define UART0_STATUS_RFF_Msk (0x400UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_RFE_Pos (9UL) /*!< RFE (Bit 9) */
+#define UART0_STATUS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_RBSY_Pos (8UL) /*!< RBSY (Bit 8) */
+#define UART0_STATUS_RBSY_Msk (0x100UL) /*!< RBSY (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_TFL_Pos (3UL) /*!< TFL (Bit 3) */
+#define UART0_STATUS_TFL_Msk (0xf8UL) /*!< TFL (Bitfield-Mask: 0x1f) */
+#define UART0_STATUS_TFF_Pos (2UL) /*!< TFF (Bit 2) */
+#define UART0_STATUS_TFF_Msk (0x4UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_TFE_Pos (1UL) /*!< TFE (Bit 1) */
+#define UART0_STATUS_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_TBSY_Pos (0UL) /*!< TBSY (Bit 0) */
+#define UART0_STATUS_TBSY_Msk (0x1UL) /*!< TBSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define UART1_CR0_ABRM_Pos (20UL) /*!< ABRM (Bit 20) */
+#define UART1_CR0_ABRM_Msk (0x300000UL) /*!< ABRM (Bitfield-Mask: 0x03) */
+#define UART1_CR0_OVDIS_Pos (17UL) /*!< OVDIS (Bit 17) */
+#define UART1_CR0_OVDIS_Msk (0x20000UL) /*!< OVDIS (Bitfield-Mask: 0x01) */
+#define UART1_CR0_LOOP_Pos (16UL) /*!< LOOP (Bit 16) */
+#define UART1_CR0_LOOP_Msk (0x10000UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define UART1_CR0_ONEBIT_Pos (15UL) /*!< ONEBIT (Bit 15) */
+#define UART1_CR0_ONEBIT_Msk (0x8000UL) /*!< ONEBIT (Bitfield-Mask: 0x01) */
+#define UART1_CR0_RTOM_Pos (14UL) /*!< RTOM (Bit 14) */
+#define UART1_CR0_RTOM_Msk (0x4000UL) /*!< RTOM (Bitfield-Mask: 0x01) */
+#define UART1_CR0_NFE_Pos (13UL) /*!< NFE (Bit 13) */
+#define UART1_CR0_NFE_Msk (0x2000UL) /*!< NFE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_OVER8_Pos (12UL) /*!< OVER8 (Bit 12) */
+#define UART1_CR0_OVER8_Msk (0x1000UL) /*!< OVER8 (Bitfield-Mask: 0x01) */
+#define UART1_CR0_RTOE_Pos (11UL) /*!< RTOE (Bit 11) */
+#define UART1_CR0_RTOE_Msk (0x800UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_TPOL_Pos (10UL) /*!< TPOL (Bit 10) */
+#define UART1_CR0_TPOL_Msk (0x400UL) /*!< TPOL (Bitfield-Mask: 0x01) */
+#define UART1_CR0_RPOL_Pos (9UL) /*!< RPOL (Bit 9) */
+#define UART1_CR0_RPOL_Msk (0x200UL) /*!< RPOL (Bitfield-Mask: 0x01) */
+#define UART1_CR0_SWAP_Pos (8UL) /*!< SWAP (Bit 8) */
+#define UART1_CR0_SWAP_Msk (0x100UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define UART1_CR0_OWE_Pos (7UL) /*!< OWE (Bit 7) */
+#define UART1_CR0_OWE_Msk (0x80UL) /*!< OWE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_DTE_Pos (6UL) /*!< DTE (Bit 6) */
+#define UART1_CR0_DTE_Msk (0x40UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_DRE_Pos (5UL) /*!< DRE (Bit 5) */
+#define UART1_CR0_DRE_Msk (0x20UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_TFR_Pos (4UL) /*!< TFR (Bit 4) */
+#define UART1_CR0_TFR_Msk (0x10UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define UART1_CR0_RFR_Pos (3UL) /*!< RFR (Bit 3) */
+#define UART1_CR0_RFR_Msk (0x8UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define UART1_CR0_TE_Pos (2UL) /*!< TE (Bit 2) */
+#define UART1_CR0_TE_Msk (0x4UL) /*!< TE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_RE_Pos (1UL) /*!< RE (Bit 1) */
+#define UART1_CR0_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_UE_Pos (0UL) /*!< UE (Bit 0) */
+#define UART1_CR0_UE_Msk (0x1UL) /*!< UE (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define UART1_CR1_ABR_Pos (21UL) /*!< ABR (Bit 21) */
+#define UART1_CR1_ABR_Msk (0x200000UL) /*!< ABR (Bitfield-Mask: 0x01) */
+#define UART1_CR1_IDR_Pos (20UL) /*!< IDR (Bit 20) */
+#define UART1_CR1_IDR_Msk (0x100000UL) /*!< IDR (Bitfield-Mask: 0x01) */
+#define UART1_CR1_BKR_Pos (19UL) /*!< BKR (Bit 19) */
+#define UART1_CR1_BKR_Msk (0x80000UL) /*!< BKR (Bitfield-Mask: 0x01) */
+#define UART1_CR1_TEM_Pos (18UL) /*!< TEM (Bit 18) */
+#define UART1_CR1_TEM_Msk (0x40000UL) /*!< TEM (Bitfield-Mask: 0x01) */
+#define UART1_CR1_REM_Pos (17UL) /*!< REM (Bit 17) */
+#define UART1_CR1_REM_Msk (0x20000UL) /*!< REM (Bitfield-Mask: 0x01) */
+#define UART1_CR1_EBE_Pos (16UL) /*!< EBE (Bit 16) */
+#define UART1_CR1_EBE_Msk (0x10000UL) /*!< EBE (Bitfield-Mask: 0x01) */
+#define UART1_CR1_DEP_Pos (10UL) /*!< DEP (Bit 10) */
+#define UART1_CR1_DEP_Msk (0x400UL) /*!< DEP (Bitfield-Mask: 0x01) */
+#define UART1_CR1_REP_Pos (9UL) /*!< REP (Bit 9) */
+#define UART1_CR1_REP_Msk (0x200UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define UART1_CR1_RS485E_Pos (8UL) /*!< RS485E (Bit 8) */
+#define UART1_CR1_RS485E_Msk (0x100UL) /*!< RS485E (Bitfield-Mask: 0x01) */
+#define UART1_CR1_MSB_Pos (7UL) /*!< MSB (Bit 7) */
+#define UART1_CR1_MSB_Msk (0x80UL) /*!< MSB (Bitfield-Mask: 0x01) */
+#define UART1_CR1_SPE_Pos (5UL) /*!< SPE (Bit 5) */
+#define UART1_CR1_SPE_Msk (0x20UL) /*!< SPE (Bitfield-Mask: 0x01) */
+#define UART1_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
+#define UART1_CR1_PSEL_Msk (0x10UL) /*!< PSEL (Bitfield-Mask: 0x01) */
+#define UART1_CR1_PEN_Pos (3UL) /*!< PEN (Bit 3) */
+#define UART1_CR1_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
+#define UART1_CR1_STP_Pos (2UL) /*!< STP (Bit 2) */
+#define UART1_CR1_STP_Msk (0x4UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define UART1_CR1_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+#define UART1_CR1_LEN_Msk (0x3UL) /*!< LEN (Bitfield-Mask: 0x03) */
+/* ========================================================= BAUD ========================================================== */
+#define UART1_BAUD_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define UART1_BAUD_BAUD_Msk (0xffffUL) /*!< BAUD (Bitfield-Mask: 0xffff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define UART1_FIFOCTRL_TXFT_Pos (4UL) /*!< TXFT (Bit 4) */
+#define UART1_FIFOCTRL_TXFT_Msk (0xf0UL) /*!< TXFT (Bitfield-Mask: 0x0f) */
+#define UART1_FIFOCTRL_RXFT_Pos (0UL) /*!< RXFT (Bit 0) */
+#define UART1_FIFOCTRL_RXFT_Msk (0xfUL) /*!< RXFT (Bitfield-Mask: 0x0f) */
+/* ======================================================== TIMING0 ======================================================== */
+#define UART1_TIMING0_DEDT_Pos (16UL) /*!< DEDT (Bit 16) */
+#define UART1_TIMING0_DEDT_Msk (0xffff0000UL) /*!< DEDT (Bitfield-Mask: 0xffff) */
+#define UART1_TIMING0_DEAT_Pos (0UL) /*!< DEAT (Bit 0) */
+#define UART1_TIMING0_DEAT_Msk (0xffffUL) /*!< DEAT (Bitfield-Mask: 0xffff) */
+/* ======================================================== TIMING1 ======================================================== */
+#define UART1_TIMING1_DRET_Pos (16UL) /*!< DRET (Bit 16) */
+#define UART1_TIMING1_DRET_Msk (0xffff0000UL) /*!< DRET (Bitfield-Mask: 0xffff) */
+#define UART1_TIMING1_RDET_Pos (0UL) /*!< RDET (Bit 0) */
+#define UART1_TIMING1_RDET_Msk (0xffffUL) /*!< RDET (Bitfield-Mask: 0xffff) */
+/* ========================================================== TDR ========================================================== */
+#define UART1_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define UART1_TDR_TD_Msk (0x1ffUL) /*!< TD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== RDR ========================================================== */
+#define UART1_RDR_OVDA_Pos (16UL) /*!< OVDA (Bit 16) */
+#define UART1_RDR_OVDA_Msk (0x7ff0000UL) /*!< OVDA (Bitfield-Mask: 0x7ff) */
+#define UART1_RDR_FMST_Pos (10UL) /*!< FMST (Bit 10) */
+#define UART1_RDR_FMST_Msk (0x400UL) /*!< FMST (Bitfield-Mask: 0x01) */
+#define UART1_RDR_PRST_Pos (9UL) /*!< PRST (Bit 9) */
+#define UART1_RDR_PRST_Msk (0x200UL) /*!< PRST (Bitfield-Mask: 0x01) */
+#define UART1_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define UART1_RDR_RD_Msk (0x1ffUL) /*!< RD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== TAR ========================================================== */
+#define UART1_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define UART1_TAR_TAR_Msk (0xffUL) /*!< TAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RAR ========================================================== */
+#define UART1_RAR_RAR_Pos (0UL) /*!< RAR (Bit 0) */
+#define UART1_RAR_RAR_Msk (0xffUL) /*!< RAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RTO ========================================================== */
+#define UART1_RTO_RTO_Pos (0UL) /*!< RTO (Bit 0) */
+#define UART1_RTO_RTO_Msk (0xffffUL) /*!< RTO (Bitfield-Mask: 0xffff) */
+/* ========================================================= INTEN ========================================================= */
+#define UART1_INTEN_ABRE_Pos (16UL) /*!< ABRE (Bit 16) */
+#define UART1_INTEN_ABRE_Msk (0x10000UL) /*!< ABRE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_AMIE_Pos (15UL) /*!< AMIE (Bit 15) */
+#define UART1_INTEN_AMIE_Msk (0x8000UL) /*!< AMIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_IDLE_Pos (14UL) /*!< IDLE (Bit 14) */
+#define UART1_INTEN_IDLE_Msk (0x4000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_TBIE_Pos (13UL) /*!< TBIE (Bit 13) */
+#define UART1_INTEN_TBIE_Msk (0x2000UL) /*!< TBIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_TDIE_Pos (12UL) /*!< TDIE (Bit 12) */
+#define UART1_INTEN_TDIE_Msk (0x1000UL) /*!< TDIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_RTIE_Pos (11UL) /*!< RTIE (Bit 11) */
+#define UART1_INTEN_RTIE_Msk (0x800UL) /*!< RTIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_BKIE_Pos (10UL) /*!< BKIE (Bit 10) */
+#define UART1_INTEN_BKIE_Msk (0x400UL) /*!< BKIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_FEIE_Pos (9UL) /*!< FEIE (Bit 9) */
+#define UART1_INTEN_FEIE_Msk (0x200UL) /*!< FEIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_PEIE_Pos (8UL) /*!< PEIE (Bit 8) */
+#define UART1_INTEN_PEIE_Msk (0x100UL) /*!< PEIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_NOIE_Pos (7UL) /*!< NOIE (Bit 7) */
+#define UART1_INTEN_NOIE_Msk (0x80UL) /*!< NOIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_IDIE_Pos (6UL) /*!< IDIE (Bit 6) */
+#define UART1_INTEN_IDIE_Msk (0x40UL) /*!< IDIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_TOIE_Pos (4UL) /*!< TOIE (Bit 4) */
+#define UART1_INTEN_TOIE_Msk (0x10UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_RUIE_Pos (3UL) /*!< RUIE (Bit 3) */
+#define UART1_INTEN_RUIE_Msk (0x8UL) /*!< RUIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_ROIE_Pos (2UL) /*!< ROIE (Bit 2) */
+#define UART1_INTEN_ROIE_Msk (0x4UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_TEIE_Pos (1UL) /*!< TEIE (Bit 1) */
+#define UART1_INTEN_TEIE_Msk (0x2UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_RFIE_Pos (0UL) /*!< RFIE (Bit 0) */
+#define UART1_INTEN_RFIE_Msk (0x1UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define UART1_INT_ABRF_Pos (16UL) /*!< ABRF (Bit 16) */
+#define UART1_INT_ABRF_Msk (0x10000UL) /*!< ABRF (Bitfield-Mask: 0x01) */
+#define UART1_INT_AMIF_Pos (15UL) /*!< AMIF (Bit 15) */
+#define UART1_INT_AMIF_Msk (0x8000UL) /*!< AMIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_IDLF_Pos (14UL) /*!< IDLF (Bit 14) */
+#define UART1_INT_IDLF_Msk (0x4000UL) /*!< IDLF (Bitfield-Mask: 0x01) */
+#define UART1_INT_TBIF_Pos (13UL) /*!< TBIF (Bit 13) */
+#define UART1_INT_TBIF_Msk (0x2000UL) /*!< TBIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_TDIF_Pos (12UL) /*!< TDIF (Bit 12) */
+#define UART1_INT_TDIF_Msk (0x1000UL) /*!< TDIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_RTOI_Pos (11UL) /*!< RTOI (Bit 11) */
+#define UART1_INT_RTOI_Msk (0x800UL) /*!< RTOI (Bitfield-Mask: 0x01) */
+#define UART1_INT_BKIF_Pos (10UL) /*!< BKIF (Bit 10) */
+#define UART1_INT_BKIF_Msk (0x400UL) /*!< BKIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_FEIF_Pos (9UL) /*!< FEIF (Bit 9) */
+#define UART1_INT_FEIF_Msk (0x200UL) /*!< FEIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_PEIF_Pos (8UL) /*!< PEIF (Bit 8) */
+#define UART1_INT_PEIF_Msk (0x100UL) /*!< PEIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_NOIF_Pos (7UL) /*!< NOIF (Bit 7) */
+#define UART1_INT_NOIF_Msk (0x80UL) /*!< NOIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_IDIF_Pos (6UL) /*!< IDIF (Bit 6) */
+#define UART1_INT_IDIF_Msk (0x40UL) /*!< IDIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_TOIF_Pos (4UL) /*!< TOIF (Bit 4) */
+#define UART1_INT_TOIF_Msk (0x10UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_RUIF_Pos (3UL) /*!< RUIF (Bit 3) */
+#define UART1_INT_RUIF_Msk (0x8UL) /*!< RUIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_ROIF_Pos (2UL) /*!< ROIF (Bit 2) */
+#define UART1_INT_ROIF_Msk (0x4UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define UART1_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define UART1_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define UART1_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define UART1_STATUS_RSE_Pos (16UL) /*!< RSE (Bit 16) */
+#define UART1_STATUS_RSE_Msk (0x10000UL) /*!< RSE (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_RFL_Pos (11UL) /*!< RFL (Bit 11) */
+#define UART1_STATUS_RFL_Msk (0xf800UL) /*!< RFL (Bitfield-Mask: 0x1f) */
+#define UART1_STATUS_RFF_Pos (10UL) /*!< RFF (Bit 10) */
+#define UART1_STATUS_RFF_Msk (0x400UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_RFE_Pos (9UL) /*!< RFE (Bit 9) */
+#define UART1_STATUS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_RBSY_Pos (8UL) /*!< RBSY (Bit 8) */
+#define UART1_STATUS_RBSY_Msk (0x100UL) /*!< RBSY (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_TFL_Pos (3UL) /*!< TFL (Bit 3) */
+#define UART1_STATUS_TFL_Msk (0xf8UL) /*!< TFL (Bitfield-Mask: 0x1f) */
+#define UART1_STATUS_TFF_Pos (2UL) /*!< TFF (Bit 2) */
+#define UART1_STATUS_TFF_Msk (0x4UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_TFE_Pos (1UL) /*!< TFE (Bit 1) */
+#define UART1_STATUS_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_TBSY_Pos (0UL) /*!< TBSY (Bit 0) */
+#define UART1_STATUS_TBSY_Msk (0x1UL) /*!< TBSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define UART2_CR0_ABRM_Pos (20UL) /*!< ABRM (Bit 20) */
+#define UART2_CR0_ABRM_Msk (0x300000UL) /*!< ABRM (Bitfield-Mask: 0x03) */
+#define UART2_CR0_OVDIS_Pos (17UL) /*!< OVDIS (Bit 17) */
+#define UART2_CR0_OVDIS_Msk (0x20000UL) /*!< OVDIS (Bitfield-Mask: 0x01) */
+#define UART2_CR0_LOOP_Pos (16UL) /*!< LOOP (Bit 16) */
+#define UART2_CR0_LOOP_Msk (0x10000UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define UART2_CR0_ONEBIT_Pos (15UL) /*!< ONEBIT (Bit 15) */
+#define UART2_CR0_ONEBIT_Msk (0x8000UL) /*!< ONEBIT (Bitfield-Mask: 0x01) */
+#define UART2_CR0_RTOM_Pos (14UL) /*!< RTOM (Bit 14) */
+#define UART2_CR0_RTOM_Msk (0x4000UL) /*!< RTOM (Bitfield-Mask: 0x01) */
+#define UART2_CR0_NFE_Pos (13UL) /*!< NFE (Bit 13) */
+#define UART2_CR0_NFE_Msk (0x2000UL) /*!< NFE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_OVER8_Pos (12UL) /*!< OVER8 (Bit 12) */
+#define UART2_CR0_OVER8_Msk (0x1000UL) /*!< OVER8 (Bitfield-Mask: 0x01) */
+#define UART2_CR0_RTOE_Pos (11UL) /*!< RTOE (Bit 11) */
+#define UART2_CR0_RTOE_Msk (0x800UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_TPOL_Pos (10UL) /*!< TPOL (Bit 10) */
+#define UART2_CR0_TPOL_Msk (0x400UL) /*!< TPOL (Bitfield-Mask: 0x01) */
+#define UART2_CR0_RPOL_Pos (9UL) /*!< RPOL (Bit 9) */
+#define UART2_CR0_RPOL_Msk (0x200UL) /*!< RPOL (Bitfield-Mask: 0x01) */
+#define UART2_CR0_SWAP_Pos (8UL) /*!< SWAP (Bit 8) */
+#define UART2_CR0_SWAP_Msk (0x100UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define UART2_CR0_OWE_Pos (7UL) /*!< OWE (Bit 7) */
+#define UART2_CR0_OWE_Msk (0x80UL) /*!< OWE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_DTE_Pos (6UL) /*!< DTE (Bit 6) */
+#define UART2_CR0_DTE_Msk (0x40UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_DRE_Pos (5UL) /*!< DRE (Bit 5) */
+#define UART2_CR0_DRE_Msk (0x20UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_TFR_Pos (4UL) /*!< TFR (Bit 4) */
+#define UART2_CR0_TFR_Msk (0x10UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define UART2_CR0_RFR_Pos (3UL) /*!< RFR (Bit 3) */
+#define UART2_CR0_RFR_Msk (0x8UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define UART2_CR0_TE_Pos (2UL) /*!< TE (Bit 2) */
+#define UART2_CR0_TE_Msk (0x4UL) /*!< TE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_RE_Pos (1UL) /*!< RE (Bit 1) */
+#define UART2_CR0_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_UE_Pos (0UL) /*!< UE (Bit 0) */
+#define UART2_CR0_UE_Msk (0x1UL) /*!< UE (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define UART2_CR1_ABR_Pos (21UL) /*!< ABR (Bit 21) */
+#define UART2_CR1_ABR_Msk (0x200000UL) /*!< ABR (Bitfield-Mask: 0x01) */
+#define UART2_CR1_IDR_Pos (20UL) /*!< IDR (Bit 20) */
+#define UART2_CR1_IDR_Msk (0x100000UL) /*!< IDR (Bitfield-Mask: 0x01) */
+#define UART2_CR1_BKR_Pos (19UL) /*!< BKR (Bit 19) */
+#define UART2_CR1_BKR_Msk (0x80000UL) /*!< BKR (Bitfield-Mask: 0x01) */
+#define UART2_CR1_TEM_Pos (18UL) /*!< TEM (Bit 18) */
+#define UART2_CR1_TEM_Msk (0x40000UL) /*!< TEM (Bitfield-Mask: 0x01) */
+#define UART2_CR1_REM_Pos (17UL) /*!< REM (Bit 17) */
+#define UART2_CR1_REM_Msk (0x20000UL) /*!< REM (Bitfield-Mask: 0x01) */
+#define UART2_CR1_EBE_Pos (16UL) /*!< EBE (Bit 16) */
+#define UART2_CR1_EBE_Msk (0x10000UL) /*!< EBE (Bitfield-Mask: 0x01) */
+#define UART2_CR1_DEP_Pos (10UL) /*!< DEP (Bit 10) */
+#define UART2_CR1_DEP_Msk (0x400UL) /*!< DEP (Bitfield-Mask: 0x01) */
+#define UART2_CR1_REP_Pos (9UL) /*!< REP (Bit 9) */
+#define UART2_CR1_REP_Msk (0x200UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define UART2_CR1_RS485E_Pos (8UL) /*!< RS485E (Bit 8) */
+#define UART2_CR1_RS485E_Msk (0x100UL) /*!< RS485E (Bitfield-Mask: 0x01) */
+#define UART2_CR1_MSB_Pos (7UL) /*!< MSB (Bit 7) */
+#define UART2_CR1_MSB_Msk (0x80UL) /*!< MSB (Bitfield-Mask: 0x01) */
+#define UART2_CR1_SPE_Pos (5UL) /*!< SPE (Bit 5) */
+#define UART2_CR1_SPE_Msk (0x20UL) /*!< SPE (Bitfield-Mask: 0x01) */
+#define UART2_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
+#define UART2_CR1_PSEL_Msk (0x10UL) /*!< PSEL (Bitfield-Mask: 0x01) */
+#define UART2_CR1_PEN_Pos (3UL) /*!< PEN (Bit 3) */
+#define UART2_CR1_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
+#define UART2_CR1_STP_Pos (2UL) /*!< STP (Bit 2) */
+#define UART2_CR1_STP_Msk (0x4UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define UART2_CR1_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+#define UART2_CR1_LEN_Msk (0x3UL) /*!< LEN (Bitfield-Mask: 0x03) */
+/* ========================================================= BAUD ========================================================== */
+#define UART2_BAUD_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define UART2_BAUD_BAUD_Msk (0xffffUL) /*!< BAUD (Bitfield-Mask: 0xffff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define UART2_FIFOCTRL_TXFT_Pos (4UL) /*!< TXFT (Bit 4) */
+#define UART2_FIFOCTRL_TXFT_Msk (0xf0UL) /*!< TXFT (Bitfield-Mask: 0x0f) */
+#define UART2_FIFOCTRL_RXFT_Pos (0UL) /*!< RXFT (Bit 0) */
+#define UART2_FIFOCTRL_RXFT_Msk (0xfUL) /*!< RXFT (Bitfield-Mask: 0x0f) */
+/* ======================================================== TIMING0 ======================================================== */
+#define UART2_TIMING0_DEDT_Pos (16UL) /*!< DEDT (Bit 16) */
+#define UART2_TIMING0_DEDT_Msk (0xffff0000UL) /*!< DEDT (Bitfield-Mask: 0xffff) */
+#define UART2_TIMING0_DEAT_Pos (0UL) /*!< DEAT (Bit 0) */
+#define UART2_TIMING0_DEAT_Msk (0xffffUL) /*!< DEAT (Bitfield-Mask: 0xffff) */
+/* ======================================================== TIMING1 ======================================================== */
+#define UART2_TIMING1_DRET_Pos (16UL) /*!< DRET (Bit 16) */
+#define UART2_TIMING1_DRET_Msk (0xffff0000UL) /*!< DRET (Bitfield-Mask: 0xffff) */
+#define UART2_TIMING1_RDET_Pos (0UL) /*!< RDET (Bit 0) */
+#define UART2_TIMING1_RDET_Msk (0xffffUL) /*!< RDET (Bitfield-Mask: 0xffff) */
+/* ========================================================== TDR ========================================================== */
+#define UART2_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define UART2_TDR_TD_Msk (0x1ffUL) /*!< TD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== RDR ========================================================== */
+#define UART2_RDR_OVDA_Pos (16UL) /*!< OVDA (Bit 16) */
+#define UART2_RDR_OVDA_Msk (0x7ff0000UL) /*!< OVDA (Bitfield-Mask: 0x7ff) */
+#define UART2_RDR_FMST_Pos (10UL) /*!< FMST (Bit 10) */
+#define UART2_RDR_FMST_Msk (0x400UL) /*!< FMST (Bitfield-Mask: 0x01) */
+#define UART2_RDR_PRST_Pos (9UL) /*!< PRST (Bit 9) */
+#define UART2_RDR_PRST_Msk (0x200UL) /*!< PRST (Bitfield-Mask: 0x01) */
+#define UART2_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define UART2_RDR_RD_Msk (0x1ffUL) /*!< RD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== TAR ========================================================== */
+#define UART2_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define UART2_TAR_TAR_Msk (0xffUL) /*!< TAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RAR ========================================================== */
+#define UART2_RAR_RAR_Pos (0UL) /*!< RAR (Bit 0) */
+#define UART2_RAR_RAR_Msk (0xffUL) /*!< RAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RTO ========================================================== */
+#define UART2_RTO_RTO_Pos (0UL) /*!< RTO (Bit 0) */
+#define UART2_RTO_RTO_Msk (0xffffUL) /*!< RTO (Bitfield-Mask: 0xffff) */
+/* ========================================================= INTEN ========================================================= */
+#define UART2_INTEN_ABRE_Pos (16UL) /*!< ABRE (Bit 16) */
+#define UART2_INTEN_ABRE_Msk (0x10000UL) /*!< ABRE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_AMIE_Pos (15UL) /*!< AMIE (Bit 15) */
+#define UART2_INTEN_AMIE_Msk (0x8000UL) /*!< AMIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_IDLE_Pos (14UL) /*!< IDLE (Bit 14) */
+#define UART2_INTEN_IDLE_Msk (0x4000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_TBIE_Pos (13UL) /*!< TBIE (Bit 13) */
+#define UART2_INTEN_TBIE_Msk (0x2000UL) /*!< TBIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_TDIE_Pos (12UL) /*!< TDIE (Bit 12) */
+#define UART2_INTEN_TDIE_Msk (0x1000UL) /*!< TDIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_RTIE_Pos (11UL) /*!< RTIE (Bit 11) */
+#define UART2_INTEN_RTIE_Msk (0x800UL) /*!< RTIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_BKIE_Pos (10UL) /*!< BKIE (Bit 10) */
+#define UART2_INTEN_BKIE_Msk (0x400UL) /*!< BKIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_FEIE_Pos (9UL) /*!< FEIE (Bit 9) */
+#define UART2_INTEN_FEIE_Msk (0x200UL) /*!< FEIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_PEIE_Pos (8UL) /*!< PEIE (Bit 8) */
+#define UART2_INTEN_PEIE_Msk (0x100UL) /*!< PEIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_NOIE_Pos (7UL) /*!< NOIE (Bit 7) */
+#define UART2_INTEN_NOIE_Msk (0x80UL) /*!< NOIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_IDIE_Pos (6UL) /*!< IDIE (Bit 6) */
+#define UART2_INTEN_IDIE_Msk (0x40UL) /*!< IDIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_TOIE_Pos (4UL) /*!< TOIE (Bit 4) */
+#define UART2_INTEN_TOIE_Msk (0x10UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_RUIE_Pos (3UL) /*!< RUIE (Bit 3) */
+#define UART2_INTEN_RUIE_Msk (0x8UL) /*!< RUIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_ROIE_Pos (2UL) /*!< ROIE (Bit 2) */
+#define UART2_INTEN_ROIE_Msk (0x4UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_TEIE_Pos (1UL) /*!< TEIE (Bit 1) */
+#define UART2_INTEN_TEIE_Msk (0x2UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_RFIE_Pos (0UL) /*!< RFIE (Bit 0) */
+#define UART2_INTEN_RFIE_Msk (0x1UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define UART2_INT_ABRF_Pos (16UL) /*!< ABRF (Bit 16) */
+#define UART2_INT_ABRF_Msk (0x10000UL) /*!< ABRF (Bitfield-Mask: 0x01) */
+#define UART2_INT_AMIF_Pos (15UL) /*!< AMIF (Bit 15) */
+#define UART2_INT_AMIF_Msk (0x8000UL) /*!< AMIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_IDLF_Pos (14UL) /*!< IDLF (Bit 14) */
+#define UART2_INT_IDLF_Msk (0x4000UL) /*!< IDLF (Bitfield-Mask: 0x01) */
+#define UART2_INT_TBIF_Pos (13UL) /*!< TBIF (Bit 13) */
+#define UART2_INT_TBIF_Msk (0x2000UL) /*!< TBIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_TDIF_Pos (12UL) /*!< TDIF (Bit 12) */
+#define UART2_INT_TDIF_Msk (0x1000UL) /*!< TDIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_RTOI_Pos (11UL) /*!< RTOI (Bit 11) */
+#define UART2_INT_RTOI_Msk (0x800UL) /*!< RTOI (Bitfield-Mask: 0x01) */
+#define UART2_INT_BKIF_Pos (10UL) /*!< BKIF (Bit 10) */
+#define UART2_INT_BKIF_Msk (0x400UL) /*!< BKIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_FEIF_Pos (9UL) /*!< FEIF (Bit 9) */
+#define UART2_INT_FEIF_Msk (0x200UL) /*!< FEIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_PEIF_Pos (8UL) /*!< PEIF (Bit 8) */
+#define UART2_INT_PEIF_Msk (0x100UL) /*!< PEIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_NOIF_Pos (7UL) /*!< NOIF (Bit 7) */
+#define UART2_INT_NOIF_Msk (0x80UL) /*!< NOIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_IDIF_Pos (6UL) /*!< IDIF (Bit 6) */
+#define UART2_INT_IDIF_Msk (0x40UL) /*!< IDIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_TOIF_Pos (4UL) /*!< TOIF (Bit 4) */
+#define UART2_INT_TOIF_Msk (0x10UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_RUIF_Pos (3UL) /*!< RUIF (Bit 3) */
+#define UART2_INT_RUIF_Msk (0x8UL) /*!< RUIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_ROIF_Pos (2UL) /*!< ROIF (Bit 2) */
+#define UART2_INT_ROIF_Msk (0x4UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define UART2_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define UART2_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define UART2_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define UART2_STATUS_RSE_Pos (16UL) /*!< RSE (Bit 16) */
+#define UART2_STATUS_RSE_Msk (0x10000UL) /*!< RSE (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_RFL_Pos (11UL) /*!< RFL (Bit 11) */
+#define UART2_STATUS_RFL_Msk (0xf800UL) /*!< RFL (Bitfield-Mask: 0x1f) */
+#define UART2_STATUS_RFF_Pos (10UL) /*!< RFF (Bit 10) */
+#define UART2_STATUS_RFF_Msk (0x400UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_RFE_Pos (9UL) /*!< RFE (Bit 9) */
+#define UART2_STATUS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_RBSY_Pos (8UL) /*!< RBSY (Bit 8) */
+#define UART2_STATUS_RBSY_Msk (0x100UL) /*!< RBSY (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_TFL_Pos (3UL) /*!< TFL (Bit 3) */
+#define UART2_STATUS_TFL_Msk (0xf8UL) /*!< TFL (Bitfield-Mask: 0x1f) */
+#define UART2_STATUS_TFF_Pos (2UL) /*!< TFF (Bit 2) */
+#define UART2_STATUS_TFF_Msk (0x4UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_TFE_Pos (1UL) /*!< TFE (Bit 1) */
+#define UART2_STATUS_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_TBSY_Pos (0UL) /*!< TBSY (Bit 0) */
+#define UART2_STATUS_TBSY_Msk (0x1UL) /*!< TBSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define UART3_CR0_ABRM_Pos (20UL) /*!< ABRM (Bit 20) */
+#define UART3_CR0_ABRM_Msk (0x300000UL) /*!< ABRM (Bitfield-Mask: 0x03) */
+#define UART3_CR0_OVDIS_Pos (17UL) /*!< OVDIS (Bit 17) */
+#define UART3_CR0_OVDIS_Msk (0x20000UL) /*!< OVDIS (Bitfield-Mask: 0x01) */
+#define UART3_CR0_LOOP_Pos (16UL) /*!< LOOP (Bit 16) */
+#define UART3_CR0_LOOP_Msk (0x10000UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define UART3_CR0_ONEBIT_Pos (15UL) /*!< ONEBIT (Bit 15) */
+#define UART3_CR0_ONEBIT_Msk (0x8000UL) /*!< ONEBIT (Bitfield-Mask: 0x01) */
+#define UART3_CR0_RTOM_Pos (14UL) /*!< RTOM (Bit 14) */
+#define UART3_CR0_RTOM_Msk (0x4000UL) /*!< RTOM (Bitfield-Mask: 0x01) */
+#define UART3_CR0_NFE_Pos (13UL) /*!< NFE (Bit 13) */
+#define UART3_CR0_NFE_Msk (0x2000UL) /*!< NFE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_OVER8_Pos (12UL) /*!< OVER8 (Bit 12) */
+#define UART3_CR0_OVER8_Msk (0x1000UL) /*!< OVER8 (Bitfield-Mask: 0x01) */
+#define UART3_CR0_RTOE_Pos (11UL) /*!< RTOE (Bit 11) */
+#define UART3_CR0_RTOE_Msk (0x800UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_TPOL_Pos (10UL) /*!< TPOL (Bit 10) */
+#define UART3_CR0_TPOL_Msk (0x400UL) /*!< TPOL (Bitfield-Mask: 0x01) */
+#define UART3_CR0_RPOL_Pos (9UL) /*!< RPOL (Bit 9) */
+#define UART3_CR0_RPOL_Msk (0x200UL) /*!< RPOL (Bitfield-Mask: 0x01) */
+#define UART3_CR0_SWAP_Pos (8UL) /*!< SWAP (Bit 8) */
+#define UART3_CR0_SWAP_Msk (0x100UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define UART3_CR0_OWE_Pos (7UL) /*!< OWE (Bit 7) */
+#define UART3_CR0_OWE_Msk (0x80UL) /*!< OWE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_DTE_Pos (6UL) /*!< DTE (Bit 6) */
+#define UART3_CR0_DTE_Msk (0x40UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_DRE_Pos (5UL) /*!< DRE (Bit 5) */
+#define UART3_CR0_DRE_Msk (0x20UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_TFR_Pos (4UL) /*!< TFR (Bit 4) */
+#define UART3_CR0_TFR_Msk (0x10UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define UART3_CR0_RFR_Pos (3UL) /*!< RFR (Bit 3) */
+#define UART3_CR0_RFR_Msk (0x8UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define UART3_CR0_TE_Pos (2UL) /*!< TE (Bit 2) */
+#define UART3_CR0_TE_Msk (0x4UL) /*!< TE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_RE_Pos (1UL) /*!< RE (Bit 1) */
+#define UART3_CR0_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_UE_Pos (0UL) /*!< UE (Bit 0) */
+#define UART3_CR0_UE_Msk (0x1UL) /*!< UE (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define UART3_CR1_ABR_Pos (21UL) /*!< ABR (Bit 21) */
+#define UART3_CR1_ABR_Msk (0x200000UL) /*!< ABR (Bitfield-Mask: 0x01) */
+#define UART3_CR1_IDR_Pos (20UL) /*!< IDR (Bit 20) */
+#define UART3_CR1_IDR_Msk (0x100000UL) /*!< IDR (Bitfield-Mask: 0x01) */
+#define UART3_CR1_BKR_Pos (19UL) /*!< BKR (Bit 19) */
+#define UART3_CR1_BKR_Msk (0x80000UL) /*!< BKR (Bitfield-Mask: 0x01) */
+#define UART3_CR1_TEM_Pos (18UL) /*!< TEM (Bit 18) */
+#define UART3_CR1_TEM_Msk (0x40000UL) /*!< TEM (Bitfield-Mask: 0x01) */
+#define UART3_CR1_REM_Pos (17UL) /*!< REM (Bit 17) */
+#define UART3_CR1_REM_Msk (0x20000UL) /*!< REM (Bitfield-Mask: 0x01) */
+#define UART3_CR1_EBE_Pos (16UL) /*!< EBE (Bit 16) */
+#define UART3_CR1_EBE_Msk (0x10000UL) /*!< EBE (Bitfield-Mask: 0x01) */
+#define UART3_CR1_DEP_Pos (10UL) /*!< DEP (Bit 10) */
+#define UART3_CR1_DEP_Msk (0x400UL) /*!< DEP (Bitfield-Mask: 0x01) */
+#define UART3_CR1_REP_Pos (9UL) /*!< REP (Bit 9) */
+#define UART3_CR1_REP_Msk (0x200UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define UART3_CR1_RS485E_Pos (8UL) /*!< RS485E (Bit 8) */
+#define UART3_CR1_RS485E_Msk (0x100UL) /*!< RS485E (Bitfield-Mask: 0x01) */
+#define UART3_CR1_MSB_Pos (7UL) /*!< MSB (Bit 7) */
+#define UART3_CR1_MSB_Msk (0x80UL) /*!< MSB (Bitfield-Mask: 0x01) */
+#define UART3_CR1_SPE_Pos (5UL) /*!< SPE (Bit 5) */
+#define UART3_CR1_SPE_Msk (0x20UL) /*!< SPE (Bitfield-Mask: 0x01) */
+#define UART3_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
+#define UART3_CR1_PSEL_Msk (0x10UL) /*!< PSEL (Bitfield-Mask: 0x01) */
+#define UART3_CR1_PEN_Pos (3UL) /*!< PEN (Bit 3) */
+#define UART3_CR1_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
+#define UART3_CR1_STP_Pos (2UL) /*!< STP (Bit 2) */
+#define UART3_CR1_STP_Msk (0x4UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define UART3_CR1_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+#define UART3_CR1_LEN_Msk (0x3UL) /*!< LEN (Bitfield-Mask: 0x03) */
+/* ========================================================= BAUD ========================================================== */
+#define UART3_BAUD_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define UART3_BAUD_BAUD_Msk (0xffffUL) /*!< BAUD (Bitfield-Mask: 0xffff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define UART3_FIFOCTRL_TXFT_Pos (4UL) /*!< TXFT (Bit 4) */
+#define UART3_FIFOCTRL_TXFT_Msk (0xf0UL) /*!< TXFT (Bitfield-Mask: 0x0f) */
+#define UART3_FIFOCTRL_RXFT_Pos (0UL) /*!< RXFT (Bit 0) */
+#define UART3_FIFOCTRL_RXFT_Msk (0xfUL) /*!< RXFT (Bitfield-Mask: 0x0f) */
+/* ======================================================== TIMING0 ======================================================== */
+#define UART3_TIMING0_DEDT_Pos (16UL) /*!< DEDT (Bit 16) */
+#define UART3_TIMING0_DEDT_Msk (0xffff0000UL) /*!< DEDT (Bitfield-Mask: 0xffff) */
+#define UART3_TIMING0_DEAT_Pos (0UL) /*!< DEAT (Bit 0) */
+#define UART3_TIMING0_DEAT_Msk (0xffffUL) /*!< DEAT (Bitfield-Mask: 0xffff) */
+/* ======================================================== TIMING1 ======================================================== */
+#define UART3_TIMING1_DRET_Pos (16UL) /*!< DRET (Bit 16) */
+#define UART3_TIMING1_DRET_Msk (0xffff0000UL) /*!< DRET (Bitfield-Mask: 0xffff) */
+#define UART3_TIMING1_RDET_Pos (0UL) /*!< RDET (Bit 0) */
+#define UART3_TIMING1_RDET_Msk (0xffffUL) /*!< RDET (Bitfield-Mask: 0xffff) */
+/* ========================================================== TDR ========================================================== */
+#define UART3_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define UART3_TDR_TD_Msk (0x1ffUL) /*!< TD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== RDR ========================================================== */
+#define UART3_RDR_OVDA_Pos (16UL) /*!< OVDA (Bit 16) */
+#define UART3_RDR_OVDA_Msk (0x7ff0000UL) /*!< OVDA (Bitfield-Mask: 0x7ff) */
+#define UART3_RDR_FMST_Pos (10UL) /*!< FMST (Bit 10) */
+#define UART3_RDR_FMST_Msk (0x400UL) /*!< FMST (Bitfield-Mask: 0x01) */
+#define UART3_RDR_PRST_Pos (9UL) /*!< PRST (Bit 9) */
+#define UART3_RDR_PRST_Msk (0x200UL) /*!< PRST (Bitfield-Mask: 0x01) */
+#define UART3_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define UART3_RDR_RD_Msk (0x1ffUL) /*!< RD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== TAR ========================================================== */
+#define UART3_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define UART3_TAR_TAR_Msk (0xffUL) /*!< TAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RAR ========================================================== */
+#define UART3_RAR_RAR_Pos (0UL) /*!< RAR (Bit 0) */
+#define UART3_RAR_RAR_Msk (0xffUL) /*!< RAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RTO ========================================================== */
+#define UART3_RTO_RTO_Pos (0UL) /*!< RTO (Bit 0) */
+#define UART3_RTO_RTO_Msk (0xffffUL) /*!< RTO (Bitfield-Mask: 0xffff) */
+/* ========================================================= INTEN ========================================================= */
+#define UART3_INTEN_ABRE_Pos (16UL) /*!< ABRE (Bit 16) */
+#define UART3_INTEN_ABRE_Msk (0x10000UL) /*!< ABRE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_AMIE_Pos (15UL) /*!< AMIE (Bit 15) */
+#define UART3_INTEN_AMIE_Msk (0x8000UL) /*!< AMIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_IDLE_Pos (14UL) /*!< IDLE (Bit 14) */
+#define UART3_INTEN_IDLE_Msk (0x4000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_TBIE_Pos (13UL) /*!< TBIE (Bit 13) */
+#define UART3_INTEN_TBIE_Msk (0x2000UL) /*!< TBIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_TDIE_Pos (12UL) /*!< TDIE (Bit 12) */
+#define UART3_INTEN_TDIE_Msk (0x1000UL) /*!< TDIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_RTIE_Pos (11UL) /*!< RTIE (Bit 11) */
+#define UART3_INTEN_RTIE_Msk (0x800UL) /*!< RTIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_BKIE_Pos (10UL) /*!< BKIE (Bit 10) */
+#define UART3_INTEN_BKIE_Msk (0x400UL) /*!< BKIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_FEIE_Pos (9UL) /*!< FEIE (Bit 9) */
+#define UART3_INTEN_FEIE_Msk (0x200UL) /*!< FEIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_PEIE_Pos (8UL) /*!< PEIE (Bit 8) */
+#define UART3_INTEN_PEIE_Msk (0x100UL) /*!< PEIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_NOIE_Pos (7UL) /*!< NOIE (Bit 7) */
+#define UART3_INTEN_NOIE_Msk (0x80UL) /*!< NOIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_IDIE_Pos (6UL) /*!< IDIE (Bit 6) */
+#define UART3_INTEN_IDIE_Msk (0x40UL) /*!< IDIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_TOIE_Pos (4UL) /*!< TOIE (Bit 4) */
+#define UART3_INTEN_TOIE_Msk (0x10UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_RUIE_Pos (3UL) /*!< RUIE (Bit 3) */
+#define UART3_INTEN_RUIE_Msk (0x8UL) /*!< RUIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_ROIE_Pos (2UL) /*!< ROIE (Bit 2) */
+#define UART3_INTEN_ROIE_Msk (0x4UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_TEIE_Pos (1UL) /*!< TEIE (Bit 1) */
+#define UART3_INTEN_TEIE_Msk (0x2UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_RFIE_Pos (0UL) /*!< RFIE (Bit 0) */
+#define UART3_INTEN_RFIE_Msk (0x1UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define UART3_INT_ABRF_Pos (16UL) /*!< ABRF (Bit 16) */
+#define UART3_INT_ABRF_Msk (0x10000UL) /*!< ABRF (Bitfield-Mask: 0x01) */
+#define UART3_INT_AMIF_Pos (15UL) /*!< AMIF (Bit 15) */
+#define UART3_INT_AMIF_Msk (0x8000UL) /*!< AMIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_IDLF_Pos (14UL) /*!< IDLF (Bit 14) */
+#define UART3_INT_IDLF_Msk (0x4000UL) /*!< IDLF (Bitfield-Mask: 0x01) */
+#define UART3_INT_TBIF_Pos (13UL) /*!< TBIF (Bit 13) */
+#define UART3_INT_TBIF_Msk (0x2000UL) /*!< TBIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_TDIF_Pos (12UL) /*!< TDIF (Bit 12) */
+#define UART3_INT_TDIF_Msk (0x1000UL) /*!< TDIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_RTOI_Pos (11UL) /*!< RTOI (Bit 11) */
+#define UART3_INT_RTOI_Msk (0x800UL) /*!< RTOI (Bitfield-Mask: 0x01) */
+#define UART3_INT_BKIF_Pos (10UL) /*!< BKIF (Bit 10) */
+#define UART3_INT_BKIF_Msk (0x400UL) /*!< BKIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_FEIF_Pos (9UL) /*!< FEIF (Bit 9) */
+#define UART3_INT_FEIF_Msk (0x200UL) /*!< FEIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_PEIF_Pos (8UL) /*!< PEIF (Bit 8) */
+#define UART3_INT_PEIF_Msk (0x100UL) /*!< PEIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_NOIF_Pos (7UL) /*!< NOIF (Bit 7) */
+#define UART3_INT_NOIF_Msk (0x80UL) /*!< NOIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_IDIF_Pos (6UL) /*!< IDIF (Bit 6) */
+#define UART3_INT_IDIF_Msk (0x40UL) /*!< IDIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_TOIF_Pos (4UL) /*!< TOIF (Bit 4) */
+#define UART3_INT_TOIF_Msk (0x10UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_RUIF_Pos (3UL) /*!< RUIF (Bit 3) */
+#define UART3_INT_RUIF_Msk (0x8UL) /*!< RUIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_ROIF_Pos (2UL) /*!< ROIF (Bit 2) */
+#define UART3_INT_ROIF_Msk (0x4UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define UART3_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define UART3_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define UART3_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define UART3_STATUS_RSE_Pos (16UL) /*!< RSE (Bit 16) */
+#define UART3_STATUS_RSE_Msk (0x10000UL) /*!< RSE (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_RFL_Pos (11UL) /*!< RFL (Bit 11) */
+#define UART3_STATUS_RFL_Msk (0xf800UL) /*!< RFL (Bitfield-Mask: 0x1f) */
+#define UART3_STATUS_RFF_Pos (10UL) /*!< RFF (Bit 10) */
+#define UART3_STATUS_RFF_Msk (0x400UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_RFE_Pos (9UL) /*!< RFE (Bit 9) */
+#define UART3_STATUS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_RBSY_Pos (8UL) /*!< RBSY (Bit 8) */
+#define UART3_STATUS_RBSY_Msk (0x100UL) /*!< RBSY (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_TFL_Pos (3UL) /*!< TFL (Bit 3) */
+#define UART3_STATUS_TFL_Msk (0xf8UL) /*!< TFL (Bitfield-Mask: 0x1f) */
+#define UART3_STATUS_TFF_Pos (2UL) /*!< TFF (Bit 2) */
+#define UART3_STATUS_TFF_Msk (0x4UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_TFE_Pos (1UL) /*!< TFE (Bit 1) */
+#define UART3_STATUS_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_TBSY_Pos (0UL) /*!< TBSY (Bit 0) */
+#define UART3_STATUS_TBSY_Msk (0x1UL) /*!< TBSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define UART4_CR0_ABRM_Pos (20UL) /*!< ABRM (Bit 20) */
+#define UART4_CR0_ABRM_Msk (0x300000UL) /*!< ABRM (Bitfield-Mask: 0x03) */
+#define UART4_CR0_OVDIS_Pos (17UL) /*!< OVDIS (Bit 17) */
+#define UART4_CR0_OVDIS_Msk (0x20000UL) /*!< OVDIS (Bitfield-Mask: 0x01) */
+#define UART4_CR0_LOOP_Pos (16UL) /*!< LOOP (Bit 16) */
+#define UART4_CR0_LOOP_Msk (0x10000UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define UART4_CR0_ONEBIT_Pos (15UL) /*!< ONEBIT (Bit 15) */
+#define UART4_CR0_ONEBIT_Msk (0x8000UL) /*!< ONEBIT (Bitfield-Mask: 0x01) */
+#define UART4_CR0_RTOM_Pos (14UL) /*!< RTOM (Bit 14) */
+#define UART4_CR0_RTOM_Msk (0x4000UL) /*!< RTOM (Bitfield-Mask: 0x01) */
+#define UART4_CR0_NFE_Pos (13UL) /*!< NFE (Bit 13) */
+#define UART4_CR0_NFE_Msk (0x2000UL) /*!< NFE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_OVER8_Pos (12UL) /*!< OVER8 (Bit 12) */
+#define UART4_CR0_OVER8_Msk (0x1000UL) /*!< OVER8 (Bitfield-Mask: 0x01) */
+#define UART4_CR0_RTOE_Pos (11UL) /*!< RTOE (Bit 11) */
+#define UART4_CR0_RTOE_Msk (0x800UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_TPOL_Pos (10UL) /*!< TPOL (Bit 10) */
+#define UART4_CR0_TPOL_Msk (0x400UL) /*!< TPOL (Bitfield-Mask: 0x01) */
+#define UART4_CR0_RPOL_Pos (9UL) /*!< RPOL (Bit 9) */
+#define UART4_CR0_RPOL_Msk (0x200UL) /*!< RPOL (Bitfield-Mask: 0x01) */
+#define UART4_CR0_SWAP_Pos (8UL) /*!< SWAP (Bit 8) */
+#define UART4_CR0_SWAP_Msk (0x100UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define UART4_CR0_OWE_Pos (7UL) /*!< OWE (Bit 7) */
+#define UART4_CR0_OWE_Msk (0x80UL) /*!< OWE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_DTE_Pos (6UL) /*!< DTE (Bit 6) */
+#define UART4_CR0_DTE_Msk (0x40UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_DRE_Pos (5UL) /*!< DRE (Bit 5) */
+#define UART4_CR0_DRE_Msk (0x20UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_TFR_Pos (4UL) /*!< TFR (Bit 4) */
+#define UART4_CR0_TFR_Msk (0x10UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define UART4_CR0_RFR_Pos (3UL) /*!< RFR (Bit 3) */
+#define UART4_CR0_RFR_Msk (0x8UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define UART4_CR0_TE_Pos (2UL) /*!< TE (Bit 2) */
+#define UART4_CR0_TE_Msk (0x4UL) /*!< TE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_RE_Pos (1UL) /*!< RE (Bit 1) */
+#define UART4_CR0_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_UE_Pos (0UL) /*!< UE (Bit 0) */
+#define UART4_CR0_UE_Msk (0x1UL) /*!< UE (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define UART4_CR1_ABR_Pos (21UL) /*!< ABR (Bit 21) */
+#define UART4_CR1_ABR_Msk (0x200000UL) /*!< ABR (Bitfield-Mask: 0x01) */
+#define UART4_CR1_IDR_Pos (20UL) /*!< IDR (Bit 20) */
+#define UART4_CR1_IDR_Msk (0x100000UL) /*!< IDR (Bitfield-Mask: 0x01) */
+#define UART4_CR1_BKR_Pos (19UL) /*!< BKR (Bit 19) */
+#define UART4_CR1_BKR_Msk (0x80000UL) /*!< BKR (Bitfield-Mask: 0x01) */
+#define UART4_CR1_TEM_Pos (18UL) /*!< TEM (Bit 18) */
+#define UART4_CR1_TEM_Msk (0x40000UL) /*!< TEM (Bitfield-Mask: 0x01) */
+#define UART4_CR1_REM_Pos (17UL) /*!< REM (Bit 17) */
+#define UART4_CR1_REM_Msk (0x20000UL) /*!< REM (Bitfield-Mask: 0x01) */
+#define UART4_CR1_EBE_Pos (16UL) /*!< EBE (Bit 16) */
+#define UART4_CR1_EBE_Msk (0x10000UL) /*!< EBE (Bitfield-Mask: 0x01) */
+#define UART4_CR1_DEP_Pos (10UL) /*!< DEP (Bit 10) */
+#define UART4_CR1_DEP_Msk (0x400UL) /*!< DEP (Bitfield-Mask: 0x01) */
+#define UART4_CR1_REP_Pos (9UL) /*!< REP (Bit 9) */
+#define UART4_CR1_REP_Msk (0x200UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define UART4_CR1_RS485E_Pos (8UL) /*!< RS485E (Bit 8) */
+#define UART4_CR1_RS485E_Msk (0x100UL) /*!< RS485E (Bitfield-Mask: 0x01) */
+#define UART4_CR1_MSB_Pos (7UL) /*!< MSB (Bit 7) */
+#define UART4_CR1_MSB_Msk (0x80UL) /*!< MSB (Bitfield-Mask: 0x01) */
+#define UART4_CR1_SPE_Pos (5UL) /*!< SPE (Bit 5) */
+#define UART4_CR1_SPE_Msk (0x20UL) /*!< SPE (Bitfield-Mask: 0x01) */
+#define UART4_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
+#define UART4_CR1_PSEL_Msk (0x10UL) /*!< PSEL (Bitfield-Mask: 0x01) */
+#define UART4_CR1_PEN_Pos (3UL) /*!< PEN (Bit 3) */
+#define UART4_CR1_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
+#define UART4_CR1_STP_Pos (2UL) /*!< STP (Bit 2) */
+#define UART4_CR1_STP_Msk (0x4UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define UART4_CR1_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+#define UART4_CR1_LEN_Msk (0x3UL) /*!< LEN (Bitfield-Mask: 0x03) */
+/* ========================================================= BAUD ========================================================== */
+#define UART4_BAUD_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define UART4_BAUD_BAUD_Msk (0xffffUL) /*!< BAUD (Bitfield-Mask: 0xffff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define UART4_FIFOCTRL_TXFT_Pos (4UL) /*!< TXFT (Bit 4) */
+#define UART4_FIFOCTRL_TXFT_Msk (0xf0UL) /*!< TXFT (Bitfield-Mask: 0x0f) */
+#define UART4_FIFOCTRL_RXFT_Pos (0UL) /*!< RXFT (Bit 0) */
+#define UART4_FIFOCTRL_RXFT_Msk (0xfUL) /*!< RXFT (Bitfield-Mask: 0x0f) */
+/* ======================================================== TIMING0 ======================================================== */
+#define UART4_TIMING0_DEDT_Pos (16UL) /*!< DEDT (Bit 16) */
+#define UART4_TIMING0_DEDT_Msk (0xffff0000UL) /*!< DEDT (Bitfield-Mask: 0xffff) */
+#define UART4_TIMING0_DEAT_Pos (0UL) /*!< DEAT (Bit 0) */
+#define UART4_TIMING0_DEAT_Msk (0xffffUL) /*!< DEAT (Bitfield-Mask: 0xffff) */
+/* ======================================================== TIMING1 ======================================================== */
+#define UART4_TIMING1_DRET_Pos (16UL) /*!< DRET (Bit 16) */
+#define UART4_TIMING1_DRET_Msk (0xffff0000UL) /*!< DRET (Bitfield-Mask: 0xffff) */
+#define UART4_TIMING1_RDET_Pos (0UL) /*!< RDET (Bit 0) */
+#define UART4_TIMING1_RDET_Msk (0xffffUL) /*!< RDET (Bitfield-Mask: 0xffff) */
+/* ========================================================== TDR ========================================================== */
+#define UART4_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define UART4_TDR_TD_Msk (0x1ffUL) /*!< TD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== RDR ========================================================== */
+#define UART4_RDR_OVDA_Pos (16UL) /*!< OVDA (Bit 16) */
+#define UART4_RDR_OVDA_Msk (0x7ff0000UL) /*!< OVDA (Bitfield-Mask: 0x7ff) */
+#define UART4_RDR_FMST_Pos (10UL) /*!< FMST (Bit 10) */
+#define UART4_RDR_FMST_Msk (0x400UL) /*!< FMST (Bitfield-Mask: 0x01) */
+#define UART4_RDR_PRST_Pos (9UL) /*!< PRST (Bit 9) */
+#define UART4_RDR_PRST_Msk (0x200UL) /*!< PRST (Bitfield-Mask: 0x01) */
+#define UART4_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define UART4_RDR_RD_Msk (0x1ffUL) /*!< RD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== TAR ========================================================== */
+#define UART4_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define UART4_TAR_TAR_Msk (0xffUL) /*!< TAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RAR ========================================================== */
+#define UART4_RAR_RAR_Pos (0UL) /*!< RAR (Bit 0) */
+#define UART4_RAR_RAR_Msk (0xffUL) /*!< RAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RTO ========================================================== */
+#define UART4_RTO_RTO_Pos (0UL) /*!< RTO (Bit 0) */
+#define UART4_RTO_RTO_Msk (0xffffUL) /*!< RTO (Bitfield-Mask: 0xffff) */
+/* ========================================================= INTEN ========================================================= */
+#define UART4_INTEN_ABRE_Pos (16UL) /*!< ABRE (Bit 16) */
+#define UART4_INTEN_ABRE_Msk (0x10000UL) /*!< ABRE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_AMIE_Pos (15UL) /*!< AMIE (Bit 15) */
+#define UART4_INTEN_AMIE_Msk (0x8000UL) /*!< AMIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_IDLE_Pos (14UL) /*!< IDLE (Bit 14) */
+#define UART4_INTEN_IDLE_Msk (0x4000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_TBIE_Pos (13UL) /*!< TBIE (Bit 13) */
+#define UART4_INTEN_TBIE_Msk (0x2000UL) /*!< TBIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_TDIE_Pos (12UL) /*!< TDIE (Bit 12) */
+#define UART4_INTEN_TDIE_Msk (0x1000UL) /*!< TDIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_RTIE_Pos (11UL) /*!< RTIE (Bit 11) */
+#define UART4_INTEN_RTIE_Msk (0x800UL) /*!< RTIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_BKIE_Pos (10UL) /*!< BKIE (Bit 10) */
+#define UART4_INTEN_BKIE_Msk (0x400UL) /*!< BKIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_FEIE_Pos (9UL) /*!< FEIE (Bit 9) */
+#define UART4_INTEN_FEIE_Msk (0x200UL) /*!< FEIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_PEIE_Pos (8UL) /*!< PEIE (Bit 8) */
+#define UART4_INTEN_PEIE_Msk (0x100UL) /*!< PEIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_NOIE_Pos (7UL) /*!< NOIE (Bit 7) */
+#define UART4_INTEN_NOIE_Msk (0x80UL) /*!< NOIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_IDIE_Pos (6UL) /*!< IDIE (Bit 6) */
+#define UART4_INTEN_IDIE_Msk (0x40UL) /*!< IDIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_TOIE_Pos (4UL) /*!< TOIE (Bit 4) */
+#define UART4_INTEN_TOIE_Msk (0x10UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_RUIE_Pos (3UL) /*!< RUIE (Bit 3) */
+#define UART4_INTEN_RUIE_Msk (0x8UL) /*!< RUIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_ROIE_Pos (2UL) /*!< ROIE (Bit 2) */
+#define UART4_INTEN_ROIE_Msk (0x4UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_TEIE_Pos (1UL) /*!< TEIE (Bit 1) */
+#define UART4_INTEN_TEIE_Msk (0x2UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_RFIE_Pos (0UL) /*!< RFIE (Bit 0) */
+#define UART4_INTEN_RFIE_Msk (0x1UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define UART4_INT_ABRF_Pos (16UL) /*!< ABRF (Bit 16) */
+#define UART4_INT_ABRF_Msk (0x10000UL) /*!< ABRF (Bitfield-Mask: 0x01) */
+#define UART4_INT_AMIF_Pos (15UL) /*!< AMIF (Bit 15) */
+#define UART4_INT_AMIF_Msk (0x8000UL) /*!< AMIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_IDLF_Pos (14UL) /*!< IDLF (Bit 14) */
+#define UART4_INT_IDLF_Msk (0x4000UL) /*!< IDLF (Bitfield-Mask: 0x01) */
+#define UART4_INT_TBIF_Pos (13UL) /*!< TBIF (Bit 13) */
+#define UART4_INT_TBIF_Msk (0x2000UL) /*!< TBIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_TDIF_Pos (12UL) /*!< TDIF (Bit 12) */
+#define UART4_INT_TDIF_Msk (0x1000UL) /*!< TDIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_RTOI_Pos (11UL) /*!< RTOI (Bit 11) */
+#define UART4_INT_RTOI_Msk (0x800UL) /*!< RTOI (Bitfield-Mask: 0x01) */
+#define UART4_INT_BKIF_Pos (10UL) /*!< BKIF (Bit 10) */
+#define UART4_INT_BKIF_Msk (0x400UL) /*!< BKIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_FEIF_Pos (9UL) /*!< FEIF (Bit 9) */
+#define UART4_INT_FEIF_Msk (0x200UL) /*!< FEIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_PEIF_Pos (8UL) /*!< PEIF (Bit 8) */
+#define UART4_INT_PEIF_Msk (0x100UL) /*!< PEIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_NOIF_Pos (7UL) /*!< NOIF (Bit 7) */
+#define UART4_INT_NOIF_Msk (0x80UL) /*!< NOIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_IDIF_Pos (6UL) /*!< IDIF (Bit 6) */
+#define UART4_INT_IDIF_Msk (0x40UL) /*!< IDIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_TOIF_Pos (4UL) /*!< TOIF (Bit 4) */
+#define UART4_INT_TOIF_Msk (0x10UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_RUIF_Pos (3UL) /*!< RUIF (Bit 3) */
+#define UART4_INT_RUIF_Msk (0x8UL) /*!< RUIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_ROIF_Pos (2UL) /*!< ROIF (Bit 2) */
+#define UART4_INT_ROIF_Msk (0x4UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define UART4_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define UART4_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define UART4_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define UART4_STATUS_RSE_Pos (16UL) /*!< RSE (Bit 16) */
+#define UART4_STATUS_RSE_Msk (0x10000UL) /*!< RSE (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_RFL_Pos (11UL) /*!< RFL (Bit 11) */
+#define UART4_STATUS_RFL_Msk (0xf800UL) /*!< RFL (Bitfield-Mask: 0x1f) */
+#define UART4_STATUS_RFF_Pos (10UL) /*!< RFF (Bit 10) */
+#define UART4_STATUS_RFF_Msk (0x400UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_RFE_Pos (9UL) /*!< RFE (Bit 9) */
+#define UART4_STATUS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_RBSY_Pos (8UL) /*!< RBSY (Bit 8) */
+#define UART4_STATUS_RBSY_Msk (0x100UL) /*!< RBSY (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_TFL_Pos (3UL) /*!< TFL (Bit 3) */
+#define UART4_STATUS_TFL_Msk (0xf8UL) /*!< TFL (Bitfield-Mask: 0x1f) */
+#define UART4_STATUS_TFF_Pos (2UL) /*!< TFF (Bit 2) */
+#define UART4_STATUS_TFF_Msk (0x4UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_TFE_Pos (1UL) /*!< TFE (Bit 1) */
+#define UART4_STATUS_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_TBSY_Pos (0UL) /*!< TBSY (Bit 0) */
+#define UART4_STATUS_TBSY_Msk (0x1UL) /*!< TBSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ SYSCTRL ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== SYSDCR ========================================================= */
+#define SYSCTRL_SYSDCR_TMR10DEN_Pos (11UL) /*!< TMR10DEN (Bit 11) */
+#define SYSCTRL_SYSDCR_TMR10DEN_Msk (0x800UL) /*!< TMR10DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR9DEN_Pos (10UL) /*!< TMR9DEN (Bit 10) */
+#define SYSCTRL_SYSDCR_TMR9DEN_Msk (0x400UL) /*!< TMR9DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR4DEN_Pos (9UL) /*!< TMR4DEN (Bit 9) */
+#define SYSCTRL_SYSDCR_TMR4DEN_Msk (0x200UL) /*!< TMR4DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR3DEN_Pos (8UL) /*!< TMR3DEN (Bit 8) */
+#define SYSCTRL_SYSDCR_TMR3DEN_Msk (0x100UL) /*!< TMR3DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR2DEN_Pos (7UL) /*!< TMR2DEN (Bit 7) */
+#define SYSCTRL_SYSDCR_TMR2DEN_Msk (0x80UL) /*!< TMR2DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR1DEN_Pos (6UL) /*!< TMR1DEN (Bit 6) */
+#define SYSCTRL_SYSDCR_TMR1DEN_Msk (0x40UL) /*!< TMR1DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR0DEN_Pos (5UL) /*!< TMR0DEN (Bit 5) */
+#define SYSCTRL_SYSDCR_TMR0DEN_Msk (0x20UL) /*!< TMR0DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR8DEN_Pos (4UL) /*!< TMR8DEN (Bit 4) */
+#define SYSCTRL_SYSDCR_TMR8DEN_Msk (0x10UL) /*!< TMR8DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR7DEN_Pos (3UL) /*!< TMR7DEN (Bit 3) */
+#define SYSCTRL_SYSDCR_TMR7DEN_Msk (0x8UL) /*!< TMR7DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_PWMDEN_Pos (2UL) /*!< PWMDEN (Bit 2) */
+#define SYSCTRL_SYSDCR_PWMDEN_Msk (0x4UL) /*!< PWMDEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_WWDGDEN_Pos (1UL) /*!< WWDGDEN (Bit 1) */
+#define SYSCTRL_SYSDCR_WWDGDEN_Msk (0x2UL) /*!< WWDGDEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_IWDGDEN_Pos (0UL) /*!< IWDGDEN (Bit 0) */
+#define SYSCTRL_SYSDCR_IWDGDEN_Msk (0x1UL) /*!< IWDGDEN (Bitfield-Mask: 0x01) */
+/* ========================================================= SYSCR ========================================================= */
+#define SYSCTRL_SYSCR_FBM_Pos (8UL) /*!< FBM (Bit 8) */
+#define SYSCTRL_SYSCR_FBM_Msk (0x100UL) /*!< FBM (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_QEI2FE_Pos (6UL) /*!< QEI2FE (Bit 6) */
+#define SYSCTRL_SYSCR_QEI2FE_Msk (0x40UL) /*!< QEI2FE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_QEI1FE_Pos (5UL) /*!< QEI1FE (Bit 5) */
+#define SYSCTRL_SYSCR_QEI1FE_Msk (0x20UL) /*!< QEI1FE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_QEI0FE_Pos (4UL) /*!< QEI0FE (Bit 4) */
+#define SYSCTRL_SYSCR_QEI0FE_Msk (0x10UL) /*!< QEI0FE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_PLLFE_Pos (3UL) /*!< PLLFE (Bit 3) */
+#define SYSCTRL_SYSCR_PLLFE_Msk (0x8UL) /*!< PLLFE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_OSCFE_Pos (2UL) /*!< OSCFE (Bit 2) */
+#define SYSCTRL_SYSCR_OSCFE_Msk (0x4UL) /*!< OSCFE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_LKFE_Pos (1UL) /*!< LKFE (Bit 1) */
+#define SYSCTRL_SYSCR_LKFE_Msk (0x2UL) /*!< LKFE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_ECCFE_Pos (0UL) /*!< ECCFE (Bit 0) */
+#define SYSCTRL_SYSCR_ECCFE_Msk (0x1UL) /*!< ECCFE (Bitfield-Mask: 0x01) */
+/* ======================================================== DMARCR ========================================================= */
+#define SYSCTRL_DMARCR_DRCR_Pos (19UL) /*!< DRCR (Bit 19) */
+#define SYSCTRL_DMARCR_DRCR_Msk (0xfff80000UL) /*!< DRCR (Bitfield-Mask: 0x1fff) */
+/* ======================================================== SYSATR ========================================================= */
+#define SYSCTRL_SYSATR_ABFSRC_Pos (10UL) /*!< ABFSRC (Bit 10) */
+#define SYSCTRL_SYSATR_ABFSRC_Msk (0x7c00UL) /*!< ABFSRC (Bitfield-Mask: 0x1f) */
+#define SYSCTRL_SYSATR_ABFBYP_Pos (9UL) /*!< ABFBYP (Bit 9) */
+#define SYSCTRL_SYSATR_ABFBYP_Msk (0x200UL) /*!< ABFBYP (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSATR_ABFEN_Pos (8UL) /*!< ABFEN (Bit 8) */
+#define SYSCTRL_SYSATR_ABFEN_Msk (0x100UL) /*!< ABFEN (Bitfield-Mask: 0x01) */
+/* ========================================================= PWRCR ========================================================= */
+#define SYSCTRL_PWRCR_AVDDDRD_Pos (8UL) /*!< AVDDDRD (Bit 8) */
+#define SYSCTRL_PWRCR_AVDDDRD_Msk (0x100UL) /*!< AVDDDRD (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PWRCR_VDDSET_Pos (4UL) /*!< VDDSET (Bit 4) */
+#define SYSCTRL_PWRCR_VDDSET_Msk (0xf0UL) /*!< VDDSET (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_PWRCR_AVDDSET_Pos (2UL) /*!< AVDDSET (Bit 2) */
+#define SYSCTRL_PWRCR_AVDDSET_Msk (0xcUL) /*!< AVDDSET (Bitfield-Mask: 0x03) */
+#define SYSCTRL_PWRCR_AVDDEN_Pos (1UL) /*!< AVDDEN (Bit 1) */
+#define SYSCTRL_PWRCR_AVDDEN_Msk (0x2UL) /*!< AVDDEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PWRCR_TSE_Pos (0UL) /*!< TSE (Bit 0) */
+#define SYSCTRL_PWRCR_TSE_Msk (0x1UL) /*!< TSE (Bitfield-Mask: 0x01) */
+/* ========================================================= PLCR ========================================================== */
+#define SYSCTRL_PLCR_VDDOCL_Pos (12UL) /*!< VDDOCL (Bit 12) */
+#define SYSCTRL_PLCR_VDDOCL_Msk (0x3000UL) /*!< VDDOCL (Bitfield-Mask: 0x03) */
+#define SYSCTRL_PLCR_AVCCLVL_Pos (10UL) /*!< AVCCLVL (Bit 10) */
+#define SYSCTRL_PLCR_AVCCLVL_Msk (0xc00UL) /*!< AVCCLVL (Bitfield-Mask: 0x03) */
+#define SYSCTRL_PLCR_VDDLVS_Pos (4UL) /*!< VDDLVS (Bit 4) */
+#define SYSCTRL_PLCR_VDDLVS_Msk (0x70UL) /*!< VDDLVS (Bitfield-Mask: 0x07) */
+#define SYSCTRL_PLCR_VDDOCE_Pos (3UL) /*!< VDDOCE (Bit 3) */
+#define SYSCTRL_PLCR_VDDOCE_Msk (0x8UL) /*!< VDDOCE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PLCR_AVCCLVE_Pos (2UL) /*!< AVCCLVE (Bit 2) */
+#define SYSCTRL_PLCR_AVCCLVE_Msk (0x4UL) /*!< AVCCLVE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PLCR_VCCLVE_Pos (1UL) /*!< VCCLVE (Bit 1) */
+#define SYSCTRL_PLCR_VCCLVE_Msk (0x2UL) /*!< VCCLVE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PLCR_VDDLVE_Pos (0UL) /*!< VDDLVE (Bit 0) */
+#define SYSCTRL_PLCR_VDDLVE_Msk (0x1UL) /*!< VDDLVE (Bitfield-Mask: 0x01) */
+/* ========================================================= PECR ========================================================== */
+#define SYSCTRL_PECR_VDDOCBE_Pos (11UL) /*!< VDDOCBE (Bit 11) */
+#define SYSCTRL_PECR_VDDOCBE_Msk (0x800UL) /*!< VDDOCBE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_AVCCLVBE_Pos (10UL) /*!< AVCCLVBE (Bit 10) */
+#define SYSCTRL_PECR_AVCCLVBE_Msk (0x400UL) /*!< AVCCLVBE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VCCLVBE_Pos (9UL) /*!< VCCLVBE (Bit 9) */
+#define SYSCTRL_PECR_VCCLVBE_Msk (0x200UL) /*!< VCCLVBE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VDDLVBE_Pos (8UL) /*!< VDDLVBE (Bit 8) */
+#define SYSCTRL_PECR_VDDLVBE_Msk (0x100UL) /*!< VDDLVBE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VDDOCRE_Pos (7UL) /*!< VDDOCRE (Bit 7) */
+#define SYSCTRL_PECR_VDDOCRE_Msk (0x80UL) /*!< VDDOCRE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_AVCCLVRE_Pos (6UL) /*!< AVCCLVRE (Bit 6) */
+#define SYSCTRL_PECR_AVCCLVRE_Msk (0x40UL) /*!< AVCCLVRE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VCCLVRE_Pos (5UL) /*!< VCCLVRE (Bit 5) */
+#define SYSCTRL_PECR_VCCLVRE_Msk (0x20UL) /*!< VCCLVRE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VDDLVRE_Pos (4UL) /*!< VDDLVRE (Bit 4) */
+#define SYSCTRL_PECR_VDDLVRE_Msk (0x10UL) /*!< VDDLVRE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VDDOCIE_Pos (3UL) /*!< VDDOCIE (Bit 3) */
+#define SYSCTRL_PECR_VDDOCIE_Msk (0x8UL) /*!< VDDOCIE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_AVCCLVIE_Pos (2UL) /*!< AVCCLVIE (Bit 2) */
+#define SYSCTRL_PECR_AVCCLVIE_Msk (0x4UL) /*!< AVCCLVIE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VCCLVIE_Pos (1UL) /*!< VCCLVIE (Bit 1) */
+#define SYSCTRL_PECR_VCCLVIE_Msk (0x2UL) /*!< VCCLVIE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VDDLVIE_Pos (0UL) /*!< VDDLVIE (Bit 0) */
+#define SYSCTRL_PECR_VDDLVIE_Msk (0x1UL) /*!< VDDLVIE (Bitfield-Mask: 0x01) */
+/* ========================================================== PSR ========================================================== */
+#define SYSCTRL_PSR_VDDOCS_Pos (3UL) /*!< VDDOCS (Bit 3) */
+#define SYSCTRL_PSR_VDDOCS_Msk (0x8UL) /*!< VDDOCS (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PSR_AVCCLVS_Pos (2UL) /*!< AVCCLVS (Bit 2) */
+#define SYSCTRL_PSR_AVCCLVS_Msk (0x4UL) /*!< AVCCLVS (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PSR_VCCLVS_Pos (1UL) /*!< VCCLVS (Bit 1) */
+#define SYSCTRL_PSR_VCCLVS_Msk (0x2UL) /*!< VCCLVS (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PSR_VDDLVS_Pos (0UL) /*!< VDDLVS (Bit 0) */
+#define SYSCTRL_PSR_VDDLVS_Msk (0x1UL) /*!< VDDLVS (Bitfield-Mask: 0x01) */
+/* ========================================================= PWRDR ========================================================= */
+#define SYSCTRL_PWRDR_VDDOCF_Pos (12UL) /*!< VDDOCF (Bit 12) */
+#define SYSCTRL_PWRDR_VDDOCF_Msk (0xf000UL) /*!< VDDOCF (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_PWRDR_AVCCLVF_Pos (8UL) /*!< AVCCLVF (Bit 8) */
+#define SYSCTRL_PWRDR_AVCCLVF_Msk (0xf00UL) /*!< AVCCLVF (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_PWRDR_VCCLVF_Pos (4UL) /*!< VCCLVF (Bit 4) */
+#define SYSCTRL_PWRDR_VCCLVF_Msk (0xf0UL) /*!< VCCLVF (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_PWRDR_VDDLVF_Pos (0UL) /*!< VDDLVF (Bit 0) */
+#define SYSCTRL_PWRDR_VDDLVF_Msk (0xfUL) /*!< VDDLVF (Bitfield-Mask: 0x0f) */
+/* ========================================================= CIDR ========================================================== */
+#define SYSCTRL_CIDR_DCN_Pos (16UL) /*!< DCN (Bit 16) */
+#define SYSCTRL_CIDR_DCN_Msk (0xff0000UL) /*!< DCN (Bitfield-Mask: 0xff) */
+#define SYSCTRL_CIDR_CID_Pos (0UL) /*!< CID (Bit 0) */
+#define SYSCTRL_CIDR_CID_Msk (0xffffUL) /*!< CID (Bitfield-Mask: 0xffff) */
+/* ========================================================= KEYR ========================================================== */
+#define SYSCTRL_KEYR_KST1_Pos (17UL) /*!< KST1 (Bit 17) */
+#define SYSCTRL_KEYR_KST1_Msk (0x20000UL) /*!< KST1 (Bitfield-Mask: 0x01) */
+#define SYSCTRL_KEYR_KST0_Pos (16UL) /*!< KST0 (Bit 16) */
+#define SYSCTRL_KEYR_KST0_Msk (0x10000UL) /*!< KST0 (Bitfield-Mask: 0x01) */
+#define SYSCTRL_KEYR_KEY_Pos (0UL) /*!< KEY (Bit 0) */
+#define SYSCTRL_KEYR_KEY_Msk (0xffffUL) /*!< KEY (Bitfield-Mask: 0xffff) */
+/* ========================================================= UID0 ========================================================== */
+#define SYSCTRL_UID0_UID0_Pos (0UL) /*!< UID0 (Bit 0) */
+#define SYSCTRL_UID0_UID0_Msk (0xffffffffUL) /*!< UID0 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UID1 ========================================================== */
+#define SYSCTRL_UID1_UID1_Pos (0UL) /*!< UID1 (Bit 0) */
+#define SYSCTRL_UID1_UID1_Msk (0xffffffffUL) /*!< UID1 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UID2 ========================================================== */
+#define SYSCTRL_UID2_UID2_Pos (0UL) /*!< UID2 (Bit 0) */
+#define SYSCTRL_UID2_UID2_Msk (0xffffffffUL) /*!< UID2 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UID3 ========================================================== */
+#define SYSCTRL_UID3_UID3_Pos (0UL) /*!< UID3 (Bit 0) */
+#define SYSCTRL_UID3_UID3_Msk (0xffffffffUL) /*!< UID3 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ATCR ========================================================== */
+#define SYSCTRL_ATCR_VBFRDY_Pos (31UL) /*!< VBFRDY (Bit 31) */
+#define SYSCTRL_ATCR_VBFRDY_Msk (0x80000000UL) /*!< VBFRDY (Bitfield-Mask: 0x01) */
+#define SYSCTRL_ATCR_BGV_Pos (20UL) /*!< BGV (Bit 20) */
+#define SYSCTRL_ATCR_BGV_Msk (0x7ff00000UL) /*!< BGV (Bitfield-Mask: 0x7ff) */
+#define SYSCTRL_ATCR_VBFCL_Pos (19UL) /*!< VBFCL (Bit 19) */
+#define SYSCTRL_ATCR_VBFCL_Msk (0x80000UL) /*!< VBFCL (Bitfield-Mask: 0x01) */
+#define SYSCTRL_ATCR_VBFTRIM_Pos (14UL) /*!< VBFTRIM (Bit 14) */
+#define SYSCTRL_ATCR_VBFTRIM_Msk (0x7c000UL) /*!< VBFTRIM (Bitfield-Mask: 0x1f) */
+#define SYSCTRL_ATCR_VBFSEL_Pos (13UL) /*!< VBFSEL (Bit 13) */
+#define SYSCTRL_ATCR_VBFSEL_Msk (0x2000UL) /*!< VBFSEL (Bitfield-Mask: 0x01) */
+#define SYSCTRL_ATCR_VBFEN_Pos (12UL) /*!< VBFEN (Bit 12) */
+#define SYSCTRL_ATCR_VBFEN_Msk (0x1000UL) /*!< VBFEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_ATCR_REFITRIM_Pos (6UL) /*!< REFITRIM (Bit 6) */
+#define SYSCTRL_ATCR_REFITRIM_Msk (0xfc0UL) /*!< REFITRIM (Bitfield-Mask: 0x3f) */
+#define SYSCTRL_ATCR_REFVTRIM_Pos (1UL) /*!< REFVTRIM (Bit 1) */
+#define SYSCTRL_ATCR_REFVTRIM_Msk (0x3eUL) /*!< REFVTRIM (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCR0 ========================================================== */
+#define SYSCTRL_FCR0_ADC3TRIM_Pos (24UL) /*!< ADC3TRIM (Bit 24) */
+#define SYSCTRL_FCR0_ADC3TRIM_Msk (0x1f000000UL) /*!< ADC3TRIM (Bitfield-Mask: 0x1f) */
+#define SYSCTRL_FCR0_ADC2TRIM_Pos (16UL) /*!< ADC2TRIM (Bit 16) */
+#define SYSCTRL_FCR0_ADC2TRIM_Msk (0x1f0000UL) /*!< ADC2TRIM (Bitfield-Mask: 0x1f) */
+#define SYSCTRL_FCR0_ADC1TRIM_Pos (8UL) /*!< ADC1TRIM (Bit 8) */
+#define SYSCTRL_FCR0_ADC1TRIM_Msk (0x1f00UL) /*!< ADC1TRIM (Bitfield-Mask: 0x1f) */
+#define SYSCTRL_FCR0_ADC0TRIM_Pos (0UL) /*!< ADC0TRIM (Bit 0) */
+#define SYSCTRL_FCR0_ADC0TRIM_Msk (0x1fUL) /*!< ADC0TRIM (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCR1 ========================================================== */
+#define SYSCTRL_FCR1_DAC2TRIM_Pos (28UL) /*!< DAC2TRIM (Bit 28) */
+#define SYSCTRL_FCR1_DAC2TRIM_Msk (0xf0000000UL) /*!< DAC2TRIM (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_FCR1_DAC1TRIM_Pos (24UL) /*!< DAC1TRIM (Bit 24) */
+#define SYSCTRL_FCR1_DAC1TRIM_Msk (0xf000000UL) /*!< DAC1TRIM (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_FCR1_DAC0TRIM_Pos (20UL) /*!< DAC0TRIM (Bit 20) */
+#define SYSCTRL_FCR1_DAC0TRIM_Msk (0xf00000UL) /*!< DAC0TRIM (Bitfield-Mask: 0x0f) */
+/* ========================================================= FCR2 ========================================================== */
+#define SYSCTRL_FCR2_RC8M_Pos (8UL) /*!< RC8M (Bit 8) */
+#define SYSCTRL_FCR2_RC8M_Msk (0xffffff00UL) /*!< RC8M (Bitfield-Mask: 0xffffff) */
+#define SYSCTRL_FCR2_ADCPVEN_Pos (4UL) /*!< ADCPVEN (Bit 4) */
+#define SYSCTRL_FCR2_ADCPVEN_Msk (0x10UL) /*!< ADCPVEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_FCR2_PLL0BANDx_Pos (2UL) /*!< PLL0BANDx (Bit 2) */
+#define SYSCTRL_FCR2_PLL0BANDx_Msk (0xcUL) /*!< PLL0BANDx (Bitfield-Mask: 0x03) */
+#define SYSCTRL_FCR2_PLL0BANDy_Pos (0UL) /*!< PLL0BANDy (Bit 0) */
+#define SYSCTRL_FCR2_PLL0BANDy_Msk (0x3UL) /*!< PLL0BANDy (Bitfield-Mask: 0x03) */
+/* ========================================================= FCR3 ========================================================== */
+#define SYSCTRL_FCR3_PLL0INTy_Pos (16UL) /*!< PLL0INTy (Bit 16) */
+#define SYSCTRL_FCR3_PLL0INTy_Msk (0x3fff0000UL) /*!< PLL0INTy (Bitfield-Mask: 0x3fff) */
+#define SYSCTRL_FCR3_PLL0FRACy_Pos (0UL) /*!< PLL0FRACy (Bit 0) */
+#define SYSCTRL_FCR3_PLL0FRACy_Msk (0xffffUL) /*!< PLL0FRACy (Bitfield-Mask: 0xffff) */
+/* ========================================================= FCR4 ========================================================== */
+#define SYSCTRL_FCR4_PLL0INTx_Pos (16UL) /*!< PLL0INTx (Bit 16) */
+#define SYSCTRL_FCR4_PLL0INTx_Msk (0x3fff0000UL) /*!< PLL0INTx (Bitfield-Mask: 0x3fff) */
+#define SYSCTRL_FCR4_PLL0FRACx_Pos (0UL) /*!< PLL0FRACx (Bit 0) */
+#define SYSCTRL_FCR4_PLL0FRACx_Msk (0xffffUL) /*!< PLL0FRACx (Bitfield-Mask: 0xffff) */
+/* ========================================================= FCR5 ========================================================== */
+#define SYSCTRL_FCR5_RC32K_Pos (16UL) /*!< RC32K (Bit 16) */
+#define SYSCTRL_FCR5_RC32K_Msk (0xffff0000UL) /*!< RC32K (Bitfield-Mask: 0xffff) */
+#define SYSCTRL_FCR5_Tsensor_Pos (0UL) /*!< Tsensor (Bit 0) */
+#define SYSCTRL_FCR5_Tsensor_Msk (0xffffUL) /*!< Tsensor (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ SPI0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define SPI0_ENABLE_CSI_Pos (15UL) /*!< CSI (Bit 15) */
+#define SPI0_ENABLE_CSI_Msk (0x8000UL) /*!< CSI (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_CSIS_Pos (14UL) /*!< CSIS (Bit 14) */
+#define SPI0_ENABLE_CSIS_Msk (0x4000UL) /*!< CSIS (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_CSO_Pos (13UL) /*!< CSO (Bit 13) */
+#define SPI0_ENABLE_CSO_Msk (0x2000UL) /*!< CSO (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_CSOS_Pos (12UL) /*!< CSOS (Bit 12) */
+#define SPI0_ENABLE_CSOS_Msk (0x1000UL) /*!< CSOS (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_DTE_Pos (9UL) /*!< DTE (Bit 9) */
+#define SPI0_ENABLE_DTE_Msk (0x200UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_DRE_Pos (8UL) /*!< DRE (Bit 8) */
+#define SPI0_ENABLE_DRE_Msk (0x100UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_LOOP_Pos (7UL) /*!< LOOP (Bit 7) */
+#define SPI0_ENABLE_LOOP_Msk (0x80UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_SWAP_Pos (6UL) /*!< SWAP (Bit 6) */
+#define SPI0_ENABLE_SWAP_Msk (0x40UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_CSPOL_Pos (5UL) /*!< CSPOL (Bit 5) */
+#define SPI0_ENABLE_CSPOL_Msk (0x20UL) /*!< CSPOL (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_CSSEL_Pos (4UL) /*!< CSSEL (Bit 4) */
+#define SPI0_ENABLE_CSSEL_Msk (0x10UL) /*!< CSSEL (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_TWE_Pos (3UL) /*!< TWE (Bit 3) */
+#define SPI0_ENABLE_TWE_Msk (0x8UL) /*!< TWE (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_TFR_Pos (2UL) /*!< TFR (Bit 2) */
+#define SPI0_ENABLE_TFR_Msk (0x4UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_RFR_Pos (1UL) /*!< RFR (Bit 1) */
+#define SPI0_ENABLE_RFR_Msk (0x2UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_SPIEN_Pos (0UL) /*!< SPIEN (Bit 0) */
+#define SPI0_ENABLE_SPIEN_Msk (0x1UL) /*!< SPIEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define SPI0_CTRL_RXDLY_Pos (16UL) /*!< RXDLY (Bit 16) */
+#define SPI0_CTRL_RXDLY_Msk (0x70000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define SPI0_CTRL_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define SPI0_CTRL_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define SPI0_CTRL_UDRCFG_Pos (7UL) /*!< UDRCFG (Bit 7) */
+#define SPI0_CTRL_UDRCFG_Msk (0x80UL) /*!< UDRCFG (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_LSB_Pos (6UL) /*!< LSB (Bit 6) */
+#define SPI0_CTRL_LSB_Msk (0x40UL) /*!< LSB (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_RXEN_Pos (5UL) /*!< RXEN (Bit 5) */
+#define SPI0_CTRL_RXEN_Msk (0x20UL) /*!< RXEN (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_TXEN_Pos (4UL) /*!< TXEN (Bit 4) */
+#define SPI0_CTRL_TXEN_Msk (0x10UL) /*!< TXEN (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_SHZOE_Pos (3UL) /*!< SHZOE (Bit 3) */
+#define SPI0_CTRL_SHZOE_Msk (0x8UL) /*!< SHZOE (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_CPOL_Pos (2UL) /*!< CPOL (Bit 2) */
+#define SPI0_CTRL_CPOL_Msk (0x4UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_CPHA_Pos (1UL) /*!< CPHA (Bit 1) */
+#define SPI0_CTRL_CPHA_Msk (0x2UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_MSTEN_Pos (0UL) /*!< MSTEN (Bit 0) */
+#define SPI0_CTRL_MSTEN_Msk (0x1UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+/* ========================================================= BAUD ========================================================== */
+#define SPI0_BAUD_BAUD_Pos (1UL) /*!< BAUD (Bit 1) */
+#define SPI0_BAUD_BAUD_Msk (0xffeUL) /*!< BAUD (Bitfield-Mask: 0x7ff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define SPI0_FIFOCTRL_RXFTLR_Pos (4UL) /*!< RXFTLR (Bit 4) */
+#define SPI0_FIFOCTRL_RXFTLR_Msk (0xf0UL) /*!< RXFTLR (Bitfield-Mask: 0x0f) */
+#define SPI0_FIFOCTRL_TXFTLR_Pos (0UL) /*!< TXFTLR (Bit 0) */
+#define SPI0_FIFOCTRL_TXFTLR_Msk (0xfUL) /*!< TXFTLR (Bitfield-Mask: 0x0f) */
+/* ========================================================== CNT ========================================================== */
+#define SPI0_CNT_DCNT_Pos (0UL) /*!< DCNT (Bit 0) */
+#define SPI0_CNT_DCNT_Msk (0xffffUL) /*!< DCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= RCNT ========================================================== */
+#define SPI0_RCNT_RCNT_Pos (0UL) /*!< RCNT (Bit 0) */
+#define SPI0_RCNT_RCNT_Msk (0xffffUL) /*!< RCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= START ========================================================= */
+#define SPI0_START_STOP_Pos (1UL) /*!< STOP (Bit 1) */
+#define SPI0_START_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */
+#define SPI0_START_START_Pos (0UL) /*!< START (Bit 0) */
+#define SPI0_START_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ======================================================== TIMING ========================================================= */
+#define SPI0_TIMING_MCSI_Pos (16UL) /*!< MCSI (Bit 16) */
+#define SPI0_TIMING_MCSI_Msk (0x1f0000UL) /*!< MCSI (Bitfield-Mask: 0x1f) */
+#define SPI0_TIMING_MIDI_Pos (0UL) /*!< MIDI (Bit 0) */
+#define SPI0_TIMING_MIDI_Msk (0x1fUL) /*!< MIDI (Bitfield-Mask: 0x1f) */
+/* ========================================================= INTEN ========================================================= */
+#define SPI0_INTEN_RXCIE_Pos (11UL) /*!< RXCIE (Bit 11) */
+#define SPI0_INTEN_RXCIE_Msk (0x800UL) /*!< RXCIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_TXCIE_Pos (10UL) /*!< TXCIE (Bit 10) */
+#define SPI0_INTEN_TXCIE_Msk (0x400UL) /*!< TXCIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_RXDEIE_Pos (9UL) /*!< RXDEIE (Bit 9) */
+#define SPI0_INTEN_RXDEIE_Msk (0x200UL) /*!< RXDEIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_TXDEIE_Pos (8UL) /*!< TXDEIE (Bit 8) */
+#define SPI0_INTEN_TXDEIE_Msk (0x100UL) /*!< TXDEIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_MDFIE_Pos (7UL) /*!< MDFIE (Bit 7) */
+#define SPI0_INTEN_MDFIE_Msk (0x80UL) /*!< MDFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_OPFIE_Pos (6UL) /*!< OPFIE (Bit 6) */
+#define SPI0_INTEN_OPFIE_Msk (0x40UL) /*!< OPFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_TXUFIE_Pos (5UL) /*!< TXUFIE (Bit 5) */
+#define SPI0_INTEN_TXUFIE_Msk (0x20UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_TXOFIE_Pos (4UL) /*!< TXOFIE (Bit 4) */
+#define SPI0_INTEN_TXOFIE_Msk (0x10UL) /*!< TXOFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_RXUFIE_Pos (3UL) /*!< RXUFIE (Bit 3) */
+#define SPI0_INTEN_RXUFIE_Msk (0x8UL) /*!< RXUFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_RXOFIE_Pos (2UL) /*!< RXOFIE (Bit 2) */
+#define SPI0_INTEN_RXOFIE_Msk (0x4UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_TXEIE_Pos (1UL) /*!< TXEIE (Bit 1) */
+#define SPI0_INTEN_TXEIE_Msk (0x2UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_RXFIE_Pos (0UL) /*!< RXFIE (Bit 0) */
+#define SPI0_INTEN_RXFIE_Msk (0x1UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define SPI0_INT_RXCI_Pos (11UL) /*!< RXCI (Bit 11) */
+#define SPI0_INT_RXCI_Msk (0x800UL) /*!< RXCI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_TXCI_Pos (10UL) /*!< TXCI (Bit 10) */
+#define SPI0_INT_TXCI_Msk (0x400UL) /*!< TXCI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_RXDEI_Pos (9UL) /*!< RXDEI (Bit 9) */
+#define SPI0_INT_RXDEI_Msk (0x200UL) /*!< RXDEI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_TXDEI_Pos (8UL) /*!< TXDEI (Bit 8) */
+#define SPI0_INT_TXDEI_Msk (0x100UL) /*!< TXDEI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_MDFI_Pos (7UL) /*!< MDFI (Bit 7) */
+#define SPI0_INT_MDFI_Msk (0x80UL) /*!< MDFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_OPFI_Pos (6UL) /*!< OPFI (Bit 6) */
+#define SPI0_INT_OPFI_Msk (0x40UL) /*!< OPFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_TXUFI_Pos (5UL) /*!< TXUFI (Bit 5) */
+#define SPI0_INT_TXUFI_Msk (0x20UL) /*!< TXUFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_TXOFI_Pos (4UL) /*!< TXOFI (Bit 4) */
+#define SPI0_INT_TXOFI_Msk (0x10UL) /*!< TXOFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_RXUFI_Pos (3UL) /*!< RXUFI (Bit 3) */
+#define SPI0_INT_RXUFI_Msk (0x8UL) /*!< RXUFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_RXOFI_Pos (2UL) /*!< RXOFI (Bit 2) */
+#define SPI0_INT_RXOFI_Msk (0x4UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define SPI0_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define SPI0_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define SPI0_STATUS_RFF_Pos (30UL) /*!< RFF (Bit 30) */
+#define SPI0_STATUS_RFF_Msk (0x40000000UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define SPI0_STATUS_RFE_Pos (29UL) /*!< RFE (Bit 29) */
+#define SPI0_STATUS_RFE_Msk (0x20000000UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define SPI0_STATUS_RXFLR_Pos (24UL) /*!< RXFLR (Bit 24) */
+#define SPI0_STATUS_RXFLR_Msk (0x1f000000UL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
+#define SPI0_STATUS_TFF_Pos (22UL) /*!< TFF (Bit 22) */
+#define SPI0_STATUS_TFF_Msk (0x400000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define SPI0_STATUS_TFE_Pos (21UL) /*!< TFE (Bit 21) */
+#define SPI0_STATUS_TFE_Msk (0x200000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define SPI0_STATUS_TXFLR_Pos (16UL) /*!< TXFLR (Bit 16) */
+#define SPI0_STATUS_TXFLR_Msk (0x1f0000UL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
+#define SPI0_STATUS_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */
+#define SPI0_STATUS_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+/* ========================================================== TDR ========================================================== */
+#define SPI0_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define SPI0_TDR_TD_Msk (0xffffUL) /*!< TD (Bitfield-Mask: 0xffff) */
+/* ========================================================== RDR ========================================================== */
+#define SPI0_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define SPI0_RDR_RD_Msk (0xffffUL) /*!< RD (Bitfield-Mask: 0xffff) */
+/* ========================================================= UDRDR ========================================================= */
+#define SPI0_UDRDR_UDRDR_Pos (0UL) /*!< UDRDR (Bit 0) */
+#define SPI0_UDRDR_UDRDR_Msk (0xffffUL) /*!< UDRDR (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ SPI1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define SPI1_ENABLE_CSI_Pos (15UL) /*!< CSI (Bit 15) */
+#define SPI1_ENABLE_CSI_Msk (0x8000UL) /*!< CSI (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_CSIS_Pos (14UL) /*!< CSIS (Bit 14) */
+#define SPI1_ENABLE_CSIS_Msk (0x4000UL) /*!< CSIS (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_CSO_Pos (13UL) /*!< CSO (Bit 13) */
+#define SPI1_ENABLE_CSO_Msk (0x2000UL) /*!< CSO (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_CSOS_Pos (12UL) /*!< CSOS (Bit 12) */
+#define SPI1_ENABLE_CSOS_Msk (0x1000UL) /*!< CSOS (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_DTE_Pos (9UL) /*!< DTE (Bit 9) */
+#define SPI1_ENABLE_DTE_Msk (0x200UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_DRE_Pos (8UL) /*!< DRE (Bit 8) */
+#define SPI1_ENABLE_DRE_Msk (0x100UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_LOOP_Pos (7UL) /*!< LOOP (Bit 7) */
+#define SPI1_ENABLE_LOOP_Msk (0x80UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_SWAP_Pos (6UL) /*!< SWAP (Bit 6) */
+#define SPI1_ENABLE_SWAP_Msk (0x40UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_CSPOL_Pos (5UL) /*!< CSPOL (Bit 5) */
+#define SPI1_ENABLE_CSPOL_Msk (0x20UL) /*!< CSPOL (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_CSSEL_Pos (4UL) /*!< CSSEL (Bit 4) */
+#define SPI1_ENABLE_CSSEL_Msk (0x10UL) /*!< CSSEL (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_TWE_Pos (3UL) /*!< TWE (Bit 3) */
+#define SPI1_ENABLE_TWE_Msk (0x8UL) /*!< TWE (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_TFR_Pos (2UL) /*!< TFR (Bit 2) */
+#define SPI1_ENABLE_TFR_Msk (0x4UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_RFR_Pos (1UL) /*!< RFR (Bit 1) */
+#define SPI1_ENABLE_RFR_Msk (0x2UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_SPIEN_Pos (0UL) /*!< SPIEN (Bit 0) */
+#define SPI1_ENABLE_SPIEN_Msk (0x1UL) /*!< SPIEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define SPI1_CTRL_RXDLY_Pos (16UL) /*!< RXDLY (Bit 16) */
+#define SPI1_CTRL_RXDLY_Msk (0x70000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define SPI1_CTRL_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define SPI1_CTRL_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define SPI1_CTRL_UDRCFG_Pos (7UL) /*!< UDRCFG (Bit 7) */
+#define SPI1_CTRL_UDRCFG_Msk (0x80UL) /*!< UDRCFG (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_LSB_Pos (6UL) /*!< LSB (Bit 6) */
+#define SPI1_CTRL_LSB_Msk (0x40UL) /*!< LSB (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_RXEN_Pos (5UL) /*!< RXEN (Bit 5) */
+#define SPI1_CTRL_RXEN_Msk (0x20UL) /*!< RXEN (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_TXEN_Pos (4UL) /*!< TXEN (Bit 4) */
+#define SPI1_CTRL_TXEN_Msk (0x10UL) /*!< TXEN (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_SHZOE_Pos (3UL) /*!< SHZOE (Bit 3) */
+#define SPI1_CTRL_SHZOE_Msk (0x8UL) /*!< SHZOE (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_CPOL_Pos (2UL) /*!< CPOL (Bit 2) */
+#define SPI1_CTRL_CPOL_Msk (0x4UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_CPHA_Pos (1UL) /*!< CPHA (Bit 1) */
+#define SPI1_CTRL_CPHA_Msk (0x2UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_MSTEN_Pos (0UL) /*!< MSTEN (Bit 0) */
+#define SPI1_CTRL_MSTEN_Msk (0x1UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+/* ========================================================= BAUD ========================================================== */
+#define SPI1_BAUD_BAUD_Pos (1UL) /*!< BAUD (Bit 1) */
+#define SPI1_BAUD_BAUD_Msk (0xffeUL) /*!< BAUD (Bitfield-Mask: 0x7ff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define SPI1_FIFOCTRL_RXFTLR_Pos (4UL) /*!< RXFTLR (Bit 4) */
+#define SPI1_FIFOCTRL_RXFTLR_Msk (0xf0UL) /*!< RXFTLR (Bitfield-Mask: 0x0f) */
+#define SPI1_FIFOCTRL_TXFTLR_Pos (0UL) /*!< TXFTLR (Bit 0) */
+#define SPI1_FIFOCTRL_TXFTLR_Msk (0xfUL) /*!< TXFTLR (Bitfield-Mask: 0x0f) */
+/* ========================================================== CNT ========================================================== */
+#define SPI1_CNT_DCNT_Pos (0UL) /*!< DCNT (Bit 0) */
+#define SPI1_CNT_DCNT_Msk (0xffffUL) /*!< DCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= RCNT ========================================================== */
+#define SPI1_RCNT_RCNT_Pos (0UL) /*!< RCNT (Bit 0) */
+#define SPI1_RCNT_RCNT_Msk (0xffffUL) /*!< RCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= START ========================================================= */
+#define SPI1_START_STOP_Pos (1UL) /*!< STOP (Bit 1) */
+#define SPI1_START_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */
+#define SPI1_START_START_Pos (0UL) /*!< START (Bit 0) */
+#define SPI1_START_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ======================================================== TIMING ========================================================= */
+#define SPI1_TIMING_MCSI_Pos (16UL) /*!< MCSI (Bit 16) */
+#define SPI1_TIMING_MCSI_Msk (0x1f0000UL) /*!< MCSI (Bitfield-Mask: 0x1f) */
+#define SPI1_TIMING_MIDI_Pos (0UL) /*!< MIDI (Bit 0) */
+#define SPI1_TIMING_MIDI_Msk (0x1fUL) /*!< MIDI (Bitfield-Mask: 0x1f) */
+/* ========================================================= INTEN ========================================================= */
+#define SPI1_INTEN_RXCIE_Pos (11UL) /*!< RXCIE (Bit 11) */
+#define SPI1_INTEN_RXCIE_Msk (0x800UL) /*!< RXCIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_TXCIE_Pos (10UL) /*!< TXCIE (Bit 10) */
+#define SPI1_INTEN_TXCIE_Msk (0x400UL) /*!< TXCIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_RXDEIE_Pos (9UL) /*!< RXDEIE (Bit 9) */
+#define SPI1_INTEN_RXDEIE_Msk (0x200UL) /*!< RXDEIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_TXDEIE_Pos (8UL) /*!< TXDEIE (Bit 8) */
+#define SPI1_INTEN_TXDEIE_Msk (0x100UL) /*!< TXDEIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_MDFIE_Pos (7UL) /*!< MDFIE (Bit 7) */
+#define SPI1_INTEN_MDFIE_Msk (0x80UL) /*!< MDFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_OPFIE_Pos (6UL) /*!< OPFIE (Bit 6) */
+#define SPI1_INTEN_OPFIE_Msk (0x40UL) /*!< OPFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_TXUFIE_Pos (5UL) /*!< TXUFIE (Bit 5) */
+#define SPI1_INTEN_TXUFIE_Msk (0x20UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_TXOFIE_Pos (4UL) /*!< TXOFIE (Bit 4) */
+#define SPI1_INTEN_TXOFIE_Msk (0x10UL) /*!< TXOFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_RXUFIE_Pos (3UL) /*!< RXUFIE (Bit 3) */
+#define SPI1_INTEN_RXUFIE_Msk (0x8UL) /*!< RXUFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_RXOFIE_Pos (2UL) /*!< RXOFIE (Bit 2) */
+#define SPI1_INTEN_RXOFIE_Msk (0x4UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_TXEIE_Pos (1UL) /*!< TXEIE (Bit 1) */
+#define SPI1_INTEN_TXEIE_Msk (0x2UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_RXFIE_Pos (0UL) /*!< RXFIE (Bit 0) */
+#define SPI1_INTEN_RXFIE_Msk (0x1UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define SPI1_INT_RXCI_Pos (11UL) /*!< RXCI (Bit 11) */
+#define SPI1_INT_RXCI_Msk (0x800UL) /*!< RXCI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_TXCI_Pos (10UL) /*!< TXCI (Bit 10) */
+#define SPI1_INT_TXCI_Msk (0x400UL) /*!< TXCI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_RXDEI_Pos (9UL) /*!< RXDEI (Bit 9) */
+#define SPI1_INT_RXDEI_Msk (0x200UL) /*!< RXDEI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_TXDEI_Pos (8UL) /*!< TXDEI (Bit 8) */
+#define SPI1_INT_TXDEI_Msk (0x100UL) /*!< TXDEI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_MDFI_Pos (7UL) /*!< MDFI (Bit 7) */
+#define SPI1_INT_MDFI_Msk (0x80UL) /*!< MDFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_OPFI_Pos (6UL) /*!< OPFI (Bit 6) */
+#define SPI1_INT_OPFI_Msk (0x40UL) /*!< OPFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_TXUFI_Pos (5UL) /*!< TXUFI (Bit 5) */
+#define SPI1_INT_TXUFI_Msk (0x20UL) /*!< TXUFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_TXOFI_Pos (4UL) /*!< TXOFI (Bit 4) */
+#define SPI1_INT_TXOFI_Msk (0x10UL) /*!< TXOFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_RXUFI_Pos (3UL) /*!< RXUFI (Bit 3) */
+#define SPI1_INT_RXUFI_Msk (0x8UL) /*!< RXUFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_RXOFI_Pos (2UL) /*!< RXOFI (Bit 2) */
+#define SPI1_INT_RXOFI_Msk (0x4UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define SPI1_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define SPI1_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define SPI1_STATUS_RFF_Pos (30UL) /*!< RFF (Bit 30) */
+#define SPI1_STATUS_RFF_Msk (0x40000000UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define SPI1_STATUS_RFE_Pos (29UL) /*!< RFE (Bit 29) */
+#define SPI1_STATUS_RFE_Msk (0x20000000UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define SPI1_STATUS_RXFLR_Pos (24UL) /*!< RXFLR (Bit 24) */
+#define SPI1_STATUS_RXFLR_Msk (0x1f000000UL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
+#define SPI1_STATUS_TFF_Pos (22UL) /*!< TFF (Bit 22) */
+#define SPI1_STATUS_TFF_Msk (0x400000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define SPI1_STATUS_TFE_Pos (21UL) /*!< TFE (Bit 21) */
+#define SPI1_STATUS_TFE_Msk (0x200000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define SPI1_STATUS_TXFLR_Pos (16UL) /*!< TXFLR (Bit 16) */
+#define SPI1_STATUS_TXFLR_Msk (0x1f0000UL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
+#define SPI1_STATUS_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */
+#define SPI1_STATUS_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+/* ========================================================== TDR ========================================================== */
+#define SPI1_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define SPI1_TDR_TD_Msk (0xffffUL) /*!< TD (Bitfield-Mask: 0xffff) */
+/* ========================================================== RDR ========================================================== */
+#define SPI1_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define SPI1_RDR_RD_Msk (0xffffUL) /*!< RD (Bitfield-Mask: 0xffff) */
+/* ========================================================= UDRDR ========================================================= */
+#define SPI1_UDRDR_UDRDR_Pos (0UL) /*!< UDRDR (Bit 0) */
+#define SPI1_UDRDR_UDRDR_Msk (0xffffUL) /*!< UDRDR (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ RCU ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PLL0CR ========================================================= */
+#define RCU_PLL0CR_EN_Pos (31UL) /*!< EN (Bit 31) */
+#define RCU_PLL0CR_EN_Msk (0x80000000UL) /*!< EN (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_LKF_Pos (30UL) /*!< LKF (Bit 30) */
+#define RCU_PLL0CR_LKF_Msk (0x40000000UL) /*!< LKF (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_RFD_Pos (11UL) /*!< RFD (Bit 11) */
+#define RCU_PLL0CR_RFD_Msk (0x800UL) /*!< RFD (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_LPF_Pos (10UL) /*!< LPF (Bit 10) */
+#define RCU_PLL0CR_LPF_Msk (0x400UL) /*!< LPF (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_BDS_Pos (8UL) /*!< BDS (Bit 8) */
+#define RCU_PLL0CR_BDS_Msk (0x300UL) /*!< BDS (Bitfield-Mask: 0x03) */
+#define RCU_PLL0CR_UG_Pos (3UL) /*!< UG (Bit 3) */
+#define RCU_PLL0CR_UG_Msk (0x8UL) /*!< UG (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_ARE_Pos (2UL) /*!< ARE (Bit 2) */
+#define RCU_PLL0CR_ARE_Msk (0x4UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_RCS_Pos (0UL) /*!< RCS (Bit 0) */
+#define RCU_PLL0CR_RCS_Msk (0x3UL) /*!< RCS (Bitfield-Mask: 0x03) */
+/* ======================================================== PLL0FR ========================================================= */
+#define RCU_PLL0FR_INT_Pos (16UL) /*!< INT (Bit 16) */
+#define RCU_PLL0FR_INT_Msk (0x3fff0000UL) /*!< INT (Bitfield-Mask: 0x3fff) */
+#define RCU_PLL0FR_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
+#define RCU_PLL0FR_FRAC_Msk (0xffffUL) /*!< FRAC (Bitfield-Mask: 0xffff) */
+/* ========================================================== CCR ========================================================== */
+#define RCU_CCR_P1PSC_Pos (12UL) /*!< P1PSC (Bit 12) */
+#define RCU_CCR_P1PSC_Msk (0xf000UL) /*!< P1PSC (Bitfield-Mask: 0x0f) */
+#define RCU_CCR_P0PSC_Pos (8UL) /*!< P0PSC (Bit 8) */
+#define RCU_CCR_P0PSC_Msk (0xf00UL) /*!< P0PSC (Bitfield-Mask: 0x0f) */
+#define RCU_CCR_HPSC_Pos (2UL) /*!< HPSC (Bit 2) */
+#define RCU_CCR_HPSC_Msk (0xfcUL) /*!< HPSC (Bitfield-Mask: 0x3f) */
+#define RCU_CCR_SCS_Pos (0UL) /*!< SCS (Bit 0) */
+#define RCU_CCR_SCS_Msk (0x3UL) /*!< SCS (Bitfield-Mask: 0x03) */
+/* ========================================================= PCSR ========================================================== */
+#define RCU_PCSR_TMR6CS_Pos (8UL) /*!< TMR6CS (Bit 8) */
+#define RCU_PCSR_TMR6CS_Msk (0x300UL) /*!< TMR6CS (Bitfield-Mask: 0x03) */
+#define RCU_PCSR_CANCS_Pos (6UL) /*!< CANCS (Bit 6) */
+#define RCU_PCSR_CANCS_Msk (0xc0UL) /*!< CANCS (Bitfield-Mask: 0x03) */
+#define RCU_PCSR_USBCS_Pos (4UL) /*!< USBCS (Bit 4) */
+#define RCU_PCSR_USBCS_Msk (0x30UL) /*!< USBCS (Bitfield-Mask: 0x03) */
+#define RCU_PCSR_ADCCS_Pos (2UL) /*!< ADCCS (Bit 2) */
+#define RCU_PCSR_ADCCS_Msk (0xcUL) /*!< ADCCS (Bitfield-Mask: 0x03) */
+#define RCU_PCSR_PWMCS_Pos (0UL) /*!< PWMCS (Bit 0) */
+#define RCU_PCSR_PWMCS_Msk (0x3UL) /*!< PWMCS (Bitfield-Mask: 0x03) */
+/* ========================================================= PCDR0 ========================================================= */
+#define RCU_PCDR0_PDDIV_Pos (24UL) /*!< PDDIV (Bit 24) */
+#define RCU_PCDR0_PDDIV_Msk (0xff000000UL) /*!< PDDIV (Bitfield-Mask: 0xff) */
+#define RCU_PCDR0_PCDIV_Pos (16UL) /*!< PCDIV (Bit 16) */
+#define RCU_PCDR0_PCDIV_Msk (0xff0000UL) /*!< PCDIV (Bitfield-Mask: 0xff) */
+#define RCU_PCDR0_PBDIV_Pos (8UL) /*!< PBDIV (Bit 8) */
+#define RCU_PCDR0_PBDIV_Msk (0xff00UL) /*!< PBDIV (Bitfield-Mask: 0xff) */
+#define RCU_PCDR0_PADIV_Pos (0UL) /*!< PADIV (Bit 0) */
+#define RCU_PCDR0_PADIV_Msk (0xffUL) /*!< PADIV (Bitfield-Mask: 0xff) */
+/* ========================================================= PCDR1 ========================================================= */
+#define RCU_PCDR1_PFDIV_Pos (8UL) /*!< PFDIV (Bit 8) */
+#define RCU_PCDR1_PFDIV_Msk (0xff00UL) /*!< PFDIV (Bitfield-Mask: 0xff) */
+#define RCU_PCDR1_PEDIV_Pos (0UL) /*!< PEDIV (Bit 0) */
+#define RCU_PCDR1_PEDIV_Msk (0xffUL) /*!< PEDIV (Bitfield-Mask: 0xff) */
+/* ========================================================= PCDR2 ========================================================= */
+#define RCU_PCDR2_CANDIV_Pos (12UL) /*!< CANDIV (Bit 12) */
+#define RCU_PCDR2_CANDIV_Msk (0xf000UL) /*!< CANDIV (Bitfield-Mask: 0x0f) */
+#define RCU_PCDR2_USBDIV_Pos (8UL) /*!< USBDIV (Bit 8) */
+#define RCU_PCDR2_USBDIV_Msk (0xf00UL) /*!< USBDIV (Bitfield-Mask: 0x0f) */
+#define RCU_PCDR2_ADCDIV_Pos (4UL) /*!< ADCDIV (Bit 4) */
+#define RCU_PCDR2_ADCDIV_Msk (0xf0UL) /*!< ADCDIV (Bitfield-Mask: 0x0f) */
+#define RCU_PCDR2_PWMDIV_Pos (0UL) /*!< PWMDIV (Bit 0) */
+#define RCU_PCDR2_PWMDIV_Msk (0xfUL) /*!< PWMDIV (Bitfield-Mask: 0x0f) */
+/* ========================================================= PCENR ========================================================= */
+#define RCU_PCENR_TMR6FEN_Pos (15UL) /*!< TMR6FEN (Bit 15) */
+#define RCU_PCENR_TMR6FEN_Msk (0x8000UL) /*!< TMR6FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_CAN1FEN_Pos (14UL) /*!< CAN1FEN (Bit 14) */
+#define RCU_PCENR_CAN1FEN_Msk (0x4000UL) /*!< CAN1FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_CAN0FEN_Pos (13UL) /*!< CAN0FEN (Bit 13) */
+#define RCU_PCENR_CAN0FEN_Msk (0x2000UL) /*!< CAN0FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_USBFEN_Pos (12UL) /*!< USBFEN (Bit 12) */
+#define RCU_PCENR_USBFEN_Msk (0x1000UL) /*!< USBFEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM7FEN_Pos (11UL) /*!< PWM7FEN (Bit 11) */
+#define RCU_PCENR_PWM7FEN_Msk (0x800UL) /*!< PWM7FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM6FEN_Pos (10UL) /*!< PWM6FEN (Bit 10) */
+#define RCU_PCENR_PWM6FEN_Msk (0x400UL) /*!< PWM6FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM5FEN_Pos (9UL) /*!< PWM5FEN (Bit 9) */
+#define RCU_PCENR_PWM5FEN_Msk (0x200UL) /*!< PWM5FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM4FEN_Pos (8UL) /*!< PWM4FEN (Bit 8) */
+#define RCU_PCENR_PWM4FEN_Msk (0x100UL) /*!< PWM4FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM3FEN_Pos (7UL) /*!< PWM3FEN (Bit 7) */
+#define RCU_PCENR_PWM3FEN_Msk (0x80UL) /*!< PWM3FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM2FEN_Pos (6UL) /*!< PWM2FEN (Bit 6) */
+#define RCU_PCENR_PWM2FEN_Msk (0x40UL) /*!< PWM2FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM1FEN_Pos (5UL) /*!< PWM1FEN (Bit 5) */
+#define RCU_PCENR_PWM1FEN_Msk (0x20UL) /*!< PWM1FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM0FEN_Pos (4UL) /*!< PWM0FEN (Bit 4) */
+#define RCU_PCENR_PWM0FEN_Msk (0x10UL) /*!< PWM0FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_ADC3FEN_Pos (3UL) /*!< ADC3FEN (Bit 3) */
+#define RCU_PCENR_ADC3FEN_Msk (0x8UL) /*!< ADC3FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_ADC2FEN_Pos (2UL) /*!< ADC2FEN (Bit 2) */
+#define RCU_PCENR_ADC2FEN_Msk (0x4UL) /*!< ADC2FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_ADC1FEN_Pos (1UL) /*!< ADC1FEN (Bit 1) */
+#define RCU_PCENR_ADC1FEN_Msk (0x2UL) /*!< ADC1FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_ADC0FEN_Pos (0UL) /*!< ADC0FEN (Bit 0) */
+#define RCU_PCENR_ADC0FEN_Msk (0x1UL) /*!< ADC0FEN (Bitfield-Mask: 0x01) */
+/* ======================================================== APB0ENR ======================================================== */
+#define RCU_APB0ENR_TMR6EN_Pos (8UL) /*!< TMR6EN (Bit 8) */
+#define RCU_APB0ENR_TMR6EN_Msk (0x100UL) /*!< TMR6EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_TMR8EN_Pos (7UL) /*!< TMR8EN (Bit 7) */
+#define RCU_APB0ENR_TMR8EN_Msk (0x80UL) /*!< TMR8EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_TMR7EN_Pos (6UL) /*!< TMR7EN (Bit 6) */
+#define RCU_APB0ENR_TMR7EN_Msk (0x40UL) /*!< TMR7EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_UART2EN_Pos (5UL) /*!< UART2EN (Bit 5) */
+#define RCU_APB0ENR_UART2EN_Msk (0x20UL) /*!< UART2EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_UART1EN_Pos (4UL) /*!< UART1EN (Bit 4) */
+#define RCU_APB0ENR_UART1EN_Msk (0x10UL) /*!< UART1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_UART0EN_Pos (3UL) /*!< UART0EN (Bit 3) */
+#define RCU_APB0ENR_UART0EN_Msk (0x8UL) /*!< UART0EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_I2C2EN_Pos (2UL) /*!< I2C2EN (Bit 2) */
+#define RCU_APB0ENR_I2C2EN_Msk (0x4UL) /*!< I2C2EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_I2C1EN_Pos (1UL) /*!< I2C1EN (Bit 1) */
+#define RCU_APB0ENR_I2C1EN_Msk (0x2UL) /*!< I2C1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_I2C0EN_Pos (0UL) /*!< I2C0EN (Bit 0) */
+#define RCU_APB0ENR_I2C0EN_Msk (0x1UL) /*!< I2C0EN (Bitfield-Mask: 0x01) */
+/* ======================================================== APB1ENR ======================================================== */
+#define RCU_APB1ENR_TMR2EN_Pos (13UL) /*!< TMR2EN (Bit 13) */
+#define RCU_APB1ENR_TMR2EN_Msk (0x2000UL) /*!< TMR2EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_TMR1EN_Pos (12UL) /*!< TMR1EN (Bit 12) */
+#define RCU_APB1ENR_TMR1EN_Msk (0x1000UL) /*!< TMR1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_TMR0EN_Pos (11UL) /*!< TMR0EN (Bit 11) */
+#define RCU_APB1ENR_TMR0EN_Msk (0x800UL) /*!< TMR0EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_PDM3EN_Pos (10UL) /*!< PDM3EN (Bit 10) */
+#define RCU_APB1ENR_PDM3EN_Msk (0x400UL) /*!< PDM3EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_PDM2EN_Pos (9UL) /*!< PDM2EN (Bit 9) */
+#define RCU_APB1ENR_PDM2EN_Msk (0x200UL) /*!< PDM2EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_PDM1EN_Pos (8UL) /*!< PDM1EN (Bit 8) */
+#define RCU_APB1ENR_PDM1EN_Msk (0x100UL) /*!< PDM1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_PDM0EN_Pos (7UL) /*!< PDM0EN (Bit 7) */
+#define RCU_APB1ENR_PDM0EN_Msk (0x80UL) /*!< PDM0EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_XIFEN_Pos (6UL) /*!< XIFEN (Bit 6) */
+#define RCU_APB1ENR_XIFEN_Msk (0x40UL) /*!< XIFEN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_CAN1EN_Pos (5UL) /*!< CAN1EN (Bit 5) */
+#define RCU_APB1ENR_CAN1EN_Msk (0x20UL) /*!< CAN1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_CAN0EN_Pos (4UL) /*!< CAN0EN (Bit 4) */
+#define RCU_APB1ENR_CAN0EN_Msk (0x10UL) /*!< CAN0EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_SPI1EN_Pos (3UL) /*!< SPI1EN (Bit 3) */
+#define RCU_APB1ENR_SPI1EN_Msk (0x8UL) /*!< SPI1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_SPI0EN_Pos (2UL) /*!< SPI0EN (Bit 2) */
+#define RCU_APB1ENR_SPI0EN_Msk (0x4UL) /*!< SPI0EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_UART4EN_Pos (1UL) /*!< UART4EN (Bit 1) */
+#define RCU_APB1ENR_UART4EN_Msk (0x2UL) /*!< UART4EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_UART3EN_Pos (0UL) /*!< UART3EN (Bit 0) */
+#define RCU_APB1ENR_UART3EN_Msk (0x1UL) /*!< UART3EN (Bitfield-Mask: 0x01) */
+/* ======================================================== AHB0ENR ======================================================== */
+#define RCU_AHB0ENR_QEI2EN_Pos (12UL) /*!< QEI2EN (Bit 12) */
+#define RCU_AHB0ENR_QEI2EN_Msk (0x1000UL) /*!< QEI2EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_QEI1EN_Pos (11UL) /*!< QEI1EN (Bit 11) */
+#define RCU_AHB0ENR_QEI1EN_Msk (0x800UL) /*!< QEI1EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_QEI0EN_Pos (10UL) /*!< QEI0EN (Bit 10) */
+#define RCU_AHB0ENR_QEI0EN_Msk (0x400UL) /*!< QEI0EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_TMR4EN_Pos (9UL) /*!< TMR4EN (Bit 9) */
+#define RCU_AHB0ENR_TMR4EN_Msk (0x200UL) /*!< TMR4EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_TMR3EN_Pos (8UL) /*!< TMR3EN (Bit 8) */
+#define RCU_AHB0ENR_TMR3EN_Msk (0x100UL) /*!< TMR3EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PFEN_Pos (7UL) /*!< PFEN (Bit 7) */
+#define RCU_AHB0ENR_PFEN_Msk (0x80UL) /*!< PFEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PEEN_Pos (6UL) /*!< PEEN (Bit 6) */
+#define RCU_AHB0ENR_PEEN_Msk (0x40UL) /*!< PEEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PDEN_Pos (5UL) /*!< PDEN (Bit 5) */
+#define RCU_AHB0ENR_PDEN_Msk (0x20UL) /*!< PDEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PCEN_Pos (4UL) /*!< PCEN (Bit 4) */
+#define RCU_AHB0ENR_PCEN_Msk (0x10UL) /*!< PCEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PBEN_Pos (3UL) /*!< PBEN (Bit 3) */
+#define RCU_AHB0ENR_PBEN_Msk (0x8UL) /*!< PBEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PAEN_Pos (2UL) /*!< PAEN (Bit 2) */
+#define RCU_AHB0ENR_PAEN_Msk (0x4UL) /*!< PAEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_FLSEN_Pos (1UL) /*!< FLSEN (Bit 1) */
+#define RCU_AHB0ENR_FLSEN_Msk (0x2UL) /*!< FLSEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */
+#define RCU_AHB0ENR_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+/* ======================================================== AHB1ENR ======================================================== */
+#define RCU_AHB1ENR_CORDICEN_Pos (23UL) /*!< CORDICEN (Bit 23) */
+#define RCU_AHB1ENR_CORDICEN_Msk (0x800000UL) /*!< CORDICEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR5EN_Pos (22UL) /*!< IIR5EN (Bit 22) */
+#define RCU_AHB1ENR_IIR5EN_Msk (0x400000UL) /*!< IIR5EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR4EN_Pos (21UL) /*!< IIR4EN (Bit 21) */
+#define RCU_AHB1ENR_IIR4EN_Msk (0x200000UL) /*!< IIR4EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR3EN_Pos (20UL) /*!< IIR3EN (Bit 20) */
+#define RCU_AHB1ENR_IIR3EN_Msk (0x100000UL) /*!< IIR3EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR2EN_Pos (19UL) /*!< IIR2EN (Bit 19) */
+#define RCU_AHB1ENR_IIR2EN_Msk (0x80000UL) /*!< IIR2EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR1EN_Pos (18UL) /*!< IIR1EN (Bit 18) */
+#define RCU_AHB1ENR_IIR1EN_Msk (0x40000UL) /*!< IIR1EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR0EN_Pos (17UL) /*!< IIR0EN (Bit 17) */
+#define RCU_AHB1ENR_IIR0EN_Msk (0x20000UL) /*!< IIR0EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM7EN_Pos (16UL) /*!< PWM7EN (Bit 16) */
+#define RCU_AHB1ENR_PWM7EN_Msk (0x10000UL) /*!< PWM7EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM6EN_Pos (15UL) /*!< PWM6EN (Bit 15) */
+#define RCU_AHB1ENR_PWM6EN_Msk (0x8000UL) /*!< PWM6EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM5EN_Pos (14UL) /*!< PWM5EN (Bit 14) */
+#define RCU_AHB1ENR_PWM5EN_Msk (0x4000UL) /*!< PWM5EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM4EN_Pos (13UL) /*!< PWM4EN (Bit 13) */
+#define RCU_AHB1ENR_PWM4EN_Msk (0x2000UL) /*!< PWM4EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM3EN_Pos (12UL) /*!< PWM3EN (Bit 12) */
+#define RCU_AHB1ENR_PWM3EN_Msk (0x1000UL) /*!< PWM3EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM2EN_Pos (11UL) /*!< PWM2EN (Bit 11) */
+#define RCU_AHB1ENR_PWM2EN_Msk (0x800UL) /*!< PWM2EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM1EN_Pos (10UL) /*!< PWM1EN (Bit 10) */
+#define RCU_AHB1ENR_PWM1EN_Msk (0x400UL) /*!< PWM1EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM0EN_Pos (9UL) /*!< PWM0EN (Bit 9) */
+#define RCU_AHB1ENR_PWM0EN_Msk (0x200UL) /*!< PWM0EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_CMPxEN_Pos (8UL) /*!< CMPxEN (Bit 8) */
+#define RCU_AHB1ENR_CMPxEN_Msk (0x100UL) /*!< CMPxEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_DACxEN_Pos (7UL) /*!< DACxEN (Bit 7) */
+#define RCU_AHB1ENR_DACxEN_Msk (0x80UL) /*!< DACxEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_ADC3EN_Pos (6UL) /*!< ADC3EN (Bit 6) */
+#define RCU_AHB1ENR_ADC3EN_Msk (0x40UL) /*!< ADC3EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_ADC2EN_Pos (5UL) /*!< ADC2EN (Bit 5) */
+#define RCU_AHB1ENR_ADC2EN_Msk (0x20UL) /*!< ADC2EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_ADC1EN_Pos (4UL) /*!< ADC1EN (Bit 4) */
+#define RCU_AHB1ENR_ADC1EN_Msk (0x10UL) /*!< ADC1EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_ADC0EN_Pos (3UL) /*!< ADC0EN (Bit 3) */
+#define RCU_AHB1ENR_ADC0EN_Msk (0x8UL) /*!< ADC0EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_USBEN_Pos (2UL) /*!< USBEN (Bit 2) */
+#define RCU_AHB1ENR_USBEN_Msk (0x4UL) /*!< USBEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_TMR10EN_Pos (1UL) /*!< TMR10EN (Bit 1) */
+#define RCU_AHB1ENR_TMR10EN_Msk (0x2UL) /*!< TMR10EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_TMR9EN_Pos (0UL) /*!< TMR9EN (Bit 0) */
+#define RCU_AHB1ENR_TMR9EN_Msk (0x1UL) /*!< TMR9EN (Bitfield-Mask: 0x01) */
+/* ======================================================= APB0RSTR ======================================================== */
+#define RCU_APB0RSTR_TMR6RST_Pos (8UL) /*!< TMR6RST (Bit 8) */
+#define RCU_APB0RSTR_TMR6RST_Msk (0x100UL) /*!< TMR6RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_TMR8RST_Pos (7UL) /*!< TMR8RST (Bit 7) */
+#define RCU_APB0RSTR_TMR8RST_Msk (0x80UL) /*!< TMR8RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_TMR7RST_Pos (6UL) /*!< TMR7RST (Bit 6) */
+#define RCU_APB0RSTR_TMR7RST_Msk (0x40UL) /*!< TMR7RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_UART2RST_Pos (5UL) /*!< UART2RST (Bit 5) */
+#define RCU_APB0RSTR_UART2RST_Msk (0x20UL) /*!< UART2RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_UART1RST_Pos (4UL) /*!< UART1RST (Bit 4) */
+#define RCU_APB0RSTR_UART1RST_Msk (0x10UL) /*!< UART1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_UART0RST_Pos (3UL) /*!< UART0RST (Bit 3) */
+#define RCU_APB0RSTR_UART0RST_Msk (0x8UL) /*!< UART0RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_I2C2RST_Pos (2UL) /*!< I2C2RST (Bit 2) */
+#define RCU_APB0RSTR_I2C2RST_Msk (0x4UL) /*!< I2C2RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_I2C1RST_Pos (1UL) /*!< I2C1RST (Bit 1) */
+#define RCU_APB0RSTR_I2C1RST_Msk (0x2UL) /*!< I2C1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_I2C0RST_Pos (0UL) /*!< I2C0RST (Bit 0) */
+#define RCU_APB0RSTR_I2C0RST_Msk (0x1UL) /*!< I2C0RST (Bitfield-Mask: 0x01) */
+/* ======================================================= APB1RSTR ======================================================== */
+#define RCU_APB1RSTR_TMR2RST_Pos (13UL) /*!< TMR2RST (Bit 13) */
+#define RCU_APB1RSTR_TMR2RST_Msk (0x2000UL) /*!< TMR2RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_TMR1RST_Pos (12UL) /*!< TMR1RST (Bit 12) */
+#define RCU_APB1RSTR_TMR1RST_Msk (0x1000UL) /*!< TMR1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_TMR0RST_Pos (11UL) /*!< TMR0RST (Bit 11) */
+#define RCU_APB1RSTR_TMR0RST_Msk (0x800UL) /*!< TMR0RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_PDM3RST_Pos (10UL) /*!< PDM3RST (Bit 10) */
+#define RCU_APB1RSTR_PDM3RST_Msk (0x400UL) /*!< PDM3RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_PDM2RST_Pos (9UL) /*!< PDM2RST (Bit 9) */
+#define RCU_APB1RSTR_PDM2RST_Msk (0x200UL) /*!< PDM2RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_PDM1RST_Pos (8UL) /*!< PDM1RST (Bit 8) */
+#define RCU_APB1RSTR_PDM1RST_Msk (0x100UL) /*!< PDM1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_PDM0RST_Pos (7UL) /*!< PDM0RST (Bit 7) */
+#define RCU_APB1RSTR_PDM0RST_Msk (0x80UL) /*!< PDM0RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_XIFRST_Pos (6UL) /*!< XIFRST (Bit 6) */
+#define RCU_APB1RSTR_XIFRST_Msk (0x40UL) /*!< XIFRST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_CAN1RST_Pos (5UL) /*!< CAN1RST (Bit 5) */
+#define RCU_APB1RSTR_CAN1RST_Msk (0x20UL) /*!< CAN1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_CAN0RST_Pos (4UL) /*!< CAN0RST (Bit 4) */
+#define RCU_APB1RSTR_CAN0RST_Msk (0x10UL) /*!< CAN0RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_SPI1RST_Pos (3UL) /*!< SPI1RST (Bit 3) */
+#define RCU_APB1RSTR_SPI1RST_Msk (0x8UL) /*!< SPI1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_SPI0RST_Pos (2UL) /*!< SPI0RST (Bit 2) */
+#define RCU_APB1RSTR_SPI0RST_Msk (0x4UL) /*!< SPI0RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_UART4RST_Pos (1UL) /*!< UART4RST (Bit 1) */
+#define RCU_APB1RSTR_UART4RST_Msk (0x2UL) /*!< UART4RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_UART3RST_Pos (0UL) /*!< UART3RST (Bit 0) */
+#define RCU_APB1RSTR_UART3RST_Msk (0x1UL) /*!< UART3RST (Bitfield-Mask: 0x01) */
+/* ======================================================= AHB0RSTR ======================================================== */
+#define RCU_AHB0RSTR_QEI2RST_Pos (12UL) /*!< QEI2RST (Bit 12) */
+#define RCU_AHB0RSTR_QEI2RST_Msk (0x1000UL) /*!< QEI2RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_QEI1RST_Pos (11UL) /*!< QEI1RST (Bit 11) */
+#define RCU_AHB0RSTR_QEI1RST_Msk (0x800UL) /*!< QEI1RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_QEI0RST_Pos (10UL) /*!< QEI0RST (Bit 10) */
+#define RCU_AHB0RSTR_QEI0RST_Msk (0x400UL) /*!< QEI0RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_TMR4RST_Pos (9UL) /*!< TMR4RST (Bit 9) */
+#define RCU_AHB0RSTR_TMR4RST_Msk (0x200UL) /*!< TMR4RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_TMR3RST_Pos (8UL) /*!< TMR3RST (Bit 8) */
+#define RCU_AHB0RSTR_TMR3RST_Msk (0x100UL) /*!< TMR3RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PFRST_Pos (7UL) /*!< PFRST (Bit 7) */
+#define RCU_AHB0RSTR_PFRST_Msk (0x80UL) /*!< PFRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PERST_Pos (6UL) /*!< PERST (Bit 6) */
+#define RCU_AHB0RSTR_PERST_Msk (0x40UL) /*!< PERST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PDRST_Pos (5UL) /*!< PDRST (Bit 5) */
+#define RCU_AHB0RSTR_PDRST_Msk (0x20UL) /*!< PDRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PCRST_Pos (4UL) /*!< PCRST (Bit 4) */
+#define RCU_AHB0RSTR_PCRST_Msk (0x10UL) /*!< PCRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PBRST_Pos (3UL) /*!< PBRST (Bit 3) */
+#define RCU_AHB0RSTR_PBRST_Msk (0x8UL) /*!< PBRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PARST_Pos (2UL) /*!< PARST (Bit 2) */
+#define RCU_AHB0RSTR_PARST_Msk (0x4UL) /*!< PARST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_FLSRST_Pos (1UL) /*!< FLSRST (Bit 1) */
+#define RCU_AHB0RSTR_FLSRST_Msk (0x2UL) /*!< FLSRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_DMARST_Pos (0UL) /*!< DMARST (Bit 0) */
+#define RCU_AHB0RSTR_DMARST_Msk (0x1UL) /*!< DMARST (Bitfield-Mask: 0x01) */
+/* ======================================================= AHB1RSTR ======================================================== */
+#define RCU_AHB1RSTR_CORDICRST_Pos (13UL) /*!< CORDICRST (Bit 13) */
+#define RCU_AHB1RSTR_CORDICRST_Msk (0x2000UL) /*!< CORDICRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR5RST_Pos (12UL) /*!< IIR5RST (Bit 12) */
+#define RCU_AHB1RSTR_IIR5RST_Msk (0x1000UL) /*!< IIR5RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR4RST_Pos (11UL) /*!< IIR4RST (Bit 11) */
+#define RCU_AHB1RSTR_IIR4RST_Msk (0x800UL) /*!< IIR4RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR3RST_Pos (10UL) /*!< IIR3RST (Bit 10) */
+#define RCU_AHB1RSTR_IIR3RST_Msk (0x400UL) /*!< IIR3RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR2RST_Pos (9UL) /*!< IIR2RST (Bit 9) */
+#define RCU_AHB1RSTR_IIR2RST_Msk (0x200UL) /*!< IIR2RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR1RST_Pos (8UL) /*!< IIR1RST (Bit 8) */
+#define RCU_AHB1RSTR_IIR1RST_Msk (0x100UL) /*!< IIR1RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR0RST_Pos (7UL) /*!< IIR0RST (Bit 7) */
+#define RCU_AHB1RSTR_IIR0RST_Msk (0x80UL) /*!< IIR0RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_PWMRST_Pos (6UL) /*!< PWMRST (Bit 6) */
+#define RCU_AHB1RSTR_PWMRST_Msk (0x40UL) /*!< PWMRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_CMPRST_Pos (5UL) /*!< CMPRST (Bit 5) */
+#define RCU_AHB1RSTR_CMPRST_Msk (0x20UL) /*!< CMPRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_DACRST_Pos (4UL) /*!< DACRST (Bit 4) */
+#define RCU_AHB1RSTR_DACRST_Msk (0x10UL) /*!< DACRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_ADCRST_Pos (3UL) /*!< ADCRST (Bit 3) */
+#define RCU_AHB1RSTR_ADCRST_Msk (0x8UL) /*!< ADCRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_USBRST_Pos (2UL) /*!< USBRST (Bit 2) */
+#define RCU_AHB1RSTR_USBRST_Msk (0x4UL) /*!< USBRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_TMR10RST_Pos (1UL) /*!< TMR10RST (Bit 1) */
+#define RCU_AHB1RSTR_TMR10RST_Msk (0x2UL) /*!< TMR10RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_TMR9RST_Pos (0UL) /*!< TMR9RST (Bit 0) */
+#define RCU_AHB1RSTR_TMR9RST_Msk (0x1UL) /*!< TMR9RST (Bitfield-Mask: 0x01) */
+/* ======================================================== XOSCCR ========================================================= */
+#define RCU_XOSCCR_HEN_Pos (4UL) /*!< HEN (Bit 4) */
+#define RCU_XOSCCR_HEN_Msk (0x10UL) /*!< HEN (Bitfield-Mask: 0x01) */
+#define RCU_XOSCCR_XDR_Pos (1UL) /*!< XDR (Bit 1) */
+#define RCU_XOSCCR_XDR_Msk (0xeUL) /*!< XDR (Bitfield-Mask: 0x07) */
+#define RCU_XOSCCR_XEN_Pos (0UL) /*!< XEN (Bit 0) */
+#define RCU_XOSCCR_XEN_Msk (0x1UL) /*!< XEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CSSCR ========================================================= */
+#define RCU_CSSCR_LMT_Pos (6UL) /*!< LMT (Bit 6) */
+#define RCU_CSSCR_LMT_Msk (0xc0UL) /*!< LMT (Bitfield-Mask: 0x03) */
+#define RCU_CSSCR_WIN_Pos (4UL) /*!< WIN (Bit 4) */
+#define RCU_CSSCR_WIN_Msk (0x30UL) /*!< WIN (Bitfield-Mask: 0x03) */
+#define RCU_CSSCR_LPD_Pos (3UL) /*!< LPD (Bit 3) */
+#define RCU_CSSCR_LPD_Msk (0x8UL) /*!< LPD (Bitfield-Mask: 0x01) */
+#define RCU_CSSCR_LPE_Pos (2UL) /*!< LPE (Bit 2) */
+#define RCU_CSSCR_LPE_Msk (0x4UL) /*!< LPE (Bitfield-Mask: 0x01) */
+#define RCU_CSSCR_SSE_Pos (1UL) /*!< SSE (Bit 1) */
+#define RCU_CSSCR_SSE_Msk (0x2UL) /*!< SSE (Bitfield-Mask: 0x01) */
+#define RCU_CSSCR_SWE_Pos (0UL) /*!< SWE (Bit 0) */
+#define RCU_CSSCR_SWE_Msk (0x1UL) /*!< SWE (Bitfield-Mask: 0x01) */
+/* ========================================================= DBGCR ========================================================= */
+#define RCU_DBGCR_ECIE_Pos (5UL) /*!< ECIE (Bit 5) */
+#define RCU_DBGCR_ECIE_Msk (0x20UL) /*!< ECIE (Bitfield-Mask: 0x01) */
+#define RCU_DBGCR_MCOEN_Pos (4UL) /*!< MCOEN (Bit 4) */
+#define RCU_DBGCR_MCOEN_Msk (0x10UL) /*!< MCOEN (Bitfield-Mask: 0x01) */
+#define RCU_DBGCR_MCO_Pos (0UL) /*!< MCO (Bit 0) */
+#define RCU_DBGCR_MCO_Msk (0x7UL) /*!< MCO (Bitfield-Mask: 0x07) */
+/* ======================================================== SRSTSR ========================================================= */
+#define RCU_SRSTSR_IWRSTE_Pos (11UL) /*!< IWRSTE (Bit 11) */
+#define RCU_SRSTSR_IWRSTE_Msk (0x800UL) /*!< IWRSTE (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_WWRSTE_Pos (10UL) /*!< WWRSTE (Bit 10) */
+#define RCU_SRSTSR_WWRSTE_Msk (0x400UL) /*!< WWRSTE (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_LKRSTE_Pos (9UL) /*!< LKRSTE (Bit 9) */
+#define RCU_SRSTSR_LKRSTE_Msk (0x200UL) /*!< LKRSTE (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_SQRSTE_Pos (8UL) /*!< SQRSTE (Bit 8) */
+#define RCU_SRSTSR_SQRSTE_Msk (0x100UL) /*!< SQRSTE (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_WWR_Pos (5UL) /*!< WWR (Bit 5) */
+#define RCU_SRSTSR_WWR_Msk (0x20UL) /*!< WWR (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_IWR_Pos (4UL) /*!< IWR (Bit 4) */
+#define RCU_SRSTSR_IWR_Msk (0x10UL) /*!< IWR (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_LKR_Pos (3UL) /*!< LKR (Bit 3) */
+#define RCU_SRSTSR_LKR_Msk (0x8UL) /*!< LKR (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_SQR_Pos (2UL) /*!< SQR (Bit 2) */
+#define RCU_SRSTSR_SQR_Msk (0x4UL) /*!< SQR (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_LPR_Pos (1UL) /*!< LPR (Bit 1) */
+#define RCU_SRSTSR_LPR_Msk (0x2UL) /*!< LPR (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_MCR_Pos (0UL) /*!< MCR (Bit 0) */
+#define RCU_SRSTSR_MCR_Msk (0x1UL) /*!< MCR (Bitfield-Mask: 0x01) */
+/* ========================================================= KEYR ========================================================== */
+#define RCU_KEYR_KEY_Pos (0UL) /*!< KEY (Bit 0) */
+#define RCU_KEYR_KEY_Msk (0x1UL) /*!< KEY (Bitfield-Mask: 0x01) */
+/* ========================================================= SRSR ========================================================== */
+#define RCU_SRSR_WWR_Pos (5UL) /*!< WWR (Bit 5) */
+#define RCU_SRSR_WWR_Msk (0x20UL) /*!< WWR (Bitfield-Mask: 0x01) */
+#define RCU_SRSR_IWR_Pos (4UL) /*!< IWR (Bit 4) */
+#define RCU_SRSR_IWR_Msk (0x10UL) /*!< IWR (Bitfield-Mask: 0x01) */
+#define RCU_SRSR_LKR_Pos (3UL) /*!< LKR (Bit 3) */
+#define RCU_SRSR_LKR_Msk (0x8UL) /*!< LKR (Bitfield-Mask: 0x01) */
+#define RCU_SRSR_SQR_Pos (2UL) /*!< SQR (Bit 2) */
+#define RCU_SRSR_SQR_Msk (0x4UL) /*!< SQR (Bitfield-Mask: 0x01) */
+#define RCU_SRSR_LPR_Pos (1UL) /*!< LPR (Bit 1) */
+#define RCU_SRSR_LPR_Msk (0x2UL) /*!< LPR (Bitfield-Mask: 0x01) */
+#define RCU_SRSR_MCR_Pos (0UL) /*!< MCR (Bit 0) */
+#define RCU_SRSR_MCR_Msk (0x1UL) /*!< MCR (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ QEI0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== POSCNT ========================================================= */
+#define QEI0_POSCNT_POSCNT_Pos (0UL) /*!< POSCNT (Bit 0) */
+#define QEI0_POSCNT_POSCNT_Msk (0xffffffffUL) /*!< POSCNT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSINIT ======================================================== */
+#define QEI0_POSINIT_POSINIT_Pos (0UL) /*!< POSINIT (Bit 0) */
+#define QEI0_POSINIT_POSINIT_Msk (0xffffffffUL) /*!< POSINIT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSMAX ========================================================= */
+#define QEI0_POSMAX_POSMAX_Pos (0UL) /*!< POSMAX (Bit 0) */
+#define QEI0_POSMAX_POSMAX_Msk (0xffffffffUL) /*!< POSMAX (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSCMP ========================================================= */
+#define QEI0_POSCMP_POSCMP_Pos (0UL) /*!< POSCMP (Bit 0) */
+#define QEI0_POSCMP_POSCMP_Msk (0xffffffffUL) /*!< POSCMP (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSILAT ======================================================== */
+#define QEI0_POSILAT_POSILAT_Pos (0UL) /*!< POSILAT (Bit 0) */
+#define QEI0_POSILAT_POSILAT_Msk (0xffffffffUL) /*!< POSILAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSLAT ========================================================= */
+#define QEI0_POSLAT_POSLAT_Pos (0UL) /*!< POSLAT (Bit 0) */
+#define QEI0_POSLAT_POSLAT_Msk (0xffffffffUL) /*!< POSLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UTMR ========================================================== */
+#define QEI0_UTMR_UTMR_Pos (0UL) /*!< UTMR (Bit 0) */
+#define QEI0_UTMR_UTMR_Msk (0xffffffffUL) /*!< UTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UPRD ========================================================== */
+#define QEI0_UPRD_UPRD_Pos (0UL) /*!< UPRD (Bit 0) */
+#define QEI0_UPRD_UPRD_Msk (0xffffffffUL) /*!< UPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== DECCTL ========================================================= */
+#define QEI0_DECCTL_DBC_Pos (16UL) /*!< DBC (Bit 16) */
+#define QEI0_DECCTL_DBC_Msk (0xff0000UL) /*!< DBC (Bitfield-Mask: 0xff) */
+#define QEI0_DECCTL_DCM_Pos (14UL) /*!< DCM (Bit 14) */
+#define QEI0_DECCTL_DCM_Msk (0x4000UL) /*!< DCM (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_QSRC_Pos (12UL) /*!< QSRC (Bit 12) */
+#define QEI0_DECCTL_QSRC_Msk (0x3000UL) /*!< QSRC (Bitfield-Mask: 0x03) */
+#define QEI0_DECCTL_XCR_Pos (6UL) /*!< XCR (Bit 6) */
+#define QEI0_DECCTL_XCR_Msk (0x40UL) /*!< XCR (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_IGATE_Pos (5UL) /*!< IGATE (Bit 5) */
+#define QEI0_DECCTL_IGATE_Msk (0x20UL) /*!< IGATE (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_SWAP_Pos (4UL) /*!< SWAP (Bit 4) */
+#define QEI0_DECCTL_SWAP_Msk (0x10UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_QBP_Pos (3UL) /*!< QBP (Bit 3) */
+#define QEI0_DECCTL_QBP_Msk (0x8UL) /*!< QBP (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_QAP_Pos (2UL) /*!< QAP (Bit 2) */
+#define QEI0_DECCTL_QAP_Msk (0x4UL) /*!< QAP (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_QIP_Pos (0UL) /*!< QIP (Bit 0) */
+#define QEI0_DECCTL_QIP_Msk (0x1UL) /*!< QIP (Bitfield-Mask: 0x01) */
+/* ======================================================== QEPCTL ========================================================= */
+#define QEI0_QEPCTL_PCRM_Pos (12UL) /*!< PCRM (Bit 12) */
+#define QEI0_QEPCTL_PCRM_Msk (0x3000UL) /*!< PCRM (Bitfield-Mask: 0x03) */
+#define QEI0_QEPCTL_SWI_Pos (8UL) /*!< SWI (Bit 8) */
+#define QEI0_QEPCTL_SWI_Msk (0x100UL) /*!< SWI (Bitfield-Mask: 0x01) */
+#define QEI0_QEPCTL_IEI_Pos (6UL) /*!< IEI (Bit 6) */
+#define QEI0_QEPCTL_IEI_Msk (0xc0UL) /*!< IEI (Bitfield-Mask: 0x03) */
+#define QEI0_QEPCTL_IEL_Pos (4UL) /*!< IEL (Bit 4) */
+#define QEI0_QEPCTL_IEL_Msk (0x30UL) /*!< IEL (Bitfield-Mask: 0x03) */
+#define QEI0_QEPCTL_UTE_Pos (1UL) /*!< UTE (Bit 1) */
+#define QEI0_QEPCTL_UTE_Msk (0x2UL) /*!< UTE (Bitfield-Mask: 0x01) */
+#define QEI0_QEPCTL_QPE_Pos (0UL) /*!< QPE (Bit 0) */
+#define QEI0_QEPCTL_QPE_Msk (0x1UL) /*!< QPE (Bitfield-Mask: 0x01) */
+/* ======================================================== POSCTL ========================================================= */
+#define QEI0_POSCTL_PSE_Pos (1UL) /*!< PSE (Bit 1) */
+#define QEI0_POSCTL_PSE_Msk (0x2UL) /*!< PSE (Bitfield-Mask: 0x01) */
+#define QEI0_POSCTL_CCE_Pos (0UL) /*!< CCE (Bit 0) */
+#define QEI0_POSCTL_CCE_Msk (0x1UL) /*!< CCE (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPCTL ========================================================= */
+#define QEI0_CAPCTL_UPPS_Pos (8UL) /*!< UPPS (Bit 8) */
+#define QEI0_CAPCTL_UPPS_Msk (0xf00UL) /*!< UPPS (Bitfield-Mask: 0x0f) */
+#define QEI0_CAPCTL_CCPS_Pos (4UL) /*!< CCPS (Bit 4) */
+#define QEI0_CAPCTL_CCPS_Msk (0x70UL) /*!< CCPS (Bitfield-Mask: 0x07) */
+#define QEI0_CAPCTL_CMD_Pos (1UL) /*!< CMD (Bit 1) */
+#define QEI0_CAPCTL_CMD_Msk (0x2UL) /*!< CMD (Bitfield-Mask: 0x01) */
+#define QEI0_CAPCTL_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define QEI0_CAPCTL_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= QCTMR ========================================================= */
+#define QEI0_QCTMR_CTMR_Pos (0UL) /*!< CTMR (Bit 0) */
+#define QEI0_QCTMR_CTMR_Msk (0xffffffffUL) /*!< CTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= QCPRD ========================================================= */
+#define QEI0_QCPRD_CPRD_Pos (0UL) /*!< CPRD (Bit 0) */
+#define QEI0_QCPRD_CPRD_Msk (0xffffffffUL) /*!< CPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CTMRLAT ======================================================== */
+#define QEI0_CTMRLAT_CTMRLAT_Pos (0UL) /*!< CTMRLAT (Bit 0) */
+#define QEI0_CTMRLAT_CTMRLAT_Msk (0xffffffffUL) /*!< CTMRLAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CPRDLAT ======================================================== */
+#define QEI0_CPRDLAT_CPRDLAT_Pos (0UL) /*!< CPRDLAT (Bit 0) */
+#define QEI0_CPRDLAT_CPRDLAT_Msk (0xffffffffUL) /*!< CPRDLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= IENR ========================================================== */
+#define QEI0_IENR_CDE_Pos (10UL) /*!< CDE (Bit 10) */
+#define QEI0_IENR_CDE_Msk (0x400UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PRE_Pos (9UL) /*!< PRE (Bit 9) */
+#define QEI0_IENR_PRE_Msk (0x200UL) /*!< PRE (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PIE_Pos (8UL) /*!< PIE (Bit 8) */
+#define QEI0_IENR_PIE_Msk (0x100UL) /*!< PIE (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI0_IENR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI0_IENR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI0_IENR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI0_IENR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI0_IENR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI0_IENR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_QPE_Pos (1UL) /*!< QPE (Bit 1) */
+#define QEI0_IENR_QPE_Msk (0x2UL) /*!< QPE (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI0_IENR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+/* ========================================================= STSR ========================================================== */
+#define QEI0_STSR_QDF_Pos (16UL) /*!< QDF (Bit 16) */
+#define QEI0_STSR_QDF_Msk (0x10000UL) /*!< QDF (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_QDI_Pos (15UL) /*!< QDI (Bit 15) */
+#define QEI0_STSR_QDI_Msk (0x8000UL) /*!< QDI (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_QDS_Pos (14UL) /*!< QDS (Bit 14) */
+#define QEI0_STSR_QDS_Msk (0x4000UL) /*!< QDS (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_COE_Pos (13UL) /*!< COE (Bit 13) */
+#define QEI0_STSR_COE_Msk (0x2000UL) /*!< COE (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_CDE_Pos (12UL) /*!< CDE (Bit 12) */
+#define QEI0_STSR_CDE_Msk (0x1000UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_FIS_Pos (11UL) /*!< FIS (Bit 11) */
+#define QEI0_STSR_FIS_Msk (0x800UL) /*!< FIS (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_CDS_Pos (10UL) /*!< CDS (Bit 10) */
+#define QEI0_STSR_CDS_Msk (0x400UL) /*!< CDS (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PRS_Pos (9UL) /*!< PRS (Bit 9) */
+#define QEI0_STSR_PRS_Msk (0x200UL) /*!< PRS (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PIS_Pos (8UL) /*!< PIS (Bit 8) */
+#define QEI0_STSR_PIS_Msk (0x100UL) /*!< PIS (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI0_STSR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI0_STSR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI0_STSR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI0_STSR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI0_STSR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI0_STSR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PHE_Pos (1UL) /*!< PHE (Bit 1) */
+#define QEI0_STSR_PHE_Msk (0x2UL) /*!< PHE (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI0_STSR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ QEI1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== POSCNT ========================================================= */
+#define QEI1_POSCNT_POSCNT_Pos (0UL) /*!< POSCNT (Bit 0) */
+#define QEI1_POSCNT_POSCNT_Msk (0xffffffffUL) /*!< POSCNT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSINIT ======================================================== */
+#define QEI1_POSINIT_POSINIT_Pos (0UL) /*!< POSINIT (Bit 0) */
+#define QEI1_POSINIT_POSINIT_Msk (0xffffffffUL) /*!< POSINIT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSMAX ========================================================= */
+#define QEI1_POSMAX_POSMAX_Pos (0UL) /*!< POSMAX (Bit 0) */
+#define QEI1_POSMAX_POSMAX_Msk (0xffffffffUL) /*!< POSMAX (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSCMP ========================================================= */
+#define QEI1_POSCMP_POSCMP_Pos (0UL) /*!< POSCMP (Bit 0) */
+#define QEI1_POSCMP_POSCMP_Msk (0xffffffffUL) /*!< POSCMP (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSILAT ======================================================== */
+#define QEI1_POSILAT_POSILAT_Pos (0UL) /*!< POSILAT (Bit 0) */
+#define QEI1_POSILAT_POSILAT_Msk (0xffffffffUL) /*!< POSILAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSLAT ========================================================= */
+#define QEI1_POSLAT_POSLAT_Pos (0UL) /*!< POSLAT (Bit 0) */
+#define QEI1_POSLAT_POSLAT_Msk (0xffffffffUL) /*!< POSLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UTMR ========================================================== */
+#define QEI1_UTMR_UTMR_Pos (0UL) /*!< UTMR (Bit 0) */
+#define QEI1_UTMR_UTMR_Msk (0xffffffffUL) /*!< UTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UPRD ========================================================== */
+#define QEI1_UPRD_UPRD_Pos (0UL) /*!< UPRD (Bit 0) */
+#define QEI1_UPRD_UPRD_Msk (0xffffffffUL) /*!< UPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== DECCTL ========================================================= */
+#define QEI1_DECCTL_DBC_Pos (16UL) /*!< DBC (Bit 16) */
+#define QEI1_DECCTL_DBC_Msk (0xff0000UL) /*!< DBC (Bitfield-Mask: 0xff) */
+#define QEI1_DECCTL_DCM_Pos (14UL) /*!< DCM (Bit 14) */
+#define QEI1_DECCTL_DCM_Msk (0x4000UL) /*!< DCM (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_QSRC_Pos (12UL) /*!< QSRC (Bit 12) */
+#define QEI1_DECCTL_QSRC_Msk (0x3000UL) /*!< QSRC (Bitfield-Mask: 0x03) */
+#define QEI1_DECCTL_XCR_Pos (6UL) /*!< XCR (Bit 6) */
+#define QEI1_DECCTL_XCR_Msk (0x40UL) /*!< XCR (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_IGATE_Pos (5UL) /*!< IGATE (Bit 5) */
+#define QEI1_DECCTL_IGATE_Msk (0x20UL) /*!< IGATE (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_SWAP_Pos (4UL) /*!< SWAP (Bit 4) */
+#define QEI1_DECCTL_SWAP_Msk (0x10UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_QBP_Pos (3UL) /*!< QBP (Bit 3) */
+#define QEI1_DECCTL_QBP_Msk (0x8UL) /*!< QBP (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_QAP_Pos (2UL) /*!< QAP (Bit 2) */
+#define QEI1_DECCTL_QAP_Msk (0x4UL) /*!< QAP (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_QIP_Pos (0UL) /*!< QIP (Bit 0) */
+#define QEI1_DECCTL_QIP_Msk (0x1UL) /*!< QIP (Bitfield-Mask: 0x01) */
+/* ======================================================== QEPCTL ========================================================= */
+#define QEI1_QEPCTL_PCRM_Pos (12UL) /*!< PCRM (Bit 12) */
+#define QEI1_QEPCTL_PCRM_Msk (0x3000UL) /*!< PCRM (Bitfield-Mask: 0x03) */
+#define QEI1_QEPCTL_SWI_Pos (8UL) /*!< SWI (Bit 8) */
+#define QEI1_QEPCTL_SWI_Msk (0x100UL) /*!< SWI (Bitfield-Mask: 0x01) */
+#define QEI1_QEPCTL_IEI_Pos (6UL) /*!< IEI (Bit 6) */
+#define QEI1_QEPCTL_IEI_Msk (0xc0UL) /*!< IEI (Bitfield-Mask: 0x03) */
+#define QEI1_QEPCTL_IEL_Pos (4UL) /*!< IEL (Bit 4) */
+#define QEI1_QEPCTL_IEL_Msk (0x30UL) /*!< IEL (Bitfield-Mask: 0x03) */
+#define QEI1_QEPCTL_UTE_Pos (1UL) /*!< UTE (Bit 1) */
+#define QEI1_QEPCTL_UTE_Msk (0x2UL) /*!< UTE (Bitfield-Mask: 0x01) */
+#define QEI1_QEPCTL_QPE_Pos (0UL) /*!< QPE (Bit 0) */
+#define QEI1_QEPCTL_QPE_Msk (0x1UL) /*!< QPE (Bitfield-Mask: 0x01) */
+/* ======================================================== POSCTL ========================================================= */
+#define QEI1_POSCTL_PSE_Pos (1UL) /*!< PSE (Bit 1) */
+#define QEI1_POSCTL_PSE_Msk (0x2UL) /*!< PSE (Bitfield-Mask: 0x01) */
+#define QEI1_POSCTL_CCE_Pos (0UL) /*!< CCE (Bit 0) */
+#define QEI1_POSCTL_CCE_Msk (0x1UL) /*!< CCE (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPCTL ========================================================= */
+#define QEI1_CAPCTL_UPPS_Pos (8UL) /*!< UPPS (Bit 8) */
+#define QEI1_CAPCTL_UPPS_Msk (0xf00UL) /*!< UPPS (Bitfield-Mask: 0x0f) */
+#define QEI1_CAPCTL_CCPS_Pos (4UL) /*!< CCPS (Bit 4) */
+#define QEI1_CAPCTL_CCPS_Msk (0x70UL) /*!< CCPS (Bitfield-Mask: 0x07) */
+#define QEI1_CAPCTL_CMD_Pos (1UL) /*!< CMD (Bit 1) */
+#define QEI1_CAPCTL_CMD_Msk (0x2UL) /*!< CMD (Bitfield-Mask: 0x01) */
+#define QEI1_CAPCTL_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define QEI1_CAPCTL_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= QCTMR ========================================================= */
+#define QEI1_QCTMR_CTMR_Pos (0UL) /*!< CTMR (Bit 0) */
+#define QEI1_QCTMR_CTMR_Msk (0xffffffffUL) /*!< CTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= QCPRD ========================================================= */
+#define QEI1_QCPRD_CPRD_Pos (0UL) /*!< CPRD (Bit 0) */
+#define QEI1_QCPRD_CPRD_Msk (0xffffffffUL) /*!< CPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CTMRLAT ======================================================== */
+#define QEI1_CTMRLAT_CTMRLAT_Pos (0UL) /*!< CTMRLAT (Bit 0) */
+#define QEI1_CTMRLAT_CTMRLAT_Msk (0xffffffffUL) /*!< CTMRLAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CPRDLAT ======================================================== */
+#define QEI1_CPRDLAT_CPRDLAT_Pos (0UL) /*!< CPRDLAT (Bit 0) */
+#define QEI1_CPRDLAT_CPRDLAT_Msk (0xffffffffUL) /*!< CPRDLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= IENR ========================================================== */
+#define QEI1_IENR_CDE_Pos (10UL) /*!< CDE (Bit 10) */
+#define QEI1_IENR_CDE_Msk (0x400UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PRE_Pos (9UL) /*!< PRE (Bit 9) */
+#define QEI1_IENR_PRE_Msk (0x200UL) /*!< PRE (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PIE_Pos (8UL) /*!< PIE (Bit 8) */
+#define QEI1_IENR_PIE_Msk (0x100UL) /*!< PIE (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI1_IENR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI1_IENR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI1_IENR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI1_IENR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI1_IENR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI1_IENR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_QPE_Pos (1UL) /*!< QPE (Bit 1) */
+#define QEI1_IENR_QPE_Msk (0x2UL) /*!< QPE (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI1_IENR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+/* ========================================================= STSR ========================================================== */
+#define QEI1_STSR_QDF_Pos (16UL) /*!< QDF (Bit 16) */
+#define QEI1_STSR_QDF_Msk (0x10000UL) /*!< QDF (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_QDI_Pos (15UL) /*!< QDI (Bit 15) */
+#define QEI1_STSR_QDI_Msk (0x8000UL) /*!< QDI (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_QDS_Pos (14UL) /*!< QDS (Bit 14) */
+#define QEI1_STSR_QDS_Msk (0x4000UL) /*!< QDS (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_COE_Pos (13UL) /*!< COE (Bit 13) */
+#define QEI1_STSR_COE_Msk (0x2000UL) /*!< COE (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_CDE_Pos (12UL) /*!< CDE (Bit 12) */
+#define QEI1_STSR_CDE_Msk (0x1000UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_FIS_Pos (11UL) /*!< FIS (Bit 11) */
+#define QEI1_STSR_FIS_Msk (0x800UL) /*!< FIS (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_CDS_Pos (10UL) /*!< CDS (Bit 10) */
+#define QEI1_STSR_CDS_Msk (0x400UL) /*!< CDS (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PRS_Pos (9UL) /*!< PRS (Bit 9) */
+#define QEI1_STSR_PRS_Msk (0x200UL) /*!< PRS (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PIS_Pos (8UL) /*!< PIS (Bit 8) */
+#define QEI1_STSR_PIS_Msk (0x100UL) /*!< PIS (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI1_STSR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI1_STSR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI1_STSR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI1_STSR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI1_STSR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI1_STSR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PHE_Pos (1UL) /*!< PHE (Bit 1) */
+#define QEI1_STSR_PHE_Msk (0x2UL) /*!< PHE (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI1_STSR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ QEI2 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== POSCNT ========================================================= */
+#define QEI2_POSCNT_POSCNT_Pos (0UL) /*!< POSCNT (Bit 0) */
+#define QEI2_POSCNT_POSCNT_Msk (0xffffffffUL) /*!< POSCNT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSINIT ======================================================== */
+#define QEI2_POSINIT_POSINIT_Pos (0UL) /*!< POSINIT (Bit 0) */
+#define QEI2_POSINIT_POSINIT_Msk (0xffffffffUL) /*!< POSINIT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSMAX ========================================================= */
+#define QEI2_POSMAX_POSMAX_Pos (0UL) /*!< POSMAX (Bit 0) */
+#define QEI2_POSMAX_POSMAX_Msk (0xffffffffUL) /*!< POSMAX (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSCMP ========================================================= */
+#define QEI2_POSCMP_POSCMP_Pos (0UL) /*!< POSCMP (Bit 0) */
+#define QEI2_POSCMP_POSCMP_Msk (0xffffffffUL) /*!< POSCMP (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSILAT ======================================================== */
+#define QEI2_POSILAT_POSILAT_Pos (0UL) /*!< POSILAT (Bit 0) */
+#define QEI2_POSILAT_POSILAT_Msk (0xffffffffUL) /*!< POSILAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSLAT ========================================================= */
+#define QEI2_POSLAT_POSLAT_Pos (0UL) /*!< POSLAT (Bit 0) */
+#define QEI2_POSLAT_POSLAT_Msk (0xffffffffUL) /*!< POSLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UTMR ========================================================== */
+#define QEI2_UTMR_UTMR_Pos (0UL) /*!< UTMR (Bit 0) */
+#define QEI2_UTMR_UTMR_Msk (0xffffffffUL) /*!< UTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UPRD ========================================================== */
+#define QEI2_UPRD_UPRD_Pos (0UL) /*!< UPRD (Bit 0) */
+#define QEI2_UPRD_UPRD_Msk (0xffffffffUL) /*!< UPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== DECCTL ========================================================= */
+#define QEI2_DECCTL_DBC_Pos (16UL) /*!< DBC (Bit 16) */
+#define QEI2_DECCTL_DBC_Msk (0xff0000UL) /*!< DBC (Bitfield-Mask: 0xff) */
+#define QEI2_DECCTL_DCM_Pos (14UL) /*!< DCM (Bit 14) */
+#define QEI2_DECCTL_DCM_Msk (0x4000UL) /*!< DCM (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_QSRC_Pos (12UL) /*!< QSRC (Bit 12) */
+#define QEI2_DECCTL_QSRC_Msk (0x3000UL) /*!< QSRC (Bitfield-Mask: 0x03) */
+#define QEI2_DECCTL_XCR_Pos (6UL) /*!< XCR (Bit 6) */
+#define QEI2_DECCTL_XCR_Msk (0x40UL) /*!< XCR (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_IGATE_Pos (5UL) /*!< IGATE (Bit 5) */
+#define QEI2_DECCTL_IGATE_Msk (0x20UL) /*!< IGATE (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_SWAP_Pos (4UL) /*!< SWAP (Bit 4) */
+#define QEI2_DECCTL_SWAP_Msk (0x10UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_QBP_Pos (3UL) /*!< QBP (Bit 3) */
+#define QEI2_DECCTL_QBP_Msk (0x8UL) /*!< QBP (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_QAP_Pos (2UL) /*!< QAP (Bit 2) */
+#define QEI2_DECCTL_QAP_Msk (0x4UL) /*!< QAP (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_QIP_Pos (0UL) /*!< QIP (Bit 0) */
+#define QEI2_DECCTL_QIP_Msk (0x1UL) /*!< QIP (Bitfield-Mask: 0x01) */
+/* ======================================================== QEPCTL ========================================================= */
+#define QEI2_QEPCTL_PCRM_Pos (12UL) /*!< PCRM (Bit 12) */
+#define QEI2_QEPCTL_PCRM_Msk (0x3000UL) /*!< PCRM (Bitfield-Mask: 0x03) */
+#define QEI2_QEPCTL_SWI_Pos (8UL) /*!< SWI (Bit 8) */
+#define QEI2_QEPCTL_SWI_Msk (0x100UL) /*!< SWI (Bitfield-Mask: 0x01) */
+#define QEI2_QEPCTL_IEI_Pos (6UL) /*!< IEI (Bit 6) */
+#define QEI2_QEPCTL_IEI_Msk (0xc0UL) /*!< IEI (Bitfield-Mask: 0x03) */
+#define QEI2_QEPCTL_IEL_Pos (4UL) /*!< IEL (Bit 4) */
+#define QEI2_QEPCTL_IEL_Msk (0x30UL) /*!< IEL (Bitfield-Mask: 0x03) */
+#define QEI2_QEPCTL_UTE_Pos (1UL) /*!< UTE (Bit 1) */
+#define QEI2_QEPCTL_UTE_Msk (0x2UL) /*!< UTE (Bitfield-Mask: 0x01) */
+#define QEI2_QEPCTL_QPE_Pos (0UL) /*!< QPE (Bit 0) */
+#define QEI2_QEPCTL_QPE_Msk (0x1UL) /*!< QPE (Bitfield-Mask: 0x01) */
+/* ======================================================== POSCTL ========================================================= */
+#define QEI2_POSCTL_PSE_Pos (1UL) /*!< PSE (Bit 1) */
+#define QEI2_POSCTL_PSE_Msk (0x2UL) /*!< PSE (Bitfield-Mask: 0x01) */
+#define QEI2_POSCTL_CCE_Pos (0UL) /*!< CCE (Bit 0) */
+#define QEI2_POSCTL_CCE_Msk (0x1UL) /*!< CCE (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPCTL ========================================================= */
+#define QEI2_CAPCTL_UPPS_Pos (8UL) /*!< UPPS (Bit 8) */
+#define QEI2_CAPCTL_UPPS_Msk (0xf00UL) /*!< UPPS (Bitfield-Mask: 0x0f) */
+#define QEI2_CAPCTL_CCPS_Pos (4UL) /*!< CCPS (Bit 4) */
+#define QEI2_CAPCTL_CCPS_Msk (0x70UL) /*!< CCPS (Bitfield-Mask: 0x07) */
+#define QEI2_CAPCTL_CMD_Pos (1UL) /*!< CMD (Bit 1) */
+#define QEI2_CAPCTL_CMD_Msk (0x2UL) /*!< CMD (Bitfield-Mask: 0x01) */
+#define QEI2_CAPCTL_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define QEI2_CAPCTL_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= QCTMR ========================================================= */
+#define QEI2_QCTMR_CTMR_Pos (0UL) /*!< CTMR (Bit 0) */
+#define QEI2_QCTMR_CTMR_Msk (0xffffffffUL) /*!< CTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= QCPRD ========================================================= */
+#define QEI2_QCPRD_CPRD_Pos (0UL) /*!< CPRD (Bit 0) */
+#define QEI2_QCPRD_CPRD_Msk (0xffffffffUL) /*!< CPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CTMRLAT ======================================================== */
+#define QEI2_CTMRLAT_CTMRLAT_Pos (0UL) /*!< CTMRLAT (Bit 0) */
+#define QEI2_CTMRLAT_CTMRLAT_Msk (0xffffffffUL) /*!< CTMRLAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CPRDLAT ======================================================== */
+#define QEI2_CPRDLAT_CPRDLAT_Pos (0UL) /*!< CPRDLAT (Bit 0) */
+#define QEI2_CPRDLAT_CPRDLAT_Msk (0xffffffffUL) /*!< CPRDLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= IENR ========================================================== */
+#define QEI2_IENR_CDE_Pos (10UL) /*!< CDE (Bit 10) */
+#define QEI2_IENR_CDE_Msk (0x400UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PRE_Pos (9UL) /*!< PRE (Bit 9) */
+#define QEI2_IENR_PRE_Msk (0x200UL) /*!< PRE (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PIE_Pos (8UL) /*!< PIE (Bit 8) */
+#define QEI2_IENR_PIE_Msk (0x100UL) /*!< PIE (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI2_IENR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI2_IENR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI2_IENR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI2_IENR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI2_IENR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI2_IENR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_QPE_Pos (1UL) /*!< QPE (Bit 1) */
+#define QEI2_IENR_QPE_Msk (0x2UL) /*!< QPE (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI2_IENR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+/* ========================================================= STSR ========================================================== */
+#define QEI2_STSR_QDF_Pos (16UL) /*!< QDF (Bit 16) */
+#define QEI2_STSR_QDF_Msk (0x10000UL) /*!< QDF (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_QDI_Pos (15UL) /*!< QDI (Bit 15) */
+#define QEI2_STSR_QDI_Msk (0x8000UL) /*!< QDI (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_QDS_Pos (14UL) /*!< QDS (Bit 14) */
+#define QEI2_STSR_QDS_Msk (0x4000UL) /*!< QDS (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_COE_Pos (13UL) /*!< COE (Bit 13) */
+#define QEI2_STSR_COE_Msk (0x2000UL) /*!< COE (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_CDE_Pos (12UL) /*!< CDE (Bit 12) */
+#define QEI2_STSR_CDE_Msk (0x1000UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_FIS_Pos (11UL) /*!< FIS (Bit 11) */
+#define QEI2_STSR_FIS_Msk (0x800UL) /*!< FIS (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_CDS_Pos (10UL) /*!< CDS (Bit 10) */
+#define QEI2_STSR_CDS_Msk (0x400UL) /*!< CDS (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PRS_Pos (9UL) /*!< PRS (Bit 9) */
+#define QEI2_STSR_PRS_Msk (0x200UL) /*!< PRS (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PIS_Pos (8UL) /*!< PIS (Bit 8) */
+#define QEI2_STSR_PIS_Msk (0x100UL) /*!< PIS (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI2_STSR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI2_STSR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI2_STSR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI2_STSR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI2_STSR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI2_STSR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PHE_Pos (1UL) /*!< PHE (Bit 1) */
+#define QEI2_STSR_PHE_Msk (0x2UL) /*!< PHE (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI2_STSR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ PDM0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define PDM0_ENABLE_INMOD_Pos (1UL) /*!< INMOD (Bit 1) */
+#define PDM0_ENABLE_INMOD_Msk (0x2UL) /*!< INMOD (Bitfield-Mask: 0x01) */
+#define PDM0_ENABLE_PDMEN_Pos (0UL) /*!< PDMEN (Bit 0) */
+#define PDM0_ENABLE_PDMEN_Msk (0x1UL) /*!< PDMEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define PDM0_CTRL_RXDLY_Pos (28UL) /*!< RXDLY (Bit 28) */
+#define PDM0_CTRL_RXDLY_Msk (0x70000000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define PDM0_CTRL_DMAEN_Pos (19UL) /*!< DMAEN (Bit 19) */
+#define PDM0_CTRL_DMAEN_Msk (0x80000UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+#define PDM0_CTRL_SAMPMODE_Pos (18UL) /*!< SAMPMODE (Bit 18) */
+#define PDM0_CTRL_SAMPMODE_Msk (0x40000UL) /*!< SAMPMODE (Bitfield-Mask: 0x01) */
+#define PDM0_CTRL_SCPOL_Pos (17UL) /*!< SCPOL (Bit 17) */
+#define PDM0_CTRL_SCPOL_Msk (0x20000UL) /*!< SCPOL (Bitfield-Mask: 0x01) */
+#define PDM0_CTRL_MSTEN_Pos (16UL) /*!< MSTEN (Bit 16) */
+#define PDM0_CTRL_MSTEN_Msk (0x10000UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define PDM0_CTRL_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define PDM0_CTRL_BAUD_Msk (0xfffUL) /*!< BAUD (Bitfield-Mask: 0xfff) */
+/* ========================================================= DFCR ========================================================== */
+#define PDM0_DFCR_SHIFT_Pos (16UL) /*!< SHIFT (Bit 16) */
+#define PDM0_DFCR_SHIFT_Msk (0xf0000UL) /*!< SHIFT (Bitfield-Mask: 0x0f) */
+#define PDM0_DFCR_SDSYNCEN_Pos (14UL) /*!< SDSYNCEN (Bit 14) */
+#define PDM0_DFCR_SDSYNCEN_Msk (0x4000UL) /*!< SDSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM0_DFCR_DFDR_Pos (13UL) /*!< DFDR (Bit 13) */
+#define PDM0_DFCR_DFDR_Msk (0x2000UL) /*!< DFDR (Bitfield-Mask: 0x01) */
+#define PDM0_DFCR_DFBYPASS_Pos (12UL) /*!< DFBYPASS (Bit 12) */
+#define PDM0_DFCR_DFBYPASS_Msk (0x1000UL) /*!< DFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM0_DFCR_DFSST_Pos (9UL) /*!< DFSST (Bit 9) */
+#define PDM0_DFCR_DFSST_Msk (0xe00UL) /*!< DFSST (Bitfield-Mask: 0x07) */
+#define PDM0_DFCR_DFEN_Pos (8UL) /*!< DFEN (Bit 8) */
+#define PDM0_DFCR_DFEN_Msk (0x100UL) /*!< DFEN (Bitfield-Mask: 0x01) */
+#define PDM0_DFCR_DOSR_Pos (0UL) /*!< DOSR (Bit 0) */
+#define PDM0_DFCR_DOSR_Msk (0xffUL) /*!< DOSR (Bitfield-Mask: 0xff) */
+/* ========================================================= CFCR ========================================================== */
+#define PDM0_CFCR_COMPSEL_Pos (10UL) /*!< COMPSEL (Bit 10) */
+#define PDM0_CFCR_COMPSEL_Msk (0x400UL) /*!< COMPSEL (Bitfield-Mask: 0x01) */
+#define PDM0_CFCR_CFBYPASS_Pos (9UL) /*!< CFBYPASS (Bit 9) */
+#define PDM0_CFCR_CFBYPASS_Msk (0x200UL) /*!< CFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM0_CFCR_CFSST_Pos (6UL) /*!< CFSST (Bit 6) */
+#define PDM0_CFCR_CFSST_Msk (0x1c0UL) /*!< CFSST (Bitfield-Mask: 0x07) */
+#define PDM0_CFCR_CFEN_Pos (5UL) /*!< CFEN (Bit 5) */
+#define PDM0_CFCR_CFEN_Msk (0x20UL) /*!< CFEN (Bitfield-Mask: 0x01) */
+#define PDM0_CFCR_COSR_Pos (0UL) /*!< COSR (Bit 0) */
+#define PDM0_CFCR_COSR_Msk (0x1fUL) /*!< COSR (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCSR ========================================================== */
+#define PDM0_FCSR_FIFORST_Pos (18UL) /*!< FIFORST (Bit 18) */
+#define PDM0_FCSR_FIFORST_Msk (0x40000UL) /*!< FIFORST (Bitfield-Mask: 0x01) */
+#define PDM0_FCSR_FIFOFULL_Pos (17UL) /*!< FIFOFULL (Bit 17) */
+#define PDM0_FCSR_FIFOFULL_Msk (0x20000UL) /*!< FIFOFULL (Bitfield-Mask: 0x01) */
+#define PDM0_FCSR_FIFOEMPTY_Pos (16UL) /*!< FIFOEMPTY (Bit 16) */
+#define PDM0_FCSR_FIFOEMPTY_Msk (0x10000UL) /*!< FIFOEMPTY (Bitfield-Mask: 0x01) */
+#define PDM0_FCSR_PDMFST_Pos (8UL) /*!< PDMFST (Bit 8) */
+#define PDM0_FCSR_PDMFST_Msk (0xf00UL) /*!< PDMFST (Bitfield-Mask: 0x0f) */
+#define PDM0_FCSR_PDMFIL_Pos (0UL) /*!< PDMFIL (Bit 0) */
+#define PDM0_FCSR_PDMFIL_Msk (0x7UL) /*!< PDMFIL (Bitfield-Mask: 0x07) */
+/* ========================================================== IER ========================================================== */
+#define PDM0_IER_FIUIE_Pos (7UL) /*!< FIUIE (Bit 7) */
+#define PDM0_IER_FIUIE_Msk (0x80UL) /*!< FIUIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_CTIE_Pos (6UL) /*!< CTIE (Bit 6) */
+#define PDM0_IER_CTIE_Msk (0x40UL) /*!< CTIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_FFIE_Pos (5UL) /*!< FFIE (Bit 5) */
+#define PDM0_IER_FFIE_Msk (0x20UL) /*!< FFIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_FIOIE_Pos (4UL) /*!< FIOIE (Bit 4) */
+#define PDM0_IER_FIOIE_Msk (0x10UL) /*!< FIOIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_DOFIE_Pos (3UL) /*!< DOFIE (Bit 3) */
+#define PDM0_IER_DOFIE_Msk (0x8UL) /*!< DOFIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_DFIE_Pos (2UL) /*!< DFIE (Bit 2) */
+#define PDM0_IER_DFIE_Msk (0x4UL) /*!< DFIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_LLIE_Pos (1UL) /*!< LLIE (Bit 1) */
+#define PDM0_IER_LLIE_Msk (0x2UL) /*!< LLIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_HLIE_Pos (0UL) /*!< HLIE (Bit 0) */
+#define PDM0_IER_HLIE_Msk (0x1UL) /*!< HLIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define PDM0_ISR_FIUINTR_Pos (7UL) /*!< FIUINTR (Bit 7) */
+#define PDM0_ISR_FIUINTR_Msk (0x80UL) /*!< FIUINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_CTOINTR_Pos (6UL) /*!< CTOINTR (Bit 6) */
+#define PDM0_ISR_CTOINTR_Msk (0x40UL) /*!< CTOINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_FIFINTR_Pos (5UL) /*!< FIFINTR (Bit 5) */
+#define PDM0_ISR_FIFINTR_Msk (0x20UL) /*!< FIFINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_FIOINTR_Pos (4UL) /*!< FIOINTR (Bit 4) */
+#define PDM0_ISR_FIOINTR_Msk (0x10UL) /*!< FIOINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_DOINTR_Pos (3UL) /*!< DOINTR (Bit 3) */
+#define PDM0_ISR_DOINTR_Msk (0x8UL) /*!< DOINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_DFINTR_Pos (2UL) /*!< DFINTR (Bit 2) */
+#define PDM0_ISR_DFINTR_Msk (0x4UL) /*!< DFINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_LLINTR_Pos (1UL) /*!< LLINTR (Bit 1) */
+#define PDM0_ISR_LLINTR_Msk (0x2UL) /*!< LLINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_HLINTR_Pos (0UL) /*!< HLINTR (Bit 0) */
+#define PDM0_ISR_HLINTR_Msk (0x1UL) /*!< HLINTR (Bitfield-Mask: 0x01) */
+/* ========================================================= DDAT ========================================================== */
+#define PDM0_DDAT_DDAT_Pos (0UL) /*!< DDAT (Bit 0) */
+#define PDM0_DDAT_DDAT_Msk (0xffffffUL) /*!< DDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CDAT ========================================================== */
+#define PDM0_CDAT_CDAT_Pos (0UL) /*!< CDAT (Bit 0) */
+#define PDM0_CDAT_CDAT_Msk (0xffffUL) /*!< CDAT (Bitfield-Mask: 0xffff) */
+/* ========================================================= FDAT ========================================================== */
+#define PDM0_FDAT_FDAT_Pos (0UL) /*!< FDAT (Bit 0) */
+#define PDM0_FDAT_FDAT_Msk (0xffffffUL) /*!< FDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CMPH ========================================================== */
+#define PDM0_CMPH_HLT_Pos (0UL) /*!< HLT (Bit 0) */
+#define PDM0_CMPH_HLT_Msk (0xffffUL) /*!< HLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPL ========================================================== */
+#define PDM0_CMPL_LLT_Pos (0UL) /*!< LLT (Bit 0) */
+#define PDM0_CMPL_LLT_Msk (0xffffUL) /*!< LLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CLKTO ========================================================= */
+#define PDM0_CLKTO_CLKTOT_Pos (0UL) /*!< CLKTOT (Bit 0) */
+#define PDM0_CLKTO_CLKTOT_Msk (0x3ffffUL) /*!< CLKTOT (Bitfield-Mask: 0x3ffff) */
+/* ======================================================== SDSYNC ========================================================= */
+#define PDM0_SDSYNC_WTSCLREN_Pos (10UL) /*!< WTSCLREN (Bit 10) */
+#define PDM0_SDSYNC_WTSCLREN_Msk (0x400UL) /*!< WTSCLREN (Bitfield-Mask: 0x01) */
+#define PDM0_SDSYNC_FFSYNCCLREN_Pos (9UL) /*!< FFSYNCCLREN (Bit 9) */
+#define PDM0_SDSYNC_FFSYNCCLREN_Msk (0x200UL) /*!< FFSYNCCLREN (Bitfield-Mask: 0x01) */
+#define PDM0_SDSYNC_WTSYNCLR_Pos (8UL) /*!< WTSYNCLR (Bit 8) */
+#define PDM0_SDSYNC_WTSYNCLR_Msk (0x100UL) /*!< WTSYNCLR (Bitfield-Mask: 0x01) */
+#define PDM0_SDSYNC_WTSYNFLG_Pos (7UL) /*!< WTSYNFLG (Bit 7) */
+#define PDM0_SDSYNC_WTSYNFLG_Msk (0x80UL) /*!< WTSYNFLG (Bitfield-Mask: 0x01) */
+#define PDM0_SDSYNC_WTSYNCEN_Pos (6UL) /*!< WTSYNCEN (Bit 6) */
+#define PDM0_SDSYNC_WTSYNCEN_Msk (0x40UL) /*!< WTSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM0_SDSYNC_SYNCSEL_Pos (0UL) /*!< SYNCSEL (Bit 0) */
+#define PDM0_SDSYNC_SYNCSEL_Msk (0x3fUL) /*!< SYNCSEL (Bitfield-Mask: 0x3f) */
+/* ========================================================= IDAT ========================================================== */
+#define PDM0_IDAT_IDAT_Pos (0UL) /*!< IDAT (Bit 0) */
+#define PDM0_IDAT_IDAT_Msk (0xffffUL) /*!< IDAT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ PDM1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define PDM1_ENABLE_INMOD_Pos (1UL) /*!< INMOD (Bit 1) */
+#define PDM1_ENABLE_INMOD_Msk (0x2UL) /*!< INMOD (Bitfield-Mask: 0x01) */
+#define PDM1_ENABLE_PDMEN_Pos (0UL) /*!< PDMEN (Bit 0) */
+#define PDM1_ENABLE_PDMEN_Msk (0x1UL) /*!< PDMEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define PDM1_CTRL_RXDLY_Pos (28UL) /*!< RXDLY (Bit 28) */
+#define PDM1_CTRL_RXDLY_Msk (0x70000000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define PDM1_CTRL_DMAEN_Pos (19UL) /*!< DMAEN (Bit 19) */
+#define PDM1_CTRL_DMAEN_Msk (0x80000UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+#define PDM1_CTRL_SAMPMODE_Pos (18UL) /*!< SAMPMODE (Bit 18) */
+#define PDM1_CTRL_SAMPMODE_Msk (0x40000UL) /*!< SAMPMODE (Bitfield-Mask: 0x01) */
+#define PDM1_CTRL_SCPOL_Pos (17UL) /*!< SCPOL (Bit 17) */
+#define PDM1_CTRL_SCPOL_Msk (0x20000UL) /*!< SCPOL (Bitfield-Mask: 0x01) */
+#define PDM1_CTRL_MSTEN_Pos (16UL) /*!< MSTEN (Bit 16) */
+#define PDM1_CTRL_MSTEN_Msk (0x10000UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define PDM1_CTRL_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define PDM1_CTRL_BAUD_Msk (0xfffUL) /*!< BAUD (Bitfield-Mask: 0xfff) */
+/* ========================================================= DFCR ========================================================== */
+#define PDM1_DFCR_SHIFT_Pos (16UL) /*!< SHIFT (Bit 16) */
+#define PDM1_DFCR_SHIFT_Msk (0xf0000UL) /*!< SHIFT (Bitfield-Mask: 0x0f) */
+#define PDM1_DFCR_SDSYNCEN_Pos (14UL) /*!< SDSYNCEN (Bit 14) */
+#define PDM1_DFCR_SDSYNCEN_Msk (0x4000UL) /*!< SDSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM1_DFCR_DFDR_Pos (13UL) /*!< DFDR (Bit 13) */
+#define PDM1_DFCR_DFDR_Msk (0x2000UL) /*!< DFDR (Bitfield-Mask: 0x01) */
+#define PDM1_DFCR_DFBYPASS_Pos (12UL) /*!< DFBYPASS (Bit 12) */
+#define PDM1_DFCR_DFBYPASS_Msk (0x1000UL) /*!< DFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM1_DFCR_DFSST_Pos (9UL) /*!< DFSST (Bit 9) */
+#define PDM1_DFCR_DFSST_Msk (0xe00UL) /*!< DFSST (Bitfield-Mask: 0x07) */
+#define PDM1_DFCR_DFEN_Pos (8UL) /*!< DFEN (Bit 8) */
+#define PDM1_DFCR_DFEN_Msk (0x100UL) /*!< DFEN (Bitfield-Mask: 0x01) */
+#define PDM1_DFCR_DOSR_Pos (0UL) /*!< DOSR (Bit 0) */
+#define PDM1_DFCR_DOSR_Msk (0xffUL) /*!< DOSR (Bitfield-Mask: 0xff) */
+/* ========================================================= CFCR ========================================================== */
+#define PDM1_CFCR_COMPSEL_Pos (10UL) /*!< COMPSEL (Bit 10) */
+#define PDM1_CFCR_COMPSEL_Msk (0x400UL) /*!< COMPSEL (Bitfield-Mask: 0x01) */
+#define PDM1_CFCR_CFBYPASS_Pos (9UL) /*!< CFBYPASS (Bit 9) */
+#define PDM1_CFCR_CFBYPASS_Msk (0x200UL) /*!< CFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM1_CFCR_CFSST_Pos (6UL) /*!< CFSST (Bit 6) */
+#define PDM1_CFCR_CFSST_Msk (0x1c0UL) /*!< CFSST (Bitfield-Mask: 0x07) */
+#define PDM1_CFCR_CFEN_Pos (5UL) /*!< CFEN (Bit 5) */
+#define PDM1_CFCR_CFEN_Msk (0x20UL) /*!< CFEN (Bitfield-Mask: 0x01) */
+#define PDM1_CFCR_COSR_Pos (0UL) /*!< COSR (Bit 0) */
+#define PDM1_CFCR_COSR_Msk (0x1fUL) /*!< COSR (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCSR ========================================================== */
+#define PDM1_FCSR_FIFORST_Pos (18UL) /*!< FIFORST (Bit 18) */
+#define PDM1_FCSR_FIFORST_Msk (0x40000UL) /*!< FIFORST (Bitfield-Mask: 0x01) */
+#define PDM1_FCSR_FIFOFULL_Pos (17UL) /*!< FIFOFULL (Bit 17) */
+#define PDM1_FCSR_FIFOFULL_Msk (0x20000UL) /*!< FIFOFULL (Bitfield-Mask: 0x01) */
+#define PDM1_FCSR_FIFOEMPTY_Pos (16UL) /*!< FIFOEMPTY (Bit 16) */
+#define PDM1_FCSR_FIFOEMPTY_Msk (0x10000UL) /*!< FIFOEMPTY (Bitfield-Mask: 0x01) */
+#define PDM1_FCSR_PDMFST_Pos (8UL) /*!< PDMFST (Bit 8) */
+#define PDM1_FCSR_PDMFST_Msk (0xf00UL) /*!< PDMFST (Bitfield-Mask: 0x0f) */
+#define PDM1_FCSR_PDMFIL_Pos (0UL) /*!< PDMFIL (Bit 0) */
+#define PDM1_FCSR_PDMFIL_Msk (0x7UL) /*!< PDMFIL (Bitfield-Mask: 0x07) */
+/* ========================================================== IER ========================================================== */
+#define PDM1_IER_FIUIE_Pos (7UL) /*!< FIUIE (Bit 7) */
+#define PDM1_IER_FIUIE_Msk (0x80UL) /*!< FIUIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_CTIE_Pos (6UL) /*!< CTIE (Bit 6) */
+#define PDM1_IER_CTIE_Msk (0x40UL) /*!< CTIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_FFIE_Pos (5UL) /*!< FFIE (Bit 5) */
+#define PDM1_IER_FFIE_Msk (0x20UL) /*!< FFIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_FIOIE_Pos (4UL) /*!< FIOIE (Bit 4) */
+#define PDM1_IER_FIOIE_Msk (0x10UL) /*!< FIOIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_DOFIE_Pos (3UL) /*!< DOFIE (Bit 3) */
+#define PDM1_IER_DOFIE_Msk (0x8UL) /*!< DOFIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_DFIE_Pos (2UL) /*!< DFIE (Bit 2) */
+#define PDM1_IER_DFIE_Msk (0x4UL) /*!< DFIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_LLIE_Pos (1UL) /*!< LLIE (Bit 1) */
+#define PDM1_IER_LLIE_Msk (0x2UL) /*!< LLIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_HLIE_Pos (0UL) /*!< HLIE (Bit 0) */
+#define PDM1_IER_HLIE_Msk (0x1UL) /*!< HLIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define PDM1_ISR_FIUINTR_Pos (7UL) /*!< FIUINTR (Bit 7) */
+#define PDM1_ISR_FIUINTR_Msk (0x80UL) /*!< FIUINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_CTOINTR_Pos (6UL) /*!< CTOINTR (Bit 6) */
+#define PDM1_ISR_CTOINTR_Msk (0x40UL) /*!< CTOINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_FIFINTR_Pos (5UL) /*!< FIFINTR (Bit 5) */
+#define PDM1_ISR_FIFINTR_Msk (0x20UL) /*!< FIFINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_FIOINTR_Pos (4UL) /*!< FIOINTR (Bit 4) */
+#define PDM1_ISR_FIOINTR_Msk (0x10UL) /*!< FIOINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_DOINTR_Pos (3UL) /*!< DOINTR (Bit 3) */
+#define PDM1_ISR_DOINTR_Msk (0x8UL) /*!< DOINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_DFINTR_Pos (2UL) /*!< DFINTR (Bit 2) */
+#define PDM1_ISR_DFINTR_Msk (0x4UL) /*!< DFINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_LLINTR_Pos (1UL) /*!< LLINTR (Bit 1) */
+#define PDM1_ISR_LLINTR_Msk (0x2UL) /*!< LLINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_HLINTR_Pos (0UL) /*!< HLINTR (Bit 0) */
+#define PDM1_ISR_HLINTR_Msk (0x1UL) /*!< HLINTR (Bitfield-Mask: 0x01) */
+/* ========================================================= DDAT ========================================================== */
+#define PDM1_DDAT_DDAT_Pos (0UL) /*!< DDAT (Bit 0) */
+#define PDM1_DDAT_DDAT_Msk (0xffffffUL) /*!< DDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CDAT ========================================================== */
+#define PDM1_CDAT_CDAT_Pos (0UL) /*!< CDAT (Bit 0) */
+#define PDM1_CDAT_CDAT_Msk (0xffffUL) /*!< CDAT (Bitfield-Mask: 0xffff) */
+/* ========================================================= FDAT ========================================================== */
+#define PDM1_FDAT_FDAT_Pos (0UL) /*!< FDAT (Bit 0) */
+#define PDM1_FDAT_FDAT_Msk (0xffffffUL) /*!< FDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CMPH ========================================================== */
+#define PDM1_CMPH_HLT_Pos (0UL) /*!< HLT (Bit 0) */
+#define PDM1_CMPH_HLT_Msk (0xffffUL) /*!< HLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPL ========================================================== */
+#define PDM1_CMPL_LLT_Pos (0UL) /*!< LLT (Bit 0) */
+#define PDM1_CMPL_LLT_Msk (0xffffUL) /*!< LLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CLKTO ========================================================= */
+#define PDM1_CLKTO_CLKTOT_Pos (0UL) /*!< CLKTOT (Bit 0) */
+#define PDM1_CLKTO_CLKTOT_Msk (0x3ffffUL) /*!< CLKTOT (Bitfield-Mask: 0x3ffff) */
+/* ======================================================== SDSYNC ========================================================= */
+#define PDM1_SDSYNC_WTSCLREN_Pos (10UL) /*!< WTSCLREN (Bit 10) */
+#define PDM1_SDSYNC_WTSCLREN_Msk (0x400UL) /*!< WTSCLREN (Bitfield-Mask: 0x01) */
+#define PDM1_SDSYNC_FFSYNCCLREN_Pos (9UL) /*!< FFSYNCCLREN (Bit 9) */
+#define PDM1_SDSYNC_FFSYNCCLREN_Msk (0x200UL) /*!< FFSYNCCLREN (Bitfield-Mask: 0x01) */
+#define PDM1_SDSYNC_WTSYNCLR_Pos (8UL) /*!< WTSYNCLR (Bit 8) */
+#define PDM1_SDSYNC_WTSYNCLR_Msk (0x100UL) /*!< WTSYNCLR (Bitfield-Mask: 0x01) */
+#define PDM1_SDSYNC_WTSYNFLG_Pos (7UL) /*!< WTSYNFLG (Bit 7) */
+#define PDM1_SDSYNC_WTSYNFLG_Msk (0x80UL) /*!< WTSYNFLG (Bitfield-Mask: 0x01) */
+#define PDM1_SDSYNC_WTSYNCEN_Pos (6UL) /*!< WTSYNCEN (Bit 6) */
+#define PDM1_SDSYNC_WTSYNCEN_Msk (0x40UL) /*!< WTSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM1_SDSYNC_SYNCSEL_Pos (0UL) /*!< SYNCSEL (Bit 0) */
+#define PDM1_SDSYNC_SYNCSEL_Msk (0x3fUL) /*!< SYNCSEL (Bitfield-Mask: 0x3f) */
+/* ========================================================= IDAT ========================================================== */
+#define PDM1_IDAT_IDAT_Pos (0UL) /*!< IDAT (Bit 0) */
+#define PDM1_IDAT_IDAT_Msk (0xffffUL) /*!< IDAT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ PDM2 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define PDM2_ENABLE_INMOD_Pos (1UL) /*!< INMOD (Bit 1) */
+#define PDM2_ENABLE_INMOD_Msk (0x2UL) /*!< INMOD (Bitfield-Mask: 0x01) */
+#define PDM2_ENABLE_PDMEN_Pos (0UL) /*!< PDMEN (Bit 0) */
+#define PDM2_ENABLE_PDMEN_Msk (0x1UL) /*!< PDMEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define PDM2_CTRL_RXDLY_Pos (28UL) /*!< RXDLY (Bit 28) */
+#define PDM2_CTRL_RXDLY_Msk (0x70000000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define PDM2_CTRL_DMAEN_Pos (19UL) /*!< DMAEN (Bit 19) */
+#define PDM2_CTRL_DMAEN_Msk (0x80000UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+#define PDM2_CTRL_SAMPMODE_Pos (18UL) /*!< SAMPMODE (Bit 18) */
+#define PDM2_CTRL_SAMPMODE_Msk (0x40000UL) /*!< SAMPMODE (Bitfield-Mask: 0x01) */
+#define PDM2_CTRL_SCPOL_Pos (17UL) /*!< SCPOL (Bit 17) */
+#define PDM2_CTRL_SCPOL_Msk (0x20000UL) /*!< SCPOL (Bitfield-Mask: 0x01) */
+#define PDM2_CTRL_MSTEN_Pos (16UL) /*!< MSTEN (Bit 16) */
+#define PDM2_CTRL_MSTEN_Msk (0x10000UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define PDM2_CTRL_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define PDM2_CTRL_BAUD_Msk (0xfffUL) /*!< BAUD (Bitfield-Mask: 0xfff) */
+/* ========================================================= DFCR ========================================================== */
+#define PDM2_DFCR_SHIFT_Pos (16UL) /*!< SHIFT (Bit 16) */
+#define PDM2_DFCR_SHIFT_Msk (0xf0000UL) /*!< SHIFT (Bitfield-Mask: 0x0f) */
+#define PDM2_DFCR_SDSYNCEN_Pos (14UL) /*!< SDSYNCEN (Bit 14) */
+#define PDM2_DFCR_SDSYNCEN_Msk (0x4000UL) /*!< SDSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM2_DFCR_DFDR_Pos (13UL) /*!< DFDR (Bit 13) */
+#define PDM2_DFCR_DFDR_Msk (0x2000UL) /*!< DFDR (Bitfield-Mask: 0x01) */
+#define PDM2_DFCR_DFBYPASS_Pos (12UL) /*!< DFBYPASS (Bit 12) */
+#define PDM2_DFCR_DFBYPASS_Msk (0x1000UL) /*!< DFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM2_DFCR_DFSST_Pos (9UL) /*!< DFSST (Bit 9) */
+#define PDM2_DFCR_DFSST_Msk (0xe00UL) /*!< DFSST (Bitfield-Mask: 0x07) */
+#define PDM2_DFCR_DFEN_Pos (8UL) /*!< DFEN (Bit 8) */
+#define PDM2_DFCR_DFEN_Msk (0x100UL) /*!< DFEN (Bitfield-Mask: 0x01) */
+#define PDM2_DFCR_DOSR_Pos (0UL) /*!< DOSR (Bit 0) */
+#define PDM2_DFCR_DOSR_Msk (0xffUL) /*!< DOSR (Bitfield-Mask: 0xff) */
+/* ========================================================= CFCR ========================================================== */
+#define PDM2_CFCR_COMPSEL_Pos (10UL) /*!< COMPSEL (Bit 10) */
+#define PDM2_CFCR_COMPSEL_Msk (0x400UL) /*!< COMPSEL (Bitfield-Mask: 0x01) */
+#define PDM2_CFCR_CFBYPASS_Pos (9UL) /*!< CFBYPASS (Bit 9) */
+#define PDM2_CFCR_CFBYPASS_Msk (0x200UL) /*!< CFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM2_CFCR_CFSST_Pos (6UL) /*!< CFSST (Bit 6) */
+#define PDM2_CFCR_CFSST_Msk (0x1c0UL) /*!< CFSST (Bitfield-Mask: 0x07) */
+#define PDM2_CFCR_CFEN_Pos (5UL) /*!< CFEN (Bit 5) */
+#define PDM2_CFCR_CFEN_Msk (0x20UL) /*!< CFEN (Bitfield-Mask: 0x01) */
+#define PDM2_CFCR_COSR_Pos (0UL) /*!< COSR (Bit 0) */
+#define PDM2_CFCR_COSR_Msk (0x1fUL) /*!< COSR (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCSR ========================================================== */
+#define PDM2_FCSR_FIFORST_Pos (18UL) /*!< FIFORST (Bit 18) */
+#define PDM2_FCSR_FIFORST_Msk (0x40000UL) /*!< FIFORST (Bitfield-Mask: 0x01) */
+#define PDM2_FCSR_FIFOFULL_Pos (17UL) /*!< FIFOFULL (Bit 17) */
+#define PDM2_FCSR_FIFOFULL_Msk (0x20000UL) /*!< FIFOFULL (Bitfield-Mask: 0x01) */
+#define PDM2_FCSR_FIFOEMPTY_Pos (16UL) /*!< FIFOEMPTY (Bit 16) */
+#define PDM2_FCSR_FIFOEMPTY_Msk (0x10000UL) /*!< FIFOEMPTY (Bitfield-Mask: 0x01) */
+#define PDM2_FCSR_PDMFST_Pos (8UL) /*!< PDMFST (Bit 8) */
+#define PDM2_FCSR_PDMFST_Msk (0xf00UL) /*!< PDMFST (Bitfield-Mask: 0x0f) */
+#define PDM2_FCSR_PDMFIL_Pos (0UL) /*!< PDMFIL (Bit 0) */
+#define PDM2_FCSR_PDMFIL_Msk (0x7UL) /*!< PDMFIL (Bitfield-Mask: 0x07) */
+/* ========================================================== IER ========================================================== */
+#define PDM2_IER_FIUIE_Pos (7UL) /*!< FIUIE (Bit 7) */
+#define PDM2_IER_FIUIE_Msk (0x80UL) /*!< FIUIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_CTIE_Pos (6UL) /*!< CTIE (Bit 6) */
+#define PDM2_IER_CTIE_Msk (0x40UL) /*!< CTIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_FFIE_Pos (5UL) /*!< FFIE (Bit 5) */
+#define PDM2_IER_FFIE_Msk (0x20UL) /*!< FFIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_FIOIE_Pos (4UL) /*!< FIOIE (Bit 4) */
+#define PDM2_IER_FIOIE_Msk (0x10UL) /*!< FIOIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_DOFIE_Pos (3UL) /*!< DOFIE (Bit 3) */
+#define PDM2_IER_DOFIE_Msk (0x8UL) /*!< DOFIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_DFIE_Pos (2UL) /*!< DFIE (Bit 2) */
+#define PDM2_IER_DFIE_Msk (0x4UL) /*!< DFIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_LLIE_Pos (1UL) /*!< LLIE (Bit 1) */
+#define PDM2_IER_LLIE_Msk (0x2UL) /*!< LLIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_HLIE_Pos (0UL) /*!< HLIE (Bit 0) */
+#define PDM2_IER_HLIE_Msk (0x1UL) /*!< HLIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define PDM2_ISR_FIUINTR_Pos (7UL) /*!< FIUINTR (Bit 7) */
+#define PDM2_ISR_FIUINTR_Msk (0x80UL) /*!< FIUINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_CTOINTR_Pos (6UL) /*!< CTOINTR (Bit 6) */
+#define PDM2_ISR_CTOINTR_Msk (0x40UL) /*!< CTOINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_FIFINTR_Pos (5UL) /*!< FIFINTR (Bit 5) */
+#define PDM2_ISR_FIFINTR_Msk (0x20UL) /*!< FIFINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_FIOINTR_Pos (4UL) /*!< FIOINTR (Bit 4) */
+#define PDM2_ISR_FIOINTR_Msk (0x10UL) /*!< FIOINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_DOINTR_Pos (3UL) /*!< DOINTR (Bit 3) */
+#define PDM2_ISR_DOINTR_Msk (0x8UL) /*!< DOINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_DFINTR_Pos (2UL) /*!< DFINTR (Bit 2) */
+#define PDM2_ISR_DFINTR_Msk (0x4UL) /*!< DFINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_LLINTR_Pos (1UL) /*!< LLINTR (Bit 1) */
+#define PDM2_ISR_LLINTR_Msk (0x2UL) /*!< LLINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_HLINTR_Pos (0UL) /*!< HLINTR (Bit 0) */
+#define PDM2_ISR_HLINTR_Msk (0x1UL) /*!< HLINTR (Bitfield-Mask: 0x01) */
+/* ========================================================= DDAT ========================================================== */
+#define PDM2_DDAT_DDAT_Pos (0UL) /*!< DDAT (Bit 0) */
+#define PDM2_DDAT_DDAT_Msk (0xffffffUL) /*!< DDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CDAT ========================================================== */
+#define PDM2_CDAT_CDAT_Pos (0UL) /*!< CDAT (Bit 0) */
+#define PDM2_CDAT_CDAT_Msk (0xffffUL) /*!< CDAT (Bitfield-Mask: 0xffff) */
+/* ========================================================= FDAT ========================================================== */
+#define PDM2_FDAT_FDAT_Pos (0UL) /*!< FDAT (Bit 0) */
+#define PDM2_FDAT_FDAT_Msk (0xffffffUL) /*!< FDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CMPH ========================================================== */
+#define PDM2_CMPH_HLT_Pos (0UL) /*!< HLT (Bit 0) */
+#define PDM2_CMPH_HLT_Msk (0xffffUL) /*!< HLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPL ========================================================== */
+#define PDM2_CMPL_LLT_Pos (0UL) /*!< LLT (Bit 0) */
+#define PDM2_CMPL_LLT_Msk (0xffffUL) /*!< LLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CLKTO ========================================================= */
+#define PDM2_CLKTO_CLKTOT_Pos (0UL) /*!< CLKTOT (Bit 0) */
+#define PDM2_CLKTO_CLKTOT_Msk (0x3ffffUL) /*!< CLKTOT (Bitfield-Mask: 0x3ffff) */
+/* ======================================================== SDSYNC ========================================================= */
+#define PDM2_SDSYNC_WTSCLREN_Pos (10UL) /*!< WTSCLREN (Bit 10) */
+#define PDM2_SDSYNC_WTSCLREN_Msk (0x400UL) /*!< WTSCLREN (Bitfield-Mask: 0x01) */
+#define PDM2_SDSYNC_FFSYNCCLREN_Pos (9UL) /*!< FFSYNCCLREN (Bit 9) */
+#define PDM2_SDSYNC_FFSYNCCLREN_Msk (0x200UL) /*!< FFSYNCCLREN (Bitfield-Mask: 0x01) */
+#define PDM2_SDSYNC_WTSYNCLR_Pos (8UL) /*!< WTSYNCLR (Bit 8) */
+#define PDM2_SDSYNC_WTSYNCLR_Msk (0x100UL) /*!< WTSYNCLR (Bitfield-Mask: 0x01) */
+#define PDM2_SDSYNC_WTSYNFLG_Pos (7UL) /*!< WTSYNFLG (Bit 7) */
+#define PDM2_SDSYNC_WTSYNFLG_Msk (0x80UL) /*!< WTSYNFLG (Bitfield-Mask: 0x01) */
+#define PDM2_SDSYNC_WTSYNCEN_Pos (6UL) /*!< WTSYNCEN (Bit 6) */
+#define PDM2_SDSYNC_WTSYNCEN_Msk (0x40UL) /*!< WTSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM2_SDSYNC_SYNCSEL_Pos (0UL) /*!< SYNCSEL (Bit 0) */
+#define PDM2_SDSYNC_SYNCSEL_Msk (0x3fUL) /*!< SYNCSEL (Bitfield-Mask: 0x3f) */
+/* ========================================================= IDAT ========================================================== */
+#define PDM2_IDAT_IDAT_Pos (0UL) /*!< IDAT (Bit 0) */
+#define PDM2_IDAT_IDAT_Msk (0xffffUL) /*!< IDAT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ PDM3 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define PDM3_ENABLE_INMOD_Pos (1UL) /*!< INMOD (Bit 1) */
+#define PDM3_ENABLE_INMOD_Msk (0x2UL) /*!< INMOD (Bitfield-Mask: 0x01) */
+#define PDM3_ENABLE_PDMEN_Pos (0UL) /*!< PDMEN (Bit 0) */
+#define PDM3_ENABLE_PDMEN_Msk (0x1UL) /*!< PDMEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define PDM3_CTRL_RXDLY_Pos (28UL) /*!< RXDLY (Bit 28) */
+#define PDM3_CTRL_RXDLY_Msk (0x70000000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define PDM3_CTRL_DMAEN_Pos (19UL) /*!< DMAEN (Bit 19) */
+#define PDM3_CTRL_DMAEN_Msk (0x80000UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+#define PDM3_CTRL_SAMPMODE_Pos (18UL) /*!< SAMPMODE (Bit 18) */
+#define PDM3_CTRL_SAMPMODE_Msk (0x40000UL) /*!< SAMPMODE (Bitfield-Mask: 0x01) */
+#define PDM3_CTRL_SCPOL_Pos (17UL) /*!< SCPOL (Bit 17) */
+#define PDM3_CTRL_SCPOL_Msk (0x20000UL) /*!< SCPOL (Bitfield-Mask: 0x01) */
+#define PDM3_CTRL_MSTEN_Pos (16UL) /*!< MSTEN (Bit 16) */
+#define PDM3_CTRL_MSTEN_Msk (0x10000UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define PDM3_CTRL_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define PDM3_CTRL_BAUD_Msk (0xfffUL) /*!< BAUD (Bitfield-Mask: 0xfff) */
+/* ========================================================= DFCR ========================================================== */
+#define PDM3_DFCR_SHIFT_Pos (16UL) /*!< SHIFT (Bit 16) */
+#define PDM3_DFCR_SHIFT_Msk (0xf0000UL) /*!< SHIFT (Bitfield-Mask: 0x0f) */
+#define PDM3_DFCR_SDSYNCEN_Pos (14UL) /*!< SDSYNCEN (Bit 14) */
+#define PDM3_DFCR_SDSYNCEN_Msk (0x4000UL) /*!< SDSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM3_DFCR_DFDR_Pos (13UL) /*!< DFDR (Bit 13) */
+#define PDM3_DFCR_DFDR_Msk (0x2000UL) /*!< DFDR (Bitfield-Mask: 0x01) */
+#define PDM3_DFCR_DFBYPASS_Pos (12UL) /*!< DFBYPASS (Bit 12) */
+#define PDM3_DFCR_DFBYPASS_Msk (0x1000UL) /*!< DFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM3_DFCR_DFSST_Pos (9UL) /*!< DFSST (Bit 9) */
+#define PDM3_DFCR_DFSST_Msk (0xe00UL) /*!< DFSST (Bitfield-Mask: 0x07) */
+#define PDM3_DFCR_DFEN_Pos (8UL) /*!< DFEN (Bit 8) */
+#define PDM3_DFCR_DFEN_Msk (0x100UL) /*!< DFEN (Bitfield-Mask: 0x01) */
+#define PDM3_DFCR_DOSR_Pos (0UL) /*!< DOSR (Bit 0) */
+#define PDM3_DFCR_DOSR_Msk (0xffUL) /*!< DOSR (Bitfield-Mask: 0xff) */
+/* ========================================================= CFCR ========================================================== */
+#define PDM3_CFCR_COMPSEL_Pos (10UL) /*!< COMPSEL (Bit 10) */
+#define PDM3_CFCR_COMPSEL_Msk (0x400UL) /*!< COMPSEL (Bitfield-Mask: 0x01) */
+#define PDM3_CFCR_CFBYPASS_Pos (9UL) /*!< CFBYPASS (Bit 9) */
+#define PDM3_CFCR_CFBYPASS_Msk (0x200UL) /*!< CFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM3_CFCR_CFSST_Pos (6UL) /*!< CFSST (Bit 6) */
+#define PDM3_CFCR_CFSST_Msk (0x1c0UL) /*!< CFSST (Bitfield-Mask: 0x07) */
+#define PDM3_CFCR_CFEN_Pos (5UL) /*!< CFEN (Bit 5) */
+#define PDM3_CFCR_CFEN_Msk (0x20UL) /*!< CFEN (Bitfield-Mask: 0x01) */
+#define PDM3_CFCR_COSR_Pos (0UL) /*!< COSR (Bit 0) */
+#define PDM3_CFCR_COSR_Msk (0x1fUL) /*!< COSR (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCSR ========================================================== */
+#define PDM3_FCSR_FIFORST_Pos (18UL) /*!< FIFORST (Bit 18) */
+#define PDM3_FCSR_FIFORST_Msk (0x40000UL) /*!< FIFORST (Bitfield-Mask: 0x01) */
+#define PDM3_FCSR_FIFOFULL_Pos (17UL) /*!< FIFOFULL (Bit 17) */
+#define PDM3_FCSR_FIFOFULL_Msk (0x20000UL) /*!< FIFOFULL (Bitfield-Mask: 0x01) */
+#define PDM3_FCSR_FIFOEMPTY_Pos (16UL) /*!< FIFOEMPTY (Bit 16) */
+#define PDM3_FCSR_FIFOEMPTY_Msk (0x10000UL) /*!< FIFOEMPTY (Bitfield-Mask: 0x01) */
+#define PDM3_FCSR_PDMFST_Pos (8UL) /*!< PDMFST (Bit 8) */
+#define PDM3_FCSR_PDMFST_Msk (0xf00UL) /*!< PDMFST (Bitfield-Mask: 0x0f) */
+#define PDM3_FCSR_PDMFIL_Pos (0UL) /*!< PDMFIL (Bit 0) */
+#define PDM3_FCSR_PDMFIL_Msk (0x7UL) /*!< PDMFIL (Bitfield-Mask: 0x07) */
+/* ========================================================== IER ========================================================== */
+#define PDM3_IER_FIUIE_Pos (7UL) /*!< FIUIE (Bit 7) */
+#define PDM3_IER_FIUIE_Msk (0x80UL) /*!< FIUIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_CTIE_Pos (6UL) /*!< CTIE (Bit 6) */
+#define PDM3_IER_CTIE_Msk (0x40UL) /*!< CTIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_FFIE_Pos (5UL) /*!< FFIE (Bit 5) */
+#define PDM3_IER_FFIE_Msk (0x20UL) /*!< FFIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_FIOIE_Pos (4UL) /*!< FIOIE (Bit 4) */
+#define PDM3_IER_FIOIE_Msk (0x10UL) /*!< FIOIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_DOFIE_Pos (3UL) /*!< DOFIE (Bit 3) */
+#define PDM3_IER_DOFIE_Msk (0x8UL) /*!< DOFIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_DFIE_Pos (2UL) /*!< DFIE (Bit 2) */
+#define PDM3_IER_DFIE_Msk (0x4UL) /*!< DFIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_LLIE_Pos (1UL) /*!< LLIE (Bit 1) */
+#define PDM3_IER_LLIE_Msk (0x2UL) /*!< LLIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_HLIE_Pos (0UL) /*!< HLIE (Bit 0) */
+#define PDM3_IER_HLIE_Msk (0x1UL) /*!< HLIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define PDM3_ISR_FIUINTR_Pos (7UL) /*!< FIUINTR (Bit 7) */
+#define PDM3_ISR_FIUINTR_Msk (0x80UL) /*!< FIUINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_CTOINTR_Pos (6UL) /*!< CTOINTR (Bit 6) */
+#define PDM3_ISR_CTOINTR_Msk (0x40UL) /*!< CTOINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_FIFINTR_Pos (5UL) /*!< FIFINTR (Bit 5) */
+#define PDM3_ISR_FIFINTR_Msk (0x20UL) /*!< FIFINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_FIOINTR_Pos (4UL) /*!< FIOINTR (Bit 4) */
+#define PDM3_ISR_FIOINTR_Msk (0x10UL) /*!< FIOINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_DOINTR_Pos (3UL) /*!< DOINTR (Bit 3) */
+#define PDM3_ISR_DOINTR_Msk (0x8UL) /*!< DOINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_DFINTR_Pos (2UL) /*!< DFINTR (Bit 2) */
+#define PDM3_ISR_DFINTR_Msk (0x4UL) /*!< DFINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_LLINTR_Pos (1UL) /*!< LLINTR (Bit 1) */
+#define PDM3_ISR_LLINTR_Msk (0x2UL) /*!< LLINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_HLINTR_Pos (0UL) /*!< HLINTR (Bit 0) */
+#define PDM3_ISR_HLINTR_Msk (0x1UL) /*!< HLINTR (Bitfield-Mask: 0x01) */
+/* ========================================================= DDAT ========================================================== */
+#define PDM3_DDAT_DDAT_Pos (0UL) /*!< DDAT (Bit 0) */
+#define PDM3_DDAT_DDAT_Msk (0xffffffUL) /*!< DDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CDAT ========================================================== */
+#define PDM3_CDAT_CDAT_Pos (0UL) /*!< CDAT (Bit 0) */
+#define PDM3_CDAT_CDAT_Msk (0xffffUL) /*!< CDAT (Bitfield-Mask: 0xffff) */
+/* ========================================================= FDAT ========================================================== */
+#define PDM3_FDAT_FDAT_Pos (0UL) /*!< FDAT (Bit 0) */
+#define PDM3_FDAT_FDAT_Msk (0xffffffUL) /*!< FDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CMPH ========================================================== */
+#define PDM3_CMPH_HLT_Pos (0UL) /*!< HLT (Bit 0) */
+#define PDM3_CMPH_HLT_Msk (0xffffUL) /*!< HLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPL ========================================================== */
+#define PDM3_CMPL_LLT_Pos (0UL) /*!< LLT (Bit 0) */
+#define PDM3_CMPL_LLT_Msk (0xffffUL) /*!< LLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CLKTO ========================================================= */
+#define PDM3_CLKTO_CLKTOT_Pos (0UL) /*!< CLKTOT (Bit 0) */
+#define PDM3_CLKTO_CLKTOT_Msk (0x3ffffUL) /*!< CLKTOT (Bitfield-Mask: 0x3ffff) */
+/* ======================================================== SDSYNC ========================================================= */
+#define PDM3_SDSYNC_WTSCLREN_Pos (10UL) /*!< WTSCLREN (Bit 10) */
+#define PDM3_SDSYNC_WTSCLREN_Msk (0x400UL) /*!< WTSCLREN (Bitfield-Mask: 0x01) */
+#define PDM3_SDSYNC_FFSYNCCLREN_Pos (9UL) /*!< FFSYNCCLREN (Bit 9) */
+#define PDM3_SDSYNC_FFSYNCCLREN_Msk (0x200UL) /*!< FFSYNCCLREN (Bitfield-Mask: 0x01) */
+#define PDM3_SDSYNC_WTSYNCLR_Pos (8UL) /*!< WTSYNCLR (Bit 8) */
+#define PDM3_SDSYNC_WTSYNCLR_Msk (0x100UL) /*!< WTSYNCLR (Bitfield-Mask: 0x01) */
+#define PDM3_SDSYNC_WTSYNFLG_Pos (7UL) /*!< WTSYNFLG (Bit 7) */
+#define PDM3_SDSYNC_WTSYNFLG_Msk (0x80UL) /*!< WTSYNFLG (Bitfield-Mask: 0x01) */
+#define PDM3_SDSYNC_WTSYNCEN_Pos (6UL) /*!< WTSYNCEN (Bit 6) */
+#define PDM3_SDSYNC_WTSYNCEN_Msk (0x40UL) /*!< WTSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM3_SDSYNC_SYNCSEL_Pos (0UL) /*!< SYNCSEL (Bit 0) */
+#define PDM3_SDSYNC_SYNCSEL_Msk (0x3fUL) /*!< SYNCSEL (Bitfield-Mask: 0x3f) */
+/* ========================================================= IDAT ========================================================== */
+#define PDM3_IDAT_IDAT_Pos (0UL) /*!< IDAT (Bit 0) */
+#define PDM3_IDAT_IDAT_Msk (0xffffUL) /*!< IDAT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IWDG ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= KEYR ========================================================== */
+#define IWDG_KEYR_KEY_Pos (0UL) /*!< KEY (Bit 0) */
+#define IWDG_KEYR_KEY_Msk (0xffffUL) /*!< KEY (Bitfield-Mask: 0xffff) */
+/* ========================================================== CR =========================================================== */
+#define IWDG_CR_TOIE_Pos (1UL) /*!< TOIE (Bit 1) */
+#define IWDG_CR_TOIE_Msk (0x2UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define IWDG_CR_MODE_Pos (0UL) /*!< MODE (Bit 0) */
+#define IWDG_CR_MODE_Msk (0x1UL) /*!< MODE (Bitfield-Mask: 0x01) */
+/* ========================================================== RLR ========================================================== */
+#define IWDG_RLR_RLV_Pos (0UL) /*!< RLV (Bit 0) */
+#define IWDG_RLR_RLV_Msk (0xffffUL) /*!< RLV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define IWDG_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define IWDG_PSCR_PSC_Msk (0x7UL) /*!< PSC (Bitfield-Mask: 0x07) */
+/* ========================================================== SR =========================================================== */
+#define IWDG_SR_TOIF_Pos (2UL) /*!< TOIF (Bit 2) */
+#define IWDG_SR_TOIF_Msk (0x4UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define IWDG_SR_RLVUPD_Pos (1UL) /*!< RLVUPD (Bit 1) */
+#define IWDG_SR_RLVUPD_Msk (0x2UL) /*!< RLVUPD (Bitfield-Mask: 0x01) */
+#define IWDG_SR_PSCUPD_Pos (0UL) /*!< PSCUPD (Bit 0) */
+#define IWDG_SR_PSCUPD_Msk (0x1UL) /*!< PSCUPD (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR0_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR0_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR0_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR0_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR0_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR0_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR0_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR0_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR0_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR0_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR0_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR0_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR0_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR0_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR0_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR0_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR0_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR0_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR0_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR0_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR0_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR0_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR0_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR0_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR0_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR0_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR0_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR0_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR0_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR0_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR0_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR0_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR0_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR0_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR0_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR0_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR0_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR0_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR0_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR0_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR0_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR0_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR0_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR0_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR1_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR1_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR1_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR1_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR1_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR1_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR1_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR1_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR1_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR1_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR1_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR1_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR1_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR1_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR1_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR1_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR1_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR1_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR1_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR1_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR1_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR1_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR1_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR1_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR1_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR1_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR1_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR1_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR1_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR1_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR1_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR1_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR1_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR1_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR1_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR1_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR1_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR1_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR1_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR1_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR1_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR1_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR1_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR1_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR2_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR2_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR2_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR2_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR2_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR2_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR2_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR2_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR2_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR2_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR2_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR2_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR2_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR2_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR2_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR2_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR2_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR2_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR2_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR2_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR2_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR2_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR2_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR2_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR2_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR2_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR2_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR2_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR2_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR2_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR2_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR2_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR2_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR2_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR2_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR2_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR2_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR2_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR2_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR2_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR2_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR2_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR2_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR2_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR3_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR3_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR3_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR3_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR3_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR3_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR3_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR3_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR3_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR3_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR3_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR3_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR3_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR3_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR3_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR3_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR3_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR3_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR3_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR3_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR3_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR3_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR3_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR3_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR3_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR3_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR3_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR3_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR3_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR3_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR3_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR3_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR3_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR3_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR3_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR3_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR3_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR3_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR3_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR3_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR3_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR3_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR3_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR3_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR4_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR4_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR4_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR4_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR4_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR4_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR4_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR4_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR4_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR4_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR4_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR4_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR4_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR4_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR4_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR4_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR4_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR4_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR4_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR4_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR4_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR4_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR4_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR4_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR4_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR4_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR4_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR4_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR4_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR4_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR4_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR4_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR4_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR4_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR4_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR4_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR4_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR4_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR4_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR4_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR4_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR4_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR4_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR4_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR5 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR5_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR5_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR5_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR5_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR5_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR5_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR5_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR5_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR5_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR5_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR5_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR5_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR5_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR5_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR5_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR5_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR5_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR5_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR5_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR5_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR5_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR5_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR5_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR5_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR5_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR5_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR5_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR5_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR5_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR5_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR5_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR5_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR5_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR5_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR5_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR5_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR5_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR5_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR5_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR5_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR5_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR5_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR5_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR5_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ I2C0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define I2C0_ENABLE_HDRX_Pos (18UL) /*!< HDRX (Bit 18) */
+#define I2C0_ENABLE_HDRX_Msk (0xc0000UL) /*!< HDRX (Bitfield-Mask: 0x03) */
+#define I2C0_ENABLE_NSTCH_Pos (17UL) /*!< NSTCH (Bit 17) */
+#define I2C0_ENABLE_NSTCH_Msk (0x20000UL) /*!< NSTCH (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_MSTCH_Pos (16UL) /*!< MSTCH (Bit 16) */
+#define I2C0_ENABLE_MSTCH_Msk (0x10000UL) /*!< MSTCH (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_SMTOEN_Pos (15UL) /*!< SMTOEN (Bit 15) */
+#define I2C0_ENABLE_SMTOEN_Msk (0x8000UL) /*!< SMTOEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_SMHEN_Pos (14UL) /*!< SMHEN (Bit 14) */
+#define I2C0_ENABLE_SMHEN_Msk (0x4000UL) /*!< SMHEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_SMARPEN_Pos (13UL) /*!< SMARPEN (Bit 13) */
+#define I2C0_ENABLE_SMARPEN_Msk (0x2000UL) /*!< SMARPEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_SMALEN_Pos (12UL) /*!< SMALEN (Bit 12) */
+#define I2C0_ENABLE_SMALEN_Msk (0x1000UL) /*!< SMALEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_OSAEN_Pos (11UL) /*!< OSAEN (Bit 11) */
+#define I2C0_ENABLE_OSAEN_Msk (0x800UL) /*!< OSAEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_GCEN_Pos (10UL) /*!< GCEN (Bit 10) */
+#define I2C0_ENABLE_GCEN_Msk (0x400UL) /*!< GCEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_A10BEN_Pos (9UL) /*!< A10BEN (Bit 9) */
+#define I2C0_ENABLE_A10BEN_Msk (0x200UL) /*!< A10BEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_MSTEN_Pos (8UL) /*!< MSTEN (Bit 8) */
+#define I2C0_ENABLE_MSTEN_Msk (0x100UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_RFHSEN_Pos (7UL) /*!< RFHSEN (Bit 7) */
+#define I2C0_ENABLE_RFHSEN_Msk (0x80UL) /*!< RFHSEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_DMATXEN_Pos (6UL) /*!< DMATXEN (Bit 6) */
+#define I2C0_ENABLE_DMATXEN_Msk (0x40UL) /*!< DMATXEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_DMARXEN_Pos (5UL) /*!< DMARXEN (Bit 5) */
+#define I2C0_ENABLE_DMARXEN_Msk (0x20UL) /*!< DMARXEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_RLSCMD_Pos (4UL) /*!< RLSCMD (Bit 4) */
+#define I2C0_ENABLE_RLSCMD_Msk (0x10UL) /*!< RLSCMD (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_TFRST_Pos (3UL) /*!< TFRST (Bit 3) */
+#define I2C0_ENABLE_TFRST_Msk (0x8UL) /*!< TFRST (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_RFRST_Pos (2UL) /*!< RFRST (Bit 2) */
+#define I2C0_ENABLE_RFRST_Msk (0x4UL) /*!< RFRST (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_UDRCFG_Pos (1UL) /*!< UDRCFG (Bit 1) */
+#define I2C0_ENABLE_UDRCFG_Msk (0x2UL) /*!< UDRCFG (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_I2CEN_Pos (0UL) /*!< I2CEN (Bit 0) */
+#define I2C0_ENABLE_I2CEN_Msk (0x1UL) /*!< I2CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define I2C0_CTRL_AUTOEND_Pos (14UL) /*!< AUTOEND (Bit 14) */
+#define I2C0_CTRL_AUTOEND_Msk (0x4000UL) /*!< AUTOEND (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_MODE10B_Pos (13UL) /*!< MODE10B (Bit 13) */
+#define I2C0_CTRL_MODE10B_Msk (0x2000UL) /*!< MODE10B (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_PECBYTE_Pos (12UL) /*!< PECBYTE (Bit 12) */
+#define I2C0_CTRL_PECBYTE_Msk (0x1000UL) /*!< PECBYTE (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_NACK_Pos (11UL) /*!< NACK (Bit 11) */
+#define I2C0_CTRL_NACK_Msk (0x800UL) /*!< NACK (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_START_Pos (10UL) /*!< START (Bit 10) */
+#define I2C0_CTRL_START_Msk (0x400UL) /*!< START (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_STOP_Pos (9UL) /*!< STOP (Bit 9) */
+#define I2C0_CTRL_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_DIRECT_Pos (8UL) /*!< DIRECT (Bit 8) */
+#define I2C0_CTRL_DIRECT_Msk (0x100UL) /*!< DIRECT (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_I2CCNT_Pos (0UL) /*!< I2CCNT (Bit 0) */
+#define I2C0_CTRL_I2CCNT_Msk (0xffUL) /*!< I2CCNT (Bitfield-Mask: 0xff) */
+/* ========================================================= BAUD ========================================================== */
+#define I2C0_BAUD_SCLHCNT_Pos (16UL) /*!< SCLHCNT (Bit 16) */
+#define I2C0_BAUD_SCLHCNT_Msk (0x3ff0000UL) /*!< SCLHCNT (Bitfield-Mask: 0x3ff) */
+#define I2C0_BAUD_SCLLCNT_Pos (0UL) /*!< SCLLCNT (Bit 0) */
+#define I2C0_BAUD_SCLLCNT_Msk (0x3ffUL) /*!< SCLLCNT (Bitfield-Mask: 0x3ff) */
+/* ========================================================= UDRDR ========================================================= */
+#define I2C0_UDRDR_UDRDR_Pos (0UL) /*!< UDRDR (Bit 0) */
+#define I2C0_UDRDR_UDRDR_Msk (0xffUL) /*!< UDRDR (Bitfield-Mask: 0xff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define I2C0_FIFOCTRL_RXFTLR_Pos (4UL) /*!< RXFTLR (Bit 4) */
+#define I2C0_FIFOCTRL_RXFTLR_Msk (0xf0UL) /*!< RXFTLR (Bitfield-Mask: 0x0f) */
+#define I2C0_FIFOCTRL_TXFTLR_Pos (0UL) /*!< TXFTLR (Bit 0) */
+#define I2C0_FIFOCTRL_TXFTLR_Msk (0xfUL) /*!< TXFTLR (Bitfield-Mask: 0x0f) */
+/* ========================================================== TAR ========================================================== */
+#define I2C0_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define I2C0_TAR_TAR_Msk (0x3ffUL) /*!< TAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== SAR ========================================================== */
+#define I2C0_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define I2C0_SAR_SAR_Msk (0x3ffUL) /*!< SAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================= OSAR ========================================================== */
+#define I2C0_OSAR_OSAM_Pos (16UL) /*!< OSAM (Bit 16) */
+#define I2C0_OSAR_OSAM_Msk (0x3ff0000UL) /*!< OSAM (Bitfield-Mask: 0x3ff) */
+#define I2C0_OSAR_OSAR_Pos (0UL) /*!< OSAR (Bit 0) */
+#define I2C0_OSAR_OSAR_Msk (0x3ffUL) /*!< OSAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== PEC ========================================================== */
+#define I2C0_PEC_IDPEC_Pos (8UL) /*!< IDPEC (Bit 8) */
+#define I2C0_PEC_IDPEC_Msk (0xff00UL) /*!< IDPEC (Bitfield-Mask: 0xff) */
+#define I2C0_PEC_RXPEC_Pos (0UL) /*!< RXPEC (Bit 0) */
+#define I2C0_PEC_RXPEC_Msk (0xffUL) /*!< RXPEC (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMING ========================================================= */
+#define I2C0_TIMING_SPKLEN_Pos (24UL) /*!< SPKLEN (Bit 24) */
+#define I2C0_TIMING_SPKLEN_Msk (0xff000000UL) /*!< SPKLEN (Bitfield-Mask: 0xff) */
+#define I2C0_TIMING_SLVSUDAT_Pos (16UL) /*!< SLVSUDAT (Bit 16) */
+#define I2C0_TIMING_SLVSUDAT_Msk (0xff0000UL) /*!< SLVSUDAT (Bitfield-Mask: 0xff) */
+#define I2C0_TIMING_SUDAT_Pos (8UL) /*!< SUDAT (Bit 8) */
+#define I2C0_TIMING_SUDAT_Msk (0xff00UL) /*!< SUDAT (Bitfield-Mask: 0xff) */
+#define I2C0_TIMING_HDDAT_Pos (0UL) /*!< HDDAT (Bit 0) */
+#define I2C0_TIMING_HDDAT_Msk (0xffUL) /*!< HDDAT (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMEOUT ======================================================== */
+#define I2C0_TIMEOUT_SEXTTO_Pos (16UL) /*!< SEXTTO (Bit 16) */
+#define I2C0_TIMEOUT_SEXTTO_Msk (0xffff0000UL) /*!< SEXTTO (Bitfield-Mask: 0xffff) */
+#define I2C0_TIMEOUT_MEXTTO_Pos (0UL) /*!< MEXTTO (Bit 0) */
+#define I2C0_TIMEOUT_MEXTTO_Msk (0xffffUL) /*!< MEXTTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== BUSTOUT ======================================================== */
+#define I2C0_BUSTOUT_TOSEL_Pos (31UL) /*!< TOSEL (Bit 31) */
+#define I2C0_BUSTOUT_TOSEL_Msk (0x80000000UL) /*!< TOSEL (Bitfield-Mask: 0x01) */
+#define I2C0_BUSTOUT_BTO_Pos (0UL) /*!< BTO (Bit 0) */
+#define I2C0_BUSTOUT_BTO_Msk (0xffffUL) /*!< BTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== INTREN ========================================================= */
+#define I2C0_INTREN_BTOIE_Pos (23UL) /*!< BTOIE (Bit 23) */
+#define I2C0_INTREN_BTOIE_Msk (0x800000UL) /*!< BTOIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_MOHIE_Pos (22UL) /*!< MOHIE (Bit 22) */
+#define I2C0_INTREN_MOHIE_Msk (0x400000UL) /*!< MOHIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_SWTXIE_Pos (21UL) /*!< SWTXIE (Bit 21) */
+#define I2C0_INTREN_SWTXIE_Msk (0x200000UL) /*!< SWTXIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_MTXAIE_Pos (20UL) /*!< MTXAIE (Bit 20) */
+#define I2C0_INTREN_MTXAIE_Msk (0x100000UL) /*!< MTXAIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RXGCIE_Pos (19UL) /*!< RXGCIE (Bit 19) */
+#define I2C0_INTREN_RXGCIE_Msk (0x80000UL) /*!< RXGCIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_PECRXIE_Pos (18UL) /*!< PECRXIE (Bit 18) */
+#define I2C0_INTREN_PECRXIE_Msk (0x40000UL) /*!< PECRXIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_SEXTOIE_Pos (17UL) /*!< SEXTOIE (Bit 17) */
+#define I2C0_INTREN_SEXTOIE_Msk (0x20000UL) /*!< SEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_MEXTOIE_Pos (16UL) /*!< MEXTOIE (Bit 16) */
+#define I2C0_INTREN_MEXTOIE_Msk (0x10000UL) /*!< MEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_ALDETIE_Pos (15UL) /*!< ALDETIE (Bit 15) */
+#define I2C0_INTREN_ALDETIE_Msk (0x8000UL) /*!< ALDETIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_NACKIE_Pos (14UL) /*!< NACKIE (Bit 14) */
+#define I2C0_INTREN_NACKIE_Msk (0x4000UL) /*!< NACKIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RSDETIE_Pos (13UL) /*!< RSDETIE (Bit 13) */
+#define I2C0_INTREN_RSDETIE_Msk (0x2000UL) /*!< RSDETIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_SPDETIE_Pos (12UL) /*!< SPDETIE (Bit 12) */
+#define I2C0_INTREN_SPDETIE_Msk (0x1000UL) /*!< SPDETIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_STDETIE_Pos (11UL) /*!< STDETIE (Bit 11) */
+#define I2C0_INTREN_STDETIE_Msk (0x800UL) /*!< STDETIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RXADIE_Pos (10UL) /*!< RXADIE (Bit 10) */
+#define I2C0_INTREN_RXADIE_Msk (0x400UL) /*!< RXADIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_TXADIE_Pos (9UL) /*!< TXADIE (Bit 9) */
+#define I2C0_INTREN_TXADIE_Msk (0x200UL) /*!< TXADIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_MDEIE_Pos (8UL) /*!< MDEIE (Bit 8) */
+#define I2C0_INTREN_MDEIE_Msk (0x100UL) /*!< MDEIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_BUSEIE_Pos (7UL) /*!< BUSEIE (Bit 7) */
+#define I2C0_INTREN_BUSEIE_Msk (0x80UL) /*!< BUSEIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_ARBFIE_Pos (6UL) /*!< ARBFIE (Bit 6) */
+#define I2C0_INTREN_ARBFIE_Msk (0x40UL) /*!< ARBFIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_TXUFIE_Pos (5UL) /*!< TXUFIE (Bit 5) */
+#define I2C0_INTREN_TXUFIE_Msk (0x20UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_TXOFIE_Pos (4UL) /*!< TXOFIE (Bit 4) */
+#define I2C0_INTREN_TXOFIE_Msk (0x10UL) /*!< TXOFIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RXUFIE_Pos (3UL) /*!< RXUFIE (Bit 3) */
+#define I2C0_INTREN_RXUFIE_Msk (0x8UL) /*!< RXUFIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RXOFIE_Pos (2UL) /*!< RXOFIE (Bit 2) */
+#define I2C0_INTREN_RXOFIE_Msk (0x4UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_TXEIE_Pos (1UL) /*!< TXEIE (Bit 1) */
+#define I2C0_INTREN_TXEIE_Msk (0x2UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RXFIE_Pos (0UL) /*!< RXFIE (Bit 0) */
+#define I2C0_INTREN_RXFIE_Msk (0x1UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+/* ========================================================= INTR ========================================================== */
+#define I2C0_INTR_RCNT_Pos (24UL) /*!< RCNT (Bit 24) */
+#define I2C0_INTR_RCNT_Msk (0xff000000UL) /*!< RCNT (Bitfield-Mask: 0xff) */
+#define I2C0_INTR_BTOI_Pos (23UL) /*!< BTOI (Bit 23) */
+#define I2C0_INTR_BTOI_Msk (0x800000UL) /*!< BTOI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_MOHI_Pos (22UL) /*!< MOHI (Bit 22) */
+#define I2C0_INTR_MOHI_Msk (0x400000UL) /*!< MOHI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_SWTXI_Pos (21UL) /*!< SWTXI (Bit 21) */
+#define I2C0_INTR_SWTXI_Msk (0x200000UL) /*!< SWTXI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_MTXAI_Pos (20UL) /*!< MTXAI (Bit 20) */
+#define I2C0_INTR_MTXAI_Msk (0x100000UL) /*!< MTXAI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RXGCI_Pos (19UL) /*!< RXGCI (Bit 19) */
+#define I2C0_INTR_RXGCI_Msk (0x80000UL) /*!< RXGCI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_PECRXI_Pos (18UL) /*!< PECRXI (Bit 18) */
+#define I2C0_INTR_PECRXI_Msk (0x40000UL) /*!< PECRXI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_SEXTOI_Pos (17UL) /*!< SEXTOI (Bit 17) */
+#define I2C0_INTR_SEXTOI_Msk (0x20000UL) /*!< SEXTOI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_MEXTOI_Pos (16UL) /*!< MEXTOI (Bit 16) */
+#define I2C0_INTR_MEXTOI_Msk (0x10000UL) /*!< MEXTOI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_ALDETI_Pos (15UL) /*!< ALDETI (Bit 15) */
+#define I2C0_INTR_ALDETI_Msk (0x8000UL) /*!< ALDETI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_NACKI_Pos (14UL) /*!< NACKI (Bit 14) */
+#define I2C0_INTR_NACKI_Msk (0x4000UL) /*!< NACKI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RSDETI_Pos (13UL) /*!< RSDETI (Bit 13) */
+#define I2C0_INTR_RSDETI_Msk (0x2000UL) /*!< RSDETI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_SPETI_Pos (12UL) /*!< SPETI (Bit 12) */
+#define I2C0_INTR_SPETI_Msk (0x1000UL) /*!< SPETI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_STDETI_Pos (11UL) /*!< STDETI (Bit 11) */
+#define I2C0_INTR_STDETI_Msk (0x800UL) /*!< STDETI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RXADI_Pos (10UL) /*!< RXADI (Bit 10) */
+#define I2C0_INTR_RXADI_Msk (0x400UL) /*!< RXADI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_TXADI_Pos (9UL) /*!< TXADI (Bit 9) */
+#define I2C0_INTR_TXADI_Msk (0x200UL) /*!< TXADI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_MDEI_Pos (8UL) /*!< MDEI (Bit 8) */
+#define I2C0_INTR_MDEI_Msk (0x100UL) /*!< MDEI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_BUSEI_Pos (7UL) /*!< BUSEI (Bit 7) */
+#define I2C0_INTR_BUSEI_Msk (0x80UL) /*!< BUSEI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_ARBFI_Pos (6UL) /*!< ARBFI (Bit 6) */
+#define I2C0_INTR_ARBFI_Msk (0x40UL) /*!< ARBFI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_TXUFI_Pos (5UL) /*!< TXUFI (Bit 5) */
+#define I2C0_INTR_TXUFI_Msk (0x20UL) /*!< TXUFI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_TXOFI_Pos (4UL) /*!< TXOFI (Bit 4) */
+#define I2C0_INTR_TXOFI_Msk (0x10UL) /*!< TXOFI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RXUFI_Pos (3UL) /*!< RXUFI (Bit 3) */
+#define I2C0_INTR_RXUFI_Msk (0x8UL) /*!< RXUFI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RXOFI_Pos (2UL) /*!< RXOFI (Bit 2) */
+#define I2C0_INTR_RXOFI_Msk (0x4UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define I2C0_INTR_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define I2C0_INTR_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define I2C0_STATUS_RFF_Pos (30UL) /*!< RFF (Bit 30) */
+#define I2C0_STATUS_RFF_Msk (0x40000000UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define I2C0_STATUS_RFE_Pos (29UL) /*!< RFE (Bit 29) */
+#define I2C0_STATUS_RFE_Msk (0x20000000UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define I2C0_STATUS_RXFLR_Pos (24UL) /*!< RXFLR (Bit 24) */
+#define I2C0_STATUS_RXFLR_Msk (0x1f000000UL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
+#define I2C0_STATUS_TFF_Pos (22UL) /*!< TFF (Bit 22) */
+#define I2C0_STATUS_TFF_Msk (0x400000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define I2C0_STATUS_TFE_Pos (21UL) /*!< TFE (Bit 21) */
+#define I2C0_STATUS_TFE_Msk (0x200000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define I2C0_STATUS_TXFLR_Pos (16UL) /*!< TXFLR (Bit 16) */
+#define I2C0_STATUS_TXFLR_Msk (0x1f0000UL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
+#define I2C0_STATUS_ARBSTA_Pos (2UL) /*!< ARBSTA (Bit 2) */
+#define I2C0_STATUS_ARBSTA_Msk (0xcUL) /*!< ARBSTA (Bitfield-Mask: 0x03) */
+#define I2C0_STATUS_BUSBSY_Pos (1UL) /*!< BUSBSY (Bit 1) */
+#define I2C0_STATUS_BUSBSY_Msk (0x2UL) /*!< BUSBSY (Bitfield-Mask: 0x01) */
+#define I2C0_STATUS_FSMBSY_Pos (0UL) /*!< FSMBSY (Bit 0) */
+#define I2C0_STATUS_FSMBSY_Msk (0x1UL) /*!< FSMBSY (Bitfield-Mask: 0x01) */
+/* ======================================================== TXDATA ========================================================= */
+#define I2C0_TXDATA_TXDATA_Pos (0UL) /*!< TXDATA (Bit 0) */
+#define I2C0_TXDATA_TXDATA_Msk (0xffUL) /*!< TXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXDATA ========================================================= */
+#define I2C0_RXDATA_RXDATA_Pos (0UL) /*!< RXDATA (Bit 0) */
+#define I2C0_RXDATA_RXDATA_Msk (0xffUL) /*!< RXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXADDR ========================================================= */
+#define I2C0_RXADDR_ADDR_Pos (1UL) /*!< ADDR (Bit 1) */
+#define I2C0_RXADDR_ADDR_Msk (0xfeUL) /*!< ADDR (Bitfield-Mask: 0x7f) */
+#define I2C0_RXADDR_DIR_Pos (0UL) /*!< DIR (Bit 0) */
+#define I2C0_RXADDR_DIR_Msk (0x1UL) /*!< DIR (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ I2C1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define I2C1_ENABLE_HDRX_Pos (18UL) /*!< HDRX (Bit 18) */
+#define I2C1_ENABLE_HDRX_Msk (0xc0000UL) /*!< HDRX (Bitfield-Mask: 0x03) */
+#define I2C1_ENABLE_NSTCH_Pos (17UL) /*!< NSTCH (Bit 17) */
+#define I2C1_ENABLE_NSTCH_Msk (0x20000UL) /*!< NSTCH (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_MSTCH_Pos (16UL) /*!< MSTCH (Bit 16) */
+#define I2C1_ENABLE_MSTCH_Msk (0x10000UL) /*!< MSTCH (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_SMTOEN_Pos (15UL) /*!< SMTOEN (Bit 15) */
+#define I2C1_ENABLE_SMTOEN_Msk (0x8000UL) /*!< SMTOEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_SMHEN_Pos (14UL) /*!< SMHEN (Bit 14) */
+#define I2C1_ENABLE_SMHEN_Msk (0x4000UL) /*!< SMHEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_SMARPEN_Pos (13UL) /*!< SMARPEN (Bit 13) */
+#define I2C1_ENABLE_SMARPEN_Msk (0x2000UL) /*!< SMARPEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_SMALEN_Pos (12UL) /*!< SMALEN (Bit 12) */
+#define I2C1_ENABLE_SMALEN_Msk (0x1000UL) /*!< SMALEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_OSAEN_Pos (11UL) /*!< OSAEN (Bit 11) */
+#define I2C1_ENABLE_OSAEN_Msk (0x800UL) /*!< OSAEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_GCEN_Pos (10UL) /*!< GCEN (Bit 10) */
+#define I2C1_ENABLE_GCEN_Msk (0x400UL) /*!< GCEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_A10BEN_Pos (9UL) /*!< A10BEN (Bit 9) */
+#define I2C1_ENABLE_A10BEN_Msk (0x200UL) /*!< A10BEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_MSTEN_Pos (8UL) /*!< MSTEN (Bit 8) */
+#define I2C1_ENABLE_MSTEN_Msk (0x100UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_RFHSEN_Pos (7UL) /*!< RFHSEN (Bit 7) */
+#define I2C1_ENABLE_RFHSEN_Msk (0x80UL) /*!< RFHSEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_DMATXEN_Pos (6UL) /*!< DMATXEN (Bit 6) */
+#define I2C1_ENABLE_DMATXEN_Msk (0x40UL) /*!< DMATXEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_DMARXEN_Pos (5UL) /*!< DMARXEN (Bit 5) */
+#define I2C1_ENABLE_DMARXEN_Msk (0x20UL) /*!< DMARXEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_RLSCMD_Pos (4UL) /*!< RLSCMD (Bit 4) */
+#define I2C1_ENABLE_RLSCMD_Msk (0x10UL) /*!< RLSCMD (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_TFRST_Pos (3UL) /*!< TFRST (Bit 3) */
+#define I2C1_ENABLE_TFRST_Msk (0x8UL) /*!< TFRST (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_RFRST_Pos (2UL) /*!< RFRST (Bit 2) */
+#define I2C1_ENABLE_RFRST_Msk (0x4UL) /*!< RFRST (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_UDRCFG_Pos (1UL) /*!< UDRCFG (Bit 1) */
+#define I2C1_ENABLE_UDRCFG_Msk (0x2UL) /*!< UDRCFG (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_I2CEN_Pos (0UL) /*!< I2CEN (Bit 0) */
+#define I2C1_ENABLE_I2CEN_Msk (0x1UL) /*!< I2CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define I2C1_CTRL_AUTOEND_Pos (14UL) /*!< AUTOEND (Bit 14) */
+#define I2C1_CTRL_AUTOEND_Msk (0x4000UL) /*!< AUTOEND (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_MODE10B_Pos (13UL) /*!< MODE10B (Bit 13) */
+#define I2C1_CTRL_MODE10B_Msk (0x2000UL) /*!< MODE10B (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_PECBYTE_Pos (12UL) /*!< PECBYTE (Bit 12) */
+#define I2C1_CTRL_PECBYTE_Msk (0x1000UL) /*!< PECBYTE (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_NACK_Pos (11UL) /*!< NACK (Bit 11) */
+#define I2C1_CTRL_NACK_Msk (0x800UL) /*!< NACK (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_START_Pos (10UL) /*!< START (Bit 10) */
+#define I2C1_CTRL_START_Msk (0x400UL) /*!< START (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_STOP_Pos (9UL) /*!< STOP (Bit 9) */
+#define I2C1_CTRL_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_DIRECT_Pos (8UL) /*!< DIRECT (Bit 8) */
+#define I2C1_CTRL_DIRECT_Msk (0x100UL) /*!< DIRECT (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_I2CCNT_Pos (0UL) /*!< I2CCNT (Bit 0) */
+#define I2C1_CTRL_I2CCNT_Msk (0xffUL) /*!< I2CCNT (Bitfield-Mask: 0xff) */
+/* ========================================================= BAUD ========================================================== */
+#define I2C1_BAUD_SCLHCNT_Pos (16UL) /*!< SCLHCNT (Bit 16) */
+#define I2C1_BAUD_SCLHCNT_Msk (0x3ff0000UL) /*!< SCLHCNT (Bitfield-Mask: 0x3ff) */
+#define I2C1_BAUD_SCLLCNT_Pos (0UL) /*!< SCLLCNT (Bit 0) */
+#define I2C1_BAUD_SCLLCNT_Msk (0x3ffUL) /*!< SCLLCNT (Bitfield-Mask: 0x3ff) */
+/* ========================================================= UDRDR ========================================================= */
+#define I2C1_UDRDR_UDRDR_Pos (0UL) /*!< UDRDR (Bit 0) */
+#define I2C1_UDRDR_UDRDR_Msk (0xffUL) /*!< UDRDR (Bitfield-Mask: 0xff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define I2C1_FIFOCTRL_RXFTLR_Pos (4UL) /*!< RXFTLR (Bit 4) */
+#define I2C1_FIFOCTRL_RXFTLR_Msk (0xf0UL) /*!< RXFTLR (Bitfield-Mask: 0x0f) */
+#define I2C1_FIFOCTRL_TXFTLR_Pos (0UL) /*!< TXFTLR (Bit 0) */
+#define I2C1_FIFOCTRL_TXFTLR_Msk (0xfUL) /*!< TXFTLR (Bitfield-Mask: 0x0f) */
+/* ========================================================== TAR ========================================================== */
+#define I2C1_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define I2C1_TAR_TAR_Msk (0x3ffUL) /*!< TAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== SAR ========================================================== */
+#define I2C1_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define I2C1_SAR_SAR_Msk (0x3ffUL) /*!< SAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================= OSAR ========================================================== */
+#define I2C1_OSAR_OSAM_Pos (16UL) /*!< OSAM (Bit 16) */
+#define I2C1_OSAR_OSAM_Msk (0x3ff0000UL) /*!< OSAM (Bitfield-Mask: 0x3ff) */
+#define I2C1_OSAR_OSAR_Pos (0UL) /*!< OSAR (Bit 0) */
+#define I2C1_OSAR_OSAR_Msk (0x3ffUL) /*!< OSAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== PEC ========================================================== */
+#define I2C1_PEC_IDPEC_Pos (8UL) /*!< IDPEC (Bit 8) */
+#define I2C1_PEC_IDPEC_Msk (0xff00UL) /*!< IDPEC (Bitfield-Mask: 0xff) */
+#define I2C1_PEC_RXPEC_Pos (0UL) /*!< RXPEC (Bit 0) */
+#define I2C1_PEC_RXPEC_Msk (0xffUL) /*!< RXPEC (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMING ========================================================= */
+#define I2C1_TIMING_SPKLEN_Pos (24UL) /*!< SPKLEN (Bit 24) */
+#define I2C1_TIMING_SPKLEN_Msk (0xff000000UL) /*!< SPKLEN (Bitfield-Mask: 0xff) */
+#define I2C1_TIMING_SLVSUDAT_Pos (16UL) /*!< SLVSUDAT (Bit 16) */
+#define I2C1_TIMING_SLVSUDAT_Msk (0xff0000UL) /*!< SLVSUDAT (Bitfield-Mask: 0xff) */
+#define I2C1_TIMING_SUDAT_Pos (8UL) /*!< SUDAT (Bit 8) */
+#define I2C1_TIMING_SUDAT_Msk (0xff00UL) /*!< SUDAT (Bitfield-Mask: 0xff) */
+#define I2C1_TIMING_HDDAT_Pos (0UL) /*!< HDDAT (Bit 0) */
+#define I2C1_TIMING_HDDAT_Msk (0xffUL) /*!< HDDAT (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMEOUT ======================================================== */
+#define I2C1_TIMEOUT_SEXTTO_Pos (16UL) /*!< SEXTTO (Bit 16) */
+#define I2C1_TIMEOUT_SEXTTO_Msk (0xffff0000UL) /*!< SEXTTO (Bitfield-Mask: 0xffff) */
+#define I2C1_TIMEOUT_MEXTTO_Pos (0UL) /*!< MEXTTO (Bit 0) */
+#define I2C1_TIMEOUT_MEXTTO_Msk (0xffffUL) /*!< MEXTTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== BUSTOUT ======================================================== */
+#define I2C1_BUSTOUT_TOSEL_Pos (31UL) /*!< TOSEL (Bit 31) */
+#define I2C1_BUSTOUT_TOSEL_Msk (0x80000000UL) /*!< TOSEL (Bitfield-Mask: 0x01) */
+#define I2C1_BUSTOUT_BTO_Pos (0UL) /*!< BTO (Bit 0) */
+#define I2C1_BUSTOUT_BTO_Msk (0xffffUL) /*!< BTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== INTREN ========================================================= */
+#define I2C1_INTREN_BTOIE_Pos (23UL) /*!< BTOIE (Bit 23) */
+#define I2C1_INTREN_BTOIE_Msk (0x800000UL) /*!< BTOIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_MOHIE_Pos (22UL) /*!< MOHIE (Bit 22) */
+#define I2C1_INTREN_MOHIE_Msk (0x400000UL) /*!< MOHIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_SWTXIE_Pos (21UL) /*!< SWTXIE (Bit 21) */
+#define I2C1_INTREN_SWTXIE_Msk (0x200000UL) /*!< SWTXIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_MTXAIE_Pos (20UL) /*!< MTXAIE (Bit 20) */
+#define I2C1_INTREN_MTXAIE_Msk (0x100000UL) /*!< MTXAIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RXGCIE_Pos (19UL) /*!< RXGCIE (Bit 19) */
+#define I2C1_INTREN_RXGCIE_Msk (0x80000UL) /*!< RXGCIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_PECRXIE_Pos (18UL) /*!< PECRXIE (Bit 18) */
+#define I2C1_INTREN_PECRXIE_Msk (0x40000UL) /*!< PECRXIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_SEXTOIE_Pos (17UL) /*!< SEXTOIE (Bit 17) */
+#define I2C1_INTREN_SEXTOIE_Msk (0x20000UL) /*!< SEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_MEXTOIE_Pos (16UL) /*!< MEXTOIE (Bit 16) */
+#define I2C1_INTREN_MEXTOIE_Msk (0x10000UL) /*!< MEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_ALDETIE_Pos (15UL) /*!< ALDETIE (Bit 15) */
+#define I2C1_INTREN_ALDETIE_Msk (0x8000UL) /*!< ALDETIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_NACKIE_Pos (14UL) /*!< NACKIE (Bit 14) */
+#define I2C1_INTREN_NACKIE_Msk (0x4000UL) /*!< NACKIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RSDETIE_Pos (13UL) /*!< RSDETIE (Bit 13) */
+#define I2C1_INTREN_RSDETIE_Msk (0x2000UL) /*!< RSDETIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_SPDETIE_Pos (12UL) /*!< SPDETIE (Bit 12) */
+#define I2C1_INTREN_SPDETIE_Msk (0x1000UL) /*!< SPDETIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_STDETIE_Pos (11UL) /*!< STDETIE (Bit 11) */
+#define I2C1_INTREN_STDETIE_Msk (0x800UL) /*!< STDETIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RXADIE_Pos (10UL) /*!< RXADIE (Bit 10) */
+#define I2C1_INTREN_RXADIE_Msk (0x400UL) /*!< RXADIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_TXADIE_Pos (9UL) /*!< TXADIE (Bit 9) */
+#define I2C1_INTREN_TXADIE_Msk (0x200UL) /*!< TXADIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_MDEIE_Pos (8UL) /*!< MDEIE (Bit 8) */
+#define I2C1_INTREN_MDEIE_Msk (0x100UL) /*!< MDEIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_BUSEIE_Pos (7UL) /*!< BUSEIE (Bit 7) */
+#define I2C1_INTREN_BUSEIE_Msk (0x80UL) /*!< BUSEIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_ARBFIE_Pos (6UL) /*!< ARBFIE (Bit 6) */
+#define I2C1_INTREN_ARBFIE_Msk (0x40UL) /*!< ARBFIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_TXUFIE_Pos (5UL) /*!< TXUFIE (Bit 5) */
+#define I2C1_INTREN_TXUFIE_Msk (0x20UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_TXOFIE_Pos (4UL) /*!< TXOFIE (Bit 4) */
+#define I2C1_INTREN_TXOFIE_Msk (0x10UL) /*!< TXOFIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RXUFIE_Pos (3UL) /*!< RXUFIE (Bit 3) */
+#define I2C1_INTREN_RXUFIE_Msk (0x8UL) /*!< RXUFIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RXOFIE_Pos (2UL) /*!< RXOFIE (Bit 2) */
+#define I2C1_INTREN_RXOFIE_Msk (0x4UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_TXEIE_Pos (1UL) /*!< TXEIE (Bit 1) */
+#define I2C1_INTREN_TXEIE_Msk (0x2UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RXFIE_Pos (0UL) /*!< RXFIE (Bit 0) */
+#define I2C1_INTREN_RXFIE_Msk (0x1UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+/* ========================================================= INTR ========================================================== */
+#define I2C1_INTR_RCNT_Pos (24UL) /*!< RCNT (Bit 24) */
+#define I2C1_INTR_RCNT_Msk (0xff000000UL) /*!< RCNT (Bitfield-Mask: 0xff) */
+#define I2C1_INTR_BTOI_Pos (23UL) /*!< BTOI (Bit 23) */
+#define I2C1_INTR_BTOI_Msk (0x800000UL) /*!< BTOI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_MOHI_Pos (22UL) /*!< MOHI (Bit 22) */
+#define I2C1_INTR_MOHI_Msk (0x400000UL) /*!< MOHI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_SWTXI_Pos (21UL) /*!< SWTXI (Bit 21) */
+#define I2C1_INTR_SWTXI_Msk (0x200000UL) /*!< SWTXI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_MTXAI_Pos (20UL) /*!< MTXAI (Bit 20) */
+#define I2C1_INTR_MTXAI_Msk (0x100000UL) /*!< MTXAI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RXGCI_Pos (19UL) /*!< RXGCI (Bit 19) */
+#define I2C1_INTR_RXGCI_Msk (0x80000UL) /*!< RXGCI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_PECRXI_Pos (18UL) /*!< PECRXI (Bit 18) */
+#define I2C1_INTR_PECRXI_Msk (0x40000UL) /*!< PECRXI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_SEXTOI_Pos (17UL) /*!< SEXTOI (Bit 17) */
+#define I2C1_INTR_SEXTOI_Msk (0x20000UL) /*!< SEXTOI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_MEXTOI_Pos (16UL) /*!< MEXTOI (Bit 16) */
+#define I2C1_INTR_MEXTOI_Msk (0x10000UL) /*!< MEXTOI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_ALDETI_Pos (15UL) /*!< ALDETI (Bit 15) */
+#define I2C1_INTR_ALDETI_Msk (0x8000UL) /*!< ALDETI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_NACKI_Pos (14UL) /*!< NACKI (Bit 14) */
+#define I2C1_INTR_NACKI_Msk (0x4000UL) /*!< NACKI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RSDETI_Pos (13UL) /*!< RSDETI (Bit 13) */
+#define I2C1_INTR_RSDETI_Msk (0x2000UL) /*!< RSDETI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_SPETI_Pos (12UL) /*!< SPETI (Bit 12) */
+#define I2C1_INTR_SPETI_Msk (0x1000UL) /*!< SPETI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_STDETI_Pos (11UL) /*!< STDETI (Bit 11) */
+#define I2C1_INTR_STDETI_Msk (0x800UL) /*!< STDETI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RXADI_Pos (10UL) /*!< RXADI (Bit 10) */
+#define I2C1_INTR_RXADI_Msk (0x400UL) /*!< RXADI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_TXADI_Pos (9UL) /*!< TXADI (Bit 9) */
+#define I2C1_INTR_TXADI_Msk (0x200UL) /*!< TXADI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_MDEI_Pos (8UL) /*!< MDEI (Bit 8) */
+#define I2C1_INTR_MDEI_Msk (0x100UL) /*!< MDEI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_BUSEI_Pos (7UL) /*!< BUSEI (Bit 7) */
+#define I2C1_INTR_BUSEI_Msk (0x80UL) /*!< BUSEI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_ARBFI_Pos (6UL) /*!< ARBFI (Bit 6) */
+#define I2C1_INTR_ARBFI_Msk (0x40UL) /*!< ARBFI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_TXUFI_Pos (5UL) /*!< TXUFI (Bit 5) */
+#define I2C1_INTR_TXUFI_Msk (0x20UL) /*!< TXUFI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_TXOFI_Pos (4UL) /*!< TXOFI (Bit 4) */
+#define I2C1_INTR_TXOFI_Msk (0x10UL) /*!< TXOFI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RXUFI_Pos (3UL) /*!< RXUFI (Bit 3) */
+#define I2C1_INTR_RXUFI_Msk (0x8UL) /*!< RXUFI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RXOFI_Pos (2UL) /*!< RXOFI (Bit 2) */
+#define I2C1_INTR_RXOFI_Msk (0x4UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define I2C1_INTR_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define I2C1_INTR_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define I2C1_STATUS_RFF_Pos (30UL) /*!< RFF (Bit 30) */
+#define I2C1_STATUS_RFF_Msk (0x40000000UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define I2C1_STATUS_RFE_Pos (29UL) /*!< RFE (Bit 29) */
+#define I2C1_STATUS_RFE_Msk (0x20000000UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define I2C1_STATUS_RXFLR_Pos (24UL) /*!< RXFLR (Bit 24) */
+#define I2C1_STATUS_RXFLR_Msk (0x1f000000UL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
+#define I2C1_STATUS_TFF_Pos (22UL) /*!< TFF (Bit 22) */
+#define I2C1_STATUS_TFF_Msk (0x400000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define I2C1_STATUS_TFE_Pos (21UL) /*!< TFE (Bit 21) */
+#define I2C1_STATUS_TFE_Msk (0x200000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define I2C1_STATUS_TXFLR_Pos (16UL) /*!< TXFLR (Bit 16) */
+#define I2C1_STATUS_TXFLR_Msk (0x1f0000UL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
+#define I2C1_STATUS_ARBSTA_Pos (2UL) /*!< ARBSTA (Bit 2) */
+#define I2C1_STATUS_ARBSTA_Msk (0xcUL) /*!< ARBSTA (Bitfield-Mask: 0x03) */
+#define I2C1_STATUS_BUSBSY_Pos (1UL) /*!< BUSBSY (Bit 1) */
+#define I2C1_STATUS_BUSBSY_Msk (0x2UL) /*!< BUSBSY (Bitfield-Mask: 0x01) */
+#define I2C1_STATUS_FSMBSY_Pos (0UL) /*!< FSMBSY (Bit 0) */
+#define I2C1_STATUS_FSMBSY_Msk (0x1UL) /*!< FSMBSY (Bitfield-Mask: 0x01) */
+/* ======================================================== TXDATA ========================================================= */
+#define I2C1_TXDATA_TXDATA_Pos (0UL) /*!< TXDATA (Bit 0) */
+#define I2C1_TXDATA_TXDATA_Msk (0xffUL) /*!< TXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXDATA ========================================================= */
+#define I2C1_RXDATA_RXDATA_Pos (0UL) /*!< RXDATA (Bit 0) */
+#define I2C1_RXDATA_RXDATA_Msk (0xffUL) /*!< RXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXADDR ========================================================= */
+#define I2C1_RXADDR_ADDR_Pos (1UL) /*!< ADDR (Bit 1) */
+#define I2C1_RXADDR_ADDR_Msk (0xfeUL) /*!< ADDR (Bitfield-Mask: 0x7f) */
+#define I2C1_RXADDR_DIR_Pos (0UL) /*!< DIR (Bit 0) */
+#define I2C1_RXADDR_DIR_Msk (0x1UL) /*!< DIR (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ I2C2 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define I2C2_ENABLE_HDRX_Pos (18UL) /*!< HDRX (Bit 18) */
+#define I2C2_ENABLE_HDRX_Msk (0xc0000UL) /*!< HDRX (Bitfield-Mask: 0x03) */
+#define I2C2_ENABLE_NSTCH_Pos (17UL) /*!< NSTCH (Bit 17) */
+#define I2C2_ENABLE_NSTCH_Msk (0x20000UL) /*!< NSTCH (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_MSTCH_Pos (16UL) /*!< MSTCH (Bit 16) */
+#define I2C2_ENABLE_MSTCH_Msk (0x10000UL) /*!< MSTCH (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_SMTOEN_Pos (15UL) /*!< SMTOEN (Bit 15) */
+#define I2C2_ENABLE_SMTOEN_Msk (0x8000UL) /*!< SMTOEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_SMHEN_Pos (14UL) /*!< SMHEN (Bit 14) */
+#define I2C2_ENABLE_SMHEN_Msk (0x4000UL) /*!< SMHEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_SMARPEN_Pos (13UL) /*!< SMARPEN (Bit 13) */
+#define I2C2_ENABLE_SMARPEN_Msk (0x2000UL) /*!< SMARPEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_SMALEN_Pos (12UL) /*!< SMALEN (Bit 12) */
+#define I2C2_ENABLE_SMALEN_Msk (0x1000UL) /*!< SMALEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_OSAEN_Pos (11UL) /*!< OSAEN (Bit 11) */
+#define I2C2_ENABLE_OSAEN_Msk (0x800UL) /*!< OSAEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_GCEN_Pos (10UL) /*!< GCEN (Bit 10) */
+#define I2C2_ENABLE_GCEN_Msk (0x400UL) /*!< GCEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_A10BEN_Pos (9UL) /*!< A10BEN (Bit 9) */
+#define I2C2_ENABLE_A10BEN_Msk (0x200UL) /*!< A10BEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_MSTEN_Pos (8UL) /*!< MSTEN (Bit 8) */
+#define I2C2_ENABLE_MSTEN_Msk (0x100UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_RFHSEN_Pos (7UL) /*!< RFHSEN (Bit 7) */
+#define I2C2_ENABLE_RFHSEN_Msk (0x80UL) /*!< RFHSEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_DMATXEN_Pos (6UL) /*!< DMATXEN (Bit 6) */
+#define I2C2_ENABLE_DMATXEN_Msk (0x40UL) /*!< DMATXEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_DMARXEN_Pos (5UL) /*!< DMARXEN (Bit 5) */
+#define I2C2_ENABLE_DMARXEN_Msk (0x20UL) /*!< DMARXEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_RLSCMD_Pos (4UL) /*!< RLSCMD (Bit 4) */
+#define I2C2_ENABLE_RLSCMD_Msk (0x10UL) /*!< RLSCMD (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_TFRST_Pos (3UL) /*!< TFRST (Bit 3) */
+#define I2C2_ENABLE_TFRST_Msk (0x8UL) /*!< TFRST (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_RFRST_Pos (2UL) /*!< RFRST (Bit 2) */
+#define I2C2_ENABLE_RFRST_Msk (0x4UL) /*!< RFRST (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_UDRCFG_Pos (1UL) /*!< UDRCFG (Bit 1) */
+#define I2C2_ENABLE_UDRCFG_Msk (0x2UL) /*!< UDRCFG (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_I2CEN_Pos (0UL) /*!< I2CEN (Bit 0) */
+#define I2C2_ENABLE_I2CEN_Msk (0x1UL) /*!< I2CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define I2C2_CTRL_AUTOEND_Pos (14UL) /*!< AUTOEND (Bit 14) */
+#define I2C2_CTRL_AUTOEND_Msk (0x4000UL) /*!< AUTOEND (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_MODE10B_Pos (13UL) /*!< MODE10B (Bit 13) */
+#define I2C2_CTRL_MODE10B_Msk (0x2000UL) /*!< MODE10B (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_PECBYTE_Pos (12UL) /*!< PECBYTE (Bit 12) */
+#define I2C2_CTRL_PECBYTE_Msk (0x1000UL) /*!< PECBYTE (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_NACK_Pos (11UL) /*!< NACK (Bit 11) */
+#define I2C2_CTRL_NACK_Msk (0x800UL) /*!< NACK (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_START_Pos (10UL) /*!< START (Bit 10) */
+#define I2C2_CTRL_START_Msk (0x400UL) /*!< START (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_STOP_Pos (9UL) /*!< STOP (Bit 9) */
+#define I2C2_CTRL_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_DIRECT_Pos (8UL) /*!< DIRECT (Bit 8) */
+#define I2C2_CTRL_DIRECT_Msk (0x100UL) /*!< DIRECT (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_I2CCNT_Pos (0UL) /*!< I2CCNT (Bit 0) */
+#define I2C2_CTRL_I2CCNT_Msk (0xffUL) /*!< I2CCNT (Bitfield-Mask: 0xff) */
+/* ========================================================= BAUD ========================================================== */
+#define I2C2_BAUD_SCLHCNT_Pos (16UL) /*!< SCLHCNT (Bit 16) */
+#define I2C2_BAUD_SCLHCNT_Msk (0x3ff0000UL) /*!< SCLHCNT (Bitfield-Mask: 0x3ff) */
+#define I2C2_BAUD_SCLLCNT_Pos (0UL) /*!< SCLLCNT (Bit 0) */
+#define I2C2_BAUD_SCLLCNT_Msk (0x3ffUL) /*!< SCLLCNT (Bitfield-Mask: 0x3ff) */
+/* ========================================================= UDRDR ========================================================= */
+#define I2C2_UDRDR_UDRDR_Pos (0UL) /*!< UDRDR (Bit 0) */
+#define I2C2_UDRDR_UDRDR_Msk (0xffUL) /*!< UDRDR (Bitfield-Mask: 0xff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define I2C2_FIFOCTRL_RXFTLR_Pos (4UL) /*!< RXFTLR (Bit 4) */
+#define I2C2_FIFOCTRL_RXFTLR_Msk (0xf0UL) /*!< RXFTLR (Bitfield-Mask: 0x0f) */
+#define I2C2_FIFOCTRL_TXFTLR_Pos (0UL) /*!< TXFTLR (Bit 0) */
+#define I2C2_FIFOCTRL_TXFTLR_Msk (0xfUL) /*!< TXFTLR (Bitfield-Mask: 0x0f) */
+/* ========================================================== TAR ========================================================== */
+#define I2C2_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define I2C2_TAR_TAR_Msk (0x3ffUL) /*!< TAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== SAR ========================================================== */
+#define I2C2_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define I2C2_SAR_SAR_Msk (0x3ffUL) /*!< SAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================= OSAR ========================================================== */
+#define I2C2_OSAR_OSAM_Pos (16UL) /*!< OSAM (Bit 16) */
+#define I2C2_OSAR_OSAM_Msk (0x3ff0000UL) /*!< OSAM (Bitfield-Mask: 0x3ff) */
+#define I2C2_OSAR_OSAR_Pos (0UL) /*!< OSAR (Bit 0) */
+#define I2C2_OSAR_OSAR_Msk (0x3ffUL) /*!< OSAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== PEC ========================================================== */
+#define I2C2_PEC_IDPEC_Pos (8UL) /*!< IDPEC (Bit 8) */
+#define I2C2_PEC_IDPEC_Msk (0xff00UL) /*!< IDPEC (Bitfield-Mask: 0xff) */
+#define I2C2_PEC_RXPEC_Pos (0UL) /*!< RXPEC (Bit 0) */
+#define I2C2_PEC_RXPEC_Msk (0xffUL) /*!< RXPEC (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMING ========================================================= */
+#define I2C2_TIMING_SPKLEN_Pos (24UL) /*!< SPKLEN (Bit 24) */
+#define I2C2_TIMING_SPKLEN_Msk (0xff000000UL) /*!< SPKLEN (Bitfield-Mask: 0xff) */
+#define I2C2_TIMING_SLVSUDAT_Pos (16UL) /*!< SLVSUDAT (Bit 16) */
+#define I2C2_TIMING_SLVSUDAT_Msk (0xff0000UL) /*!< SLVSUDAT (Bitfield-Mask: 0xff) */
+#define I2C2_TIMING_SUDAT_Pos (8UL) /*!< SUDAT (Bit 8) */
+#define I2C2_TIMING_SUDAT_Msk (0xff00UL) /*!< SUDAT (Bitfield-Mask: 0xff) */
+#define I2C2_TIMING_HDDAT_Pos (0UL) /*!< HDDAT (Bit 0) */
+#define I2C2_TIMING_HDDAT_Msk (0xffUL) /*!< HDDAT (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMEOUT ======================================================== */
+#define I2C2_TIMEOUT_SEXTTO_Pos (16UL) /*!< SEXTTO (Bit 16) */
+#define I2C2_TIMEOUT_SEXTTO_Msk (0xffff0000UL) /*!< SEXTTO (Bitfield-Mask: 0xffff) */
+#define I2C2_TIMEOUT_MEXTTO_Pos (0UL) /*!< MEXTTO (Bit 0) */
+#define I2C2_TIMEOUT_MEXTTO_Msk (0xffffUL) /*!< MEXTTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== BUSTOUT ======================================================== */
+#define I2C2_BUSTOUT_TOSEL_Pos (31UL) /*!< TOSEL (Bit 31) */
+#define I2C2_BUSTOUT_TOSEL_Msk (0x80000000UL) /*!< TOSEL (Bitfield-Mask: 0x01) */
+#define I2C2_BUSTOUT_BTO_Pos (0UL) /*!< BTO (Bit 0) */
+#define I2C2_BUSTOUT_BTO_Msk (0xffffUL) /*!< BTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== INTREN ========================================================= */
+#define I2C2_INTREN_BTOIE_Pos (23UL) /*!< BTOIE (Bit 23) */
+#define I2C2_INTREN_BTOIE_Msk (0x800000UL) /*!< BTOIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_MOHIE_Pos (22UL) /*!< MOHIE (Bit 22) */
+#define I2C2_INTREN_MOHIE_Msk (0x400000UL) /*!< MOHIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_SWTXIE_Pos (21UL) /*!< SWTXIE (Bit 21) */
+#define I2C2_INTREN_SWTXIE_Msk (0x200000UL) /*!< SWTXIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_MTXAIE_Pos (20UL) /*!< MTXAIE (Bit 20) */
+#define I2C2_INTREN_MTXAIE_Msk (0x100000UL) /*!< MTXAIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RXGCIE_Pos (19UL) /*!< RXGCIE (Bit 19) */
+#define I2C2_INTREN_RXGCIE_Msk (0x80000UL) /*!< RXGCIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_PECRXIE_Pos (18UL) /*!< PECRXIE (Bit 18) */
+#define I2C2_INTREN_PECRXIE_Msk (0x40000UL) /*!< PECRXIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_SEXTOIE_Pos (17UL) /*!< SEXTOIE (Bit 17) */
+#define I2C2_INTREN_SEXTOIE_Msk (0x20000UL) /*!< SEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_MEXTOIE_Pos (16UL) /*!< MEXTOIE (Bit 16) */
+#define I2C2_INTREN_MEXTOIE_Msk (0x10000UL) /*!< MEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_ALDETIE_Pos (15UL) /*!< ALDETIE (Bit 15) */
+#define I2C2_INTREN_ALDETIE_Msk (0x8000UL) /*!< ALDETIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_NACKIE_Pos (14UL) /*!< NACKIE (Bit 14) */
+#define I2C2_INTREN_NACKIE_Msk (0x4000UL) /*!< NACKIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RSDETIE_Pos (13UL) /*!< RSDETIE (Bit 13) */
+#define I2C2_INTREN_RSDETIE_Msk (0x2000UL) /*!< RSDETIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_SPDETIE_Pos (12UL) /*!< SPDETIE (Bit 12) */
+#define I2C2_INTREN_SPDETIE_Msk (0x1000UL) /*!< SPDETIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_STDETIE_Pos (11UL) /*!< STDETIE (Bit 11) */
+#define I2C2_INTREN_STDETIE_Msk (0x800UL) /*!< STDETIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RXADIE_Pos (10UL) /*!< RXADIE (Bit 10) */
+#define I2C2_INTREN_RXADIE_Msk (0x400UL) /*!< RXADIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_TXADIE_Pos (9UL) /*!< TXADIE (Bit 9) */
+#define I2C2_INTREN_TXADIE_Msk (0x200UL) /*!< TXADIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_MDEIE_Pos (8UL) /*!< MDEIE (Bit 8) */
+#define I2C2_INTREN_MDEIE_Msk (0x100UL) /*!< MDEIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_BUSEIE_Pos (7UL) /*!< BUSEIE (Bit 7) */
+#define I2C2_INTREN_BUSEIE_Msk (0x80UL) /*!< BUSEIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_ARBFIE_Pos (6UL) /*!< ARBFIE (Bit 6) */
+#define I2C2_INTREN_ARBFIE_Msk (0x40UL) /*!< ARBFIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_TXUFIE_Pos (5UL) /*!< TXUFIE (Bit 5) */
+#define I2C2_INTREN_TXUFIE_Msk (0x20UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_TXOFIE_Pos (4UL) /*!< TXOFIE (Bit 4) */
+#define I2C2_INTREN_TXOFIE_Msk (0x10UL) /*!< TXOFIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RXUFIE_Pos (3UL) /*!< RXUFIE (Bit 3) */
+#define I2C2_INTREN_RXUFIE_Msk (0x8UL) /*!< RXUFIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RXOFIE_Pos (2UL) /*!< RXOFIE (Bit 2) */
+#define I2C2_INTREN_RXOFIE_Msk (0x4UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_TXEIE_Pos (1UL) /*!< TXEIE (Bit 1) */
+#define I2C2_INTREN_TXEIE_Msk (0x2UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RXFIE_Pos (0UL) /*!< RXFIE (Bit 0) */
+#define I2C2_INTREN_RXFIE_Msk (0x1UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+/* ========================================================= INTR ========================================================== */
+#define I2C2_INTR_RCNT_Pos (24UL) /*!< RCNT (Bit 24) */
+#define I2C2_INTR_RCNT_Msk (0xff000000UL) /*!< RCNT (Bitfield-Mask: 0xff) */
+#define I2C2_INTR_BTOI_Pos (23UL) /*!< BTOI (Bit 23) */
+#define I2C2_INTR_BTOI_Msk (0x800000UL) /*!< BTOI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_MOHI_Pos (22UL) /*!< MOHI (Bit 22) */
+#define I2C2_INTR_MOHI_Msk (0x400000UL) /*!< MOHI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_SWTXI_Pos (21UL) /*!< SWTXI (Bit 21) */
+#define I2C2_INTR_SWTXI_Msk (0x200000UL) /*!< SWTXI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_MTXAI_Pos (20UL) /*!< MTXAI (Bit 20) */
+#define I2C2_INTR_MTXAI_Msk (0x100000UL) /*!< MTXAI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RXGCI_Pos (19UL) /*!< RXGCI (Bit 19) */
+#define I2C2_INTR_RXGCI_Msk (0x80000UL) /*!< RXGCI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_PECRXI_Pos (18UL) /*!< PECRXI (Bit 18) */
+#define I2C2_INTR_PECRXI_Msk (0x40000UL) /*!< PECRXI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_SEXTOI_Pos (17UL) /*!< SEXTOI (Bit 17) */
+#define I2C2_INTR_SEXTOI_Msk (0x20000UL) /*!< SEXTOI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_MEXTOI_Pos (16UL) /*!< MEXTOI (Bit 16) */
+#define I2C2_INTR_MEXTOI_Msk (0x10000UL) /*!< MEXTOI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_ALDETI_Pos (15UL) /*!< ALDETI (Bit 15) */
+#define I2C2_INTR_ALDETI_Msk (0x8000UL) /*!< ALDETI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_NACKI_Pos (14UL) /*!< NACKI (Bit 14) */
+#define I2C2_INTR_NACKI_Msk (0x4000UL) /*!< NACKI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RSDETI_Pos (13UL) /*!< RSDETI (Bit 13) */
+#define I2C2_INTR_RSDETI_Msk (0x2000UL) /*!< RSDETI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_SPETI_Pos (12UL) /*!< SPETI (Bit 12) */
+#define I2C2_INTR_SPETI_Msk (0x1000UL) /*!< SPETI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_STDETI_Pos (11UL) /*!< STDETI (Bit 11) */
+#define I2C2_INTR_STDETI_Msk (0x800UL) /*!< STDETI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RXADI_Pos (10UL) /*!< RXADI (Bit 10) */
+#define I2C2_INTR_RXADI_Msk (0x400UL) /*!< RXADI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_TXADI_Pos (9UL) /*!< TXADI (Bit 9) */
+#define I2C2_INTR_TXADI_Msk (0x200UL) /*!< TXADI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_MDEI_Pos (8UL) /*!< MDEI (Bit 8) */
+#define I2C2_INTR_MDEI_Msk (0x100UL) /*!< MDEI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_BUSEI_Pos (7UL) /*!< BUSEI (Bit 7) */
+#define I2C2_INTR_BUSEI_Msk (0x80UL) /*!< BUSEI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_ARBFI_Pos (6UL) /*!< ARBFI (Bit 6) */
+#define I2C2_INTR_ARBFI_Msk (0x40UL) /*!< ARBFI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_TXUFI_Pos (5UL) /*!< TXUFI (Bit 5) */
+#define I2C2_INTR_TXUFI_Msk (0x20UL) /*!< TXUFI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_TXOFI_Pos (4UL) /*!< TXOFI (Bit 4) */
+#define I2C2_INTR_TXOFI_Msk (0x10UL) /*!< TXOFI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RXUFI_Pos (3UL) /*!< RXUFI (Bit 3) */
+#define I2C2_INTR_RXUFI_Msk (0x8UL) /*!< RXUFI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RXOFI_Pos (2UL) /*!< RXOFI (Bit 2) */
+#define I2C2_INTR_RXOFI_Msk (0x4UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define I2C2_INTR_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define I2C2_INTR_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define I2C2_STATUS_RFF_Pos (30UL) /*!< RFF (Bit 30) */
+#define I2C2_STATUS_RFF_Msk (0x40000000UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define I2C2_STATUS_RFE_Pos (29UL) /*!< RFE (Bit 29) */
+#define I2C2_STATUS_RFE_Msk (0x20000000UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define I2C2_STATUS_RXFLR_Pos (24UL) /*!< RXFLR (Bit 24) */
+#define I2C2_STATUS_RXFLR_Msk (0x1f000000UL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
+#define I2C2_STATUS_TFF_Pos (22UL) /*!< TFF (Bit 22) */
+#define I2C2_STATUS_TFF_Msk (0x400000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define I2C2_STATUS_TFE_Pos (21UL) /*!< TFE (Bit 21) */
+#define I2C2_STATUS_TFE_Msk (0x200000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define I2C2_STATUS_TXFLR_Pos (16UL) /*!< TXFLR (Bit 16) */
+#define I2C2_STATUS_TXFLR_Msk (0x1f0000UL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
+#define I2C2_STATUS_ARBSTA_Pos (2UL) /*!< ARBSTA (Bit 2) */
+#define I2C2_STATUS_ARBSTA_Msk (0xcUL) /*!< ARBSTA (Bitfield-Mask: 0x03) */
+#define I2C2_STATUS_BUSBSY_Pos (1UL) /*!< BUSBSY (Bit 1) */
+#define I2C2_STATUS_BUSBSY_Msk (0x2UL) /*!< BUSBSY (Bitfield-Mask: 0x01) */
+#define I2C2_STATUS_FSMBSY_Pos (0UL) /*!< FSMBSY (Bit 0) */
+#define I2C2_STATUS_FSMBSY_Msk (0x1UL) /*!< FSMBSY (Bitfield-Mask: 0x01) */
+/* ======================================================== TXDATA ========================================================= */
+#define I2C2_TXDATA_TXDATA_Pos (0UL) /*!< TXDATA (Bit 0) */
+#define I2C2_TXDATA_TXDATA_Msk (0xffUL) /*!< TXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXDATA ========================================================= */
+#define I2C2_RXDATA_RXDATA_Pos (0UL) /*!< RXDATA (Bit 0) */
+#define I2C2_RXDATA_RXDATA_Msk (0xffUL) /*!< RXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXADDR ========================================================= */
+#define I2C2_RXADDR_ADDR_Pos (1UL) /*!< ADDR (Bit 1) */
+#define I2C2_RXADDR_ADDR_Msk (0xfeUL) /*!< ADDR (Bitfield-Mask: 0x7f) */
+#define I2C2_RXADDR_DIR_Pos (0UL) /*!< DIR (Bit 0) */
+#define I2C2_RXADDR_DIR_Msk (0x1UL) /*!< DIR (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV0_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV0_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV0_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV0_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV0_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV0_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV0_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV0_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV0_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV0_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV0_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV0_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV0_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV0_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV0_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV0_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV0_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV0_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV0_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV0_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV0_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV0_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV0_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV0_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV0_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV0_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV0_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV0_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV0_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV0_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV0_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV0_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV0_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV0_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV0_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV0_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV0_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV0_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV0_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV0_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV0_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV0_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV0_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV0_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV0_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV0_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV0_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV0_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV0_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV0_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV0_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV0_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV0_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV0_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV0_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV0_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV0_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV0_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV0_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV0_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV0_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV0_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV0_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV0_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV0_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV0_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV0_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV0_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV0_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV0_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV0_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV0_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV0_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV0_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV0_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV0_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV0_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV0_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV0_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV0_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV0_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV0_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV0_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV0_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV0_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV0_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV0_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV0_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV0_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV0_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV0_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV0_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV0_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV0_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV0_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV0_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV0_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV0_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV0_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV0_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV0_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV0_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV0_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV0_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV0_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV0_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV0_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV0_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV0_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV0_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV0_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV0_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV0_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV0_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV0_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV0_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV0_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV0_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV0_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV0_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV0_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV0_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV0_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV0_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV0_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV0_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV0_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV0_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV0_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV0_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV0_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV0_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV0_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV0_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV0_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV0_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV0_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV0_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV0_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV0_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV0_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV0_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV0_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV0_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV0_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV0_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV0_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV0_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV0_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV0_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV0_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV0_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV0_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV0_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV0_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV0_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV0_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV0_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV0_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV0_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV0_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV0_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV0_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV0_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV0_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV0_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV0_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV0_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV0_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV0_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV0_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV0_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV0_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV0_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV0_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV0_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV0_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV0_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV0_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV0_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV0_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV0_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV0_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV0_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV0_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV0_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV0_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV0_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV0_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV0_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV0_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV0_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV0_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV0_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV0_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV0_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV0_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV0_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV0_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV0_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV0_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV0_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV0_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV0_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV0_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV0_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV0_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV0_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV0_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV0_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV0_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV0_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV0_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV0_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV0_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV0_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV0_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV0_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV0_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV0_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV0_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV0_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV0_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV0_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV0_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV0_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV0_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV0_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV0_RSTR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV0_RSTR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV4CMPD_Pos (30UL) /*!< SLV4CMPD (Bit 30) */
+#define HRPWM_SLV0_RSTR_SLV4CMPD_Msk (0x40000000UL) /*!< SLV4CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV4CMPB_Pos (29UL) /*!< SLV4CMPB (Bit 29) */
+#define HRPWM_SLV0_RSTR_SLV4CMPB_Msk (0x20000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV4CMPA_Pos (28UL) /*!< SLV4CMPA (Bit 28) */
+#define HRPWM_SLV0_RSTR_SLV4CMPA_Msk (0x10000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV3CMPD_Pos (27UL) /*!< SLV3CMPD (Bit 27) */
+#define HRPWM_SLV0_RSTR_SLV3CMPD_Msk (0x8000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV3CMPB_Pos (26UL) /*!< SLV3CMPB (Bit 26) */
+#define HRPWM_SLV0_RSTR_SLV3CMPB_Msk (0x4000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV3CMPA_Pos (25UL) /*!< SLV3CMPA (Bit 25) */
+#define HRPWM_SLV0_RSTR_SLV3CMPA_Msk (0x2000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV2CMPD_Pos (24UL) /*!< SLV2CMPD (Bit 24) */
+#define HRPWM_SLV0_RSTR_SLV2CMPD_Msk (0x1000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV0_RSTR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV0_RSTR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV1CMPD_Pos (21UL) /*!< SLV1CMPD (Bit 21) */
+#define HRPWM_SLV0_RSTR_SLV1CMPD_Msk (0x200000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV1CMPB_Pos (20UL) /*!< SLV1CMPB (Bit 20) */
+#define HRPWM_SLV0_RSTR_SLV1CMPB_Msk (0x100000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV1CMPA_Pos (19UL) /*!< SLV1CMPA (Bit 19) */
+#define HRPWM_SLV0_RSTR_SLV1CMPA_Msk (0x80000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV0_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV0_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV0_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV0_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV0_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV0_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV0_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV0_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV0_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV0_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV0_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV0_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV0_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV0_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV0_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV0_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV0_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV0_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV0_RSTR_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV0_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV0_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV0_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV0_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV0_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV0_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV0_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV0_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV0_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV0_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV0_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV0_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV0_CAPACR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV0_CAPACR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV0_CAPACR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV0_CAPACR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV0_CAPACR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV0_CAPACR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV0_CAPACR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV0_CAPACR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV0_CAPACR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV0_CAPACR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV0_CAPACR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV0_CAPACR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV0_CAPACR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV2CMPB_Pos (19UL) /*!< SLV2CMPB (Bit 19) */
+#define HRPWM_SLV0_CAPACR_SLV2CMPB_Msk (0x80000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV2CMPA_Pos (18UL) /*!< SLV2CMPA (Bit 18) */
+#define HRPWM_SLV0_CAPACR_SLV2CMPA_Msk (0x40000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV2CLRA_Pos (17UL) /*!< SLV2CLRA (Bit 17) */
+#define HRPWM_SLV0_CAPACR_SLV2CLRA_Msk (0x20000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV2SETA_Pos (16UL) /*!< SLV2SETA (Bit 16) */
+#define HRPWM_SLV0_CAPACR_SLV2SETA_Msk (0x10000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV1CMPB_Pos (15UL) /*!< SLV1CMPB (Bit 15) */
+#define HRPWM_SLV0_CAPACR_SLV1CMPB_Msk (0x8000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV1CMPA_Pos (14UL) /*!< SLV1CMPA (Bit 14) */
+#define HRPWM_SLV0_CAPACR_SLV1CMPA_Msk (0x4000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV1CLRA_Pos (13UL) /*!< SLV1CLRA (Bit 13) */
+#define HRPWM_SLV0_CAPACR_SLV1CLRA_Msk (0x2000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV1SETA_Pos (12UL) /*!< SLV1SETA (Bit 12) */
+#define HRPWM_SLV0_CAPACR_SLV1SETA_Msk (0x1000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV0_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV0_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV0_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV0_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV0_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV0_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV0_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV0_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV0_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV0_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV0_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV0_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV0_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV0_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV0_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV0_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV0_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV0_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV0_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV0_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV0_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV0_CAPBCR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV0_CAPBCR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV0_CAPBCR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV0_CAPBCR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV0_CAPBCR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV0_CAPBCR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV0_CAPBCR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV0_CAPBCR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV0_CAPBCR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV0_CAPBCR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV0_CAPBCR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV0_CAPBCR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV0_CAPBCR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV2CMPB_Pos (19UL) /*!< SLV2CMPB (Bit 19) */
+#define HRPWM_SLV0_CAPBCR_SLV2CMPB_Msk (0x80000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV2CMPA_Pos (18UL) /*!< SLV2CMPA (Bit 18) */
+#define HRPWM_SLV0_CAPBCR_SLV2CMPA_Msk (0x40000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV2CLRA_Pos (17UL) /*!< SLV2CLRA (Bit 17) */
+#define HRPWM_SLV0_CAPBCR_SLV2CLRA_Msk (0x20000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV2SETA_Pos (16UL) /*!< SLV2SETA (Bit 16) */
+#define HRPWM_SLV0_CAPBCR_SLV2SETA_Msk (0x10000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV1CMPB_Pos (15UL) /*!< SLV1CMPB (Bit 15) */
+#define HRPWM_SLV0_CAPBCR_SLV1CMPB_Msk (0x8000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV1CMPA_Pos (14UL) /*!< SLV1CMPA (Bit 14) */
+#define HRPWM_SLV0_CAPBCR_SLV1CMPA_Msk (0x4000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV1CLRA_Pos (13UL) /*!< SLV1CLRA (Bit 13) */
+#define HRPWM_SLV0_CAPBCR_SLV1CLRA_Msk (0x2000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV1SETA_Pos (12UL) /*!< SLV1SETA (Bit 12) */
+#define HRPWM_SLV0_CAPBCR_SLV1SETA_Msk (0x1000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV0_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV0_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV0_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV0_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV0_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV0_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV0_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV0_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV0_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV0_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV0_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV0_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV0_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV0_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV0_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV0_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV0_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV0_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV0_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV0_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV0_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV0_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV0_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV0_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV0_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV0_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV0_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV0_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV0_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV0_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV0_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV0_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV0_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV0_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV0_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV0_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV0_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV0_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV0_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV0_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV0_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV0_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV0_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV0_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV0_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV0_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV0_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV0_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV0_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV0_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV0_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV0_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV0_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV0_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV0_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV0_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV0_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV0_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV0_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV0_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV0_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV0_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV0_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV0_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV0_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV0_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV0_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV0_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV0_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV0_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV0_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV1_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV1_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV1_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV1_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV1_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV1_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV1_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV1_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV1_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV1_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV1_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV1_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV1_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV1_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV1_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV1_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV1_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV1_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV1_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV1_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV1_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV1_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV1_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV1_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV1_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV1_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV1_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV1_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV1_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV1_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV1_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV1_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV1_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV1_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV1_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV1_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV1_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV1_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV1_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV1_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV1_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV1_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV1_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV1_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV1_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV1_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV1_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV1_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV1_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV1_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV1_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV1_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV1_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV1_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV1_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV1_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV1_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV1_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV1_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV1_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV1_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV1_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV1_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV1_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV1_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV1_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV1_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV1_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV1_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV1_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV1_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV1_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV1_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV1_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV1_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV1_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV1_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV1_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV1_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV1_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV1_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV1_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV1_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV1_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV1_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV1_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV1_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV1_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV1_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV1_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV1_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV1_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV1_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV1_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV1_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV1_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV1_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV1_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV1_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV1_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV1_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV1_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV1_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV1_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV1_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV1_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV1_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV1_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV1_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV1_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV1_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV1_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV1_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV1_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV1_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV1_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV1_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV1_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV1_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV1_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV1_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV1_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV1_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV1_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV1_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV1_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV1_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV1_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV1_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV1_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV1_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV1_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV1_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV1_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV1_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV1_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV1_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV1_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV1_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV1_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV1_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV1_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV1_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV1_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV1_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV1_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV1_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV1_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV1_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV1_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV1_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV1_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV1_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV1_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV1_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV1_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV1_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV1_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV1_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV1_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV1_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV1_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV1_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV1_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV1_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV1_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV1_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV1_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV1_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV1_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV1_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV1_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV1_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV1_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV1_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV1_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV1_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV1_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV1_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV1_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV1_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV1_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV1_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV1_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV1_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV1_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV1_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV1_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV1_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV1_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV1_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV1_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV1_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV1_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV1_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV1_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV1_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV1_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV1_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV1_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV1_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV1_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV1_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV1_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV1_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV1_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV1_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV1_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV1_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV1_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV1_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV1_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV1_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV1_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV1_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV1_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV1_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV1_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV1_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV1_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV1_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV1_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV1_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV1_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV1_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV1_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV1_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV1_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV1_RSTR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV1_RSTR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV4CMPD_Pos (30UL) /*!< SLV4CMPD (Bit 30) */
+#define HRPWM_SLV1_RSTR_SLV4CMPD_Msk (0x40000000UL) /*!< SLV4CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV4CMPB_Pos (29UL) /*!< SLV4CMPB (Bit 29) */
+#define HRPWM_SLV1_RSTR_SLV4CMPB_Msk (0x20000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV4CMPA_Pos (28UL) /*!< SLV4CMPA (Bit 28) */
+#define HRPWM_SLV1_RSTR_SLV4CMPA_Msk (0x10000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV3CMPD_Pos (27UL) /*!< SLV3CMPD (Bit 27) */
+#define HRPWM_SLV1_RSTR_SLV3CMPD_Msk (0x8000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV3CMPB_Pos (26UL) /*!< SLV3CMPB (Bit 26) */
+#define HRPWM_SLV1_RSTR_SLV3CMPB_Msk (0x4000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV3CMPA_Pos (25UL) /*!< SLV3CMPA (Bit 25) */
+#define HRPWM_SLV1_RSTR_SLV3CMPA_Msk (0x2000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV2CMPD_Pos (24UL) /*!< SLV2CMPD (Bit 24) */
+#define HRPWM_SLV1_RSTR_SLV2CMPD_Msk (0x1000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV1_RSTR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV1_RSTR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV1_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV1_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV1_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV1_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV1_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV1_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV1_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV1_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV1_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV1_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV1_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV1_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV1_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV1_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV1_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV1_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV1_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV1_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV1_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV1_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV1_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV1_RSTR_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV1_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV1_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV1_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV1_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV1_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV1_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV1_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV1_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV1_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV1_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV1_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV1_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV1_CAPACR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV1_CAPACR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV1_CAPACR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV1_CAPACR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV1_CAPACR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV1_CAPACR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV1_CAPACR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV1_CAPACR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV1_CAPACR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV1_CAPACR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV1_CAPACR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV1_CAPACR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV1_CAPACR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV2CMPB_Pos (19UL) /*!< SLV2CMPB (Bit 19) */
+#define HRPWM_SLV1_CAPACR_SLV2CMPB_Msk (0x80000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV2CMPA_Pos (18UL) /*!< SLV2CMPA (Bit 18) */
+#define HRPWM_SLV1_CAPACR_SLV2CMPA_Msk (0x40000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV2CLRA_Pos (17UL) /*!< SLV2CLRA (Bit 17) */
+#define HRPWM_SLV1_CAPACR_SLV2CLRA_Msk (0x20000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV2SETA_Pos (16UL) /*!< SLV2SETA (Bit 16) */
+#define HRPWM_SLV1_CAPACR_SLV2SETA_Msk (0x10000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV1_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV1_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV1_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV1_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV1_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV1_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV1_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV1_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV1_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV1_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV1_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV1_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV1_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV1_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV1_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV1_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV1_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV1_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV1_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV1_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV1_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV1_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV1_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV1_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV1_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV1_CAPBCR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV1_CAPBCR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV1_CAPBCR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV1_CAPBCR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV1_CAPBCR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV1_CAPBCR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV1_CAPBCR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV1_CAPBCR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV1_CAPBCR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV1_CAPBCR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV1_CAPBCR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV1_CAPBCR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV1_CAPBCR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV2CMPB_Pos (19UL) /*!< SLV2CMPB (Bit 19) */
+#define HRPWM_SLV1_CAPBCR_SLV2CMPB_Msk (0x80000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV2CMPA_Pos (18UL) /*!< SLV2CMPA (Bit 18) */
+#define HRPWM_SLV1_CAPBCR_SLV2CMPA_Msk (0x40000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV2CLRA_Pos (17UL) /*!< SLV2CLRA (Bit 17) */
+#define HRPWM_SLV1_CAPBCR_SLV2CLRA_Msk (0x20000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV2SETA_Pos (16UL) /*!< SLV2SETA (Bit 16) */
+#define HRPWM_SLV1_CAPBCR_SLV2SETA_Msk (0x10000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV1_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV1_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV1_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV1_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV1_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV1_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV1_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV1_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV1_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV1_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV1_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV1_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV1_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV1_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV1_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV1_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV1_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV1_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV1_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV1_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV1_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV1_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV1_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV1_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV1_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV1_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV1_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV1_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV1_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV1_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV1_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV1_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV1_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV1_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV1_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV1_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV1_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV1_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV1_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV1_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV1_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV1_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV1_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV1_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV1_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV1_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV1_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV1_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV1_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV1_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV1_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV1_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV1_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV1_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV1_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV1_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV1_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV1_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV1_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV1_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV1_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV1_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV1_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV1_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV1_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV1_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV1_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV1_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV1_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV1_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV1_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV1_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV1_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV1_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV1_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV2 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV2_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV2_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV2_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV2_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV2_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV2_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV2_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV2_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV2_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV2_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV2_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV2_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV2_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV2_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV2_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV2_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV2_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV2_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV2_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV2_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV2_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV2_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV2_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV2_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV2_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV2_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV2_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV2_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV2_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV2_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV2_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV2_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV2_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV2_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV2_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV2_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV2_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV2_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV2_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV2_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV2_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV2_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV2_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV2_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV2_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV2_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV2_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV2_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV2_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV2_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV2_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV2_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV2_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV2_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV2_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV2_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV2_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV2_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV2_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV2_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV2_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV2_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV2_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV2_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV2_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV2_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV2_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV2_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV2_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV2_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV2_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV2_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV2_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV2_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV2_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV2_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV2_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV2_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV2_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV2_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV2_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV2_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV2_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV2_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV2_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV2_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV2_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV2_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV2_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV2_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV2_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV2_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV2_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV2_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV2_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV2_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV2_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV2_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV2_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV2_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV2_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV2_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV2_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV2_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV2_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV2_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV2_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV2_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV2_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV2_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV2_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV2_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV2_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV2_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV2_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV2_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV2_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV2_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV2_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV2_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV2_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV2_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV2_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV2_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV2_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV2_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV2_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV2_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV2_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV2_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV2_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV2_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV2_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV2_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV2_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV2_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV2_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV2_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV2_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV2_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV2_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV2_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV2_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV2_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV2_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV2_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV2_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV2_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV2_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV2_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV2_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV2_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV2_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV2_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV2_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV2_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV2_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV2_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV2_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV2_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV2_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV2_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV2_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV2_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV2_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV2_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV2_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV2_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV2_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV2_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV2_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV2_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV2_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV2_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV2_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV2_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV2_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV2_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV2_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV2_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV2_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV2_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV2_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV2_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV2_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV2_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV2_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV2_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV2_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV2_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV2_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV2_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV2_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV2_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV2_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV2_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV2_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV2_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV2_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV2_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV2_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV2_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV2_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV2_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV2_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV2_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV2_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV2_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV2_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV2_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV2_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV2_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV2_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV2_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV2_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV2_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV2_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV2_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV2_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV2_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV2_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV2_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV2_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV2_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV2_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV2_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV2_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV2_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV2_RSTR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV2_RSTR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV4CMPD_Pos (30UL) /*!< SLV4CMPD (Bit 30) */
+#define HRPWM_SLV2_RSTR_SLV4CMPD_Msk (0x40000000UL) /*!< SLV4CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV4CMPB_Pos (29UL) /*!< SLV4CMPB (Bit 29) */
+#define HRPWM_SLV2_RSTR_SLV4CMPB_Msk (0x20000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV4CMPA_Pos (28UL) /*!< SLV4CMPA (Bit 28) */
+#define HRPWM_SLV2_RSTR_SLV4CMPA_Msk (0x10000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV3CMPD_Pos (27UL) /*!< SLV3CMPD (Bit 27) */
+#define HRPWM_SLV2_RSTR_SLV3CMPD_Msk (0x8000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV3CMPB_Pos (26UL) /*!< SLV3CMPB (Bit 26) */
+#define HRPWM_SLV2_RSTR_SLV3CMPB_Msk (0x4000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV3CMPA_Pos (25UL) /*!< SLV3CMPA (Bit 25) */
+#define HRPWM_SLV2_RSTR_SLV3CMPA_Msk (0x2000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV2_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV2_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV2_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV2_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV2_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV2_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV2_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV2_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV2_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV2_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV2_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV2_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV2_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV2_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV2_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV2_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV2_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV2_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV2_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV2_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV2_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV2_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV2_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV2_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV2_RSTR_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV2_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV2_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV2_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV2_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV2_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV2_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV2_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV2_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV2_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV2_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV2_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV2_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV2_CAPACR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV2_CAPACR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV2_CAPACR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV2_CAPACR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV2_CAPACR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV2_CAPACR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV2_CAPACR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV2_CAPACR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV2_CAPACR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV2_CAPACR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV2_CAPACR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV2_CAPACR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV2_CAPACR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV2_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV2_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV2_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV2_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV2_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV2_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV2_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV2_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV2_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV2_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV2_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV2_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV2_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV2_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV2_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV2_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV2_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV2_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV2_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV2_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV2_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV2_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV2_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV2_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV2_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV2_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV2_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV2_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV2_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV2_CAPBCR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV2_CAPBCR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV2_CAPBCR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV2_CAPBCR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV2_CAPBCR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV2_CAPBCR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV2_CAPBCR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV2_CAPBCR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV2_CAPBCR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV2_CAPBCR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV2_CAPBCR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV2_CAPBCR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV2_CAPBCR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV2_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV2_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV2_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV2_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV2_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV2_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV2_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV2_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV2_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV2_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV2_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV2_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV2_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV2_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV2_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV2_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV2_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV2_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV2_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV2_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV2_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV2_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV2_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV2_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV2_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV2_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV2_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV2_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV2_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV2_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV2_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV2_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV2_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV2_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV2_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV2_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV2_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV2_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV2_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV2_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV2_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV2_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV2_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV2_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV2_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV2_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV2_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV2_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV2_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV2_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV2_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV2_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV2_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV2_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV2_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV2_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV2_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV2_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV2_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV2_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV2_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV2_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV2_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV2_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV2_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV2_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV2_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV2_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV2_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV2_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV2_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV2_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV2_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV2_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV2_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV2_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV2_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV2_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV2_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV3 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV3_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV3_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV3_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV3_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV3_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV3_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV3_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV3_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV3_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV3_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV3_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV3_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV3_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV3_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV3_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV3_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV3_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV3_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV3_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV3_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV3_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV3_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV3_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV3_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV3_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV3_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV3_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV3_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV3_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV3_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV3_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV3_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV3_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV3_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV3_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV3_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV3_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV3_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV3_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV3_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV3_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV3_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV3_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV3_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV3_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV3_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV3_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV3_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV3_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV3_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV3_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV3_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV3_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV3_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV3_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV3_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV3_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV3_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV3_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV3_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV3_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV3_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV3_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV3_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV3_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV3_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV3_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV3_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV3_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV3_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV3_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV3_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV3_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV3_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV3_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV3_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV3_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV3_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV3_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV3_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV3_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV3_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV3_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV3_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV3_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV3_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV3_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV3_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV3_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV3_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV3_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV3_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV3_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV3_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV3_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV3_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV3_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV3_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV3_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV3_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV3_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV3_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV3_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV3_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV3_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV3_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV3_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV3_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV3_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV3_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV3_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV3_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV3_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV3_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV3_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV3_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV3_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV3_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV3_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV3_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV3_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV3_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV3_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV3_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV3_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV3_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV3_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV3_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV3_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV3_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV3_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV3_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV3_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV3_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV3_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV3_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV3_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV3_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV3_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV3_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV3_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV3_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV3_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV3_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV3_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV3_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV3_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV3_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV3_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV3_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV3_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV3_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV3_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV3_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV3_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV3_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV3_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV3_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV3_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV3_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV3_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV3_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV3_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV3_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV3_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV3_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV3_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV3_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV3_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV3_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV3_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV3_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV3_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV3_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV3_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV3_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV3_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV3_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV3_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV3_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV3_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV3_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV3_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV3_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV3_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV3_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV3_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV3_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV3_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV3_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV3_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV3_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV3_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV3_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV3_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV3_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV3_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV3_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV3_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV3_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV3_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV3_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV3_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV3_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV3_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV3_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV3_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV3_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV3_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV3_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV3_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV3_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV3_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV3_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV3_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV3_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV3_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV3_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV3_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV3_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV3_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV3_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV3_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV3_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV3_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV3_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV3_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV3_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV3_RSTR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV3_RSTR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV4CMPD_Pos (30UL) /*!< SLV4CMPD (Bit 30) */
+#define HRPWM_SLV3_RSTR_SLV4CMPD_Msk (0x40000000UL) /*!< SLV4CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV4CMPB_Pos (29UL) /*!< SLV4CMPB (Bit 29) */
+#define HRPWM_SLV3_RSTR_SLV4CMPB_Msk (0x20000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV4CMPA_Pos (28UL) /*!< SLV4CMPA (Bit 28) */
+#define HRPWM_SLV3_RSTR_SLV4CMPA_Msk (0x10000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV2CMPD_Pos (27UL) /*!< SLV2CMPD (Bit 27) */
+#define HRPWM_SLV3_RSTR_SLV2CMPD_Msk (0x8000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV2CMPB_Pos (26UL) /*!< SLV2CMPB (Bit 26) */
+#define HRPWM_SLV3_RSTR_SLV2CMPB_Msk (0x4000000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV2CMPA_Pos (25UL) /*!< SLV2CMPA (Bit 25) */
+#define HRPWM_SLV3_RSTR_SLV2CMPA_Msk (0x2000000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV3_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV3_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV3_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV3_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV3_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV3_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV3_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV3_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV3_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV3_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV3_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV3_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV3_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV3_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV3_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV3_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV3_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV3_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV3_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV3_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV3_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV3_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV3_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV3_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV3_RSTR_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV3_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV3_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV3_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV3_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV3_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV3_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV3_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV3_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV3_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV3_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV3_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV3_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV3_CAPACR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV3_CAPACR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV3_CAPACR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV3_CAPACR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV3_CAPACR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV3_CAPACR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV3_CAPACR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV3_CAPACR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV3_CAPACR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV3_CAPACR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV3_CAPACR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV3_CAPACR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV3_CAPACR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV3_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV3_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV3_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV3_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV3_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV3_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV3_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV3_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV3_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV3_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV3_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV3_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV3_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV3_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV3_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV3_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV3_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV3_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV3_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV3_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV3_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV3_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV3_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV3_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV3_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV3_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV3_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV3_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV3_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV3_CAPBCR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV3_CAPBCR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV3_CAPBCR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV3_CAPBCR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV3_CAPBCR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV3_CAPBCR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV3_CAPBCR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV3_CAPBCR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV3_CAPBCR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV3_CAPBCR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV3_CAPBCR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV3_CAPBCR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV3_CAPBCR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV3_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV3_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV3_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV3_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV3_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV3_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV3_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV3_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV3_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV3_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV3_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV3_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV3_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV3_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV3_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV3_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV3_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV3_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV3_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV3_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV3_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV3_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV3_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV3_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV3_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV3_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV3_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV3_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV3_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV3_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV3_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV3_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV3_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV3_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV3_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV3_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV3_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV3_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV3_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV3_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV3_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV3_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV3_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV3_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV3_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV3_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV3_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV3_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV3_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV3_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV3_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV3_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV3_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV3_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV3_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV3_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV3_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV3_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV3_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV3_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV3_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV3_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV3_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV3_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV3_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV3_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV3_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV3_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV3_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV3_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV3_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV3_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV3_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV3_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV3_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV3_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV3_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV3_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV3_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV4 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV4_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV4_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV4_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV4_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV4_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV4_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV4_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV4_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV4_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV4_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV4_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV4_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV4_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV4_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV4_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV4_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV4_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV4_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV4_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV4_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV4_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV4_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV4_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV4_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV4_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV4_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV4_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV4_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV4_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV4_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV4_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV4_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV4_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV4_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV4_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV4_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV4_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV4_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV4_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV4_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV4_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV4_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV4_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV4_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV4_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV4_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV4_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV4_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV4_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV4_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV4_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV4_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV4_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV4_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV4_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV4_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV4_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV4_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV4_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV4_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV4_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV4_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV4_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV4_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV4_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV4_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV4_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV4_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV4_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV4_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV4_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV4_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV4_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV4_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV4_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV4_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV4_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV4_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV4_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV4_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV4_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV4_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV4_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV4_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV4_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV4_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV4_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV4_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV4_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV4_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV4_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV4_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV4_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV4_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV4_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV4_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV4_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV4_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV4_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV4_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV4_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV4_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV4_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV4_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV4_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV4_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV4_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV4_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV4_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV4_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV4_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV4_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV4_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV4_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV4_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV4_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV4_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV4_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV4_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV4_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV4_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV4_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV4_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV4_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV4_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV4_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV4_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV4_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV4_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV4_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV4_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV4_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV4_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV4_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV4_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV4_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV4_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV4_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV4_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV4_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV4_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV4_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV4_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV4_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV4_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV4_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV4_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV4_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV4_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV4_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV4_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV4_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV4_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV4_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV4_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV4_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV4_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV4_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV4_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV4_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV4_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV4_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV4_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV4_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV4_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV4_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV4_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV4_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV4_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV4_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV4_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV4_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV4_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV4_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV4_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV4_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV4_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV4_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV4_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV4_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV4_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV4_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV4_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV4_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV4_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV4_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV4_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV4_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV4_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV4_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV4_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV4_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV4_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV4_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV4_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV4_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV4_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV4_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV4_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV4_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV4_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV4_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV4_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV4_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV4_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV4_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV4_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV4_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV4_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV4_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV4_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV4_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV4_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV4_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV4_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV4_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV4_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV4_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV4_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV4_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV4_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV4_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV4_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV4_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV4_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV4_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV4_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV4_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV4_RSTR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV4_RSTR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV3CMPD_Pos (30UL) /*!< SLV3CMPD (Bit 30) */
+#define HRPWM_SLV4_RSTR_SLV3CMPD_Msk (0x40000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV3CMPB_Pos (29UL) /*!< SLV3CMPB (Bit 29) */
+#define HRPWM_SLV4_RSTR_SLV3CMPB_Msk (0x20000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV3CMPA_Pos (28UL) /*!< SLV3CMPA (Bit 28) */
+#define HRPWM_SLV4_RSTR_SLV3CMPA_Msk (0x10000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV2CMPD_Pos (27UL) /*!< SLV2CMPD (Bit 27) */
+#define HRPWM_SLV4_RSTR_SLV2CMPD_Msk (0x8000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV2CMPB_Pos (26UL) /*!< SLV2CMPB (Bit 26) */
+#define HRPWM_SLV4_RSTR_SLV2CMPB_Msk (0x4000000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV2CMPA_Pos (25UL) /*!< SLV2CMPA (Bit 25) */
+#define HRPWM_SLV4_RSTR_SLV2CMPA_Msk (0x2000000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV4_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV4_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV4_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV4_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV4_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV4_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV4_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV4_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV4_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV4_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV4_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV4_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV4_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV4_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV4_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV4_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV4_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV4_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV4_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV4_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV4_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV4_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV4_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV4_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV4_RSTR_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV4_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV4_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV4_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV4_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV4_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV4_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV4_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV4_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV4_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV4_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV4_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV4_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV4_CAPACR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV4_CAPACR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV4_CAPACR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV4_CAPACR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV4_CAPACR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV4_CAPACR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV4_CAPACR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV4_CAPACR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV4_CAPACR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV4_CAPACR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV4_CAPACR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV4_CAPACR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV4_CAPACR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV4_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV4_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV4_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV4_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV4_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV4_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV4_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV4_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV4_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV4_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV4_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV4_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV4_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV4_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV4_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV4_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV4_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV4_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV4_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV4_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV4_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV4_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV4_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV4_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV4_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV4_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV4_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV4_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV4_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV4_CAPBCR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV4_CAPBCR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV4_CAPBCR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV4_CAPBCR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV4_CAPBCR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV4_CAPBCR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV4_CAPBCR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV4_CAPBCR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV4_CAPBCR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV4_CAPBCR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV4_CAPBCR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV4_CAPBCR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV4_CAPBCR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV4_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV4_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV4_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV4_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV4_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV4_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV4_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV4_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV4_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV4_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV4_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV4_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV4_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV4_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV4_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV4_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV4_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV4_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV4_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV4_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV4_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV4_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV4_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV4_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV4_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV4_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV4_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV4_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV4_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV4_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV4_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV4_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV4_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV4_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV4_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV4_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV4_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV4_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV4_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV4_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV4_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV4_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV4_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV4_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV4_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV4_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV4_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV4_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV4_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV4_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV4_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV4_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV4_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV4_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV4_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV4_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV4_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV4_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV4_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV4_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV4_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV4_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV4_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV4_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV4_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV4_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV4_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV4_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV4_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV4_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV4_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV4_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV4_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV4_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV4_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV4_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV4_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV4_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV4_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV5 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV5_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV5_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV5_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV5_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV5_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV5_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV5_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV5_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV5_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV5_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV5_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV5_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV5_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV5_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV5_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV5_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV5_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV5_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV5_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV5_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV5_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV5_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV5_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV5_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV5_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV5_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV5_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV5_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV5_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV5_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV5_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV5_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV5_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV5_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV5_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV5_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV5_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV5_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV5_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV5_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV5_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV5_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV5_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV5_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV5_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV5_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV5_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV5_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV5_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV5_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV5_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV5_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV5_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV5_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV5_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV5_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV5_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV5_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV5_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV5_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV5_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV5_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV5_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV5_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV5_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV5_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV5_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV5_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV5_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV5_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV5_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV5_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV5_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV5_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV5_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV5_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV5_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV5_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV5_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV5_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV5_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV5_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV5_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV5_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV5_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV5_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV5_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV5_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV5_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV5_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV5_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV5_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV5_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV5_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV5_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV5_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV5_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV5_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV5_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV5_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV5_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV5_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV5_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV5_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV5_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV5_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV5_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV5_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV5_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV5_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV5_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV5_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV5_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV5_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV5_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV5_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV5_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV5_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV5_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV5_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV5_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV5_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV5_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV5_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV5_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV5_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV5_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV5_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV5_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV5_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV5_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV5_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV5_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV5_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV5_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV5_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV5_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV5_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV5_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV5_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV5_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV5_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV5_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV5_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV5_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV5_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV5_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV5_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV5_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV5_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV5_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV5_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV5_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV5_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV5_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV5_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV5_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV5_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV5_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV5_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV5_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV5_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV5_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV5_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV5_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV5_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV5_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV5_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV5_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV5_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV5_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV5_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV5_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV5_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV5_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV5_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV5_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV5_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV5_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV5_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV5_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV5_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV5_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV5_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV5_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV5_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV5_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV5_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV5_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV5_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV5_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV5_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV5_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV5_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV5_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV5_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV5_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV5_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV5_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV5_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV5_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV5_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV5_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV5_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV5_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV5_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV5_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV5_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV5_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV5_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV5_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV5_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV5_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV5_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV5_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV5_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV5_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV5_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV5_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV5_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV5_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV5_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV5_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV5_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV5_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV5_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV5_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV5_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV5_RSTR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV5_RSTR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV3CMPD_Pos (30UL) /*!< SLV3CMPD (Bit 30) */
+#define HRPWM_SLV5_RSTR_SLV3CMPD_Msk (0x40000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV3CMPB_Pos (29UL) /*!< SLV3CMPB (Bit 29) */
+#define HRPWM_SLV5_RSTR_SLV3CMPB_Msk (0x20000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV3CMPA_Pos (28UL) /*!< SLV3CMPA (Bit 28) */
+#define HRPWM_SLV5_RSTR_SLV3CMPA_Msk (0x10000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV2CMPD_Pos (27UL) /*!< SLV2CMPD (Bit 27) */
+#define HRPWM_SLV5_RSTR_SLV2CMPD_Msk (0x8000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV2CMPB_Pos (26UL) /*!< SLV2CMPB (Bit 26) */
+#define HRPWM_SLV5_RSTR_SLV2CMPB_Msk (0x4000000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV2CMPA_Pos (25UL) /*!< SLV2CMPA (Bit 25) */
+#define HRPWM_SLV5_RSTR_SLV2CMPA_Msk (0x2000000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV5_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV5_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV5_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV5_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV5_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV5_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV5_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV5_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV5_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV5_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV5_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV5_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV5_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV5_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV5_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV5_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV5_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV5_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV5_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV5_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV5_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV5_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV5_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV5_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV4CMPA_Pos (0UL) /*!< SLV4CMPA (Bit 0) */
+#define HRPWM_SLV5_RSTR_SLV4CMPA_Msk (0x1UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV5_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV5_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV5_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV5_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV5_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV5_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV5_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV5_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV5_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV5_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV5_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV5_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV5_CAPACR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV5_CAPACR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV5_CAPACR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV5_CAPACR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV5_CAPACR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV5_CAPACR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV5_CAPACR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV5_CAPACR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV5_CAPACR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV5_CAPACR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV5_CAPACR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV5_CAPACR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV5_CAPACR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV5_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV5_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV5_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV5_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV5_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV5_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV5_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV5_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV5_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV5_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV5_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV5_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV5_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV5_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV5_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV5_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV5_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV5_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV5_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV5_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV5_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV5_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV5_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV5_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV5_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV5_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV5_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV5_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV5_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV5_CAPBCR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV5_CAPBCR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV5_CAPBCR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV5_CAPBCR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV5_CAPBCR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV5_CAPBCR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV5_CAPBCR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV5_CAPBCR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV5_CAPBCR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV5_CAPBCR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV5_CAPBCR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV5_CAPBCR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV5_CAPBCR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV5_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV5_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV5_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV5_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV5_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV5_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV5_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV5_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV5_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV5_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV5_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV5_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV5_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV5_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV5_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV5_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV5_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV5_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV5_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV5_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV5_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV5_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV5_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV5_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV5_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV5_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV5_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV5_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV5_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV5_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV5_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV5_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV5_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV5_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV5_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV5_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV5_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV5_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV5_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV5_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV5_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV5_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV5_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV5_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV5_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV5_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV5_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV5_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV5_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV5_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV5_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV5_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV5_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV5_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV5_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV5_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV5_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV5_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV5_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV5_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV5_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV5_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV5_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV5_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV5_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV5_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV5_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV5_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV5_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV5_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV5_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV5_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV5_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV5_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV5_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV5_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV5_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV5_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV5_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV6 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV6_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV6_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV6_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV6_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV6_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV6_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV6_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV6_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV6_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV6_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV6_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV6_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV6_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV6_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV6_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV6_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV6_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV6_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV6_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV6_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV6_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV6_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV6_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV6_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV6_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV6_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV6_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV6_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV6_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV6_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV6_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV6_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV6_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV6_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV6_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV6_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV6_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV6_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV6_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV6_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV6_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV6_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV6_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV6_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV6_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV6_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV6_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV6_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV6_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV6_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV6_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV6_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV6_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV6_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV6_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV6_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV6_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV6_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV6_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV6_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV6_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV6_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV6_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV6_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV6_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV6_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV6_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV6_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV6_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV6_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV6_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV6_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV6_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV6_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV6_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV6_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV6_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV6_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV6_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV6_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV6_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV6_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV6_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV6_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV6_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV6_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV6_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV6_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV6_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV6_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV6_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV6_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV6_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV6_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV6_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV6_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV6_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV6_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV6_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV6_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV6_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV6_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV6_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV6_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV6_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV6_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV6_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV6_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV6_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV6_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV6_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV6_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV6_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV6_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV6_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV6_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV6_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV6_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV6_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV6_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV6_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV6_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV6_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV6_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV6_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV6_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV6_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV6_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV6_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV6_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV6_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV6_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV6_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV6_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV6_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV6_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV6_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV6_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV6_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV6_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV6_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV6_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV6_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV6_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV6_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV6_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV6_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV6_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV6_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV6_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV6_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV6_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV6_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV6_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV6_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV6_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV6_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV6_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV6_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV6_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV6_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV6_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV6_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV6_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV6_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV6_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV6_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV6_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV6_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV6_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV6_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV6_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV6_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV6_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV6_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV6_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV6_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV6_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV6_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV6_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV6_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV6_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV6_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV6_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV6_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV6_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV6_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV6_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV6_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV6_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV6_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV6_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV6_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV6_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV6_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV6_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV6_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV6_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV6_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV6_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV6_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV6_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV6_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV6_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV6_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV6_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV6_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV6_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV6_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV6_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV6_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV6_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV6_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV6_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV6_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV6_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV6_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV6_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV6_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV6_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV6_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV6_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV6_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV6_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV6_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV6_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV6_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV6_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV6_RSTR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV6_RSTR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV3CMPD_Pos (30UL) /*!< SLV3CMPD (Bit 30) */
+#define HRPWM_SLV6_RSTR_SLV3CMPD_Msk (0x40000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV3CMPB_Pos (29UL) /*!< SLV3CMPB (Bit 29) */
+#define HRPWM_SLV6_RSTR_SLV3CMPB_Msk (0x20000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV3CMPA_Pos (28UL) /*!< SLV3CMPA (Bit 28) */
+#define HRPWM_SLV6_RSTR_SLV3CMPA_Msk (0x10000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV2CMPD_Pos (27UL) /*!< SLV2CMPD (Bit 27) */
+#define HRPWM_SLV6_RSTR_SLV2CMPD_Msk (0x8000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV2CMPB_Pos (26UL) /*!< SLV2CMPB (Bit 26) */
+#define HRPWM_SLV6_RSTR_SLV2CMPB_Msk (0x4000000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV2CMPA_Pos (25UL) /*!< SLV2CMPA (Bit 25) */
+#define HRPWM_SLV6_RSTR_SLV2CMPA_Msk (0x2000000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV6_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV6_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV6_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV6_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV6_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV6_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV6_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV6_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV6_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV6_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV6_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV6_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV6_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV6_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV6_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV6_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV6_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV6_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV6_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV6_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV6_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV6_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV6_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV6_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV4CMPA_Pos (0UL) /*!< SLV4CMPA (Bit 0) */
+#define HRPWM_SLV6_RSTR_SLV4CMPA_Msk (0x1UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV6_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV6_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV6_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV6_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTER_SLV5CMPD_Pos (2UL) /*!< SLV5CMPD (Bit 2) */
+#define HRPWM_SLV6_RSTER_SLV5CMPD_Msk (0x4UL) /*!< SLV5CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTER_SLV5CMPB_Pos (1UL) /*!< SLV5CMPB (Bit 1) */
+#define HRPWM_SLV6_RSTER_SLV5CMPB_Msk (0x2UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTER_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV6_RSTER_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV6_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV6_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV6_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV6_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV6_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV6_CAPACR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV6_CAPACR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV6_CAPACR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV6_CAPACR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV6_CAPACR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV6_CAPACR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV6_CAPACR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV6_CAPACR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV6_CAPACR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV6_CAPACR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV6_CAPACR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV6_CAPACR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV6_CAPACR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV6_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV6_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV6_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV6_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV6_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV6_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV6_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV6_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV6_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV6_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV6_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV6_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV6_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV6_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV6_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV6_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV6_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV6_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV6_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV6_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV6_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV6_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV6_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV6_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV6_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV5CMPB_Pos (3UL) /*!< SLV5CMPB (Bit 3) */
+#define HRPWM_SLV6_CAPACER_SLV5CMPB_Msk (0x8UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV5CMPA_Pos (2UL) /*!< SLV5CMPA (Bit 2) */
+#define HRPWM_SLV6_CAPACER_SLV5CMPA_Msk (0x4UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV5CLRA_Pos (1UL) /*!< SLV5CLRA (Bit 1) */
+#define HRPWM_SLV6_CAPACER_SLV5CLRA_Msk (0x2UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV5SETA_Pos (0UL) /*!< SLV5SETA (Bit 0) */
+#define HRPWM_SLV6_CAPACER_SLV5SETA_Msk (0x1UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV6_CAPBCR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV6_CAPBCR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV6_CAPBCR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV6_CAPBCR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV6_CAPBCR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV6_CAPBCR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV6_CAPBCR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV6_CAPBCR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV6_CAPBCR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV6_CAPBCR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV6_CAPBCR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV6_CAPBCR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV6_CAPBCR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV6_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV6_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV6_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV6_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV6_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV6_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV6_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV6_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV6_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV6_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV6_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV6_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV6_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV6_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV6_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV5CMPB_Pos (3UL) /*!< SLV5CMPB (Bit 3) */
+#define HRPWM_SLV6_CAPBCER_SLV5CMPB_Msk (0x8UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV5CMPA_Pos (2UL) /*!< SLV5CMPA (Bit 2) */
+#define HRPWM_SLV6_CAPBCER_SLV5CMPA_Msk (0x4UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV5CLRA_Pos (1UL) /*!< SLV5CLRA (Bit 1) */
+#define HRPWM_SLV6_CAPBCER_SLV5CLRA_Msk (0x2UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV5SETA_Pos (0UL) /*!< SLV5SETA (Bit 0) */
+#define HRPWM_SLV6_CAPBCER_SLV5SETA_Msk (0x1UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV6_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV6_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV6_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV6_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV6_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV6_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV6_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV6_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV6_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV6_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV6_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV6_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV6_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV6_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV6_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV6_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV6_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV6_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV6_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV6_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV6_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV6_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV6_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV6_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV6_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV6_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV6_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV6_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV6_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV6_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV6_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV6_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV6_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV6_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV6_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV6_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV6_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV6_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV6_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV6_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV6_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV6_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV6_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV6_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV6_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV6_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV6_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV6_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV6_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV6_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV6_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV6_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV6_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV6_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV6_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV6_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV6_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV6_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV6_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV6_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV7 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV7_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV7_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV7_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV7_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV7_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV7_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV7_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV7_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV7_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV7_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV7_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV7_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV7_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV7_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV7_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV7_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV7_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV7_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV7_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV7_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV7_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV7_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV7_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV7_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV7_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV7_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV7_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV7_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV7_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV7_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV7_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV7_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV7_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV7_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV7_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV7_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV7_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV7_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV7_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV7_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV7_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV7_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV7_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV7_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV7_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV7_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV7_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV7_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV7_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV7_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV7_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV7_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV7_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV7_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV7_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV7_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV7_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV7_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV7_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV7_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV7_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV7_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV7_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV7_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV7_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV7_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV7_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV7_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV7_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV7_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV7_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV7_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV7_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV7_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV7_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV7_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV7_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV7_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV7_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV7_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV7_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV7_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV7_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV7_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV7_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV7_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV7_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV7_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV7_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV7_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV7_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV7_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV7_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV7_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV7_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV7_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV7_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV7_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV7_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV7_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV7_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV7_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV7_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV7_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV7_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV7_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV7_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV7_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV7_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV7_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV7_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV7_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV7_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV7_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV7_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV7_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV7_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV7_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV7_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV7_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV7_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV7_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV7_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV7_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV7_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV7_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV7_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV7_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV7_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV7_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV7_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV7_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV7_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV7_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV7_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV7_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV7_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV7_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV7_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV7_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV7_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV7_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV7_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV7_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV7_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV7_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV7_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV7_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV7_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV7_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV7_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV7_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV7_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV7_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV7_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV7_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV7_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV7_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV7_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV7_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV7_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV7_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV7_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV7_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV7_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV7_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV7_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV7_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV7_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV7_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV7_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV7_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV7_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV7_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV7_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV7_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV7_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV7_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV7_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV7_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV7_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV7_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV7_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV7_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV7_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV7_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV7_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV7_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV7_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV7_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV7_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV7_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV7_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV7_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV7_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV7_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV7_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV7_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV7_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV7_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV7_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV7_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV7_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV7_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV7_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV7_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV7_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV7_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV7_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV7_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV7_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV7_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV7_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV7_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV7_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV7_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV7_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV7_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV7_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV7_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV7_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV7_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV7_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV7_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV7_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV7_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV7_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV7_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV7_RSTR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV7_RSTR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV3CMPD_Pos (30UL) /*!< SLV3CMPD (Bit 30) */
+#define HRPWM_SLV7_RSTR_SLV3CMPD_Msk (0x40000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV3CMPB_Pos (29UL) /*!< SLV3CMPB (Bit 29) */
+#define HRPWM_SLV7_RSTR_SLV3CMPB_Msk (0x20000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV3CMPA_Pos (28UL) /*!< SLV3CMPA (Bit 28) */
+#define HRPWM_SLV7_RSTR_SLV3CMPA_Msk (0x10000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV2CMPD_Pos (27UL) /*!< SLV2CMPD (Bit 27) */
+#define HRPWM_SLV7_RSTR_SLV2CMPD_Msk (0x8000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV2CMPB_Pos (26UL) /*!< SLV2CMPB (Bit 26) */
+#define HRPWM_SLV7_RSTR_SLV2CMPB_Msk (0x4000000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV2CMPA_Pos (25UL) /*!< SLV2CMPA (Bit 25) */
+#define HRPWM_SLV7_RSTR_SLV2CMPA_Msk (0x2000000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV7_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV7_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV7_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV7_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV7_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV7_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV7_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV7_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV7_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV7_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV7_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV7_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV7_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV7_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV7_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV7_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV7_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV7_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV7_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV7_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV7_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV7_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV7_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV7_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV4CMPA_Pos (0UL) /*!< SLV4CMPA (Bit 0) */
+#define HRPWM_SLV7_RSTR_SLV4CMPA_Msk (0x1UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV7_RSTER_SLV6CMPD_Pos (5UL) /*!< SLV6CMPD (Bit 5) */
+#define HRPWM_SLV7_RSTER_SLV6CMPD_Msk (0x20UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTER_SLV6CMPB_Pos (4UL) /*!< SLV6CMPB (Bit 4) */
+#define HRPWM_SLV7_RSTER_SLV6CMPB_Msk (0x10UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTER_SLV6CMPA_Pos (3UL) /*!< SLV6CMPA (Bit 3) */
+#define HRPWM_SLV7_RSTER_SLV6CMPA_Msk (0x8UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTER_SLV5CMPD_Pos (2UL) /*!< SLV5CMPD (Bit 2) */
+#define HRPWM_SLV7_RSTER_SLV5CMPD_Msk (0x4UL) /*!< SLV5CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTER_SLV5CMPB_Pos (1UL) /*!< SLV5CMPB (Bit 1) */
+#define HRPWM_SLV7_RSTER_SLV5CMPB_Msk (0x2UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTER_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV7_RSTER_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV7_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV7_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV7_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV7_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV7_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV7_CAPACR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV7_CAPACR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV7_CAPACR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV7_CAPACR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV7_CAPACR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV7_CAPACR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV7_CAPACR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV7_CAPACR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV7_CAPACR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV7_CAPACR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV7_CAPACR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV7_CAPACR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV7_CAPACR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV7_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV7_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV7_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV7_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV7_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV7_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV7_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV7_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV7_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV7_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV7_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV7_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV7_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV7_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV7_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV7_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV7_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV7_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV7_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV7_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV7_CAPACER_SLV6CMPB_Pos (7UL) /*!< SLV6CMPB (Bit 7) */
+#define HRPWM_SLV7_CAPACER_SLV6CMPB_Msk (0x80UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV6CMPA_Pos (6UL) /*!< SLV6CMPA (Bit 6) */
+#define HRPWM_SLV7_CAPACER_SLV6CMPA_Msk (0x40UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV6CLRA_Pos (5UL) /*!< SLV6CLRA (Bit 5) */
+#define HRPWM_SLV7_CAPACER_SLV6CLRA_Msk (0x20UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV6SETA_Pos (4UL) /*!< SLV6SETA (Bit 4) */
+#define HRPWM_SLV7_CAPACER_SLV6SETA_Msk (0x10UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV5CMPB_Pos (3UL) /*!< SLV5CMPB (Bit 3) */
+#define HRPWM_SLV7_CAPACER_SLV5CMPB_Msk (0x8UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV5CMPA_Pos (2UL) /*!< SLV5CMPA (Bit 2) */
+#define HRPWM_SLV7_CAPACER_SLV5CMPA_Msk (0x4UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV5CLRA_Pos (1UL) /*!< SLV5CLRA (Bit 1) */
+#define HRPWM_SLV7_CAPACER_SLV5CLRA_Msk (0x2UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV5SETA_Pos (0UL) /*!< SLV5SETA (Bit 0) */
+#define HRPWM_SLV7_CAPACER_SLV5SETA_Msk (0x1UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV7_CAPBCR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV7_CAPBCR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV7_CAPBCR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV7_CAPBCR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV7_CAPBCR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV7_CAPBCR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV7_CAPBCR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV7_CAPBCR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV7_CAPBCR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV7_CAPBCR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV7_CAPBCR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV7_CAPBCR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV7_CAPBCR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV7_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV7_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV7_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV7_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV7_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV7_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV7_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV7_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV7_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV7_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV7_CAPBCER_SLV6CMPB_Pos (7UL) /*!< SLV6CMPB (Bit 7) */
+#define HRPWM_SLV7_CAPBCER_SLV6CMPB_Msk (0x80UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV6CMPA_Pos (6UL) /*!< SLV6CMPA (Bit 6) */
+#define HRPWM_SLV7_CAPBCER_SLV6CMPA_Msk (0x40UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV6CLRA_Pos (5UL) /*!< SLV6CLRA (Bit 5) */
+#define HRPWM_SLV7_CAPBCER_SLV6CLRA_Msk (0x20UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV6SETA_Pos (4UL) /*!< SLV6SETA (Bit 4) */
+#define HRPWM_SLV7_CAPBCER_SLV6SETA_Msk (0x10UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV5CMPB_Pos (3UL) /*!< SLV5CMPB (Bit 3) */
+#define HRPWM_SLV7_CAPBCER_SLV5CMPB_Msk (0x8UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV5CMPA_Pos (2UL) /*!< SLV5CMPA (Bit 2) */
+#define HRPWM_SLV7_CAPBCER_SLV5CMPA_Msk (0x4UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV5CLRA_Pos (1UL) /*!< SLV5CLRA (Bit 1) */
+#define HRPWM_SLV7_CAPBCER_SLV5CLRA_Msk (0x2UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV5SETA_Pos (0UL) /*!< SLV5SETA (Bit 0) */
+#define HRPWM_SLV7_CAPBCER_SLV5SETA_Msk (0x1UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV7_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV7_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV7_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV7_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV7_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV7_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV7_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV7_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV7_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV7_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV7_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV7_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV7_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV7_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV7_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV7_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV7_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV7_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV7_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV7_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV7_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV7_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV7_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV7_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV7_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV7_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV7_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV7_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV7_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV7_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV7_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV7_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV7_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV7_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV7_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV7_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV7_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV7_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV7_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV7_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV7_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV7_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV7_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV7_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV7_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV7_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV7_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV7_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV7_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV7_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV7_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV7_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV7_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV7_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV7_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV7_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV7_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV7_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV7_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV7_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_COM ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define HRPWM_COM_CR0_USRC3_Pos (28UL) /*!< USRC3 (Bit 28) */
+#define HRPWM_COM_CR0_USRC3_Msk (0xf0000000UL) /*!< USRC3 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR0_USRC2_Pos (24UL) /*!< USRC2 (Bit 24) */
+#define HRPWM_COM_CR0_USRC2_Msk (0xf000000UL) /*!< USRC2 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR0_USRC1_Pos (20UL) /*!< USRC1 (Bit 20) */
+#define HRPWM_COM_CR0_USRC1_Msk (0xf00000UL) /*!< USRC1 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR0_USRC0_Pos (16UL) /*!< USRC0 (Bit 16) */
+#define HRPWM_COM_CR0_USRC0_Msk (0xf0000UL) /*!< USRC0 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR0_BMUDIS_Pos (15UL) /*!< BMUDIS (Bit 15) */
+#define HRPWM_COM_CR0_BMUDIS_Msk (0x8000UL) /*!< BMUDIS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS7_Pos (8UL) /*!< UDIS7 (Bit 8) */
+#define HRPWM_COM_CR0_UDIS7_Msk (0x100UL) /*!< UDIS7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS6_Pos (7UL) /*!< UDIS6 (Bit 7) */
+#define HRPWM_COM_CR0_UDIS6_Msk (0x80UL) /*!< UDIS6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS5_Pos (6UL) /*!< UDIS5 (Bit 6) */
+#define HRPWM_COM_CR0_UDIS5_Msk (0x40UL) /*!< UDIS5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS4_Pos (5UL) /*!< UDIS4 (Bit 5) */
+#define HRPWM_COM_CR0_UDIS4_Msk (0x20UL) /*!< UDIS4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS3_Pos (4UL) /*!< UDIS3 (Bit 4) */
+#define HRPWM_COM_CR0_UDIS3_Msk (0x10UL) /*!< UDIS3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS2_Pos (3UL) /*!< UDIS2 (Bit 3) */
+#define HRPWM_COM_CR0_UDIS2_Msk (0x8UL) /*!< UDIS2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS1_Pos (2UL) /*!< UDIS1 (Bit 2) */
+#define HRPWM_COM_CR0_UDIS1_Msk (0x4UL) /*!< UDIS1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS0_Pos (1UL) /*!< UDIS0 (Bit 1) */
+#define HRPWM_COM_CR0_UDIS0_Msk (0x2UL) /*!< UDIS0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_MUDIS_Pos (0UL) /*!< MUDIS (Bit 0) */
+#define HRPWM_COM_CR0_MUDIS_Msk (0x1UL) /*!< MUDIS (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define HRPWM_COM_CR1_TLEN3_Pos (28UL) /*!< TLEN3 (Bit 28) */
+#define HRPWM_COM_CR1_TLEN3_Msk (0xf0000000UL) /*!< TLEN3 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR1_TLEN2_Pos (24UL) /*!< TLEN2 (Bit 24) */
+#define HRPWM_COM_CR1_TLEN2_Msk (0xf000000UL) /*!< TLEN2 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR1_TLEN1_Pos (20UL) /*!< TLEN1 (Bit 20) */
+#define HRPWM_COM_CR1_TLEN1_Msk (0xf00000UL) /*!< TLEN1 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR1_TLEN0_Pos (16UL) /*!< TLEN0 (Bit 16) */
+#define HRPWM_COM_CR1_TLEN0_Msk (0xf0000UL) /*!< TLEN0 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR1_SWP7_Pos (7UL) /*!< SWP7 (Bit 7) */
+#define HRPWM_COM_CR1_SWP7_Msk (0x80UL) /*!< SWP7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP6_Pos (6UL) /*!< SWP6 (Bit 6) */
+#define HRPWM_COM_CR1_SWP6_Msk (0x40UL) /*!< SWP6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP5_Pos (5UL) /*!< SWP5 (Bit 5) */
+#define HRPWM_COM_CR1_SWP5_Msk (0x20UL) /*!< SWP5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP4_Pos (4UL) /*!< SWP4 (Bit 4) */
+#define HRPWM_COM_CR1_SWP4_Msk (0x10UL) /*!< SWP4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP3_Pos (3UL) /*!< SWP3 (Bit 3) */
+#define HRPWM_COM_CR1_SWP3_Msk (0x8UL) /*!< SWP3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP2_Pos (2UL) /*!< SWP2 (Bit 2) */
+#define HRPWM_COM_CR1_SWP2_Msk (0x4UL) /*!< SWP2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP1_Pos (1UL) /*!< SWP1 (Bit 1) */
+#define HRPWM_COM_CR1_SWP1_Msk (0x2UL) /*!< SWP1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP0_Pos (0UL) /*!< SWP0 (Bit 0) */
+#define HRPWM_COM_CR1_SWP0_Msk (0x1UL) /*!< SWP0 (Bitfield-Mask: 0x01) */
+/* ========================================================== CR2 ========================================================== */
+#define HRPWM_COM_CR2_RST7_Pos (24UL) /*!< RST7 (Bit 24) */
+#define HRPWM_COM_CR2_RST7_Msk (0x1000000UL) /*!< RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST6_Pos (23UL) /*!< RST6 (Bit 23) */
+#define HRPWM_COM_CR2_RST6_Msk (0x800000UL) /*!< RST6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST5_Pos (22UL) /*!< RST5 (Bit 22) */
+#define HRPWM_COM_CR2_RST5_Msk (0x400000UL) /*!< RST5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST4_Pos (21UL) /*!< RST4 (Bit 21) */
+#define HRPWM_COM_CR2_RST4_Msk (0x200000UL) /*!< RST4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST3_Pos (20UL) /*!< RST3 (Bit 20) */
+#define HRPWM_COM_CR2_RST3_Msk (0x100000UL) /*!< RST3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST2_Pos (19UL) /*!< RST2 (Bit 19) */
+#define HRPWM_COM_CR2_RST2_Msk (0x80000UL) /*!< RST2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST1_Pos (18UL) /*!< RST1 (Bit 18) */
+#define HRPWM_COM_CR2_RST1_Msk (0x40000UL) /*!< RST1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST0_Pos (17UL) /*!< RST0 (Bit 17) */
+#define HRPWM_COM_CR2_RST0_Msk (0x20000UL) /*!< RST0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_MRST_Pos (16UL) /*!< MRST (Bit 16) */
+#define HRPWM_COM_CR2_MRST_Msk (0x10000UL) /*!< MRST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU7_Pos (8UL) /*!< SWU7 (Bit 8) */
+#define HRPWM_COM_CR2_SWU7_Msk (0x100UL) /*!< SWU7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU6_Pos (7UL) /*!< SWU6 (Bit 7) */
+#define HRPWM_COM_CR2_SWU6_Msk (0x80UL) /*!< SWU6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU5_Pos (6UL) /*!< SWU5 (Bit 6) */
+#define HRPWM_COM_CR2_SWU5_Msk (0x40UL) /*!< SWU5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU4_Pos (5UL) /*!< SWU4 (Bit 5) */
+#define HRPWM_COM_CR2_SWU4_Msk (0x20UL) /*!< SWU4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU3_Pos (4UL) /*!< SWU3 (Bit 4) */
+#define HRPWM_COM_CR2_SWU3_Msk (0x10UL) /*!< SWU3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU2_Pos (3UL) /*!< SWU2 (Bit 3) */
+#define HRPWM_COM_CR2_SWU2_Msk (0x8UL) /*!< SWU2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU1_Pos (2UL) /*!< SWU1 (Bit 2) */
+#define HRPWM_COM_CR2_SWU1_Msk (0x4UL) /*!< SWU1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU0_Pos (1UL) /*!< SWU0 (Bit 1) */
+#define HRPWM_COM_CR2_SWU0_Msk (0x2UL) /*!< SWU0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_MSWU_Pos (0UL) /*!< MSWU (Bit 0) */
+#define HRPWM_COM_CR2_MSWU_Msk (0x1UL) /*!< MSWU (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define HRPWM_COM_ISR_BMPER_Pos (15UL) /*!< BMPER (Bit 15) */
+#define HRPWM_COM_ISR_BMPER_Msk (0x8000UL) /*!< BMPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT7_Pos (8UL) /*!< FLT7 (Bit 8) */
+#define HRPWM_COM_ISR_FLT7_Msk (0x100UL) /*!< FLT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT6_Pos (7UL) /*!< FLT6 (Bit 7) */
+#define HRPWM_COM_ISR_FLT6_Msk (0x80UL) /*!< FLT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT5_Pos (6UL) /*!< FLT5 (Bit 6) */
+#define HRPWM_COM_ISR_FLT5_Msk (0x40UL) /*!< FLT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT4_Pos (5UL) /*!< FLT4 (Bit 5) */
+#define HRPWM_COM_ISR_FLT4_Msk (0x20UL) /*!< FLT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT3_Pos (4UL) /*!< FLT3 (Bit 4) */
+#define HRPWM_COM_ISR_FLT3_Msk (0x10UL) /*!< FLT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT2_Pos (3UL) /*!< FLT2 (Bit 3) */
+#define HRPWM_COM_ISR_FLT2_Msk (0x8UL) /*!< FLT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT1_Pos (2UL) /*!< FLT1 (Bit 2) */
+#define HRPWM_COM_ISR_FLT1_Msk (0x4UL) /*!< FLT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT0_Pos (1UL) /*!< FLT0 (Bit 1) */
+#define HRPWM_COM_ISR_FLT0_Msk (0x2UL) /*!< FLT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_SYSFLT_Pos (0UL) /*!< SYSFLT (Bit 0) */
+#define HRPWM_COM_ISR_SYSFLT_Msk (0x1UL) /*!< SYSFLT (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define HRPWM_COM_IER_BMPERIE_Pos (15UL) /*!< BMPERIE (Bit 15) */
+#define HRPWM_COM_IER_BMPERIE_Msk (0x8000UL) /*!< BMPERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT7IE_Pos (8UL) /*!< FLT7IE (Bit 8) */
+#define HRPWM_COM_IER_FLT7IE_Msk (0x100UL) /*!< FLT7IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT6IE_Pos (7UL) /*!< FLT6IE (Bit 7) */
+#define HRPWM_COM_IER_FLT6IE_Msk (0x80UL) /*!< FLT6IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT5IE_Pos (6UL) /*!< FLT5IE (Bit 6) */
+#define HRPWM_COM_IER_FLT5IE_Msk (0x40UL) /*!< FLT5IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT4IE_Pos (5UL) /*!< FLT4IE (Bit 5) */
+#define HRPWM_COM_IER_FLT4IE_Msk (0x20UL) /*!< FLT4IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT3IE_Pos (4UL) /*!< FLT3IE (Bit 4) */
+#define HRPWM_COM_IER_FLT3IE_Msk (0x10UL) /*!< FLT3IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT2IE_Pos (3UL) /*!< FLT2IE (Bit 3) */
+#define HRPWM_COM_IER_FLT2IE_Msk (0x8UL) /*!< FLT2IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT1IE_Pos (2UL) /*!< FLT1IE (Bit 2) */
+#define HRPWM_COM_IER_FLT1IE_Msk (0x4UL) /*!< FLT1IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT0IE_Pos (1UL) /*!< FLT0IE (Bit 1) */
+#define HRPWM_COM_IER_FLT0IE_Msk (0x2UL) /*!< FLT0IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_SYSFLTIE_Pos (0UL) /*!< SYSFLTIE (Bit 0) */
+#define HRPWM_COM_IER_SYSFLTIE_Msk (0x1UL) /*!< SYSFLTIE (Bitfield-Mask: 0x01) */
+/* ========================================================= OENR ========================================================== */
+#define HRPWM_COM_OENR_OEN7B_Pos (15UL) /*!< OEN7B (Bit 15) */
+#define HRPWM_COM_OENR_OEN7B_Msk (0x8000UL) /*!< OEN7B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN7A_Pos (14UL) /*!< OEN7A (Bit 14) */
+#define HRPWM_COM_OENR_OEN7A_Msk (0x4000UL) /*!< OEN7A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN6B_Pos (13UL) /*!< OEN6B (Bit 13) */
+#define HRPWM_COM_OENR_OEN6B_Msk (0x2000UL) /*!< OEN6B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN6A_Pos (12UL) /*!< OEN6A (Bit 12) */
+#define HRPWM_COM_OENR_OEN6A_Msk (0x1000UL) /*!< OEN6A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN5B_Pos (11UL) /*!< OEN5B (Bit 11) */
+#define HRPWM_COM_OENR_OEN5B_Msk (0x800UL) /*!< OEN5B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN5A_Pos (10UL) /*!< OEN5A (Bit 10) */
+#define HRPWM_COM_OENR_OEN5A_Msk (0x400UL) /*!< OEN5A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN4B_Pos (9UL) /*!< OEN4B (Bit 9) */
+#define HRPWM_COM_OENR_OEN4B_Msk (0x200UL) /*!< OEN4B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN4A_Pos (8UL) /*!< OEN4A (Bit 8) */
+#define HRPWM_COM_OENR_OEN4A_Msk (0x100UL) /*!< OEN4A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN3B_Pos (7UL) /*!< OEN3B (Bit 7) */
+#define HRPWM_COM_OENR_OEN3B_Msk (0x80UL) /*!< OEN3B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN3A_Pos (6UL) /*!< OEN3A (Bit 6) */
+#define HRPWM_COM_OENR_OEN3A_Msk (0x40UL) /*!< OEN3A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN2B_Pos (5UL) /*!< OEN2B (Bit 5) */
+#define HRPWM_COM_OENR_OEN2B_Msk (0x20UL) /*!< OEN2B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN2A_Pos (4UL) /*!< OEN2A (Bit 4) */
+#define HRPWM_COM_OENR_OEN2A_Msk (0x10UL) /*!< OEN2A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN1B_Pos (3UL) /*!< OEN1B (Bit 3) */
+#define HRPWM_COM_OENR_OEN1B_Msk (0x8UL) /*!< OEN1B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN1A_Pos (2UL) /*!< OEN1A (Bit 2) */
+#define HRPWM_COM_OENR_OEN1A_Msk (0x4UL) /*!< OEN1A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN0B_Pos (1UL) /*!< OEN0B (Bit 1) */
+#define HRPWM_COM_OENR_OEN0B_Msk (0x2UL) /*!< OEN0B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN0A_Pos (0UL) /*!< OEN0A (Bit 0) */
+#define HRPWM_COM_OENR_OEN0A_Msk (0x1UL) /*!< OEN0A (Bitfield-Mask: 0x01) */
+/* ========================================================= ODISR ========================================================= */
+#define HRPWM_COM_ODISR_ODIS7B_Pos (15UL) /*!< ODIS7B (Bit 15) */
+#define HRPWM_COM_ODISR_ODIS7B_Msk (0x8000UL) /*!< ODIS7B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS7A_Pos (14UL) /*!< ODIS7A (Bit 14) */
+#define HRPWM_COM_ODISR_ODIS7A_Msk (0x4000UL) /*!< ODIS7A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS6B_Pos (13UL) /*!< ODIS6B (Bit 13) */
+#define HRPWM_COM_ODISR_ODIS6B_Msk (0x2000UL) /*!< ODIS6B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS6A_Pos (12UL) /*!< ODIS6A (Bit 12) */
+#define HRPWM_COM_ODISR_ODIS6A_Msk (0x1000UL) /*!< ODIS6A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS5B_Pos (11UL) /*!< ODIS5B (Bit 11) */
+#define HRPWM_COM_ODISR_ODIS5B_Msk (0x800UL) /*!< ODIS5B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS5A_Pos (10UL) /*!< ODIS5A (Bit 10) */
+#define HRPWM_COM_ODISR_ODIS5A_Msk (0x400UL) /*!< ODIS5A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS4B_Pos (9UL) /*!< ODIS4B (Bit 9) */
+#define HRPWM_COM_ODISR_ODIS4B_Msk (0x200UL) /*!< ODIS4B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS4A_Pos (8UL) /*!< ODIS4A (Bit 8) */
+#define HRPWM_COM_ODISR_ODIS4A_Msk (0x100UL) /*!< ODIS4A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS3B_Pos (7UL) /*!< ODIS3B (Bit 7) */
+#define HRPWM_COM_ODISR_ODIS3B_Msk (0x80UL) /*!< ODIS3B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS3A_Pos (6UL) /*!< ODIS3A (Bit 6) */
+#define HRPWM_COM_ODISR_ODIS3A_Msk (0x40UL) /*!< ODIS3A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS2B_Pos (5UL) /*!< ODIS2B (Bit 5) */
+#define HRPWM_COM_ODISR_ODIS2B_Msk (0x20UL) /*!< ODIS2B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS2A_Pos (4UL) /*!< ODIS2A (Bit 4) */
+#define HRPWM_COM_ODISR_ODIS2A_Msk (0x10UL) /*!< ODIS2A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS1B_Pos (3UL) /*!< ODIS1B (Bit 3) */
+#define HRPWM_COM_ODISR_ODIS1B_Msk (0x8UL) /*!< ODIS1B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS1A_Pos (2UL) /*!< ODIS1A (Bit 2) */
+#define HRPWM_COM_ODISR_ODIS1A_Msk (0x4UL) /*!< ODIS1A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS0B_Pos (1UL) /*!< ODIS0B (Bit 1) */
+#define HRPWM_COM_ODISR_ODIS0B_Msk (0x2UL) /*!< ODIS0B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS0A_Pos (0UL) /*!< ODIS0A (Bit 0) */
+#define HRPWM_COM_ODISR_ODIS0A_Msk (0x1UL) /*!< ODIS0A (Bitfield-Mask: 0x01) */
+/* ========================================================= EECR0 ========================================================= */
+#define HRPWM_COM_EECR0_EE4FAST_Pos (29UL) /*!< EE4FAST (Bit 29) */
+#define HRPWM_COM_EECR0_EE4FAST_Msk (0x20000000UL) /*!< EE4FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE4SNS_Pos (27UL) /*!< EE4SNS (Bit 27) */
+#define HRPWM_COM_EECR0_EE4SNS_Msk (0x18000000UL) /*!< EE4SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE4POL_Pos (26UL) /*!< EE4POL (Bit 26) */
+#define HRPWM_COM_EECR0_EE4POL_Msk (0x4000000UL) /*!< EE4POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE4SRC_Pos (24UL) /*!< EE4SRC (Bit 24) */
+#define HRPWM_COM_EECR0_EE4SRC_Msk (0x3000000UL) /*!< EE4SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE3FAST_Pos (23UL) /*!< EE3FAST (Bit 23) */
+#define HRPWM_COM_EECR0_EE3FAST_Msk (0x800000UL) /*!< EE3FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE3SNS_Pos (21UL) /*!< EE3SNS (Bit 21) */
+#define HRPWM_COM_EECR0_EE3SNS_Msk (0x600000UL) /*!< EE3SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE3POL_Pos (20UL) /*!< EE3POL (Bit 20) */
+#define HRPWM_COM_EECR0_EE3POL_Msk (0x100000UL) /*!< EE3POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE3SRC_Pos (18UL) /*!< EE3SRC (Bit 18) */
+#define HRPWM_COM_EECR0_EE3SRC_Msk (0xc0000UL) /*!< EE3SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE2FAST_Pos (17UL) /*!< EE2FAST (Bit 17) */
+#define HRPWM_COM_EECR0_EE2FAST_Msk (0x20000UL) /*!< EE2FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE2SNS_Pos (15UL) /*!< EE2SNS (Bit 15) */
+#define HRPWM_COM_EECR0_EE2SNS_Msk (0x18000UL) /*!< EE2SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE2POL_Pos (14UL) /*!< EE2POL (Bit 14) */
+#define HRPWM_COM_EECR0_EE2POL_Msk (0x4000UL) /*!< EE2POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE2SRC_Pos (12UL) /*!< EE2SRC (Bit 12) */
+#define HRPWM_COM_EECR0_EE2SRC_Msk (0x3000UL) /*!< EE2SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE1FAST_Pos (11UL) /*!< EE1FAST (Bit 11) */
+#define HRPWM_COM_EECR0_EE1FAST_Msk (0x800UL) /*!< EE1FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE1SNS_Pos (9UL) /*!< EE1SNS (Bit 9) */
+#define HRPWM_COM_EECR0_EE1SNS_Msk (0x600UL) /*!< EE1SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE1POL_Pos (8UL) /*!< EE1POL (Bit 8) */
+#define HRPWM_COM_EECR0_EE1POL_Msk (0x100UL) /*!< EE1POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE1SRC_Pos (6UL) /*!< EE1SRC (Bit 6) */
+#define HRPWM_COM_EECR0_EE1SRC_Msk (0xc0UL) /*!< EE1SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE0FAST_Pos (5UL) /*!< EE0FAST (Bit 5) */
+#define HRPWM_COM_EECR0_EE0FAST_Msk (0x20UL) /*!< EE0FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE0SNS_Pos (3UL) /*!< EE0SNS (Bit 3) */
+#define HRPWM_COM_EECR0_EE0SNS_Msk (0x18UL) /*!< EE0SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE0POL_Pos (2UL) /*!< EE0POL (Bit 2) */
+#define HRPWM_COM_EECR0_EE0POL_Msk (0x4UL) /*!< EE0POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE0SRC_Pos (0UL) /*!< EE0SRC (Bit 0) */
+#define HRPWM_COM_EECR0_EE0SRC_Msk (0x3UL) /*!< EE0SRC (Bitfield-Mask: 0x03) */
+/* ========================================================= EECR1 ========================================================= */
+#define HRPWM_COM_EECR1_EE9FAST_Pos (29UL) /*!< EE9FAST (Bit 29) */
+#define HRPWM_COM_EECR1_EE9FAST_Msk (0x20000000UL) /*!< EE9FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE9SNS_Pos (27UL) /*!< EE9SNS (Bit 27) */
+#define HRPWM_COM_EECR1_EE9SNS_Msk (0x18000000UL) /*!< EE9SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE9POL_Pos (26UL) /*!< EE9POL (Bit 26) */
+#define HRPWM_COM_EECR1_EE9POL_Msk (0x4000000UL) /*!< EE9POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE9SRC_Pos (24UL) /*!< EE9SRC (Bit 24) */
+#define HRPWM_COM_EECR1_EE9SRC_Msk (0x3000000UL) /*!< EE9SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE8FAST_Pos (23UL) /*!< EE8FAST (Bit 23) */
+#define HRPWM_COM_EECR1_EE8FAST_Msk (0x800000UL) /*!< EE8FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE8SNS_Pos (21UL) /*!< EE8SNS (Bit 21) */
+#define HRPWM_COM_EECR1_EE8SNS_Msk (0x600000UL) /*!< EE8SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE8POL_Pos (20UL) /*!< EE8POL (Bit 20) */
+#define HRPWM_COM_EECR1_EE8POL_Msk (0x100000UL) /*!< EE8POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE8SRC_Pos (18UL) /*!< EE8SRC (Bit 18) */
+#define HRPWM_COM_EECR1_EE8SRC_Msk (0xc0000UL) /*!< EE8SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE7FAST_Pos (17UL) /*!< EE7FAST (Bit 17) */
+#define HRPWM_COM_EECR1_EE7FAST_Msk (0x20000UL) /*!< EE7FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE7SNS_Pos (15UL) /*!< EE7SNS (Bit 15) */
+#define HRPWM_COM_EECR1_EE7SNS_Msk (0x18000UL) /*!< EE7SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE7POL_Pos (14UL) /*!< EE7POL (Bit 14) */
+#define HRPWM_COM_EECR1_EE7POL_Msk (0x4000UL) /*!< EE7POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE7SRC_Pos (12UL) /*!< EE7SRC (Bit 12) */
+#define HRPWM_COM_EECR1_EE7SRC_Msk (0x3000UL) /*!< EE7SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE6FAST_Pos (11UL) /*!< EE6FAST (Bit 11) */
+#define HRPWM_COM_EECR1_EE6FAST_Msk (0x800UL) /*!< EE6FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE6SNS_Pos (9UL) /*!< EE6SNS (Bit 9) */
+#define HRPWM_COM_EECR1_EE6SNS_Msk (0x600UL) /*!< EE6SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE6POL_Pos (8UL) /*!< EE6POL (Bit 8) */
+#define HRPWM_COM_EECR1_EE6POL_Msk (0x100UL) /*!< EE6POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE6SRC_Pos (6UL) /*!< EE6SRC (Bit 6) */
+#define HRPWM_COM_EECR1_EE6SRC_Msk (0xc0UL) /*!< EE6SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE5FAST_Pos (5UL) /*!< EE5FAST (Bit 5) */
+#define HRPWM_COM_EECR1_EE5FAST_Msk (0x20UL) /*!< EE5FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE5SNS_Pos (3UL) /*!< EE5SNS (Bit 3) */
+#define HRPWM_COM_EECR1_EE5SNS_Msk (0x18UL) /*!< EE5SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE5POL_Pos (2UL) /*!< EE5POL (Bit 2) */
+#define HRPWM_COM_EECR1_EE5POL_Msk (0x4UL) /*!< EE5POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE5SRC_Pos (0UL) /*!< EE5SRC (Bit 0) */
+#define HRPWM_COM_EECR1_EE5SRC_Msk (0x3UL) /*!< EE5SRC (Bitfield-Mask: 0x03) */
+/* ========================================================= EECR2 ========================================================= */
+#define HRPWM_COM_EECR2_EEVSD_Pos (30UL) /*!< EEVSD (Bit 30) */
+#define HRPWM_COM_EECR2_EEVSD_Msk (0xc0000000UL) /*!< EEVSD (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR2_EE4F_Pos (16UL) /*!< EE4F (Bit 16) */
+#define HRPWM_COM_EECR2_EE4F_Msk (0xf0000UL) /*!< EE4F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR2_EE3F_Pos (12UL) /*!< EE3F (Bit 12) */
+#define HRPWM_COM_EECR2_EE3F_Msk (0xf000UL) /*!< EE3F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR2_EE2F_Pos (8UL) /*!< EE2F (Bit 8) */
+#define HRPWM_COM_EECR2_EE2F_Msk (0xf00UL) /*!< EE2F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR2_EE1F_Pos (4UL) /*!< EE1F (Bit 4) */
+#define HRPWM_COM_EECR2_EE1F_Msk (0xf0UL) /*!< EE1F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR2_EE0F_Pos (0UL) /*!< EE0F (Bit 0) */
+#define HRPWM_COM_EECR2_EE0F_Msk (0xfUL) /*!< EE0F (Bitfield-Mask: 0x0f) */
+/* ========================================================= EECR3 ========================================================= */
+#define HRPWM_COM_EECR3_EE9F_Pos (16UL) /*!< EE9F (Bit 16) */
+#define HRPWM_COM_EECR3_EE9F_Msk (0xf0000UL) /*!< EE9F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR3_EE8F_Pos (12UL) /*!< EE8F (Bit 12) */
+#define HRPWM_COM_EECR3_EE8F_Msk (0xf000UL) /*!< EE8F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR3_EE7F_Pos (8UL) /*!< EE7F (Bit 8) */
+#define HRPWM_COM_EECR3_EE7F_Msk (0xf00UL) /*!< EE7F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR3_EE6F_Pos (4UL) /*!< EE6F (Bit 4) */
+#define HRPWM_COM_EECR3_EE6F_Msk (0xf0UL) /*!< EE6F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR3_EE5F_Pos (0UL) /*!< EE5F (Bit 0) */
+#define HRPWM_COM_EECR3_EE5F_Msk (0xfUL) /*!< EE5F (Bitfield-Mask: 0x0f) */
+/* ========================================================= ADC0R ========================================================= */
+#define HRPWM_COM_ADC0R_ADC0RST5_Pos (31UL) /*!< ADC0RST5 (Bit 31) */
+#define HRPWM_COM_ADC0R_ADC0RST5_Msk (0x80000000UL) /*!< ADC0RST5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER5_Pos (30UL) /*!< ADC0PER5 (Bit 30) */
+#define HRPWM_COM_ADC0R_ADC0PER5_Msk (0x40000000UL) /*!< ADC0PER5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD5_Pos (29UL) /*!< ADC0CMPD5 (Bit 29) */
+#define HRPWM_COM_ADC0R_ADC0CMPD5_Msk (0x20000000UL) /*!< ADC0CMPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC5_Pos (28UL) /*!< ADC0CMPC5 (Bit 28) */
+#define HRPWM_COM_ADC0R_ADC0CMPC5_Msk (0x10000000UL) /*!< ADC0CMPC5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPB5_Pos (27UL) /*!< ADC0CMPB5 (Bit 27) */
+#define HRPWM_COM_ADC0R_ADC0CMPB5_Msk (0x8000000UL) /*!< ADC0CMPB5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER4_Pos (26UL) /*!< ADC0PER4 (Bit 26) */
+#define HRPWM_COM_ADC0R_ADC0PER4_Msk (0x4000000UL) /*!< ADC0PER4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD4_Pos (25UL) /*!< ADC0CMPD4 (Bit 25) */
+#define HRPWM_COM_ADC0R_ADC0CMPD4_Msk (0x2000000UL) /*!< ADC0CMPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC4_Pos (24UL) /*!< ADC0CMPC4 (Bit 24) */
+#define HRPWM_COM_ADC0R_ADC0CMPC4_Msk (0x1000000UL) /*!< ADC0CMPC4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER3_Pos (23UL) /*!< ADC0PER3 (Bit 23) */
+#define HRPWM_COM_ADC0R_ADC0PER3_Msk (0x800000UL) /*!< ADC0PER3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD3_Pos (22UL) /*!< ADC0CMPD3 (Bit 22) */
+#define HRPWM_COM_ADC0R_ADC0CMPD3_Msk (0x400000UL) /*!< ADC0CMPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC3_Pos (21UL) /*!< ADC0CMPC3 (Bit 21) */
+#define HRPWM_COM_ADC0R_ADC0CMPC3_Msk (0x200000UL) /*!< ADC0CMPC3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER2_Pos (20UL) /*!< ADC0PER2 (Bit 20) */
+#define HRPWM_COM_ADC0R_ADC0PER2_Msk (0x100000UL) /*!< ADC0PER2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD2_Pos (19UL) /*!< ADC0CMPD2 (Bit 19) */
+#define HRPWM_COM_ADC0R_ADC0CMPD2_Msk (0x80000UL) /*!< ADC0CMPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC2_Pos (18UL) /*!< ADC0CMPC2 (Bit 18) */
+#define HRPWM_COM_ADC0R_ADC0CMPC2_Msk (0x40000UL) /*!< ADC0CMPC2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0RST1_Pos (17UL) /*!< ADC0RST1 (Bit 17) */
+#define HRPWM_COM_ADC0R_ADC0RST1_Msk (0x20000UL) /*!< ADC0RST1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER1_Pos (16UL) /*!< ADC0PER1 (Bit 16) */
+#define HRPWM_COM_ADC0R_ADC0PER1_Msk (0x10000UL) /*!< ADC0PER1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD1_Pos (15UL) /*!< ADC0CMPD1 (Bit 15) */
+#define HRPWM_COM_ADC0R_ADC0CMPD1_Msk (0x8000UL) /*!< ADC0CMPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC1_Pos (14UL) /*!< ADC0CMPC1 (Bit 14) */
+#define HRPWM_COM_ADC0R_ADC0CMPC1_Msk (0x4000UL) /*!< ADC0CMPC1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0RST0_Pos (13UL) /*!< ADC0RST0 (Bit 13) */
+#define HRPWM_COM_ADC0R_ADC0RST0_Msk (0x2000UL) /*!< ADC0RST0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER0_Pos (12UL) /*!< ADC0PER0 (Bit 12) */
+#define HRPWM_COM_ADC0R_ADC0PER0_Msk (0x1000UL) /*!< ADC0PER0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD0_Pos (11UL) /*!< ADC0CMPD0 (Bit 11) */
+#define HRPWM_COM_ADC0R_ADC0CMPD0_Msk (0x800UL) /*!< ADC0CMPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC0_Pos (10UL) /*!< ADC0CMPC0 (Bit 10) */
+#define HRPWM_COM_ADC0R_ADC0CMPC0_Msk (0x400UL) /*!< ADC0CMPC0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0EEV4_Pos (9UL) /*!< ADC0EEV4 (Bit 9) */
+#define HRPWM_COM_ADC0R_ADC0EEV4_Msk (0x200UL) /*!< ADC0EEV4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0EEV3_Pos (8UL) /*!< ADC0EEV3 (Bit 8) */
+#define HRPWM_COM_ADC0R_ADC0EEV3_Msk (0x100UL) /*!< ADC0EEV3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0EEV2_Pos (7UL) /*!< ADC0EEV2 (Bit 7) */
+#define HRPWM_COM_ADC0R_ADC0EEV2_Msk (0x80UL) /*!< ADC0EEV2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0EEV1_Pos (6UL) /*!< ADC0EEV1 (Bit 6) */
+#define HRPWM_COM_ADC0R_ADC0EEV1_Msk (0x40UL) /*!< ADC0EEV1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0EEV0_Pos (5UL) /*!< ADC0EEV0 (Bit 5) */
+#define HRPWM_COM_ADC0R_ADC0EEV0_Msk (0x20UL) /*!< ADC0EEV0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0MPER_Pos (4UL) /*!< ADC0MPER (Bit 4) */
+#define HRPWM_COM_ADC0R_ADC0MPER_Msk (0x10UL) /*!< ADC0MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0MCMPD_Pos (3UL) /*!< ADC0MCMPD (Bit 3) */
+#define HRPWM_COM_ADC0R_ADC0MCMPD_Msk (0x8UL) /*!< ADC0MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0MCMPC_Pos (2UL) /*!< ADC0MCMPC (Bit 2) */
+#define HRPWM_COM_ADC0R_ADC0MCMPC_Msk (0x4UL) /*!< ADC0MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0MCMPB_Pos (1UL) /*!< ADC0MCMPB (Bit 1) */
+#define HRPWM_COM_ADC0R_ADC0MCMPB_Msk (0x2UL) /*!< ADC0MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0MCMPA_Pos (0UL) /*!< ADC0MCMPA (Bit 0) */
+#define HRPWM_COM_ADC0R_ADC0MCMPA_Msk (0x1UL) /*!< ADC0MCMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== ADC0ER ========================================================= */
+#define HRPWM_COM_ADC0ER_ADC0RST7_Pos (7UL) /*!< ADC0RST7 (Bit 7) */
+#define HRPWM_COM_ADC0ER_ADC0RST7_Msk (0x80UL) /*!< ADC0RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0PER7_Pos (6UL) /*!< ADC0PER7 (Bit 6) */
+#define HRPWM_COM_ADC0ER_ADC0PER7_Msk (0x40UL) /*!< ADC0PER7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0CMPD7_Pos (5UL) /*!< ADC0CMPD7 (Bit 5) */
+#define HRPWM_COM_ADC0ER_ADC0CMPD7_Msk (0x20UL) /*!< ADC0CMPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0CMPC7_Pos (4UL) /*!< ADC0CMPC7 (Bit 4) */
+#define HRPWM_COM_ADC0ER_ADC0CMPC7_Msk (0x10UL) /*!< ADC0CMPC7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0RST6_Pos (3UL) /*!< ADC0RST6 (Bit 3) */
+#define HRPWM_COM_ADC0ER_ADC0RST6_Msk (0x8UL) /*!< ADC0RST6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0PER6_Pos (2UL) /*!< ADC0PER6 (Bit 2) */
+#define HRPWM_COM_ADC0ER_ADC0PER6_Msk (0x4UL) /*!< ADC0PER6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0CMPD6_Pos (1UL) /*!< ADC0CMPD6 (Bit 1) */
+#define HRPWM_COM_ADC0ER_ADC0CMPD6_Msk (0x2UL) /*!< ADC0CMPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0CMPC6_Pos (0UL) /*!< ADC0CMPC6 (Bit 0) */
+#define HRPWM_COM_ADC0ER_ADC0CMPC6_Msk (0x1UL) /*!< ADC0CMPC6 (Bitfield-Mask: 0x01) */
+/* ========================================================= ADC1R ========================================================= */
+#define HRPWM_COM_ADC1R_ADC1PER5_Pos (31UL) /*!< ADC1PER5 (Bit 31) */
+#define HRPWM_COM_ADC1R_ADC1PER5_Msk (0x80000000UL) /*!< ADC1PER5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD5_Pos (30UL) /*!< ADC1CMPD5 (Bit 30) */
+#define HRPWM_COM_ADC1R_ADC1CMPD5_Msk (0x40000000UL) /*!< ADC1CMPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPC5_Pos (29UL) /*!< ADC1CMPC5 (Bit 29) */
+#define HRPWM_COM_ADC1R_ADC1CMPC5_Msk (0x20000000UL) /*!< ADC1CMPC5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB5_Pos (28UL) /*!< ADC1CMPB5 (Bit 28) */
+#define HRPWM_COM_ADC1R_ADC1CMPB5_Msk (0x10000000UL) /*!< ADC1CMPB5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1RST4_Pos (27UL) /*!< ADC1RST4 (Bit 27) */
+#define HRPWM_COM_ADC1R_ADC1RST4_Msk (0x8000000UL) /*!< ADC1RST4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD4_Pos (26UL) /*!< ADC1CMPD4 (Bit 26) */
+#define HRPWM_COM_ADC1R_ADC1CMPD4_Msk (0x4000000UL) /*!< ADC1CMPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPC4_Pos (25UL) /*!< ADC1CMPC4 (Bit 25) */
+#define HRPWM_COM_ADC1R_ADC1CMPC4_Msk (0x2000000UL) /*!< ADC1CMPC4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB4_Pos (24UL) /*!< ADC1CMPB4 (Bit 24) */
+#define HRPWM_COM_ADC1R_ADC1CMPB4_Msk (0x1000000UL) /*!< ADC1CMPB4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1RST3_Pos (23UL) /*!< ADC1RST3 (Bit 23) */
+#define HRPWM_COM_ADC1R_ADC1RST3_Msk (0x800000UL) /*!< ADC1RST3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1PER3_Pos (22UL) /*!< ADC1PER3 (Bit 22) */
+#define HRPWM_COM_ADC1R_ADC1PER3_Msk (0x400000UL) /*!< ADC1PER3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD3_Pos (21UL) /*!< ADC1CMPD3 (Bit 21) */
+#define HRPWM_COM_ADC1R_ADC1CMPD3_Msk (0x200000UL) /*!< ADC1CMPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB3_Pos (20UL) /*!< ADC1CMPB3 (Bit 20) */
+#define HRPWM_COM_ADC1R_ADC1CMPB3_Msk (0x100000UL) /*!< ADC1CMPB3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1RST2_Pos (19UL) /*!< ADC1RST2 (Bit 19) */
+#define HRPWM_COM_ADC1R_ADC1RST2_Msk (0x80000UL) /*!< ADC1RST2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1PER2_Pos (18UL) /*!< ADC1PER2 (Bit 18) */
+#define HRPWM_COM_ADC1R_ADC1PER2_Msk (0x40000UL) /*!< ADC1PER2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD2_Pos (17UL) /*!< ADC1CMPD2 (Bit 17) */
+#define HRPWM_COM_ADC1R_ADC1CMPD2_Msk (0x20000UL) /*!< ADC1CMPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB2_Pos (16UL) /*!< ADC1CMPB2 (Bit 16) */
+#define HRPWM_COM_ADC1R_ADC1CMPB2_Msk (0x10000UL) /*!< ADC1CMPB2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1PER1_Pos (15UL) /*!< ADC1PER1 (Bit 15) */
+#define HRPWM_COM_ADC1R_ADC1PER1_Msk (0x8000UL) /*!< ADC1PER1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD1_Pos (14UL) /*!< ADC1CMPD1 (Bit 14) */
+#define HRPWM_COM_ADC1R_ADC1CMPD1_Msk (0x4000UL) /*!< ADC1CMPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB1_Pos (13UL) /*!< ADC1CMPB1 (Bit 13) */
+#define HRPWM_COM_ADC1R_ADC1CMPB1_Msk (0x2000UL) /*!< ADC1CMPB1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1PER0_Pos (12UL) /*!< ADC1PER0 (Bit 12) */
+#define HRPWM_COM_ADC1R_ADC1PER0_Msk (0x1000UL) /*!< ADC1PER0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD0_Pos (11UL) /*!< ADC1CMPD0 (Bit 11) */
+#define HRPWM_COM_ADC1R_ADC1CMPD0_Msk (0x800UL) /*!< ADC1CMPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB0_Pos (10UL) /*!< ADC1CMPB0 (Bit 10) */
+#define HRPWM_COM_ADC1R_ADC1CMPB0_Msk (0x400UL) /*!< ADC1CMPB0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1EEV9_Pos (9UL) /*!< ADC1EEV9 (Bit 9) */
+#define HRPWM_COM_ADC1R_ADC1EEV9_Msk (0x200UL) /*!< ADC1EEV9 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1EEV8_Pos (8UL) /*!< ADC1EEV8 (Bit 8) */
+#define HRPWM_COM_ADC1R_ADC1EEV8_Msk (0x100UL) /*!< ADC1EEV8 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1EEV7_Pos (7UL) /*!< ADC1EEV7 (Bit 7) */
+#define HRPWM_COM_ADC1R_ADC1EEV7_Msk (0x80UL) /*!< ADC1EEV7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1EEV6_Pos (6UL) /*!< ADC1EEV6 (Bit 6) */
+#define HRPWM_COM_ADC1R_ADC1EEV6_Msk (0x40UL) /*!< ADC1EEV6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1EEV5_Pos (5UL) /*!< ADC1EEV5 (Bit 5) */
+#define HRPWM_COM_ADC1R_ADC1EEV5_Msk (0x20UL) /*!< ADC1EEV5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1MPER_Pos (4UL) /*!< ADC1MPER (Bit 4) */
+#define HRPWM_COM_ADC1R_ADC1MPER_Msk (0x10UL) /*!< ADC1MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1MCMPD_Pos (3UL) /*!< ADC1MCMPD (Bit 3) */
+#define HRPWM_COM_ADC1R_ADC1MCMPD_Msk (0x8UL) /*!< ADC1MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1MCMPC_Pos (2UL) /*!< ADC1MCMPC (Bit 2) */
+#define HRPWM_COM_ADC1R_ADC1MCMPC_Msk (0x4UL) /*!< ADC1MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1MCMPB_Pos (1UL) /*!< ADC1MCMPB (Bit 1) */
+#define HRPWM_COM_ADC1R_ADC1MCMPB_Msk (0x2UL) /*!< ADC1MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1MCMPA_Pos (0UL) /*!< ADC1MCMPA (Bit 0) */
+#define HRPWM_COM_ADC1R_ADC1MCMPA_Msk (0x1UL) /*!< ADC1MCMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== ADC1ER ========================================================= */
+#define HRPWM_COM_ADC1ER_ADC1RST7_Pos (7UL) /*!< ADC1RST7 (Bit 7) */
+#define HRPWM_COM_ADC1ER_ADC1RST7_Msk (0x80UL) /*!< ADC1RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1PER7_Pos (6UL) /*!< ADC1PER7 (Bit 6) */
+#define HRPWM_COM_ADC1ER_ADC1PER7_Msk (0x40UL) /*!< ADC1PER7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1CMPD7_Pos (5UL) /*!< ADC1CMPD7 (Bit 5) */
+#define HRPWM_COM_ADC1ER_ADC1CMPD7_Msk (0x20UL) /*!< ADC1CMPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1CMPB7_Pos (4UL) /*!< ADC1CMPB7 (Bit 4) */
+#define HRPWM_COM_ADC1ER_ADC1CMPB7_Msk (0x10UL) /*!< ADC1CMPB7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1RST6_Pos (3UL) /*!< ADC1RST6 (Bit 3) */
+#define HRPWM_COM_ADC1ER_ADC1RST6_Msk (0x8UL) /*!< ADC1RST6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1PER6_Pos (2UL) /*!< ADC1PER6 (Bit 2) */
+#define HRPWM_COM_ADC1ER_ADC1PER6_Msk (0x4UL) /*!< ADC1PER6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1CMPD6_Pos (1UL) /*!< ADC1CMPD6 (Bit 1) */
+#define HRPWM_COM_ADC1ER_ADC1CMPD6_Msk (0x2UL) /*!< ADC1CMPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1CMPB6_Pos (0UL) /*!< ADC1CMPB6 (Bit 0) */
+#define HRPWM_COM_ADC1ER_ADC1CMPB6_Msk (0x1UL) /*!< ADC1CMPB6 (Bitfield-Mask: 0x01) */
+/* ========================================================= ADC2R ========================================================= */
+#define HRPWM_COM_ADC2R_ADC2RST5_Pos (31UL) /*!< ADC2RST5 (Bit 31) */
+#define HRPWM_COM_ADC2R_ADC2RST5_Msk (0x80000000UL) /*!< ADC2RST5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER5_Pos (30UL) /*!< ADC2PER5 (Bit 30) */
+#define HRPWM_COM_ADC2R_ADC2PER5_Msk (0x40000000UL) /*!< ADC2PER5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD5_Pos (29UL) /*!< ADC2CMPD5 (Bit 29) */
+#define HRPWM_COM_ADC2R_ADC2CMPD5_Msk (0x20000000UL) /*!< ADC2CMPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC5_Pos (28UL) /*!< ADC2CMPC5 (Bit 28) */
+#define HRPWM_COM_ADC2R_ADC2CMPC5_Msk (0x10000000UL) /*!< ADC2CMPC5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPB5_Pos (27UL) /*!< ADC2CMPB5 (Bit 27) */
+#define HRPWM_COM_ADC2R_ADC2CMPB5_Msk (0x8000000UL) /*!< ADC2CMPB5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER4_Pos (26UL) /*!< ADC2PER4 (Bit 26) */
+#define HRPWM_COM_ADC2R_ADC2PER4_Msk (0x4000000UL) /*!< ADC2PER4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD4_Pos (25UL) /*!< ADC2CMPD4 (Bit 25) */
+#define HRPWM_COM_ADC2R_ADC2CMPD4_Msk (0x2000000UL) /*!< ADC2CMPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC4_Pos (24UL) /*!< ADC2CMPC4 (Bit 24) */
+#define HRPWM_COM_ADC2R_ADC2CMPC4_Msk (0x1000000UL) /*!< ADC2CMPC4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER3_Pos (23UL) /*!< ADC2PER3 (Bit 23) */
+#define HRPWM_COM_ADC2R_ADC2PER3_Msk (0x800000UL) /*!< ADC2PER3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD3_Pos (22UL) /*!< ADC2CMPD3 (Bit 22) */
+#define HRPWM_COM_ADC2R_ADC2CMPD3_Msk (0x400000UL) /*!< ADC2CMPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC3_Pos (21UL) /*!< ADC2CMPC3 (Bit 21) */
+#define HRPWM_COM_ADC2R_ADC2CMPC3_Msk (0x200000UL) /*!< ADC2CMPC3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER2_Pos (20UL) /*!< ADC2PER2 (Bit 20) */
+#define HRPWM_COM_ADC2R_ADC2PER2_Msk (0x100000UL) /*!< ADC2PER2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD2_Pos (19UL) /*!< ADC2CMPD2 (Bit 19) */
+#define HRPWM_COM_ADC2R_ADC2CMPD2_Msk (0x80000UL) /*!< ADC2CMPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC2_Pos (18UL) /*!< ADC2CMPC2 (Bit 18) */
+#define HRPWM_COM_ADC2R_ADC2CMPC2_Msk (0x40000UL) /*!< ADC2CMPC2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2RST1_Pos (17UL) /*!< ADC2RST1 (Bit 17) */
+#define HRPWM_COM_ADC2R_ADC2RST1_Msk (0x20000UL) /*!< ADC2RST1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER1_Pos (16UL) /*!< ADC2PER1 (Bit 16) */
+#define HRPWM_COM_ADC2R_ADC2PER1_Msk (0x10000UL) /*!< ADC2PER1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD1_Pos (15UL) /*!< ADC2CMPD1 (Bit 15) */
+#define HRPWM_COM_ADC2R_ADC2CMPD1_Msk (0x8000UL) /*!< ADC2CMPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC1_Pos (14UL) /*!< ADC2CMPC1 (Bit 14) */
+#define HRPWM_COM_ADC2R_ADC2CMPC1_Msk (0x4000UL) /*!< ADC2CMPC1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2RST0_Pos (13UL) /*!< ADC2RST0 (Bit 13) */
+#define HRPWM_COM_ADC2R_ADC2RST0_Msk (0x2000UL) /*!< ADC2RST0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER0_Pos (12UL) /*!< ADC2PER0 (Bit 12) */
+#define HRPWM_COM_ADC2R_ADC2PER0_Msk (0x1000UL) /*!< ADC2PER0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD0_Pos (11UL) /*!< ADC2CMPD0 (Bit 11) */
+#define HRPWM_COM_ADC2R_ADC2CMPD0_Msk (0x800UL) /*!< ADC2CMPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC0_Pos (10UL) /*!< ADC2CMPC0 (Bit 10) */
+#define HRPWM_COM_ADC2R_ADC2CMPC0_Msk (0x400UL) /*!< ADC2CMPC0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2EEV4_Pos (9UL) /*!< ADC2EEV4 (Bit 9) */
+#define HRPWM_COM_ADC2R_ADC2EEV4_Msk (0x200UL) /*!< ADC2EEV4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2EEV3_Pos (8UL) /*!< ADC2EEV3 (Bit 8) */
+#define HRPWM_COM_ADC2R_ADC2EEV3_Msk (0x100UL) /*!< ADC2EEV3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2EEV2_Pos (7UL) /*!< ADC2EEV2 (Bit 7) */
+#define HRPWM_COM_ADC2R_ADC2EEV2_Msk (0x80UL) /*!< ADC2EEV2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2EEV1_Pos (6UL) /*!< ADC2EEV1 (Bit 6) */
+#define HRPWM_COM_ADC2R_ADC2EEV1_Msk (0x40UL) /*!< ADC2EEV1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2EEV0_Pos (5UL) /*!< ADC2EEV0 (Bit 5) */
+#define HRPWM_COM_ADC2R_ADC2EEV0_Msk (0x20UL) /*!< ADC2EEV0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2MPER_Pos (4UL) /*!< ADC2MPER (Bit 4) */
+#define HRPWM_COM_ADC2R_ADC2MPER_Msk (0x10UL) /*!< ADC2MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2MCMPD_Pos (3UL) /*!< ADC2MCMPD (Bit 3) */
+#define HRPWM_COM_ADC2R_ADC2MCMPD_Msk (0x8UL) /*!< ADC2MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2MCMPC_Pos (2UL) /*!< ADC2MCMPC (Bit 2) */
+#define HRPWM_COM_ADC2R_ADC2MCMPC_Msk (0x4UL) /*!< ADC2MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2MCMPB_Pos (1UL) /*!< ADC2MCMPB (Bit 1) */
+#define HRPWM_COM_ADC2R_ADC2MCMPB_Msk (0x2UL) /*!< ADC2MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2MCMPA_Pos (0UL) /*!< ADC2MCMPA (Bit 0) */
+#define HRPWM_COM_ADC2R_ADC2MCMPA_Msk (0x1UL) /*!< ADC2MCMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== ADC2ER ========================================================= */
+#define HRPWM_COM_ADC2ER_ADC2RST7_Pos (7UL) /*!< ADC2RST7 (Bit 7) */
+#define HRPWM_COM_ADC2ER_ADC2RST7_Msk (0x80UL) /*!< ADC2RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2PER7_Pos (6UL) /*!< ADC2PER7 (Bit 6) */
+#define HRPWM_COM_ADC2ER_ADC2PER7_Msk (0x40UL) /*!< ADC2PER7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2CMPD7_Pos (5UL) /*!< ADC2CMPD7 (Bit 5) */
+#define HRPWM_COM_ADC2ER_ADC2CMPD7_Msk (0x20UL) /*!< ADC2CMPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2CMPC7_Pos (4UL) /*!< ADC2CMPC7 (Bit 4) */
+#define HRPWM_COM_ADC2ER_ADC2CMPC7_Msk (0x10UL) /*!< ADC2CMPC7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2RST6_Pos (3UL) /*!< ADC2RST6 (Bit 3) */
+#define HRPWM_COM_ADC2ER_ADC2RST6_Msk (0x8UL) /*!< ADC2RST6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2PER6_Pos (2UL) /*!< ADC2PER6 (Bit 2) */
+#define HRPWM_COM_ADC2ER_ADC2PER6_Msk (0x4UL) /*!< ADC2PER6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2CMPD6_Pos (1UL) /*!< ADC2CMPD6 (Bit 1) */
+#define HRPWM_COM_ADC2ER_ADC2CMPD6_Msk (0x2UL) /*!< ADC2CMPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2CMPC6_Pos (0UL) /*!< ADC2CMPC6 (Bit 0) */
+#define HRPWM_COM_ADC2ER_ADC2CMPC6_Msk (0x1UL) /*!< ADC2CMPC6 (Bitfield-Mask: 0x01) */
+/* ========================================================= ADC3R ========================================================= */
+#define HRPWM_COM_ADC3R_ADC3PER5_Pos (31UL) /*!< ADC3PER5 (Bit 31) */
+#define HRPWM_COM_ADC3R_ADC3PER5_Msk (0x80000000UL) /*!< ADC3PER5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD5_Pos (30UL) /*!< ADC3CMPD5 (Bit 30) */
+#define HRPWM_COM_ADC3R_ADC3CMPD5_Msk (0x40000000UL) /*!< ADC3CMPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPC5_Pos (29UL) /*!< ADC3CMPC5 (Bit 29) */
+#define HRPWM_COM_ADC3R_ADC3CMPC5_Msk (0x20000000UL) /*!< ADC3CMPC5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB5_Pos (28UL) /*!< ADC3CMPB5 (Bit 28) */
+#define HRPWM_COM_ADC3R_ADC3CMPB5_Msk (0x10000000UL) /*!< ADC3CMPB5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3RST4_Pos (27UL) /*!< ADC3RST4 (Bit 27) */
+#define HRPWM_COM_ADC3R_ADC3RST4_Msk (0x8000000UL) /*!< ADC3RST4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD4_Pos (26UL) /*!< ADC3CMPD4 (Bit 26) */
+#define HRPWM_COM_ADC3R_ADC3CMPD4_Msk (0x4000000UL) /*!< ADC3CMPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPC4_Pos (25UL) /*!< ADC3CMPC4 (Bit 25) */
+#define HRPWM_COM_ADC3R_ADC3CMPC4_Msk (0x2000000UL) /*!< ADC3CMPC4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB4_Pos (24UL) /*!< ADC3CMPB4 (Bit 24) */
+#define HRPWM_COM_ADC3R_ADC3CMPB4_Msk (0x1000000UL) /*!< ADC3CMPB4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3RST3_Pos (23UL) /*!< ADC3RST3 (Bit 23) */
+#define HRPWM_COM_ADC3R_ADC3RST3_Msk (0x800000UL) /*!< ADC3RST3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3PER3_Pos (22UL) /*!< ADC3PER3 (Bit 22) */
+#define HRPWM_COM_ADC3R_ADC3PER3_Msk (0x400000UL) /*!< ADC3PER3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD3_Pos (21UL) /*!< ADC3CMPD3 (Bit 21) */
+#define HRPWM_COM_ADC3R_ADC3CMPD3_Msk (0x200000UL) /*!< ADC3CMPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB3_Pos (20UL) /*!< ADC3CMPB3 (Bit 20) */
+#define HRPWM_COM_ADC3R_ADC3CMPB3_Msk (0x100000UL) /*!< ADC3CMPB3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3RST2_Pos (19UL) /*!< ADC3RST2 (Bit 19) */
+#define HRPWM_COM_ADC3R_ADC3RST2_Msk (0x80000UL) /*!< ADC3RST2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3PER2_Pos (18UL) /*!< ADC3PER2 (Bit 18) */
+#define HRPWM_COM_ADC3R_ADC3PER2_Msk (0x40000UL) /*!< ADC3PER2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD2_Pos (17UL) /*!< ADC3CMPD2 (Bit 17) */
+#define HRPWM_COM_ADC3R_ADC3CMPD2_Msk (0x20000UL) /*!< ADC3CMPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB2_Pos (16UL) /*!< ADC3CMPB2 (Bit 16) */
+#define HRPWM_COM_ADC3R_ADC3CMPB2_Msk (0x10000UL) /*!< ADC3CMPB2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3PER1_Pos (15UL) /*!< ADC3PER1 (Bit 15) */
+#define HRPWM_COM_ADC3R_ADC3PER1_Msk (0x8000UL) /*!< ADC3PER1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD1_Pos (14UL) /*!< ADC3CMPD1 (Bit 14) */
+#define HRPWM_COM_ADC3R_ADC3CMPD1_Msk (0x4000UL) /*!< ADC3CMPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB1_Pos (13UL) /*!< ADC3CMPB1 (Bit 13) */
+#define HRPWM_COM_ADC3R_ADC3CMPB1_Msk (0x2000UL) /*!< ADC3CMPB1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3PER0_Pos (12UL) /*!< ADC3PER0 (Bit 12) */
+#define HRPWM_COM_ADC3R_ADC3PER0_Msk (0x1000UL) /*!< ADC3PER0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD0_Pos (11UL) /*!< ADC3CMPD0 (Bit 11) */
+#define HRPWM_COM_ADC3R_ADC3CMPD0_Msk (0x800UL) /*!< ADC3CMPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB0_Pos (10UL) /*!< ADC3CMPB0 (Bit 10) */
+#define HRPWM_COM_ADC3R_ADC3CMPB0_Msk (0x400UL) /*!< ADC3CMPB0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3EEV9_Pos (9UL) /*!< ADC3EEV9 (Bit 9) */
+#define HRPWM_COM_ADC3R_ADC3EEV9_Msk (0x200UL) /*!< ADC3EEV9 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3EEV8_Pos (8UL) /*!< ADC3EEV8 (Bit 8) */
+#define HRPWM_COM_ADC3R_ADC3EEV8_Msk (0x100UL) /*!< ADC3EEV8 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3EEV7_Pos (7UL) /*!< ADC3EEV7 (Bit 7) */
+#define HRPWM_COM_ADC3R_ADC3EEV7_Msk (0x80UL) /*!< ADC3EEV7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3EEV6_Pos (6UL) /*!< ADC3EEV6 (Bit 6) */
+#define HRPWM_COM_ADC3R_ADC3EEV6_Msk (0x40UL) /*!< ADC3EEV6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3EEV5_Pos (5UL) /*!< ADC3EEV5 (Bit 5) */
+#define HRPWM_COM_ADC3R_ADC3EEV5_Msk (0x20UL) /*!< ADC3EEV5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3MPER_Pos (4UL) /*!< ADC3MPER (Bit 4) */
+#define HRPWM_COM_ADC3R_ADC3MPER_Msk (0x10UL) /*!< ADC3MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3MCMPD_Pos (3UL) /*!< ADC3MCMPD (Bit 3) */
+#define HRPWM_COM_ADC3R_ADC3MCMPD_Msk (0x8UL) /*!< ADC3MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3MCMPC_Pos (2UL) /*!< ADC3MCMPC (Bit 2) */
+#define HRPWM_COM_ADC3R_ADC3MCMPC_Msk (0x4UL) /*!< ADC3MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3MCMPB_Pos (1UL) /*!< ADC3MCMPB (Bit 1) */
+#define HRPWM_COM_ADC3R_ADC3MCMPB_Msk (0x2UL) /*!< ADC3MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3MCMPA_Pos (0UL) /*!< ADC3MCMPA (Bit 0) */
+#define HRPWM_COM_ADC3R_ADC3MCMPA_Msk (0x1UL) /*!< ADC3MCMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== ADC3ER ========================================================= */
+#define HRPWM_COM_ADC3ER_ADC3RST7_Pos (7UL) /*!< ADC3RST7 (Bit 7) */
+#define HRPWM_COM_ADC3ER_ADC3RST7_Msk (0x80UL) /*!< ADC3RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3PER7_Pos (6UL) /*!< ADC3PER7 (Bit 6) */
+#define HRPWM_COM_ADC3ER_ADC3PER7_Msk (0x40UL) /*!< ADC3PER7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3CMPD7_Pos (5UL) /*!< ADC3CMPD7 (Bit 5) */
+#define HRPWM_COM_ADC3ER_ADC3CMPD7_Msk (0x20UL) /*!< ADC3CMPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3CMPB7_Pos (4UL) /*!< ADC3CMPB7 (Bit 4) */
+#define HRPWM_COM_ADC3ER_ADC3CMPB7_Msk (0x10UL) /*!< ADC3CMPB7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3RST6_Pos (3UL) /*!< ADC3RST6 (Bit 3) */
+#define HRPWM_COM_ADC3ER_ADC3RST6_Msk (0x8UL) /*!< ADC3RST6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3PER6_Pos (2UL) /*!< ADC3PER6 (Bit 2) */
+#define HRPWM_COM_ADC3ER_ADC3PER6_Msk (0x4UL) /*!< ADC3PER6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3CMPD6_Pos (1UL) /*!< ADC3CMPD6 (Bit 1) */
+#define HRPWM_COM_ADC3ER_ADC3CMPD6_Msk (0x2UL) /*!< ADC3CMPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3CMPB6_Pos (0UL) /*!< ADC3CMPB6 (Bit 0) */
+#define HRPWM_COM_ADC3ER_ADC3CMPB6_Msk (0x1UL) /*!< ADC3CMPB6 (Bitfield-Mask: 0x01) */
+/* ========================================================= ADC4R ========================================================= */
+#define HRPWM_COM_ADC4R_ADC6TRG_Pos (16UL) /*!< ADC6TRG (Bit 16) */
+#define HRPWM_COM_ADC4R_ADC6TRG_Msk (0x3f0000UL) /*!< ADC6TRG (Bitfield-Mask: 0x3f) */
+#define HRPWM_COM_ADC4R_ADC5TRG_Pos (8UL) /*!< ADC5TRG (Bit 8) */
+#define HRPWM_COM_ADC4R_ADC5TRG_Msk (0x3f00UL) /*!< ADC5TRG (Bitfield-Mask: 0x3f) */
+#define HRPWM_COM_ADC4R_ADC4TRG_Pos (0UL) /*!< ADC4TRG (Bit 0) */
+#define HRPWM_COM_ADC4R_ADC4TRG_Msk (0x3fUL) /*!< ADC4TRG (Bitfield-Mask: 0x3f) */
+/* ========================================================= ADC5R ========================================================= */
+#define HRPWM_COM_ADC5R_ADC9TRG_Pos (16UL) /*!< ADC9TRG (Bit 16) */
+#define HRPWM_COM_ADC5R_ADC9TRG_Msk (0x3f0000UL) /*!< ADC9TRG (Bitfield-Mask: 0x3f) */
+#define HRPWM_COM_ADC5R_ADC8TRG_Pos (8UL) /*!< ADC8TRG (Bit 8) */
+#define HRPWM_COM_ADC5R_ADC8TRG_Msk (0x3f00UL) /*!< ADC8TRG (Bitfield-Mask: 0x3f) */
+#define HRPWM_COM_ADC5R_ADC7TRG_Pos (0UL) /*!< ADC7TRG (Bit 0) */
+#define HRPWM_COM_ADC5R_ADC7TRG_Msk (0x3fUL) /*!< ADC7TRG (Bitfield-Mask: 0x3f) */
+/* ========================================================= ADCUR ========================================================= */
+#define HRPWM_COM_ADCUR_USRC9_Pos (20UL) /*!< USRC9 (Bit 20) */
+#define HRPWM_COM_ADCUR_USRC9_Msk (0xf00000UL) /*!< USRC9 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCUR_USRC8_Pos (16UL) /*!< USRC8 (Bit 16) */
+#define HRPWM_COM_ADCUR_USRC8_Msk (0xf0000UL) /*!< USRC8 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCUR_USRC7_Pos (12UL) /*!< USRC7 (Bit 12) */
+#define HRPWM_COM_ADCUR_USRC7_Msk (0xf000UL) /*!< USRC7 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCUR_USRC6_Pos (8UL) /*!< USRC6 (Bit 8) */
+#define HRPWM_COM_ADCUR_USRC6_Msk (0xf00UL) /*!< USRC6 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCUR_USRC5_Pos (4UL) /*!< USRC5 (Bit 4) */
+#define HRPWM_COM_ADCUR_USRC5_Msk (0xf0UL) /*!< USRC5 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCUR_USRC4_Pos (0UL) /*!< USRC4 (Bit 0) */
+#define HRPWM_COM_ADCUR_USRC4_Msk (0xfUL) /*!< USRC4 (Bitfield-Mask: 0x0f) */
+/* ========================================================= ADCLR ========================================================= */
+#define HRPWM_COM_ADCLR_TLEN9_Pos (20UL) /*!< TLEN9 (Bit 20) */
+#define HRPWM_COM_ADCLR_TLEN9_Msk (0xf00000UL) /*!< TLEN9 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCLR_TLEN8_Pos (16UL) /*!< TLEN8 (Bit 16) */
+#define HRPWM_COM_ADCLR_TLEN8_Msk (0xf0000UL) /*!< TLEN8 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCLR_TLEN7_Pos (12UL) /*!< TLEN7 (Bit 12) */
+#define HRPWM_COM_ADCLR_TLEN7_Msk (0xf000UL) /*!< TLEN7 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCLR_TLEN6_Pos (8UL) /*!< TLEN6 (Bit 8) */
+#define HRPWM_COM_ADCLR_TLEN6_Msk (0xf00UL) /*!< TLEN6 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCLR_TLEN5_Pos (4UL) /*!< TLEN5 (Bit 4) */
+#define HRPWM_COM_ADCLR_TLEN5_Msk (0xf0UL) /*!< TLEN5 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCLR_TLEN4_Pos (0UL) /*!< TLEN4 (Bit 0) */
+#define HRPWM_COM_ADCLR_TLEN4_Msk (0xfUL) /*!< TLEN4 (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADPSR0 ========================================================= */
+#define HRPWM_COM_ADPSR0_PSC4_Pos (24UL) /*!< PSC4 (Bit 24) */
+#define HRPWM_COM_ADPSR0_PSC4_Msk (0x1f000000UL) /*!< PSC4 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR0_PSC3_Pos (18UL) /*!< PSC3 (Bit 18) */
+#define HRPWM_COM_ADPSR0_PSC3_Msk (0x7c0000UL) /*!< PSC3 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR0_PSC2_Pos (12UL) /*!< PSC2 (Bit 12) */
+#define HRPWM_COM_ADPSR0_PSC2_Msk (0x1f000UL) /*!< PSC2 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR0_PSC1_Pos (6UL) /*!< PSC1 (Bit 6) */
+#define HRPWM_COM_ADPSR0_PSC1_Msk (0x7c0UL) /*!< PSC1 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR0_PSC0_Pos (0UL) /*!< PSC0 (Bit 0) */
+#define HRPWM_COM_ADPSR0_PSC0_Msk (0x1fUL) /*!< PSC0 (Bitfield-Mask: 0x1f) */
+/* ======================================================== ADPSR1 ========================================================= */
+#define HRPWM_COM_ADPSR1_PSC9_Pos (24UL) /*!< PSC9 (Bit 24) */
+#define HRPWM_COM_ADPSR1_PSC9_Msk (0x1f000000UL) /*!< PSC9 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR1_PSC8_Pos (18UL) /*!< PSC8 (Bit 18) */
+#define HRPWM_COM_ADPSR1_PSC8_Msk (0x7c0000UL) /*!< PSC8 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR1_PSC7_Pos (12UL) /*!< PSC7 (Bit 12) */
+#define HRPWM_COM_ADPSR1_PSC7_Msk (0x1f000UL) /*!< PSC7 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR1_PSC6_Pos (6UL) /*!< PSC6 (Bit 6) */
+#define HRPWM_COM_ADPSR1_PSC6_Msk (0x7c0UL) /*!< PSC6 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR1_PSC5_Pos (0UL) /*!< PSC5 (Bit 0) */
+#define HRPWM_COM_ADPSR1_PSC5_Msk (0x1fUL) /*!< PSC5 (Bitfield-Mask: 0x1f) */
+/* ========================================================= DLLCR ========================================================= */
+#define HRPWM_COM_DLLCR_DLLLCK_Pos (31UL) /*!< DLLLCK (Bit 31) */
+#define HRPWM_COM_DLLCR_DLLLCK_Msk (0x80000000UL) /*!< DLLLCK (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_DLLCR_DLLTHRES0_Pos (11UL) /*!< DLLTHRES0 (Bit 11) */
+#define HRPWM_COM_DLLCR_DLLTHRES0_Msk (0xf800UL) /*!< DLLTHRES0 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_DLLCR_DLLTHRES1_Pos (6UL) /*!< DLLTHRES1 (Bit 6) */
+#define HRPWM_COM_DLLCR_DLLTHRES1_Msk (0x7c0UL) /*!< DLLTHRES1 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_DLLCR_DLLSTART_Pos (3UL) /*!< DLLSTART (Bit 3) */
+#define HRPWM_COM_DLLCR_DLLSTART_Msk (0x8UL) /*!< DLLSTART (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_DLLCR_DLLGCP_Pos (1UL) /*!< DLLGCP (Bit 1) */
+#define HRPWM_COM_DLLCR_DLLGCP_Msk (0x6UL) /*!< DLLGCP (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_DLLCR_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */
+#define HRPWM_COM_DLLCR_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */
+/* ========================================================= EECER ========================================================= */
+#define HRPWM_COM_EECER_EE9SRCH_Pos (18UL) /*!< EE9SRCH (Bit 18) */
+#define HRPWM_COM_EECER_EE9SRCH_Msk (0xc0000UL) /*!< EE9SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE8SRCH_Pos (16UL) /*!< EE8SRCH (Bit 16) */
+#define HRPWM_COM_EECER_EE8SRCH_Msk (0x30000UL) /*!< EE8SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE7SRCH_Pos (14UL) /*!< EE7SRCH (Bit 14) */
+#define HRPWM_COM_EECER_EE7SRCH_Msk (0xc000UL) /*!< EE7SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE6SRCH_Pos (12UL) /*!< EE6SRCH (Bit 12) */
+#define HRPWM_COM_EECER_EE6SRCH_Msk (0x3000UL) /*!< EE6SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE5SRCH_Pos (10UL) /*!< EE5SRCH (Bit 10) */
+#define HRPWM_COM_EECER_EE5SRCH_Msk (0xc00UL) /*!< EE5SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE4SRCH_Pos (8UL) /*!< EE4SRCH (Bit 8) */
+#define HRPWM_COM_EECER_EE4SRCH_Msk (0x300UL) /*!< EE4SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE3SRCH_Pos (6UL) /*!< EE3SRCH (Bit 6) */
+#define HRPWM_COM_EECER_EE3SRCH_Msk (0xc0UL) /*!< EE3SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE2SRCH_Pos (4UL) /*!< EE2SRCH (Bit 4) */
+#define HRPWM_COM_EECER_EE2SRCH_Msk (0x30UL) /*!< EE2SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE1SRCH_Pos (2UL) /*!< EE1SRCH (Bit 2) */
+#define HRPWM_COM_EECER_EE1SRCH_Msk (0xcUL) /*!< EE1SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE0SRCH_Pos (0UL) /*!< EE0SRCH (Bit 0) */
+#define HRPWM_COM_EECER_EE0SRCH_Msk (0x3UL) /*!< EE0SRCH (Bitfield-Mask: 0x03) */
+/* ======================================================== FLTINR0 ======================================================== */
+#define HRPWM_COM_FLTINR0_FLT7SRC_Pos (30UL) /*!< FLT7SRC (Bit 30) */
+#define HRPWM_COM_FLTINR0_FLT7SRC_Msk (0xc0000000UL) /*!< FLT7SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT7P_Pos (29UL) /*!< FLT7P (Bit 29) */
+#define HRPWM_COM_FLTINR0_FLT7P_Msk (0x20000000UL) /*!< FLT7P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT7E_Pos (28UL) /*!< FLT7E (Bit 28) */
+#define HRPWM_COM_FLTINR0_FLT7E_Msk (0x10000000UL) /*!< FLT7E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT6SRC_Pos (26UL) /*!< FLT6SRC (Bit 26) */
+#define HRPWM_COM_FLTINR0_FLT6SRC_Msk (0xc000000UL) /*!< FLT6SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT6P_Pos (25UL) /*!< FLT6P (Bit 25) */
+#define HRPWM_COM_FLTINR0_FLT6P_Msk (0x2000000UL) /*!< FLT6P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT6E_Pos (24UL) /*!< FLT6E (Bit 24) */
+#define HRPWM_COM_FLTINR0_FLT6E_Msk (0x1000000UL) /*!< FLT6E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT5SRC_Pos (22UL) /*!< FLT5SRC (Bit 22) */
+#define HRPWM_COM_FLTINR0_FLT5SRC_Msk (0xc00000UL) /*!< FLT5SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT5P_Pos (21UL) /*!< FLT5P (Bit 21) */
+#define HRPWM_COM_FLTINR0_FLT5P_Msk (0x200000UL) /*!< FLT5P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT5E_Pos (20UL) /*!< FLT5E (Bit 20) */
+#define HRPWM_COM_FLTINR0_FLT5E_Msk (0x100000UL) /*!< FLT5E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT4SRC_Pos (18UL) /*!< FLT4SRC (Bit 18) */
+#define HRPWM_COM_FLTINR0_FLT4SRC_Msk (0xc0000UL) /*!< FLT4SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT4P_Pos (17UL) /*!< FLT4P (Bit 17) */
+#define HRPWM_COM_FLTINR0_FLT4P_Msk (0x20000UL) /*!< FLT4P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT4E_Pos (16UL) /*!< FLT4E (Bit 16) */
+#define HRPWM_COM_FLTINR0_FLT4E_Msk (0x10000UL) /*!< FLT4E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT3SRC_Pos (14UL) /*!< FLT3SRC (Bit 14) */
+#define HRPWM_COM_FLTINR0_FLT3SRC_Msk (0xc000UL) /*!< FLT3SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT3P_Pos (13UL) /*!< FLT3P (Bit 13) */
+#define HRPWM_COM_FLTINR0_FLT3P_Msk (0x2000UL) /*!< FLT3P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT3E_Pos (12UL) /*!< FLT3E (Bit 12) */
+#define HRPWM_COM_FLTINR0_FLT3E_Msk (0x1000UL) /*!< FLT3E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT2SRC_Pos (10UL) /*!< FLT2SRC (Bit 10) */
+#define HRPWM_COM_FLTINR0_FLT2SRC_Msk (0xc00UL) /*!< FLT2SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT2P_Pos (9UL) /*!< FLT2P (Bit 9) */
+#define HRPWM_COM_FLTINR0_FLT2P_Msk (0x200UL) /*!< FLT2P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT2E_Pos (8UL) /*!< FLT2E (Bit 8) */
+#define HRPWM_COM_FLTINR0_FLT2E_Msk (0x100UL) /*!< FLT2E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT1SRC_Pos (6UL) /*!< FLT1SRC (Bit 6) */
+#define HRPWM_COM_FLTINR0_FLT1SRC_Msk (0xc0UL) /*!< FLT1SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT1P_Pos (5UL) /*!< FLT1P (Bit 5) */
+#define HRPWM_COM_FLTINR0_FLT1P_Msk (0x20UL) /*!< FLT1P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT1E_Pos (4UL) /*!< FLT1E (Bit 4) */
+#define HRPWM_COM_FLTINR0_FLT1E_Msk (0x10UL) /*!< FLT1E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT0SRC_Pos (2UL) /*!< FLT0SRC (Bit 2) */
+#define HRPWM_COM_FLTINR0_FLT0SRC_Msk (0xcUL) /*!< FLT0SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT0P_Pos (1UL) /*!< FLT0P (Bit 1) */
+#define HRPWM_COM_FLTINR0_FLT0P_Msk (0x2UL) /*!< FLT0P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT0E_Pos (0UL) /*!< FLT0E (Bit 0) */
+#define HRPWM_COM_FLTINR0_FLT0E_Msk (0x1UL) /*!< FLT0E (Bitfield-Mask: 0x01) */
+/* ======================================================== FLTINR1 ======================================================== */
+#define HRPWM_COM_FLTINR1_FLTSD_Pos (30UL) /*!< FLTSD (Bit 30) */
+#define HRPWM_COM_FLTINR1_FLTSD_Msk (0xc0000000UL) /*!< FLTSD (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR1_FLT5F_Pos (20UL) /*!< FLT5F (Bit 20) */
+#define HRPWM_COM_FLTINR1_FLT5F_Msk (0xf00000UL) /*!< FLT5F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR1_FLT4F_Pos (16UL) /*!< FLT4F (Bit 16) */
+#define HRPWM_COM_FLTINR1_FLT4F_Msk (0xf0000UL) /*!< FLT4F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR1_FLT3F_Pos (12UL) /*!< FLT3F (Bit 12) */
+#define HRPWM_COM_FLTINR1_FLT3F_Msk (0xf000UL) /*!< FLT3F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR1_FLT2F_Pos (8UL) /*!< FLT2F (Bit 8) */
+#define HRPWM_COM_FLTINR1_FLT2F_Msk (0xf00UL) /*!< FLT2F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR1_FLT1F_Pos (4UL) /*!< FLT1F (Bit 4) */
+#define HRPWM_COM_FLTINR1_FLT1F_Msk (0xf0UL) /*!< FLT1F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR1_FLT0F_Pos (0UL) /*!< FLT0F (Bit 0) */
+#define HRPWM_COM_FLTINR1_FLT0F_Msk (0xfUL) /*!< FLT0F (Bitfield-Mask: 0x0f) */
+/* ======================================================== FLTINER ======================================================== */
+#define HRPWM_COM_FLTINER_FLT7F_Pos (4UL) /*!< FLT7F (Bit 4) */
+#define HRPWM_COM_FLTINER_FLT7F_Msk (0xf0UL) /*!< FLT7F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINER_FLT6F_Pos (0UL) /*!< FLT6F (Bit 0) */
+#define HRPWM_COM_FLTINER_FLT6F_Msk (0xfUL) /*!< FLT6F (Bitfield-Mask: 0x0f) */
+/* ======================================================== FLTINR2 ======================================================== */
+#define HRPWM_COM_FLTINR2_FLT7RSTM_Pos (31UL) /*!< FLT7RSTM (Bit 31) */
+#define HRPWM_COM_FLTINR2_FLT7RSTM_Msk (0x80000000UL) /*!< FLT7RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT7CRES_Pos (30UL) /*!< FLT7CRES (Bit 30) */
+#define HRPWM_COM_FLTINR2_FLT7CRES_Msk (0x40000000UL) /*!< FLT7CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT7BLKS_Pos (29UL) /*!< FLT7BLKS (Bit 29) */
+#define HRPWM_COM_FLTINR2_FLT7BLKS_Msk (0x20000000UL) /*!< FLT7BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT7BLKE_Pos (28UL) /*!< FLT7BLKE (Bit 28) */
+#define HRPWM_COM_FLTINR2_FLT7BLKE_Msk (0x10000000UL) /*!< FLT7BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT6RSTM_Pos (27UL) /*!< FLT6RSTM (Bit 27) */
+#define HRPWM_COM_FLTINR2_FLT6RSTM_Msk (0x8000000UL) /*!< FLT6RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT6CRES_Pos (26UL) /*!< FLT6CRES (Bit 26) */
+#define HRPWM_COM_FLTINR2_FLT6CRES_Msk (0x4000000UL) /*!< FLT6CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT6BLKS_Pos (25UL) /*!< FLT6BLKS (Bit 25) */
+#define HRPWM_COM_FLTINR2_FLT6BLKS_Msk (0x2000000UL) /*!< FLT6BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT6BLKE_Pos (24UL) /*!< FLT6BLKE (Bit 24) */
+#define HRPWM_COM_FLTINR2_FLT6BLKE_Msk (0x1000000UL) /*!< FLT6BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT5RSTM_Pos (23UL) /*!< FLT5RSTM (Bit 23) */
+#define HRPWM_COM_FLTINR2_FLT5RSTM_Msk (0x800000UL) /*!< FLT5RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT5CRES_Pos (22UL) /*!< FLT5CRES (Bit 22) */
+#define HRPWM_COM_FLTINR2_FLT5CRES_Msk (0x400000UL) /*!< FLT5CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT5BLKS_Pos (21UL) /*!< FLT5BLKS (Bit 21) */
+#define HRPWM_COM_FLTINR2_FLT5BLKS_Msk (0x200000UL) /*!< FLT5BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT5BLKE_Pos (20UL) /*!< FLT5BLKE (Bit 20) */
+#define HRPWM_COM_FLTINR2_FLT5BLKE_Msk (0x100000UL) /*!< FLT5BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT4RSTM_Pos (19UL) /*!< FLT4RSTM (Bit 19) */
+#define HRPWM_COM_FLTINR2_FLT4RSTM_Msk (0x80000UL) /*!< FLT4RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT4CRES_Pos (18UL) /*!< FLT4CRES (Bit 18) */
+#define HRPWM_COM_FLTINR2_FLT4CRES_Msk (0x40000UL) /*!< FLT4CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT4BLKS_Pos (17UL) /*!< FLT4BLKS (Bit 17) */
+#define HRPWM_COM_FLTINR2_FLT4BLKS_Msk (0x20000UL) /*!< FLT4BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT4BLKE_Pos (16UL) /*!< FLT4BLKE (Bit 16) */
+#define HRPWM_COM_FLTINR2_FLT4BLKE_Msk (0x10000UL) /*!< FLT4BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT3RSTM_Pos (15UL) /*!< FLT3RSTM (Bit 15) */
+#define HRPWM_COM_FLTINR2_FLT3RSTM_Msk (0x8000UL) /*!< FLT3RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT3CRES_Pos (14UL) /*!< FLT3CRES (Bit 14) */
+#define HRPWM_COM_FLTINR2_FLT3CRES_Msk (0x4000UL) /*!< FLT3CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT3BLKS_Pos (13UL) /*!< FLT3BLKS (Bit 13) */
+#define HRPWM_COM_FLTINR2_FLT3BLKS_Msk (0x2000UL) /*!< FLT3BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT3BLKE_Pos (12UL) /*!< FLT3BLKE (Bit 12) */
+#define HRPWM_COM_FLTINR2_FLT3BLKE_Msk (0x1000UL) /*!< FLT3BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT2RSTM_Pos (11UL) /*!< FLT2RSTM (Bit 11) */
+#define HRPWM_COM_FLTINR2_FLT2RSTM_Msk (0x800UL) /*!< FLT2RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT2CRES_Pos (10UL) /*!< FLT2CRES (Bit 10) */
+#define HRPWM_COM_FLTINR2_FLT2CRES_Msk (0x400UL) /*!< FLT2CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT2BLKS_Pos (9UL) /*!< FLT2BLKS (Bit 9) */
+#define HRPWM_COM_FLTINR2_FLT2BLKS_Msk (0x200UL) /*!< FLT2BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT2BLKE_Pos (8UL) /*!< FLT2BLKE (Bit 8) */
+#define HRPWM_COM_FLTINR2_FLT2BLKE_Msk (0x100UL) /*!< FLT2BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT1RSTM_Pos (7UL) /*!< FLT1RSTM (Bit 7) */
+#define HRPWM_COM_FLTINR2_FLT1RSTM_Msk (0x80UL) /*!< FLT1RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT1CRES_Pos (6UL) /*!< FLT1CRES (Bit 6) */
+#define HRPWM_COM_FLTINR2_FLT1CRES_Msk (0x40UL) /*!< FLT1CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT1BLKS_Pos (5UL) /*!< FLT1BLKS (Bit 5) */
+#define HRPWM_COM_FLTINR2_FLT1BLKS_Msk (0x20UL) /*!< FLT1BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT1BLKE_Pos (4UL) /*!< FLT1BLKE (Bit 4) */
+#define HRPWM_COM_FLTINR2_FLT1BLKE_Msk (0x10UL) /*!< FLT1BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT0RSTM_Pos (3UL) /*!< FLT0RSTM (Bit 3) */
+#define HRPWM_COM_FLTINR2_FLT0RSTM_Msk (0x8UL) /*!< FLT0RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT0CRES_Pos (2UL) /*!< FLT0CRES (Bit 2) */
+#define HRPWM_COM_FLTINR2_FLT0CRES_Msk (0x4UL) /*!< FLT0CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT0BLKS_Pos (1UL) /*!< FLT0BLKS (Bit 1) */
+#define HRPWM_COM_FLTINR2_FLT0BLKS_Msk (0x2UL) /*!< FLT0BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT0BLKE_Pos (0UL) /*!< FLT0BLKE (Bit 0) */
+#define HRPWM_COM_FLTINR2_FLT0BLKE_Msk (0x1UL) /*!< FLT0BLKE (Bitfield-Mask: 0x01) */
+/* ======================================================== FLTINR3 ======================================================== */
+#define HRPWM_COM_FLTINR3_FLT7CNT_Pos (28UL) /*!< FLT7CNT (Bit 28) */
+#define HRPWM_COM_FLTINR3_FLT7CNT_Msk (0xf0000000UL) /*!< FLT7CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT6CNT_Pos (24UL) /*!< FLT6CNT (Bit 24) */
+#define HRPWM_COM_FLTINR3_FLT6CNT_Msk (0xf000000UL) /*!< FLT6CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT5CNT_Pos (20UL) /*!< FLT5CNT (Bit 20) */
+#define HRPWM_COM_FLTINR3_FLT5CNT_Msk (0xf00000UL) /*!< FLT5CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT4CNT_Pos (16UL) /*!< FLT4CNT (Bit 16) */
+#define HRPWM_COM_FLTINR3_FLT4CNT_Msk (0xf0000UL) /*!< FLT4CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT3CNT_Pos (12UL) /*!< FLT3CNT (Bit 12) */
+#define HRPWM_COM_FLTINR3_FLT3CNT_Msk (0xf000UL) /*!< FLT3CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT2CNT_Pos (8UL) /*!< FLT2CNT (Bit 8) */
+#define HRPWM_COM_FLTINR3_FLT2CNT_Msk (0xf00UL) /*!< FLT2CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT1CNT_Pos (4UL) /*!< FLT1CNT (Bit 4) */
+#define HRPWM_COM_FLTINR3_FLT1CNT_Msk (0xf0UL) /*!< FLT1CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT0CNT_Pos (0UL) /*!< FLT0CNT (Bit 0) */
+#define HRPWM_COM_FLTINR3_FLT0CNT_Msk (0xfUL) /*!< FLT0CNT (Bitfield-Mask: 0x0f) */
+/* ========================================================= BMCR ========================================================== */
+#define HRPWM_COM_BMCR_BMSTAT_Pos (31UL) /*!< BMSTAT (Bit 31) */
+#define HRPWM_COM_BMCR_BMSTAT_Msk (0x80000000UL) /*!< BMSTAT (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMEXIT_Pos (30UL) /*!< BMEXIT (Bit 30) */
+#define HRPWM_COM_BMCR_BMEXIT_Msk (0x40000000UL) /*!< BMEXIT (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS7_Pos (24UL) /*!< BMDIS7 (Bit 24) */
+#define HRPWM_COM_BMCR_BMDIS7_Msk (0x1000000UL) /*!< BMDIS7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS6_Pos (23UL) /*!< BMDIS6 (Bit 23) */
+#define HRPWM_COM_BMCR_BMDIS6_Msk (0x800000UL) /*!< BMDIS6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS5_Pos (22UL) /*!< BMDIS5 (Bit 22) */
+#define HRPWM_COM_BMCR_BMDIS5_Msk (0x400000UL) /*!< BMDIS5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS4_Pos (21UL) /*!< BMDIS4 (Bit 21) */
+#define HRPWM_COM_BMCR_BMDIS4_Msk (0x200000UL) /*!< BMDIS4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS3_Pos (20UL) /*!< BMDIS3 (Bit 20) */
+#define HRPWM_COM_BMCR_BMDIS3_Msk (0x100000UL) /*!< BMDIS3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS2_Pos (19UL) /*!< BMDIS2 (Bit 19) */
+#define HRPWM_COM_BMCR_BMDIS2_Msk (0x80000UL) /*!< BMDIS2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS1_Pos (18UL) /*!< BMDIS1 (Bit 18) */
+#define HRPWM_COM_BMCR_BMDIS1_Msk (0x40000UL) /*!< BMDIS1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS0_Pos (17UL) /*!< BMDIS0 (Bit 17) */
+#define HRPWM_COM_BMCR_BMDIS0_Msk (0x20000UL) /*!< BMDIS0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_MBMDIS_Pos (16UL) /*!< MBMDIS (Bit 16) */
+#define HRPWM_COM_BMCR_MBMDIS_Msk (0x10000UL) /*!< MBMDIS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMTM_Pos (11UL) /*!< BMTM (Bit 11) */
+#define HRPWM_COM_BMCR_BMTM_Msk (0x800UL) /*!< BMTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMPREN_Pos (10UL) /*!< BMPREN (Bit 10) */
+#define HRPWM_COM_BMCR_BMPREN_Msk (0x400UL) /*!< BMPREN (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMPRSC_Pos (6UL) /*!< BMPRSC (Bit 6) */
+#define HRPWM_COM_BMCR_BMPRSC_Msk (0x3c0UL) /*!< BMPRSC (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_BMCR_BMCLK_Pos (2UL) /*!< BMCLK (Bit 2) */
+#define HRPWM_COM_BMCR_BMCLK_Msk (0x3cUL) /*!< BMCLK (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_BMCR_BMOM_Pos (1UL) /*!< BMOM (Bit 1) */
+#define HRPWM_COM_BMCR_BMOM_Msk (0x2UL) /*!< BMOM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BME_Pos (0UL) /*!< BME (Bit 0) */
+#define HRPWM_COM_BMCR_BME_Msk (0x1UL) /*!< BME (Bitfield-Mask: 0x01) */
+/* ======================================================== BMTRGR0 ======================================================== */
+#define HRPWM_COM_BMTRGR0_OCHPEV_Pos (31UL) /*!< OCHPEV (Bit 31) */
+#define HRPWM_COM_BMTRGR0_OCHPEV_Msk (0x80000000UL) /*!< OCHPEV (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_EEV8_Pos (30UL) /*!< EEV8 (Bit 30) */
+#define HRPWM_COM_BMTRGR0_EEV8_Msk (0x40000000UL) /*!< EEV8 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_EEV7_Pos (29UL) /*!< EEV7 (Bit 29) */
+#define HRPWM_COM_BMTRGR0_EEV7_Msk (0x20000000UL) /*!< EEV7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_PER4EEV8_Pos (28UL) /*!< PER4EEV8 (Bit 28) */
+#define HRPWM_COM_BMTRGR0_PER4EEV8_Msk (0x10000000UL) /*!< PER4EEV8 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_PER0EEV7_Pos (27UL) /*!< PER0EEV7 (Bit 27) */
+#define HRPWM_COM_BMTRGR0_PER0EEV7_Msk (0x8000000UL) /*!< PER0EEV7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPA5_Pos (26UL) /*!< CMPA5 (Bit 26) */
+#define HRPWM_COM_BMTRGR0_CMPA5_Msk (0x4000000UL) /*!< CMPA5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP5_Pos (25UL) /*!< REP5 (Bit 25) */
+#define HRPWM_COM_BMTRGR0_REP5_Msk (0x2000000UL) /*!< REP5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_RST5_Pos (24UL) /*!< RST5 (Bit 24) */
+#define HRPWM_COM_BMTRGR0_RST5_Msk (0x1000000UL) /*!< RST5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPB4_Pos (23UL) /*!< CMPB4 (Bit 23) */
+#define HRPWM_COM_BMTRGR0_CMPB4_Msk (0x800000UL) /*!< CMPB4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPA4_Pos (22UL) /*!< CMPA4 (Bit 22) */
+#define HRPWM_COM_BMTRGR0_CMPA4_Msk (0x400000UL) /*!< CMPA4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP4_Pos (21UL) /*!< REP4 (Bit 21) */
+#define HRPWM_COM_BMTRGR0_REP4_Msk (0x200000UL) /*!< REP4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPB3_Pos (20UL) /*!< CMPB3 (Bit 20) */
+#define HRPWM_COM_BMTRGR0_CMPB3_Msk (0x100000UL) /*!< CMPB3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP3_Pos (19UL) /*!< REP3 (Bit 19) */
+#define HRPWM_COM_BMTRGR0_REP3_Msk (0x80000UL) /*!< REP3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_RST3_Pos (18UL) /*!< RST3 (Bit 18) */
+#define HRPWM_COM_BMTRGR0_RST3_Msk (0x40000UL) /*!< RST3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPA2_Pos (17UL) /*!< CMPA2 (Bit 17) */
+#define HRPWM_COM_BMTRGR0_CMPA2_Msk (0x20000UL) /*!< CMPA2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP2_Pos (16UL) /*!< REP2 (Bit 16) */
+#define HRPWM_COM_BMTRGR0_REP2_Msk (0x10000UL) /*!< REP2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_RST2_Pos (15UL) /*!< RST2 (Bit 15) */
+#define HRPWM_COM_BMTRGR0_RST2_Msk (0x8000UL) /*!< RST2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPB1_Pos (14UL) /*!< CMPB1 (Bit 14) */
+#define HRPWM_COM_BMTRGR0_CMPB1_Msk (0x4000UL) /*!< CMPB1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPA1_Pos (13UL) /*!< CMPA1 (Bit 13) */
+#define HRPWM_COM_BMTRGR0_CMPA1_Msk (0x2000UL) /*!< CMPA1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP1_Pos (12UL) /*!< REP1 (Bit 12) */
+#define HRPWM_COM_BMTRGR0_REP1_Msk (0x1000UL) /*!< REP1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_RST1_Pos (11UL) /*!< RST1 (Bit 11) */
+#define HRPWM_COM_BMTRGR0_RST1_Msk (0x800UL) /*!< RST1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPB0_Pos (10UL) /*!< CMPB0 (Bit 10) */
+#define HRPWM_COM_BMTRGR0_CMPB0_Msk (0x400UL) /*!< CMPB0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPA0_Pos (9UL) /*!< CMPA0 (Bit 9) */
+#define HRPWM_COM_BMTRGR0_CMPA0_Msk (0x200UL) /*!< CMPA0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP0_Pos (8UL) /*!< REP0 (Bit 8) */
+#define HRPWM_COM_BMTRGR0_REP0_Msk (0x100UL) /*!< REP0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_RST0_Pos (7UL) /*!< RST0 (Bit 7) */
+#define HRPWM_COM_BMTRGR0_RST0_Msk (0x80UL) /*!< RST0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MCMPD_Pos (6UL) /*!< MCMPD (Bit 6) */
+#define HRPWM_COM_BMTRGR0_MCMPD_Msk (0x40UL) /*!< MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MCMPC_Pos (5UL) /*!< MCMPC (Bit 5) */
+#define HRPWM_COM_BMTRGR0_MCMPC_Msk (0x20UL) /*!< MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MCMPB_Pos (4UL) /*!< MCMPB (Bit 4) */
+#define HRPWM_COM_BMTRGR0_MCMPB_Msk (0x10UL) /*!< MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MCMPA_Pos (3UL) /*!< MCMPA (Bit 3) */
+#define HRPWM_COM_BMTRGR0_MCMPA_Msk (0x8UL) /*!< MCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MREP_Pos (2UL) /*!< MREP (Bit 2) */
+#define HRPWM_COM_BMTRGR0_MREP_Msk (0x4UL) /*!< MREP (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MRST_Pos (1UL) /*!< MRST (Bit 1) */
+#define HRPWM_COM_BMTRGR0_MRST_Msk (0x2UL) /*!< MRST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_SW_Pos (0UL) /*!< SW (Bit 0) */
+#define HRPWM_COM_BMTRGR0_SW_Msk (0x1UL) /*!< SW (Bitfield-Mask: 0x01) */
+/* ======================================================== BMTRGR1 ======================================================== */
+#define HRPWM_COM_BMTRGR1_CMPB7_Pos (7UL) /*!< CMPB7 (Bit 7) */
+#define HRPWM_COM_BMTRGR1_CMPB7_Msk (0x80UL) /*!< CMPB7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_CMPA7_Pos (6UL) /*!< CMPA7 (Bit 6) */
+#define HRPWM_COM_BMTRGR1_CMPA7_Msk (0x40UL) /*!< CMPA7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_REP7_Pos (5UL) /*!< REP7 (Bit 5) */
+#define HRPWM_COM_BMTRGR1_REP7_Msk (0x20UL) /*!< REP7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_RST7_Pos (4UL) /*!< RST7 (Bit 4) */
+#define HRPWM_COM_BMTRGR1_RST7_Msk (0x10UL) /*!< RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_CMPB6_Pos (3UL) /*!< CMPB6 (Bit 3) */
+#define HRPWM_COM_BMTRGR1_CMPB6_Msk (0x8UL) /*!< CMPB6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_CMPA6_Pos (2UL) /*!< CMPA6 (Bit 2) */
+#define HRPWM_COM_BMTRGR1_CMPA6_Msk (0x4UL) /*!< CMPA6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_REP6_Pos (1UL) /*!< REP6 (Bit 1) */
+#define HRPWM_COM_BMTRGR1_REP6_Msk (0x2UL) /*!< REP6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_RST6_Pos (0UL) /*!< RST6 (Bit 0) */
+#define HRPWM_COM_BMTRGR1_RST6_Msk (0x1UL) /*!< RST6 (Bitfield-Mask: 0x01) */
+/* ========================================================= BMPER ========================================================= */
+#define HRPWM_COM_BMPER_BMPER_Pos (0UL) /*!< BMPER (Bit 0) */
+#define HRPWM_COM_BMPER_BMPER_Msk (0xffffUL) /*!< BMPER (Bitfield-Mask: 0xffff) */
+/* ======================================================== BMCMPR ========================================================= */
+#define HRPWM_COM_BMCMPR_BMCMP_Pos (0UL) /*!< BMCMP (Bit 0) */
+#define HRPWM_COM_BMCMPR_BMCMP_Msk (0xffffUL) /*!< BMCMP (Bitfield-Mask: 0xffff) */
+/* ======================================================== BDMUPR ========================================================= */
+#define HRPWM_COM_BDMUPR_MCMPDR_Pos (10UL) /*!< MCMPDR (Bit 10) */
+#define HRPWM_COM_BDMUPR_MCMPDR_Msk (0x400UL) /*!< MCMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCMPCR_Pos (9UL) /*!< MCMPCR (Bit 9) */
+#define HRPWM_COM_BDMUPR_MCMPCR_Msk (0x200UL) /*!< MCMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCMPBR_Pos (8UL) /*!< MCMPBR (Bit 8) */
+#define HRPWM_COM_BDMUPR_MCMPBR_Msk (0x100UL) /*!< MCMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCMPAR_Pos (7UL) /*!< MCMPAR (Bit 7) */
+#define HRPWM_COM_BDMUPR_MCMPAR_Msk (0x80UL) /*!< MCMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MREP_Pos (6UL) /*!< MREP (Bit 6) */
+#define HRPWM_COM_BDMUPR_MREP_Msk (0x40UL) /*!< MREP (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MPER_Pos (5UL) /*!< MPER (Bit 5) */
+#define HRPWM_COM_BDMUPR_MPER_Msk (0x20UL) /*!< MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCNTR_Pos (4UL) /*!< MCNTR (Bit 4) */
+#define HRPWM_COM_BDMUPR_MCNTR_Msk (0x10UL) /*!< MCNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MDIER_Pos (3UL) /*!< MDIER (Bit 3) */
+#define HRPWM_COM_BDMUPR_MDIER_Msk (0x8UL) /*!< MDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MISR_Pos (2UL) /*!< MISR (Bit 2) */
+#define HRPWM_COM_BDMUPR_MISR_Msk (0x4UL) /*!< MISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCR1_Pos (1UL) /*!< MCR1 (Bit 1) */
+#define HRPWM_COM_BDMUPR_MCR1_Msk (0x2UL) /*!< MCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCR0_Pos (0UL) /*!< MCR0 (Bit 0) */
+#define HRPWM_COM_BDMUPR_MCR0_Msk (0x1UL) /*!< MCR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR0 ========================================================= */
+#define HRPWM_COM_BDUPR0_FLT0R_Pos (29UL) /*!< FLT0R (Bit 29) */
+#define HRPWM_COM_BDUPR0_FLT0R_Msk (0x20000000UL) /*!< FLT0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_OUT0R_Pos (28UL) /*!< OUT0R (Bit 28) */
+#define HRPWM_COM_BDUPR0_OUT0R_Msk (0x10000000UL) /*!< OUT0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPB0CER_Pos (27UL) /*!< CAPB0CER (Bit 27) */
+#define HRPWM_COM_BDUPR0_CAPB0CER_Msk (0x8000000UL) /*!< CAPB0CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPB0CR_Pos (26UL) /*!< CAPB0CR (Bit 26) */
+#define HRPWM_COM_BDUPR0_CAPB0CR_Msk (0x4000000UL) /*!< CAPB0CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPA0CER_Pos (25UL) /*!< CAPA0CER (Bit 25) */
+#define HRPWM_COM_BDUPR0_CAPA0CER_Msk (0x2000000UL) /*!< CAPA0CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPA0CR_Pos (24UL) /*!< CAPA0CR (Bit 24) */
+#define HRPWM_COM_BDUPR0_CAPA0CR_Msk (0x1000000UL) /*!< CAPA0CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CHP0R_Pos (23UL) /*!< CHP0R (Bit 23) */
+#define HRPWM_COM_BDUPR0_CHP0R_Msk (0x800000UL) /*!< CHP0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_RST0ER_Pos (22UL) /*!< RST0ER (Bit 22) */
+#define HRPWM_COM_BDUPR0_RST0ER_Msk (0x400000UL) /*!< RST0ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_RST0R_Pos (21UL) /*!< RST0R (Bit 21) */
+#define HRPWM_COM_BDUPR0_RST0R_Msk (0x200000UL) /*!< RST0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_EEF0R2_Pos (20UL) /*!< EEF0R2 (Bit 20) */
+#define HRPWM_COM_BDUPR0_EEF0R2_Msk (0x100000UL) /*!< EEF0R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_EEF0R1_Pos (19UL) /*!< EEF0R1 (Bit 19) */
+#define HRPWM_COM_BDUPR0_EEF0R1_Msk (0x80000UL) /*!< EEF0R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_EEF0R0_Pos (18UL) /*!< EEF0R0 (Bit 18) */
+#define HRPWM_COM_BDUPR0_EEF0R0_Msk (0x40000UL) /*!< EEF0R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CLR0BR_Pos (17UL) /*!< CLR0BR (Bit 17) */
+#define HRPWM_COM_BDUPR0_CLR0BR_Msk (0x20000UL) /*!< CLR0BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_SET0BR_Pos (16UL) /*!< SET0BR (Bit 16) */
+#define HRPWM_COM_BDUPR0_SET0BR_Msk (0x10000UL) /*!< SET0BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CLR0AR_Pos (15UL) /*!< CLR0AR (Bit 15) */
+#define HRPWM_COM_BDUPR0_CLR0AR_Msk (0x8000UL) /*!< CLR0AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_SET0AR_Pos (14UL) /*!< SET0AR (Bit 14) */
+#define HRPWM_COM_BDUPR0_SET0AR_Msk (0x4000UL) /*!< SET0AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_DT0R_Pos (13UL) /*!< DT0R (Bit 13) */
+#define HRPWM_COM_BDUPR0_DT0R_Msk (0x2000UL) /*!< DT0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPB0R_Pos (12UL) /*!< CAPB0R (Bit 12) */
+#define HRPWM_COM_BDUPR0_CAPB0R_Msk (0x1000UL) /*!< CAPB0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPA0R_Pos (11UL) /*!< CAPA0R (Bit 11) */
+#define HRPWM_COM_BDUPR0_CAPA0R_Msk (0x800UL) /*!< CAPA0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CMPD0R_Pos (10UL) /*!< CMPD0R (Bit 10) */
+#define HRPWM_COM_BDUPR0_CMPD0R_Msk (0x400UL) /*!< CMPD0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CMPC0R_Pos (9UL) /*!< CMPC0R (Bit 9) */
+#define HRPWM_COM_BDUPR0_CMPC0R_Msk (0x200UL) /*!< CMPC0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CMPB0R_Pos (8UL) /*!< CMPB0R (Bit 8) */
+#define HRPWM_COM_BDUPR0_CMPB0R_Msk (0x100UL) /*!< CMPB0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CMPA0R_Pos (7UL) /*!< CMPA0R (Bit 7) */
+#define HRPWM_COM_BDUPR0_CMPA0R_Msk (0x80UL) /*!< CMPA0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_REP0R_Pos (6UL) /*!< REP0R (Bit 6) */
+#define HRPWM_COM_BDUPR0_REP0R_Msk (0x40UL) /*!< REP0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_PER0R_Pos (5UL) /*!< PER0R (Bit 5) */
+#define HRPWM_COM_BDUPR0_PER0R_Msk (0x20UL) /*!< PER0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CNT0R_Pos (4UL) /*!< CNT0R (Bit 4) */
+#define HRPWM_COM_BDUPR0_CNT0R_Msk (0x10UL) /*!< CNT0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_PWM0DIER_Pos (3UL) /*!< PWM0DIER (Bit 3) */
+#define HRPWM_COM_BDUPR0_PWM0DIER_Msk (0x8UL) /*!< PWM0DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_PWM0ISR_Pos (2UL) /*!< PWM0ISR (Bit 2) */
+#define HRPWM_COM_BDUPR0_PWM0ISR_Msk (0x4UL) /*!< PWM0ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_PWM0CR1_Pos (1UL) /*!< PWM0CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR0_PWM0CR1_Msk (0x2UL) /*!< PWM0CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_PWM0CR0_Pos (0UL) /*!< PWM0CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR0_PWM0CR0_Msk (0x1UL) /*!< PWM0CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR1 ========================================================= */
+#define HRPWM_COM_BDUPR1_FLT1R_Pos (29UL) /*!< FLT1R (Bit 29) */
+#define HRPWM_COM_BDUPR1_FLT1R_Msk (0x20000000UL) /*!< FLT1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_OUT1R_Pos (28UL) /*!< OUT1R (Bit 28) */
+#define HRPWM_COM_BDUPR1_OUT1R_Msk (0x10000000UL) /*!< OUT1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPB1CER_Pos (27UL) /*!< CAPB1CER (Bit 27) */
+#define HRPWM_COM_BDUPR1_CAPB1CER_Msk (0x8000000UL) /*!< CAPB1CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPB1CR_Pos (26UL) /*!< CAPB1CR (Bit 26) */
+#define HRPWM_COM_BDUPR1_CAPB1CR_Msk (0x4000000UL) /*!< CAPB1CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPA1CER_Pos (25UL) /*!< CAPA1CER (Bit 25) */
+#define HRPWM_COM_BDUPR1_CAPA1CER_Msk (0x2000000UL) /*!< CAPA1CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPA1CR_Pos (24UL) /*!< CAPA1CR (Bit 24) */
+#define HRPWM_COM_BDUPR1_CAPA1CR_Msk (0x1000000UL) /*!< CAPA1CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CHP1R_Pos (23UL) /*!< CHP1R (Bit 23) */
+#define HRPWM_COM_BDUPR1_CHP1R_Msk (0x800000UL) /*!< CHP1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_RST1ER_Pos (22UL) /*!< RST1ER (Bit 22) */
+#define HRPWM_COM_BDUPR1_RST1ER_Msk (0x400000UL) /*!< RST1ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_RST1R_Pos (21UL) /*!< RST1R (Bit 21) */
+#define HRPWM_COM_BDUPR1_RST1R_Msk (0x200000UL) /*!< RST1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_EEF1R2_Pos (20UL) /*!< EEF1R2 (Bit 20) */
+#define HRPWM_COM_BDUPR1_EEF1R2_Msk (0x100000UL) /*!< EEF1R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_EEF1R1_Pos (19UL) /*!< EEF1R1 (Bit 19) */
+#define HRPWM_COM_BDUPR1_EEF1R1_Msk (0x80000UL) /*!< EEF1R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_EEF1R0_Pos (18UL) /*!< EEF1R0 (Bit 18) */
+#define HRPWM_COM_BDUPR1_EEF1R0_Msk (0x40000UL) /*!< EEF1R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CLR1BR_Pos (17UL) /*!< CLR1BR (Bit 17) */
+#define HRPWM_COM_BDUPR1_CLR1BR_Msk (0x20000UL) /*!< CLR1BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_SET1BR_Pos (16UL) /*!< SET1BR (Bit 16) */
+#define HRPWM_COM_BDUPR1_SET1BR_Msk (0x10000UL) /*!< SET1BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CLR1AR_Pos (15UL) /*!< CLR1AR (Bit 15) */
+#define HRPWM_COM_BDUPR1_CLR1AR_Msk (0x8000UL) /*!< CLR1AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_SET1AR_Pos (14UL) /*!< SET1AR (Bit 14) */
+#define HRPWM_COM_BDUPR1_SET1AR_Msk (0x4000UL) /*!< SET1AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_DT1R_Pos (13UL) /*!< DT1R (Bit 13) */
+#define HRPWM_COM_BDUPR1_DT1R_Msk (0x2000UL) /*!< DT1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPB1R_Pos (12UL) /*!< CAPB1R (Bit 12) */
+#define HRPWM_COM_BDUPR1_CAPB1R_Msk (0x1000UL) /*!< CAPB1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPA1R_Pos (11UL) /*!< CAPA1R (Bit 11) */
+#define HRPWM_COM_BDUPR1_CAPA1R_Msk (0x800UL) /*!< CAPA1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CMPD1R_Pos (10UL) /*!< CMPD1R (Bit 10) */
+#define HRPWM_COM_BDUPR1_CMPD1R_Msk (0x400UL) /*!< CMPD1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CMPC1R_Pos (9UL) /*!< CMPC1R (Bit 9) */
+#define HRPWM_COM_BDUPR1_CMPC1R_Msk (0x200UL) /*!< CMPC1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CMPB1R_Pos (8UL) /*!< CMPB1R (Bit 8) */
+#define HRPWM_COM_BDUPR1_CMPB1R_Msk (0x100UL) /*!< CMPB1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CMPA1R_Pos (7UL) /*!< CMPA1R (Bit 7) */
+#define HRPWM_COM_BDUPR1_CMPA1R_Msk (0x80UL) /*!< CMPA1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_REP1R_Pos (6UL) /*!< REP1R (Bit 6) */
+#define HRPWM_COM_BDUPR1_REP1R_Msk (0x40UL) /*!< REP1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_PER1R_Pos (5UL) /*!< PER1R (Bit 5) */
+#define HRPWM_COM_BDUPR1_PER1R_Msk (0x20UL) /*!< PER1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CNT1R_Pos (4UL) /*!< CNT1R (Bit 4) */
+#define HRPWM_COM_BDUPR1_CNT1R_Msk (0x10UL) /*!< CNT1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_PWM1DIER_Pos (3UL) /*!< PWM1DIER (Bit 3) */
+#define HRPWM_COM_BDUPR1_PWM1DIER_Msk (0x8UL) /*!< PWM1DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_PWM1ISR_Pos (2UL) /*!< PWM1ISR (Bit 2) */
+#define HRPWM_COM_BDUPR1_PWM1ISR_Msk (0x4UL) /*!< PWM1ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_PWM1CR1_Pos (1UL) /*!< PWM1CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR1_PWM1CR1_Msk (0x2UL) /*!< PWM1CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_PWM1CR0_Pos (0UL) /*!< PWM1CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR1_PWM1CR0_Msk (0x1UL) /*!< PWM1CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR2 ========================================================= */
+#define HRPWM_COM_BDUPR2_FLT2R_Pos (29UL) /*!< FLT2R (Bit 29) */
+#define HRPWM_COM_BDUPR2_FLT2R_Msk (0x20000000UL) /*!< FLT2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_OUT2R_Pos (28UL) /*!< OUT2R (Bit 28) */
+#define HRPWM_COM_BDUPR2_OUT2R_Msk (0x10000000UL) /*!< OUT2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPB2CER_Pos (27UL) /*!< CAPB2CER (Bit 27) */
+#define HRPWM_COM_BDUPR2_CAPB2CER_Msk (0x8000000UL) /*!< CAPB2CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPB2CR_Pos (26UL) /*!< CAPB2CR (Bit 26) */
+#define HRPWM_COM_BDUPR2_CAPB2CR_Msk (0x4000000UL) /*!< CAPB2CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPA2CER_Pos (25UL) /*!< CAPA2CER (Bit 25) */
+#define HRPWM_COM_BDUPR2_CAPA2CER_Msk (0x2000000UL) /*!< CAPA2CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPA2CR_Pos (24UL) /*!< CAPA2CR (Bit 24) */
+#define HRPWM_COM_BDUPR2_CAPA2CR_Msk (0x1000000UL) /*!< CAPA2CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CHP2R_Pos (23UL) /*!< CHP2R (Bit 23) */
+#define HRPWM_COM_BDUPR2_CHP2R_Msk (0x800000UL) /*!< CHP2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_RST2ER_Pos (22UL) /*!< RST2ER (Bit 22) */
+#define HRPWM_COM_BDUPR2_RST2ER_Msk (0x400000UL) /*!< RST2ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_RST2R_Pos (21UL) /*!< RST2R (Bit 21) */
+#define HRPWM_COM_BDUPR2_RST2R_Msk (0x200000UL) /*!< RST2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_EEF2R2_Pos (20UL) /*!< EEF2R2 (Bit 20) */
+#define HRPWM_COM_BDUPR2_EEF2R2_Msk (0x100000UL) /*!< EEF2R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_EEF2R1_Pos (19UL) /*!< EEF2R1 (Bit 19) */
+#define HRPWM_COM_BDUPR2_EEF2R1_Msk (0x80000UL) /*!< EEF2R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_EEF2R0_Pos (18UL) /*!< EEF2R0 (Bit 18) */
+#define HRPWM_COM_BDUPR2_EEF2R0_Msk (0x40000UL) /*!< EEF2R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CLR2BR_Pos (17UL) /*!< CLR2BR (Bit 17) */
+#define HRPWM_COM_BDUPR2_CLR2BR_Msk (0x20000UL) /*!< CLR2BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_SET2BR_Pos (16UL) /*!< SET2BR (Bit 16) */
+#define HRPWM_COM_BDUPR2_SET2BR_Msk (0x10000UL) /*!< SET2BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CLR2AR_Pos (15UL) /*!< CLR2AR (Bit 15) */
+#define HRPWM_COM_BDUPR2_CLR2AR_Msk (0x8000UL) /*!< CLR2AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_SET2AR_Pos (14UL) /*!< SET2AR (Bit 14) */
+#define HRPWM_COM_BDUPR2_SET2AR_Msk (0x4000UL) /*!< SET2AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_DT2R_Pos (13UL) /*!< DT2R (Bit 13) */
+#define HRPWM_COM_BDUPR2_DT2R_Msk (0x2000UL) /*!< DT2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPB2R_Pos (12UL) /*!< CAPB2R (Bit 12) */
+#define HRPWM_COM_BDUPR2_CAPB2R_Msk (0x1000UL) /*!< CAPB2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPA2R_Pos (11UL) /*!< CAPA2R (Bit 11) */
+#define HRPWM_COM_BDUPR2_CAPA2R_Msk (0x800UL) /*!< CAPA2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CMPD2R_Pos (10UL) /*!< CMPD2R (Bit 10) */
+#define HRPWM_COM_BDUPR2_CMPD2R_Msk (0x400UL) /*!< CMPD2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CMPC2R_Pos (9UL) /*!< CMPC2R (Bit 9) */
+#define HRPWM_COM_BDUPR2_CMPC2R_Msk (0x200UL) /*!< CMPC2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CMPB2R_Pos (8UL) /*!< CMPB2R (Bit 8) */
+#define HRPWM_COM_BDUPR2_CMPB2R_Msk (0x100UL) /*!< CMPB2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CMPA2R_Pos (7UL) /*!< CMPA2R (Bit 7) */
+#define HRPWM_COM_BDUPR2_CMPA2R_Msk (0x80UL) /*!< CMPA2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_REP2R_Pos (6UL) /*!< REP2R (Bit 6) */
+#define HRPWM_COM_BDUPR2_REP2R_Msk (0x40UL) /*!< REP2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_PER2R_Pos (5UL) /*!< PER2R (Bit 5) */
+#define HRPWM_COM_BDUPR2_PER2R_Msk (0x20UL) /*!< PER2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CNT2R_Pos (4UL) /*!< CNT2R (Bit 4) */
+#define HRPWM_COM_BDUPR2_CNT2R_Msk (0x10UL) /*!< CNT2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_PWM2DIER_Pos (3UL) /*!< PWM2DIER (Bit 3) */
+#define HRPWM_COM_BDUPR2_PWM2DIER_Msk (0x8UL) /*!< PWM2DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_PWM2ISR_Pos (2UL) /*!< PWM2ISR (Bit 2) */
+#define HRPWM_COM_BDUPR2_PWM2ISR_Msk (0x4UL) /*!< PWM2ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_PWM2CR1_Pos (1UL) /*!< PWM2CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR2_PWM2CR1_Msk (0x2UL) /*!< PWM2CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_PWM2CR0_Pos (0UL) /*!< PWM2CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR2_PWM2CR0_Msk (0x1UL) /*!< PWM2CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR3 ========================================================= */
+#define HRPWM_COM_BDUPR3_FLT3R_Pos (29UL) /*!< FLT3R (Bit 29) */
+#define HRPWM_COM_BDUPR3_FLT3R_Msk (0x20000000UL) /*!< FLT3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_OUT3R_Pos (28UL) /*!< OUT3R (Bit 28) */
+#define HRPWM_COM_BDUPR3_OUT3R_Msk (0x10000000UL) /*!< OUT3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPB3CER_Pos (27UL) /*!< CAPB3CER (Bit 27) */
+#define HRPWM_COM_BDUPR3_CAPB3CER_Msk (0x8000000UL) /*!< CAPB3CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPB3CR_Pos (26UL) /*!< CAPB3CR (Bit 26) */
+#define HRPWM_COM_BDUPR3_CAPB3CR_Msk (0x4000000UL) /*!< CAPB3CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPA3CER_Pos (25UL) /*!< CAPA3CER (Bit 25) */
+#define HRPWM_COM_BDUPR3_CAPA3CER_Msk (0x2000000UL) /*!< CAPA3CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPA3CR_Pos (24UL) /*!< CAPA3CR (Bit 24) */
+#define HRPWM_COM_BDUPR3_CAPA3CR_Msk (0x1000000UL) /*!< CAPA3CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CHP3R_Pos (23UL) /*!< CHP3R (Bit 23) */
+#define HRPWM_COM_BDUPR3_CHP3R_Msk (0x800000UL) /*!< CHP3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_RST3ER_Pos (22UL) /*!< RST3ER (Bit 22) */
+#define HRPWM_COM_BDUPR3_RST3ER_Msk (0x400000UL) /*!< RST3ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_RST3R_Pos (21UL) /*!< RST3R (Bit 21) */
+#define HRPWM_COM_BDUPR3_RST3R_Msk (0x200000UL) /*!< RST3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_EEF3R2_Pos (20UL) /*!< EEF3R2 (Bit 20) */
+#define HRPWM_COM_BDUPR3_EEF3R2_Msk (0x100000UL) /*!< EEF3R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_EEF3R1_Pos (19UL) /*!< EEF3R1 (Bit 19) */
+#define HRPWM_COM_BDUPR3_EEF3R1_Msk (0x80000UL) /*!< EEF3R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_EEF3R0_Pos (18UL) /*!< EEF3R0 (Bit 18) */
+#define HRPWM_COM_BDUPR3_EEF3R0_Msk (0x40000UL) /*!< EEF3R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CLR3BR_Pos (17UL) /*!< CLR3BR (Bit 17) */
+#define HRPWM_COM_BDUPR3_CLR3BR_Msk (0x20000UL) /*!< CLR3BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_SET3BR_Pos (16UL) /*!< SET3BR (Bit 16) */
+#define HRPWM_COM_BDUPR3_SET3BR_Msk (0x10000UL) /*!< SET3BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CLR3AR_Pos (15UL) /*!< CLR3AR (Bit 15) */
+#define HRPWM_COM_BDUPR3_CLR3AR_Msk (0x8000UL) /*!< CLR3AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_SET3AR_Pos (14UL) /*!< SET3AR (Bit 14) */
+#define HRPWM_COM_BDUPR3_SET3AR_Msk (0x4000UL) /*!< SET3AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_DT3R_Pos (13UL) /*!< DT3R (Bit 13) */
+#define HRPWM_COM_BDUPR3_DT3R_Msk (0x2000UL) /*!< DT3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPB3R_Pos (12UL) /*!< CAPB3R (Bit 12) */
+#define HRPWM_COM_BDUPR3_CAPB3R_Msk (0x1000UL) /*!< CAPB3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPA3R_Pos (11UL) /*!< CAPA3R (Bit 11) */
+#define HRPWM_COM_BDUPR3_CAPA3R_Msk (0x800UL) /*!< CAPA3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CMPD3R_Pos (10UL) /*!< CMPD3R (Bit 10) */
+#define HRPWM_COM_BDUPR3_CMPD3R_Msk (0x400UL) /*!< CMPD3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CMPC3R_Pos (9UL) /*!< CMPC3R (Bit 9) */
+#define HRPWM_COM_BDUPR3_CMPC3R_Msk (0x200UL) /*!< CMPC3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CMPB3R_Pos (8UL) /*!< CMPB3R (Bit 8) */
+#define HRPWM_COM_BDUPR3_CMPB3R_Msk (0x100UL) /*!< CMPB3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CMPA3R_Pos (7UL) /*!< CMPA3R (Bit 7) */
+#define HRPWM_COM_BDUPR3_CMPA3R_Msk (0x80UL) /*!< CMPA3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_REP3R_Pos (6UL) /*!< REP3R (Bit 6) */
+#define HRPWM_COM_BDUPR3_REP3R_Msk (0x40UL) /*!< REP3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_PER3R_Pos (5UL) /*!< PER3R (Bit 5) */
+#define HRPWM_COM_BDUPR3_PER3R_Msk (0x20UL) /*!< PER3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CNT3R_Pos (4UL) /*!< CNT3R (Bit 4) */
+#define HRPWM_COM_BDUPR3_CNT3R_Msk (0x10UL) /*!< CNT3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_PWM3DIER_Pos (3UL) /*!< PWM3DIER (Bit 3) */
+#define HRPWM_COM_BDUPR3_PWM3DIER_Msk (0x8UL) /*!< PWM3DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_PWM3ISR_Pos (2UL) /*!< PWM3ISR (Bit 2) */
+#define HRPWM_COM_BDUPR3_PWM3ISR_Msk (0x4UL) /*!< PWM3ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_PWM3CR1_Pos (1UL) /*!< PWM3CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR3_PWM3CR1_Msk (0x2UL) /*!< PWM3CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_PWM3CR0_Pos (0UL) /*!< PWM3CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR3_PWM3CR0_Msk (0x1UL) /*!< PWM3CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR4 ========================================================= */
+#define HRPWM_COM_BDUPR4_FLT4R_Pos (29UL) /*!< FLT4R (Bit 29) */
+#define HRPWM_COM_BDUPR4_FLT4R_Msk (0x20000000UL) /*!< FLT4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_OUT4R_Pos (28UL) /*!< OUT4R (Bit 28) */
+#define HRPWM_COM_BDUPR4_OUT4R_Msk (0x10000000UL) /*!< OUT4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPB4CER_Pos (27UL) /*!< CAPB4CER (Bit 27) */
+#define HRPWM_COM_BDUPR4_CAPB4CER_Msk (0x8000000UL) /*!< CAPB4CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPB4CR_Pos (26UL) /*!< CAPB4CR (Bit 26) */
+#define HRPWM_COM_BDUPR4_CAPB4CR_Msk (0x4000000UL) /*!< CAPB4CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPA4CER_Pos (25UL) /*!< CAPA4CER (Bit 25) */
+#define HRPWM_COM_BDUPR4_CAPA4CER_Msk (0x2000000UL) /*!< CAPA4CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPA4CR_Pos (24UL) /*!< CAPA4CR (Bit 24) */
+#define HRPWM_COM_BDUPR4_CAPA4CR_Msk (0x1000000UL) /*!< CAPA4CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CHP4R_Pos (23UL) /*!< CHP4R (Bit 23) */
+#define HRPWM_COM_BDUPR4_CHP4R_Msk (0x800000UL) /*!< CHP4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_RST4ER_Pos (22UL) /*!< RST4ER (Bit 22) */
+#define HRPWM_COM_BDUPR4_RST4ER_Msk (0x400000UL) /*!< RST4ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_RST4R_Pos (21UL) /*!< RST4R (Bit 21) */
+#define HRPWM_COM_BDUPR4_RST4R_Msk (0x200000UL) /*!< RST4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_EEF4R2_Pos (20UL) /*!< EEF4R2 (Bit 20) */
+#define HRPWM_COM_BDUPR4_EEF4R2_Msk (0x100000UL) /*!< EEF4R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_EEF4R1_Pos (19UL) /*!< EEF4R1 (Bit 19) */
+#define HRPWM_COM_BDUPR4_EEF4R1_Msk (0x80000UL) /*!< EEF4R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_EEF4R0_Pos (18UL) /*!< EEF4R0 (Bit 18) */
+#define HRPWM_COM_BDUPR4_EEF4R0_Msk (0x40000UL) /*!< EEF4R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CLR4BR_Pos (17UL) /*!< CLR4BR (Bit 17) */
+#define HRPWM_COM_BDUPR4_CLR4BR_Msk (0x20000UL) /*!< CLR4BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_SET4BR_Pos (16UL) /*!< SET4BR (Bit 16) */
+#define HRPWM_COM_BDUPR4_SET4BR_Msk (0x10000UL) /*!< SET4BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CLR4AR_Pos (15UL) /*!< CLR4AR (Bit 15) */
+#define HRPWM_COM_BDUPR4_CLR4AR_Msk (0x8000UL) /*!< CLR4AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_SET4AR_Pos (14UL) /*!< SET4AR (Bit 14) */
+#define HRPWM_COM_BDUPR4_SET4AR_Msk (0x4000UL) /*!< SET4AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_DT4R_Pos (13UL) /*!< DT4R (Bit 13) */
+#define HRPWM_COM_BDUPR4_DT4R_Msk (0x2000UL) /*!< DT4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPB4R_Pos (12UL) /*!< CAPB4R (Bit 12) */
+#define HRPWM_COM_BDUPR4_CAPB4R_Msk (0x1000UL) /*!< CAPB4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPA4R_Pos (11UL) /*!< CAPA4R (Bit 11) */
+#define HRPWM_COM_BDUPR4_CAPA4R_Msk (0x800UL) /*!< CAPA4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CMPD4R_Pos (10UL) /*!< CMPD4R (Bit 10) */
+#define HRPWM_COM_BDUPR4_CMPD4R_Msk (0x400UL) /*!< CMPD4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CMPC4R_Pos (9UL) /*!< CMPC4R (Bit 9) */
+#define HRPWM_COM_BDUPR4_CMPC4R_Msk (0x200UL) /*!< CMPC4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CMPB4R_Pos (8UL) /*!< CMPB4R (Bit 8) */
+#define HRPWM_COM_BDUPR4_CMPB4R_Msk (0x100UL) /*!< CMPB4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CMPA4R_Pos (7UL) /*!< CMPA4R (Bit 7) */
+#define HRPWM_COM_BDUPR4_CMPA4R_Msk (0x80UL) /*!< CMPA4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_REP4R_Pos (6UL) /*!< REP4R (Bit 6) */
+#define HRPWM_COM_BDUPR4_REP4R_Msk (0x40UL) /*!< REP4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_PER4R_Pos (5UL) /*!< PER4R (Bit 5) */
+#define HRPWM_COM_BDUPR4_PER4R_Msk (0x20UL) /*!< PER4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CNT4R_Pos (4UL) /*!< CNT4R (Bit 4) */
+#define HRPWM_COM_BDUPR4_CNT4R_Msk (0x10UL) /*!< CNT4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_PWM4DIER_Pos (3UL) /*!< PWM4DIER (Bit 3) */
+#define HRPWM_COM_BDUPR4_PWM4DIER_Msk (0x8UL) /*!< PWM4DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_PWM4ISR_Pos (2UL) /*!< PWM4ISR (Bit 2) */
+#define HRPWM_COM_BDUPR4_PWM4ISR_Msk (0x4UL) /*!< PWM4ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_PWM4CR1_Pos (1UL) /*!< PWM4CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR4_PWM4CR1_Msk (0x2UL) /*!< PWM4CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_PWM4CR0_Pos (0UL) /*!< PWM4CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR4_PWM4CR0_Msk (0x1UL) /*!< PWM4CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR5 ========================================================= */
+#define HRPWM_COM_BDUPR5_FLT5R_Pos (29UL) /*!< FLT5R (Bit 29) */
+#define HRPWM_COM_BDUPR5_FLT5R_Msk (0x20000000UL) /*!< FLT5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_OUT5R_Pos (28UL) /*!< OUT5R (Bit 28) */
+#define HRPWM_COM_BDUPR5_OUT5R_Msk (0x10000000UL) /*!< OUT5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPB5CER_Pos (27UL) /*!< CAPB5CER (Bit 27) */
+#define HRPWM_COM_BDUPR5_CAPB5CER_Msk (0x8000000UL) /*!< CAPB5CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPB5CR_Pos (26UL) /*!< CAPB5CR (Bit 26) */
+#define HRPWM_COM_BDUPR5_CAPB5CR_Msk (0x4000000UL) /*!< CAPB5CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPA5CER_Pos (25UL) /*!< CAPA5CER (Bit 25) */
+#define HRPWM_COM_BDUPR5_CAPA5CER_Msk (0x2000000UL) /*!< CAPA5CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPA5CR_Pos (24UL) /*!< CAPA5CR (Bit 24) */
+#define HRPWM_COM_BDUPR5_CAPA5CR_Msk (0x1000000UL) /*!< CAPA5CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CHP5R_Pos (23UL) /*!< CHP5R (Bit 23) */
+#define HRPWM_COM_BDUPR5_CHP5R_Msk (0x800000UL) /*!< CHP5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_RST5ER_Pos (22UL) /*!< RST5ER (Bit 22) */
+#define HRPWM_COM_BDUPR5_RST5ER_Msk (0x400000UL) /*!< RST5ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_RST5R_Pos (21UL) /*!< RST5R (Bit 21) */
+#define HRPWM_COM_BDUPR5_RST5R_Msk (0x200000UL) /*!< RST5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_EEF5R2_Pos (20UL) /*!< EEF5R2 (Bit 20) */
+#define HRPWM_COM_BDUPR5_EEF5R2_Msk (0x100000UL) /*!< EEF5R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_EEF5R1_Pos (19UL) /*!< EEF5R1 (Bit 19) */
+#define HRPWM_COM_BDUPR5_EEF5R1_Msk (0x80000UL) /*!< EEF5R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_EEF5R0_Pos (18UL) /*!< EEF5R0 (Bit 18) */
+#define HRPWM_COM_BDUPR5_EEF5R0_Msk (0x40000UL) /*!< EEF5R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CLR5BR_Pos (17UL) /*!< CLR5BR (Bit 17) */
+#define HRPWM_COM_BDUPR5_CLR5BR_Msk (0x20000UL) /*!< CLR5BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_SET5BR_Pos (16UL) /*!< SET5BR (Bit 16) */
+#define HRPWM_COM_BDUPR5_SET5BR_Msk (0x10000UL) /*!< SET5BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CLR5AR_Pos (15UL) /*!< CLR5AR (Bit 15) */
+#define HRPWM_COM_BDUPR5_CLR5AR_Msk (0x8000UL) /*!< CLR5AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_SET5AR_Pos (14UL) /*!< SET5AR (Bit 14) */
+#define HRPWM_COM_BDUPR5_SET5AR_Msk (0x4000UL) /*!< SET5AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_DT5R_Pos (13UL) /*!< DT5R (Bit 13) */
+#define HRPWM_COM_BDUPR5_DT5R_Msk (0x2000UL) /*!< DT5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPB5R_Pos (12UL) /*!< CAPB5R (Bit 12) */
+#define HRPWM_COM_BDUPR5_CAPB5R_Msk (0x1000UL) /*!< CAPB5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPA5R_Pos (11UL) /*!< CAPA5R (Bit 11) */
+#define HRPWM_COM_BDUPR5_CAPA5R_Msk (0x800UL) /*!< CAPA5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CMPD5R_Pos (10UL) /*!< CMPD5R (Bit 10) */
+#define HRPWM_COM_BDUPR5_CMPD5R_Msk (0x400UL) /*!< CMPD5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CMPC5R_Pos (9UL) /*!< CMPC5R (Bit 9) */
+#define HRPWM_COM_BDUPR5_CMPC5R_Msk (0x200UL) /*!< CMPC5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CMPB5R_Pos (8UL) /*!< CMPB5R (Bit 8) */
+#define HRPWM_COM_BDUPR5_CMPB5R_Msk (0x100UL) /*!< CMPB5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CMPA5R_Pos (7UL) /*!< CMPA5R (Bit 7) */
+#define HRPWM_COM_BDUPR5_CMPA5R_Msk (0x80UL) /*!< CMPA5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_REP5R_Pos (6UL) /*!< REP5R (Bit 6) */
+#define HRPWM_COM_BDUPR5_REP5R_Msk (0x40UL) /*!< REP5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_PER5R_Pos (5UL) /*!< PER5R (Bit 5) */
+#define HRPWM_COM_BDUPR5_PER5R_Msk (0x20UL) /*!< PER5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CNT5R_Pos (4UL) /*!< CNT5R (Bit 4) */
+#define HRPWM_COM_BDUPR5_CNT5R_Msk (0x10UL) /*!< CNT5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_PWM5DIER_Pos (3UL) /*!< PWM5DIER (Bit 3) */
+#define HRPWM_COM_BDUPR5_PWM5DIER_Msk (0x8UL) /*!< PWM5DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_PWM5ISR_Pos (2UL) /*!< PWM5ISR (Bit 2) */
+#define HRPWM_COM_BDUPR5_PWM5ISR_Msk (0x4UL) /*!< PWM5ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_PWM5CR1_Pos (1UL) /*!< PWM5CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR5_PWM5CR1_Msk (0x2UL) /*!< PWM5CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_PWM5CR0_Pos (0UL) /*!< PWM5CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR5_PWM5CR0_Msk (0x1UL) /*!< PWM5CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR6 ========================================================= */
+#define HRPWM_COM_BDUPR6_FLT6R_Pos (29UL) /*!< FLT6R (Bit 29) */
+#define HRPWM_COM_BDUPR6_FLT6R_Msk (0x20000000UL) /*!< FLT6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_OUT6R_Pos (28UL) /*!< OUT6R (Bit 28) */
+#define HRPWM_COM_BDUPR6_OUT6R_Msk (0x10000000UL) /*!< OUT6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPB6CER_Pos (27UL) /*!< CAPB6CER (Bit 27) */
+#define HRPWM_COM_BDUPR6_CAPB6CER_Msk (0x8000000UL) /*!< CAPB6CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPB6CR_Pos (26UL) /*!< CAPB6CR (Bit 26) */
+#define HRPWM_COM_BDUPR6_CAPB6CR_Msk (0x4000000UL) /*!< CAPB6CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPA6CER_Pos (25UL) /*!< CAPA6CER (Bit 25) */
+#define HRPWM_COM_BDUPR6_CAPA6CER_Msk (0x2000000UL) /*!< CAPA6CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPA6CR_Pos (24UL) /*!< CAPA6CR (Bit 24) */
+#define HRPWM_COM_BDUPR6_CAPA6CR_Msk (0x1000000UL) /*!< CAPA6CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CHP6R_Pos (23UL) /*!< CHP6R (Bit 23) */
+#define HRPWM_COM_BDUPR6_CHP6R_Msk (0x800000UL) /*!< CHP6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_RST6ER_Pos (22UL) /*!< RST6ER (Bit 22) */
+#define HRPWM_COM_BDUPR6_RST6ER_Msk (0x400000UL) /*!< RST6ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_RST6R_Pos (21UL) /*!< RST6R (Bit 21) */
+#define HRPWM_COM_BDUPR6_RST6R_Msk (0x200000UL) /*!< RST6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_EEF6R2_Pos (20UL) /*!< EEF6R2 (Bit 20) */
+#define HRPWM_COM_BDUPR6_EEF6R2_Msk (0x100000UL) /*!< EEF6R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_EEF6R1_Pos (19UL) /*!< EEF6R1 (Bit 19) */
+#define HRPWM_COM_BDUPR6_EEF6R1_Msk (0x80000UL) /*!< EEF6R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_EEF6R0_Pos (18UL) /*!< EEF6R0 (Bit 18) */
+#define HRPWM_COM_BDUPR6_EEF6R0_Msk (0x40000UL) /*!< EEF6R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CLR6BR_Pos (17UL) /*!< CLR6BR (Bit 17) */
+#define HRPWM_COM_BDUPR6_CLR6BR_Msk (0x20000UL) /*!< CLR6BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_SET6BR_Pos (16UL) /*!< SET6BR (Bit 16) */
+#define HRPWM_COM_BDUPR6_SET6BR_Msk (0x10000UL) /*!< SET6BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CLR6AR_Pos (15UL) /*!< CLR6AR (Bit 15) */
+#define HRPWM_COM_BDUPR6_CLR6AR_Msk (0x8000UL) /*!< CLR6AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_SET6AR_Pos (14UL) /*!< SET6AR (Bit 14) */
+#define HRPWM_COM_BDUPR6_SET6AR_Msk (0x4000UL) /*!< SET6AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_DT6R_Pos (13UL) /*!< DT6R (Bit 13) */
+#define HRPWM_COM_BDUPR6_DT6R_Msk (0x2000UL) /*!< DT6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPB6R_Pos (12UL) /*!< CAPB6R (Bit 12) */
+#define HRPWM_COM_BDUPR6_CAPB6R_Msk (0x1000UL) /*!< CAPB6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPA6R_Pos (11UL) /*!< CAPA6R (Bit 11) */
+#define HRPWM_COM_BDUPR6_CAPA6R_Msk (0x800UL) /*!< CAPA6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CMPD6R_Pos (10UL) /*!< CMPD6R (Bit 10) */
+#define HRPWM_COM_BDUPR6_CMPD6R_Msk (0x400UL) /*!< CMPD6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CMPC6R_Pos (9UL) /*!< CMPC6R (Bit 9) */
+#define HRPWM_COM_BDUPR6_CMPC6R_Msk (0x200UL) /*!< CMPC6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CMPB6R_Pos (8UL) /*!< CMPB6R (Bit 8) */
+#define HRPWM_COM_BDUPR6_CMPB6R_Msk (0x100UL) /*!< CMPB6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CMPA6R_Pos (7UL) /*!< CMPA6R (Bit 7) */
+#define HRPWM_COM_BDUPR6_CMPA6R_Msk (0x80UL) /*!< CMPA6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_REP6R_Pos (6UL) /*!< REP6R (Bit 6) */
+#define HRPWM_COM_BDUPR6_REP6R_Msk (0x40UL) /*!< REP6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_PER6R_Pos (5UL) /*!< PER6R (Bit 5) */
+#define HRPWM_COM_BDUPR6_PER6R_Msk (0x20UL) /*!< PER6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CNT6R_Pos (4UL) /*!< CNT6R (Bit 4) */
+#define HRPWM_COM_BDUPR6_CNT6R_Msk (0x10UL) /*!< CNT6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_PWM6DIER_Pos (3UL) /*!< PWM6DIER (Bit 3) */
+#define HRPWM_COM_BDUPR6_PWM6DIER_Msk (0x8UL) /*!< PWM6DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_PWM6ISR_Pos (2UL) /*!< PWM6ISR (Bit 2) */
+#define HRPWM_COM_BDUPR6_PWM6ISR_Msk (0x4UL) /*!< PWM6ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_PWM6CR1_Pos (1UL) /*!< PWM6CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR6_PWM6CR1_Msk (0x2UL) /*!< PWM6CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_PWM6CR0_Pos (0UL) /*!< PWM6CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR6_PWM6CR0_Msk (0x1UL) /*!< PWM6CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR7 ========================================================= */
+#define HRPWM_COM_BDUPR7_FLT7R_Pos (29UL) /*!< FLT7R (Bit 29) */
+#define HRPWM_COM_BDUPR7_FLT7R_Msk (0x20000000UL) /*!< FLT7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_OUT7R_Pos (28UL) /*!< OUT7R (Bit 28) */
+#define HRPWM_COM_BDUPR7_OUT7R_Msk (0x10000000UL) /*!< OUT7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPB7CER_Pos (27UL) /*!< CAPB7CER (Bit 27) */
+#define HRPWM_COM_BDUPR7_CAPB7CER_Msk (0x8000000UL) /*!< CAPB7CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPB7CR_Pos (26UL) /*!< CAPB7CR (Bit 26) */
+#define HRPWM_COM_BDUPR7_CAPB7CR_Msk (0x4000000UL) /*!< CAPB7CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPA7CER_Pos (25UL) /*!< CAPA7CER (Bit 25) */
+#define HRPWM_COM_BDUPR7_CAPA7CER_Msk (0x2000000UL) /*!< CAPA7CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPA7CR_Pos (24UL) /*!< CAPA7CR (Bit 24) */
+#define HRPWM_COM_BDUPR7_CAPA7CR_Msk (0x1000000UL) /*!< CAPA7CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CHP7R_Pos (23UL) /*!< CHP7R (Bit 23) */
+#define HRPWM_COM_BDUPR7_CHP7R_Msk (0x800000UL) /*!< CHP7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_RST7ER_Pos (22UL) /*!< RST7ER (Bit 22) */
+#define HRPWM_COM_BDUPR7_RST7ER_Msk (0x400000UL) /*!< RST7ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_RST7R_Pos (21UL) /*!< RST7R (Bit 21) */
+#define HRPWM_COM_BDUPR7_RST7R_Msk (0x200000UL) /*!< RST7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_EEF7R2_Pos (20UL) /*!< EEF7R2 (Bit 20) */
+#define HRPWM_COM_BDUPR7_EEF7R2_Msk (0x100000UL) /*!< EEF7R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_EEF7R1_Pos (19UL) /*!< EEF7R1 (Bit 19) */
+#define HRPWM_COM_BDUPR7_EEF7R1_Msk (0x80000UL) /*!< EEF7R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_EEF7R0_Pos (18UL) /*!< EEF7R0 (Bit 18) */
+#define HRPWM_COM_BDUPR7_EEF7R0_Msk (0x40000UL) /*!< EEF7R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CLR7BR_Pos (17UL) /*!< CLR7BR (Bit 17) */
+#define HRPWM_COM_BDUPR7_CLR7BR_Msk (0x20000UL) /*!< CLR7BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_SET7BR_Pos (16UL) /*!< SET7BR (Bit 16) */
+#define HRPWM_COM_BDUPR7_SET7BR_Msk (0x10000UL) /*!< SET7BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CLR7AR_Pos (15UL) /*!< CLR7AR (Bit 15) */
+#define HRPWM_COM_BDUPR7_CLR7AR_Msk (0x8000UL) /*!< CLR7AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_SET7AR_Pos (14UL) /*!< SET7AR (Bit 14) */
+#define HRPWM_COM_BDUPR7_SET7AR_Msk (0x4000UL) /*!< SET7AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_DT7R_Pos (13UL) /*!< DT7R (Bit 13) */
+#define HRPWM_COM_BDUPR7_DT7R_Msk (0x2000UL) /*!< DT7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPB7R_Pos (12UL) /*!< CAPB7R (Bit 12) */
+#define HRPWM_COM_BDUPR7_CAPB7R_Msk (0x1000UL) /*!< CAPB7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPA7R_Pos (11UL) /*!< CAPA7R (Bit 11) */
+#define HRPWM_COM_BDUPR7_CAPA7R_Msk (0x800UL) /*!< CAPA7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CMPD7R_Pos (10UL) /*!< CMPD7R (Bit 10) */
+#define HRPWM_COM_BDUPR7_CMPD7R_Msk (0x400UL) /*!< CMPD7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CMPC7R_Pos (9UL) /*!< CMPC7R (Bit 9) */
+#define HRPWM_COM_BDUPR7_CMPC7R_Msk (0x200UL) /*!< CMPC7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CMPB7R_Pos (8UL) /*!< CMPB7R (Bit 8) */
+#define HRPWM_COM_BDUPR7_CMPB7R_Msk (0x100UL) /*!< CMPB7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CMPA7R_Pos (7UL) /*!< CMPA7R (Bit 7) */
+#define HRPWM_COM_BDUPR7_CMPA7R_Msk (0x80UL) /*!< CMPA7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_REP7R_Pos (6UL) /*!< REP7R (Bit 6) */
+#define HRPWM_COM_BDUPR7_REP7R_Msk (0x40UL) /*!< REP7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_PER7R_Pos (5UL) /*!< PER7R (Bit 5) */
+#define HRPWM_COM_BDUPR7_PER7R_Msk (0x20UL) /*!< PER7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CNT7R_Pos (4UL) /*!< CNT7R (Bit 4) */
+#define HRPWM_COM_BDUPR7_CNT7R_Msk (0x10UL) /*!< CNT7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_PWM7DIER_Pos (3UL) /*!< PWM7DIER (Bit 3) */
+#define HRPWM_COM_BDUPR7_PWM7DIER_Msk (0x8UL) /*!< PWM7DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_PWM7ISR_Pos (2UL) /*!< PWM7ISR (Bit 2) */
+#define HRPWM_COM_BDUPR7_PWM7ISR_Msk (0x4UL) /*!< PWM7ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_PWM7CR1_Pos (1UL) /*!< PWM7CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR7_PWM7CR1_Msk (0x2UL) /*!< PWM7CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_PWM7CR0_Pos (0UL) /*!< PWM7CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR7_PWM7CR0_Msk (0x1UL) /*!< PWM7CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDMWADR ======================================================== */
+#define HRPWM_COM_BDMWADR_BDMADR_Pos (0UL) /*!< BDMADR (Bit 0) */
+#define HRPWM_COM_BDMWADR_BDMADR_Msk (0xffffffffUL) /*!< BDMADR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== BDMADR ========================================================= */
+#define HRPWM_COM_BDMADR_BDMADR_Pos (0UL) /*!< BDMADR (Bit 0) */
+#define HRPWM_COM_BDMADR_BDMADR_Msk (0xffffffffUL) /*!< BDMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_MST ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= MCR0 ========================================================== */
+#define HRPWM_MST_MCR0_BRSTDMA_Pos (30UL) /*!< BRSTDMA (Bit 30) */
+#define HRPWM_MST_MCR0_BRSTDMA_Msk (0xc0000000UL) /*!< BRSTDMA (Bitfield-Mask: 0x03) */
+#define HRPWM_MST_MCR0_MREPU_Pos (27UL) /*!< MREPU (Bit 27) */
+#define HRPWM_MST_MCR0_MREPU_Msk (0x8000000UL) /*!< MREPU (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_MRSTU_Pos (26UL) /*!< MRSTU (Bit 26) */
+#define HRPWM_MST_MCR0_MRSTU_Msk (0x4000000UL) /*!< MRSTU (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_MST_MCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_MST_MCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_MST_MCR0_SYNCOUTSRC_Pos (14UL) /*!< SYNCOUTSRC (Bit 14) */
+#define HRPWM_MST_MCR0_SYNCOUTSRC_Msk (0xc000UL) /*!< SYNCOUTSRC (Bitfield-Mask: 0x03) */
+#define HRPWM_MST_MCR0_SYNCOUTEN_Pos (13UL) /*!< SYNCOUTEN (Bit 13) */
+#define HRPWM_MST_MCR0_SYNCOUTEN_Msk (0x2000UL) /*!< SYNCOUTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_SYNCOUTPOL_Pos (12UL) /*!< SYNCOUTPOL (Bit 12) */
+#define HRPWM_MST_MCR0_SYNCOUTPOL_Msk (0x1000UL) /*!< SYNCOUTPOL (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_SYNCSTRTM_Pos (11UL) /*!< SYNCSTRTM (Bit 11) */
+#define HRPWM_MST_MCR0_SYNCSTRTM_Msk (0x800UL) /*!< SYNCSTRTM (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_SYNCRSTM_Pos (10UL) /*!< SYNCRSTM (Bit 10) */
+#define HRPWM_MST_MCR0_SYNCRSTM_Msk (0x400UL) /*!< SYNCRSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_SYNCINEN_Pos (9UL) /*!< SYNCINEN (Bit 9) */
+#define HRPWM_MST_MCR0_SYNCINEN_Msk (0x200UL) /*!< SYNCINEN (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_SYNCINSRC_Pos (8UL) /*!< SYNCINSRC (Bit 8) */
+#define HRPWM_MST_MCR0_SYNCINSRC_Msk (0x100UL) /*!< SYNCINSRC (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_MST_MCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_MST_MCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_MST_MCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_MST_MCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_MST_MCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_MST_MCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ========================================================= MCR1 ========================================================== */
+#define HRPWM_MST_MCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_MST_MCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN7_Pos (24UL) /*!< CEN7 (Bit 24) */
+#define HRPWM_MST_MCR1_CEN7_Msk (0x1000000UL) /*!< CEN7 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN6_Pos (23UL) /*!< CEN6 (Bit 23) */
+#define HRPWM_MST_MCR1_CEN6_Msk (0x800000UL) /*!< CEN6 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN5_Pos (22UL) /*!< CEN5 (Bit 22) */
+#define HRPWM_MST_MCR1_CEN5_Msk (0x400000UL) /*!< CEN5 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN4_Pos (21UL) /*!< CEN4 (Bit 21) */
+#define HRPWM_MST_MCR1_CEN4_Msk (0x200000UL) /*!< CEN4 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN3_Pos (20UL) /*!< CEN3 (Bit 20) */
+#define HRPWM_MST_MCR1_CEN3_Msk (0x100000UL) /*!< CEN3 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN2_Pos (19UL) /*!< CEN2 (Bit 19) */
+#define HRPWM_MST_MCR1_CEN2_Msk (0x80000UL) /*!< CEN2 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN1_Pos (18UL) /*!< CEN1 (Bit 18) */
+#define HRPWM_MST_MCR1_CEN1_Msk (0x40000UL) /*!< CEN1 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN0_Pos (17UL) /*!< CEN0 (Bit 17) */
+#define HRPWM_MST_MCR1_CEN0_Msk (0x20000UL) /*!< CEN0 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_MCEN_Pos (16UL) /*!< MCEN (Bit 16) */
+#define HRPWM_MST_MCR1_MCEN_Msk (0x10000UL) /*!< MCEN (Bitfield-Mask: 0x01) */
+/* ========================================================= MISR ========================================================== */
+#define HRPWM_MST_MISR_MREP_Pos (8UL) /*!< MREP (Bit 8) */
+#define HRPWM_MST_MISR_MREP_Msk (0x100UL) /*!< MREP (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MRST_Pos (7UL) /*!< MRST (Bit 7) */
+#define HRPWM_MST_MISR_MRST_Msk (0x80UL) /*!< MRST (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MUPD_Pos (6UL) /*!< MUPD (Bit 6) */
+#define HRPWM_MST_MISR_MUPD_Msk (0x40UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_SYNC_Pos (5UL) /*!< SYNC (Bit 5) */
+#define HRPWM_MST_MISR_SYNC_Msk (0x20UL) /*!< SYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MPER_Pos (4UL) /*!< MPER (Bit 4) */
+#define HRPWM_MST_MISR_MPER_Msk (0x10UL) /*!< MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MCMPD_Pos (3UL) /*!< MCMPD (Bit 3) */
+#define HRPWM_MST_MISR_MCMPD_Msk (0x8UL) /*!< MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MCMPC_Pos (2UL) /*!< MCMPC (Bit 2) */
+#define HRPWM_MST_MISR_MCMPC_Msk (0x4UL) /*!< MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MCMPB_Pos (1UL) /*!< MCMPB (Bit 1) */
+#define HRPWM_MST_MISR_MCMPB_Msk (0x2UL) /*!< MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MCMPA_Pos (0UL) /*!< MCMPA (Bit 0) */
+#define HRPWM_MST_MISR_MCMPA_Msk (0x1UL) /*!< MCMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= MDIER ========================================================= */
+#define HRPWM_MST_MDIER_MREPDE_Pos (24UL) /*!< MREPDE (Bit 24) */
+#define HRPWM_MST_MDIER_MREPDE_Msk (0x1000000UL) /*!< MREPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MRSTDE_Pos (23UL) /*!< MRSTDE (Bit 23) */
+#define HRPWM_MST_MDIER_MRSTDE_Msk (0x800000UL) /*!< MRSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MUPDDE_Pos (22UL) /*!< MUPDDE (Bit 22) */
+#define HRPWM_MST_MDIER_MUPDDE_Msk (0x400000UL) /*!< MUPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_SYNCDE_Pos (21UL) /*!< SYNCDE (Bit 21) */
+#define HRPWM_MST_MDIER_SYNCDE_Msk (0x200000UL) /*!< SYNCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MPERDE_Pos (20UL) /*!< MPERDE (Bit 20) */
+#define HRPWM_MST_MDIER_MPERDE_Msk (0x100000UL) /*!< MPERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPDDE_Pos (19UL) /*!< MCMPDDE (Bit 19) */
+#define HRPWM_MST_MDIER_MCMPDDE_Msk (0x80000UL) /*!< MCMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPCDE_Pos (18UL) /*!< MCMPCDE (Bit 18) */
+#define HRPWM_MST_MDIER_MCMPCDE_Msk (0x40000UL) /*!< MCMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPBDE_Pos (17UL) /*!< MCMPBDE (Bit 17) */
+#define HRPWM_MST_MDIER_MCMPBDE_Msk (0x20000UL) /*!< MCMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPADE_Pos (16UL) /*!< MCMPADE (Bit 16) */
+#define HRPWM_MST_MDIER_MCMPADE_Msk (0x10000UL) /*!< MCMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MREPIE_Pos (8UL) /*!< MREPIE (Bit 8) */
+#define HRPWM_MST_MDIER_MREPIE_Msk (0x100UL) /*!< MREPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MRSTIE_Pos (7UL) /*!< MRSTIE (Bit 7) */
+#define HRPWM_MST_MDIER_MRSTIE_Msk (0x80UL) /*!< MRSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MUPDIE_Pos (6UL) /*!< MUPDIE (Bit 6) */
+#define HRPWM_MST_MDIER_MUPDIE_Msk (0x40UL) /*!< MUPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_SYNCIE_Pos (5UL) /*!< SYNCIE (Bit 5) */
+#define HRPWM_MST_MDIER_SYNCIE_Msk (0x20UL) /*!< SYNCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MPERIE_Pos (4UL) /*!< MPERIE (Bit 4) */
+#define HRPWM_MST_MDIER_MPERIE_Msk (0x10UL) /*!< MPERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPDIE_Pos (3UL) /*!< MCMPDIE (Bit 3) */
+#define HRPWM_MST_MDIER_MCMPDIE_Msk (0x8UL) /*!< MCMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPCIE_Pos (2UL) /*!< MCMPCIE (Bit 2) */
+#define HRPWM_MST_MDIER_MCMPCIE_Msk (0x4UL) /*!< MCMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPBIE_Pos (1UL) /*!< MCMPBIE (Bit 1) */
+#define HRPWM_MST_MDIER_MCMPBIE_Msk (0x2UL) /*!< MCMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPAIE_Pos (0UL) /*!< MCMPAIE (Bit 0) */
+#define HRPWM_MST_MDIER_MCMPAIE_Msk (0x1UL) /*!< MCMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= MCNTR ========================================================= */
+#define HRPWM_MST_MCNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_MST_MCNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_MST_MCNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCNTR_MCNT_Pos (0UL) /*!< MCNT (Bit 0) */
+#define HRPWM_MST_MCNTR_MCNT_Msk (0xffffUL) /*!< MCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= MPER ========================================================== */
+#define HRPWM_MST_MPER_MPER_Pos (0UL) /*!< MPER (Bit 0) */
+#define HRPWM_MST_MPER_MPER_Msk (0xffffUL) /*!< MPER (Bitfield-Mask: 0xffff) */
+/* ========================================================= MREP ========================================================== */
+#define HRPWM_MST_MREP_MREP_Pos (0UL) /*!< MREP (Bit 0) */
+#define HRPWM_MST_MREP_MREP_Msk (0xffUL) /*!< MREP (Bitfield-Mask: 0xff) */
+/* ======================================================== MCMPAR ========================================================= */
+#define HRPWM_MST_MCMPAR_MCMPA_Pos (0UL) /*!< MCMPA (Bit 0) */
+#define HRPWM_MST_MCMPAR_MCMPA_Msk (0xffffUL) /*!< MCMPA (Bitfield-Mask: 0xffff) */
+/* ======================================================== MCMPBR ========================================================= */
+#define HRPWM_MST_MCMPBR_MCMPB_Pos (0UL) /*!< MCMPB (Bit 0) */
+#define HRPWM_MST_MCMPBR_MCMPB_Msk (0xffffUL) /*!< MCMPB (Bitfield-Mask: 0xffff) */
+/* ======================================================== MCMPCR ========================================================= */
+#define HRPWM_MST_MCMPCR_MCMPC_Pos (0UL) /*!< MCMPC (Bit 0) */
+#define HRPWM_MST_MCMPCR_MCMPC_Msk (0xffffUL) /*!< MCMPC (Bitfield-Mask: 0xffff) */
+/* ======================================================== MCMPDR ========================================================= */
+#define HRPWM_MST_MCMPDR_MCMPD_Pos (0UL) /*!< MCMPD (Bit 0) */
+#define HRPWM_MST_MCMPDR_MCMPD_Msk (0xffffUL) /*!< MCMPD (Bitfield-Mask: 0xffff) */
+/* ======================================================== MDMAUR ========================================================= */
+#define HRPWM_MST_MDMAUR_MCMPDR_Pos (10UL) /*!< MCMPDR (Bit 10) */
+#define HRPWM_MST_MDMAUR_MCMPDR_Msk (0x400UL) /*!< MCMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCMPCR_Pos (9UL) /*!< MCMPCR (Bit 9) */
+#define HRPWM_MST_MDMAUR_MCMPCR_Msk (0x200UL) /*!< MCMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCMPBR_Pos (8UL) /*!< MCMPBR (Bit 8) */
+#define HRPWM_MST_MDMAUR_MCMPBR_Msk (0x100UL) /*!< MCMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCMPAR_Pos (7UL) /*!< MCMPAR (Bit 7) */
+#define HRPWM_MST_MDMAUR_MCMPAR_Msk (0x80UL) /*!< MCMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MREP_Pos (6UL) /*!< MREP (Bit 6) */
+#define HRPWM_MST_MDMAUR_MREP_Msk (0x40UL) /*!< MREP (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MPER_Pos (5UL) /*!< MPER (Bit 5) */
+#define HRPWM_MST_MDMAUR_MPER_Msk (0x20UL) /*!< MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCNTR_Pos (4UL) /*!< MCNTR (Bit 4) */
+#define HRPWM_MST_MDMAUR_MCNTR_Msk (0x10UL) /*!< MCNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MDIER_Pos (3UL) /*!< MDIER (Bit 3) */
+#define HRPWM_MST_MDMAUR_MDIER_Msk (0x8UL) /*!< MDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MISR_Pos (2UL) /*!< MISR (Bit 2) */
+#define HRPWM_MST_MDMAUR_MISR_Msk (0x4UL) /*!< MISR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCR1_Pos (1UL) /*!< MCR1 (Bit 1) */
+#define HRPWM_MST_MDMAUR_MCR1_Msk (0x2UL) /*!< MCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCR0_Pos (0UL) /*!< MCR0 (Bit 0) */
+#define HRPWM_MST_MDMAUR_MCR0_Msk (0x1UL) /*!< MCR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== MDMADR ========================================================= */
+#define HRPWM_MST_MDMADR_MDMADR_Pos (0UL) /*!< MDMADR (Bit 0) */
+#define HRPWM_MST_MDMADR_MDMADR_Msk (0xffffffffUL) /*!< MDMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR3_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR3_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR3_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR3_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR3_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_CMS_Pos (5UL) /*!< CMS (Bit 5) */
+#define TMR3_CR0_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */
+#define TMR3_CR0_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+#define TMR3_CR0_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR3_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR3_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR3_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR3_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR3_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR3_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR3_SCR_EE_Pos (22UL) /*!< EE (Bit 22) */
+#define TMR3_SCR_EE_Msk (0x400000UL) /*!< EE (Bitfield-Mask: 0x01) */
+#define TMR3_SCR_EMS_Pos (20UL) /*!< EMS (Bit 20) */
+#define TMR3_SCR_EMS_Msk (0x300000UL) /*!< EMS (Bitfield-Mask: 0x03) */
+#define TMR3_SCR_EFS_Pos (16UL) /*!< EFS (Bit 16) */
+#define TMR3_SCR_EFS_Msk (0xf0000UL) /*!< EFS (Bitfield-Mask: 0x0f) */
+#define TMR3_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR3_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR3_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR3_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR3_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR3_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR3_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR3_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C3OIE_Pos (7UL) /*!< C3OIE (Bit 7) */
+#define TMR3_IER_C3OIE_Msk (0x80UL) /*!< C3OIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C3MIE_Pos (6UL) /*!< C3MIE (Bit 6) */
+#define TMR3_IER_C3MIE_Msk (0x40UL) /*!< C3MIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C2OIE_Pos (5UL) /*!< C2OIE (Bit 5) */
+#define TMR3_IER_C2OIE_Msk (0x20UL) /*!< C2OIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C2MIE_Pos (4UL) /*!< C2MIE (Bit 4) */
+#define TMR3_IER_C2MIE_Msk (0x10UL) /*!< C2MIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR3_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR3_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR3_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR3_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR3_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR3_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR3_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR3_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC3OIF_Pos (7UL) /*!< CC3OIF (Bit 7) */
+#define TMR3_SR_CC3OIF_Msk (0x80UL) /*!< CC3OIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC3MIF_Pos (6UL) /*!< CC3MIF (Bit 6) */
+#define TMR3_SR_CC3MIF_Msk (0x40UL) /*!< CC3MIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC2OIF_Pos (5UL) /*!< CC2OIF (Bit 5) */
+#define TMR3_SR_CC2OIF_Msk (0x20UL) /*!< CC2OIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC2MIF_Pos (4UL) /*!< CC2MIF (Bit 4) */
+#define TMR3_SR_CC2MIF_Msk (0x10UL) /*!< CC2MIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR3_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR3_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR3_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR3_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR3_UGR_CC3UG_Pos (7UL) /*!< CC3UG (Bit 7) */
+#define TMR3_UGR_CC3UG_Msk (0x80UL) /*!< CC3UG (Bitfield-Mask: 0x01) */
+#define TMR3_UGR_CC2UG_Pos (6UL) /*!< CC2UG (Bit 6) */
+#define TMR3_UGR_CC2UG_Msk (0x40UL) /*!< CC2UG (Bitfield-Mask: 0x01) */
+#define TMR3_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR3_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR3_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR3_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR3_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR3_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR3_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR3_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR3_CCMR_OC3M_Pos (28UL) /*!< OC3M (Bit 28) */
+#define TMR3_CCMR_OC3M_Msk (0xf0000000UL) /*!< OC3M (Bitfield-Mask: 0x0f) */
+#define TMR3_CCMR_CC3PE_Pos (26UL) /*!< CC3PE (Bit 26) */
+#define TMR3_CCMR_CC3PE_Msk (0xc000000UL) /*!< CC3PE (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_CC3S_Pos (24UL) /*!< CC3S (Bit 24) */
+#define TMR3_CCMR_CC3S_Msk (0x3000000UL) /*!< CC3S (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_OC2M_Pos (20UL) /*!< OC2M (Bit 20) */
+#define TMR3_CCMR_OC2M_Msk (0xf00000UL) /*!< OC2M (Bitfield-Mask: 0x0f) */
+#define TMR3_CCMR_CC2PE_Pos (18UL) /*!< CC2PE (Bit 18) */
+#define TMR3_CCMR_CC2PE_Msk (0xc0000UL) /*!< CC2PE (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_CC2S_Pos (16UL) /*!< CC2S (Bit 16) */
+#define TMR3_CCMR_CC2S_Msk (0x30000UL) /*!< CC2S (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR3_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR3_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR3_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR3_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR3_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR3_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR3_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR3_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR3_CCER_CC3P_Pos (14UL) /*!< CC3P (Bit 14) */
+#define TMR3_CCER_CC3P_Msk (0xc000UL) /*!< CC3P (Bitfield-Mask: 0x03) */
+#define TMR3_CCER_CC3E_Pos (12UL) /*!< CC3E (Bit 12) */
+#define TMR3_CCER_CC3E_Msk (0x1000UL) /*!< CC3E (Bitfield-Mask: 0x01) */
+#define TMR3_CCER_CC2P_Pos (10UL) /*!< CC2P (Bit 10) */
+#define TMR3_CCER_CC2P_Msk (0xc00UL) /*!< CC2P (Bitfield-Mask: 0x03) */
+#define TMR3_CCER_CC2E_Pos (8UL) /*!< CC2E (Bit 8) */
+#define TMR3_CCER_CC2E_Msk (0x100UL) /*!< CC2E (Bitfield-Mask: 0x01) */
+#define TMR3_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR3_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR3_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR3_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR3_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR3_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR3_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR3_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR3_TTCR_TC3E_Pos (11UL) /*!< TC3E (Bit 11) */
+#define TMR3_TTCR_TC3E_Msk (0x800UL) /*!< TC3E (Bitfield-Mask: 0x01) */
+#define TMR3_TTCR_TC2E_Pos (10UL) /*!< TC2E (Bit 10) */
+#define TMR3_TTCR_TC2E_Msk (0x400UL) /*!< TC2E (Bitfield-Mask: 0x01) */
+#define TMR3_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR3_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR3_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR3_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR3_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR3_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR3_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR3_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR3_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR3_CPR_CPV_Msk (0xffffffffUL) /*!< CPV (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR3_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR3_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR3_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR3_CNTR_CNT_Msk (0xffffffffUL) /*!< CNT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR3_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR3_CC0R_CC0V_Msk (0xffffffffUL) /*!< CC0V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR3_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR3_CC1R_CC1V_Msk (0xffffffffUL) /*!< CC1V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC2R ========================================================== */
+#define TMR3_CC2R_CC2V_Pos (0UL) /*!< CC2V (Bit 0) */
+#define TMR3_CC2R_CC2V_Msk (0xffffffffUL) /*!< CC2V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC3R ========================================================== */
+#define TMR3_CC3R_CC3V_Pos (0UL) /*!< CC3V (Bit 0) */
+#define TMR3_CC3R_CC3V_Msk (0xffffffffUL) /*!< CC3V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR3_CIR_C3TIS_Pos (24UL) /*!< C3TIS (Bit 24) */
+#define TMR3_CIR_C3TIS_Msk (0xf000000UL) /*!< C3TIS (Bitfield-Mask: 0x0f) */
+#define TMR3_CIR_C2TIS_Pos (16UL) /*!< C2TIS (Bit 16) */
+#define TMR3_CIR_C2TIS_Msk (0xf0000UL) /*!< C2TIS (Bitfield-Mask: 0x0f) */
+#define TMR3_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR3_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR3_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR3_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR4_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR4_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR4_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR4_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR4_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_CMS_Pos (5UL) /*!< CMS (Bit 5) */
+#define TMR4_CR0_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */
+#define TMR4_CR0_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+#define TMR4_CR0_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR4_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR4_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR4_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR4_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR4_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR4_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR4_SCR_EE_Pos (22UL) /*!< EE (Bit 22) */
+#define TMR4_SCR_EE_Msk (0x400000UL) /*!< EE (Bitfield-Mask: 0x01) */
+#define TMR4_SCR_EMS_Pos (20UL) /*!< EMS (Bit 20) */
+#define TMR4_SCR_EMS_Msk (0x300000UL) /*!< EMS (Bitfield-Mask: 0x03) */
+#define TMR4_SCR_EFS_Pos (16UL) /*!< EFS (Bit 16) */
+#define TMR4_SCR_EFS_Msk (0xf0000UL) /*!< EFS (Bitfield-Mask: 0x0f) */
+#define TMR4_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR4_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR4_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR4_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR4_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR4_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR4_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR4_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C3OIE_Pos (7UL) /*!< C3OIE (Bit 7) */
+#define TMR4_IER_C3OIE_Msk (0x80UL) /*!< C3OIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C3MIE_Pos (6UL) /*!< C3MIE (Bit 6) */
+#define TMR4_IER_C3MIE_Msk (0x40UL) /*!< C3MIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C2OIE_Pos (5UL) /*!< C2OIE (Bit 5) */
+#define TMR4_IER_C2OIE_Msk (0x20UL) /*!< C2OIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C2MIE_Pos (4UL) /*!< C2MIE (Bit 4) */
+#define TMR4_IER_C2MIE_Msk (0x10UL) /*!< C2MIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR4_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR4_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR4_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR4_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR4_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR4_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR4_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR4_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC3OIF_Pos (7UL) /*!< CC3OIF (Bit 7) */
+#define TMR4_SR_CC3OIF_Msk (0x80UL) /*!< CC3OIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC3MIF_Pos (6UL) /*!< CC3MIF (Bit 6) */
+#define TMR4_SR_CC3MIF_Msk (0x40UL) /*!< CC3MIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC2OIF_Pos (5UL) /*!< CC2OIF (Bit 5) */
+#define TMR4_SR_CC2OIF_Msk (0x20UL) /*!< CC2OIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC2MIF_Pos (4UL) /*!< CC2MIF (Bit 4) */
+#define TMR4_SR_CC2MIF_Msk (0x10UL) /*!< CC2MIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR4_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR4_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR4_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR4_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR4_UGR_CC3UG_Pos (7UL) /*!< CC3UG (Bit 7) */
+#define TMR4_UGR_CC3UG_Msk (0x80UL) /*!< CC3UG (Bitfield-Mask: 0x01) */
+#define TMR4_UGR_CC2UG_Pos (6UL) /*!< CC2UG (Bit 6) */
+#define TMR4_UGR_CC2UG_Msk (0x40UL) /*!< CC2UG (Bitfield-Mask: 0x01) */
+#define TMR4_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR4_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR4_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR4_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR4_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR4_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR4_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR4_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR4_CCMR_OC3M_Pos (28UL) /*!< OC3M (Bit 28) */
+#define TMR4_CCMR_OC3M_Msk (0xf0000000UL) /*!< OC3M (Bitfield-Mask: 0x0f) */
+#define TMR4_CCMR_CC3PE_Pos (26UL) /*!< CC3PE (Bit 26) */
+#define TMR4_CCMR_CC3PE_Msk (0xc000000UL) /*!< CC3PE (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_CC3S_Pos (24UL) /*!< CC3S (Bit 24) */
+#define TMR4_CCMR_CC3S_Msk (0x3000000UL) /*!< CC3S (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_OC2M_Pos (20UL) /*!< OC2M (Bit 20) */
+#define TMR4_CCMR_OC2M_Msk (0xf00000UL) /*!< OC2M (Bitfield-Mask: 0x0f) */
+#define TMR4_CCMR_CC2PE_Pos (18UL) /*!< CC2PE (Bit 18) */
+#define TMR4_CCMR_CC2PE_Msk (0xc0000UL) /*!< CC2PE (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_CC2S_Pos (16UL) /*!< CC2S (Bit 16) */
+#define TMR4_CCMR_CC2S_Msk (0x30000UL) /*!< CC2S (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR4_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR4_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR4_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR4_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR4_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR4_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR4_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR4_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR4_CCER_CC3P_Pos (14UL) /*!< CC3P (Bit 14) */
+#define TMR4_CCER_CC3P_Msk (0xc000UL) /*!< CC3P (Bitfield-Mask: 0x03) */
+#define TMR4_CCER_CC3E_Pos (12UL) /*!< CC3E (Bit 12) */
+#define TMR4_CCER_CC3E_Msk (0x1000UL) /*!< CC3E (Bitfield-Mask: 0x01) */
+#define TMR4_CCER_CC2P_Pos (10UL) /*!< CC2P (Bit 10) */
+#define TMR4_CCER_CC2P_Msk (0xc00UL) /*!< CC2P (Bitfield-Mask: 0x03) */
+#define TMR4_CCER_CC2E_Pos (8UL) /*!< CC2E (Bit 8) */
+#define TMR4_CCER_CC2E_Msk (0x100UL) /*!< CC2E (Bitfield-Mask: 0x01) */
+#define TMR4_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR4_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR4_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR4_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR4_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR4_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR4_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR4_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR4_TTCR_TC3E_Pos (11UL) /*!< TC3E (Bit 11) */
+#define TMR4_TTCR_TC3E_Msk (0x800UL) /*!< TC3E (Bitfield-Mask: 0x01) */
+#define TMR4_TTCR_TC2E_Pos (10UL) /*!< TC2E (Bit 10) */
+#define TMR4_TTCR_TC2E_Msk (0x400UL) /*!< TC2E (Bitfield-Mask: 0x01) */
+#define TMR4_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR4_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR4_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR4_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR4_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR4_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR4_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR4_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR4_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR4_CPR_CPV_Msk (0xffffffffUL) /*!< CPV (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR4_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR4_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR4_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR4_CNTR_CNT_Msk (0xffffffffUL) /*!< CNT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR4_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR4_CC0R_CC0V_Msk (0xffffffffUL) /*!< CC0V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR4_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR4_CC1R_CC1V_Msk (0xffffffffUL) /*!< CC1V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC2R ========================================================== */
+#define TMR4_CC2R_CC2V_Pos (0UL) /*!< CC2V (Bit 0) */
+#define TMR4_CC2R_CC2V_Msk (0xffffffffUL) /*!< CC2V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC3R ========================================================== */
+#define TMR4_CC3R_CC3V_Pos (0UL) /*!< CC3V (Bit 0) */
+#define TMR4_CC3R_CC3V_Msk (0xffffffffUL) /*!< CC3V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR4_CIR_C3TIS_Pos (24UL) /*!< C3TIS (Bit 24) */
+#define TMR4_CIR_C3TIS_Msk (0xf000000UL) /*!< C3TIS (Bitfield-Mask: 0x0f) */
+#define TMR4_CIR_C2TIS_Pos (16UL) /*!< C2TIS (Bit 16) */
+#define TMR4_CIR_C2TIS_Msk (0xf0000UL) /*!< C2TIS (Bitfield-Mask: 0x0f) */
+#define TMR4_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR4_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR4_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR4_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR0_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR0_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR0_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR0_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR0_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR0_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR0_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR0_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR0_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR0_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR0_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR0_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR0_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR0_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR0_CR1_OIS1N_Pos (11UL) /*!< OIS1N (Bit 11) */
+#define TMR0_CR1_OIS1N_Msk (0x800UL) /*!< OIS1N (Bitfield-Mask: 0x01) */
+#define TMR0_CR1_OIS1_Pos (10UL) /*!< OIS1 (Bit 10) */
+#define TMR0_CR1_OIS1_Msk (0x400UL) /*!< OIS1 (Bitfield-Mask: 0x01) */
+#define TMR0_CR1_OIS0N_Pos (9UL) /*!< OIS0N (Bit 9) */
+#define TMR0_CR1_OIS0N_Msk (0x200UL) /*!< OIS0N (Bitfield-Mask: 0x01) */
+#define TMR0_CR1_OIS0_Pos (8UL) /*!< OIS0 (Bit 8) */
+#define TMR0_CR1_OIS0_Msk (0x100UL) /*!< OIS0 (Bitfield-Mask: 0x01) */
+#define TMR0_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR0_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR0_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR0_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR0_SCR_FE_Pos (7UL) /*!< FE (Bit 7) */
+#define TMR0_SCR_FE_Msk (0x80UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define TMR0_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR0_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR0_IER_BIE_Pos (11UL) /*!< BIE (Bit 11) */
+#define TMR0_IER_BIE_Msk (0x800UL) /*!< BIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR0_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR0_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR0_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR0_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR0_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR0_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR0_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR0_SR_SBIF_Pos (12UL) /*!< SBIF (Bit 12) */
+#define TMR0_SR_SBIF_Msk (0x1000UL) /*!< SBIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_BIF_Pos (11UL) /*!< BIF (Bit 11) */
+#define TMR0_SR_BIF_Msk (0x800UL) /*!< BIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR0_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR0_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR0_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR0_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR0_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR0_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR0_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR0_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR0_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR0_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR0_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR0_UGR_BG_Pos (2UL) /*!< BG (Bit 2) */
+#define TMR0_UGR_BG_Msk (0x4UL) /*!< BG (Bitfield-Mask: 0x01) */
+#define TMR0_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR0_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR0_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR0_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR0_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR0_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR0_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR0_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR0_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR0_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR0_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR0_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR0_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR0_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR0_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR0_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR0_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR0_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR0_CCER_CC1NE_Pos (5UL) /*!< CC1NE (Bit 5) */
+#define TMR0_CCER_CC1NE_Msk (0x20UL) /*!< CC1NE (Bitfield-Mask: 0x01) */
+#define TMR0_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR0_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR0_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR0_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR0_CCER_CC0NE_Pos (1UL) /*!< CC0NE (Bit 1) */
+#define TMR0_CCER_CC0NE_Msk (0x2UL) /*!< CC0NE (Bitfield-Mask: 0x01) */
+#define TMR0_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR0_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+#define TMR0_DCR_BKF_Pos (14UL) /*!< BKF (Bit 14) */
+#define TMR0_DCR_BKF_Msk (0x3fc000UL) /*!< BKF (Bitfield-Mask: 0xff) */
+#define TMR0_DCR_BKP_Pos (13UL) /*!< BKP (Bit 13) */
+#define TMR0_DCR_BKP_Msk (0x2000UL) /*!< BKP (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_BKE_Pos (12UL) /*!< BKE (Bit 12) */
+#define TMR0_DCR_BKE_Msk (0x1000UL) /*!< BKE (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_MOE_Pos (11UL) /*!< MOE (Bit 11) */
+#define TMR0_DCR_MOE_Msk (0x800UL) /*!< MOE (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_AOE_Pos (10UL) /*!< AOE (Bit 10) */
+#define TMR0_DCR_AOE_Msk (0x400UL) /*!< AOE (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_OSSR_Pos (9UL) /*!< OSSR (Bit 9) */
+#define TMR0_DCR_OSSR_Msk (0x200UL) /*!< OSSR (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_OSSI_Pos (8UL) /*!< OSSI (Bit 8) */
+#define TMR0_DCR_OSSI_Msk (0x100UL) /*!< OSSI (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_DTG_Pos (0UL) /*!< DTG (Bit 0) */
+#define TMR0_DCR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR0_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR0_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR0_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR0_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR0_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR0_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR0_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR0_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR0_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR0_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR0_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR0_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR0_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR0_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================== CRR ========================================================== */
+#define TMR0_CRR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define TMR0_CRR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR0_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR0_CC0R_CC0V_Msk (0xffffUL) /*!< CC0V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR0_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR0_CC1R_CC1V_Msk (0xffffUL) /*!< CC1V (Bitfield-Mask: 0xffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR0_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR0_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR0_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR0_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+/* ========================================================== BPR ========================================================== */
+#define TMR0_BPR_BPOL_Pos (0UL) /*!< BPOL (Bit 0) */
+#define TMR0_BPR_BPOL_Msk (0xffffUL) /*!< BPOL (Bitfield-Mask: 0xffff) */
+/* ========================================================== BER ========================================================== */
+#define TMR0_BER_BIEN_Pos (0UL) /*!< BIEN (Bit 0) */
+#define TMR0_BER_BIEN_Msk (0xffffUL) /*!< BIEN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR1_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR1_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR1_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR1_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR1_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR1_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR1_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR1_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR1_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR1_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR1_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR1_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR1_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR1_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR1_CR1_OIS1N_Pos (11UL) /*!< OIS1N (Bit 11) */
+#define TMR1_CR1_OIS1N_Msk (0x800UL) /*!< OIS1N (Bitfield-Mask: 0x01) */
+#define TMR1_CR1_OIS1_Pos (10UL) /*!< OIS1 (Bit 10) */
+#define TMR1_CR1_OIS1_Msk (0x400UL) /*!< OIS1 (Bitfield-Mask: 0x01) */
+#define TMR1_CR1_OIS0N_Pos (9UL) /*!< OIS0N (Bit 9) */
+#define TMR1_CR1_OIS0N_Msk (0x200UL) /*!< OIS0N (Bitfield-Mask: 0x01) */
+#define TMR1_CR1_OIS0_Pos (8UL) /*!< OIS0 (Bit 8) */
+#define TMR1_CR1_OIS0_Msk (0x100UL) /*!< OIS0 (Bitfield-Mask: 0x01) */
+#define TMR1_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR1_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR1_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR1_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR1_SCR_FE_Pos (7UL) /*!< FE (Bit 7) */
+#define TMR1_SCR_FE_Msk (0x80UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define TMR1_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR1_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR1_IER_BIE_Pos (11UL) /*!< BIE (Bit 11) */
+#define TMR1_IER_BIE_Msk (0x800UL) /*!< BIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR1_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR1_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR1_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR1_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR1_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR1_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR1_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR1_SR_SBIF_Pos (12UL) /*!< SBIF (Bit 12) */
+#define TMR1_SR_SBIF_Msk (0x1000UL) /*!< SBIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_BIF_Pos (11UL) /*!< BIF (Bit 11) */
+#define TMR1_SR_BIF_Msk (0x800UL) /*!< BIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR1_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR1_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR1_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR1_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR1_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR1_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR1_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR1_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR1_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR1_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR1_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR1_UGR_BG_Pos (2UL) /*!< BG (Bit 2) */
+#define TMR1_UGR_BG_Msk (0x4UL) /*!< BG (Bitfield-Mask: 0x01) */
+#define TMR1_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR1_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR1_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR1_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR1_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR1_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR1_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR1_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR1_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR1_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR1_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR1_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR1_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR1_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR1_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR1_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR1_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR1_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR1_CCER_CC1NE_Pos (5UL) /*!< CC1NE (Bit 5) */
+#define TMR1_CCER_CC1NE_Msk (0x20UL) /*!< CC1NE (Bitfield-Mask: 0x01) */
+#define TMR1_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR1_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR1_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR1_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR1_CCER_CC0NE_Pos (1UL) /*!< CC0NE (Bit 1) */
+#define TMR1_CCER_CC0NE_Msk (0x2UL) /*!< CC0NE (Bitfield-Mask: 0x01) */
+#define TMR1_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR1_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+#define TMR1_DCR_BKF_Pos (14UL) /*!< BKF (Bit 14) */
+#define TMR1_DCR_BKF_Msk (0x3fc000UL) /*!< BKF (Bitfield-Mask: 0xff) */
+#define TMR1_DCR_BKP_Pos (13UL) /*!< BKP (Bit 13) */
+#define TMR1_DCR_BKP_Msk (0x2000UL) /*!< BKP (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_BKE_Pos (12UL) /*!< BKE (Bit 12) */
+#define TMR1_DCR_BKE_Msk (0x1000UL) /*!< BKE (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_MOE_Pos (11UL) /*!< MOE (Bit 11) */
+#define TMR1_DCR_MOE_Msk (0x800UL) /*!< MOE (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_AOE_Pos (10UL) /*!< AOE (Bit 10) */
+#define TMR1_DCR_AOE_Msk (0x400UL) /*!< AOE (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_OSSR_Pos (9UL) /*!< OSSR (Bit 9) */
+#define TMR1_DCR_OSSR_Msk (0x200UL) /*!< OSSR (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_OSSI_Pos (8UL) /*!< OSSI (Bit 8) */
+#define TMR1_DCR_OSSI_Msk (0x100UL) /*!< OSSI (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_DTG_Pos (0UL) /*!< DTG (Bit 0) */
+#define TMR1_DCR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR1_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR1_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR1_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR1_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR1_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR1_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR1_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR1_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR1_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR1_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR1_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR1_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR1_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR1_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================== CRR ========================================================== */
+#define TMR1_CRR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define TMR1_CRR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR1_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR1_CC0R_CC0V_Msk (0xffffUL) /*!< CC0V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR1_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR1_CC1R_CC1V_Msk (0xffffUL) /*!< CC1V (Bitfield-Mask: 0xffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR1_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR1_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR1_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR1_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+/* ========================================================== BPR ========================================================== */
+#define TMR1_BPR_BPOL_Pos (0UL) /*!< BPOL (Bit 0) */
+#define TMR1_BPR_BPOL_Msk (0xffffUL) /*!< BPOL (Bitfield-Mask: 0xffff) */
+/* ========================================================== BER ========================================================== */
+#define TMR1_BER_BIEN_Pos (0UL) /*!< BIEN (Bit 0) */
+#define TMR1_BER_BIEN_Msk (0xffffUL) /*!< BIEN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR2_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR2_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR2_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR2_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR2_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR2_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR2_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR2_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR2_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR2_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR2_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR2_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR2_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR2_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR2_CR1_OIS1N_Pos (11UL) /*!< OIS1N (Bit 11) */
+#define TMR2_CR1_OIS1N_Msk (0x800UL) /*!< OIS1N (Bitfield-Mask: 0x01) */
+#define TMR2_CR1_OIS1_Pos (10UL) /*!< OIS1 (Bit 10) */
+#define TMR2_CR1_OIS1_Msk (0x400UL) /*!< OIS1 (Bitfield-Mask: 0x01) */
+#define TMR2_CR1_OIS0N_Pos (9UL) /*!< OIS0N (Bit 9) */
+#define TMR2_CR1_OIS0N_Msk (0x200UL) /*!< OIS0N (Bitfield-Mask: 0x01) */
+#define TMR2_CR1_OIS0_Pos (8UL) /*!< OIS0 (Bit 8) */
+#define TMR2_CR1_OIS0_Msk (0x100UL) /*!< OIS0 (Bitfield-Mask: 0x01) */
+#define TMR2_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR2_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR2_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR2_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR2_SCR_FE_Pos (7UL) /*!< FE (Bit 7) */
+#define TMR2_SCR_FE_Msk (0x80UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define TMR2_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR2_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR2_IER_BIE_Pos (11UL) /*!< BIE (Bit 11) */
+#define TMR2_IER_BIE_Msk (0x800UL) /*!< BIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR2_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR2_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR2_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR2_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR2_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR2_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR2_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR2_SR_SBIF_Pos (12UL) /*!< SBIF (Bit 12) */
+#define TMR2_SR_SBIF_Msk (0x1000UL) /*!< SBIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_BIF_Pos (11UL) /*!< BIF (Bit 11) */
+#define TMR2_SR_BIF_Msk (0x800UL) /*!< BIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR2_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR2_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR2_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR2_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR2_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR2_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR2_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR2_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR2_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR2_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR2_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR2_UGR_BG_Pos (2UL) /*!< BG (Bit 2) */
+#define TMR2_UGR_BG_Msk (0x4UL) /*!< BG (Bitfield-Mask: 0x01) */
+#define TMR2_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR2_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR2_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR2_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR2_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR2_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR2_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR2_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR2_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR2_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR2_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR2_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR2_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR2_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR2_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR2_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR2_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR2_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR2_CCER_CC1NE_Pos (5UL) /*!< CC1NE (Bit 5) */
+#define TMR2_CCER_CC1NE_Msk (0x20UL) /*!< CC1NE (Bitfield-Mask: 0x01) */
+#define TMR2_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR2_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR2_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR2_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR2_CCER_CC0NE_Pos (1UL) /*!< CC0NE (Bit 1) */
+#define TMR2_CCER_CC0NE_Msk (0x2UL) /*!< CC0NE (Bitfield-Mask: 0x01) */
+#define TMR2_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR2_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+#define TMR2_DCR_BKF_Pos (14UL) /*!< BKF (Bit 14) */
+#define TMR2_DCR_BKF_Msk (0x3fc000UL) /*!< BKF (Bitfield-Mask: 0xff) */
+#define TMR2_DCR_BKP_Pos (13UL) /*!< BKP (Bit 13) */
+#define TMR2_DCR_BKP_Msk (0x2000UL) /*!< BKP (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_BKE_Pos (12UL) /*!< BKE (Bit 12) */
+#define TMR2_DCR_BKE_Msk (0x1000UL) /*!< BKE (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_MOE_Pos (11UL) /*!< MOE (Bit 11) */
+#define TMR2_DCR_MOE_Msk (0x800UL) /*!< MOE (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_AOE_Pos (10UL) /*!< AOE (Bit 10) */
+#define TMR2_DCR_AOE_Msk (0x400UL) /*!< AOE (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_OSSR_Pos (9UL) /*!< OSSR (Bit 9) */
+#define TMR2_DCR_OSSR_Msk (0x200UL) /*!< OSSR (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_OSSI_Pos (8UL) /*!< OSSI (Bit 8) */
+#define TMR2_DCR_OSSI_Msk (0x100UL) /*!< OSSI (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_DTG_Pos (0UL) /*!< DTG (Bit 0) */
+#define TMR2_DCR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR2_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR2_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR2_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR2_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR2_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR2_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR2_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR2_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR2_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR2_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR2_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR2_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR2_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR2_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================== CRR ========================================================== */
+#define TMR2_CRR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define TMR2_CRR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR2_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR2_CC0R_CC0V_Msk (0xffffUL) /*!< CC0V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR2_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR2_CC1R_CC1V_Msk (0xffffUL) /*!< CC1V (Bitfield-Mask: 0xffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR2_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR2_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR2_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR2_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+/* ========================================================== BPR ========================================================== */
+#define TMR2_BPR_BPOL_Pos (0UL) /*!< BPOL (Bit 0) */
+#define TMR2_BPR_BPOL_Msk (0xffffUL) /*!< BPOL (Bitfield-Mask: 0xffff) */
+/* ========================================================== BER ========================================================== */
+#define TMR2_BER_BIEN_Pos (0UL) /*!< BIEN (Bit 0) */
+#define TMR2_BER_BIEN_Msk (0xffffUL) /*!< BIEN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOA ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOA_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOA_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOA_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOA_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOA_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOA_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOA_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOA_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOA_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOA_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOA_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOA_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOA_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOA_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOA_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOA_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOA_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOA_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOA_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOA_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOA_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOA_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOA_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOA_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOA_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOA_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOA_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOA_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOA_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOA_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOA_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOA_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOA_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOA_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOB ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOB_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOB_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOB_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOB_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOB_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOB_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOB_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOB_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOB_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOB_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOB_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOB_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOB_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOB_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOB_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOB_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOB_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOB_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOB_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOB_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOB_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOB_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOB_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOB_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOB_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOB_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOB_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOB_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOB_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOB_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOB_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOB_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOB_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOB_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOC_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOC_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOC_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOC_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOC_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOC_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOC_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOC_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOC_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOC_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOC_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOC_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOC_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOC_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOC_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOC_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOC_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOC_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOC_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOC_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOC_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOC_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOC_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOC_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOC_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOC_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOC_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOC_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOC_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOC_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOC_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOC_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOC_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOC_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOD ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOD_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOD_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOD_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOD_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOD_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOD_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOD_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOD_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOD_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOD_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOD_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOD_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOD_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOD_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOD_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOD_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOD_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOD_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOD_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOD_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOD_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOD_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOD_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOD_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOD_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOD_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOD_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOD_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOD_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOD_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOD_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOD_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOD_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOD_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOE ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOE_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOE_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOE_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOE_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOE_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOE_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOE_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOE_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOE_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOE_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOE_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOE_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOE_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOE_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOE_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOE_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOE_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOE_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOE_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOE_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOE_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOE_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOE_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOE_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOE_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOE_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOE_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOE_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOE_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOE_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOE_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOE_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOE_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOE_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOF ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOF_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOF_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOF_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOF_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOF_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOF_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOF_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOF_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOF_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOF_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOF_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOF_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOF_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOF_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOF_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOF_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOF_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOF_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOF_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOF_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOF_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOF_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOF_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOF_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOF_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOF_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOF_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOF_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOF_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOF_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOF_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOF_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOF_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOF_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ FLASH ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define FLASH_CR_LCK_Pos (31UL) /*!< LCK (Bit 31) */
+#define FLASH_CR_LCK_Msk (0x80000000UL) /*!< LCK (Bitfield-Mask: 0x01) */
+#define FLASH_CR_NMIE_Pos (10UL) /*!< NMIE (Bit 10) */
+#define FLASH_CR_NMIE_Msk (0x400UL) /*!< NMIE (Bitfield-Mask: 0x01) */
+#define FLASH_CR_EIE_Pos (7UL) /*!< EIE (Bit 7) */
+#define FLASH_CR_EIE_Msk (0x80UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define FLASH_CR_FLE_Pos (6UL) /*!< FLE (Bit 6) */
+#define FLASH_CR_FLE_Msk (0x40UL) /*!< FLE (Bitfield-Mask: 0x01) */
+#define FLASH_CR_DPE_Pos (5UL) /*!< DPE (Bit 5) */
+#define FLASH_CR_DPE_Msk (0x20UL) /*!< DPE (Bitfield-Mask: 0x01) */
+#define FLASH_CR_IPE_Pos (4UL) /*!< IPE (Bit 4) */
+#define FLASH_CR_IPE_Msk (0x10UL) /*!< IPE (Bitfield-Mask: 0x01) */
+#define FLASH_CR_CRS_Pos (3UL) /*!< CRS (Bit 3) */
+#define FLASH_CR_CRS_Msk (0x8UL) /*!< CRS (Bitfield-Mask: 0x01) */
+#define FLASH_CR_ES_Pos (1UL) /*!< ES (Bit 1) */
+#define FLASH_CR_ES_Msk (0x2UL) /*!< ES (Bitfield-Mask: 0x01) */
+#define FLASH_CR_PS_Pos (0UL) /*!< PS (Bit 0) */
+#define FLASH_CR_PS_Msk (0x1UL) /*!< PS (Bitfield-Mask: 0x01) */
+/* ========================================================== LPR ========================================================== */
+#define FLASH_LPR_LCK_Pos (31UL) /*!< LCK (Bit 31) */
+#define FLASH_LPR_LCK_Msk (0x80000000UL) /*!< LCK (Bitfield-Mask: 0x01) */
+#define FLASH_LPR_SEL_Pos (2UL) /*!< SEL (Bit 2) */
+#define FLASH_LPR_SEL_Msk (0xcUL) /*!< SEL (Bitfield-Mask: 0x03) */
+#define FLASH_LPR_LW_Pos (1UL) /*!< LW (Bit 1) */
+#define FLASH_LPR_LW_Msk (0x2UL) /*!< LW (Bitfield-Mask: 0x01) */
+#define FLASH_LPR_LS_Pos (0UL) /*!< LS (Bit 0) */
+#define FLASH_LPR_LS_Msk (0x1UL) /*!< LS (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define FLASH_SR_BST_Pos (31UL) /*!< BST (Bit 31) */
+#define FLASH_SR_BST_Msk (0x80000000UL) /*!< BST (Bitfield-Mask: 0x01) */
+#define FLASH_SR_BMS_Pos (30UL) /*!< BMS (Bit 30) */
+#define FLASH_SR_BMS_Msk (0x40000000UL) /*!< BMS (Bitfield-Mask: 0x01) */
+#define FLASH_SR_OPE_Pos (10UL) /*!< OPE (Bit 10) */
+#define FLASH_SR_OPE_Msk (0x400UL) /*!< OPE (Bitfield-Mask: 0x01) */
+#define FLASH_SR_PES_Pos (9UL) /*!< PES (Bit 9) */
+#define FLASH_SR_PES_Msk (0x200UL) /*!< PES (Bitfield-Mask: 0x01) */
+#define FLASH_SR_PGE_Pos (8UL) /*!< PGE (Bit 8) */
+#define FLASH_SR_PGE_Msk (0x100UL) /*!< PGE (Bitfield-Mask: 0x01) */
+#define FLASH_SR_BM_Pos (7UL) /*!< BM (Bit 7) */
+#define FLASH_SR_BM_Msk (0x80UL) /*!< BM (Bitfield-Mask: 0x01) */
+#define FLASH_SR_WM_Pos (6UL) /*!< WM (Bit 6) */
+#define FLASH_SR_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */
+#define FLASH_SR_DBC_Pos (5UL) /*!< DBC (Bit 5) */
+#define FLASH_SR_DBC_Msk (0x20UL) /*!< DBC (Bitfield-Mask: 0x01) */
+#define FLASH_SR_SBC_Pos (4UL) /*!< SBC (Bit 4) */
+#define FLASH_SR_SBC_Msk (0x10UL) /*!< SBC (Bitfield-Mask: 0x01) */
+#define FLASH_SR_BSY_Pos (3UL) /*!< BSY (Bit 3) */
+#define FLASH_SR_BSY_Msk (0x8UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define FLASH_SR_IOS_Pos (2UL) /*!< IOS (Bit 2) */
+#define FLASH_SR_IOS_Msk (0x4UL) /*!< IOS (Bitfield-Mask: 0x01) */
+#define FLASH_SR_WPS_Pos (1UL) /*!< WPS (Bit 1) */
+#define FLASH_SR_WPS_Msk (0x2UL) /*!< WPS (Bitfield-Mask: 0x01) */
+#define FLASH_SR_OES_Pos (0UL) /*!< OES (Bit 0) */
+#define FLASH_SR_OES_Msk (0x1UL) /*!< OES (Bitfield-Mask: 0x01) */
+/* ========================================================= PDR0 ========================================================== */
+#define FLASH_PDR0_PD0_Pos (0UL) /*!< PD0 (Bit 0) */
+#define FLASH_PDR0_PD0_Msk (0xffffffffUL) /*!< PD0 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= PDR1 ========================================================== */
+#define FLASH_PDR1_PD1_Pos (0UL) /*!< PD1 (Bit 0) */
+#define FLASH_PDR1_PD1_Msk (0xffffffffUL) /*!< PD1 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== PAR ========================================================== */
+#define FLASH_PAR_EM_Pos (20UL) /*!< EM (Bit 20) */
+#define FLASH_PAR_EM_Msk (0x300000UL) /*!< EM (Bitfield-Mask: 0x03) */
+#define FLASH_PAR_PA_Pos (0UL) /*!< PA (Bit 0) */
+#define FLASH_PAR_PA_Msk (0x7ffffUL) /*!< PA (Bitfield-Mask: 0x7ffff) */
+/* ========================================================== KR =========================================================== */
+#define FLASH_KR_PLK_Pos (16UL) /*!< PLK (Bit 16) */
+#define FLASH_KR_PLK_Msk (0x10000UL) /*!< PLK (Bitfield-Mask: 0x01) */
+#define FLASH_KR_KEY_Pos (0UL) /*!< KEY (Bit 0) */
+#define FLASH_KR_KEY_Msk (0xffffUL) /*!< KEY (Bitfield-Mask: 0xffff) */
+/* ========================================================== RPR ========================================================== */
+#define FLASH_RPR_RPLV_Pos (0UL) /*!< RPLV (Bit 0) */
+#define FLASH_RPR_RPLV_Msk (0xffUL) /*!< RPLV (Bitfield-Mask: 0xff) */
+/* ========================================================== WPR ========================================================== */
+#define FLASH_WPR_WRPC_Pos (0UL) /*!< WRPC (Bit 0) */
+#define FLASH_WPR_WRPC_Msk (0xffffffffUL) /*!< WRPC (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== TR =========================================================== */
+#define FLASH_TR_APG_Pos (12UL) /*!< APG (Bit 12) */
+#define FLASH_TR_APG_Msk (0x3ff000UL) /*!< APG (Bitfield-Mask: 0x3ff) */
+#define FLASH_TR_UNIT_Pos (4UL) /*!< UNIT (Bit 4) */
+#define FLASH_TR_UNIT_Msk (0xff0UL) /*!< UNIT (Bitfield-Mask: 0xff) */
+#define FLASH_TR_RC_Pos (0UL) /*!< RC (Bit 0) */
+#define FLASH_TR_RC_Msk (0xfUL) /*!< RC (Bitfield-Mask: 0x0f) */
+/* ========================================================= OPDR ========================================================== */
+#define FLASH_OPDR_MAP_Pos (28UL) /*!< MAP (Bit 28) */
+#define FLASH_OPDR_MAP_Msk (0xf0000000UL) /*!< MAP (Bitfield-Mask: 0x0f) */
+#define FLASH_OPDR_BMD_Pos (24UL) /*!< BMD (Bit 24) */
+#define FLASH_OPDR_BMD_Msk (0xf000000UL) /*!< BMD (Bitfield-Mask: 0x0f) */
+#define FLASH_OPDR_WWEN_Pos (20UL) /*!< WWEN (Bit 20) */
+#define FLASH_OPDR_WWEN_Msk (0xf00000UL) /*!< WWEN (Bitfield-Mask: 0x0f) */
+#define FLASH_OPDR_IWEN_Pos (16UL) /*!< IWEN (Bit 16) */
+#define FLASH_OPDR_IWEN_Msk (0xf0000UL) /*!< IWEN (Bitfield-Mask: 0x0f) */
+#define FLASH_OPDR_EBP_Pos (12UL) /*!< EBP (Bit 12) */
+#define FLASH_OPDR_EBP_Msk (0xf000UL) /*!< EBP (Bitfield-Mask: 0x0f) */
+#define FLASH_OPDR_BORLV_Pos (8UL) /*!< BORLV (Bit 8) */
+#define FLASH_OPDR_BORLV_Msk (0x300UL) /*!< BORLV (Bitfield-Mask: 0x03) */
+#define FLASH_OPDR_BSEL_Pos (4UL) /*!< BSEL (Bit 4) */
+#define FLASH_OPDR_BSEL_Msk (0x70UL) /*!< BSEL (Bitfield-Mask: 0x07) */
+#define FLASH_OPDR_BLK_Pos (0UL) /*!< BLK (Bit 0) */
+#define FLASH_OPDR_BLK_Msk (0xfUL) /*!< BLK (Bitfield-Mask: 0x0f) */
+/* ========================================================= EAR0 ========================================================== */
+#define FLASH_EAR0_EAD1_Pos (0UL) /*!< EAD1 (Bit 0) */
+#define FLASH_EAR0_EAD1_Msk (0xffffffffUL) /*!< EAD1 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= EAR1 ========================================================== */
+#define FLASH_EAR1_EADn_Pos (0UL) /*!< EADn (Bit 0) */
+#define FLASH_EAR1_EADn_Msk (0xffffffffUL) /*!< EADn (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA0_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA0_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA0_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA0_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA0_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA0_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA0_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA0_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA0_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA0_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA0_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA0_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA0_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA0_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA0_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA0_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA0_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA0_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA0_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA0_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA0_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA0_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA0_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA0_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA0_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA0_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA0_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA0_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA0_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA0_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA0_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA0_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA0_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA0_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA0_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA0_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA0_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA0_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA0_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA0_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA0_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA0_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA1_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA1_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA1_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA1_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA1_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA1_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA1_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA1_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA1_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA1_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA1_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA1_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA1_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA1_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA1_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA1_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA1_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA1_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA1_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA1_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA1_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA1_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA1_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA1_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA1_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA1_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA1_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA1_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA1_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA1_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA1_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA1_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA1_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA1_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA1_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA1_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA1_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA1_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA1_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA1_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA1_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA1_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA2_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA2_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA2_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA2_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA2_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA2_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA2_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA2_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA2_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA2_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA2_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA2_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA2_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA2_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA2_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA2_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA2_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA2_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA2_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA2_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA2_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA2_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA2_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA2_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA2_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA2_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA2_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA2_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA2_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA2_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA2_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA2_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA2_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA2_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA2_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA2_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA2_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA2_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA2_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA2_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA2_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA2_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA3_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA3_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA3_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA3_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA3_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA3_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA3_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA3_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA3_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA3_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA3_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA3_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA3_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA3_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA3_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA3_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA3_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA3_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA3_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA3_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA3_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA3_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA3_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA3_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA3_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA3_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA3_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA3_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA3_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA3_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA3_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA3_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA3_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA3_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA3_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA3_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA3_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA3_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA3_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA3_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA3_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA3_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA4_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA4_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA4_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA4_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA4_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA4_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA4_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA4_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA4_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA4_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA4_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA4_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA4_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA4_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA4_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA4_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA4_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA4_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA4_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA4_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA4_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA4_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA4_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA4_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA4_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA4_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA4_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA4_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA4_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA4_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA4_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA4_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA4_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA4_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA4_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA4_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA4_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA4_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA4_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA4_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA4_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA4_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA5 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA5_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA5_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA5_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA5_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA5_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA5_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA5_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA5_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA5_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA5_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA5_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA5_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA5_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA5_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA5_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA5_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA5_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA5_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA5_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA5_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA5_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA5_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA5_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA5_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA5_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA5_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA5_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA5_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA5_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA5_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA5_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA5_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA5_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA5_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA5_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA5_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA5_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA5_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA5_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA5_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA5_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA5_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC0_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC0_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC0_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC0_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC0_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC0_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC0_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC0_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC0_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC0_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC0_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC0_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC0_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC0_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC0_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC0_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC0_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC0_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC0_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC0_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC0_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC0_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC0_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC0_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC0_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC0_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC0_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC0_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC0_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC0_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC0_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC0_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC0_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC0_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC0_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC0_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC0_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC0_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC0_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC0_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC0_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC0_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC0_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC1_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC1_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC1_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC1_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC1_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC1_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC1_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC1_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC1_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC1_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC1_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC1_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC1_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC1_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC1_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC1_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC1_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC1_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC1_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC1_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC1_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC1_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC1_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC1_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC1_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC1_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC1_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC1_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC1_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC1_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC1_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC1_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC1_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC1_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC1_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC1_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC1_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC1_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC1_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC1_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC1_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC1_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC1_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC1_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC2_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC2_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC2_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC2_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC2_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC2_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC2_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC2_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC2_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC2_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC2_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC2_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC2_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC2_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC2_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC2_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC2_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC2_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC2_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC2_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC2_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC2_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC2_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC2_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC2_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC2_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC2_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC2_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC2_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC2_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC2_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC2_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC2_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC2_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC2_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC2_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC2_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC2_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC2_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC2_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC2_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC2_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC2_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC2_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC3_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC3_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC3_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC3_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC3_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC3_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC3_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC3_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC3_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC3_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC3_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC3_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC3_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC3_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC3_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC3_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC3_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC3_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC3_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC3_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC3_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC3_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC3_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC3_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC3_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC3_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC3_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC3_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC3_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC3_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC3_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC3_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC3_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC3_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC3_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC3_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC3_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC3_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC3_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC3_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC3_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC3_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC3_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC3_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC4_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC4_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC4_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC4_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC4_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC4_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC4_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC4_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC4_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC4_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC4_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC4_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC4_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC4_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC4_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC4_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC4_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC4_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC4_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC4_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC4_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC4_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC4_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC4_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC4_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC4_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC4_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC4_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC4_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC4_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC4_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC4_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC4_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC4_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC4_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC4_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC4_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC4_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC4_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC4_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC4_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC4_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC4_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC4_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC5 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC5_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC5_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC5_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC5_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC5_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC5_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC5_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC5_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC5_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC5_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC5_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC5_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC5_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC5_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC5_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC5_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC5_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC5_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC5_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC5_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC5_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC5_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC5_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC5_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC5_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC5_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC5_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC5_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC5_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC5_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC5_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC5_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC5_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC5_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC5_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC5_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC5_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC5_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC5_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC5_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC5_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC5_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC5_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC5_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC6 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC6_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC6_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC6_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC6_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC6_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC6_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC6_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC6_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC6_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC6_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC6_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC6_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC6_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC6_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC6_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC6_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC6_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC6_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC6_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC6_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC6_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC6_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC6_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC6_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC6_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC6_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC6_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC6_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC6_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC6_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC6_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC6_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC6_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC6_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC6_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC6_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC6_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC6_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC6_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC6_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC6_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC6_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC6_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC6_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC7 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC7_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC7_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC7_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC7_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC7_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC7_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC7_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC7_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC7_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC7_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC7_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC7_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC7_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC7_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC7_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC7_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC7_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC7_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC7_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC7_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC7_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC7_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC7_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC7_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC7_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC7_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC7_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC7_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC7_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC7_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC7_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC7_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC7_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC7_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC7_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC7_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC7_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC7_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC7_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC7_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC7_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC7_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC7_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC7_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC8 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC8_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC8_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC8_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC8_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC8_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC8_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC8_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC8_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC8_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC8_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC8_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC8_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC8_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC8_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC8_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC8_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC8_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC8_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC8_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC8_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC8_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC8_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC8_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC8_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC8_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC8_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC8_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC8_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC8_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC8_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC8_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC8_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC8_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC8_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC8_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC8_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC8_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC8_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC8_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC8_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC8_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC8_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC8_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC8_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CORDIC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CSR0 ========================================================== */
+#define CORDIC_CSR0_RRDY_Pos (31UL) /*!< RRDY (Bit 31) */
+#define CORDIC_CSR0_RRDY_Msk (0x80000000UL) /*!< RRDY (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_ERR_Pos (30UL) /*!< ERR (Bit 30) */
+#define CORDIC_CSR0_ERR_Msk (0x40000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_RRDYCLR_Pos (29UL) /*!< RRDYCLR (Bit 29) */
+#define CORDIC_CSR0_RRDYCLR_Msk (0x20000000UL) /*!< RRDYCLR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_ERRCLR_Pos (28UL) /*!< ERRCLR (Bit 28) */
+#define CORDIC_CSR0_ERRCLR_Msk (0x10000000UL) /*!< ERRCLR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_ARGSIZE_Pos (22UL) /*!< ARGSIZE (Bit 22) */
+#define CORDIC_CSR0_ARGSIZE_Msk (0x400000UL) /*!< ARGSIZE (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_RESSIZE_Pos (21UL) /*!< RESSIZE (Bit 21) */
+#define CORDIC_CSR0_RESSIZE_Msk (0x200000UL) /*!< RESSIZE (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_NARGS_Pos (20UL) /*!< NARGS (Bit 20) */
+#define CORDIC_CSR0_NARGS_Msk (0x100000UL) /*!< NARGS (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_NRES_Pos (19UL) /*!< NRES (Bit 19) */
+#define CORDIC_CSR0_NRES_Msk (0x80000UL) /*!< NRES (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_ERRIEN_Pos (17UL) /*!< ERRIEN (Bit 17) */
+#define CORDIC_CSR0_ERRIEN_Msk (0x20000UL) /*!< ERRIEN (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_RRDYIEN_Pos (16UL) /*!< RRDYIEN (Bit 16) */
+#define CORDIC_CSR0_RRDYIEN_Msk (0x10000UL) /*!< RRDYIEN (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_SCALE_Pos (8UL) /*!< SCALE (Bit 8) */
+#define CORDIC_CSR0_SCALE_Msk (0x1f00UL) /*!< SCALE (Bitfield-Mask: 0x1f) */
+#define CORDIC_CSR0_FUNC_Pos (0UL) /*!< FUNC (Bit 0) */
+#define CORDIC_CSR0_FUNC_Msk (0xfUL) /*!< FUNC (Bitfield-Mask: 0x0f) */
+/* ========================================================= ARX0 ========================================================== */
+#define CORDIC_ARX0_ARGRESX_Pos (0UL) /*!< ARGRESX (Bit 0) */
+#define CORDIC_ARX0_ARGRESX_Msk (0xffffffffUL) /*!< ARGRESX (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ARY0 ========================================================== */
+#define CORDIC_ARY0_ARGRESY_Pos (0UL) /*!< ARGRESY (Bit 0) */
+#define CORDIC_ARY0_ARGRESY_Msk (0xffffffffUL) /*!< ARGRESY (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CSR1 ========================================================== */
+#define CORDIC_CSR1_RRDY_Pos (31UL) /*!< RRDY (Bit 31) */
+#define CORDIC_CSR1_RRDY_Msk (0x80000000UL) /*!< RRDY (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_ERR_Pos (30UL) /*!< ERR (Bit 30) */
+#define CORDIC_CSR1_ERR_Msk (0x40000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_RRDYCLR_Pos (29UL) /*!< RRDYCLR (Bit 29) */
+#define CORDIC_CSR1_RRDYCLR_Msk (0x20000000UL) /*!< RRDYCLR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_ERRCLR_Pos (28UL) /*!< ERRCLR (Bit 28) */
+#define CORDIC_CSR1_ERRCLR_Msk (0x10000000UL) /*!< ERRCLR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_ARGSIZE_Pos (22UL) /*!< ARGSIZE (Bit 22) */
+#define CORDIC_CSR1_ARGSIZE_Msk (0x400000UL) /*!< ARGSIZE (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_RESSIZE_Pos (21UL) /*!< RESSIZE (Bit 21) */
+#define CORDIC_CSR1_RESSIZE_Msk (0x200000UL) /*!< RESSIZE (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_NARGS_Pos (20UL) /*!< NARGS (Bit 20) */
+#define CORDIC_CSR1_NARGS_Msk (0x100000UL) /*!< NARGS (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_NRES_Pos (19UL) /*!< NRES (Bit 19) */
+#define CORDIC_CSR1_NRES_Msk (0x80000UL) /*!< NRES (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_ERRIEN_Pos (17UL) /*!< ERRIEN (Bit 17) */
+#define CORDIC_CSR1_ERRIEN_Msk (0x20000UL) /*!< ERRIEN (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_RRDYIEN_Pos (16UL) /*!< RRDYIEN (Bit 16) */
+#define CORDIC_CSR1_RRDYIEN_Msk (0x10000UL) /*!< RRDYIEN (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_SCALE_Pos (8UL) /*!< SCALE (Bit 8) */
+#define CORDIC_CSR1_SCALE_Msk (0x1f00UL) /*!< SCALE (Bitfield-Mask: 0x1f) */
+#define CORDIC_CSR1_FUNC_Pos (0UL) /*!< FUNC (Bit 0) */
+#define CORDIC_CSR1_FUNC_Msk (0xfUL) /*!< FUNC (Bitfield-Mask: 0x0f) */
+/* ========================================================= ARX1 ========================================================== */
+#define CORDIC_ARX1_ARGRESX_Pos (0UL) /*!< ARGRESX (Bit 0) */
+#define CORDIC_ARX1_ARGRESX_Msk (0xffffffffUL) /*!< ARGRESX (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ARY1 ========================================================== */
+#define CORDIC_ARY1_ARGRESY_Pos (0UL) /*!< ARGRESY (Bit 0) */
+#define CORDIC_ARY1_ARGRESY_Msk (0xffffffffUL) /*!< ARGRESY (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP0_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP0_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP0_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP0_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP0_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP0_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP0_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP0_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP0_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP0_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP0_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP0_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP0_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP0_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP0_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP0_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP0_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP0_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP0_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP0_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP0_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP0_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP0_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP0_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP0_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP0_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP0_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP0_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP1_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP1_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP1_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP1_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP1_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP1_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP1_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP1_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP1_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP1_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP1_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP1_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP1_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP1_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP1_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP1_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP1_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP1_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP1_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP1_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP1_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP1_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP1_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP1_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP1_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP1_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP1_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP1_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP2_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP2_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP2_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP2_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP2_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP2_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP2_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP2_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP2_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP2_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP2_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP2_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP2_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP2_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP2_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP2_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP2_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP2_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP2_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP2_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP2_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP2_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP2_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP2_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP2_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP2_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP2_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP2_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP3_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP3_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP3_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP3_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP3_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP3_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP3_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP3_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP3_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP3_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP3_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP3_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP3_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP3_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP3_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP3_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP3_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP3_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP3_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP3_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP3_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP3_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP3_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP3_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP3_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP3_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP3_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP3_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP4_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP4_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP4_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP4_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP4_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP4_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP4_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP4_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP4_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP4_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP4_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP4_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP4_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP4_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP4_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP4_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP4_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP4_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP4_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP4_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP4_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP4_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP4_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP4_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP4_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP4_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP4_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP4_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP5 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP5_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP5_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP5_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP5_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP5_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP5_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP5_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP5_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP5_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP5_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP5_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP5_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP5_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP5_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP5_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP5_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP5_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP5_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP5_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP5_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP5_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP5_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP5_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP5_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP5_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP5_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP5_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP5_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP6 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP6_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP6_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP6_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP6_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP6_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP6_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP6_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP6_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP6_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP6_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP6_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP6_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP6_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP6_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP6_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP6_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP6_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP6_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP6_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP6_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP6_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP6_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP6_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP6_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP6_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP6_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP6_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP6_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP7 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP7_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP7_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP7_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP7_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP7_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP7_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP7_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP7_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP7_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP7_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP7_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP7_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP7_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP7_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP7_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP7_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP7_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP7_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP7_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP7_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP7_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP7_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP7_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP7_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP7_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP7_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP7_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP7_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP8 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP8_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP8_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP8_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP8_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP8_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP8_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP8_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP8_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP8_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP8_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP8_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP8_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP8_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP8_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP8_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP8_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP8_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP8_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP8_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP8_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP8_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP8_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP8_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP8_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP8_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP8_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP8_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP8_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CAN0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CTRL ========================================================== */
+#define CAN0_CTRL_AFWL_Pos (28UL) /*!< AFWL (Bit 28) */
+#define CAN0_CTRL_AFWL_Msk (0xf0000000UL) /*!< AFWL (Bitfield-Mask: 0x0f) */
+#define CAN0_CTRL_EWL_Pos (24UL) /*!< EWL (Bit 24) */
+#define CAN0_CTRL_EWL_Msk (0xf000000UL) /*!< EWL (Bitfield-Mask: 0x0f) */
+#define CAN0_CTRL_EREL_Pos (22UL) /*!< EREL (Bit 22) */
+#define CAN0_CTRL_EREL_Msk (0x400000UL) /*!< EREL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_SREL_Pos (21UL) /*!< SREL (Bit 21) */
+#define CAN0_CTRL_SREL_Msk (0x200000UL) /*!< SREL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_RREL_Pos (20UL) /*!< RREL (Bit 20) */
+#define CAN0_CTRL_RREL_Msk (0x100000UL) /*!< RREL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_FD_EN_Pos (18UL) /*!< FD_EN (Bit 18) */
+#define CAN0_CTRL_FD_EN_Msk (0x40000UL) /*!< FD_EN (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_FD_ISO_Pos (17UL) /*!< FD_ISO (Bit 17) */
+#define CAN0_CTRL_FD_ISO_Msk (0x20000UL) /*!< FD_ISO (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TSNEXT_Pos (16UL) /*!< TSNEXT (Bit 16) */
+#define CAN0_CTRL_TSNEXT_Msk (0x10000UL) /*!< TSNEXT (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_PEDT_Pos (15UL) /*!< PEDT (Bit 15) */
+#define CAN0_CTRL_PEDT_Msk (0x8000UL) /*!< PEDT (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_MUXSEL_Pos (13UL) /*!< MUXSEL (Bit 13) */
+#define CAN0_CTRL_MUXSEL_Msk (0x2000UL) /*!< MUXSEL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TBSEL_Pos (12UL) /*!< TBSEL (Bit 12) */
+#define CAN0_CTRL_TBSEL_Msk (0x1000UL) /*!< TBSEL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_LOM_Pos (11UL) /*!< LOM (Bit 11) */
+#define CAN0_CTRL_LOM_Msk (0x800UL) /*!< LOM (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TPE_Pos (9UL) /*!< TPE (Bit 9) */
+#define CAN0_CTRL_TPE_Msk (0x200UL) /*!< TPE (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TPA_Pos (8UL) /*!< TPA (Bit 8) */
+#define CAN0_CTRL_TPA_Msk (0x100UL) /*!< TPA (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TSONE_Pos (7UL) /*!< TSONE (Bit 7) */
+#define CAN0_CTRL_TSONE_Msk (0x80UL) /*!< TSONE (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TSALL_Pos (6UL) /*!< TSALL (Bit 6) */
+#define CAN0_CTRL_TSALL_Msk (0x40UL) /*!< TSALL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TSA_Pos (5UL) /*!< TSA (Bit 5) */
+#define CAN0_CTRL_TSA_Msk (0x20UL) /*!< TSA (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_RESET_Pos (4UL) /*!< RESET (Bit 4) */
+#define CAN0_CTRL_RESET_Msk (0x10UL) /*!< RESET (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_LBME_Pos (3UL) /*!< LBME (Bit 3) */
+#define CAN0_CTRL_LBME_Msk (0x8UL) /*!< LBME (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_LBMI_Pos (2UL) /*!< LBMI (Bit 2) */
+#define CAN0_CTRL_LBMI_Msk (0x4UL) /*!< LBMI (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TPSS_Pos (1UL) /*!< TPSS (Bit 1) */
+#define CAN0_CTRL_TPSS_Msk (0x2UL) /*!< TPSS (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TSSS_Pos (0UL) /*!< TSSS (Bit 0) */
+#define CAN0_CTRL_TSSS_Msk (0x1UL) /*!< TSSS (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define CAN0_STATUS_SAFWL_Pos (28UL) /*!< SAFWL (Bit 28) */
+#define CAN0_STATUS_SAFWL_Msk (0xf0000000UL) /*!< SAFWL (Bitfield-Mask: 0x0f) */
+#define CAN0_STATUS_EAFWL_Pos (24UL) /*!< EAFWL (Bit 24) */
+#define CAN0_STATUS_EAFWL_Msk (0xf000000UL) /*!< EAFWL (Bitfield-Mask: 0x0f) */
+#define CAN0_STATUS_AEWL_Pos (20UL) /*!< AEWL (Bit 20) */
+#define CAN0_STATUS_AEWL_Msk (0xf00000UL) /*!< AEWL (Bitfield-Mask: 0x0f) */
+#define CAN0_STATUS_ROV_Pos (18UL) /*!< ROV (Bit 18) */
+#define CAN0_STATUS_ROV_Msk (0x40000UL) /*!< ROV (Bitfield-Mask: 0x01) */
+#define CAN0_STATUS_RSTAT_Pos (16UL) /*!< RSTAT (Bit 16) */
+#define CAN0_STATUS_RSTAT_Msk (0x30000UL) /*!< RSTAT (Bitfield-Mask: 0x03) */
+#define CAN0_STATUS_SOV_Pos (15UL) /*!< SOV (Bit 15) */
+#define CAN0_STATUS_SOV_Msk (0x8000UL) /*!< SOV (Bitfield-Mask: 0x01) */
+#define CAN0_STATUS_SSTAT_Pos (13UL) /*!< SSTAT (Bit 13) */
+#define CAN0_STATUS_SSTAT_Msk (0x6000UL) /*!< SSTAT (Bitfield-Mask: 0x03) */
+#define CAN0_STATUS_TSSTAT_Pos (8UL) /*!< TSSTAT (Bit 8) */
+#define CAN0_STATUS_TSSTAT_Msk (0x1f00UL) /*!< TSSTAT (Bitfield-Mask: 0x1f) */
+#define CAN0_STATUS_EOV_Pos (7UL) /*!< EOV (Bit 7) */
+#define CAN0_STATUS_EOV_Msk (0x80UL) /*!< EOV (Bitfield-Mask: 0x01) */
+#define CAN0_STATUS_ESTAT_Pos (5UL) /*!< ESTAT (Bit 5) */
+#define CAN0_STATUS_ESTAT_Msk (0x60UL) /*!< ESTAT (Bitfield-Mask: 0x03) */
+#define CAN0_STATUS_RACTIVE_Pos (2UL) /*!< RACTIVE (Bit 2) */
+#define CAN0_STATUS_RACTIVE_Msk (0x4UL) /*!< RACTIVE (Bitfield-Mask: 0x01) */
+#define CAN0_STATUS_TACTIVE_Pos (1UL) /*!< TACTIVE (Bit 1) */
+#define CAN0_STATUS_TACTIVE_Msk (0x2UL) /*!< TACTIVE (Bitfield-Mask: 0x01) */
+#define CAN0_STATUS_BUSOFF_Pos (0UL) /*!< BUSOFF (Bit 0) */
+#define CAN0_STATUS_BUSOFF_Msk (0x1UL) /*!< BUSOFF (Bitfield-Mask: 0x01) */
+/* ======================================================== INTREN ========================================================= */
+#define CAN0_INTREN_TEIE_Pos (31UL) /*!< TEIE (Bit 31) */
+#define CAN0_INTREN_TEIE_Msk (0x80000000UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_TAEIE_Pos (30UL) /*!< TAEIE (Bit 30) */
+#define CAN0_INTREN_TAEIE_Msk (0x40000000UL) /*!< TAEIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_PMIE_Pos (29UL) /*!< PMIE (Bit 29) */
+#define CAN0_INTREN_PMIE_Msk (0x20000000UL) /*!< PMIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_TSCIE_Pos (28UL) /*!< TSCIE (Bit 28) */
+#define CAN0_INTREN_TSCIE_Msk (0x10000000UL) /*!< TSCIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_RTOIE_Pos (27UL) /*!< RTOIE (Bit 27) */
+#define CAN0_INTREN_RTOIE_Msk (0x8000000UL) /*!< RTOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_STOIE_Pos (26UL) /*!< STOIE (Bit 26) */
+#define CAN0_INTREN_STOIE_Msk (0x4000000UL) /*!< STOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_ETOIE_Pos (25UL) /*!< ETOIE (Bit 25) */
+#define CAN0_INTREN_ETOIE_Msk (0x2000000UL) /*!< ETOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_CTOIE_Pos (24UL) /*!< CTOIE (Bit 24) */
+#define CAN0_INTREN_CTOIE_Msk (0x1000000UL) /*!< CTOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_SOIE_Pos (23UL) /*!< SOIE (Bit 23) */
+#define CAN0_INTREN_SOIE_Msk (0x800000UL) /*!< SOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_SFIE_Pos (22UL) /*!< SFIE (Bit 22) */
+#define CAN0_INTREN_SFIE_Msk (0x400000UL) /*!< SFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_SAFIE_Pos (21UL) /*!< SAFIE (Bit 21) */
+#define CAN0_INTREN_SAFIE_Msk (0x200000UL) /*!< SAFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_EOIE_Pos (20UL) /*!< EOIE (Bit 20) */
+#define CAN0_INTREN_EOIE_Msk (0x100000UL) /*!< EOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_EFIE_Pos (19UL) /*!< EFIE (Bit 19) */
+#define CAN0_INTREN_EFIE_Msk (0x80000UL) /*!< EFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_EAFIE_Pos (18UL) /*!< EAFIE (Bit 18) */
+#define CAN0_INTREN_EAFIE_Msk (0x40000UL) /*!< EAFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_AIE_Pos (17UL) /*!< AIE (Bit 17) */
+#define CAN0_INTREN_AIE_Msk (0x20000UL) /*!< AIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_SRIE_Pos (13UL) /*!< SRIE (Bit 13) */
+#define CAN0_INTREN_SRIE_Msk (0x2000UL) /*!< SRIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_ERIE_Pos (12UL) /*!< ERIE (Bit 12) */
+#define CAN0_INTREN_ERIE_Msk (0x1000UL) /*!< ERIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_ECIE_Pos (11UL) /*!< ECIE (Bit 11) */
+#define CAN0_INTREN_ECIE_Msk (0x800UL) /*!< ECIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */
+#define CAN0_INTREN_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_ALIE_Pos (9UL) /*!< ALIE (Bit 9) */
+#define CAN0_INTREN_ALIE_Msk (0x200UL) /*!< ALIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */
+#define CAN0_INTREN_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_RIE_Pos (7UL) /*!< RIE (Bit 7) */
+#define CAN0_INTREN_RIE_Msk (0x80UL) /*!< RIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_ROIE_Pos (6UL) /*!< ROIE (Bit 6) */
+#define CAN0_INTREN_ROIE_Msk (0x40UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_RFIE_Pos (5UL) /*!< RFIE (Bit 5) */
+#define CAN0_INTREN_RFIE_Msk (0x20UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_RAFIE_Pos (4UL) /*!< RAFIE (Bit 4) */
+#define CAN0_INTREN_RAFIE_Msk (0x10UL) /*!< RAFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_TPIE_Pos (3UL) /*!< TPIE (Bit 3) */
+#define CAN0_INTREN_TPIE_Msk (0x8UL) /*!< TPIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_TSIE_Pos (2UL) /*!< TSIE (Bit 2) */
+#define CAN0_INTREN_TSIE_Msk (0x4UL) /*!< TSIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_EIE_Pos (1UL) /*!< EIE (Bit 1) */
+#define CAN0_INTREN_EIE_Msk (0x2UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_TSFF_Pos (0UL) /*!< TSFF (Bit 0) */
+#define CAN0_INTREN_TSFF_Msk (0x1UL) /*!< TSFF (Bitfield-Mask: 0x01) */
+/* ======================================================== INTRST ========================================================= */
+#define CAN0_INTRST_TEIF_Pos (31UL) /*!< TEIF (Bit 31) */
+#define CAN0_INTRST_TEIF_Msk (0x80000000UL) /*!< TEIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_TAEIF_Pos (30UL) /*!< TAEIF (Bit 30) */
+#define CAN0_INTRST_TAEIF_Msk (0x40000000UL) /*!< TAEIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_PMIF_Pos (29UL) /*!< PMIF (Bit 29) */
+#define CAN0_INTRST_PMIF_Msk (0x20000000UL) /*!< PMIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_TSCIF_Pos (28UL) /*!< TSCIF (Bit 28) */
+#define CAN0_INTRST_TSCIF_Msk (0x10000000UL) /*!< TSCIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_RTOIF_Pos (27UL) /*!< RTOIF (Bit 27) */
+#define CAN0_INTRST_RTOIF_Msk (0x8000000UL) /*!< RTOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_STOIF_Pos (26UL) /*!< STOIF (Bit 26) */
+#define CAN0_INTRST_STOIF_Msk (0x4000000UL) /*!< STOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_ETOIF_Pos (25UL) /*!< ETOIF (Bit 25) */
+#define CAN0_INTRST_ETOIF_Msk (0x2000000UL) /*!< ETOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_CTOIF_Pos (24UL) /*!< CTOIF (Bit 24) */
+#define CAN0_INTRST_CTOIF_Msk (0x1000000UL) /*!< CTOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_SOIF_Pos (23UL) /*!< SOIF (Bit 23) */
+#define CAN0_INTRST_SOIF_Msk (0x800000UL) /*!< SOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_SFIF_Pos (22UL) /*!< SFIF (Bit 22) */
+#define CAN0_INTRST_SFIF_Msk (0x400000UL) /*!< SFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_SAFIF_Pos (21UL) /*!< SAFIF (Bit 21) */
+#define CAN0_INTRST_SAFIF_Msk (0x200000UL) /*!< SAFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EOIF_Pos (20UL) /*!< EOIF (Bit 20) */
+#define CAN0_INTRST_EOIF_Msk (0x100000UL) /*!< EOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EFIF_Pos (19UL) /*!< EFIF (Bit 19) */
+#define CAN0_INTRST_EFIF_Msk (0x80000UL) /*!< EFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EAFIF_Pos (18UL) /*!< EAFIF (Bit 18) */
+#define CAN0_INTRST_EAFIF_Msk (0x40000UL) /*!< EAFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EWARN_Pos (17UL) /*!< EWARN (Bit 17) */
+#define CAN0_INTRST_EWARN_Msk (0x20000UL) /*!< EWARN (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EPASS_Pos (16UL) /*!< EPASS (Bit 16) */
+#define CAN0_INTRST_EPASS_Msk (0x10000UL) /*!< EPASS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_SRIF_Pos (13UL) /*!< SRIF (Bit 13) */
+#define CAN0_INTRST_SRIF_Msk (0x2000UL) /*!< SRIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_ERIF_Pos (12UL) /*!< ERIF (Bit 12) */
+#define CAN0_INTRST_ERIF_Msk (0x1000UL) /*!< ERIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_ECIF_Pos (11UL) /*!< ECIF (Bit 11) */
+#define CAN0_INTRST_ECIF_Msk (0x800UL) /*!< ECIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EPIF_Pos (10UL) /*!< EPIF (Bit 10) */
+#define CAN0_INTRST_EPIF_Msk (0x400UL) /*!< EPIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_ALIF_Pos (9UL) /*!< ALIF (Bit 9) */
+#define CAN0_INTRST_ALIF_Msk (0x200UL) /*!< ALIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_BEIF_Pos (8UL) /*!< BEIF (Bit 8) */
+#define CAN0_INTRST_BEIF_Msk (0x100UL) /*!< BEIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_RIF_Pos (7UL) /*!< RIF (Bit 7) */
+#define CAN0_INTRST_RIF_Msk (0x80UL) /*!< RIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_ROIF_Pos (6UL) /*!< ROIF (Bit 6) */
+#define CAN0_INTRST_ROIF_Msk (0x40UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_RFIF_Pos (5UL) /*!< RFIF (Bit 5) */
+#define CAN0_INTRST_RFIF_Msk (0x20UL) /*!< RFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_RAFIF_Pos (4UL) /*!< RAFIF (Bit 4) */
+#define CAN0_INTRST_RAFIF_Msk (0x10UL) /*!< RAFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_TPIF_Pos (3UL) /*!< TPIF (Bit 3) */
+#define CAN0_INTRST_TPIF_Msk (0x8UL) /*!< TPIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_TSIF_Pos (2UL) /*!< TSIF (Bit 2) */
+#define CAN0_INTRST_TSIF_Msk (0x4UL) /*!< TSIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EIF_Pos (1UL) /*!< EIF (Bit 1) */
+#define CAN0_INTRST_EIF_Msk (0x2UL) /*!< EIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_AIF_Pos (0UL) /*!< AIF (Bit 0) */
+#define CAN0_INTRST_AIF_Msk (0x1UL) /*!< AIF (Bitfield-Mask: 0x01) */
+/* ======================================================== BITTIME ======================================================== */
+#define CAN0_BITTIME_F_SEG1_Pos (20UL) /*!< F_SEG1 (Bit 20) */
+#define CAN0_BITTIME_F_SEG1_Msk (0xf00000UL) /*!< F_SEG1 (Bitfield-Mask: 0x0f) */
+#define CAN0_BITTIME_S_SJW_Pos (16UL) /*!< S_SJW (Bit 16) */
+#define CAN0_BITTIME_S_SJW_Msk (0xf0000UL) /*!< S_SJW (Bitfield-Mask: 0x0f) */
+#define CAN0_BITTIME_F_SEG2_Pos (13UL) /*!< F_SEG2 (Bit 13) */
+#define CAN0_BITTIME_F_SEG2_Msk (0xe000UL) /*!< F_SEG2 (Bitfield-Mask: 0x07) */
+#define CAN0_BITTIME_S_SEG2_Pos (8UL) /*!< S_SEG2 (Bit 8) */
+#define CAN0_BITTIME_S_SEG2_Msk (0x1f00UL) /*!< S_SEG2 (Bitfield-Mask: 0x1f) */
+#define CAN0_BITTIME_F_SJW_Pos (6UL) /*!< F_SJW (Bit 6) */
+#define CAN0_BITTIME_F_SJW_Msk (0xc0UL) /*!< F_SJW (Bitfield-Mask: 0x03) */
+#define CAN0_BITTIME_S_SEG1_Pos (0UL) /*!< S_SEG1 (Bit 0) */
+#define CAN0_BITTIME_S_SEG1_Msk (0x3fUL) /*!< S_SEG1 (Bitfield-Mask: 0x3f) */
+/* ========================================================= PRESC ========================================================= */
+#define CAN0_PRESC_TDCEN_Pos (23UL) /*!< TDCEN (Bit 23) */
+#define CAN0_PRESC_TDCEN_Msk (0x800000UL) /*!< TDCEN (Bitfield-Mask: 0x01) */
+#define CAN0_PRESC_SSPOFF_Pos (16UL) /*!< SSPOFF (Bit 16) */
+#define CAN0_PRESC_SSPOFF_Msk (0x1f0000UL) /*!< SSPOFF (Bitfield-Mask: 0x1f) */
+#define CAN0_PRESC_F_PRESC_Pos (8UL) /*!< F_PRESC (Bit 8) */
+#define CAN0_PRESC_F_PRESC_Msk (0xff00UL) /*!< F_PRESC (Bitfield-Mask: 0xff) */
+#define CAN0_PRESC_S_PRESC_Pos (0UL) /*!< S_PRESC (Bit 0) */
+#define CAN0_PRESC_S_PRESC_Msk (0xffUL) /*!< S_PRESC (Bitfield-Mask: 0xff) */
+/* ========================================================= ERRST ========================================================= */
+#define CAN0_ERRST_RECNT_Pos (24UL) /*!< RECNT (Bit 24) */
+#define CAN0_ERRST_RECNT_Msk (0xff000000UL) /*!< RECNT (Bitfield-Mask: 0xff) */
+#define CAN0_ERRST_TECNT_Pos (16UL) /*!< TECNT (Bit 16) */
+#define CAN0_ERRST_TECNT_Msk (0xff0000UL) /*!< TECNT (Bitfield-Mask: 0xff) */
+#define CAN0_ERRST_ECNT_Pos (8UL) /*!< ECNT (Bit 8) */
+#define CAN0_ERRST_ECNT_Msk (0xff00UL) /*!< ECNT (Bitfield-Mask: 0xff) */
+#define CAN0_ERRST_KOER_Pos (5UL) /*!< KOER (Bit 5) */
+#define CAN0_ERRST_KOER_Msk (0xe0UL) /*!< KOER (Bitfield-Mask: 0x07) */
+#define CAN0_ERRST_ALC_Pos (0UL) /*!< ALC (Bit 0) */
+#define CAN0_ERRST_ALC_Msk (0x1fUL) /*!< ALC (Bitfield-Mask: 0x1f) */
+/* ========================================================= PRTST ========================================================= */
+#define CAN0_PRTST_DKOER_Pos (8UL) /*!< DKOER (Bit 8) */
+#define CAN0_PRTST_DKOER_Msk (0x700UL) /*!< DKOER (Bitfield-Mask: 0x07) */
+#define CAN0_PRTST_FDSTS_Pos (4UL) /*!< FDSTS (Bit 4) */
+#define CAN0_PRTST_FDSTS_Msk (0xf0UL) /*!< FDSTS (Bitfield-Mask: 0x0f) */
+#define CAN0_PRTST_NDSTS_Pos (2UL) /*!< NDSTS (Bit 2) */
+#define CAN0_PRTST_NDSTS_Msk (0xcUL) /*!< NDSTS (Bitfield-Mask: 0x03) */
+#define CAN0_PRTST_RBSTS_Pos (0UL) /*!< RBSTS (Bit 0) */
+#define CAN0_PRTST_RBSTS_Msk (0x3UL) /*!< RBSTS (Bitfield-Mask: 0x03) */
+/* ======================================================== INTRLS ========================================================= */
+#define CAN0_INTRLS_TEILS_Pos (31UL) /*!< TEILS (Bit 31) */
+#define CAN0_INTRLS_TEILS_Msk (0x80000000UL) /*!< TEILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_TAEILS_Pos (30UL) /*!< TAEILS (Bit 30) */
+#define CAN0_INTRLS_TAEILS_Msk (0x40000000UL) /*!< TAEILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_PMILS_Pos (29UL) /*!< PMILS (Bit 29) */
+#define CAN0_INTRLS_PMILS_Msk (0x20000000UL) /*!< PMILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_TSCILS_Pos (28UL) /*!< TSCILS (Bit 28) */
+#define CAN0_INTRLS_TSCILS_Msk (0x10000000UL) /*!< TSCILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_RTOILS_Pos (27UL) /*!< RTOILS (Bit 27) */
+#define CAN0_INTRLS_RTOILS_Msk (0x8000000UL) /*!< RTOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_STOILS_Pos (26UL) /*!< STOILS (Bit 26) */
+#define CAN0_INTRLS_STOILS_Msk (0x4000000UL) /*!< STOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_ETOILS_Pos (25UL) /*!< ETOILS (Bit 25) */
+#define CAN0_INTRLS_ETOILS_Msk (0x2000000UL) /*!< ETOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_CTOILS_Pos (24UL) /*!< CTOILS (Bit 24) */
+#define CAN0_INTRLS_CTOILS_Msk (0x1000000UL) /*!< CTOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_SOILS_Pos (23UL) /*!< SOILS (Bit 23) */
+#define CAN0_INTRLS_SOILS_Msk (0x800000UL) /*!< SOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_SFILS_Pos (22UL) /*!< SFILS (Bit 22) */
+#define CAN0_INTRLS_SFILS_Msk (0x400000UL) /*!< SFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_SAFILS_Pos (21UL) /*!< SAFILS (Bit 21) */
+#define CAN0_INTRLS_SAFILS_Msk (0x200000UL) /*!< SAFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_EOILS_Pos (20UL) /*!< EOILS (Bit 20) */
+#define CAN0_INTRLS_EOILS_Msk (0x100000UL) /*!< EOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_EFILS_Pos (19UL) /*!< EFILS (Bit 19) */
+#define CAN0_INTRLS_EFILS_Msk (0x80000UL) /*!< EFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_EAFILS_Pos (18UL) /*!< EAFILS (Bit 18) */
+#define CAN0_INTRLS_EAFILS_Msk (0x40000UL) /*!< EAFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_SRILS_Pos (13UL) /*!< SRILS (Bit 13) */
+#define CAN0_INTRLS_SRILS_Msk (0x2000UL) /*!< SRILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_ERILS_Pos (12UL) /*!< ERILS (Bit 12) */
+#define CAN0_INTRLS_ERILS_Msk (0x1000UL) /*!< ERILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_ECILS_Pos (11UL) /*!< ECILS (Bit 11) */
+#define CAN0_INTRLS_ECILS_Msk (0x800UL) /*!< ECILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_EPILS_Pos (10UL) /*!< EPILS (Bit 10) */
+#define CAN0_INTRLS_EPILS_Msk (0x400UL) /*!< EPILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_ALILS_Pos (9UL) /*!< ALILS (Bit 9) */
+#define CAN0_INTRLS_ALILS_Msk (0x200UL) /*!< ALILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_BEILS_Pos (8UL) /*!< BEILS (Bit 8) */
+#define CAN0_INTRLS_BEILS_Msk (0x100UL) /*!< BEILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_RILS_Pos (7UL) /*!< RILS (Bit 7) */
+#define CAN0_INTRLS_RILS_Msk (0x80UL) /*!< RILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_ROILS_Pos (6UL) /*!< ROILS (Bit 6) */
+#define CAN0_INTRLS_ROILS_Msk (0x40UL) /*!< ROILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_RFILS_Pos (5UL) /*!< RFILS (Bit 5) */
+#define CAN0_INTRLS_RFILS_Msk (0x20UL) /*!< RFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_RAFILS_Pos (4UL) /*!< RAFILS (Bit 4) */
+#define CAN0_INTRLS_RAFILS_Msk (0x10UL) /*!< RAFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_TPILS_Pos (3UL) /*!< TPILS (Bit 3) */
+#define CAN0_INTRLS_TPILS_Msk (0x8UL) /*!< TPILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_TSILS_Pos (2UL) /*!< TSILS (Bit 2) */
+#define CAN0_INTRLS_TSILS_Msk (0x4UL) /*!< TSILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_EILS_Pos (1UL) /*!< EILS (Bit 1) */
+#define CAN0_INTRLS_EILS_Msk (0x2UL) /*!< EILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_AILS_Pos (0UL) /*!< AILS (Bit 0) */
+#define CAN0_INTRLS_AILS_Msk (0x1UL) /*!< AILS (Bitfield-Mask: 0x01) */
+/* ========================================================= GFCR ========================================================== */
+#define CAN0_GFCR_SRFR_Pos (7UL) /*!< SRFR (Bit 7) */
+#define CAN0_GFCR_SRFR_Msk (0x80UL) /*!< SRFR (Bitfield-Mask: 0x01) */
+#define CAN0_GFCR_ERFR_Pos (6UL) /*!< ERFR (Bit 6) */
+#define CAN0_GFCR_ERFR_Msk (0x40UL) /*!< ERFR (Bitfield-Mask: 0x01) */
+#define CAN0_GFCR_PRBM_Pos (1UL) /*!< PRBM (Bit 1) */
+#define CAN0_GFCR_PRBM_Msk (0x2UL) /*!< PRBM (Bitfield-Mask: 0x01) */
+#define CAN0_GFCR_SRBM_Pos (0UL) /*!< SRBM (Bit 0) */
+#define CAN0_GFCR_SRBM_Msk (0x1UL) /*!< SRBM (Bitfield-Mask: 0x01) */
+/* ========================================================= EMCR ========================================================== */
+#define CAN0_EMCR_EIDM_Pos (0UL) /*!< EIDM (Bit 0) */
+#define CAN0_EMCR_EIDM_Msk (0x1fffffffUL) /*!< EIDM (Bitfield-Mask: 0x1fffffff) */
+/* ========================================================= PMST ========================================================== */
+#define CAN0_PMST_PMAS_Pos (4UL) /*!< PMAS (Bit 4) */
+#define CAN0_PMST_PMAS_Msk (0xf0UL) /*!< PMAS (Bitfield-Mask: 0x0f) */
+#define CAN0_PMST_PMBS_Pos (1UL) /*!< PMBS (Bit 1) */
+#define CAN0_PMST_PMBS_Msk (0x6UL) /*!< PMBS (Bitfield-Mask: 0x03) */
+#define CAN0_PMST_PMIS_Pos (0UL) /*!< PMIS (Bit 0) */
+#define CAN0_PMST_PMIS_Msk (0x1UL) /*!< PMIS (Bitfield-Mask: 0x01) */
+/* ========================================================= ACFEN ========================================================= */
+#define CAN0_ACFEN_AE15_Pos (15UL) /*!< AE15 (Bit 15) */
+#define CAN0_ACFEN_AE15_Msk (0x8000UL) /*!< AE15 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE14_Pos (14UL) /*!< AE14 (Bit 14) */
+#define CAN0_ACFEN_AE14_Msk (0x4000UL) /*!< AE14 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE13_Pos (13UL) /*!< AE13 (Bit 13) */
+#define CAN0_ACFEN_AE13_Msk (0x2000UL) /*!< AE13 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE12_Pos (12UL) /*!< AE12 (Bit 12) */
+#define CAN0_ACFEN_AE12_Msk (0x1000UL) /*!< AE12 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE11_Pos (11UL) /*!< AE11 (Bit 11) */
+#define CAN0_ACFEN_AE11_Msk (0x800UL) /*!< AE11 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE10_Pos (10UL) /*!< AE10 (Bit 10) */
+#define CAN0_ACFEN_AE10_Msk (0x400UL) /*!< AE10 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE9_Pos (9UL) /*!< AE9 (Bit 9) */
+#define CAN0_ACFEN_AE9_Msk (0x200UL) /*!< AE9 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE8_Pos (8UL) /*!< AE8 (Bit 8) */
+#define CAN0_ACFEN_AE8_Msk (0x100UL) /*!< AE8 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE7_Pos (7UL) /*!< AE7 (Bit 7) */
+#define CAN0_ACFEN_AE7_Msk (0x80UL) /*!< AE7 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE6_Pos (6UL) /*!< AE6 (Bit 6) */
+#define CAN0_ACFEN_AE6_Msk (0x40UL) /*!< AE6 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE5_Pos (5UL) /*!< AE5 (Bit 5) */
+#define CAN0_ACFEN_AE5_Msk (0x20UL) /*!< AE5 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE4_Pos (4UL) /*!< AE4 (Bit 4) */
+#define CAN0_ACFEN_AE4_Msk (0x10UL) /*!< AE4 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE3_Pos (3UL) /*!< AE3 (Bit 3) */
+#define CAN0_ACFEN_AE3_Msk (0x8UL) /*!< AE3 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE2_Pos (2UL) /*!< AE2 (Bit 2) */
+#define CAN0_ACFEN_AE2_Msk (0x4UL) /*!< AE2 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE1_Pos (1UL) /*!< AE1 (Bit 1) */
+#define CAN0_ACFEN_AE1_Msk (0x2UL) /*!< AE1 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE0_Pos (0UL) /*!< AE0 (Bit 0) */
+#define CAN0_ACFEN_AE0_Msk (0x1UL) /*!< AE0 (Bitfield-Mask: 0x01) */
+/* ======================================================== ACFCTRL ======================================================== */
+#define CAN0_ACFCTRL_SELMASK_Pos (5UL) /*!< SELMASK (Bit 5) */
+#define CAN0_ACFCTRL_SELMASK_Msk (0x20UL) /*!< SELMASK (Bitfield-Mask: 0x01) */
+#define CAN0_ACFCTRL_ACFADR_Pos (0UL) /*!< ACFADR (Bit 0) */
+#define CAN0_ACFCTRL_ACFADR_Msk (0xfUL) /*!< ACFADR (Bitfield-Mask: 0x0f) */
+/* ========================================================== ACF ========================================================== */
+#define CAN0_ACF_AIDEE_Pos (30UL) /*!< AIDEE (Bit 30) */
+#define CAN0_ACF_AIDEE_Msk (0x40000000UL) /*!< AIDEE (Bitfield-Mask: 0x01) */
+#define CAN0_ACF_AIDE_Pos (29UL) /*!< AIDE (Bit 29) */
+#define CAN0_ACF_AIDE_Msk (0x20000000UL) /*!< AIDE (Bitfield-Mask: 0x01) */
+#define CAN0_ACF_ACF_X_Pos (0UL) /*!< ACF_X (Bit 0) */
+#define CAN0_ACF_ACF_X_Msk (0x1fffffffUL) /*!< ACF_X (Bitfield-Mask: 0x1fffffff) */
+/* ========================================================= ACFE ========================================================== */
+#define CAN0_ACFE_ACF_M_Pos (4UL) /*!< ACF_M (Bit 4) */
+#define CAN0_ACFE_ACF_M_Msk (0xf0UL) /*!< ACF_M (Bitfield-Mask: 0x0f) */
+#define CAN0_ACFE_ACF_C_Pos (0UL) /*!< ACF_C (Bit 0) */
+#define CAN0_ACFE_ACF_C_Msk (0xfUL) /*!< ACF_C (Bitfield-Mask: 0x0f) */
+/* ======================================================== RBUFID ========================================================= */
+#define CAN0_RBUFID_RXD_ID_Pos (0UL) /*!< RXD_ID (Bit 0) */
+#define CAN0_RBUFID_RXD_ID_Msk (0xffffffffUL) /*!< RXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== RBUFCR ========================================================= */
+#define CAN0_RBUFCR_RXD_ACF_Pos (24UL) /*!< RXD_ACF (Bit 24) */
+#define CAN0_RBUFCR_RXD_ACF_Msk (0xf000000UL) /*!< RXD_ACF (Bitfield-Mask: 0x0f) */
+#define CAN0_RBUFCR_RXD_TS_Pos (8UL) /*!< RXD_TS (Bit 8) */
+#define CAN0_RBUFCR_RXD_TS_Msk (0xffff00UL) /*!< RXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN0_RBUFCR_RXD_CR_Pos (4UL) /*!< RXD_CR (Bit 4) */
+#define CAN0_RBUFCR_RXD_CR_Msk (0xf0UL) /*!< RXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN0_RBUFCR_RXD_DLC_Pos (0UL) /*!< RXD_DLC (Bit 0) */
+#define CAN0_RBUFCR_RXD_DLC_Msk (0xfUL) /*!< RXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== RBUFDT ========================================================= */
+#define CAN0_RBUFDT_RXD_BYTE3_Pos (24UL) /*!< RXD_BYTE3 (Bit 24) */
+#define CAN0_RBUFDT_RXD_BYTE3_Msk (0xff000000UL) /*!< RXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN0_RBUFDT_RXD_BYTE2_Pos (16UL) /*!< RXD_BYTE2 (Bit 16) */
+#define CAN0_RBUFDT_RXD_BYTE2_Msk (0xff0000UL) /*!< RXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN0_RBUFDT_RXD_BYTE1_Pos (8UL) /*!< RXD_BYTE1 (Bit 8) */
+#define CAN0_RBUFDT_RXD_BYTE1_Msk (0xff00UL) /*!< RXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN0_RBUFDT_RXD_BYTE0_Pos (0UL) /*!< RXD_BYTE0 (Bit 0) */
+#define CAN0_RBUFDT_RXD_BYTE0_Msk (0xffUL) /*!< RXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ======================================================== TBUFID ========================================================= */
+#define CAN0_TBUFID_TXD_ID_Pos (0UL) /*!< TXD_ID (Bit 0) */
+#define CAN0_TBUFID_TXD_ID_Msk (0xffffffffUL) /*!< TXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== TBUFCR ========================================================= */
+#define CAN0_TBUFCR_TXD_ETB_Pos (31UL) /*!< TXD_ETB (Bit 31) */
+#define CAN0_TBUFCR_TXD_ETB_Msk (0x80000000UL) /*!< TXD_ETB (Bitfield-Mask: 0x01) */
+#define CAN0_TBUFCR_TXD_MM_Pos (8UL) /*!< TXD_MM (Bit 8) */
+#define CAN0_TBUFCR_TXD_MM_Msk (0xff00UL) /*!< TXD_MM (Bitfield-Mask: 0xff) */
+#define CAN0_TBUFCR_TXD_CR_Pos (4UL) /*!< TXD_CR (Bit 4) */
+#define CAN0_TBUFCR_TXD_CR_Msk (0xf0UL) /*!< TXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN0_TBUFCR_TXD_DLC_Pos (0UL) /*!< TXD_DLC (Bit 0) */
+#define CAN0_TBUFCR_TXD_DLC_Msk (0xfUL) /*!< TXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== TBUFDT ========================================================= */
+#define CAN0_TBUFDT_TXD_BYTE3_Pos (24UL) /*!< TXD_BYTE3 (Bit 24) */
+#define CAN0_TBUFDT_TXD_BYTE3_Msk (0xff000000UL) /*!< TXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN0_TBUFDT_TXD_BYTE2_Pos (16UL) /*!< TXD_BYTE2 (Bit 16) */
+#define CAN0_TBUFDT_TXD_BYTE2_Msk (0xff0000UL) /*!< TXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN0_TBUFDT_TXD_BYTE1_Pos (8UL) /*!< TXD_BYTE1 (Bit 8) */
+#define CAN0_TBUFDT_TXD_BYTE1_Msk (0xff00UL) /*!< TXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN0_TBUFDT_TXD_BYTE0_Pos (0UL) /*!< TXD_BYTE0 (Bit 0) */
+#define CAN0_TBUFDT_TXD_BYTE0_Msk (0xffUL) /*!< TXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ======================================================== EBUFID ========================================================= */
+#define CAN0_EBUFID_TXD_ID_Pos (0UL) /*!< TXD_ID (Bit 0) */
+#define CAN0_EBUFID_TXD_ID_Msk (0xffffffffUL) /*!< TXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== EBUFDT ========================================================= */
+#define CAN0_EBUFDT_TXD_MM_Pos (24UL) /*!< TXD_MM (Bit 24) */
+#define CAN0_EBUFDT_TXD_MM_Msk (0xff000000UL) /*!< TXD_MM (Bitfield-Mask: 0xff) */
+#define CAN0_EBUFDT_TXD_TS_Pos (8UL) /*!< TXD_TS (Bit 8) */
+#define CAN0_EBUFDT_TXD_TS_Msk (0xffff00UL) /*!< TXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN0_EBUFDT_TXD_CR_Pos (4UL) /*!< TXD_CR (Bit 4) */
+#define CAN0_EBUFDT_TXD_CR_Msk (0xf0UL) /*!< TXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN0_EBUFDT_TXD_DLC_Pos (0UL) /*!< TXD_DLC (Bit 0) */
+#define CAN0_EBUFDT_TXD_DLC_Msk (0xfUL) /*!< TXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== SBUFID ========================================================= */
+#define CAN0_SBUFID_RXD_ID_Pos (0UL) /*!< RXD_ID (Bit 0) */
+#define CAN0_SBUFID_RXD_ID_Msk (0xffffffffUL) /*!< RXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== SBUFCR ========================================================= */
+#define CAN0_SBUFCR_RXD_ACF_Pos (24UL) /*!< RXD_ACF (Bit 24) */
+#define CAN0_SBUFCR_RXD_ACF_Msk (0xf000000UL) /*!< RXD_ACF (Bitfield-Mask: 0x0f) */
+#define CAN0_SBUFCR_RXD_TS_Pos (8UL) /*!< RXD_TS (Bit 8) */
+#define CAN0_SBUFCR_RXD_TS_Msk (0xffff00UL) /*!< RXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN0_SBUFCR_RXD_CR_Pos (4UL) /*!< RXD_CR (Bit 4) */
+#define CAN0_SBUFCR_RXD_CR_Msk (0xf0UL) /*!< RXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN0_SBUFCR_RXD_DLC_Pos (0UL) /*!< RXD_DLC (Bit 0) */
+#define CAN0_SBUFCR_RXD_DLC_Msk (0xfUL) /*!< RXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== SBUFDT ========================================================= */
+#define CAN0_SBUFDT_RXD_BYTE3_Pos (24UL) /*!< RXD_BYTE3 (Bit 24) */
+#define CAN0_SBUFDT_RXD_BYTE3_Msk (0xff000000UL) /*!< RXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN0_SBUFDT_RXD_BYTE2_Pos (16UL) /*!< RXD_BYTE2 (Bit 16) */
+#define CAN0_SBUFDT_RXD_BYTE2_Msk (0xff0000UL) /*!< RXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN0_SBUFDT_RXD_BYTE1_Pos (8UL) /*!< RXD_BYTE1 (Bit 8) */
+#define CAN0_SBUFDT_RXD_BYTE1_Msk (0xff00UL) /*!< RXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN0_SBUFDT_RXD_BYTE0_Pos (0UL) /*!< RXD_BYTE0 (Bit 0) */
+#define CAN0_SBUFDT_RXD_BYTE0_Msk (0xffUL) /*!< RXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ========================================================= TSCR ========================================================== */
+#define CAN0_TSCR_TSP_Pos (20UL) /*!< TSP (Bit 20) */
+#define CAN0_TSCR_TSP_Msk (0xf00000UL) /*!< TSP (Bitfield-Mask: 0x0f) */
+#define CAN0_TSCR_TSS_Pos (16UL) /*!< TSS (Bit 16) */
+#define CAN0_TSCR_TSS_Msk (0xf0000UL) /*!< TSS (Bitfield-Mask: 0x0f) */
+/* ========================================================== TSC ========================================================== */
+#define CAN0_TSC_TSC_Pos (0UL) /*!< TSC (Bit 0) */
+#define CAN0_TSC_TSC_Msk (0xffffUL) /*!< TSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= RTOP ========================================================== */
+#define CAN0_RTOP_RTOE_Pos (24UL) /*!< RTOE (Bit 24) */
+#define CAN0_RTOP_RTOE_Msk (0x1000000UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define CAN0_RTOP_RTOP_Pos (0UL) /*!< RTOP (Bit 0) */
+#define CAN0_RTOP_RTOP_Msk (0xffffUL) /*!< RTOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= RTOC ========================================================== */
+#define CAN0_RTOC_RTOC_Pos (0UL) /*!< RTOC (Bit 0) */
+#define CAN0_RTOC_RTOC_Msk (0xffffUL) /*!< RTOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= STOP ========================================================== */
+#define CAN0_STOP_STOE_Pos (24UL) /*!< STOE (Bit 24) */
+#define CAN0_STOP_STOE_Msk (0x1000000UL) /*!< STOE (Bitfield-Mask: 0x01) */
+#define CAN0_STOP_STOP_Pos (0UL) /*!< STOP (Bit 0) */
+#define CAN0_STOP_STOP_Msk (0xffffUL) /*!< STOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= STOC ========================================================== */
+#define CAN0_STOC_STOC_Pos (0UL) /*!< STOC (Bit 0) */
+#define CAN0_STOC_STOC_Msk (0xffffUL) /*!< STOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= ETOP ========================================================== */
+#define CAN0_ETOP_ETOE_Pos (24UL) /*!< ETOE (Bit 24) */
+#define CAN0_ETOP_ETOE_Msk (0x1000000UL) /*!< ETOE (Bitfield-Mask: 0x01) */
+#define CAN0_ETOP_ETOP_Pos (0UL) /*!< ETOP (Bit 0) */
+#define CAN0_ETOP_ETOP_Msk (0xffffUL) /*!< ETOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= ETOC ========================================================== */
+#define CAN0_ETOC_ETOC_Pos (0UL) /*!< ETOC (Bit 0) */
+#define CAN0_ETOC_ETOC_Msk (0xffffUL) /*!< ETOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CTOP ========================================================== */
+#define CAN0_CTOP_CTOE_Pos (24UL) /*!< CTOE (Bit 24) */
+#define CAN0_CTOP_CTOE_Msk (0x1000000UL) /*!< CTOE (Bitfield-Mask: 0x01) */
+#define CAN0_CTOP_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */
+#define CAN0_CTOP_CTOP_Msk (0xffffUL) /*!< CTOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= CTOC ========================================================== */
+#define CAN0_CTOC_CTOC_Pos (0UL) /*!< CTOC (Bit 0) */
+#define CAN0_CTOC_CTOC_Msk (0xffffUL) /*!< CTOC (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ CAN1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CTRL ========================================================== */
+#define CAN1_CTRL_AFWL_Pos (28UL) /*!< AFWL (Bit 28) */
+#define CAN1_CTRL_AFWL_Msk (0xf0000000UL) /*!< AFWL (Bitfield-Mask: 0x0f) */
+#define CAN1_CTRL_EWL_Pos (24UL) /*!< EWL (Bit 24) */
+#define CAN1_CTRL_EWL_Msk (0xf000000UL) /*!< EWL (Bitfield-Mask: 0x0f) */
+#define CAN1_CTRL_EREL_Pos (22UL) /*!< EREL (Bit 22) */
+#define CAN1_CTRL_EREL_Msk (0x400000UL) /*!< EREL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_SREL_Pos (21UL) /*!< SREL (Bit 21) */
+#define CAN1_CTRL_SREL_Msk (0x200000UL) /*!< SREL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_RREL_Pos (20UL) /*!< RREL (Bit 20) */
+#define CAN1_CTRL_RREL_Msk (0x100000UL) /*!< RREL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_FD_EN_Pos (18UL) /*!< FD_EN (Bit 18) */
+#define CAN1_CTRL_FD_EN_Msk (0x40000UL) /*!< FD_EN (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_FD_ISO_Pos (17UL) /*!< FD_ISO (Bit 17) */
+#define CAN1_CTRL_FD_ISO_Msk (0x20000UL) /*!< FD_ISO (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TSNEXT_Pos (16UL) /*!< TSNEXT (Bit 16) */
+#define CAN1_CTRL_TSNEXT_Msk (0x10000UL) /*!< TSNEXT (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_PEDT_Pos (15UL) /*!< PEDT (Bit 15) */
+#define CAN1_CTRL_PEDT_Msk (0x8000UL) /*!< PEDT (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_MUXSEL_Pos (13UL) /*!< MUXSEL (Bit 13) */
+#define CAN1_CTRL_MUXSEL_Msk (0x2000UL) /*!< MUXSEL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TBSEL_Pos (12UL) /*!< TBSEL (Bit 12) */
+#define CAN1_CTRL_TBSEL_Msk (0x1000UL) /*!< TBSEL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_LOM_Pos (11UL) /*!< LOM (Bit 11) */
+#define CAN1_CTRL_LOM_Msk (0x800UL) /*!< LOM (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TPE_Pos (9UL) /*!< TPE (Bit 9) */
+#define CAN1_CTRL_TPE_Msk (0x200UL) /*!< TPE (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TPA_Pos (8UL) /*!< TPA (Bit 8) */
+#define CAN1_CTRL_TPA_Msk (0x100UL) /*!< TPA (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TSONE_Pos (7UL) /*!< TSONE (Bit 7) */
+#define CAN1_CTRL_TSONE_Msk (0x80UL) /*!< TSONE (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TSALL_Pos (6UL) /*!< TSALL (Bit 6) */
+#define CAN1_CTRL_TSALL_Msk (0x40UL) /*!< TSALL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TSA_Pos (5UL) /*!< TSA (Bit 5) */
+#define CAN1_CTRL_TSA_Msk (0x20UL) /*!< TSA (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_RESET_Pos (4UL) /*!< RESET (Bit 4) */
+#define CAN1_CTRL_RESET_Msk (0x10UL) /*!< RESET (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_LBME_Pos (3UL) /*!< LBME (Bit 3) */
+#define CAN1_CTRL_LBME_Msk (0x8UL) /*!< LBME (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_LBMI_Pos (2UL) /*!< LBMI (Bit 2) */
+#define CAN1_CTRL_LBMI_Msk (0x4UL) /*!< LBMI (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TPSS_Pos (1UL) /*!< TPSS (Bit 1) */
+#define CAN1_CTRL_TPSS_Msk (0x2UL) /*!< TPSS (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TSSS_Pos (0UL) /*!< TSSS (Bit 0) */
+#define CAN1_CTRL_TSSS_Msk (0x1UL) /*!< TSSS (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define CAN1_STATUS_SAFWL_Pos (28UL) /*!< SAFWL (Bit 28) */
+#define CAN1_STATUS_SAFWL_Msk (0xf0000000UL) /*!< SAFWL (Bitfield-Mask: 0x0f) */
+#define CAN1_STATUS_EAFWL_Pos (24UL) /*!< EAFWL (Bit 24) */
+#define CAN1_STATUS_EAFWL_Msk (0xf000000UL) /*!< EAFWL (Bitfield-Mask: 0x0f) */
+#define CAN1_STATUS_AEWL_Pos (20UL) /*!< AEWL (Bit 20) */
+#define CAN1_STATUS_AEWL_Msk (0xf00000UL) /*!< AEWL (Bitfield-Mask: 0x0f) */
+#define CAN1_STATUS_ROV_Pos (18UL) /*!< ROV (Bit 18) */
+#define CAN1_STATUS_ROV_Msk (0x40000UL) /*!< ROV (Bitfield-Mask: 0x01) */
+#define CAN1_STATUS_RSTAT_Pos (16UL) /*!< RSTAT (Bit 16) */
+#define CAN1_STATUS_RSTAT_Msk (0x30000UL) /*!< RSTAT (Bitfield-Mask: 0x03) */
+#define CAN1_STATUS_SOV_Pos (15UL) /*!< SOV (Bit 15) */
+#define CAN1_STATUS_SOV_Msk (0x8000UL) /*!< SOV (Bitfield-Mask: 0x01) */
+#define CAN1_STATUS_SSTAT_Pos (13UL) /*!< SSTAT (Bit 13) */
+#define CAN1_STATUS_SSTAT_Msk (0x6000UL) /*!< SSTAT (Bitfield-Mask: 0x03) */
+#define CAN1_STATUS_TSSTAT_Pos (8UL) /*!< TSSTAT (Bit 8) */
+#define CAN1_STATUS_TSSTAT_Msk (0x1f00UL) /*!< TSSTAT (Bitfield-Mask: 0x1f) */
+#define CAN1_STATUS_EOV_Pos (7UL) /*!< EOV (Bit 7) */
+#define CAN1_STATUS_EOV_Msk (0x80UL) /*!< EOV (Bitfield-Mask: 0x01) */
+#define CAN1_STATUS_ESTAT_Pos (5UL) /*!< ESTAT (Bit 5) */
+#define CAN1_STATUS_ESTAT_Msk (0x60UL) /*!< ESTAT (Bitfield-Mask: 0x03) */
+#define CAN1_STATUS_RACTIVE_Pos (2UL) /*!< RACTIVE (Bit 2) */
+#define CAN1_STATUS_RACTIVE_Msk (0x4UL) /*!< RACTIVE (Bitfield-Mask: 0x01) */
+#define CAN1_STATUS_TACTIVE_Pos (1UL) /*!< TACTIVE (Bit 1) */
+#define CAN1_STATUS_TACTIVE_Msk (0x2UL) /*!< TACTIVE (Bitfield-Mask: 0x01) */
+#define CAN1_STATUS_BUSOFF_Pos (0UL) /*!< BUSOFF (Bit 0) */
+#define CAN1_STATUS_BUSOFF_Msk (0x1UL) /*!< BUSOFF (Bitfield-Mask: 0x01) */
+/* ======================================================== INTREN ========================================================= */
+#define CAN1_INTREN_TEIE_Pos (31UL) /*!< TEIE (Bit 31) */
+#define CAN1_INTREN_TEIE_Msk (0x80000000UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_TAEIE_Pos (30UL) /*!< TAEIE (Bit 30) */
+#define CAN1_INTREN_TAEIE_Msk (0x40000000UL) /*!< TAEIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_PMIE_Pos (29UL) /*!< PMIE (Bit 29) */
+#define CAN1_INTREN_PMIE_Msk (0x20000000UL) /*!< PMIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_TSCIE_Pos (28UL) /*!< TSCIE (Bit 28) */
+#define CAN1_INTREN_TSCIE_Msk (0x10000000UL) /*!< TSCIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_RTOIE_Pos (27UL) /*!< RTOIE (Bit 27) */
+#define CAN1_INTREN_RTOIE_Msk (0x8000000UL) /*!< RTOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_STOIE_Pos (26UL) /*!< STOIE (Bit 26) */
+#define CAN1_INTREN_STOIE_Msk (0x4000000UL) /*!< STOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_ETOIE_Pos (25UL) /*!< ETOIE (Bit 25) */
+#define CAN1_INTREN_ETOIE_Msk (0x2000000UL) /*!< ETOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_CTOIE_Pos (24UL) /*!< CTOIE (Bit 24) */
+#define CAN1_INTREN_CTOIE_Msk (0x1000000UL) /*!< CTOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_SOIE_Pos (23UL) /*!< SOIE (Bit 23) */
+#define CAN1_INTREN_SOIE_Msk (0x800000UL) /*!< SOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_SFIE_Pos (22UL) /*!< SFIE (Bit 22) */
+#define CAN1_INTREN_SFIE_Msk (0x400000UL) /*!< SFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_SAFIE_Pos (21UL) /*!< SAFIE (Bit 21) */
+#define CAN1_INTREN_SAFIE_Msk (0x200000UL) /*!< SAFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_EOIE_Pos (20UL) /*!< EOIE (Bit 20) */
+#define CAN1_INTREN_EOIE_Msk (0x100000UL) /*!< EOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_EFIE_Pos (19UL) /*!< EFIE (Bit 19) */
+#define CAN1_INTREN_EFIE_Msk (0x80000UL) /*!< EFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_EAFIE_Pos (18UL) /*!< EAFIE (Bit 18) */
+#define CAN1_INTREN_EAFIE_Msk (0x40000UL) /*!< EAFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_AIE_Pos (17UL) /*!< AIE (Bit 17) */
+#define CAN1_INTREN_AIE_Msk (0x20000UL) /*!< AIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_SRIE_Pos (13UL) /*!< SRIE (Bit 13) */
+#define CAN1_INTREN_SRIE_Msk (0x2000UL) /*!< SRIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_ERIE_Pos (12UL) /*!< ERIE (Bit 12) */
+#define CAN1_INTREN_ERIE_Msk (0x1000UL) /*!< ERIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_ECIE_Pos (11UL) /*!< ECIE (Bit 11) */
+#define CAN1_INTREN_ECIE_Msk (0x800UL) /*!< ECIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */
+#define CAN1_INTREN_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_ALIE_Pos (9UL) /*!< ALIE (Bit 9) */
+#define CAN1_INTREN_ALIE_Msk (0x200UL) /*!< ALIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */
+#define CAN1_INTREN_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_RIE_Pos (7UL) /*!< RIE (Bit 7) */
+#define CAN1_INTREN_RIE_Msk (0x80UL) /*!< RIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_ROIE_Pos (6UL) /*!< ROIE (Bit 6) */
+#define CAN1_INTREN_ROIE_Msk (0x40UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_RFIE_Pos (5UL) /*!< RFIE (Bit 5) */
+#define CAN1_INTREN_RFIE_Msk (0x20UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_RAFIE_Pos (4UL) /*!< RAFIE (Bit 4) */
+#define CAN1_INTREN_RAFIE_Msk (0x10UL) /*!< RAFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_TPIE_Pos (3UL) /*!< TPIE (Bit 3) */
+#define CAN1_INTREN_TPIE_Msk (0x8UL) /*!< TPIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_TSIE_Pos (2UL) /*!< TSIE (Bit 2) */
+#define CAN1_INTREN_TSIE_Msk (0x4UL) /*!< TSIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_EIE_Pos (1UL) /*!< EIE (Bit 1) */
+#define CAN1_INTREN_EIE_Msk (0x2UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_TSFF_Pos (0UL) /*!< TSFF (Bit 0) */
+#define CAN1_INTREN_TSFF_Msk (0x1UL) /*!< TSFF (Bitfield-Mask: 0x01) */
+/* ======================================================== INTRST ========================================================= */
+#define CAN1_INTRST_TEIF_Pos (31UL) /*!< TEIF (Bit 31) */
+#define CAN1_INTRST_TEIF_Msk (0x80000000UL) /*!< TEIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_TAEIF_Pos (30UL) /*!< TAEIF (Bit 30) */
+#define CAN1_INTRST_TAEIF_Msk (0x40000000UL) /*!< TAEIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_PMIF_Pos (29UL) /*!< PMIF (Bit 29) */
+#define CAN1_INTRST_PMIF_Msk (0x20000000UL) /*!< PMIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_TSCIF_Pos (28UL) /*!< TSCIF (Bit 28) */
+#define CAN1_INTRST_TSCIF_Msk (0x10000000UL) /*!< TSCIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_RTOIF_Pos (27UL) /*!< RTOIF (Bit 27) */
+#define CAN1_INTRST_RTOIF_Msk (0x8000000UL) /*!< RTOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_STOIF_Pos (26UL) /*!< STOIF (Bit 26) */
+#define CAN1_INTRST_STOIF_Msk (0x4000000UL) /*!< STOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_ETOIF_Pos (25UL) /*!< ETOIF (Bit 25) */
+#define CAN1_INTRST_ETOIF_Msk (0x2000000UL) /*!< ETOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_CTOIF_Pos (24UL) /*!< CTOIF (Bit 24) */
+#define CAN1_INTRST_CTOIF_Msk (0x1000000UL) /*!< CTOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_SOIF_Pos (23UL) /*!< SOIF (Bit 23) */
+#define CAN1_INTRST_SOIF_Msk (0x800000UL) /*!< SOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_SFIF_Pos (22UL) /*!< SFIF (Bit 22) */
+#define CAN1_INTRST_SFIF_Msk (0x400000UL) /*!< SFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_SAFIF_Pos (21UL) /*!< SAFIF (Bit 21) */
+#define CAN1_INTRST_SAFIF_Msk (0x200000UL) /*!< SAFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EOIF_Pos (20UL) /*!< EOIF (Bit 20) */
+#define CAN1_INTRST_EOIF_Msk (0x100000UL) /*!< EOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EFIF_Pos (19UL) /*!< EFIF (Bit 19) */
+#define CAN1_INTRST_EFIF_Msk (0x80000UL) /*!< EFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EAFIF_Pos (18UL) /*!< EAFIF (Bit 18) */
+#define CAN1_INTRST_EAFIF_Msk (0x40000UL) /*!< EAFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EWARN_Pos (17UL) /*!< EWARN (Bit 17) */
+#define CAN1_INTRST_EWARN_Msk (0x20000UL) /*!< EWARN (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EPASS_Pos (16UL) /*!< EPASS (Bit 16) */
+#define CAN1_INTRST_EPASS_Msk (0x10000UL) /*!< EPASS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_SRIF_Pos (13UL) /*!< SRIF (Bit 13) */
+#define CAN1_INTRST_SRIF_Msk (0x2000UL) /*!< SRIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_ERIF_Pos (12UL) /*!< ERIF (Bit 12) */
+#define CAN1_INTRST_ERIF_Msk (0x1000UL) /*!< ERIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_ECIF_Pos (11UL) /*!< ECIF (Bit 11) */
+#define CAN1_INTRST_ECIF_Msk (0x800UL) /*!< ECIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EPIF_Pos (10UL) /*!< EPIF (Bit 10) */
+#define CAN1_INTRST_EPIF_Msk (0x400UL) /*!< EPIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_ALIF_Pos (9UL) /*!< ALIF (Bit 9) */
+#define CAN1_INTRST_ALIF_Msk (0x200UL) /*!< ALIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_BEIF_Pos (8UL) /*!< BEIF (Bit 8) */
+#define CAN1_INTRST_BEIF_Msk (0x100UL) /*!< BEIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_RIF_Pos (7UL) /*!< RIF (Bit 7) */
+#define CAN1_INTRST_RIF_Msk (0x80UL) /*!< RIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_ROIF_Pos (6UL) /*!< ROIF (Bit 6) */
+#define CAN1_INTRST_ROIF_Msk (0x40UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_RFIF_Pos (5UL) /*!< RFIF (Bit 5) */
+#define CAN1_INTRST_RFIF_Msk (0x20UL) /*!< RFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_RAFIF_Pos (4UL) /*!< RAFIF (Bit 4) */
+#define CAN1_INTRST_RAFIF_Msk (0x10UL) /*!< RAFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_TPIF_Pos (3UL) /*!< TPIF (Bit 3) */
+#define CAN1_INTRST_TPIF_Msk (0x8UL) /*!< TPIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_TSIF_Pos (2UL) /*!< TSIF (Bit 2) */
+#define CAN1_INTRST_TSIF_Msk (0x4UL) /*!< TSIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EIF_Pos (1UL) /*!< EIF (Bit 1) */
+#define CAN1_INTRST_EIF_Msk (0x2UL) /*!< EIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_AIF_Pos (0UL) /*!< AIF (Bit 0) */
+#define CAN1_INTRST_AIF_Msk (0x1UL) /*!< AIF (Bitfield-Mask: 0x01) */
+/* ======================================================== BITTIME ======================================================== */
+#define CAN1_BITTIME_F_SEG1_Pos (20UL) /*!< F_SEG1 (Bit 20) */
+#define CAN1_BITTIME_F_SEG1_Msk (0xf00000UL) /*!< F_SEG1 (Bitfield-Mask: 0x0f) */
+#define CAN1_BITTIME_S_SJW_Pos (16UL) /*!< S_SJW (Bit 16) */
+#define CAN1_BITTIME_S_SJW_Msk (0xf0000UL) /*!< S_SJW (Bitfield-Mask: 0x0f) */
+#define CAN1_BITTIME_F_SEG2_Pos (13UL) /*!< F_SEG2 (Bit 13) */
+#define CAN1_BITTIME_F_SEG2_Msk (0xe000UL) /*!< F_SEG2 (Bitfield-Mask: 0x07) */
+#define CAN1_BITTIME_S_SEG2_Pos (8UL) /*!< S_SEG2 (Bit 8) */
+#define CAN1_BITTIME_S_SEG2_Msk (0x1f00UL) /*!< S_SEG2 (Bitfield-Mask: 0x1f) */
+#define CAN1_BITTIME_F_SJW_Pos (6UL) /*!< F_SJW (Bit 6) */
+#define CAN1_BITTIME_F_SJW_Msk (0xc0UL) /*!< F_SJW (Bitfield-Mask: 0x03) */
+#define CAN1_BITTIME_S_SEG1_Pos (0UL) /*!< S_SEG1 (Bit 0) */
+#define CAN1_BITTIME_S_SEG1_Msk (0x3fUL) /*!< S_SEG1 (Bitfield-Mask: 0x3f) */
+/* ========================================================= PRESC ========================================================= */
+#define CAN1_PRESC_TDCEN_Pos (23UL) /*!< TDCEN (Bit 23) */
+#define CAN1_PRESC_TDCEN_Msk (0x800000UL) /*!< TDCEN (Bitfield-Mask: 0x01) */
+#define CAN1_PRESC_SSPOFF_Pos (16UL) /*!< SSPOFF (Bit 16) */
+#define CAN1_PRESC_SSPOFF_Msk (0x1f0000UL) /*!< SSPOFF (Bitfield-Mask: 0x1f) */
+#define CAN1_PRESC_F_PRESC_Pos (8UL) /*!< F_PRESC (Bit 8) */
+#define CAN1_PRESC_F_PRESC_Msk (0xff00UL) /*!< F_PRESC (Bitfield-Mask: 0xff) */
+#define CAN1_PRESC_S_PRESC_Pos (0UL) /*!< S_PRESC (Bit 0) */
+#define CAN1_PRESC_S_PRESC_Msk (0xffUL) /*!< S_PRESC (Bitfield-Mask: 0xff) */
+/* ========================================================= ERRST ========================================================= */
+#define CAN1_ERRST_RECNT_Pos (24UL) /*!< RECNT (Bit 24) */
+#define CAN1_ERRST_RECNT_Msk (0xff000000UL) /*!< RECNT (Bitfield-Mask: 0xff) */
+#define CAN1_ERRST_TECNT_Pos (16UL) /*!< TECNT (Bit 16) */
+#define CAN1_ERRST_TECNT_Msk (0xff0000UL) /*!< TECNT (Bitfield-Mask: 0xff) */
+#define CAN1_ERRST_ECNT_Pos (8UL) /*!< ECNT (Bit 8) */
+#define CAN1_ERRST_ECNT_Msk (0xff00UL) /*!< ECNT (Bitfield-Mask: 0xff) */
+#define CAN1_ERRST_KOER_Pos (5UL) /*!< KOER (Bit 5) */
+#define CAN1_ERRST_KOER_Msk (0xe0UL) /*!< KOER (Bitfield-Mask: 0x07) */
+#define CAN1_ERRST_ALC_Pos (0UL) /*!< ALC (Bit 0) */
+#define CAN1_ERRST_ALC_Msk (0x1fUL) /*!< ALC (Bitfield-Mask: 0x1f) */
+/* ========================================================= PRTST ========================================================= */
+#define CAN1_PRTST_DKOER_Pos (8UL) /*!< DKOER (Bit 8) */
+#define CAN1_PRTST_DKOER_Msk (0x700UL) /*!< DKOER (Bitfield-Mask: 0x07) */
+#define CAN1_PRTST_FDSTS_Pos (4UL) /*!< FDSTS (Bit 4) */
+#define CAN1_PRTST_FDSTS_Msk (0xf0UL) /*!< FDSTS (Bitfield-Mask: 0x0f) */
+#define CAN1_PRTST_NDSTS_Pos (2UL) /*!< NDSTS (Bit 2) */
+#define CAN1_PRTST_NDSTS_Msk (0xcUL) /*!< NDSTS (Bitfield-Mask: 0x03) */
+#define CAN1_PRTST_RBSTS_Pos (0UL) /*!< RBSTS (Bit 0) */
+#define CAN1_PRTST_RBSTS_Msk (0x3UL) /*!< RBSTS (Bitfield-Mask: 0x03) */
+/* ======================================================== INTRLS ========================================================= */
+#define CAN1_INTRLS_TEILS_Pos (31UL) /*!< TEILS (Bit 31) */
+#define CAN1_INTRLS_TEILS_Msk (0x80000000UL) /*!< TEILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_TAEILS_Pos (30UL) /*!< TAEILS (Bit 30) */
+#define CAN1_INTRLS_TAEILS_Msk (0x40000000UL) /*!< TAEILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_PMILS_Pos (29UL) /*!< PMILS (Bit 29) */
+#define CAN1_INTRLS_PMILS_Msk (0x20000000UL) /*!< PMILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_TSCILS_Pos (28UL) /*!< TSCILS (Bit 28) */
+#define CAN1_INTRLS_TSCILS_Msk (0x10000000UL) /*!< TSCILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_RTOILS_Pos (27UL) /*!< RTOILS (Bit 27) */
+#define CAN1_INTRLS_RTOILS_Msk (0x8000000UL) /*!< RTOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_STOILS_Pos (26UL) /*!< STOILS (Bit 26) */
+#define CAN1_INTRLS_STOILS_Msk (0x4000000UL) /*!< STOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_ETOILS_Pos (25UL) /*!< ETOILS (Bit 25) */
+#define CAN1_INTRLS_ETOILS_Msk (0x2000000UL) /*!< ETOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_CTOILS_Pos (24UL) /*!< CTOILS (Bit 24) */
+#define CAN1_INTRLS_CTOILS_Msk (0x1000000UL) /*!< CTOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_SOILS_Pos (23UL) /*!< SOILS (Bit 23) */
+#define CAN1_INTRLS_SOILS_Msk (0x800000UL) /*!< SOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_SFILS_Pos (22UL) /*!< SFILS (Bit 22) */
+#define CAN1_INTRLS_SFILS_Msk (0x400000UL) /*!< SFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_SAFILS_Pos (21UL) /*!< SAFILS (Bit 21) */
+#define CAN1_INTRLS_SAFILS_Msk (0x200000UL) /*!< SAFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_EOILS_Pos (20UL) /*!< EOILS (Bit 20) */
+#define CAN1_INTRLS_EOILS_Msk (0x100000UL) /*!< EOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_EFILS_Pos (19UL) /*!< EFILS (Bit 19) */
+#define CAN1_INTRLS_EFILS_Msk (0x80000UL) /*!< EFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_EAFILS_Pos (18UL) /*!< EAFILS (Bit 18) */
+#define CAN1_INTRLS_EAFILS_Msk (0x40000UL) /*!< EAFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_SRILS_Pos (13UL) /*!< SRILS (Bit 13) */
+#define CAN1_INTRLS_SRILS_Msk (0x2000UL) /*!< SRILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_ERILS_Pos (12UL) /*!< ERILS (Bit 12) */
+#define CAN1_INTRLS_ERILS_Msk (0x1000UL) /*!< ERILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_ECILS_Pos (11UL) /*!< ECILS (Bit 11) */
+#define CAN1_INTRLS_ECILS_Msk (0x800UL) /*!< ECILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_EPILS_Pos (10UL) /*!< EPILS (Bit 10) */
+#define CAN1_INTRLS_EPILS_Msk (0x400UL) /*!< EPILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_ALILS_Pos (9UL) /*!< ALILS (Bit 9) */
+#define CAN1_INTRLS_ALILS_Msk (0x200UL) /*!< ALILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_BEILS_Pos (8UL) /*!< BEILS (Bit 8) */
+#define CAN1_INTRLS_BEILS_Msk (0x100UL) /*!< BEILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_RILS_Pos (7UL) /*!< RILS (Bit 7) */
+#define CAN1_INTRLS_RILS_Msk (0x80UL) /*!< RILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_ROILS_Pos (6UL) /*!< ROILS (Bit 6) */
+#define CAN1_INTRLS_ROILS_Msk (0x40UL) /*!< ROILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_RFILS_Pos (5UL) /*!< RFILS (Bit 5) */
+#define CAN1_INTRLS_RFILS_Msk (0x20UL) /*!< RFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_RAFILS_Pos (4UL) /*!< RAFILS (Bit 4) */
+#define CAN1_INTRLS_RAFILS_Msk (0x10UL) /*!< RAFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_TPILS_Pos (3UL) /*!< TPILS (Bit 3) */
+#define CAN1_INTRLS_TPILS_Msk (0x8UL) /*!< TPILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_TSILS_Pos (2UL) /*!< TSILS (Bit 2) */
+#define CAN1_INTRLS_TSILS_Msk (0x4UL) /*!< TSILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_EILS_Pos (1UL) /*!< EILS (Bit 1) */
+#define CAN1_INTRLS_EILS_Msk (0x2UL) /*!< EILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_AILS_Pos (0UL) /*!< AILS (Bit 0) */
+#define CAN1_INTRLS_AILS_Msk (0x1UL) /*!< AILS (Bitfield-Mask: 0x01) */
+/* ========================================================= GFCR ========================================================== */
+#define CAN1_GFCR_SRFR_Pos (7UL) /*!< SRFR (Bit 7) */
+#define CAN1_GFCR_SRFR_Msk (0x80UL) /*!< SRFR (Bitfield-Mask: 0x01) */
+#define CAN1_GFCR_ERFR_Pos (6UL) /*!< ERFR (Bit 6) */
+#define CAN1_GFCR_ERFR_Msk (0x40UL) /*!< ERFR (Bitfield-Mask: 0x01) */
+#define CAN1_GFCR_PRBM_Pos (1UL) /*!< PRBM (Bit 1) */
+#define CAN1_GFCR_PRBM_Msk (0x2UL) /*!< PRBM (Bitfield-Mask: 0x01) */
+#define CAN1_GFCR_SRBM_Pos (0UL) /*!< SRBM (Bit 0) */
+#define CAN1_GFCR_SRBM_Msk (0x1UL) /*!< SRBM (Bitfield-Mask: 0x01) */
+/* ========================================================= EMCR ========================================================== */
+#define CAN1_EMCR_EIDM_Pos (0UL) /*!< EIDM (Bit 0) */
+#define CAN1_EMCR_EIDM_Msk (0x1fffffffUL) /*!< EIDM (Bitfield-Mask: 0x1fffffff) */
+/* ========================================================= PMST ========================================================== */
+#define CAN1_PMST_PMAS_Pos (4UL) /*!< PMAS (Bit 4) */
+#define CAN1_PMST_PMAS_Msk (0xf0UL) /*!< PMAS (Bitfield-Mask: 0x0f) */
+#define CAN1_PMST_PMBS_Pos (1UL) /*!< PMBS (Bit 1) */
+#define CAN1_PMST_PMBS_Msk (0x6UL) /*!< PMBS (Bitfield-Mask: 0x03) */
+#define CAN1_PMST_PMIS_Pos (0UL) /*!< PMIS (Bit 0) */
+#define CAN1_PMST_PMIS_Msk (0x1UL) /*!< PMIS (Bitfield-Mask: 0x01) */
+/* ========================================================= ACFEN ========================================================= */
+#define CAN1_ACFEN_AE15_Pos (15UL) /*!< AE15 (Bit 15) */
+#define CAN1_ACFEN_AE15_Msk (0x8000UL) /*!< AE15 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE14_Pos (14UL) /*!< AE14 (Bit 14) */
+#define CAN1_ACFEN_AE14_Msk (0x4000UL) /*!< AE14 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE13_Pos (13UL) /*!< AE13 (Bit 13) */
+#define CAN1_ACFEN_AE13_Msk (0x2000UL) /*!< AE13 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE12_Pos (12UL) /*!< AE12 (Bit 12) */
+#define CAN1_ACFEN_AE12_Msk (0x1000UL) /*!< AE12 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE11_Pos (11UL) /*!< AE11 (Bit 11) */
+#define CAN1_ACFEN_AE11_Msk (0x800UL) /*!< AE11 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE10_Pos (10UL) /*!< AE10 (Bit 10) */
+#define CAN1_ACFEN_AE10_Msk (0x400UL) /*!< AE10 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE9_Pos (9UL) /*!< AE9 (Bit 9) */
+#define CAN1_ACFEN_AE9_Msk (0x200UL) /*!< AE9 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE8_Pos (8UL) /*!< AE8 (Bit 8) */
+#define CAN1_ACFEN_AE8_Msk (0x100UL) /*!< AE8 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE7_Pos (7UL) /*!< AE7 (Bit 7) */
+#define CAN1_ACFEN_AE7_Msk (0x80UL) /*!< AE7 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE6_Pos (6UL) /*!< AE6 (Bit 6) */
+#define CAN1_ACFEN_AE6_Msk (0x40UL) /*!< AE6 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE5_Pos (5UL) /*!< AE5 (Bit 5) */
+#define CAN1_ACFEN_AE5_Msk (0x20UL) /*!< AE5 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE4_Pos (4UL) /*!< AE4 (Bit 4) */
+#define CAN1_ACFEN_AE4_Msk (0x10UL) /*!< AE4 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE3_Pos (3UL) /*!< AE3 (Bit 3) */
+#define CAN1_ACFEN_AE3_Msk (0x8UL) /*!< AE3 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE2_Pos (2UL) /*!< AE2 (Bit 2) */
+#define CAN1_ACFEN_AE2_Msk (0x4UL) /*!< AE2 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE1_Pos (1UL) /*!< AE1 (Bit 1) */
+#define CAN1_ACFEN_AE1_Msk (0x2UL) /*!< AE1 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE0_Pos (0UL) /*!< AE0 (Bit 0) */
+#define CAN1_ACFEN_AE0_Msk (0x1UL) /*!< AE0 (Bitfield-Mask: 0x01) */
+/* ======================================================== ACFCTRL ======================================================== */
+#define CAN1_ACFCTRL_SELMASK_Pos (5UL) /*!< SELMASK (Bit 5) */
+#define CAN1_ACFCTRL_SELMASK_Msk (0x20UL) /*!< SELMASK (Bitfield-Mask: 0x01) */
+#define CAN1_ACFCTRL_ACFADR_Pos (0UL) /*!< ACFADR (Bit 0) */
+#define CAN1_ACFCTRL_ACFADR_Msk (0xfUL) /*!< ACFADR (Bitfield-Mask: 0x0f) */
+/* ========================================================== ACF ========================================================== */
+#define CAN1_ACF_AIDEE_Pos (30UL) /*!< AIDEE (Bit 30) */
+#define CAN1_ACF_AIDEE_Msk (0x40000000UL) /*!< AIDEE (Bitfield-Mask: 0x01) */
+#define CAN1_ACF_AIDE_Pos (29UL) /*!< AIDE (Bit 29) */
+#define CAN1_ACF_AIDE_Msk (0x20000000UL) /*!< AIDE (Bitfield-Mask: 0x01) */
+#define CAN1_ACF_ACF_X_Pos (0UL) /*!< ACF_X (Bit 0) */
+#define CAN1_ACF_ACF_X_Msk (0x1fffffffUL) /*!< ACF_X (Bitfield-Mask: 0x1fffffff) */
+/* ========================================================= ACFE ========================================================== */
+#define CAN1_ACFE_ACF_M_Pos (4UL) /*!< ACF_M (Bit 4) */
+#define CAN1_ACFE_ACF_M_Msk (0xf0UL) /*!< ACF_M (Bitfield-Mask: 0x0f) */
+#define CAN1_ACFE_ACF_C_Pos (0UL) /*!< ACF_C (Bit 0) */
+#define CAN1_ACFE_ACF_C_Msk (0xfUL) /*!< ACF_C (Bitfield-Mask: 0x0f) */
+/* ======================================================== RBUFID ========================================================= */
+#define CAN1_RBUFID_RXD_ID_Pos (0UL) /*!< RXD_ID (Bit 0) */
+#define CAN1_RBUFID_RXD_ID_Msk (0xffffffffUL) /*!< RXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== RBUFCR ========================================================= */
+#define CAN1_RBUFCR_RXD_ACF_Pos (24UL) /*!< RXD_ACF (Bit 24) */
+#define CAN1_RBUFCR_RXD_ACF_Msk (0xf000000UL) /*!< RXD_ACF (Bitfield-Mask: 0x0f) */
+#define CAN1_RBUFCR_RXD_TS_Pos (8UL) /*!< RXD_TS (Bit 8) */
+#define CAN1_RBUFCR_RXD_TS_Msk (0xffff00UL) /*!< RXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN1_RBUFCR_RXD_CR_Pos (4UL) /*!< RXD_CR (Bit 4) */
+#define CAN1_RBUFCR_RXD_CR_Msk (0xf0UL) /*!< RXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN1_RBUFCR_RXD_DLC_Pos (0UL) /*!< RXD_DLC (Bit 0) */
+#define CAN1_RBUFCR_RXD_DLC_Msk (0xfUL) /*!< RXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== RBUFDT ========================================================= */
+#define CAN1_RBUFDT_RXD_BYTE3_Pos (24UL) /*!< RXD_BYTE3 (Bit 24) */
+#define CAN1_RBUFDT_RXD_BYTE3_Msk (0xff000000UL) /*!< RXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN1_RBUFDT_RXD_BYTE2_Pos (16UL) /*!< RXD_BYTE2 (Bit 16) */
+#define CAN1_RBUFDT_RXD_BYTE2_Msk (0xff0000UL) /*!< RXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN1_RBUFDT_RXD_BYTE1_Pos (8UL) /*!< RXD_BYTE1 (Bit 8) */
+#define CAN1_RBUFDT_RXD_BYTE1_Msk (0xff00UL) /*!< RXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN1_RBUFDT_RXD_BYTE0_Pos (0UL) /*!< RXD_BYTE0 (Bit 0) */
+#define CAN1_RBUFDT_RXD_BYTE0_Msk (0xffUL) /*!< RXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ======================================================== TBUFID ========================================================= */
+#define CAN1_TBUFID_TXD_ID_Pos (0UL) /*!< TXD_ID (Bit 0) */
+#define CAN1_TBUFID_TXD_ID_Msk (0xffffffffUL) /*!< TXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== TBUFCR ========================================================= */
+#define CAN1_TBUFCR_TXD_ETB_Pos (31UL) /*!< TXD_ETB (Bit 31) */
+#define CAN1_TBUFCR_TXD_ETB_Msk (0x80000000UL) /*!< TXD_ETB (Bitfield-Mask: 0x01) */
+#define CAN1_TBUFCR_TXD_MM_Pos (8UL) /*!< TXD_MM (Bit 8) */
+#define CAN1_TBUFCR_TXD_MM_Msk (0xff00UL) /*!< TXD_MM (Bitfield-Mask: 0xff) */
+#define CAN1_TBUFCR_TXD_CR_Pos (4UL) /*!< TXD_CR (Bit 4) */
+#define CAN1_TBUFCR_TXD_CR_Msk (0xf0UL) /*!< TXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN1_TBUFCR_TXD_DLC_Pos (0UL) /*!< TXD_DLC (Bit 0) */
+#define CAN1_TBUFCR_TXD_DLC_Msk (0xfUL) /*!< TXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== TBUFDT ========================================================= */
+#define CAN1_TBUFDT_TXD_BYTE3_Pos (24UL) /*!< TXD_BYTE3 (Bit 24) */
+#define CAN1_TBUFDT_TXD_BYTE3_Msk (0xff000000UL) /*!< TXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN1_TBUFDT_TXD_BYTE2_Pos (16UL) /*!< TXD_BYTE2 (Bit 16) */
+#define CAN1_TBUFDT_TXD_BYTE2_Msk (0xff0000UL) /*!< TXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN1_TBUFDT_TXD_BYTE1_Pos (8UL) /*!< TXD_BYTE1 (Bit 8) */
+#define CAN1_TBUFDT_TXD_BYTE1_Msk (0xff00UL) /*!< TXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN1_TBUFDT_TXD_BYTE0_Pos (0UL) /*!< TXD_BYTE0 (Bit 0) */
+#define CAN1_TBUFDT_TXD_BYTE0_Msk (0xffUL) /*!< TXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ======================================================== EBUFID ========================================================= */
+#define CAN1_EBUFID_TXD_ID_Pos (0UL) /*!< TXD_ID (Bit 0) */
+#define CAN1_EBUFID_TXD_ID_Msk (0xffffffffUL) /*!< TXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== EBUFDT ========================================================= */
+#define CAN1_EBUFDT_TXD_MM_Pos (24UL) /*!< TXD_MM (Bit 24) */
+#define CAN1_EBUFDT_TXD_MM_Msk (0xff000000UL) /*!< TXD_MM (Bitfield-Mask: 0xff) */
+#define CAN1_EBUFDT_TXD_TS_Pos (8UL) /*!< TXD_TS (Bit 8) */
+#define CAN1_EBUFDT_TXD_TS_Msk (0xffff00UL) /*!< TXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN1_EBUFDT_TXD_CR_Pos (4UL) /*!< TXD_CR (Bit 4) */
+#define CAN1_EBUFDT_TXD_CR_Msk (0xf0UL) /*!< TXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN1_EBUFDT_TXD_DLC_Pos (0UL) /*!< TXD_DLC (Bit 0) */
+#define CAN1_EBUFDT_TXD_DLC_Msk (0xfUL) /*!< TXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== SBUFID ========================================================= */
+#define CAN1_SBUFID_RXD_ID_Pos (0UL) /*!< RXD_ID (Bit 0) */
+#define CAN1_SBUFID_RXD_ID_Msk (0xffffffffUL) /*!< RXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== SBUFCR ========================================================= */
+#define CAN1_SBUFCR_RXD_ACF_Pos (24UL) /*!< RXD_ACF (Bit 24) */
+#define CAN1_SBUFCR_RXD_ACF_Msk (0xf000000UL) /*!< RXD_ACF (Bitfield-Mask: 0x0f) */
+#define CAN1_SBUFCR_RXD_TS_Pos (8UL) /*!< RXD_TS (Bit 8) */
+#define CAN1_SBUFCR_RXD_TS_Msk (0xffff00UL) /*!< RXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN1_SBUFCR_RXD_CR_Pos (4UL) /*!< RXD_CR (Bit 4) */
+#define CAN1_SBUFCR_RXD_CR_Msk (0xf0UL) /*!< RXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN1_SBUFCR_RXD_DLC_Pos (0UL) /*!< RXD_DLC (Bit 0) */
+#define CAN1_SBUFCR_RXD_DLC_Msk (0xfUL) /*!< RXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== SBUFDT ========================================================= */
+#define CAN1_SBUFDT_RXD_BYTE3_Pos (24UL) /*!< RXD_BYTE3 (Bit 24) */
+#define CAN1_SBUFDT_RXD_BYTE3_Msk (0xff000000UL) /*!< RXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN1_SBUFDT_RXD_BYTE2_Pos (16UL) /*!< RXD_BYTE2 (Bit 16) */
+#define CAN1_SBUFDT_RXD_BYTE2_Msk (0xff0000UL) /*!< RXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN1_SBUFDT_RXD_BYTE1_Pos (8UL) /*!< RXD_BYTE1 (Bit 8) */
+#define CAN1_SBUFDT_RXD_BYTE1_Msk (0xff00UL) /*!< RXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN1_SBUFDT_RXD_BYTE0_Pos (0UL) /*!< RXD_BYTE0 (Bit 0) */
+#define CAN1_SBUFDT_RXD_BYTE0_Msk (0xffUL) /*!< RXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ========================================================= TSCR ========================================================== */
+#define CAN1_TSCR_TSP_Pos (20UL) /*!< TSP (Bit 20) */
+#define CAN1_TSCR_TSP_Msk (0xf00000UL) /*!< TSP (Bitfield-Mask: 0x0f) */
+#define CAN1_TSCR_TSS_Pos (16UL) /*!< TSS (Bit 16) */
+#define CAN1_TSCR_TSS_Msk (0xf0000UL) /*!< TSS (Bitfield-Mask: 0x0f) */
+/* ========================================================== TSC ========================================================== */
+#define CAN1_TSC_TSC_Pos (0UL) /*!< TSC (Bit 0) */
+#define CAN1_TSC_TSC_Msk (0xffffUL) /*!< TSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= RTOP ========================================================== */
+#define CAN1_RTOP_RTOE_Pos (24UL) /*!< RTOE (Bit 24) */
+#define CAN1_RTOP_RTOE_Msk (0x1000000UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define CAN1_RTOP_RTOP_Pos (0UL) /*!< RTOP (Bit 0) */
+#define CAN1_RTOP_RTOP_Msk (0xffffUL) /*!< RTOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= RTOC ========================================================== */
+#define CAN1_RTOC_RTOC_Pos (0UL) /*!< RTOC (Bit 0) */
+#define CAN1_RTOC_RTOC_Msk (0xffffUL) /*!< RTOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= STOP ========================================================== */
+#define CAN1_STOP_STOE_Pos (24UL) /*!< STOE (Bit 24) */
+#define CAN1_STOP_STOE_Msk (0x1000000UL) /*!< STOE (Bitfield-Mask: 0x01) */
+#define CAN1_STOP_STOP_Pos (0UL) /*!< STOP (Bit 0) */
+#define CAN1_STOP_STOP_Msk (0xffffUL) /*!< STOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= STOC ========================================================== */
+#define CAN1_STOC_STOC_Pos (0UL) /*!< STOC (Bit 0) */
+#define CAN1_STOC_STOC_Msk (0xffffUL) /*!< STOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= ETOP ========================================================== */
+#define CAN1_ETOP_ETOE_Pos (24UL) /*!< ETOE (Bit 24) */
+#define CAN1_ETOP_ETOE_Msk (0x1000000UL) /*!< ETOE (Bitfield-Mask: 0x01) */
+#define CAN1_ETOP_ETOP_Pos (0UL) /*!< ETOP (Bit 0) */
+#define CAN1_ETOP_ETOP_Msk (0xffffUL) /*!< ETOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= ETOC ========================================================== */
+#define CAN1_ETOC_ETOC_Pos (0UL) /*!< ETOC (Bit 0) */
+#define CAN1_ETOC_ETOC_Msk (0xffffUL) /*!< ETOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CTOP ========================================================== */
+#define CAN1_CTOP_CTOE_Pos (24UL) /*!< CTOE (Bit 24) */
+#define CAN1_CTOP_CTOE_Msk (0x1000000UL) /*!< CTOE (Bitfield-Mask: 0x01) */
+#define CAN1_CTOP_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */
+#define CAN1_CTOP_CTOP_Msk (0xffffUL) /*!< CTOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= CTOC ========================================================== */
+#define CAN1_CTOC_CTOC_Pos (0UL) /*!< CTOC (Bit 0) */
+#define CAN1_CTOC_CTOC_Msk (0xffffUL) /*!< CTOC (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR7 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR7_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR7_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR7_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR7_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR7_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR7_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR7_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR7_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR7_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR7_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR7_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR7_CR1_MMS_Msk (0x3UL) /*!< MMS (Bitfield-Mask: 0x03) */
+/* ========================================================== IER ========================================================== */
+#define TMR7_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR7_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR7_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR7_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR7_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR7_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR7_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR7_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR7_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR7_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================== TCR ========================================================== */
+#define TMR7_TCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR7_TCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR7_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR7_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR7_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR7_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR7_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR7_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR8 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR8_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR8_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR8_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR8_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR8_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR8_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR8_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR8_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR8_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR8_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR8_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR8_CR1_MMS_Msk (0x3UL) /*!< MMS (Bitfield-Mask: 0x03) */
+/* ========================================================== IER ========================================================== */
+#define TMR8_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR8_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR8_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR8_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR8_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR8_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR8_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR8_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR8_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR8_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================== TCR ========================================================== */
+#define TMR8_TCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR8_TCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR8_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR8_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR8_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR8_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR8_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR8_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR9 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR9_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR9_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR9_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR9_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR9_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_CMS_Pos (5UL) /*!< CMS (Bit 5) */
+#define TMR9_CR0_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */
+#define TMR9_CR0_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+#define TMR9_CR0_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR9_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR9_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR9_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR9_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR9_CR1_OIS3N_Pos (15UL) /*!< OIS3N (Bit 15) */
+#define TMR9_CR1_OIS3N_Msk (0x8000UL) /*!< OIS3N (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS3_Pos (14UL) /*!< OIS3 (Bit 14) */
+#define TMR9_CR1_OIS3_Msk (0x4000UL) /*!< OIS3 (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS2N_Pos (13UL) /*!< OIS2N (Bit 13) */
+#define TMR9_CR1_OIS2N_Msk (0x2000UL) /*!< OIS2N (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS2_Pos (12UL) /*!< OIS2 (Bit 12) */
+#define TMR9_CR1_OIS2_Msk (0x1000UL) /*!< OIS2 (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS1N_Pos (11UL) /*!< OIS1N (Bit 11) */
+#define TMR9_CR1_OIS1N_Msk (0x800UL) /*!< OIS1N (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS1_Pos (10UL) /*!< OIS1 (Bit 10) */
+#define TMR9_CR1_OIS1_Msk (0x400UL) /*!< OIS1 (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS0N_Pos (9UL) /*!< OIS0N (Bit 9) */
+#define TMR9_CR1_OIS0N_Msk (0x200UL) /*!< OIS0N (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS0_Pos (8UL) /*!< OIS0 (Bit 8) */
+#define TMR9_CR1_OIS0_Msk (0x100UL) /*!< OIS0 (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR9_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR9_SCR_ETS_Pos (24UL) /*!< ETS (Bit 24) */
+#define TMR9_SCR_ETS_Msk (0xf000000UL) /*!< ETS (Bitfield-Mask: 0x0f) */
+#define TMR9_SCR_EE_Pos (22UL) /*!< EE (Bit 22) */
+#define TMR9_SCR_EE_Msk (0x400000UL) /*!< EE (Bitfield-Mask: 0x01) */
+#define TMR9_SCR_EMS_Pos (20UL) /*!< EMS (Bit 20) */
+#define TMR9_SCR_EMS_Msk (0x300000UL) /*!< EMS (Bitfield-Mask: 0x03) */
+#define TMR9_SCR_EFS_Pos (16UL) /*!< EFS (Bit 16) */
+#define TMR9_SCR_EFS_Msk (0xf0000UL) /*!< EFS (Bitfield-Mask: 0x0f) */
+#define TMR9_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR9_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR9_SCR_FE_Pos (7UL) /*!< FE (Bit 7) */
+#define TMR9_SCR_FE_Msk (0x80UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define TMR9_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR9_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR9_IER_BIE_Pos (11UL) /*!< BIE (Bit 11) */
+#define TMR9_IER_BIE_Msk (0x800UL) /*!< BIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR9_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR9_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR9_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C3OIE_Pos (7UL) /*!< C3OIE (Bit 7) */
+#define TMR9_IER_C3OIE_Msk (0x80UL) /*!< C3OIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C3MIE_Pos (6UL) /*!< C3MIE (Bit 6) */
+#define TMR9_IER_C3MIE_Msk (0x40UL) /*!< C3MIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C2OIE_Pos (5UL) /*!< C2OIE (Bit 5) */
+#define TMR9_IER_C2OIE_Msk (0x20UL) /*!< C2OIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C2MIE_Pos (4UL) /*!< C2MIE (Bit 4) */
+#define TMR9_IER_C2MIE_Msk (0x10UL) /*!< C2MIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR9_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR9_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR9_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR9_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR9_SR_B1IF_Pos (13UL) /*!< B1IF (Bit 13) */
+#define TMR9_SR_B1IF_Msk (0x2000UL) /*!< B1IF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_SBIF_Pos (12UL) /*!< SBIF (Bit 12) */
+#define TMR9_SR_SBIF_Msk (0x1000UL) /*!< SBIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_B0IF_Pos (11UL) /*!< B0IF (Bit 11) */
+#define TMR9_SR_B0IF_Msk (0x800UL) /*!< B0IF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR9_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR9_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR9_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC3OIF_Pos (7UL) /*!< CC3OIF (Bit 7) */
+#define TMR9_SR_CC3OIF_Msk (0x80UL) /*!< CC3OIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC3MIF_Pos (6UL) /*!< CC3MIF (Bit 6) */
+#define TMR9_SR_CC3MIF_Msk (0x40UL) /*!< CC3MIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC2OIF_Pos (5UL) /*!< CC2OIF (Bit 5) */
+#define TMR9_SR_CC2OIF_Msk (0x20UL) /*!< CC2OIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC2MIF_Pos (4UL) /*!< CC2MIF (Bit 4) */
+#define TMR9_SR_CC2MIF_Msk (0x10UL) /*!< CC2MIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR9_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR9_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR9_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR9_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR9_UGR_CC3UG_Pos (7UL) /*!< CC3UG (Bit 7) */
+#define TMR9_UGR_CC3UG_Msk (0x80UL) /*!< CC3UG (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_CC2UG_Pos (6UL) /*!< CC2UG (Bit 6) */
+#define TMR9_UGR_CC2UG_Msk (0x40UL) /*!< CC2UG (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR9_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR9_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_B1G_Pos (3UL) /*!< B1G (Bit 3) */
+#define TMR9_UGR_B1G_Msk (0x8UL) /*!< B1G (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_B0G_Pos (2UL) /*!< B0G (Bit 2) */
+#define TMR9_UGR_B0G_Msk (0x4UL) /*!< B0G (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR9_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR9_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR9_CCMR_OC3M_Pos (28UL) /*!< OC3M (Bit 28) */
+#define TMR9_CCMR_OC3M_Msk (0xf0000000UL) /*!< OC3M (Bitfield-Mask: 0x0f) */
+#define TMR9_CCMR_CC3PE_Pos (26UL) /*!< CC3PE (Bit 26) */
+#define TMR9_CCMR_CC3PE_Msk (0xc000000UL) /*!< CC3PE (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_CC3S_Pos (24UL) /*!< CC3S (Bit 24) */
+#define TMR9_CCMR_CC3S_Msk (0x3000000UL) /*!< CC3S (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_OC2M_Pos (20UL) /*!< OC2M (Bit 20) */
+#define TMR9_CCMR_OC2M_Msk (0xf00000UL) /*!< OC2M (Bitfield-Mask: 0x0f) */
+#define TMR9_CCMR_CC2PE_Pos (18UL) /*!< CC2PE (Bit 18) */
+#define TMR9_CCMR_CC2PE_Msk (0xc0000UL) /*!< CC2PE (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_CC2S_Pos (16UL) /*!< CC2S (Bit 16) */
+#define TMR9_CCMR_CC2S_Msk (0x30000UL) /*!< CC2S (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR9_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR9_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR9_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR9_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR9_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR9_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR9_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR9_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR9_CCER_CC3P_Pos (14UL) /*!< CC3P (Bit 14) */
+#define TMR9_CCER_CC3P_Msk (0xc000UL) /*!< CC3P (Bitfield-Mask: 0x03) */
+#define TMR9_CCER_CC3NE_Pos (13UL) /*!< CC3NE (Bit 13) */
+#define TMR9_CCER_CC3NE_Msk (0x2000UL) /*!< CC3NE (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC3E_Pos (12UL) /*!< CC3E (Bit 12) */
+#define TMR9_CCER_CC3E_Msk (0x1000UL) /*!< CC3E (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC2P_Pos (10UL) /*!< CC2P (Bit 10) */
+#define TMR9_CCER_CC2P_Msk (0xc00UL) /*!< CC2P (Bitfield-Mask: 0x03) */
+#define TMR9_CCER_CC2NE_Pos (9UL) /*!< CC2NE (Bit 9) */
+#define TMR9_CCER_CC2NE_Msk (0x200UL) /*!< CC2NE (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC2E_Pos (8UL) /*!< CC2E (Bit 8) */
+#define TMR9_CCER_CC2E_Msk (0x100UL) /*!< CC2E (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR9_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR9_CCER_CC1NE_Pos (5UL) /*!< CC1NE (Bit 5) */
+#define TMR9_CCER_CC1NE_Msk (0x20UL) /*!< CC1NE (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR9_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR9_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR9_CCER_CC0NE_Pos (1UL) /*!< CC0NE (Bit 1) */
+#define TMR9_CCER_CC0NE_Msk (0x2UL) /*!< CC0NE (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR9_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+#define TMR9_DCR_BK1F_Pos (24UL) /*!< BK1F (Bit 24) */
+#define TMR9_DCR_BK1F_Msk (0xff000000UL) /*!< BK1F (Bitfield-Mask: 0xff) */
+#define TMR9_DCR_BK1P_Pos (23UL) /*!< BK1P (Bit 23) */
+#define TMR9_DCR_BK1P_Msk (0x800000UL) /*!< BK1P (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_BK1E_Pos (22UL) /*!< BK1E (Bit 22) */
+#define TMR9_DCR_BK1E_Msk (0x400000UL) /*!< BK1E (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_BK0F_Pos (14UL) /*!< BK0F (Bit 14) */
+#define TMR9_DCR_BK0F_Msk (0x3fc000UL) /*!< BK0F (Bitfield-Mask: 0xff) */
+#define TMR9_DCR_BK0P_Pos (13UL) /*!< BK0P (Bit 13) */
+#define TMR9_DCR_BK0P_Msk (0x2000UL) /*!< BK0P (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_BK0E_Pos (12UL) /*!< BK0E (Bit 12) */
+#define TMR9_DCR_BK0E_Msk (0x1000UL) /*!< BK0E (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_MOE_Pos (11UL) /*!< MOE (Bit 11) */
+#define TMR9_DCR_MOE_Msk (0x800UL) /*!< MOE (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_AOE_Pos (10UL) /*!< AOE (Bit 10) */
+#define TMR9_DCR_AOE_Msk (0x400UL) /*!< AOE (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_OSSR_Pos (9UL) /*!< OSSR (Bit 9) */
+#define TMR9_DCR_OSSR_Msk (0x200UL) /*!< OSSR (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_OSSI_Pos (8UL) /*!< OSSI (Bit 8) */
+#define TMR9_DCR_OSSI_Msk (0x100UL) /*!< OSSI (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_DTG_Pos (0UL) /*!< DTG (Bit 0) */
+#define TMR9_DCR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR9_TTCR_TC3E_Pos (11UL) /*!< TC3E (Bit 11) */
+#define TMR9_TTCR_TC3E_Msk (0x800UL) /*!< TC3E (Bitfield-Mask: 0x01) */
+#define TMR9_TTCR_TC2E_Pos (10UL) /*!< TC2E (Bit 10) */
+#define TMR9_TTCR_TC2E_Msk (0x400UL) /*!< TC2E (Bitfield-Mask: 0x01) */
+#define TMR9_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR9_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR9_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR9_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR9_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR9_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR9_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR9_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR9_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR9_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR9_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR9_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR9_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR9_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================== CRR ========================================================== */
+#define TMR9_CRR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define TMR9_CRR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR9_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR9_CC0R_CC0V_Msk (0xffffUL) /*!< CC0V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR9_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR9_CC1R_CC1V_Msk (0xffffUL) /*!< CC1V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC2R ========================================================== */
+#define TMR9_CC2R_CC2V_Pos (0UL) /*!< CC2V (Bit 0) */
+#define TMR9_CC2R_CC2V_Msk (0xffffUL) /*!< CC2V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC3R ========================================================== */
+#define TMR9_CC3R_CC3V_Pos (0UL) /*!< CC3V (Bit 0) */
+#define TMR9_CC3R_CC3V_Msk (0xffffUL) /*!< CC3V (Bitfield-Mask: 0xffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR9_CIR_C3TIS_Pos (24UL) /*!< C3TIS (Bit 24) */
+#define TMR9_CIR_C3TIS_Msk (0xf000000UL) /*!< C3TIS (Bitfield-Mask: 0x0f) */
+#define TMR9_CIR_C2TIS_Pos (16UL) /*!< C2TIS (Bit 16) */
+#define TMR9_CIR_C2TIS_Msk (0xf0000UL) /*!< C2TIS (Bitfield-Mask: 0x0f) */
+#define TMR9_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR9_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR9_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR9_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+/* ========================================================== BPR ========================================================== */
+#define TMR9_BPR_B1POL_Pos (16UL) /*!< B1POL (Bit 16) */
+#define TMR9_BPR_B1POL_Msk (0xffff0000UL) /*!< B1POL (Bitfield-Mask: 0xffff) */
+#define TMR9_BPR_B0POL_Pos (0UL) /*!< B0POL (Bit 0) */
+#define TMR9_BPR_B0POL_Msk (0xffffUL) /*!< B0POL (Bitfield-Mask: 0xffff) */
+/* ========================================================== BER ========================================================== */
+#define TMR9_BER_B1IEN_Pos (16UL) /*!< B1IEN (Bit 16) */
+#define TMR9_BER_B1IEN_Msk (0xffff0000UL) /*!< B1IEN (Bitfield-Mask: 0xffff) */
+#define TMR9_BER_B0IEN_Pos (0UL) /*!< B0IEN (Bit 0) */
+#define TMR9_BER_B0IEN_Msk (0xffffUL) /*!< B0IEN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR10 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR10_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR10_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR10_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR10_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR10_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_CMS_Pos (5UL) /*!< CMS (Bit 5) */
+#define TMR10_CR0_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */
+#define TMR10_CR0_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+#define TMR10_CR0_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR10_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR10_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR10_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR10_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR10_CR1_OIS3N_Pos (15UL) /*!< OIS3N (Bit 15) */
+#define TMR10_CR1_OIS3N_Msk (0x8000UL) /*!< OIS3N (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS3_Pos (14UL) /*!< OIS3 (Bit 14) */
+#define TMR10_CR1_OIS3_Msk (0x4000UL) /*!< OIS3 (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS2N_Pos (13UL) /*!< OIS2N (Bit 13) */
+#define TMR10_CR1_OIS2N_Msk (0x2000UL) /*!< OIS2N (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS2_Pos (12UL) /*!< OIS2 (Bit 12) */
+#define TMR10_CR1_OIS2_Msk (0x1000UL) /*!< OIS2 (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS1N_Pos (11UL) /*!< OIS1N (Bit 11) */
+#define TMR10_CR1_OIS1N_Msk (0x800UL) /*!< OIS1N (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS1_Pos (10UL) /*!< OIS1 (Bit 10) */
+#define TMR10_CR1_OIS1_Msk (0x400UL) /*!< OIS1 (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS0N_Pos (9UL) /*!< OIS0N (Bit 9) */
+#define TMR10_CR1_OIS0N_Msk (0x200UL) /*!< OIS0N (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS0_Pos (8UL) /*!< OIS0 (Bit 8) */
+#define TMR10_CR1_OIS0_Msk (0x100UL) /*!< OIS0 (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR10_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR10_SCR_ETS_Pos (24UL) /*!< ETS (Bit 24) */
+#define TMR10_SCR_ETS_Msk (0xf000000UL) /*!< ETS (Bitfield-Mask: 0x0f) */
+#define TMR10_SCR_EE_Pos (22UL) /*!< EE (Bit 22) */
+#define TMR10_SCR_EE_Msk (0x400000UL) /*!< EE (Bitfield-Mask: 0x01) */
+#define TMR10_SCR_EMS_Pos (20UL) /*!< EMS (Bit 20) */
+#define TMR10_SCR_EMS_Msk (0x300000UL) /*!< EMS (Bitfield-Mask: 0x03) */
+#define TMR10_SCR_EFS_Pos (16UL) /*!< EFS (Bit 16) */
+#define TMR10_SCR_EFS_Msk (0xf0000UL) /*!< EFS (Bitfield-Mask: 0x0f) */
+#define TMR10_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR10_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR10_SCR_FE_Pos (7UL) /*!< FE (Bit 7) */
+#define TMR10_SCR_FE_Msk (0x80UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define TMR10_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR10_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR10_IER_BIE_Pos (11UL) /*!< BIE (Bit 11) */
+#define TMR10_IER_BIE_Msk (0x800UL) /*!< BIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR10_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR10_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR10_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C3OIE_Pos (7UL) /*!< C3OIE (Bit 7) */
+#define TMR10_IER_C3OIE_Msk (0x80UL) /*!< C3OIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C3MIE_Pos (6UL) /*!< C3MIE (Bit 6) */
+#define TMR10_IER_C3MIE_Msk (0x40UL) /*!< C3MIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C2OIE_Pos (5UL) /*!< C2OIE (Bit 5) */
+#define TMR10_IER_C2OIE_Msk (0x20UL) /*!< C2OIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C2MIE_Pos (4UL) /*!< C2MIE (Bit 4) */
+#define TMR10_IER_C2MIE_Msk (0x10UL) /*!< C2MIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR10_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR10_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR10_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR10_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR10_SR_B1IF_Pos (13UL) /*!< B1IF (Bit 13) */
+#define TMR10_SR_B1IF_Msk (0x2000UL) /*!< B1IF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_SBIF_Pos (12UL) /*!< SBIF (Bit 12) */
+#define TMR10_SR_SBIF_Msk (0x1000UL) /*!< SBIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_B0IF_Pos (11UL) /*!< B0IF (Bit 11) */
+#define TMR10_SR_B0IF_Msk (0x800UL) /*!< B0IF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR10_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR10_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR10_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC3OIF_Pos (7UL) /*!< CC3OIF (Bit 7) */
+#define TMR10_SR_CC3OIF_Msk (0x80UL) /*!< CC3OIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC3MIF_Pos (6UL) /*!< CC3MIF (Bit 6) */
+#define TMR10_SR_CC3MIF_Msk (0x40UL) /*!< CC3MIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC2OIF_Pos (5UL) /*!< CC2OIF (Bit 5) */
+#define TMR10_SR_CC2OIF_Msk (0x20UL) /*!< CC2OIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC2MIF_Pos (4UL) /*!< CC2MIF (Bit 4) */
+#define TMR10_SR_CC2MIF_Msk (0x10UL) /*!< CC2MIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR10_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR10_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR10_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR10_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR10_UGR_CC3UG_Pos (7UL) /*!< CC3UG (Bit 7) */
+#define TMR10_UGR_CC3UG_Msk (0x80UL) /*!< CC3UG (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_CC2UG_Pos (6UL) /*!< CC2UG (Bit 6) */
+#define TMR10_UGR_CC2UG_Msk (0x40UL) /*!< CC2UG (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR10_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR10_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_B1G_Pos (3UL) /*!< B1G (Bit 3) */
+#define TMR10_UGR_B1G_Msk (0x8UL) /*!< B1G (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_B0G_Pos (2UL) /*!< B0G (Bit 2) */
+#define TMR10_UGR_B0G_Msk (0x4UL) /*!< B0G (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR10_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR10_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR10_CCMR_OC3M_Pos (28UL) /*!< OC3M (Bit 28) */
+#define TMR10_CCMR_OC3M_Msk (0xf0000000UL) /*!< OC3M (Bitfield-Mask: 0x0f) */
+#define TMR10_CCMR_CC3PE_Pos (26UL) /*!< CC3PE (Bit 26) */
+#define TMR10_CCMR_CC3PE_Msk (0xc000000UL) /*!< CC3PE (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_CC3S_Pos (24UL) /*!< CC3S (Bit 24) */
+#define TMR10_CCMR_CC3S_Msk (0x3000000UL) /*!< CC3S (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_OC2M_Pos (20UL) /*!< OC2M (Bit 20) */
+#define TMR10_CCMR_OC2M_Msk (0xf00000UL) /*!< OC2M (Bitfield-Mask: 0x0f) */
+#define TMR10_CCMR_CC2PE_Pos (18UL) /*!< CC2PE (Bit 18) */
+#define TMR10_CCMR_CC2PE_Msk (0xc0000UL) /*!< CC2PE (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_CC2S_Pos (16UL) /*!< CC2S (Bit 16) */
+#define TMR10_CCMR_CC2S_Msk (0x30000UL) /*!< CC2S (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR10_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR10_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR10_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR10_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR10_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR10_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR10_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR10_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR10_CCER_CC3P_Pos (14UL) /*!< CC3P (Bit 14) */
+#define TMR10_CCER_CC3P_Msk (0xc000UL) /*!< CC3P (Bitfield-Mask: 0x03) */
+#define TMR10_CCER_CC3NE_Pos (13UL) /*!< CC3NE (Bit 13) */
+#define TMR10_CCER_CC3NE_Msk (0x2000UL) /*!< CC3NE (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC3E_Pos (12UL) /*!< CC3E (Bit 12) */
+#define TMR10_CCER_CC3E_Msk (0x1000UL) /*!< CC3E (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC2P_Pos (10UL) /*!< CC2P (Bit 10) */
+#define TMR10_CCER_CC2P_Msk (0xc00UL) /*!< CC2P (Bitfield-Mask: 0x03) */
+#define TMR10_CCER_CC2NE_Pos (9UL) /*!< CC2NE (Bit 9) */
+#define TMR10_CCER_CC2NE_Msk (0x200UL) /*!< CC2NE (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC2E_Pos (8UL) /*!< CC2E (Bit 8) */
+#define TMR10_CCER_CC2E_Msk (0x100UL) /*!< CC2E (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR10_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR10_CCER_CC1NE_Pos (5UL) /*!< CC1NE (Bit 5) */
+#define TMR10_CCER_CC1NE_Msk (0x20UL) /*!< CC1NE (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR10_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR10_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR10_CCER_CC0NE_Pos (1UL) /*!< CC0NE (Bit 1) */
+#define TMR10_CCER_CC0NE_Msk (0x2UL) /*!< CC0NE (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR10_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+#define TMR10_DCR_BK1F_Pos (24UL) /*!< BK1F (Bit 24) */
+#define TMR10_DCR_BK1F_Msk (0xff000000UL) /*!< BK1F (Bitfield-Mask: 0xff) */
+#define TMR10_DCR_BK1P_Pos (23UL) /*!< BK1P (Bit 23) */
+#define TMR10_DCR_BK1P_Msk (0x800000UL) /*!< BK1P (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_BK1E_Pos (22UL) /*!< BK1E (Bit 22) */
+#define TMR10_DCR_BK1E_Msk (0x400000UL) /*!< BK1E (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_BK0F_Pos (14UL) /*!< BK0F (Bit 14) */
+#define TMR10_DCR_BK0F_Msk (0x3fc000UL) /*!< BK0F (Bitfield-Mask: 0xff) */
+#define TMR10_DCR_BK0P_Pos (13UL) /*!< BK0P (Bit 13) */
+#define TMR10_DCR_BK0P_Msk (0x2000UL) /*!< BK0P (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_BK0E_Pos (12UL) /*!< BK0E (Bit 12) */
+#define TMR10_DCR_BK0E_Msk (0x1000UL) /*!< BK0E (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_MOE_Pos (11UL) /*!< MOE (Bit 11) */
+#define TMR10_DCR_MOE_Msk (0x800UL) /*!< MOE (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_AOE_Pos (10UL) /*!< AOE (Bit 10) */
+#define TMR10_DCR_AOE_Msk (0x400UL) /*!< AOE (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_OSSR_Pos (9UL) /*!< OSSR (Bit 9) */
+#define TMR10_DCR_OSSR_Msk (0x200UL) /*!< OSSR (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_OSSI_Pos (8UL) /*!< OSSI (Bit 8) */
+#define TMR10_DCR_OSSI_Msk (0x100UL) /*!< OSSI (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_DTG_Pos (0UL) /*!< DTG (Bit 0) */
+#define TMR10_DCR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR10_TTCR_TC3E_Pos (11UL) /*!< TC3E (Bit 11) */
+#define TMR10_TTCR_TC3E_Msk (0x800UL) /*!< TC3E (Bitfield-Mask: 0x01) */
+#define TMR10_TTCR_TC2E_Pos (10UL) /*!< TC2E (Bit 10) */
+#define TMR10_TTCR_TC2E_Msk (0x400UL) /*!< TC2E (Bitfield-Mask: 0x01) */
+#define TMR10_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR10_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR10_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR10_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR10_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR10_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR10_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR10_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR10_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR10_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR10_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR10_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR10_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR10_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================== CRR ========================================================== */
+#define TMR10_CRR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define TMR10_CRR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR10_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR10_CC0R_CC0V_Msk (0xffffUL) /*!< CC0V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR10_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR10_CC1R_CC1V_Msk (0xffffUL) /*!< CC1V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC2R ========================================================== */
+#define TMR10_CC2R_CC2V_Pos (0UL) /*!< CC2V (Bit 0) */
+#define TMR10_CC2R_CC2V_Msk (0xffffUL) /*!< CC2V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC3R ========================================================== */
+#define TMR10_CC3R_CC3V_Pos (0UL) /*!< CC3V (Bit 0) */
+#define TMR10_CC3R_CC3V_Msk (0xffffUL) /*!< CC3V (Bitfield-Mask: 0xffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR10_CIR_C3TIS_Pos (24UL) /*!< C3TIS (Bit 24) */
+#define TMR10_CIR_C3TIS_Msk (0xf000000UL) /*!< C3TIS (Bitfield-Mask: 0x0f) */
+#define TMR10_CIR_C2TIS_Pos (16UL) /*!< C2TIS (Bit 16) */
+#define TMR10_CIR_C2TIS_Msk (0xf0000UL) /*!< C2TIS (Bitfield-Mask: 0x0f) */
+#define TMR10_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR10_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR10_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR10_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+/* ========================================================== BPR ========================================================== */
+#define TMR10_BPR_B1POL_Pos (16UL) /*!< B1POL (Bit 16) */
+#define TMR10_BPR_B1POL_Msk (0xffff0000UL) /*!< B1POL (Bitfield-Mask: 0xffff) */
+#define TMR10_BPR_B0POL_Pos (0UL) /*!< B0POL (Bit 0) */
+#define TMR10_BPR_B0POL_Msk (0xffffUL) /*!< B0POL (Bitfield-Mask: 0xffff) */
+/* ========================================================== BER ========================================================== */
+#define TMR10_BER_B1IEN_Pos (16UL) /*!< B1IEN (Bit 16) */
+#define TMR10_BER_B1IEN_Msk (0xffff0000UL) /*!< B1IEN (Bitfield-Mask: 0xffff) */
+#define TMR10_BER_B0IEN_Pos (0UL) /*!< B0IEN (Bit 0) */
+#define TMR10_BER_B0IEN_Msk (0xffffUL) /*!< B0IEN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ ADC0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define ADC0_CR_ADCALDIF_Pos (7UL) /*!< ADCALDIF (Bit 7) */
+#define ADC0_CR_ADCALDIF_Msk (0x80UL) /*!< ADCALDIF (Bitfield-Mask: 0x01) */
+#define ADC0_CR_ADCAL_Pos (6UL) /*!< ADCAL (Bit 6) */
+#define ADC0_CR_ADCAL_Msk (0x40UL) /*!< ADCAL (Bitfield-Mask: 0x01) */
+#define ADC0_CR_JADSTP_Pos (5UL) /*!< JADSTP (Bit 5) */
+#define ADC0_CR_JADSTP_Msk (0x20UL) /*!< JADSTP (Bitfield-Mask: 0x01) */
+#define ADC0_CR_ADSTP_Pos (4UL) /*!< ADSTP (Bit 4) */
+#define ADC0_CR_ADSTP_Msk (0x10UL) /*!< ADSTP (Bitfield-Mask: 0x01) */
+#define ADC0_CR_JADSTART_Pos (3UL) /*!< JADSTART (Bit 3) */
+#define ADC0_CR_JADSTART_Msk (0x8UL) /*!< JADSTART (Bitfield-Mask: 0x01) */
+#define ADC0_CR_ADSTART_Pos (2UL) /*!< ADSTART (Bit 2) */
+#define ADC0_CR_ADSTART_Msk (0x4UL) /*!< ADSTART (Bitfield-Mask: 0x01) */
+#define ADC0_CR_ADDIS_Pos (1UL) /*!< ADDIS (Bit 1) */
+#define ADC0_CR_ADDIS_Msk (0x2UL) /*!< ADDIS (Bitfield-Mask: 0x01) */
+#define ADC0_CR_ADEN_Pos (0UL) /*!< ADEN (Bit 0) */
+#define ADC0_CR_ADEN_Msk (0x1UL) /*!< ADEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR0 ========================================================= */
+#define ADC0_CFGR0_OVSCAL_Pos (28UL) /*!< OVSCAL (Bit 28) */
+#define ADC0_CFGR0_OVSCAL_Msk (0x70000000UL) /*!< OVSCAL (Bitfield-Mask: 0x07) */
+#define ADC0_CFGR0_CONT_Pos (23UL) /*!< CONT (Bit 23) */
+#define ADC0_CFGR0_CONT_Msk (0x800000UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_JAUTO_Pos (22UL) /*!< JAUTO (Bit 22) */
+#define ADC0_CFGR0_JAUTO_Msk (0x400000UL) /*!< JAUTO (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_JDISCEN_Pos (20UL) /*!< JDISCEN (Bit 20) */
+#define ADC0_CFGR0_JDISCEN_Msk (0x100000UL) /*!< JDISCEN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_DISCNUM_Pos (17UL) /*!< DISCNUM (Bit 17) */
+#define ADC0_CFGR0_DISCNUM_Msk (0xe0000UL) /*!< DISCNUM (Bitfield-Mask: 0x07) */
+#define ADC0_CFGR0_DISCEN_Pos (16UL) /*!< DISCEN (Bit 16) */
+#define ADC0_CFGR0_DISCEN_Msk (0x10000UL) /*!< DISCEN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_OVRMOD_Pos (15UL) /*!< OVRMOD (Bit 15) */
+#define ADC0_CFGR0_OVRMOD_Msk (0x8000UL) /*!< OVRMOD (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_SDMAEN_Pos (14UL) /*!< SDMAEN (Bit 14) */
+#define ADC0_CFGR0_SDMAEN_Msk (0x4000UL) /*!< SDMAEN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_TROVS_Pos (12UL) /*!< TROVS (Bit 12) */
+#define ADC0_CFGR0_TROVS_Msk (0x1000UL) /*!< TROVS (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_OVSS_Pos (8UL) /*!< OVSS (Bit 8) */
+#define ADC0_CFGR0_OVSS_Msk (0xf00UL) /*!< OVSS (Bitfield-Mask: 0x0f) */
+#define ADC0_CFGR0_ROVSM_Pos (7UL) /*!< ROVSM (Bit 7) */
+#define ADC0_CFGR0_ROVSM_Msk (0x80UL) /*!< ROVSM (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_OVSR_Pos (4UL) /*!< OVSR (Bit 4) */
+#define ADC0_CFGR0_OVSR_Msk (0x70UL) /*!< OVSR (Bitfield-Mask: 0x07) */
+#define ADC0_CFGR0_JOVSE_Pos (1UL) /*!< JOVSE (Bit 1) */
+#define ADC0_CFGR0_JOVSE_Msk (0x2UL) /*!< JOVSE (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_ROVSE_Pos (0UL) /*!< ROVSE (Bit 0) */
+#define ADC0_CFGR0_ROVSE_Msk (0x1UL) /*!< ROVSE (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR1 ========================================================= */
+#define ADC0_CFGR1_JAWD2EN_Pos (14UL) /*!< JAWD2EN (Bit 14) */
+#define ADC0_CFGR1_JAWD2EN_Msk (0x4000UL) /*!< JAWD2EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_JAWD1EN_Pos (13UL) /*!< JAWD1EN (Bit 13) */
+#define ADC0_CFGR1_JAWD1EN_Msk (0x2000UL) /*!< JAWD1EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_JAWD0EN_Pos (12UL) /*!< JAWD0EN (Bit 12) */
+#define ADC0_CFGR1_JAWD0EN_Msk (0x1000UL) /*!< JAWD0EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_AWD2EN_Pos (10UL) /*!< AWD2EN (Bit 10) */
+#define ADC0_CFGR1_AWD2EN_Msk (0x400UL) /*!< AWD2EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_AWD1EN_Pos (9UL) /*!< AWD1EN (Bit 9) */
+#define ADC0_CFGR1_AWD1EN_Msk (0x200UL) /*!< AWD1EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_AWD0EN_Pos (8UL) /*!< AWD0EN (Bit 8) */
+#define ADC0_CFGR1_AWD0EN_Msk (0x100UL) /*!< AWD0EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_ISEL_Pos (4UL) /*!< ISEL (Bit 4) */
+#define ADC0_CFGR1_ISEL_Msk (0x30UL) /*!< ISEL (Bitfield-Mask: 0x03) */
+#define ADC0_CFGR1_CHEN_Pos (3UL) /*!< CHEN (Bit 3) */
+#define ADC0_CFGR1_CHEN_Msk (0x8UL) /*!< CHEN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_REFEN_Pos (1UL) /*!< REFEN (Bit 1) */
+#define ADC0_CFGR1_REFEN_Msk (0x2UL) /*!< REFEN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_BIASEN_Pos (0UL) /*!< BIASEN (Bit 0) */
+#define ADC0_CFGR1_BIASEN_Msk (0x1UL) /*!< BIASEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define ADC0_ISR_EOSMP_Pos (9UL) /*!< EOSMP (Bit 9) */
+#define ADC0_ISR_EOSMP_Msk (0x200UL) /*!< EOSMP (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_ADRDY_Pos (8UL) /*!< ADRDY (Bit 8) */
+#define ADC0_ISR_ADRDY_Msk (0x100UL) /*!< ADRDY (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_AWD2_Pos (7UL) /*!< AWD2 (Bit 7) */
+#define ADC0_ISR_AWD2_Msk (0x80UL) /*!< AWD2 (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_AWD1_Pos (6UL) /*!< AWD1 (Bit 6) */
+#define ADC0_ISR_AWD1_Msk (0x40UL) /*!< AWD1 (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_AWD0_Pos (5UL) /*!< AWD0 (Bit 5) */
+#define ADC0_ISR_AWD0_Msk (0x20UL) /*!< AWD0 (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_OVR_Pos (4UL) /*!< OVR (Bit 4) */
+#define ADC0_ISR_OVR_Msk (0x10UL) /*!< OVR (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_JEOS_Pos (3UL) /*!< JEOS (Bit 3) */
+#define ADC0_ISR_JEOS_Msk (0x8UL) /*!< JEOS (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_JEOC_Pos (2UL) /*!< JEOC (Bit 2) */
+#define ADC0_ISR_JEOC_Msk (0x4UL) /*!< JEOC (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */
+#define ADC0_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */
+#define ADC0_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define ADC0_IER_EOSMPIE_Pos (9UL) /*!< EOSMPIE (Bit 9) */
+#define ADC0_IER_EOSMPIE_Msk (0x200UL) /*!< EOSMPIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_ADRDYIE_Pos (8UL) /*!< ADRDYIE (Bit 8) */
+#define ADC0_IER_ADRDYIE_Msk (0x100UL) /*!< ADRDYIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_AWD2IE_Pos (7UL) /*!< AWD2IE (Bit 7) */
+#define ADC0_IER_AWD2IE_Msk (0x80UL) /*!< AWD2IE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_AWD1IE_Pos (6UL) /*!< AWD1IE (Bit 6) */
+#define ADC0_IER_AWD1IE_Msk (0x40UL) /*!< AWD1IE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_AWD0IE_Pos (5UL) /*!< AWD0IE (Bit 5) */
+#define ADC0_IER_AWD0IE_Msk (0x20UL) /*!< AWD0IE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_OVRIE_Pos (4UL) /*!< OVRIE (Bit 4) */
+#define ADC0_IER_OVRIE_Msk (0x10UL) /*!< OVRIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_JEOSIE_Pos (3UL) /*!< JEOSIE (Bit 3) */
+#define ADC0_IER_JEOSIE_Msk (0x8UL) /*!< JEOSIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_JEOCIE_Pos (2UL) /*!< JEOCIE (Bit 2) */
+#define ADC0_IER_JEOCIE_Msk (0x4UL) /*!< JEOCIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_EOSIE_Pos (1UL) /*!< EOSIE (Bit 1) */
+#define ADC0_IER_EOSIE_Msk (0x2UL) /*!< EOSIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_EOCIE_Pos (0UL) /*!< EOCIE (Bit 0) */
+#define ADC0_IER_EOCIE_Msk (0x1UL) /*!< EOCIE (Bitfield-Mask: 0x01) */
+/* ======================================================== SIGSEL ========================================================= */
+#define ADC0_SIGSEL_SIGSEL_Pos (0UL) /*!< SIGSEL (Bit 0) */
+#define ADC0_SIGSEL_SIGSEL_Msk (0xfffffUL) /*!< SIGSEL (Bitfield-Mask: 0xfffff) */
+/* ========================================================= SMPR0 ========================================================= */
+#define ADC0_SMPR0_SMP7_Pos (28UL) /*!< SMP7 (Bit 28) */
+#define ADC0_SMPR0_SMP7_Msk (0x70000000UL) /*!< SMP7 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP6_Pos (24UL) /*!< SMP6 (Bit 24) */
+#define ADC0_SMPR0_SMP6_Msk (0x7000000UL) /*!< SMP6 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP5_Pos (20UL) /*!< SMP5 (Bit 20) */
+#define ADC0_SMPR0_SMP5_Msk (0x700000UL) /*!< SMP5 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP4_Pos (16UL) /*!< SMP4 (Bit 16) */
+#define ADC0_SMPR0_SMP4_Msk (0x70000UL) /*!< SMP4 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP3_Pos (12UL) /*!< SMP3 (Bit 12) */
+#define ADC0_SMPR0_SMP3_Msk (0x7000UL) /*!< SMP3 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP2_Pos (8UL) /*!< SMP2 (Bit 8) */
+#define ADC0_SMPR0_SMP2_Msk (0x700UL) /*!< SMP2 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP1_Pos (4UL) /*!< SMP1 (Bit 4) */
+#define ADC0_SMPR0_SMP1_Msk (0x70UL) /*!< SMP1 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP0_Pos (0UL) /*!< SMP0 (Bit 0) */
+#define ADC0_SMPR0_SMP0_Msk (0x7UL) /*!< SMP0 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR1 ========================================================= */
+#define ADC0_SMPR1_SMP15_Pos (28UL) /*!< SMP15 (Bit 28) */
+#define ADC0_SMPR1_SMP15_Msk (0x70000000UL) /*!< SMP15 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP14_Pos (24UL) /*!< SMP14 (Bit 24) */
+#define ADC0_SMPR1_SMP14_Msk (0x7000000UL) /*!< SMP14 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP13_Pos (20UL) /*!< SMP13 (Bit 20) */
+#define ADC0_SMPR1_SMP13_Msk (0x700000UL) /*!< SMP13 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP12_Pos (16UL) /*!< SMP12 (Bit 16) */
+#define ADC0_SMPR1_SMP12_Msk (0x70000UL) /*!< SMP12 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP11_Pos (12UL) /*!< SMP11 (Bit 12) */
+#define ADC0_SMPR1_SMP11_Msk (0x7000UL) /*!< SMP11 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP10_Pos (8UL) /*!< SMP10 (Bit 8) */
+#define ADC0_SMPR1_SMP10_Msk (0x700UL) /*!< SMP10 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP9_Pos (4UL) /*!< SMP9 (Bit 4) */
+#define ADC0_SMPR1_SMP9_Msk (0x70UL) /*!< SMP9 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP8_Pos (0UL) /*!< SMP8 (Bit 0) */
+#define ADC0_SMPR1_SMP8_Msk (0x7UL) /*!< SMP8 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR2 ========================================================= */
+#define ADC0_SMPR2_SMP19_Pos (12UL) /*!< SMP19 (Bit 12) */
+#define ADC0_SMPR2_SMP19_Msk (0x7000UL) /*!< SMP19 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR2_SMP18_Pos (8UL) /*!< SMP18 (Bit 8) */
+#define ADC0_SMPR2_SMP18_Msk (0x700UL) /*!< SMP18 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR2_SMP17_Pos (4UL) /*!< SMP17 (Bit 4) */
+#define ADC0_SMPR2_SMP17_Msk (0x70UL) /*!< SMP17 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR2_SMP16_Pos (0UL) /*!< SMP16 (Bit 0) */
+#define ADC0_SMPR2_SMP16_Msk (0x7UL) /*!< SMP16 (Bitfield-Mask: 0x07) */
+/* ========================================================= CALR0 ========================================================= */
+#define ADC0_CALR0_SAT7_Pos (31UL) /*!< SAT7 (Bit 31) */
+#define ADC0_CALR0_SAT7_Msk (0x80000000UL) /*!< SAT7 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL7_Pos (28UL) /*!< CAL7 (Bit 28) */
+#define ADC0_CALR0_CAL7_Msk (0x30000000UL) /*!< CAL7 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT6_Pos (27UL) /*!< SAT6 (Bit 27) */
+#define ADC0_CALR0_SAT6_Msk (0x8000000UL) /*!< SAT6 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL6_Pos (24UL) /*!< CAL6 (Bit 24) */
+#define ADC0_CALR0_CAL6_Msk (0x3000000UL) /*!< CAL6 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT5_Pos (23UL) /*!< SAT5 (Bit 23) */
+#define ADC0_CALR0_SAT5_Msk (0x800000UL) /*!< SAT5 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL5_Pos (20UL) /*!< CAL5 (Bit 20) */
+#define ADC0_CALR0_CAL5_Msk (0x300000UL) /*!< CAL5 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT4_Pos (19UL) /*!< SAT4 (Bit 19) */
+#define ADC0_CALR0_SAT4_Msk (0x80000UL) /*!< SAT4 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL4_Pos (16UL) /*!< CAL4 (Bit 16) */
+#define ADC0_CALR0_CAL4_Msk (0x30000UL) /*!< CAL4 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT3_Pos (15UL) /*!< SAT3 (Bit 15) */
+#define ADC0_CALR0_SAT3_Msk (0x8000UL) /*!< SAT3 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL3_Pos (12UL) /*!< CAL3 (Bit 12) */
+#define ADC0_CALR0_CAL3_Msk (0x3000UL) /*!< CAL3 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT2_Pos (11UL) /*!< SAT2 (Bit 11) */
+#define ADC0_CALR0_SAT2_Msk (0x800UL) /*!< SAT2 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL2_Pos (8UL) /*!< CAL2 (Bit 8) */
+#define ADC0_CALR0_CAL2_Msk (0x300UL) /*!< CAL2 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT1_Pos (7UL) /*!< SAT1 (Bit 7) */
+#define ADC0_CALR0_SAT1_Msk (0x80UL) /*!< SAT1 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL1_Pos (4UL) /*!< CAL1 (Bit 4) */
+#define ADC0_CALR0_CAL1_Msk (0x30UL) /*!< CAL1 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT0_Pos (3UL) /*!< SAT0 (Bit 3) */
+#define ADC0_CALR0_SAT0_Msk (0x8UL) /*!< SAT0 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL0_Pos (0UL) /*!< CAL0 (Bit 0) */
+#define ADC0_CALR0_CAL0_Msk (0x3UL) /*!< CAL0 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR1 ========================================================= */
+#define ADC0_CALR1_SAT15_Pos (31UL) /*!< SAT15 (Bit 31) */
+#define ADC0_CALR1_SAT15_Msk (0x80000000UL) /*!< SAT15 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL15_Pos (28UL) /*!< CAL15 (Bit 28) */
+#define ADC0_CALR1_CAL15_Msk (0x30000000UL) /*!< CAL15 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT14_Pos (27UL) /*!< SAT14 (Bit 27) */
+#define ADC0_CALR1_SAT14_Msk (0x8000000UL) /*!< SAT14 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL14_Pos (24UL) /*!< CAL14 (Bit 24) */
+#define ADC0_CALR1_CAL14_Msk (0x3000000UL) /*!< CAL14 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT13_Pos (23UL) /*!< SAT13 (Bit 23) */
+#define ADC0_CALR1_SAT13_Msk (0x800000UL) /*!< SAT13 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL13_Pos (20UL) /*!< CAL13 (Bit 20) */
+#define ADC0_CALR1_CAL13_Msk (0x300000UL) /*!< CAL13 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT12_Pos (19UL) /*!< SAT12 (Bit 19) */
+#define ADC0_CALR1_SAT12_Msk (0x80000UL) /*!< SAT12 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL12_Pos (16UL) /*!< CAL12 (Bit 16) */
+#define ADC0_CALR1_CAL12_Msk (0x30000UL) /*!< CAL12 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT11_Pos (15UL) /*!< SAT11 (Bit 15) */
+#define ADC0_CALR1_SAT11_Msk (0x8000UL) /*!< SAT11 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL11_Pos (12UL) /*!< CAL11 (Bit 12) */
+#define ADC0_CALR1_CAL11_Msk (0x3000UL) /*!< CAL11 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT10_Pos (11UL) /*!< SAT10 (Bit 11) */
+#define ADC0_CALR1_SAT10_Msk (0x800UL) /*!< SAT10 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL10_Pos (8UL) /*!< CAL10 (Bit 8) */
+#define ADC0_CALR1_CAL10_Msk (0x300UL) /*!< CAL10 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT9_Pos (7UL) /*!< SAT9 (Bit 7) */
+#define ADC0_CALR1_SAT9_Msk (0x80UL) /*!< SAT9 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL9_Pos (4UL) /*!< CAL9 (Bit 4) */
+#define ADC0_CALR1_CAL9_Msk (0x30UL) /*!< CAL9 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT8_Pos (3UL) /*!< SAT8 (Bit 3) */
+#define ADC0_CALR1_SAT8_Msk (0x8UL) /*!< SAT8 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL8_Pos (0UL) /*!< CAL8 (Bit 0) */
+#define ADC0_CALR1_CAL8_Msk (0x3UL) /*!< CAL8 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR2 ========================================================= */
+#define ADC0_CALR2_SAT19_Pos (15UL) /*!< SAT19 (Bit 15) */
+#define ADC0_CALR2_SAT19_Msk (0x8000UL) /*!< SAT19 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR2_CAL19_Pos (12UL) /*!< CAL19 (Bit 12) */
+#define ADC0_CALR2_CAL19_Msk (0x3000UL) /*!< CAL19 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR2_SAT18_Pos (11UL) /*!< SAT18 (Bit 11) */
+#define ADC0_CALR2_SAT18_Msk (0x800UL) /*!< SAT18 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR2_CAL18_Pos (8UL) /*!< CAL18 (Bit 8) */
+#define ADC0_CALR2_CAL18_Msk (0x300UL) /*!< CAL18 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR2_SAT17_Pos (7UL) /*!< SAT17 (Bit 7) */
+#define ADC0_CALR2_SAT17_Msk (0x80UL) /*!< SAT17 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR2_CAL17_Pos (4UL) /*!< CAL17 (Bit 4) */
+#define ADC0_CALR2_CAL17_Msk (0x30UL) /*!< CAL17 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR2_SAT16_Pos (3UL) /*!< SAT16 (Bit 3) */
+#define ADC0_CALR2_SAT16_Msk (0x8UL) /*!< SAT16 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR2_CAL16_Pos (0UL) /*!< CAL16 (Bit 0) */
+#define ADC0_CALR2_CAL16_Msk (0x3UL) /*!< CAL16 (Bitfield-Mask: 0x03) */
+/* ========================================================= SQR0 ========================================================== */
+#define ADC0_SQR0_SQ5_Pos (24UL) /*!< SQ5 (Bit 24) */
+#define ADC0_SQR0_SQ5_Msk (0x1f000000UL) /*!< SQ5 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR0_SQ4_Pos (18UL) /*!< SQ4 (Bit 18) */
+#define ADC0_SQR0_SQ4_Msk (0x7c0000UL) /*!< SQ4 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR0_SQ3_Pos (12UL) /*!< SQ3 (Bit 12) */
+#define ADC0_SQR0_SQ3_Msk (0x1f000UL) /*!< SQ3 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR0_SQ2_Pos (6UL) /*!< SQ2 (Bit 6) */
+#define ADC0_SQR0_SQ2_Msk (0x7c0UL) /*!< SQ2 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR0_SQ1_Pos (0UL) /*!< SQ1 (Bit 0) */
+#define ADC0_SQR0_SQ1_Msk (0x1fUL) /*!< SQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR1 ========================================================== */
+#define ADC0_SQR1_SQ10_Pos (24UL) /*!< SQ10 (Bit 24) */
+#define ADC0_SQR1_SQ10_Msk (0x1f000000UL) /*!< SQ10 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR1_SQ9_Pos (18UL) /*!< SQ9 (Bit 18) */
+#define ADC0_SQR1_SQ9_Msk (0x7c0000UL) /*!< SQ9 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR1_SQ8_Pos (12UL) /*!< SQ8 (Bit 12) */
+#define ADC0_SQR1_SQ8_Msk (0x1f000UL) /*!< SQ8 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR1_SQ7_Pos (6UL) /*!< SQ7 (Bit 6) */
+#define ADC0_SQR1_SQ7_Msk (0x7c0UL) /*!< SQ7 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR1_SQ6_Pos (0UL) /*!< SQ6 (Bit 0) */
+#define ADC0_SQR1_SQ6_Msk (0x1fUL) /*!< SQ6 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR2 ========================================================== */
+#define ADC0_SQR2_SQ15_Pos (24UL) /*!< SQ15 (Bit 24) */
+#define ADC0_SQR2_SQ15_Msk (0x1f000000UL) /*!< SQ15 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR2_SQ14_Pos (18UL) /*!< SQ14 (Bit 18) */
+#define ADC0_SQR2_SQ14_Msk (0x7c0000UL) /*!< SQ14 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR2_SQ13_Pos (12UL) /*!< SQ13 (Bit 12) */
+#define ADC0_SQR2_SQ13_Msk (0x1f000UL) /*!< SQ13 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR2_SQ12_Pos (6UL) /*!< SQ12 (Bit 6) */
+#define ADC0_SQR2_SQ12_Msk (0x7c0UL) /*!< SQ12 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR2_SQ11_Pos (0UL) /*!< SQ11 (Bit 0) */
+#define ADC0_SQR2_SQ11_Msk (0x1fUL) /*!< SQ11 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR3 ========================================================== */
+#define ADC0_SQR3_SQ16_Pos (0UL) /*!< SQ16 (Bit 0) */
+#define ADC0_SQR3_SQ16_Msk (0x1fUL) /*!< SQ16 (Bitfield-Mask: 0x1f) */
+/* ========================================================== LR =========================================================== */
+#define ADC0_LR_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define ADC0_LR_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define ADC0_LR_EXTEN_Pos (6UL) /*!< EXTEN (Bit 6) */
+#define ADC0_LR_EXTEN_Msk (0xc0UL) /*!< EXTEN (Bitfield-Mask: 0x03) */
+#define ADC0_LR_EXTSEL_Pos (0UL) /*!< EXTSEL (Bit 0) */
+#define ADC0_LR_EXTSEL_Msk (0x1fUL) /*!< EXTSEL (Bitfield-Mask: 0x1f) */
+/* ========================================================== DR =========================================================== */
+#define ADC0_DR_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */
+#define ADC0_DR_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MAXDR ========================================================= */
+#define ADC0_MAXDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC0_MAXDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MINDR ========================================================= */
+#define ADC0_MINDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC0_MINDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JSQR ========================================================== */
+#define ADC0_JSQR_JSQ4_Pos (18UL) /*!< JSQ4 (Bit 18) */
+#define ADC0_JSQR_JSQ4_Msk (0x7c0000UL) /*!< JSQ4 (Bitfield-Mask: 0x1f) */
+#define ADC0_JSQR_JSQ3_Pos (12UL) /*!< JSQ3 (Bit 12) */
+#define ADC0_JSQR_JSQ3_Msk (0x1f000UL) /*!< JSQ3 (Bitfield-Mask: 0x1f) */
+#define ADC0_JSQR_JSQ2_Pos (6UL) /*!< JSQ2 (Bit 6) */
+#define ADC0_JSQR_JSQ2_Msk (0x7c0UL) /*!< JSQ2 (Bitfield-Mask: 0x1f) */
+#define ADC0_JSQR_JSQ1_Pos (0UL) /*!< JSQ1 (Bit 0) */
+#define ADC0_JSQR_JSQ1_Msk (0x1fUL) /*!< JSQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================== JLR ========================================================== */
+#define ADC0_JLR_JLEN_Pos (8UL) /*!< JLEN (Bit 8) */
+#define ADC0_JLR_JLEN_Msk (0x300UL) /*!< JLEN (Bitfield-Mask: 0x03) */
+#define ADC0_JLR_JEXTEN_Pos (6UL) /*!< JEXTEN (Bit 6) */
+#define ADC0_JLR_JEXTEN_Msk (0xc0UL) /*!< JEXTEN (Bitfield-Mask: 0x03) */
+#define ADC0_JLR_JEXTSEL_Pos (0UL) /*!< JEXTSEL (Bit 0) */
+#define ADC0_JLR_JEXTSEL_Msk (0x1fUL) /*!< JEXTSEL (Bitfield-Mask: 0x1f) */
+/* ======================================================== MAXJDR ========================================================= */
+#define ADC0_MAXJDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC0_MAXJDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ======================================================== MINJDR ========================================================= */
+#define ADC0_MINJDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC0_MINJDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR0 ========================================================== */
+#define ADC0_JDR0_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC0_JDR0_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR1 ========================================================== */
+#define ADC0_JDR1_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC0_JDR1_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR2 ========================================================== */
+#define ADC0_JDR2_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC0_JDR2_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR3 ========================================================== */
+#define ADC0_JDR3_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC0_JDR3_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR0 ========================================================== */
+#define ADC0_TR0_HT0_Pos (16UL) /*!< HT0 (Bit 16) */
+#define ADC0_TR0_HT0_Msk (0xffff0000UL) /*!< HT0 (Bitfield-Mask: 0xffff) */
+#define ADC0_TR0_LT0_Pos (0UL) /*!< LT0 (Bit 0) */
+#define ADC0_TR0_LT0_Msk (0xffffUL) /*!< LT0 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR1 ========================================================== */
+#define ADC0_TR1_HT1_Pos (16UL) /*!< HT1 (Bit 16) */
+#define ADC0_TR1_HT1_Msk (0xffff0000UL) /*!< HT1 (Bitfield-Mask: 0xffff) */
+#define ADC0_TR1_LT1_Pos (0UL) /*!< LT1 (Bit 0) */
+#define ADC0_TR1_LT1_Msk (0xffffUL) /*!< LT1 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR2 ========================================================== */
+#define ADC0_TR2_HT2_Pos (16UL) /*!< HT2 (Bit 16) */
+#define ADC0_TR2_HT2_Msk (0xffff0000UL) /*!< HT2 (Bitfield-Mask: 0xffff) */
+#define ADC0_TR2_LT2_Pos (0UL) /*!< LT2 (Bit 0) */
+#define ADC0_TR2_LT2_Msk (0xffffUL) /*!< LT2 (Bitfield-Mask: 0xffff) */
+/* ======================================================== AWD0CR ========================================================= */
+#define ADC0_AWD0CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC0_AWD0CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC0_AWD0CR_AW0CH_Pos (0UL) /*!< AW0CH (Bit 0) */
+#define ADC0_AWD0CR_AW0CH_Msk (0xfffffUL) /*!< AW0CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD1CR ========================================================= */
+#define ADC0_AWD1CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC0_AWD1CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC0_AWD1CR_AW1CH_Pos (0UL) /*!< AW1CH (Bit 0) */
+#define ADC0_AWD1CR_AW1CH_Msk (0xfffffUL) /*!< AW1CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD2CR ========================================================= */
+#define ADC0_AWD2CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC0_AWD2CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC0_AWD2CR_AW2CH_Pos (0UL) /*!< AW2CH (Bit 0) */
+#define ADC0_AWD2CR_AW2CH_Msk (0xfffffUL) /*!< AW2CH (Bitfield-Mask: 0xfffff) */
+/* ========================================================= OFR0 ========================================================== */
+#define ADC0_OFR0_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC0_OFR0_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR1 ========================================================== */
+#define ADC0_OFR1_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC0_OFR1_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR2 ========================================================== */
+#define ADC0_OFR2_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC0_OFR2_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR3 ========================================================== */
+#define ADC0_OFR3_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC0_OFR3_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= GCR0 ========================================================== */
+#define ADC0_GCR0_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC0_GCR0_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR1 ========================================================== */
+#define ADC0_GCR1_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC0_GCR1_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR2 ========================================================== */
+#define ADC0_GCR2_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC0_GCR2_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR3 ========================================================== */
+#define ADC0_GCR3_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC0_GCR3_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= DISR ========================================================== */
+#define ADC0_DISR_DON19_Pos (19UL) /*!< DON19 (Bit 19) */
+#define ADC0_DISR_DON19_Msk (0x80000UL) /*!< DON19 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON18_Pos (18UL) /*!< DON18 (Bit 18) */
+#define ADC0_DISR_DON18_Msk (0x40000UL) /*!< DON18 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON17_Pos (17UL) /*!< DON17 (Bit 17) */
+#define ADC0_DISR_DON17_Msk (0x20000UL) /*!< DON17 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON16_Pos (16UL) /*!< DON16 (Bit 16) */
+#define ADC0_DISR_DON16_Msk (0x10000UL) /*!< DON16 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON15_Pos (15UL) /*!< DON15 (Bit 15) */
+#define ADC0_DISR_DON15_Msk (0x8000UL) /*!< DON15 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON14_Pos (14UL) /*!< DON14 (Bit 14) */
+#define ADC0_DISR_DON14_Msk (0x4000UL) /*!< DON14 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON13_Pos (13UL) /*!< DON13 (Bit 13) */
+#define ADC0_DISR_DON13_Msk (0x2000UL) /*!< DON13 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON12_Pos (12UL) /*!< DON12 (Bit 12) */
+#define ADC0_DISR_DON12_Msk (0x1000UL) /*!< DON12 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON11_Pos (11UL) /*!< DON11 (Bit 11) */
+#define ADC0_DISR_DON11_Msk (0x800UL) /*!< DON11 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON10_Pos (10UL) /*!< DON10 (Bit 10) */
+#define ADC0_DISR_DON10_Msk (0x400UL) /*!< DON10 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON9_Pos (9UL) /*!< DON9 (Bit 9) */
+#define ADC0_DISR_DON9_Msk (0x200UL) /*!< DON9 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON8_Pos (8UL) /*!< DON8 (Bit 8) */
+#define ADC0_DISR_DON8_Msk (0x100UL) /*!< DON8 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON7_Pos (7UL) /*!< DON7 (Bit 7) */
+#define ADC0_DISR_DON7_Msk (0x80UL) /*!< DON7 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON6_Pos (6UL) /*!< DON6 (Bit 6) */
+#define ADC0_DISR_DON6_Msk (0x40UL) /*!< DON6 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON5_Pos (5UL) /*!< DON5 (Bit 5) */
+#define ADC0_DISR_DON5_Msk (0x20UL) /*!< DON5 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON4_Pos (4UL) /*!< DON4 (Bit 4) */
+#define ADC0_DISR_DON4_Msk (0x10UL) /*!< DON4 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON3_Pos (3UL) /*!< DON3 (Bit 3) */
+#define ADC0_DISR_DON3_Msk (0x8UL) /*!< DON3 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON2_Pos (2UL) /*!< DON2 (Bit 2) */
+#define ADC0_DISR_DON2_Msk (0x4UL) /*!< DON2 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON1_Pos (1UL) /*!< DON1 (Bit 1) */
+#define ADC0_DISR_DON1_Msk (0x2UL) /*!< DON1 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON0_Pos (0UL) /*!< DON0 (Bit 0) */
+#define ADC0_DISR_DON0_Msk (0x1UL) /*!< DON0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DIER ========================================================== */
+#define ADC0_DIER_DONIE19_Pos (19UL) /*!< DONIE19 (Bit 19) */
+#define ADC0_DIER_DONIE19_Msk (0x80000UL) /*!< DONIE19 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE18_Pos (18UL) /*!< DONIE18 (Bit 18) */
+#define ADC0_DIER_DONIE18_Msk (0x40000UL) /*!< DONIE18 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE17_Pos (17UL) /*!< DONIE17 (Bit 17) */
+#define ADC0_DIER_DONIE17_Msk (0x20000UL) /*!< DONIE17 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE16_Pos (16UL) /*!< DONIE16 (Bit 16) */
+#define ADC0_DIER_DONIE16_Msk (0x10000UL) /*!< DONIE16 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE15_Pos (15UL) /*!< DONIE15 (Bit 15) */
+#define ADC0_DIER_DONIE15_Msk (0x8000UL) /*!< DONIE15 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE14_Pos (14UL) /*!< DONIE14 (Bit 14) */
+#define ADC0_DIER_DONIE14_Msk (0x4000UL) /*!< DONIE14 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE13_Pos (13UL) /*!< DONIE13 (Bit 13) */
+#define ADC0_DIER_DONIE13_Msk (0x2000UL) /*!< DONIE13 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE12_Pos (12UL) /*!< DONIE12 (Bit 12) */
+#define ADC0_DIER_DONIE12_Msk (0x1000UL) /*!< DONIE12 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE11_Pos (11UL) /*!< DONIE11 (Bit 11) */
+#define ADC0_DIER_DONIE11_Msk (0x800UL) /*!< DONIE11 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE10_Pos (10UL) /*!< DONIE10 (Bit 10) */
+#define ADC0_DIER_DONIE10_Msk (0x400UL) /*!< DONIE10 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE9_Pos (9UL) /*!< DONIE9 (Bit 9) */
+#define ADC0_DIER_DONIE9_Msk (0x200UL) /*!< DONIE9 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE8_Pos (8UL) /*!< DONIE8 (Bit 8) */
+#define ADC0_DIER_DONIE8_Msk (0x100UL) /*!< DONIE8 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE7_Pos (7UL) /*!< DONIE7 (Bit 7) */
+#define ADC0_DIER_DONIE7_Msk (0x80UL) /*!< DONIE7 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE6_Pos (6UL) /*!< DONIE6 (Bit 6) */
+#define ADC0_DIER_DONIE6_Msk (0x40UL) /*!< DONIE6 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE5_Pos (5UL) /*!< DONIE5 (Bit 5) */
+#define ADC0_DIER_DONIE5_Msk (0x20UL) /*!< DONIE5 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE4_Pos (4UL) /*!< DONIE4 (Bit 4) */
+#define ADC0_DIER_DONIE4_Msk (0x10UL) /*!< DONIE4 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE3_Pos (3UL) /*!< DONIE3 (Bit 3) */
+#define ADC0_DIER_DONIE3_Msk (0x8UL) /*!< DONIE3 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE2_Pos (2UL) /*!< DONIE2 (Bit 2) */
+#define ADC0_DIER_DONIE2_Msk (0x4UL) /*!< DONIE2 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE1_Pos (1UL) /*!< DONIE1 (Bit 1) */
+#define ADC0_DIER_DONIE1_Msk (0x2UL) /*!< DONIE1 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE0_Pos (0UL) /*!< DONIE0 (Bit 0) */
+#define ADC0_DIER_DONIE0_Msk (0x1UL) /*!< DONIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= CDR0 ========================================================== */
+#define ADC0_CDR0_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR0_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR1 ========================================================== */
+#define ADC0_CDR1_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR1_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR2 ========================================================== */
+#define ADC0_CDR2_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR2_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR3 ========================================================== */
+#define ADC0_CDR3_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR3_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR4 ========================================================== */
+#define ADC0_CDR4_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR4_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR5 ========================================================== */
+#define ADC0_CDR5_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR5_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR6 ========================================================== */
+#define ADC0_CDR6_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR6_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR7 ========================================================== */
+#define ADC0_CDR7_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR7_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR8 ========================================================== */
+#define ADC0_CDR8_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR8_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR9 ========================================================== */
+#define ADC0_CDR9_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR9_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR10 ========================================================= */
+#define ADC0_CDR10_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR10_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR11 ========================================================= */
+#define ADC0_CDR11_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR11_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR12 ========================================================= */
+#define ADC0_CDR12_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR12_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR13 ========================================================= */
+#define ADC0_CDR13_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR13_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR14 ========================================================= */
+#define ADC0_CDR14_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR14_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR15 ========================================================= */
+#define ADC0_CDR15_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR15_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR16 ========================================================= */
+#define ADC0_CDR16_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR16_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR17 ========================================================= */
+#define ADC0_CDR17_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR17_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR18 ========================================================= */
+#define ADC0_CDR18_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR18_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR19 ========================================================= */
+#define ADC0_CDR19_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR19_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= HISR ========================================================== */
+#define ADC0_HISR_HLF19_Pos (19UL) /*!< HLF19 (Bit 19) */
+#define ADC0_HISR_HLF19_Msk (0x80000UL) /*!< HLF19 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF18_Pos (18UL) /*!< HLF18 (Bit 18) */
+#define ADC0_HISR_HLF18_Msk (0x40000UL) /*!< HLF18 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF17_Pos (17UL) /*!< HLF17 (Bit 17) */
+#define ADC0_HISR_HLF17_Msk (0x20000UL) /*!< HLF17 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF16_Pos (16UL) /*!< HLF16 (Bit 16) */
+#define ADC0_HISR_HLF16_Msk (0x10000UL) /*!< HLF16 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF15_Pos (15UL) /*!< HLF15 (Bit 15) */
+#define ADC0_HISR_HLF15_Msk (0x8000UL) /*!< HLF15 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF14_Pos (14UL) /*!< HLF14 (Bit 14) */
+#define ADC0_HISR_HLF14_Msk (0x4000UL) /*!< HLF14 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF13_Pos (13UL) /*!< HLF13 (Bit 13) */
+#define ADC0_HISR_HLF13_Msk (0x2000UL) /*!< HLF13 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF12_Pos (12UL) /*!< HLF12 (Bit 12) */
+#define ADC0_HISR_HLF12_Msk (0x1000UL) /*!< HLF12 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF11_Pos (11UL) /*!< HLF11 (Bit 11) */
+#define ADC0_HISR_HLF11_Msk (0x800UL) /*!< HLF11 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF10_Pos (10UL) /*!< HLF10 (Bit 10) */
+#define ADC0_HISR_HLF10_Msk (0x400UL) /*!< HLF10 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF9_Pos (9UL) /*!< HLF9 (Bit 9) */
+#define ADC0_HISR_HLF9_Msk (0x200UL) /*!< HLF9 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF8_Pos (8UL) /*!< HLF8 (Bit 8) */
+#define ADC0_HISR_HLF8_Msk (0x100UL) /*!< HLF8 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF7_Pos (7UL) /*!< HLF7 (Bit 7) */
+#define ADC0_HISR_HLF7_Msk (0x80UL) /*!< HLF7 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF6_Pos (6UL) /*!< HLF6 (Bit 6) */
+#define ADC0_HISR_HLF6_Msk (0x40UL) /*!< HLF6 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF5_Pos (5UL) /*!< HLF5 (Bit 5) */
+#define ADC0_HISR_HLF5_Msk (0x20UL) /*!< HLF5 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF4_Pos (4UL) /*!< HLF4 (Bit 4) */
+#define ADC0_HISR_HLF4_Msk (0x10UL) /*!< HLF4 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF3_Pos (3UL) /*!< HLF3 (Bit 3) */
+#define ADC0_HISR_HLF3_Msk (0x8UL) /*!< HLF3 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF2_Pos (2UL) /*!< HLF2 (Bit 2) */
+#define ADC0_HISR_HLF2_Msk (0x4UL) /*!< HLF2 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF1_Pos (1UL) /*!< HLF1 (Bit 1) */
+#define ADC0_HISR_HLF1_Msk (0x2UL) /*!< HLF1 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF0_Pos (0UL) /*!< HLF0 (Bit 0) */
+#define ADC0_HISR_HLF0_Msk (0x1UL) /*!< HLF0 (Bitfield-Mask: 0x01) */
+/* ========================================================= HIER ========================================================== */
+#define ADC0_HIER_HLFIE19_Pos (19UL) /*!< HLFIE19 (Bit 19) */
+#define ADC0_HIER_HLFIE19_Msk (0x80000UL) /*!< HLFIE19 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE18_Pos (18UL) /*!< HLFIE18 (Bit 18) */
+#define ADC0_HIER_HLFIE18_Msk (0x40000UL) /*!< HLFIE18 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE17_Pos (17UL) /*!< HLFIE17 (Bit 17) */
+#define ADC0_HIER_HLFIE17_Msk (0x20000UL) /*!< HLFIE17 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE16_Pos (16UL) /*!< HLFIE16 (Bit 16) */
+#define ADC0_HIER_HLFIE16_Msk (0x10000UL) /*!< HLFIE16 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE15_Pos (15UL) /*!< HLFIE15 (Bit 15) */
+#define ADC0_HIER_HLFIE15_Msk (0x8000UL) /*!< HLFIE15 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE14_Pos (14UL) /*!< HLFIE14 (Bit 14) */
+#define ADC0_HIER_HLFIE14_Msk (0x4000UL) /*!< HLFIE14 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE13_Pos (13UL) /*!< HLFIE13 (Bit 13) */
+#define ADC0_HIER_HLFIE13_Msk (0x2000UL) /*!< HLFIE13 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE12_Pos (12UL) /*!< HLFIE12 (Bit 12) */
+#define ADC0_HIER_HLFIE12_Msk (0x1000UL) /*!< HLFIE12 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE11_Pos (11UL) /*!< HLFIE11 (Bit 11) */
+#define ADC0_HIER_HLFIE11_Msk (0x800UL) /*!< HLFIE11 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE10_Pos (10UL) /*!< HLFIE10 (Bit 10) */
+#define ADC0_HIER_HLFIE10_Msk (0x400UL) /*!< HLFIE10 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE9_Pos (9UL) /*!< HLFIE9 (Bit 9) */
+#define ADC0_HIER_HLFIE9_Msk (0x200UL) /*!< HLFIE9 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE8_Pos (8UL) /*!< HLFIE8 (Bit 8) */
+#define ADC0_HIER_HLFIE8_Msk (0x100UL) /*!< HLFIE8 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE7_Pos (7UL) /*!< HLFIE7 (Bit 7) */
+#define ADC0_HIER_HLFIE7_Msk (0x80UL) /*!< HLFIE7 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE6_Pos (6UL) /*!< HLFIE6 (Bit 6) */
+#define ADC0_HIER_HLFIE6_Msk (0x40UL) /*!< HLFIE6 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE5_Pos (5UL) /*!< HLFIE5 (Bit 5) */
+#define ADC0_HIER_HLFIE5_Msk (0x20UL) /*!< HLFIE5 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE4_Pos (4UL) /*!< HLFIE4 (Bit 4) */
+#define ADC0_HIER_HLFIE4_Msk (0x10UL) /*!< HLFIE4 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE3_Pos (3UL) /*!< HLFIE3 (Bit 3) */
+#define ADC0_HIER_HLFIE3_Msk (0x8UL) /*!< HLFIE3 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE2_Pos (2UL) /*!< HLFIE2 (Bit 2) */
+#define ADC0_HIER_HLFIE2_Msk (0x4UL) /*!< HLFIE2 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE1_Pos (1UL) /*!< HLFIE1 (Bit 1) */
+#define ADC0_HIER_HLFIE1_Msk (0x2UL) /*!< HLFIE1 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE0_Pos (0UL) /*!< HLFIE0 (Bit 0) */
+#define ADC0_HIER_HLFIE0_Msk (0x1UL) /*!< HLFIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FISR ========================================================== */
+#define ADC0_FISR_FUL19_Pos (19UL) /*!< FUL19 (Bit 19) */
+#define ADC0_FISR_FUL19_Msk (0x80000UL) /*!< FUL19 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL18_Pos (18UL) /*!< FUL18 (Bit 18) */
+#define ADC0_FISR_FUL18_Msk (0x40000UL) /*!< FUL18 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL17_Pos (17UL) /*!< FUL17 (Bit 17) */
+#define ADC0_FISR_FUL17_Msk (0x20000UL) /*!< FUL17 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL16_Pos (16UL) /*!< FUL16 (Bit 16) */
+#define ADC0_FISR_FUL16_Msk (0x10000UL) /*!< FUL16 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL15_Pos (15UL) /*!< FUL15 (Bit 15) */
+#define ADC0_FISR_FUL15_Msk (0x8000UL) /*!< FUL15 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL14_Pos (14UL) /*!< FUL14 (Bit 14) */
+#define ADC0_FISR_FUL14_Msk (0x4000UL) /*!< FUL14 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL13_Pos (13UL) /*!< FUL13 (Bit 13) */
+#define ADC0_FISR_FUL13_Msk (0x2000UL) /*!< FUL13 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL12_Pos (12UL) /*!< FUL12 (Bit 12) */
+#define ADC0_FISR_FUL12_Msk (0x1000UL) /*!< FUL12 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL11_Pos (11UL) /*!< FUL11 (Bit 11) */
+#define ADC0_FISR_FUL11_Msk (0x800UL) /*!< FUL11 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL10_Pos (10UL) /*!< FUL10 (Bit 10) */
+#define ADC0_FISR_FUL10_Msk (0x400UL) /*!< FUL10 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL9_Pos (9UL) /*!< FUL9 (Bit 9) */
+#define ADC0_FISR_FUL9_Msk (0x200UL) /*!< FUL9 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL8_Pos (8UL) /*!< FUL8 (Bit 8) */
+#define ADC0_FISR_FUL8_Msk (0x100UL) /*!< FUL8 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL7_Pos (7UL) /*!< FUL7 (Bit 7) */
+#define ADC0_FISR_FUL7_Msk (0x80UL) /*!< FUL7 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL6_Pos (6UL) /*!< FUL6 (Bit 6) */
+#define ADC0_FISR_FUL6_Msk (0x40UL) /*!< FUL6 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL5_Pos (5UL) /*!< FUL5 (Bit 5) */
+#define ADC0_FISR_FUL5_Msk (0x20UL) /*!< FUL5 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL4_Pos (4UL) /*!< FUL4 (Bit 4) */
+#define ADC0_FISR_FUL4_Msk (0x10UL) /*!< FUL4 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL3_Pos (3UL) /*!< FUL3 (Bit 3) */
+#define ADC0_FISR_FUL3_Msk (0x8UL) /*!< FUL3 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL2_Pos (2UL) /*!< FUL2 (Bit 2) */
+#define ADC0_FISR_FUL2_Msk (0x4UL) /*!< FUL2 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL1_Pos (1UL) /*!< FUL1 (Bit 1) */
+#define ADC0_FISR_FUL1_Msk (0x2UL) /*!< FUL1 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL0_Pos (0UL) /*!< FUL0 (Bit 0) */
+#define ADC0_FISR_FUL0_Msk (0x1UL) /*!< FUL0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FIER ========================================================== */
+#define ADC0_FIER_FULIE19_Pos (19UL) /*!< FULIE19 (Bit 19) */
+#define ADC0_FIER_FULIE19_Msk (0x80000UL) /*!< FULIE19 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE18_Pos (18UL) /*!< FULIE18 (Bit 18) */
+#define ADC0_FIER_FULIE18_Msk (0x40000UL) /*!< FULIE18 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE17_Pos (17UL) /*!< FULIE17 (Bit 17) */
+#define ADC0_FIER_FULIE17_Msk (0x20000UL) /*!< FULIE17 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE16_Pos (16UL) /*!< FULIE16 (Bit 16) */
+#define ADC0_FIER_FULIE16_Msk (0x10000UL) /*!< FULIE16 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE15_Pos (15UL) /*!< FULIE15 (Bit 15) */
+#define ADC0_FIER_FULIE15_Msk (0x8000UL) /*!< FULIE15 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE14_Pos (14UL) /*!< FULIE14 (Bit 14) */
+#define ADC0_FIER_FULIE14_Msk (0x4000UL) /*!< FULIE14 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE13_Pos (13UL) /*!< FULIE13 (Bit 13) */
+#define ADC0_FIER_FULIE13_Msk (0x2000UL) /*!< FULIE13 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE12_Pos (12UL) /*!< FULIE12 (Bit 12) */
+#define ADC0_FIER_FULIE12_Msk (0x1000UL) /*!< FULIE12 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE11_Pos (11UL) /*!< FULIE11 (Bit 11) */
+#define ADC0_FIER_FULIE11_Msk (0x800UL) /*!< FULIE11 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE10_Pos (10UL) /*!< FULIE10 (Bit 10) */
+#define ADC0_FIER_FULIE10_Msk (0x400UL) /*!< FULIE10 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE9_Pos (9UL) /*!< FULIE9 (Bit 9) */
+#define ADC0_FIER_FULIE9_Msk (0x200UL) /*!< FULIE9 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE8_Pos (8UL) /*!< FULIE8 (Bit 8) */
+#define ADC0_FIER_FULIE8_Msk (0x100UL) /*!< FULIE8 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE7_Pos (7UL) /*!< FULIE7 (Bit 7) */
+#define ADC0_FIER_FULIE7_Msk (0x80UL) /*!< FULIE7 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE6_Pos (6UL) /*!< FULIE6 (Bit 6) */
+#define ADC0_FIER_FULIE6_Msk (0x40UL) /*!< FULIE6 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE5_Pos (5UL) /*!< FULIE5 (Bit 5) */
+#define ADC0_FIER_FULIE5_Msk (0x20UL) /*!< FULIE5 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE4_Pos (4UL) /*!< FULIE4 (Bit 4) */
+#define ADC0_FIER_FULIE4_Msk (0x10UL) /*!< FULIE4 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE3_Pos (3UL) /*!< FULIE3 (Bit 3) */
+#define ADC0_FIER_FULIE3_Msk (0x8UL) /*!< FULIE3 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE2_Pos (2UL) /*!< FULIE2 (Bit 2) */
+#define ADC0_FIER_FULIE2_Msk (0x4UL) /*!< FULIE2 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE1_Pos (1UL) /*!< FULIE1 (Bit 1) */
+#define ADC0_FIER_FULIE1_Msk (0x2UL) /*!< FULIE1 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE0_Pos (0UL) /*!< FULIE0 (Bit 0) */
+#define ADC0_FIER_FULIE0_Msk (0x1UL) /*!< FULIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= TCR0 ========================================================== */
+#define ADC0_TCR0_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR0_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR0_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR0_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR0_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR0_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR0_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR0 ========================================================== */
+#define ADC0_TAR0_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR0_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR0 ========================================================== */
+#define ADC0_TLR0_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR0_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR1 ========================================================== */
+#define ADC0_TCR1_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR1_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR1_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR1_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR1_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR1_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR1_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR1 ========================================================== */
+#define ADC0_TAR1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR1_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR1 ========================================================== */
+#define ADC0_TLR1_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR1_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR2 ========================================================== */
+#define ADC0_TCR2_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR2_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR2_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR2_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR2_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR2_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR2_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR2 ========================================================== */
+#define ADC0_TAR2_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR2_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR2 ========================================================== */
+#define ADC0_TLR2_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR2_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR3 ========================================================== */
+#define ADC0_TCR3_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR3_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR3_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR3_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR3_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR3_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR3_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR3 ========================================================== */
+#define ADC0_TAR3_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR3_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR3 ========================================================== */
+#define ADC0_TLR3_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR3_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR4 ========================================================== */
+#define ADC0_TCR4_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR4_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR4_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR4_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR4_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR4_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR4_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR4_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR4 ========================================================== */
+#define ADC0_TAR4_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR4_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR4 ========================================================== */
+#define ADC0_TLR4_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR4_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR5 ========================================================== */
+#define ADC0_TCR5_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR5_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR5_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR5_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR5_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR5_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR5_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR5_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR5 ========================================================== */
+#define ADC0_TAR5_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR5_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR5 ========================================================== */
+#define ADC0_TLR5_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR5_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR6 ========================================================== */
+#define ADC0_TCR6_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR6_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR6_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR6_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR6_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR6_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR6_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR6_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR6 ========================================================== */
+#define ADC0_TAR6_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR6_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR6 ========================================================== */
+#define ADC0_TLR6_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR6_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR7 ========================================================== */
+#define ADC0_TCR7_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR7_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR7_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR7_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR7_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR7_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR7_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR7_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR7 ========================================================== */
+#define ADC0_TAR7_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR7_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR7 ========================================================== */
+#define ADC0_TLR7_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR7_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR8 ========================================================== */
+#define ADC0_TCR8_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR8_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR8_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR8_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR8_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR8_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR8_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR8_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR8 ========================================================== */
+#define ADC0_TAR8_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR8_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR8 ========================================================== */
+#define ADC0_TLR8_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR8_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR9 ========================================================== */
+#define ADC0_TCR9_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR9_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR9_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR9_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR9_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR9_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR9_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR9_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR9 ========================================================== */
+#define ADC0_TAR9_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR9_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR9 ========================================================== */
+#define ADC0_TLR9_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR9_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR10 ========================================================= */
+#define ADC0_TCR10_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR10_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR10_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR10_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR10_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR10_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR10_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR10_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR10 ========================================================= */
+#define ADC0_TAR10_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR10_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR10 ========================================================= */
+#define ADC0_TLR10_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR10_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR11 ========================================================= */
+#define ADC0_TCR11_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR11_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR11_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR11_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR11_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR11_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR11_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR11_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR11 ========================================================= */
+#define ADC0_TAR11_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR11_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR11 ========================================================= */
+#define ADC0_TLR11_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR11_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR12 ========================================================= */
+#define ADC0_TCR12_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR12_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR12_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR12_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR12_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR12_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR12_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR12_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR12 ========================================================= */
+#define ADC0_TAR12_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR12_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR12 ========================================================= */
+#define ADC0_TLR12_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR12_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR13 ========================================================= */
+#define ADC0_TCR13_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR13_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR13_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR13_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR13_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR13_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR13_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR13_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR13 ========================================================= */
+#define ADC0_TAR13_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR13_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR13 ========================================================= */
+#define ADC0_TLR13_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR13_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR14 ========================================================= */
+#define ADC0_TCR14_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR14_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR14_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR14_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR14_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR14_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR14_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR14_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR14 ========================================================= */
+#define ADC0_TAR14_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR14_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR14 ========================================================= */
+#define ADC0_TLR14_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR14_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR15 ========================================================= */
+#define ADC0_TCR15_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR15_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR15_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR15_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR15_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR15_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR15_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR15_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR15 ========================================================= */
+#define ADC0_TAR15_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR15_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR15 ========================================================= */
+#define ADC0_TLR15_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR15_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR16 ========================================================= */
+#define ADC0_TCR16_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR16_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR16_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR16_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR16_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR16_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR16_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR16_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR16 ========================================================= */
+#define ADC0_TAR16_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR16_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR16 ========================================================= */
+#define ADC0_TLR16_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR16_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR17 ========================================================= */
+#define ADC0_TCR17_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR17_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR17_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR17_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR17_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR17_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR17_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR17_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR17 ========================================================= */
+#define ADC0_TAR17_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR17_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR17 ========================================================= */
+#define ADC0_TLR17_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR17_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR18 ========================================================= */
+#define ADC0_TCR18_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR18_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR18_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR18_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR18_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR18_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR18_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR18_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR18 ========================================================= */
+#define ADC0_TAR18_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR18_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR18 ========================================================= */
+#define ADC0_TLR18_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR18_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR19 ========================================================= */
+#define ADC0_TCR19_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR19_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR19_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR19_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR19_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR19_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR19_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR19_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR19 ========================================================= */
+#define ADC0_TAR19_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR19_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR19 ========================================================= */
+#define ADC0_TLR19_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR19_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================== CCR ========================================================== */
+#define ADC0_CCR_DELAY_Pos (8UL) /*!< DELAY (Bit 8) */
+#define ADC0_CCR_DELAY_Msk (0x3ff00UL) /*!< DELAY (Bitfield-Mask: 0x3ff) */
+#define ADC0_CCR_DUAL_Pos (0UL) /*!< DUAL (Bit 0) */
+#define ADC0_CCR_DUAL_Msk (0xfUL) /*!< DUAL (Bitfield-Mask: 0x0f) */
+/* ========================================================== CSR ========================================================== */
+#define ADC0_CSR_EOSMP_SLV_Pos (25UL) /*!< EOSMP_SLV (Bit 25) */
+#define ADC0_CSR_EOSMP_SLV_Msk (0x2000000UL) /*!< EOSMP_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_ADRDY_SLV_Pos (24UL) /*!< ADRDY_SLV (Bit 24) */
+#define ADC0_CSR_ADRDY_SLV_Msk (0x1000000UL) /*!< ADRDY_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD2_SLV_Pos (23UL) /*!< AWD2_SLV (Bit 23) */
+#define ADC0_CSR_AWD2_SLV_Msk (0x800000UL) /*!< AWD2_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD1_SLV_Pos (22UL) /*!< AWD1_SLV (Bit 22) */
+#define ADC0_CSR_AWD1_SLV_Msk (0x400000UL) /*!< AWD1_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD0_SLV_Pos (21UL) /*!< AWD0_SLV (Bit 21) */
+#define ADC0_CSR_AWD0_SLV_Msk (0x200000UL) /*!< AWD0_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_OVR_SLV_Pos (20UL) /*!< OVR_SLV (Bit 20) */
+#define ADC0_CSR_OVR_SLV_Msk (0x100000UL) /*!< OVR_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_JEOS_SLV_Pos (19UL) /*!< JEOS_SLV (Bit 19) */
+#define ADC0_CSR_JEOS_SLV_Msk (0x80000UL) /*!< JEOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_JEOC_SLV_Pos (18UL) /*!< JEOC_SLV (Bit 18) */
+#define ADC0_CSR_JEOC_SLV_Msk (0x40000UL) /*!< JEOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_EOS_SLV_Pos (17UL) /*!< EOS_SLV (Bit 17) */
+#define ADC0_CSR_EOS_SLV_Msk (0x20000UL) /*!< EOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_EOC_SLV_Pos (16UL) /*!< EOC_SLV (Bit 16) */
+#define ADC0_CSR_EOC_SLV_Msk (0x10000UL) /*!< EOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_EOSMP_MST_Pos (9UL) /*!< EOSMP_MST (Bit 9) */
+#define ADC0_CSR_EOSMP_MST_Msk (0x200UL) /*!< EOSMP_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_ADRDY_MST_Pos (8UL) /*!< ADRDY_MST (Bit 8) */
+#define ADC0_CSR_ADRDY_MST_Msk (0x100UL) /*!< ADRDY_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD2_MST_Pos (7UL) /*!< AWD2_MST (Bit 7) */
+#define ADC0_CSR_AWD2_MST_Msk (0x80UL) /*!< AWD2_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD1_MST_Pos (6UL) /*!< AWD1_MST (Bit 6) */
+#define ADC0_CSR_AWD1_MST_Msk (0x40UL) /*!< AWD1_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD0_MST_Pos (5UL) /*!< AWD0_MST (Bit 5) */
+#define ADC0_CSR_AWD0_MST_Msk (0x20UL) /*!< AWD0_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_OVR_MST_Pos (4UL) /*!< OVR_MST (Bit 4) */
+#define ADC0_CSR_OVR_MST_Msk (0x10UL) /*!< OVR_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_JEOS_MST_Pos (3UL) /*!< JEOS_MST (Bit 3) */
+#define ADC0_CSR_JEOS_MST_Msk (0x8UL) /*!< JEOS_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_JEOC_MST_Pos (2UL) /*!< JEOC_MST (Bit 2) */
+#define ADC0_CSR_JEOC_MST_Msk (0x4UL) /*!< JEOC_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_EOS_MST_Pos (1UL) /*!< EOS_MST (Bit 1) */
+#define ADC0_CSR_EOS_MST_Msk (0x2UL) /*!< EOS_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_EOC_MST_Pos (0UL) /*!< EOC_MST (Bit 0) */
+#define ADC0_CSR_EOC_MST_Msk (0x1UL) /*!< EOC_MST (Bitfield-Mask: 0x01) */
+/* ========================================================== CDR ========================================================== */
+#define ADC0_CDR_RDATA_SLV_Pos (16UL) /*!< RDATA_SLV (Bit 16) */
+#define ADC0_CDR_RDATA_SLV_Msk (0xffff0000UL) /*!< RDATA_SLV (Bitfield-Mask: 0xffff) */
+#define ADC0_CDR_RDATA_MST_Pos (0UL) /*!< RDATA_MST (Bit 0) */
+#define ADC0_CDR_RDATA_MST_Msk (0xffffUL) /*!< RDATA_MST (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ ADC1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define ADC1_CR_ADCALDIF_Pos (7UL) /*!< ADCALDIF (Bit 7) */
+#define ADC1_CR_ADCALDIF_Msk (0x80UL) /*!< ADCALDIF (Bitfield-Mask: 0x01) */
+#define ADC1_CR_ADCAL_Pos (6UL) /*!< ADCAL (Bit 6) */
+#define ADC1_CR_ADCAL_Msk (0x40UL) /*!< ADCAL (Bitfield-Mask: 0x01) */
+#define ADC1_CR_JADSTP_Pos (5UL) /*!< JADSTP (Bit 5) */
+#define ADC1_CR_JADSTP_Msk (0x20UL) /*!< JADSTP (Bitfield-Mask: 0x01) */
+#define ADC1_CR_ADSTP_Pos (4UL) /*!< ADSTP (Bit 4) */
+#define ADC1_CR_ADSTP_Msk (0x10UL) /*!< ADSTP (Bitfield-Mask: 0x01) */
+#define ADC1_CR_JADSTART_Pos (3UL) /*!< JADSTART (Bit 3) */
+#define ADC1_CR_JADSTART_Msk (0x8UL) /*!< JADSTART (Bitfield-Mask: 0x01) */
+#define ADC1_CR_ADSTART_Pos (2UL) /*!< ADSTART (Bit 2) */
+#define ADC1_CR_ADSTART_Msk (0x4UL) /*!< ADSTART (Bitfield-Mask: 0x01) */
+#define ADC1_CR_ADDIS_Pos (1UL) /*!< ADDIS (Bit 1) */
+#define ADC1_CR_ADDIS_Msk (0x2UL) /*!< ADDIS (Bitfield-Mask: 0x01) */
+#define ADC1_CR_ADEN_Pos (0UL) /*!< ADEN (Bit 0) */
+#define ADC1_CR_ADEN_Msk (0x1UL) /*!< ADEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR0 ========================================================= */
+#define ADC1_CFGR0_OVSCAL_Pos (28UL) /*!< OVSCAL (Bit 28) */
+#define ADC1_CFGR0_OVSCAL_Msk (0x70000000UL) /*!< OVSCAL (Bitfield-Mask: 0x07) */
+#define ADC1_CFGR0_CONT_Pos (23UL) /*!< CONT (Bit 23) */
+#define ADC1_CFGR0_CONT_Msk (0x800000UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_JAUTO_Pos (22UL) /*!< JAUTO (Bit 22) */
+#define ADC1_CFGR0_JAUTO_Msk (0x400000UL) /*!< JAUTO (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_JDISCEN_Pos (20UL) /*!< JDISCEN (Bit 20) */
+#define ADC1_CFGR0_JDISCEN_Msk (0x100000UL) /*!< JDISCEN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_DISCNUM_Pos (17UL) /*!< DISCNUM (Bit 17) */
+#define ADC1_CFGR0_DISCNUM_Msk (0xe0000UL) /*!< DISCNUM (Bitfield-Mask: 0x07) */
+#define ADC1_CFGR0_DISCEN_Pos (16UL) /*!< DISCEN (Bit 16) */
+#define ADC1_CFGR0_DISCEN_Msk (0x10000UL) /*!< DISCEN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_OVRMOD_Pos (15UL) /*!< OVRMOD (Bit 15) */
+#define ADC1_CFGR0_OVRMOD_Msk (0x8000UL) /*!< OVRMOD (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_SDMAEN_Pos (14UL) /*!< SDMAEN (Bit 14) */
+#define ADC1_CFGR0_SDMAEN_Msk (0x4000UL) /*!< SDMAEN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_TROVS_Pos (12UL) /*!< TROVS (Bit 12) */
+#define ADC1_CFGR0_TROVS_Msk (0x1000UL) /*!< TROVS (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_OVSS_Pos (8UL) /*!< OVSS (Bit 8) */
+#define ADC1_CFGR0_OVSS_Msk (0xf00UL) /*!< OVSS (Bitfield-Mask: 0x0f) */
+#define ADC1_CFGR0_ROVSM_Pos (7UL) /*!< ROVSM (Bit 7) */
+#define ADC1_CFGR0_ROVSM_Msk (0x80UL) /*!< ROVSM (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_OVSR_Pos (4UL) /*!< OVSR (Bit 4) */
+#define ADC1_CFGR0_OVSR_Msk (0x70UL) /*!< OVSR (Bitfield-Mask: 0x07) */
+#define ADC1_CFGR0_JOVSE_Pos (1UL) /*!< JOVSE (Bit 1) */
+#define ADC1_CFGR0_JOVSE_Msk (0x2UL) /*!< JOVSE (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_ROVSE_Pos (0UL) /*!< ROVSE (Bit 0) */
+#define ADC1_CFGR0_ROVSE_Msk (0x1UL) /*!< ROVSE (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR1 ========================================================= */
+#define ADC1_CFGR1_JAWD2EN_Pos (14UL) /*!< JAWD2EN (Bit 14) */
+#define ADC1_CFGR1_JAWD2EN_Msk (0x4000UL) /*!< JAWD2EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_JAWD1EN_Pos (13UL) /*!< JAWD1EN (Bit 13) */
+#define ADC1_CFGR1_JAWD1EN_Msk (0x2000UL) /*!< JAWD1EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_JAWD0EN_Pos (12UL) /*!< JAWD0EN (Bit 12) */
+#define ADC1_CFGR1_JAWD0EN_Msk (0x1000UL) /*!< JAWD0EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_AWD2EN_Pos (10UL) /*!< AWD2EN (Bit 10) */
+#define ADC1_CFGR1_AWD2EN_Msk (0x400UL) /*!< AWD2EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_AWD1EN_Pos (9UL) /*!< AWD1EN (Bit 9) */
+#define ADC1_CFGR1_AWD1EN_Msk (0x200UL) /*!< AWD1EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_AWD0EN_Pos (8UL) /*!< AWD0EN (Bit 8) */
+#define ADC1_CFGR1_AWD0EN_Msk (0x100UL) /*!< AWD0EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_ISEL_Pos (4UL) /*!< ISEL (Bit 4) */
+#define ADC1_CFGR1_ISEL_Msk (0x30UL) /*!< ISEL (Bitfield-Mask: 0x03) */
+#define ADC1_CFGR1_CHEN_Pos (3UL) /*!< CHEN (Bit 3) */
+#define ADC1_CFGR1_CHEN_Msk (0x8UL) /*!< CHEN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_REFEN_Pos (1UL) /*!< REFEN (Bit 1) */
+#define ADC1_CFGR1_REFEN_Msk (0x2UL) /*!< REFEN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_BIASEN_Pos (0UL) /*!< BIASEN (Bit 0) */
+#define ADC1_CFGR1_BIASEN_Msk (0x1UL) /*!< BIASEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define ADC1_ISR_EOSMP_Pos (9UL) /*!< EOSMP (Bit 9) */
+#define ADC1_ISR_EOSMP_Msk (0x200UL) /*!< EOSMP (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_ADRDY_Pos (8UL) /*!< ADRDY (Bit 8) */
+#define ADC1_ISR_ADRDY_Msk (0x100UL) /*!< ADRDY (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_AWD2_Pos (7UL) /*!< AWD2 (Bit 7) */
+#define ADC1_ISR_AWD2_Msk (0x80UL) /*!< AWD2 (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_AWD1_Pos (6UL) /*!< AWD1 (Bit 6) */
+#define ADC1_ISR_AWD1_Msk (0x40UL) /*!< AWD1 (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_AWD0_Pos (5UL) /*!< AWD0 (Bit 5) */
+#define ADC1_ISR_AWD0_Msk (0x20UL) /*!< AWD0 (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_OVR_Pos (4UL) /*!< OVR (Bit 4) */
+#define ADC1_ISR_OVR_Msk (0x10UL) /*!< OVR (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_JEOS_Pos (3UL) /*!< JEOS (Bit 3) */
+#define ADC1_ISR_JEOS_Msk (0x8UL) /*!< JEOS (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_JEOC_Pos (2UL) /*!< JEOC (Bit 2) */
+#define ADC1_ISR_JEOC_Msk (0x4UL) /*!< JEOC (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */
+#define ADC1_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */
+#define ADC1_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define ADC1_IER_EOSMPIE_Pos (9UL) /*!< EOSMPIE (Bit 9) */
+#define ADC1_IER_EOSMPIE_Msk (0x200UL) /*!< EOSMPIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_ADRDYIE_Pos (8UL) /*!< ADRDYIE (Bit 8) */
+#define ADC1_IER_ADRDYIE_Msk (0x100UL) /*!< ADRDYIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_AWD2IE_Pos (7UL) /*!< AWD2IE (Bit 7) */
+#define ADC1_IER_AWD2IE_Msk (0x80UL) /*!< AWD2IE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_AWD1IE_Pos (6UL) /*!< AWD1IE (Bit 6) */
+#define ADC1_IER_AWD1IE_Msk (0x40UL) /*!< AWD1IE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_AWD0IE_Pos (5UL) /*!< AWD0IE (Bit 5) */
+#define ADC1_IER_AWD0IE_Msk (0x20UL) /*!< AWD0IE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_OVRIE_Pos (4UL) /*!< OVRIE (Bit 4) */
+#define ADC1_IER_OVRIE_Msk (0x10UL) /*!< OVRIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_JEOSIE_Pos (3UL) /*!< JEOSIE (Bit 3) */
+#define ADC1_IER_JEOSIE_Msk (0x8UL) /*!< JEOSIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_JEOCIE_Pos (2UL) /*!< JEOCIE (Bit 2) */
+#define ADC1_IER_JEOCIE_Msk (0x4UL) /*!< JEOCIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_EOSIE_Pos (1UL) /*!< EOSIE (Bit 1) */
+#define ADC1_IER_EOSIE_Msk (0x2UL) /*!< EOSIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_EOCIE_Pos (0UL) /*!< EOCIE (Bit 0) */
+#define ADC1_IER_EOCIE_Msk (0x1UL) /*!< EOCIE (Bitfield-Mask: 0x01) */
+/* ======================================================== SIGSEL ========================================================= */
+#define ADC1_SIGSEL_SIGSEL_Pos (0UL) /*!< SIGSEL (Bit 0) */
+#define ADC1_SIGSEL_SIGSEL_Msk (0xfffffUL) /*!< SIGSEL (Bitfield-Mask: 0xfffff) */
+/* ========================================================= SMPR0 ========================================================= */
+#define ADC1_SMPR0_SMP7_Pos (28UL) /*!< SMP7 (Bit 28) */
+#define ADC1_SMPR0_SMP7_Msk (0x70000000UL) /*!< SMP7 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP6_Pos (24UL) /*!< SMP6 (Bit 24) */
+#define ADC1_SMPR0_SMP6_Msk (0x7000000UL) /*!< SMP6 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP5_Pos (20UL) /*!< SMP5 (Bit 20) */
+#define ADC1_SMPR0_SMP5_Msk (0x700000UL) /*!< SMP5 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP4_Pos (16UL) /*!< SMP4 (Bit 16) */
+#define ADC1_SMPR0_SMP4_Msk (0x70000UL) /*!< SMP4 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP3_Pos (12UL) /*!< SMP3 (Bit 12) */
+#define ADC1_SMPR0_SMP3_Msk (0x7000UL) /*!< SMP3 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP2_Pos (8UL) /*!< SMP2 (Bit 8) */
+#define ADC1_SMPR0_SMP2_Msk (0x700UL) /*!< SMP2 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP1_Pos (4UL) /*!< SMP1 (Bit 4) */
+#define ADC1_SMPR0_SMP1_Msk (0x70UL) /*!< SMP1 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP0_Pos (0UL) /*!< SMP0 (Bit 0) */
+#define ADC1_SMPR0_SMP0_Msk (0x7UL) /*!< SMP0 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR1 ========================================================= */
+#define ADC1_SMPR1_SMP15_Pos (28UL) /*!< SMP15 (Bit 28) */
+#define ADC1_SMPR1_SMP15_Msk (0x70000000UL) /*!< SMP15 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP14_Pos (24UL) /*!< SMP14 (Bit 24) */
+#define ADC1_SMPR1_SMP14_Msk (0x7000000UL) /*!< SMP14 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP13_Pos (20UL) /*!< SMP13 (Bit 20) */
+#define ADC1_SMPR1_SMP13_Msk (0x700000UL) /*!< SMP13 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP12_Pos (16UL) /*!< SMP12 (Bit 16) */
+#define ADC1_SMPR1_SMP12_Msk (0x70000UL) /*!< SMP12 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP11_Pos (12UL) /*!< SMP11 (Bit 12) */
+#define ADC1_SMPR1_SMP11_Msk (0x7000UL) /*!< SMP11 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP10_Pos (8UL) /*!< SMP10 (Bit 8) */
+#define ADC1_SMPR1_SMP10_Msk (0x700UL) /*!< SMP10 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP9_Pos (4UL) /*!< SMP9 (Bit 4) */
+#define ADC1_SMPR1_SMP9_Msk (0x70UL) /*!< SMP9 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP8_Pos (0UL) /*!< SMP8 (Bit 0) */
+#define ADC1_SMPR1_SMP8_Msk (0x7UL) /*!< SMP8 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR2 ========================================================= */
+#define ADC1_SMPR2_SMP19_Pos (12UL) /*!< SMP19 (Bit 12) */
+#define ADC1_SMPR2_SMP19_Msk (0x7000UL) /*!< SMP19 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR2_SMP18_Pos (8UL) /*!< SMP18 (Bit 8) */
+#define ADC1_SMPR2_SMP18_Msk (0x700UL) /*!< SMP18 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR2_SMP17_Pos (4UL) /*!< SMP17 (Bit 4) */
+#define ADC1_SMPR2_SMP17_Msk (0x70UL) /*!< SMP17 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR2_SMP16_Pos (0UL) /*!< SMP16 (Bit 0) */
+#define ADC1_SMPR2_SMP16_Msk (0x7UL) /*!< SMP16 (Bitfield-Mask: 0x07) */
+/* ========================================================= CALR0 ========================================================= */
+#define ADC1_CALR0_SAT7_Pos (31UL) /*!< SAT7 (Bit 31) */
+#define ADC1_CALR0_SAT7_Msk (0x80000000UL) /*!< SAT7 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL7_Pos (28UL) /*!< CAL7 (Bit 28) */
+#define ADC1_CALR0_CAL7_Msk (0x30000000UL) /*!< CAL7 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT6_Pos (27UL) /*!< SAT6 (Bit 27) */
+#define ADC1_CALR0_SAT6_Msk (0x8000000UL) /*!< SAT6 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL6_Pos (24UL) /*!< CAL6 (Bit 24) */
+#define ADC1_CALR0_CAL6_Msk (0x3000000UL) /*!< CAL6 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT5_Pos (23UL) /*!< SAT5 (Bit 23) */
+#define ADC1_CALR0_SAT5_Msk (0x800000UL) /*!< SAT5 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL5_Pos (20UL) /*!< CAL5 (Bit 20) */
+#define ADC1_CALR0_CAL5_Msk (0x300000UL) /*!< CAL5 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT4_Pos (19UL) /*!< SAT4 (Bit 19) */
+#define ADC1_CALR0_SAT4_Msk (0x80000UL) /*!< SAT4 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL4_Pos (16UL) /*!< CAL4 (Bit 16) */
+#define ADC1_CALR0_CAL4_Msk (0x30000UL) /*!< CAL4 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT3_Pos (15UL) /*!< SAT3 (Bit 15) */
+#define ADC1_CALR0_SAT3_Msk (0x8000UL) /*!< SAT3 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL3_Pos (12UL) /*!< CAL3 (Bit 12) */
+#define ADC1_CALR0_CAL3_Msk (0x3000UL) /*!< CAL3 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT2_Pos (11UL) /*!< SAT2 (Bit 11) */
+#define ADC1_CALR0_SAT2_Msk (0x800UL) /*!< SAT2 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL2_Pos (8UL) /*!< CAL2 (Bit 8) */
+#define ADC1_CALR0_CAL2_Msk (0x300UL) /*!< CAL2 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT1_Pos (7UL) /*!< SAT1 (Bit 7) */
+#define ADC1_CALR0_SAT1_Msk (0x80UL) /*!< SAT1 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL1_Pos (4UL) /*!< CAL1 (Bit 4) */
+#define ADC1_CALR0_CAL1_Msk (0x30UL) /*!< CAL1 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT0_Pos (3UL) /*!< SAT0 (Bit 3) */
+#define ADC1_CALR0_SAT0_Msk (0x8UL) /*!< SAT0 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL0_Pos (0UL) /*!< CAL0 (Bit 0) */
+#define ADC1_CALR0_CAL0_Msk (0x3UL) /*!< CAL0 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR1 ========================================================= */
+#define ADC1_CALR1_SAT15_Pos (31UL) /*!< SAT15 (Bit 31) */
+#define ADC1_CALR1_SAT15_Msk (0x80000000UL) /*!< SAT15 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL15_Pos (28UL) /*!< CAL15 (Bit 28) */
+#define ADC1_CALR1_CAL15_Msk (0x30000000UL) /*!< CAL15 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT14_Pos (27UL) /*!< SAT14 (Bit 27) */
+#define ADC1_CALR1_SAT14_Msk (0x8000000UL) /*!< SAT14 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL14_Pos (24UL) /*!< CAL14 (Bit 24) */
+#define ADC1_CALR1_CAL14_Msk (0x3000000UL) /*!< CAL14 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT13_Pos (23UL) /*!< SAT13 (Bit 23) */
+#define ADC1_CALR1_SAT13_Msk (0x800000UL) /*!< SAT13 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL13_Pos (20UL) /*!< CAL13 (Bit 20) */
+#define ADC1_CALR1_CAL13_Msk (0x300000UL) /*!< CAL13 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT12_Pos (19UL) /*!< SAT12 (Bit 19) */
+#define ADC1_CALR1_SAT12_Msk (0x80000UL) /*!< SAT12 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL12_Pos (16UL) /*!< CAL12 (Bit 16) */
+#define ADC1_CALR1_CAL12_Msk (0x30000UL) /*!< CAL12 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT11_Pos (15UL) /*!< SAT11 (Bit 15) */
+#define ADC1_CALR1_SAT11_Msk (0x8000UL) /*!< SAT11 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL11_Pos (12UL) /*!< CAL11 (Bit 12) */
+#define ADC1_CALR1_CAL11_Msk (0x3000UL) /*!< CAL11 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT10_Pos (11UL) /*!< SAT10 (Bit 11) */
+#define ADC1_CALR1_SAT10_Msk (0x800UL) /*!< SAT10 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL10_Pos (8UL) /*!< CAL10 (Bit 8) */
+#define ADC1_CALR1_CAL10_Msk (0x300UL) /*!< CAL10 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT9_Pos (7UL) /*!< SAT9 (Bit 7) */
+#define ADC1_CALR1_SAT9_Msk (0x80UL) /*!< SAT9 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL9_Pos (4UL) /*!< CAL9 (Bit 4) */
+#define ADC1_CALR1_CAL9_Msk (0x30UL) /*!< CAL9 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT8_Pos (3UL) /*!< SAT8 (Bit 3) */
+#define ADC1_CALR1_SAT8_Msk (0x8UL) /*!< SAT8 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL8_Pos (0UL) /*!< CAL8 (Bit 0) */
+#define ADC1_CALR1_CAL8_Msk (0x3UL) /*!< CAL8 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR2 ========================================================= */
+#define ADC1_CALR2_SAT19_Pos (15UL) /*!< SAT19 (Bit 15) */
+#define ADC1_CALR2_SAT19_Msk (0x8000UL) /*!< SAT19 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR2_CAL19_Pos (12UL) /*!< CAL19 (Bit 12) */
+#define ADC1_CALR2_CAL19_Msk (0x3000UL) /*!< CAL19 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR2_SAT18_Pos (11UL) /*!< SAT18 (Bit 11) */
+#define ADC1_CALR2_SAT18_Msk (0x800UL) /*!< SAT18 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR2_CAL18_Pos (8UL) /*!< CAL18 (Bit 8) */
+#define ADC1_CALR2_CAL18_Msk (0x300UL) /*!< CAL18 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR2_SAT17_Pos (7UL) /*!< SAT17 (Bit 7) */
+#define ADC1_CALR2_SAT17_Msk (0x80UL) /*!< SAT17 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR2_CAL17_Pos (4UL) /*!< CAL17 (Bit 4) */
+#define ADC1_CALR2_CAL17_Msk (0x30UL) /*!< CAL17 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR2_SAT16_Pos (3UL) /*!< SAT16 (Bit 3) */
+#define ADC1_CALR2_SAT16_Msk (0x8UL) /*!< SAT16 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR2_CAL16_Pos (0UL) /*!< CAL16 (Bit 0) */
+#define ADC1_CALR2_CAL16_Msk (0x3UL) /*!< CAL16 (Bitfield-Mask: 0x03) */
+/* ========================================================= SQR0 ========================================================== */
+#define ADC1_SQR0_SQ5_Pos (24UL) /*!< SQ5 (Bit 24) */
+#define ADC1_SQR0_SQ5_Msk (0x1f000000UL) /*!< SQ5 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR0_SQ4_Pos (18UL) /*!< SQ4 (Bit 18) */
+#define ADC1_SQR0_SQ4_Msk (0x7c0000UL) /*!< SQ4 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR0_SQ3_Pos (12UL) /*!< SQ3 (Bit 12) */
+#define ADC1_SQR0_SQ3_Msk (0x1f000UL) /*!< SQ3 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR0_SQ2_Pos (6UL) /*!< SQ2 (Bit 6) */
+#define ADC1_SQR0_SQ2_Msk (0x7c0UL) /*!< SQ2 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR0_SQ1_Pos (0UL) /*!< SQ1 (Bit 0) */
+#define ADC1_SQR0_SQ1_Msk (0x1fUL) /*!< SQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR1 ========================================================== */
+#define ADC1_SQR1_SQ10_Pos (24UL) /*!< SQ10 (Bit 24) */
+#define ADC1_SQR1_SQ10_Msk (0x1f000000UL) /*!< SQ10 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR1_SQ9_Pos (18UL) /*!< SQ9 (Bit 18) */
+#define ADC1_SQR1_SQ9_Msk (0x7c0000UL) /*!< SQ9 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR1_SQ8_Pos (12UL) /*!< SQ8 (Bit 12) */
+#define ADC1_SQR1_SQ8_Msk (0x1f000UL) /*!< SQ8 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR1_SQ7_Pos (6UL) /*!< SQ7 (Bit 6) */
+#define ADC1_SQR1_SQ7_Msk (0x7c0UL) /*!< SQ7 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR1_SQ6_Pos (0UL) /*!< SQ6 (Bit 0) */
+#define ADC1_SQR1_SQ6_Msk (0x1fUL) /*!< SQ6 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR2 ========================================================== */
+#define ADC1_SQR2_SQ15_Pos (24UL) /*!< SQ15 (Bit 24) */
+#define ADC1_SQR2_SQ15_Msk (0x1f000000UL) /*!< SQ15 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR2_SQ14_Pos (18UL) /*!< SQ14 (Bit 18) */
+#define ADC1_SQR2_SQ14_Msk (0x7c0000UL) /*!< SQ14 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR2_SQ13_Pos (12UL) /*!< SQ13 (Bit 12) */
+#define ADC1_SQR2_SQ13_Msk (0x1f000UL) /*!< SQ13 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR2_SQ12_Pos (6UL) /*!< SQ12 (Bit 6) */
+#define ADC1_SQR2_SQ12_Msk (0x7c0UL) /*!< SQ12 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR2_SQ11_Pos (0UL) /*!< SQ11 (Bit 0) */
+#define ADC1_SQR2_SQ11_Msk (0x1fUL) /*!< SQ11 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR3 ========================================================== */
+#define ADC1_SQR3_SQ16_Pos (0UL) /*!< SQ16 (Bit 0) */
+#define ADC1_SQR3_SQ16_Msk (0x1fUL) /*!< SQ16 (Bitfield-Mask: 0x1f) */
+/* ========================================================== LR =========================================================== */
+#define ADC1_LR_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define ADC1_LR_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define ADC1_LR_EXTEN_Pos (6UL) /*!< EXTEN (Bit 6) */
+#define ADC1_LR_EXTEN_Msk (0xc0UL) /*!< EXTEN (Bitfield-Mask: 0x03) */
+#define ADC1_LR_EXTSEL_Pos (0UL) /*!< EXTSEL (Bit 0) */
+#define ADC1_LR_EXTSEL_Msk (0x1fUL) /*!< EXTSEL (Bitfield-Mask: 0x1f) */
+/* ========================================================== DR =========================================================== */
+#define ADC1_DR_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */
+#define ADC1_DR_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MAXDR ========================================================= */
+#define ADC1_MAXDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC1_MAXDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MINDR ========================================================= */
+#define ADC1_MINDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC1_MINDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JSQR ========================================================== */
+#define ADC1_JSQR_JSQ4_Pos (18UL) /*!< JSQ4 (Bit 18) */
+#define ADC1_JSQR_JSQ4_Msk (0x7c0000UL) /*!< JSQ4 (Bitfield-Mask: 0x1f) */
+#define ADC1_JSQR_JSQ3_Pos (12UL) /*!< JSQ3 (Bit 12) */
+#define ADC1_JSQR_JSQ3_Msk (0x1f000UL) /*!< JSQ3 (Bitfield-Mask: 0x1f) */
+#define ADC1_JSQR_JSQ2_Pos (6UL) /*!< JSQ2 (Bit 6) */
+#define ADC1_JSQR_JSQ2_Msk (0x7c0UL) /*!< JSQ2 (Bitfield-Mask: 0x1f) */
+#define ADC1_JSQR_JSQ1_Pos (0UL) /*!< JSQ1 (Bit 0) */
+#define ADC1_JSQR_JSQ1_Msk (0x1fUL) /*!< JSQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================== JLR ========================================================== */
+#define ADC1_JLR_JLEN_Pos (8UL) /*!< JLEN (Bit 8) */
+#define ADC1_JLR_JLEN_Msk (0x300UL) /*!< JLEN (Bitfield-Mask: 0x03) */
+#define ADC1_JLR_JEXTEN_Pos (6UL) /*!< JEXTEN (Bit 6) */
+#define ADC1_JLR_JEXTEN_Msk (0xc0UL) /*!< JEXTEN (Bitfield-Mask: 0x03) */
+#define ADC1_JLR_JEXTSEL_Pos (0UL) /*!< JEXTSEL (Bit 0) */
+#define ADC1_JLR_JEXTSEL_Msk (0x1fUL) /*!< JEXTSEL (Bitfield-Mask: 0x1f) */
+/* ======================================================== MAXJDR ========================================================= */
+#define ADC1_MAXJDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC1_MAXJDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ======================================================== MINJDR ========================================================= */
+#define ADC1_MINJDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC1_MINJDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR0 ========================================================== */
+#define ADC1_JDR0_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC1_JDR0_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR1 ========================================================== */
+#define ADC1_JDR1_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC1_JDR1_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR2 ========================================================== */
+#define ADC1_JDR2_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC1_JDR2_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR3 ========================================================== */
+#define ADC1_JDR3_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC1_JDR3_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR0 ========================================================== */
+#define ADC1_TR0_HT0_Pos (16UL) /*!< HT0 (Bit 16) */
+#define ADC1_TR0_HT0_Msk (0xffff0000UL) /*!< HT0 (Bitfield-Mask: 0xffff) */
+#define ADC1_TR0_LT0_Pos (0UL) /*!< LT0 (Bit 0) */
+#define ADC1_TR0_LT0_Msk (0xffffUL) /*!< LT0 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR1 ========================================================== */
+#define ADC1_TR1_HT1_Pos (16UL) /*!< HT1 (Bit 16) */
+#define ADC1_TR1_HT1_Msk (0xffff0000UL) /*!< HT1 (Bitfield-Mask: 0xffff) */
+#define ADC1_TR1_LT1_Pos (0UL) /*!< LT1 (Bit 0) */
+#define ADC1_TR1_LT1_Msk (0xffffUL) /*!< LT1 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR2 ========================================================== */
+#define ADC1_TR2_HT2_Pos (16UL) /*!< HT2 (Bit 16) */
+#define ADC1_TR2_HT2_Msk (0xffff0000UL) /*!< HT2 (Bitfield-Mask: 0xffff) */
+#define ADC1_TR2_LT2_Pos (0UL) /*!< LT2 (Bit 0) */
+#define ADC1_TR2_LT2_Msk (0xffffUL) /*!< LT2 (Bitfield-Mask: 0xffff) */
+/* ======================================================== AWD0CR ========================================================= */
+#define ADC1_AWD0CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC1_AWD0CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC1_AWD0CR_AW0CH_Pos (0UL) /*!< AW0CH (Bit 0) */
+#define ADC1_AWD0CR_AW0CH_Msk (0xfffffUL) /*!< AW0CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD1CR ========================================================= */
+#define ADC1_AWD1CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC1_AWD1CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC1_AWD1CR_AW1CH_Pos (0UL) /*!< AW1CH (Bit 0) */
+#define ADC1_AWD1CR_AW1CH_Msk (0xfffffUL) /*!< AW1CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD2CR ========================================================= */
+#define ADC1_AWD2CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC1_AWD2CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC1_AWD2CR_AW2CH_Pos (0UL) /*!< AW2CH (Bit 0) */
+#define ADC1_AWD2CR_AW2CH_Msk (0xfffffUL) /*!< AW2CH (Bitfield-Mask: 0xfffff) */
+/* ========================================================= OFR0 ========================================================== */
+#define ADC1_OFR0_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC1_OFR0_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR1 ========================================================== */
+#define ADC1_OFR1_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC1_OFR1_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR2 ========================================================== */
+#define ADC1_OFR2_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC1_OFR2_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR3 ========================================================== */
+#define ADC1_OFR3_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC1_OFR3_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= GCR0 ========================================================== */
+#define ADC1_GCR0_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC1_GCR0_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR1 ========================================================== */
+#define ADC1_GCR1_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC1_GCR1_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR2 ========================================================== */
+#define ADC1_GCR2_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC1_GCR2_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR3 ========================================================== */
+#define ADC1_GCR3_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC1_GCR3_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= DISR ========================================================== */
+#define ADC1_DISR_DON19_Pos (19UL) /*!< DON19 (Bit 19) */
+#define ADC1_DISR_DON19_Msk (0x80000UL) /*!< DON19 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON18_Pos (18UL) /*!< DON18 (Bit 18) */
+#define ADC1_DISR_DON18_Msk (0x40000UL) /*!< DON18 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON17_Pos (17UL) /*!< DON17 (Bit 17) */
+#define ADC1_DISR_DON17_Msk (0x20000UL) /*!< DON17 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON16_Pos (16UL) /*!< DON16 (Bit 16) */
+#define ADC1_DISR_DON16_Msk (0x10000UL) /*!< DON16 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON15_Pos (15UL) /*!< DON15 (Bit 15) */
+#define ADC1_DISR_DON15_Msk (0x8000UL) /*!< DON15 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON14_Pos (14UL) /*!< DON14 (Bit 14) */
+#define ADC1_DISR_DON14_Msk (0x4000UL) /*!< DON14 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON13_Pos (13UL) /*!< DON13 (Bit 13) */
+#define ADC1_DISR_DON13_Msk (0x2000UL) /*!< DON13 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON12_Pos (12UL) /*!< DON12 (Bit 12) */
+#define ADC1_DISR_DON12_Msk (0x1000UL) /*!< DON12 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON11_Pos (11UL) /*!< DON11 (Bit 11) */
+#define ADC1_DISR_DON11_Msk (0x800UL) /*!< DON11 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON10_Pos (10UL) /*!< DON10 (Bit 10) */
+#define ADC1_DISR_DON10_Msk (0x400UL) /*!< DON10 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON9_Pos (9UL) /*!< DON9 (Bit 9) */
+#define ADC1_DISR_DON9_Msk (0x200UL) /*!< DON9 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON8_Pos (8UL) /*!< DON8 (Bit 8) */
+#define ADC1_DISR_DON8_Msk (0x100UL) /*!< DON8 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON7_Pos (7UL) /*!< DON7 (Bit 7) */
+#define ADC1_DISR_DON7_Msk (0x80UL) /*!< DON7 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON6_Pos (6UL) /*!< DON6 (Bit 6) */
+#define ADC1_DISR_DON6_Msk (0x40UL) /*!< DON6 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON5_Pos (5UL) /*!< DON5 (Bit 5) */
+#define ADC1_DISR_DON5_Msk (0x20UL) /*!< DON5 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON4_Pos (4UL) /*!< DON4 (Bit 4) */
+#define ADC1_DISR_DON4_Msk (0x10UL) /*!< DON4 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON3_Pos (3UL) /*!< DON3 (Bit 3) */
+#define ADC1_DISR_DON3_Msk (0x8UL) /*!< DON3 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON2_Pos (2UL) /*!< DON2 (Bit 2) */
+#define ADC1_DISR_DON2_Msk (0x4UL) /*!< DON2 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON1_Pos (1UL) /*!< DON1 (Bit 1) */
+#define ADC1_DISR_DON1_Msk (0x2UL) /*!< DON1 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON0_Pos (0UL) /*!< DON0 (Bit 0) */
+#define ADC1_DISR_DON0_Msk (0x1UL) /*!< DON0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DIER ========================================================== */
+#define ADC1_DIER_DONIE19_Pos (19UL) /*!< DONIE19 (Bit 19) */
+#define ADC1_DIER_DONIE19_Msk (0x80000UL) /*!< DONIE19 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE18_Pos (18UL) /*!< DONIE18 (Bit 18) */
+#define ADC1_DIER_DONIE18_Msk (0x40000UL) /*!< DONIE18 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE17_Pos (17UL) /*!< DONIE17 (Bit 17) */
+#define ADC1_DIER_DONIE17_Msk (0x20000UL) /*!< DONIE17 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE16_Pos (16UL) /*!< DONIE16 (Bit 16) */
+#define ADC1_DIER_DONIE16_Msk (0x10000UL) /*!< DONIE16 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE15_Pos (15UL) /*!< DONIE15 (Bit 15) */
+#define ADC1_DIER_DONIE15_Msk (0x8000UL) /*!< DONIE15 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE14_Pos (14UL) /*!< DONIE14 (Bit 14) */
+#define ADC1_DIER_DONIE14_Msk (0x4000UL) /*!< DONIE14 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE13_Pos (13UL) /*!< DONIE13 (Bit 13) */
+#define ADC1_DIER_DONIE13_Msk (0x2000UL) /*!< DONIE13 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE12_Pos (12UL) /*!< DONIE12 (Bit 12) */
+#define ADC1_DIER_DONIE12_Msk (0x1000UL) /*!< DONIE12 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE11_Pos (11UL) /*!< DONIE11 (Bit 11) */
+#define ADC1_DIER_DONIE11_Msk (0x800UL) /*!< DONIE11 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE10_Pos (10UL) /*!< DONIE10 (Bit 10) */
+#define ADC1_DIER_DONIE10_Msk (0x400UL) /*!< DONIE10 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE9_Pos (9UL) /*!< DONIE9 (Bit 9) */
+#define ADC1_DIER_DONIE9_Msk (0x200UL) /*!< DONIE9 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE8_Pos (8UL) /*!< DONIE8 (Bit 8) */
+#define ADC1_DIER_DONIE8_Msk (0x100UL) /*!< DONIE8 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE7_Pos (7UL) /*!< DONIE7 (Bit 7) */
+#define ADC1_DIER_DONIE7_Msk (0x80UL) /*!< DONIE7 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE6_Pos (6UL) /*!< DONIE6 (Bit 6) */
+#define ADC1_DIER_DONIE6_Msk (0x40UL) /*!< DONIE6 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE5_Pos (5UL) /*!< DONIE5 (Bit 5) */
+#define ADC1_DIER_DONIE5_Msk (0x20UL) /*!< DONIE5 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE4_Pos (4UL) /*!< DONIE4 (Bit 4) */
+#define ADC1_DIER_DONIE4_Msk (0x10UL) /*!< DONIE4 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE3_Pos (3UL) /*!< DONIE3 (Bit 3) */
+#define ADC1_DIER_DONIE3_Msk (0x8UL) /*!< DONIE3 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE2_Pos (2UL) /*!< DONIE2 (Bit 2) */
+#define ADC1_DIER_DONIE2_Msk (0x4UL) /*!< DONIE2 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE1_Pos (1UL) /*!< DONIE1 (Bit 1) */
+#define ADC1_DIER_DONIE1_Msk (0x2UL) /*!< DONIE1 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE0_Pos (0UL) /*!< DONIE0 (Bit 0) */
+#define ADC1_DIER_DONIE0_Msk (0x1UL) /*!< DONIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= CDR0 ========================================================== */
+#define ADC1_CDR0_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR0_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR1 ========================================================== */
+#define ADC1_CDR1_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR1_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR2 ========================================================== */
+#define ADC1_CDR2_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR2_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR3 ========================================================== */
+#define ADC1_CDR3_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR3_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR4 ========================================================== */
+#define ADC1_CDR4_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR4_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR5 ========================================================== */
+#define ADC1_CDR5_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR5_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR6 ========================================================== */
+#define ADC1_CDR6_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR6_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR7 ========================================================== */
+#define ADC1_CDR7_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR7_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR8 ========================================================== */
+#define ADC1_CDR8_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR8_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR9 ========================================================== */
+#define ADC1_CDR9_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR9_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR10 ========================================================= */
+#define ADC1_CDR10_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR10_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR11 ========================================================= */
+#define ADC1_CDR11_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR11_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR12 ========================================================= */
+#define ADC1_CDR12_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR12_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR13 ========================================================= */
+#define ADC1_CDR13_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR13_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR14 ========================================================= */
+#define ADC1_CDR14_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR14_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR15 ========================================================= */
+#define ADC1_CDR15_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR15_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR16 ========================================================= */
+#define ADC1_CDR16_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR16_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR17 ========================================================= */
+#define ADC1_CDR17_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR17_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR18 ========================================================= */
+#define ADC1_CDR18_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR18_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR19 ========================================================= */
+#define ADC1_CDR19_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR19_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= HISR ========================================================== */
+#define ADC1_HISR_HLF19_Pos (19UL) /*!< HLF19 (Bit 19) */
+#define ADC1_HISR_HLF19_Msk (0x80000UL) /*!< HLF19 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF18_Pos (18UL) /*!< HLF18 (Bit 18) */
+#define ADC1_HISR_HLF18_Msk (0x40000UL) /*!< HLF18 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF17_Pos (17UL) /*!< HLF17 (Bit 17) */
+#define ADC1_HISR_HLF17_Msk (0x20000UL) /*!< HLF17 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF16_Pos (16UL) /*!< HLF16 (Bit 16) */
+#define ADC1_HISR_HLF16_Msk (0x10000UL) /*!< HLF16 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF15_Pos (15UL) /*!< HLF15 (Bit 15) */
+#define ADC1_HISR_HLF15_Msk (0x8000UL) /*!< HLF15 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF14_Pos (14UL) /*!< HLF14 (Bit 14) */
+#define ADC1_HISR_HLF14_Msk (0x4000UL) /*!< HLF14 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF13_Pos (13UL) /*!< HLF13 (Bit 13) */
+#define ADC1_HISR_HLF13_Msk (0x2000UL) /*!< HLF13 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF12_Pos (12UL) /*!< HLF12 (Bit 12) */
+#define ADC1_HISR_HLF12_Msk (0x1000UL) /*!< HLF12 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF11_Pos (11UL) /*!< HLF11 (Bit 11) */
+#define ADC1_HISR_HLF11_Msk (0x800UL) /*!< HLF11 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF10_Pos (10UL) /*!< HLF10 (Bit 10) */
+#define ADC1_HISR_HLF10_Msk (0x400UL) /*!< HLF10 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF9_Pos (9UL) /*!< HLF9 (Bit 9) */
+#define ADC1_HISR_HLF9_Msk (0x200UL) /*!< HLF9 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF8_Pos (8UL) /*!< HLF8 (Bit 8) */
+#define ADC1_HISR_HLF8_Msk (0x100UL) /*!< HLF8 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF7_Pos (7UL) /*!< HLF7 (Bit 7) */
+#define ADC1_HISR_HLF7_Msk (0x80UL) /*!< HLF7 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF6_Pos (6UL) /*!< HLF6 (Bit 6) */
+#define ADC1_HISR_HLF6_Msk (0x40UL) /*!< HLF6 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF5_Pos (5UL) /*!< HLF5 (Bit 5) */
+#define ADC1_HISR_HLF5_Msk (0x20UL) /*!< HLF5 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF4_Pos (4UL) /*!< HLF4 (Bit 4) */
+#define ADC1_HISR_HLF4_Msk (0x10UL) /*!< HLF4 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF3_Pos (3UL) /*!< HLF3 (Bit 3) */
+#define ADC1_HISR_HLF3_Msk (0x8UL) /*!< HLF3 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF2_Pos (2UL) /*!< HLF2 (Bit 2) */
+#define ADC1_HISR_HLF2_Msk (0x4UL) /*!< HLF2 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF1_Pos (1UL) /*!< HLF1 (Bit 1) */
+#define ADC1_HISR_HLF1_Msk (0x2UL) /*!< HLF1 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF0_Pos (0UL) /*!< HLF0 (Bit 0) */
+#define ADC1_HISR_HLF0_Msk (0x1UL) /*!< HLF0 (Bitfield-Mask: 0x01) */
+/* ========================================================= HIER ========================================================== */
+#define ADC1_HIER_HLFIE19_Pos (19UL) /*!< HLFIE19 (Bit 19) */
+#define ADC1_HIER_HLFIE19_Msk (0x80000UL) /*!< HLFIE19 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE18_Pos (18UL) /*!< HLFIE18 (Bit 18) */
+#define ADC1_HIER_HLFIE18_Msk (0x40000UL) /*!< HLFIE18 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE17_Pos (17UL) /*!< HLFIE17 (Bit 17) */
+#define ADC1_HIER_HLFIE17_Msk (0x20000UL) /*!< HLFIE17 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE16_Pos (16UL) /*!< HLFIE16 (Bit 16) */
+#define ADC1_HIER_HLFIE16_Msk (0x10000UL) /*!< HLFIE16 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE15_Pos (15UL) /*!< HLFIE15 (Bit 15) */
+#define ADC1_HIER_HLFIE15_Msk (0x8000UL) /*!< HLFIE15 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE14_Pos (14UL) /*!< HLFIE14 (Bit 14) */
+#define ADC1_HIER_HLFIE14_Msk (0x4000UL) /*!< HLFIE14 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE13_Pos (13UL) /*!< HLFIE13 (Bit 13) */
+#define ADC1_HIER_HLFIE13_Msk (0x2000UL) /*!< HLFIE13 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE12_Pos (12UL) /*!< HLFIE12 (Bit 12) */
+#define ADC1_HIER_HLFIE12_Msk (0x1000UL) /*!< HLFIE12 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE11_Pos (11UL) /*!< HLFIE11 (Bit 11) */
+#define ADC1_HIER_HLFIE11_Msk (0x800UL) /*!< HLFIE11 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE10_Pos (10UL) /*!< HLFIE10 (Bit 10) */
+#define ADC1_HIER_HLFIE10_Msk (0x400UL) /*!< HLFIE10 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE9_Pos (9UL) /*!< HLFIE9 (Bit 9) */
+#define ADC1_HIER_HLFIE9_Msk (0x200UL) /*!< HLFIE9 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE8_Pos (8UL) /*!< HLFIE8 (Bit 8) */
+#define ADC1_HIER_HLFIE8_Msk (0x100UL) /*!< HLFIE8 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE7_Pos (7UL) /*!< HLFIE7 (Bit 7) */
+#define ADC1_HIER_HLFIE7_Msk (0x80UL) /*!< HLFIE7 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE6_Pos (6UL) /*!< HLFIE6 (Bit 6) */
+#define ADC1_HIER_HLFIE6_Msk (0x40UL) /*!< HLFIE6 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE5_Pos (5UL) /*!< HLFIE5 (Bit 5) */
+#define ADC1_HIER_HLFIE5_Msk (0x20UL) /*!< HLFIE5 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE4_Pos (4UL) /*!< HLFIE4 (Bit 4) */
+#define ADC1_HIER_HLFIE4_Msk (0x10UL) /*!< HLFIE4 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE3_Pos (3UL) /*!< HLFIE3 (Bit 3) */
+#define ADC1_HIER_HLFIE3_Msk (0x8UL) /*!< HLFIE3 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE2_Pos (2UL) /*!< HLFIE2 (Bit 2) */
+#define ADC1_HIER_HLFIE2_Msk (0x4UL) /*!< HLFIE2 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE1_Pos (1UL) /*!< HLFIE1 (Bit 1) */
+#define ADC1_HIER_HLFIE1_Msk (0x2UL) /*!< HLFIE1 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE0_Pos (0UL) /*!< HLFIE0 (Bit 0) */
+#define ADC1_HIER_HLFIE0_Msk (0x1UL) /*!< HLFIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FISR ========================================================== */
+#define ADC1_FISR_FUL19_Pos (19UL) /*!< FUL19 (Bit 19) */
+#define ADC1_FISR_FUL19_Msk (0x80000UL) /*!< FUL19 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL18_Pos (18UL) /*!< FUL18 (Bit 18) */
+#define ADC1_FISR_FUL18_Msk (0x40000UL) /*!< FUL18 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL17_Pos (17UL) /*!< FUL17 (Bit 17) */
+#define ADC1_FISR_FUL17_Msk (0x20000UL) /*!< FUL17 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL16_Pos (16UL) /*!< FUL16 (Bit 16) */
+#define ADC1_FISR_FUL16_Msk (0x10000UL) /*!< FUL16 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL15_Pos (15UL) /*!< FUL15 (Bit 15) */
+#define ADC1_FISR_FUL15_Msk (0x8000UL) /*!< FUL15 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL14_Pos (14UL) /*!< FUL14 (Bit 14) */
+#define ADC1_FISR_FUL14_Msk (0x4000UL) /*!< FUL14 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL13_Pos (13UL) /*!< FUL13 (Bit 13) */
+#define ADC1_FISR_FUL13_Msk (0x2000UL) /*!< FUL13 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL12_Pos (12UL) /*!< FUL12 (Bit 12) */
+#define ADC1_FISR_FUL12_Msk (0x1000UL) /*!< FUL12 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL11_Pos (11UL) /*!< FUL11 (Bit 11) */
+#define ADC1_FISR_FUL11_Msk (0x800UL) /*!< FUL11 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL10_Pos (10UL) /*!< FUL10 (Bit 10) */
+#define ADC1_FISR_FUL10_Msk (0x400UL) /*!< FUL10 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL9_Pos (9UL) /*!< FUL9 (Bit 9) */
+#define ADC1_FISR_FUL9_Msk (0x200UL) /*!< FUL9 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL8_Pos (8UL) /*!< FUL8 (Bit 8) */
+#define ADC1_FISR_FUL8_Msk (0x100UL) /*!< FUL8 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL7_Pos (7UL) /*!< FUL7 (Bit 7) */
+#define ADC1_FISR_FUL7_Msk (0x80UL) /*!< FUL7 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL6_Pos (6UL) /*!< FUL6 (Bit 6) */
+#define ADC1_FISR_FUL6_Msk (0x40UL) /*!< FUL6 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL5_Pos (5UL) /*!< FUL5 (Bit 5) */
+#define ADC1_FISR_FUL5_Msk (0x20UL) /*!< FUL5 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL4_Pos (4UL) /*!< FUL4 (Bit 4) */
+#define ADC1_FISR_FUL4_Msk (0x10UL) /*!< FUL4 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL3_Pos (3UL) /*!< FUL3 (Bit 3) */
+#define ADC1_FISR_FUL3_Msk (0x8UL) /*!< FUL3 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL2_Pos (2UL) /*!< FUL2 (Bit 2) */
+#define ADC1_FISR_FUL2_Msk (0x4UL) /*!< FUL2 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL1_Pos (1UL) /*!< FUL1 (Bit 1) */
+#define ADC1_FISR_FUL1_Msk (0x2UL) /*!< FUL1 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL0_Pos (0UL) /*!< FUL0 (Bit 0) */
+#define ADC1_FISR_FUL0_Msk (0x1UL) /*!< FUL0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FIER ========================================================== */
+#define ADC1_FIER_FULIE19_Pos (19UL) /*!< FULIE19 (Bit 19) */
+#define ADC1_FIER_FULIE19_Msk (0x80000UL) /*!< FULIE19 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE18_Pos (18UL) /*!< FULIE18 (Bit 18) */
+#define ADC1_FIER_FULIE18_Msk (0x40000UL) /*!< FULIE18 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE17_Pos (17UL) /*!< FULIE17 (Bit 17) */
+#define ADC1_FIER_FULIE17_Msk (0x20000UL) /*!< FULIE17 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE16_Pos (16UL) /*!< FULIE16 (Bit 16) */
+#define ADC1_FIER_FULIE16_Msk (0x10000UL) /*!< FULIE16 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE15_Pos (15UL) /*!< FULIE15 (Bit 15) */
+#define ADC1_FIER_FULIE15_Msk (0x8000UL) /*!< FULIE15 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE14_Pos (14UL) /*!< FULIE14 (Bit 14) */
+#define ADC1_FIER_FULIE14_Msk (0x4000UL) /*!< FULIE14 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE13_Pos (13UL) /*!< FULIE13 (Bit 13) */
+#define ADC1_FIER_FULIE13_Msk (0x2000UL) /*!< FULIE13 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE12_Pos (12UL) /*!< FULIE12 (Bit 12) */
+#define ADC1_FIER_FULIE12_Msk (0x1000UL) /*!< FULIE12 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE11_Pos (11UL) /*!< FULIE11 (Bit 11) */
+#define ADC1_FIER_FULIE11_Msk (0x800UL) /*!< FULIE11 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE10_Pos (10UL) /*!< FULIE10 (Bit 10) */
+#define ADC1_FIER_FULIE10_Msk (0x400UL) /*!< FULIE10 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE9_Pos (9UL) /*!< FULIE9 (Bit 9) */
+#define ADC1_FIER_FULIE9_Msk (0x200UL) /*!< FULIE9 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE8_Pos (8UL) /*!< FULIE8 (Bit 8) */
+#define ADC1_FIER_FULIE8_Msk (0x100UL) /*!< FULIE8 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE7_Pos (7UL) /*!< FULIE7 (Bit 7) */
+#define ADC1_FIER_FULIE7_Msk (0x80UL) /*!< FULIE7 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE6_Pos (6UL) /*!< FULIE6 (Bit 6) */
+#define ADC1_FIER_FULIE6_Msk (0x40UL) /*!< FULIE6 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE5_Pos (5UL) /*!< FULIE5 (Bit 5) */
+#define ADC1_FIER_FULIE5_Msk (0x20UL) /*!< FULIE5 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE4_Pos (4UL) /*!< FULIE4 (Bit 4) */
+#define ADC1_FIER_FULIE4_Msk (0x10UL) /*!< FULIE4 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE3_Pos (3UL) /*!< FULIE3 (Bit 3) */
+#define ADC1_FIER_FULIE3_Msk (0x8UL) /*!< FULIE3 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE2_Pos (2UL) /*!< FULIE2 (Bit 2) */
+#define ADC1_FIER_FULIE2_Msk (0x4UL) /*!< FULIE2 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE1_Pos (1UL) /*!< FULIE1 (Bit 1) */
+#define ADC1_FIER_FULIE1_Msk (0x2UL) /*!< FULIE1 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE0_Pos (0UL) /*!< FULIE0 (Bit 0) */
+#define ADC1_FIER_FULIE0_Msk (0x1UL) /*!< FULIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= TCR0 ========================================================== */
+#define ADC1_TCR0_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR0_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR0_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR0_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR0_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR0_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR0_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR0 ========================================================== */
+#define ADC1_TAR0_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR0_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR0 ========================================================== */
+#define ADC1_TLR0_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR0_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR1 ========================================================== */
+#define ADC1_TCR1_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR1_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR1_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR1_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR1_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR1_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR1_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR1 ========================================================== */
+#define ADC1_TAR1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR1_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR1 ========================================================== */
+#define ADC1_TLR1_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR1_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR2 ========================================================== */
+#define ADC1_TCR2_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR2_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR2_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR2_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR2_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR2_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR2_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR2 ========================================================== */
+#define ADC1_TAR2_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR2_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR2 ========================================================== */
+#define ADC1_TLR2_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR2_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR3 ========================================================== */
+#define ADC1_TCR3_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR3_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR3_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR3_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR3_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR3_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR3_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR3 ========================================================== */
+#define ADC1_TAR3_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR3_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR3 ========================================================== */
+#define ADC1_TLR3_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR3_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR4 ========================================================== */
+#define ADC1_TCR4_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR4_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR4_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR4_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR4_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR4_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR4_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR4_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR4 ========================================================== */
+#define ADC1_TAR4_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR4_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR4 ========================================================== */
+#define ADC1_TLR4_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR4_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR5 ========================================================== */
+#define ADC1_TCR5_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR5_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR5_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR5_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR5_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR5_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR5_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR5_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR5 ========================================================== */
+#define ADC1_TAR5_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR5_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR5 ========================================================== */
+#define ADC1_TLR5_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR5_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR6 ========================================================== */
+#define ADC1_TCR6_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR6_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR6_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR6_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR6_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR6_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR6_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR6_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR6 ========================================================== */
+#define ADC1_TAR6_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR6_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR6 ========================================================== */
+#define ADC1_TLR6_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR6_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR7 ========================================================== */
+#define ADC1_TCR7_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR7_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR7_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR7_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR7_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR7_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR7_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR7_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR7 ========================================================== */
+#define ADC1_TAR7_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR7_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR7 ========================================================== */
+#define ADC1_TLR7_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR7_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR8 ========================================================== */
+#define ADC1_TCR8_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR8_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR8_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR8_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR8_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR8_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR8_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR8_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR8 ========================================================== */
+#define ADC1_TAR8_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR8_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR8 ========================================================== */
+#define ADC1_TLR8_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR8_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR9 ========================================================== */
+#define ADC1_TCR9_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR9_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR9_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR9_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR9_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR9_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR9_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR9_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR9 ========================================================== */
+#define ADC1_TAR9_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR9_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR9 ========================================================== */
+#define ADC1_TLR9_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR9_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR10 ========================================================= */
+#define ADC1_TCR10_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR10_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR10_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR10_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR10_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR10_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR10_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR10_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR10 ========================================================= */
+#define ADC1_TAR10_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR10_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR10 ========================================================= */
+#define ADC1_TLR10_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR10_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR11 ========================================================= */
+#define ADC1_TCR11_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR11_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR11_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR11_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR11_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR11_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR11_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR11_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR11 ========================================================= */
+#define ADC1_TAR11_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR11_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR11 ========================================================= */
+#define ADC1_TLR11_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR11_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR12 ========================================================= */
+#define ADC1_TCR12_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR12_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR12_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR12_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR12_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR12_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR12_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR12_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR12 ========================================================= */
+#define ADC1_TAR12_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR12_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR12 ========================================================= */
+#define ADC1_TLR12_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR12_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR13 ========================================================= */
+#define ADC1_TCR13_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR13_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR13_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR13_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR13_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR13_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR13_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR13_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR13 ========================================================= */
+#define ADC1_TAR13_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR13_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR13 ========================================================= */
+#define ADC1_TLR13_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR13_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR14 ========================================================= */
+#define ADC1_TCR14_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR14_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR14_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR14_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR14_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR14_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR14_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR14_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR14 ========================================================= */
+#define ADC1_TAR14_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR14_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR14 ========================================================= */
+#define ADC1_TLR14_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR14_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR15 ========================================================= */
+#define ADC1_TCR15_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR15_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR15_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR15_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR15_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR15_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR15_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR15_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR15 ========================================================= */
+#define ADC1_TAR15_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR15_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR15 ========================================================= */
+#define ADC1_TLR15_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR15_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR16 ========================================================= */
+#define ADC1_TCR16_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR16_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR16_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR16_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR16_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR16_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR16_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR16_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR16 ========================================================= */
+#define ADC1_TAR16_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR16_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR16 ========================================================= */
+#define ADC1_TLR16_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR16_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR17 ========================================================= */
+#define ADC1_TCR17_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR17_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR17_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR17_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR17_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR17_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR17_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR17_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR17 ========================================================= */
+#define ADC1_TAR17_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR17_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR17 ========================================================= */
+#define ADC1_TLR17_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR17_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR18 ========================================================= */
+#define ADC1_TCR18_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR18_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR18_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR18_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR18_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR18_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR18_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR18_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR18 ========================================================= */
+#define ADC1_TAR18_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR18_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR18 ========================================================= */
+#define ADC1_TLR18_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR18_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR19 ========================================================= */
+#define ADC1_TCR19_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR19_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR19_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR19_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR19_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR19_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR19_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR19_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR19 ========================================================= */
+#define ADC1_TAR19_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR19_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR19 ========================================================= */
+#define ADC1_TLR19_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR19_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================== CCR ========================================================== */
+#define ADC1_CCR_DELAY_Pos (8UL) /*!< DELAY (Bit 8) */
+#define ADC1_CCR_DELAY_Msk (0x3ff00UL) /*!< DELAY (Bitfield-Mask: 0x3ff) */
+#define ADC1_CCR_DUAL_Pos (0UL) /*!< DUAL (Bit 0) */
+#define ADC1_CCR_DUAL_Msk (0xfUL) /*!< DUAL (Bitfield-Mask: 0x0f) */
+/* ========================================================== CSR ========================================================== */
+#define ADC1_CSR_EOSMP_SLV_Pos (25UL) /*!< EOSMP_SLV (Bit 25) */
+#define ADC1_CSR_EOSMP_SLV_Msk (0x2000000UL) /*!< EOSMP_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_ADRDY_SLV_Pos (24UL) /*!< ADRDY_SLV (Bit 24) */
+#define ADC1_CSR_ADRDY_SLV_Msk (0x1000000UL) /*!< ADRDY_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD2_SLV_Pos (23UL) /*!< AWD2_SLV (Bit 23) */
+#define ADC1_CSR_AWD2_SLV_Msk (0x800000UL) /*!< AWD2_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD1_SLV_Pos (22UL) /*!< AWD1_SLV (Bit 22) */
+#define ADC1_CSR_AWD1_SLV_Msk (0x400000UL) /*!< AWD1_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD0_SLV_Pos (21UL) /*!< AWD0_SLV (Bit 21) */
+#define ADC1_CSR_AWD0_SLV_Msk (0x200000UL) /*!< AWD0_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_OVR_SLV_Pos (20UL) /*!< OVR_SLV (Bit 20) */
+#define ADC1_CSR_OVR_SLV_Msk (0x100000UL) /*!< OVR_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_JEOS_SLV_Pos (19UL) /*!< JEOS_SLV (Bit 19) */
+#define ADC1_CSR_JEOS_SLV_Msk (0x80000UL) /*!< JEOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_JEOC_SLV_Pos (18UL) /*!< JEOC_SLV (Bit 18) */
+#define ADC1_CSR_JEOC_SLV_Msk (0x40000UL) /*!< JEOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_EOS_SLV_Pos (17UL) /*!< EOS_SLV (Bit 17) */
+#define ADC1_CSR_EOS_SLV_Msk (0x20000UL) /*!< EOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_EOC_SLV_Pos (16UL) /*!< EOC_SLV (Bit 16) */
+#define ADC1_CSR_EOC_SLV_Msk (0x10000UL) /*!< EOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_EOSMP_MST_Pos (9UL) /*!< EOSMP_MST (Bit 9) */
+#define ADC1_CSR_EOSMP_MST_Msk (0x200UL) /*!< EOSMP_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_ADRDY_MST_Pos (8UL) /*!< ADRDY_MST (Bit 8) */
+#define ADC1_CSR_ADRDY_MST_Msk (0x100UL) /*!< ADRDY_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD2_MST_Pos (7UL) /*!< AWD2_MST (Bit 7) */
+#define ADC1_CSR_AWD2_MST_Msk (0x80UL) /*!< AWD2_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD1_MST_Pos (6UL) /*!< AWD1_MST (Bit 6) */
+#define ADC1_CSR_AWD1_MST_Msk (0x40UL) /*!< AWD1_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD0_MST_Pos (5UL) /*!< AWD0_MST (Bit 5) */
+#define ADC1_CSR_AWD0_MST_Msk (0x20UL) /*!< AWD0_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_OVR_MST_Pos (4UL) /*!< OVR_MST (Bit 4) */
+#define ADC1_CSR_OVR_MST_Msk (0x10UL) /*!< OVR_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_JEOS_MST_Pos (3UL) /*!< JEOS_MST (Bit 3) */
+#define ADC1_CSR_JEOS_MST_Msk (0x8UL) /*!< JEOS_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_JEOC_MST_Pos (2UL) /*!< JEOC_MST (Bit 2) */
+#define ADC1_CSR_JEOC_MST_Msk (0x4UL) /*!< JEOC_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_EOS_MST_Pos (1UL) /*!< EOS_MST (Bit 1) */
+#define ADC1_CSR_EOS_MST_Msk (0x2UL) /*!< EOS_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_EOC_MST_Pos (0UL) /*!< EOC_MST (Bit 0) */
+#define ADC1_CSR_EOC_MST_Msk (0x1UL) /*!< EOC_MST (Bitfield-Mask: 0x01) */
+/* ========================================================== CDR ========================================================== */
+#define ADC1_CDR_RDATA_SLV_Pos (16UL) /*!< RDATA_SLV (Bit 16) */
+#define ADC1_CDR_RDATA_SLV_Msk (0xffff0000UL) /*!< RDATA_SLV (Bitfield-Mask: 0xffff) */
+#define ADC1_CDR_RDATA_MST_Pos (0UL) /*!< RDATA_MST (Bit 0) */
+#define ADC1_CDR_RDATA_MST_Msk (0xffffUL) /*!< RDATA_MST (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ ADC2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define ADC2_CR_ADCALDIF_Pos (7UL) /*!< ADCALDIF (Bit 7) */
+#define ADC2_CR_ADCALDIF_Msk (0x80UL) /*!< ADCALDIF (Bitfield-Mask: 0x01) */
+#define ADC2_CR_ADCAL_Pos (6UL) /*!< ADCAL (Bit 6) */
+#define ADC2_CR_ADCAL_Msk (0x40UL) /*!< ADCAL (Bitfield-Mask: 0x01) */
+#define ADC2_CR_JADSTP_Pos (5UL) /*!< JADSTP (Bit 5) */
+#define ADC2_CR_JADSTP_Msk (0x20UL) /*!< JADSTP (Bitfield-Mask: 0x01) */
+#define ADC2_CR_ADSTP_Pos (4UL) /*!< ADSTP (Bit 4) */
+#define ADC2_CR_ADSTP_Msk (0x10UL) /*!< ADSTP (Bitfield-Mask: 0x01) */
+#define ADC2_CR_JADSTART_Pos (3UL) /*!< JADSTART (Bit 3) */
+#define ADC2_CR_JADSTART_Msk (0x8UL) /*!< JADSTART (Bitfield-Mask: 0x01) */
+#define ADC2_CR_ADSTART_Pos (2UL) /*!< ADSTART (Bit 2) */
+#define ADC2_CR_ADSTART_Msk (0x4UL) /*!< ADSTART (Bitfield-Mask: 0x01) */
+#define ADC2_CR_ADDIS_Pos (1UL) /*!< ADDIS (Bit 1) */
+#define ADC2_CR_ADDIS_Msk (0x2UL) /*!< ADDIS (Bitfield-Mask: 0x01) */
+#define ADC2_CR_ADEN_Pos (0UL) /*!< ADEN (Bit 0) */
+#define ADC2_CR_ADEN_Msk (0x1UL) /*!< ADEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR0 ========================================================= */
+#define ADC2_CFGR0_OVSCAL_Pos (28UL) /*!< OVSCAL (Bit 28) */
+#define ADC2_CFGR0_OVSCAL_Msk (0x70000000UL) /*!< OVSCAL (Bitfield-Mask: 0x07) */
+#define ADC2_CFGR0_CONT_Pos (23UL) /*!< CONT (Bit 23) */
+#define ADC2_CFGR0_CONT_Msk (0x800000UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_JAUTO_Pos (22UL) /*!< JAUTO (Bit 22) */
+#define ADC2_CFGR0_JAUTO_Msk (0x400000UL) /*!< JAUTO (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_JDISCEN_Pos (20UL) /*!< JDISCEN (Bit 20) */
+#define ADC2_CFGR0_JDISCEN_Msk (0x100000UL) /*!< JDISCEN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_DISCNUM_Pos (17UL) /*!< DISCNUM (Bit 17) */
+#define ADC2_CFGR0_DISCNUM_Msk (0xe0000UL) /*!< DISCNUM (Bitfield-Mask: 0x07) */
+#define ADC2_CFGR0_DISCEN_Pos (16UL) /*!< DISCEN (Bit 16) */
+#define ADC2_CFGR0_DISCEN_Msk (0x10000UL) /*!< DISCEN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_OVRMOD_Pos (15UL) /*!< OVRMOD (Bit 15) */
+#define ADC2_CFGR0_OVRMOD_Msk (0x8000UL) /*!< OVRMOD (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_SDMAEN_Pos (14UL) /*!< SDMAEN (Bit 14) */
+#define ADC2_CFGR0_SDMAEN_Msk (0x4000UL) /*!< SDMAEN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_TROVS_Pos (12UL) /*!< TROVS (Bit 12) */
+#define ADC2_CFGR0_TROVS_Msk (0x1000UL) /*!< TROVS (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_OVSS_Pos (8UL) /*!< OVSS (Bit 8) */
+#define ADC2_CFGR0_OVSS_Msk (0xf00UL) /*!< OVSS (Bitfield-Mask: 0x0f) */
+#define ADC2_CFGR0_ROVSM_Pos (7UL) /*!< ROVSM (Bit 7) */
+#define ADC2_CFGR0_ROVSM_Msk (0x80UL) /*!< ROVSM (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_OVSR_Pos (4UL) /*!< OVSR (Bit 4) */
+#define ADC2_CFGR0_OVSR_Msk (0x70UL) /*!< OVSR (Bitfield-Mask: 0x07) */
+#define ADC2_CFGR0_JOVSE_Pos (1UL) /*!< JOVSE (Bit 1) */
+#define ADC2_CFGR0_JOVSE_Msk (0x2UL) /*!< JOVSE (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_ROVSE_Pos (0UL) /*!< ROVSE (Bit 0) */
+#define ADC2_CFGR0_ROVSE_Msk (0x1UL) /*!< ROVSE (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR1 ========================================================= */
+#define ADC2_CFGR1_JAWD2EN_Pos (14UL) /*!< JAWD2EN (Bit 14) */
+#define ADC2_CFGR1_JAWD2EN_Msk (0x4000UL) /*!< JAWD2EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_JAWD1EN_Pos (13UL) /*!< JAWD1EN (Bit 13) */
+#define ADC2_CFGR1_JAWD1EN_Msk (0x2000UL) /*!< JAWD1EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_JAWD0EN_Pos (12UL) /*!< JAWD0EN (Bit 12) */
+#define ADC2_CFGR1_JAWD0EN_Msk (0x1000UL) /*!< JAWD0EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_AWD2EN_Pos (10UL) /*!< AWD2EN (Bit 10) */
+#define ADC2_CFGR1_AWD2EN_Msk (0x400UL) /*!< AWD2EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_AWD1EN_Pos (9UL) /*!< AWD1EN (Bit 9) */
+#define ADC2_CFGR1_AWD1EN_Msk (0x200UL) /*!< AWD1EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_AWD0EN_Pos (8UL) /*!< AWD0EN (Bit 8) */
+#define ADC2_CFGR1_AWD0EN_Msk (0x100UL) /*!< AWD0EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_ISEL_Pos (4UL) /*!< ISEL (Bit 4) */
+#define ADC2_CFGR1_ISEL_Msk (0x30UL) /*!< ISEL (Bitfield-Mask: 0x03) */
+#define ADC2_CFGR1_CHEN_Pos (3UL) /*!< CHEN (Bit 3) */
+#define ADC2_CFGR1_CHEN_Msk (0x8UL) /*!< CHEN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_REFEN_Pos (1UL) /*!< REFEN (Bit 1) */
+#define ADC2_CFGR1_REFEN_Msk (0x2UL) /*!< REFEN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_BIASEN_Pos (0UL) /*!< BIASEN (Bit 0) */
+#define ADC2_CFGR1_BIASEN_Msk (0x1UL) /*!< BIASEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define ADC2_ISR_EOSMP_Pos (9UL) /*!< EOSMP (Bit 9) */
+#define ADC2_ISR_EOSMP_Msk (0x200UL) /*!< EOSMP (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_ADRDY_Pos (8UL) /*!< ADRDY (Bit 8) */
+#define ADC2_ISR_ADRDY_Msk (0x100UL) /*!< ADRDY (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_AWD2_Pos (7UL) /*!< AWD2 (Bit 7) */
+#define ADC2_ISR_AWD2_Msk (0x80UL) /*!< AWD2 (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_AWD1_Pos (6UL) /*!< AWD1 (Bit 6) */
+#define ADC2_ISR_AWD1_Msk (0x40UL) /*!< AWD1 (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_AWD0_Pos (5UL) /*!< AWD0 (Bit 5) */
+#define ADC2_ISR_AWD0_Msk (0x20UL) /*!< AWD0 (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_OVR_Pos (4UL) /*!< OVR (Bit 4) */
+#define ADC2_ISR_OVR_Msk (0x10UL) /*!< OVR (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_JEOS_Pos (3UL) /*!< JEOS (Bit 3) */
+#define ADC2_ISR_JEOS_Msk (0x8UL) /*!< JEOS (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_JEOC_Pos (2UL) /*!< JEOC (Bit 2) */
+#define ADC2_ISR_JEOC_Msk (0x4UL) /*!< JEOC (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */
+#define ADC2_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */
+#define ADC2_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define ADC2_IER_EOSMPIE_Pos (9UL) /*!< EOSMPIE (Bit 9) */
+#define ADC2_IER_EOSMPIE_Msk (0x200UL) /*!< EOSMPIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_ADRDYIE_Pos (8UL) /*!< ADRDYIE (Bit 8) */
+#define ADC2_IER_ADRDYIE_Msk (0x100UL) /*!< ADRDYIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_AWD2IE_Pos (7UL) /*!< AWD2IE (Bit 7) */
+#define ADC2_IER_AWD2IE_Msk (0x80UL) /*!< AWD2IE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_AWD1IE_Pos (6UL) /*!< AWD1IE (Bit 6) */
+#define ADC2_IER_AWD1IE_Msk (0x40UL) /*!< AWD1IE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_AWD0IE_Pos (5UL) /*!< AWD0IE (Bit 5) */
+#define ADC2_IER_AWD0IE_Msk (0x20UL) /*!< AWD0IE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_OVRIE_Pos (4UL) /*!< OVRIE (Bit 4) */
+#define ADC2_IER_OVRIE_Msk (0x10UL) /*!< OVRIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_JEOSIE_Pos (3UL) /*!< JEOSIE (Bit 3) */
+#define ADC2_IER_JEOSIE_Msk (0x8UL) /*!< JEOSIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_JEOCIE_Pos (2UL) /*!< JEOCIE (Bit 2) */
+#define ADC2_IER_JEOCIE_Msk (0x4UL) /*!< JEOCIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_EOSIE_Pos (1UL) /*!< EOSIE (Bit 1) */
+#define ADC2_IER_EOSIE_Msk (0x2UL) /*!< EOSIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_EOCIE_Pos (0UL) /*!< EOCIE (Bit 0) */
+#define ADC2_IER_EOCIE_Msk (0x1UL) /*!< EOCIE (Bitfield-Mask: 0x01) */
+/* ======================================================== SIGSEL ========================================================= */
+#define ADC2_SIGSEL_SIGSEL_Pos (0UL) /*!< SIGSEL (Bit 0) */
+#define ADC2_SIGSEL_SIGSEL_Msk (0xfffffUL) /*!< SIGSEL (Bitfield-Mask: 0xfffff) */
+/* ========================================================= SMPR0 ========================================================= */
+#define ADC2_SMPR0_SMP7_Pos (28UL) /*!< SMP7 (Bit 28) */
+#define ADC2_SMPR0_SMP7_Msk (0x70000000UL) /*!< SMP7 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP6_Pos (24UL) /*!< SMP6 (Bit 24) */
+#define ADC2_SMPR0_SMP6_Msk (0x7000000UL) /*!< SMP6 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP5_Pos (20UL) /*!< SMP5 (Bit 20) */
+#define ADC2_SMPR0_SMP5_Msk (0x700000UL) /*!< SMP5 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP4_Pos (16UL) /*!< SMP4 (Bit 16) */
+#define ADC2_SMPR0_SMP4_Msk (0x70000UL) /*!< SMP4 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP3_Pos (12UL) /*!< SMP3 (Bit 12) */
+#define ADC2_SMPR0_SMP3_Msk (0x7000UL) /*!< SMP3 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP2_Pos (8UL) /*!< SMP2 (Bit 8) */
+#define ADC2_SMPR0_SMP2_Msk (0x700UL) /*!< SMP2 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP1_Pos (4UL) /*!< SMP1 (Bit 4) */
+#define ADC2_SMPR0_SMP1_Msk (0x70UL) /*!< SMP1 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP0_Pos (0UL) /*!< SMP0 (Bit 0) */
+#define ADC2_SMPR0_SMP0_Msk (0x7UL) /*!< SMP0 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR1 ========================================================= */
+#define ADC2_SMPR1_SMP15_Pos (28UL) /*!< SMP15 (Bit 28) */
+#define ADC2_SMPR1_SMP15_Msk (0x70000000UL) /*!< SMP15 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP14_Pos (24UL) /*!< SMP14 (Bit 24) */
+#define ADC2_SMPR1_SMP14_Msk (0x7000000UL) /*!< SMP14 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP13_Pos (20UL) /*!< SMP13 (Bit 20) */
+#define ADC2_SMPR1_SMP13_Msk (0x700000UL) /*!< SMP13 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP12_Pos (16UL) /*!< SMP12 (Bit 16) */
+#define ADC2_SMPR1_SMP12_Msk (0x70000UL) /*!< SMP12 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP11_Pos (12UL) /*!< SMP11 (Bit 12) */
+#define ADC2_SMPR1_SMP11_Msk (0x7000UL) /*!< SMP11 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP10_Pos (8UL) /*!< SMP10 (Bit 8) */
+#define ADC2_SMPR1_SMP10_Msk (0x700UL) /*!< SMP10 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP9_Pos (4UL) /*!< SMP9 (Bit 4) */
+#define ADC2_SMPR1_SMP9_Msk (0x70UL) /*!< SMP9 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP8_Pos (0UL) /*!< SMP8 (Bit 0) */
+#define ADC2_SMPR1_SMP8_Msk (0x7UL) /*!< SMP8 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR2 ========================================================= */
+#define ADC2_SMPR2_SMP19_Pos (12UL) /*!< SMP19 (Bit 12) */
+#define ADC2_SMPR2_SMP19_Msk (0x7000UL) /*!< SMP19 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR2_SMP18_Pos (8UL) /*!< SMP18 (Bit 8) */
+#define ADC2_SMPR2_SMP18_Msk (0x700UL) /*!< SMP18 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR2_SMP17_Pos (4UL) /*!< SMP17 (Bit 4) */
+#define ADC2_SMPR2_SMP17_Msk (0x70UL) /*!< SMP17 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR2_SMP16_Pos (0UL) /*!< SMP16 (Bit 0) */
+#define ADC2_SMPR2_SMP16_Msk (0x7UL) /*!< SMP16 (Bitfield-Mask: 0x07) */
+/* ========================================================= CALR0 ========================================================= */
+#define ADC2_CALR0_SAT7_Pos (31UL) /*!< SAT7 (Bit 31) */
+#define ADC2_CALR0_SAT7_Msk (0x80000000UL) /*!< SAT7 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL7_Pos (28UL) /*!< CAL7 (Bit 28) */
+#define ADC2_CALR0_CAL7_Msk (0x30000000UL) /*!< CAL7 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT6_Pos (27UL) /*!< SAT6 (Bit 27) */
+#define ADC2_CALR0_SAT6_Msk (0x8000000UL) /*!< SAT6 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL6_Pos (24UL) /*!< CAL6 (Bit 24) */
+#define ADC2_CALR0_CAL6_Msk (0x3000000UL) /*!< CAL6 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT5_Pos (23UL) /*!< SAT5 (Bit 23) */
+#define ADC2_CALR0_SAT5_Msk (0x800000UL) /*!< SAT5 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL5_Pos (20UL) /*!< CAL5 (Bit 20) */
+#define ADC2_CALR0_CAL5_Msk (0x300000UL) /*!< CAL5 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT4_Pos (19UL) /*!< SAT4 (Bit 19) */
+#define ADC2_CALR0_SAT4_Msk (0x80000UL) /*!< SAT4 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL4_Pos (16UL) /*!< CAL4 (Bit 16) */
+#define ADC2_CALR0_CAL4_Msk (0x30000UL) /*!< CAL4 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT3_Pos (15UL) /*!< SAT3 (Bit 15) */
+#define ADC2_CALR0_SAT3_Msk (0x8000UL) /*!< SAT3 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL3_Pos (12UL) /*!< CAL3 (Bit 12) */
+#define ADC2_CALR0_CAL3_Msk (0x3000UL) /*!< CAL3 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT2_Pos (11UL) /*!< SAT2 (Bit 11) */
+#define ADC2_CALR0_SAT2_Msk (0x800UL) /*!< SAT2 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL2_Pos (8UL) /*!< CAL2 (Bit 8) */
+#define ADC2_CALR0_CAL2_Msk (0x300UL) /*!< CAL2 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT1_Pos (7UL) /*!< SAT1 (Bit 7) */
+#define ADC2_CALR0_SAT1_Msk (0x80UL) /*!< SAT1 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL1_Pos (4UL) /*!< CAL1 (Bit 4) */
+#define ADC2_CALR0_CAL1_Msk (0x30UL) /*!< CAL1 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT0_Pos (3UL) /*!< SAT0 (Bit 3) */
+#define ADC2_CALR0_SAT0_Msk (0x8UL) /*!< SAT0 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL0_Pos (0UL) /*!< CAL0 (Bit 0) */
+#define ADC2_CALR0_CAL0_Msk (0x3UL) /*!< CAL0 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR1 ========================================================= */
+#define ADC2_CALR1_SAT15_Pos (31UL) /*!< SAT15 (Bit 31) */
+#define ADC2_CALR1_SAT15_Msk (0x80000000UL) /*!< SAT15 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL15_Pos (28UL) /*!< CAL15 (Bit 28) */
+#define ADC2_CALR1_CAL15_Msk (0x30000000UL) /*!< CAL15 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT14_Pos (27UL) /*!< SAT14 (Bit 27) */
+#define ADC2_CALR1_SAT14_Msk (0x8000000UL) /*!< SAT14 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL14_Pos (24UL) /*!< CAL14 (Bit 24) */
+#define ADC2_CALR1_CAL14_Msk (0x3000000UL) /*!< CAL14 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT13_Pos (23UL) /*!< SAT13 (Bit 23) */
+#define ADC2_CALR1_SAT13_Msk (0x800000UL) /*!< SAT13 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL13_Pos (20UL) /*!< CAL13 (Bit 20) */
+#define ADC2_CALR1_CAL13_Msk (0x300000UL) /*!< CAL13 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT12_Pos (19UL) /*!< SAT12 (Bit 19) */
+#define ADC2_CALR1_SAT12_Msk (0x80000UL) /*!< SAT12 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL12_Pos (16UL) /*!< CAL12 (Bit 16) */
+#define ADC2_CALR1_CAL12_Msk (0x30000UL) /*!< CAL12 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT11_Pos (15UL) /*!< SAT11 (Bit 15) */
+#define ADC2_CALR1_SAT11_Msk (0x8000UL) /*!< SAT11 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL11_Pos (12UL) /*!< CAL11 (Bit 12) */
+#define ADC2_CALR1_CAL11_Msk (0x3000UL) /*!< CAL11 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT10_Pos (11UL) /*!< SAT10 (Bit 11) */
+#define ADC2_CALR1_SAT10_Msk (0x800UL) /*!< SAT10 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL10_Pos (8UL) /*!< CAL10 (Bit 8) */
+#define ADC2_CALR1_CAL10_Msk (0x300UL) /*!< CAL10 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT9_Pos (7UL) /*!< SAT9 (Bit 7) */
+#define ADC2_CALR1_SAT9_Msk (0x80UL) /*!< SAT9 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL9_Pos (4UL) /*!< CAL9 (Bit 4) */
+#define ADC2_CALR1_CAL9_Msk (0x30UL) /*!< CAL9 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT8_Pos (3UL) /*!< SAT8 (Bit 3) */
+#define ADC2_CALR1_SAT8_Msk (0x8UL) /*!< SAT8 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL8_Pos (0UL) /*!< CAL8 (Bit 0) */
+#define ADC2_CALR1_CAL8_Msk (0x3UL) /*!< CAL8 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR2 ========================================================= */
+#define ADC2_CALR2_SAT19_Pos (15UL) /*!< SAT19 (Bit 15) */
+#define ADC2_CALR2_SAT19_Msk (0x8000UL) /*!< SAT19 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR2_CAL19_Pos (12UL) /*!< CAL19 (Bit 12) */
+#define ADC2_CALR2_CAL19_Msk (0x3000UL) /*!< CAL19 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR2_SAT18_Pos (11UL) /*!< SAT18 (Bit 11) */
+#define ADC2_CALR2_SAT18_Msk (0x800UL) /*!< SAT18 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR2_CAL18_Pos (8UL) /*!< CAL18 (Bit 8) */
+#define ADC2_CALR2_CAL18_Msk (0x300UL) /*!< CAL18 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR2_SAT17_Pos (7UL) /*!< SAT17 (Bit 7) */
+#define ADC2_CALR2_SAT17_Msk (0x80UL) /*!< SAT17 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR2_CAL17_Pos (4UL) /*!< CAL17 (Bit 4) */
+#define ADC2_CALR2_CAL17_Msk (0x30UL) /*!< CAL17 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR2_SAT16_Pos (3UL) /*!< SAT16 (Bit 3) */
+#define ADC2_CALR2_SAT16_Msk (0x8UL) /*!< SAT16 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR2_CAL16_Pos (0UL) /*!< CAL16 (Bit 0) */
+#define ADC2_CALR2_CAL16_Msk (0x3UL) /*!< CAL16 (Bitfield-Mask: 0x03) */
+/* ========================================================= SQR0 ========================================================== */
+#define ADC2_SQR0_SQ5_Pos (24UL) /*!< SQ5 (Bit 24) */
+#define ADC2_SQR0_SQ5_Msk (0x1f000000UL) /*!< SQ5 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR0_SQ4_Pos (18UL) /*!< SQ4 (Bit 18) */
+#define ADC2_SQR0_SQ4_Msk (0x7c0000UL) /*!< SQ4 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR0_SQ3_Pos (12UL) /*!< SQ3 (Bit 12) */
+#define ADC2_SQR0_SQ3_Msk (0x1f000UL) /*!< SQ3 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR0_SQ2_Pos (6UL) /*!< SQ2 (Bit 6) */
+#define ADC2_SQR0_SQ2_Msk (0x7c0UL) /*!< SQ2 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR0_SQ1_Pos (0UL) /*!< SQ1 (Bit 0) */
+#define ADC2_SQR0_SQ1_Msk (0x1fUL) /*!< SQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR1 ========================================================== */
+#define ADC2_SQR1_SQ10_Pos (24UL) /*!< SQ10 (Bit 24) */
+#define ADC2_SQR1_SQ10_Msk (0x1f000000UL) /*!< SQ10 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR1_SQ9_Pos (18UL) /*!< SQ9 (Bit 18) */
+#define ADC2_SQR1_SQ9_Msk (0x7c0000UL) /*!< SQ9 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR1_SQ8_Pos (12UL) /*!< SQ8 (Bit 12) */
+#define ADC2_SQR1_SQ8_Msk (0x1f000UL) /*!< SQ8 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR1_SQ7_Pos (6UL) /*!< SQ7 (Bit 6) */
+#define ADC2_SQR1_SQ7_Msk (0x7c0UL) /*!< SQ7 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR1_SQ6_Pos (0UL) /*!< SQ6 (Bit 0) */
+#define ADC2_SQR1_SQ6_Msk (0x1fUL) /*!< SQ6 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR2 ========================================================== */
+#define ADC2_SQR2_SQ15_Pos (24UL) /*!< SQ15 (Bit 24) */
+#define ADC2_SQR2_SQ15_Msk (0x1f000000UL) /*!< SQ15 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR2_SQ14_Pos (18UL) /*!< SQ14 (Bit 18) */
+#define ADC2_SQR2_SQ14_Msk (0x7c0000UL) /*!< SQ14 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR2_SQ13_Pos (12UL) /*!< SQ13 (Bit 12) */
+#define ADC2_SQR2_SQ13_Msk (0x1f000UL) /*!< SQ13 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR2_SQ12_Pos (6UL) /*!< SQ12 (Bit 6) */
+#define ADC2_SQR2_SQ12_Msk (0x7c0UL) /*!< SQ12 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR2_SQ11_Pos (0UL) /*!< SQ11 (Bit 0) */
+#define ADC2_SQR2_SQ11_Msk (0x1fUL) /*!< SQ11 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR3 ========================================================== */
+#define ADC2_SQR3_SQ16_Pos (0UL) /*!< SQ16 (Bit 0) */
+#define ADC2_SQR3_SQ16_Msk (0x1fUL) /*!< SQ16 (Bitfield-Mask: 0x1f) */
+/* ========================================================== LR =========================================================== */
+#define ADC2_LR_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define ADC2_LR_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define ADC2_LR_EXTEN_Pos (6UL) /*!< EXTEN (Bit 6) */
+#define ADC2_LR_EXTEN_Msk (0xc0UL) /*!< EXTEN (Bitfield-Mask: 0x03) */
+#define ADC2_LR_EXTSEL_Pos (0UL) /*!< EXTSEL (Bit 0) */
+#define ADC2_LR_EXTSEL_Msk (0x1fUL) /*!< EXTSEL (Bitfield-Mask: 0x1f) */
+/* ========================================================== DR =========================================================== */
+#define ADC2_DR_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */
+#define ADC2_DR_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MAXDR ========================================================= */
+#define ADC2_MAXDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC2_MAXDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MINDR ========================================================= */
+#define ADC2_MINDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC2_MINDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JSQR ========================================================== */
+#define ADC2_JSQR_JSQ4_Pos (18UL) /*!< JSQ4 (Bit 18) */
+#define ADC2_JSQR_JSQ4_Msk (0x7c0000UL) /*!< JSQ4 (Bitfield-Mask: 0x1f) */
+#define ADC2_JSQR_JSQ3_Pos (12UL) /*!< JSQ3 (Bit 12) */
+#define ADC2_JSQR_JSQ3_Msk (0x1f000UL) /*!< JSQ3 (Bitfield-Mask: 0x1f) */
+#define ADC2_JSQR_JSQ2_Pos (6UL) /*!< JSQ2 (Bit 6) */
+#define ADC2_JSQR_JSQ2_Msk (0x7c0UL) /*!< JSQ2 (Bitfield-Mask: 0x1f) */
+#define ADC2_JSQR_JSQ1_Pos (0UL) /*!< JSQ1 (Bit 0) */
+#define ADC2_JSQR_JSQ1_Msk (0x1fUL) /*!< JSQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================== JLR ========================================================== */
+#define ADC2_JLR_JLEN_Pos (8UL) /*!< JLEN (Bit 8) */
+#define ADC2_JLR_JLEN_Msk (0x300UL) /*!< JLEN (Bitfield-Mask: 0x03) */
+#define ADC2_JLR_JEXTEN_Pos (6UL) /*!< JEXTEN (Bit 6) */
+#define ADC2_JLR_JEXTEN_Msk (0xc0UL) /*!< JEXTEN (Bitfield-Mask: 0x03) */
+#define ADC2_JLR_JEXTSEL_Pos (0UL) /*!< JEXTSEL (Bit 0) */
+#define ADC2_JLR_JEXTSEL_Msk (0x1fUL) /*!< JEXTSEL (Bitfield-Mask: 0x1f) */
+/* ======================================================== MAXJDR ========================================================= */
+#define ADC2_MAXJDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC2_MAXJDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ======================================================== MINJDR ========================================================= */
+#define ADC2_MINJDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC2_MINJDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR0 ========================================================== */
+#define ADC2_JDR0_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC2_JDR0_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR1 ========================================================== */
+#define ADC2_JDR1_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC2_JDR1_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR2 ========================================================== */
+#define ADC2_JDR2_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC2_JDR2_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR3 ========================================================== */
+#define ADC2_JDR3_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC2_JDR3_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR0 ========================================================== */
+#define ADC2_TR0_HT0_Pos (16UL) /*!< HT0 (Bit 16) */
+#define ADC2_TR0_HT0_Msk (0xffff0000UL) /*!< HT0 (Bitfield-Mask: 0xffff) */
+#define ADC2_TR0_LT0_Pos (0UL) /*!< LT0 (Bit 0) */
+#define ADC2_TR0_LT0_Msk (0xffffUL) /*!< LT0 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR1 ========================================================== */
+#define ADC2_TR1_HT1_Pos (16UL) /*!< HT1 (Bit 16) */
+#define ADC2_TR1_HT1_Msk (0xffff0000UL) /*!< HT1 (Bitfield-Mask: 0xffff) */
+#define ADC2_TR1_LT1_Pos (0UL) /*!< LT1 (Bit 0) */
+#define ADC2_TR1_LT1_Msk (0xffffUL) /*!< LT1 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR2 ========================================================== */
+#define ADC2_TR2_HT2_Pos (16UL) /*!< HT2 (Bit 16) */
+#define ADC2_TR2_HT2_Msk (0xffff0000UL) /*!< HT2 (Bitfield-Mask: 0xffff) */
+#define ADC2_TR2_LT2_Pos (0UL) /*!< LT2 (Bit 0) */
+#define ADC2_TR2_LT2_Msk (0xffffUL) /*!< LT2 (Bitfield-Mask: 0xffff) */
+/* ======================================================== AWD0CR ========================================================= */
+#define ADC2_AWD0CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC2_AWD0CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC2_AWD0CR_AW0CH_Pos (0UL) /*!< AW0CH (Bit 0) */
+#define ADC2_AWD0CR_AW0CH_Msk (0xfffffUL) /*!< AW0CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD1CR ========================================================= */
+#define ADC2_AWD1CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC2_AWD1CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC2_AWD1CR_AW1CH_Pos (0UL) /*!< AW1CH (Bit 0) */
+#define ADC2_AWD1CR_AW1CH_Msk (0xfffffUL) /*!< AW1CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD2CR ========================================================= */
+#define ADC2_AWD2CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC2_AWD2CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC2_AWD2CR_AW2CH_Pos (0UL) /*!< AW2CH (Bit 0) */
+#define ADC2_AWD2CR_AW2CH_Msk (0xfffffUL) /*!< AW2CH (Bitfield-Mask: 0xfffff) */
+/* ========================================================= OFR0 ========================================================== */
+#define ADC2_OFR0_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC2_OFR0_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR1 ========================================================== */
+#define ADC2_OFR1_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC2_OFR1_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR2 ========================================================== */
+#define ADC2_OFR2_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC2_OFR2_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR3 ========================================================== */
+#define ADC2_OFR3_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC2_OFR3_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= GCR0 ========================================================== */
+#define ADC2_GCR0_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC2_GCR0_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR1 ========================================================== */
+#define ADC2_GCR1_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC2_GCR1_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR2 ========================================================== */
+#define ADC2_GCR2_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC2_GCR2_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR3 ========================================================== */
+#define ADC2_GCR3_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC2_GCR3_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= DISR ========================================================== */
+#define ADC2_DISR_DON19_Pos (19UL) /*!< DON19 (Bit 19) */
+#define ADC2_DISR_DON19_Msk (0x80000UL) /*!< DON19 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON18_Pos (18UL) /*!< DON18 (Bit 18) */
+#define ADC2_DISR_DON18_Msk (0x40000UL) /*!< DON18 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON17_Pos (17UL) /*!< DON17 (Bit 17) */
+#define ADC2_DISR_DON17_Msk (0x20000UL) /*!< DON17 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON16_Pos (16UL) /*!< DON16 (Bit 16) */
+#define ADC2_DISR_DON16_Msk (0x10000UL) /*!< DON16 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON15_Pos (15UL) /*!< DON15 (Bit 15) */
+#define ADC2_DISR_DON15_Msk (0x8000UL) /*!< DON15 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON14_Pos (14UL) /*!< DON14 (Bit 14) */
+#define ADC2_DISR_DON14_Msk (0x4000UL) /*!< DON14 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON13_Pos (13UL) /*!< DON13 (Bit 13) */
+#define ADC2_DISR_DON13_Msk (0x2000UL) /*!< DON13 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON12_Pos (12UL) /*!< DON12 (Bit 12) */
+#define ADC2_DISR_DON12_Msk (0x1000UL) /*!< DON12 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON11_Pos (11UL) /*!< DON11 (Bit 11) */
+#define ADC2_DISR_DON11_Msk (0x800UL) /*!< DON11 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON10_Pos (10UL) /*!< DON10 (Bit 10) */
+#define ADC2_DISR_DON10_Msk (0x400UL) /*!< DON10 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON9_Pos (9UL) /*!< DON9 (Bit 9) */
+#define ADC2_DISR_DON9_Msk (0x200UL) /*!< DON9 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON8_Pos (8UL) /*!< DON8 (Bit 8) */
+#define ADC2_DISR_DON8_Msk (0x100UL) /*!< DON8 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON7_Pos (7UL) /*!< DON7 (Bit 7) */
+#define ADC2_DISR_DON7_Msk (0x80UL) /*!< DON7 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON6_Pos (6UL) /*!< DON6 (Bit 6) */
+#define ADC2_DISR_DON6_Msk (0x40UL) /*!< DON6 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON5_Pos (5UL) /*!< DON5 (Bit 5) */
+#define ADC2_DISR_DON5_Msk (0x20UL) /*!< DON5 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON4_Pos (4UL) /*!< DON4 (Bit 4) */
+#define ADC2_DISR_DON4_Msk (0x10UL) /*!< DON4 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON3_Pos (3UL) /*!< DON3 (Bit 3) */
+#define ADC2_DISR_DON3_Msk (0x8UL) /*!< DON3 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON2_Pos (2UL) /*!< DON2 (Bit 2) */
+#define ADC2_DISR_DON2_Msk (0x4UL) /*!< DON2 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON1_Pos (1UL) /*!< DON1 (Bit 1) */
+#define ADC2_DISR_DON1_Msk (0x2UL) /*!< DON1 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON0_Pos (0UL) /*!< DON0 (Bit 0) */
+#define ADC2_DISR_DON0_Msk (0x1UL) /*!< DON0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DIER ========================================================== */
+#define ADC2_DIER_DONIE19_Pos (19UL) /*!< DONIE19 (Bit 19) */
+#define ADC2_DIER_DONIE19_Msk (0x80000UL) /*!< DONIE19 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE18_Pos (18UL) /*!< DONIE18 (Bit 18) */
+#define ADC2_DIER_DONIE18_Msk (0x40000UL) /*!< DONIE18 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE17_Pos (17UL) /*!< DONIE17 (Bit 17) */
+#define ADC2_DIER_DONIE17_Msk (0x20000UL) /*!< DONIE17 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE16_Pos (16UL) /*!< DONIE16 (Bit 16) */
+#define ADC2_DIER_DONIE16_Msk (0x10000UL) /*!< DONIE16 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE15_Pos (15UL) /*!< DONIE15 (Bit 15) */
+#define ADC2_DIER_DONIE15_Msk (0x8000UL) /*!< DONIE15 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE14_Pos (14UL) /*!< DONIE14 (Bit 14) */
+#define ADC2_DIER_DONIE14_Msk (0x4000UL) /*!< DONIE14 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE13_Pos (13UL) /*!< DONIE13 (Bit 13) */
+#define ADC2_DIER_DONIE13_Msk (0x2000UL) /*!< DONIE13 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE12_Pos (12UL) /*!< DONIE12 (Bit 12) */
+#define ADC2_DIER_DONIE12_Msk (0x1000UL) /*!< DONIE12 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE11_Pos (11UL) /*!< DONIE11 (Bit 11) */
+#define ADC2_DIER_DONIE11_Msk (0x800UL) /*!< DONIE11 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE10_Pos (10UL) /*!< DONIE10 (Bit 10) */
+#define ADC2_DIER_DONIE10_Msk (0x400UL) /*!< DONIE10 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE9_Pos (9UL) /*!< DONIE9 (Bit 9) */
+#define ADC2_DIER_DONIE9_Msk (0x200UL) /*!< DONIE9 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE8_Pos (8UL) /*!< DONIE8 (Bit 8) */
+#define ADC2_DIER_DONIE8_Msk (0x100UL) /*!< DONIE8 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE7_Pos (7UL) /*!< DONIE7 (Bit 7) */
+#define ADC2_DIER_DONIE7_Msk (0x80UL) /*!< DONIE7 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE6_Pos (6UL) /*!< DONIE6 (Bit 6) */
+#define ADC2_DIER_DONIE6_Msk (0x40UL) /*!< DONIE6 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE5_Pos (5UL) /*!< DONIE5 (Bit 5) */
+#define ADC2_DIER_DONIE5_Msk (0x20UL) /*!< DONIE5 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE4_Pos (4UL) /*!< DONIE4 (Bit 4) */
+#define ADC2_DIER_DONIE4_Msk (0x10UL) /*!< DONIE4 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE3_Pos (3UL) /*!< DONIE3 (Bit 3) */
+#define ADC2_DIER_DONIE3_Msk (0x8UL) /*!< DONIE3 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE2_Pos (2UL) /*!< DONIE2 (Bit 2) */
+#define ADC2_DIER_DONIE2_Msk (0x4UL) /*!< DONIE2 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE1_Pos (1UL) /*!< DONIE1 (Bit 1) */
+#define ADC2_DIER_DONIE1_Msk (0x2UL) /*!< DONIE1 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE0_Pos (0UL) /*!< DONIE0 (Bit 0) */
+#define ADC2_DIER_DONIE0_Msk (0x1UL) /*!< DONIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= CDR0 ========================================================== */
+#define ADC2_CDR0_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR0_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR1 ========================================================== */
+#define ADC2_CDR1_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR1_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR2 ========================================================== */
+#define ADC2_CDR2_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR2_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR3 ========================================================== */
+#define ADC2_CDR3_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR3_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR4 ========================================================== */
+#define ADC2_CDR4_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR4_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR5 ========================================================== */
+#define ADC2_CDR5_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR5_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR6 ========================================================== */
+#define ADC2_CDR6_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR6_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR7 ========================================================== */
+#define ADC2_CDR7_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR7_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR8 ========================================================== */
+#define ADC2_CDR8_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR8_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR9 ========================================================== */
+#define ADC2_CDR9_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR9_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR10 ========================================================= */
+#define ADC2_CDR10_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR10_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR11 ========================================================= */
+#define ADC2_CDR11_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR11_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR12 ========================================================= */
+#define ADC2_CDR12_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR12_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR13 ========================================================= */
+#define ADC2_CDR13_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR13_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR14 ========================================================= */
+#define ADC2_CDR14_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR14_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR15 ========================================================= */
+#define ADC2_CDR15_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR15_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR16 ========================================================= */
+#define ADC2_CDR16_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR16_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR17 ========================================================= */
+#define ADC2_CDR17_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR17_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR18 ========================================================= */
+#define ADC2_CDR18_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR18_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR19 ========================================================= */
+#define ADC2_CDR19_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR19_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= HISR ========================================================== */
+#define ADC2_HISR_HLF19_Pos (19UL) /*!< HLF19 (Bit 19) */
+#define ADC2_HISR_HLF19_Msk (0x80000UL) /*!< HLF19 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF18_Pos (18UL) /*!< HLF18 (Bit 18) */
+#define ADC2_HISR_HLF18_Msk (0x40000UL) /*!< HLF18 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF17_Pos (17UL) /*!< HLF17 (Bit 17) */
+#define ADC2_HISR_HLF17_Msk (0x20000UL) /*!< HLF17 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF16_Pos (16UL) /*!< HLF16 (Bit 16) */
+#define ADC2_HISR_HLF16_Msk (0x10000UL) /*!< HLF16 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF15_Pos (15UL) /*!< HLF15 (Bit 15) */
+#define ADC2_HISR_HLF15_Msk (0x8000UL) /*!< HLF15 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF14_Pos (14UL) /*!< HLF14 (Bit 14) */
+#define ADC2_HISR_HLF14_Msk (0x4000UL) /*!< HLF14 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF13_Pos (13UL) /*!< HLF13 (Bit 13) */
+#define ADC2_HISR_HLF13_Msk (0x2000UL) /*!< HLF13 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF12_Pos (12UL) /*!< HLF12 (Bit 12) */
+#define ADC2_HISR_HLF12_Msk (0x1000UL) /*!< HLF12 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF11_Pos (11UL) /*!< HLF11 (Bit 11) */
+#define ADC2_HISR_HLF11_Msk (0x800UL) /*!< HLF11 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF10_Pos (10UL) /*!< HLF10 (Bit 10) */
+#define ADC2_HISR_HLF10_Msk (0x400UL) /*!< HLF10 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF9_Pos (9UL) /*!< HLF9 (Bit 9) */
+#define ADC2_HISR_HLF9_Msk (0x200UL) /*!< HLF9 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF8_Pos (8UL) /*!< HLF8 (Bit 8) */
+#define ADC2_HISR_HLF8_Msk (0x100UL) /*!< HLF8 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF7_Pos (7UL) /*!< HLF7 (Bit 7) */
+#define ADC2_HISR_HLF7_Msk (0x80UL) /*!< HLF7 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF6_Pos (6UL) /*!< HLF6 (Bit 6) */
+#define ADC2_HISR_HLF6_Msk (0x40UL) /*!< HLF6 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF5_Pos (5UL) /*!< HLF5 (Bit 5) */
+#define ADC2_HISR_HLF5_Msk (0x20UL) /*!< HLF5 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF4_Pos (4UL) /*!< HLF4 (Bit 4) */
+#define ADC2_HISR_HLF4_Msk (0x10UL) /*!< HLF4 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF3_Pos (3UL) /*!< HLF3 (Bit 3) */
+#define ADC2_HISR_HLF3_Msk (0x8UL) /*!< HLF3 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF2_Pos (2UL) /*!< HLF2 (Bit 2) */
+#define ADC2_HISR_HLF2_Msk (0x4UL) /*!< HLF2 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF1_Pos (1UL) /*!< HLF1 (Bit 1) */
+#define ADC2_HISR_HLF1_Msk (0x2UL) /*!< HLF1 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF0_Pos (0UL) /*!< HLF0 (Bit 0) */
+#define ADC2_HISR_HLF0_Msk (0x1UL) /*!< HLF0 (Bitfield-Mask: 0x01) */
+/* ========================================================= HIER ========================================================== */
+#define ADC2_HIER_HLFIE19_Pos (19UL) /*!< HLFIE19 (Bit 19) */
+#define ADC2_HIER_HLFIE19_Msk (0x80000UL) /*!< HLFIE19 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE18_Pos (18UL) /*!< HLFIE18 (Bit 18) */
+#define ADC2_HIER_HLFIE18_Msk (0x40000UL) /*!< HLFIE18 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE17_Pos (17UL) /*!< HLFIE17 (Bit 17) */
+#define ADC2_HIER_HLFIE17_Msk (0x20000UL) /*!< HLFIE17 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE16_Pos (16UL) /*!< HLFIE16 (Bit 16) */
+#define ADC2_HIER_HLFIE16_Msk (0x10000UL) /*!< HLFIE16 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE15_Pos (15UL) /*!< HLFIE15 (Bit 15) */
+#define ADC2_HIER_HLFIE15_Msk (0x8000UL) /*!< HLFIE15 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE14_Pos (14UL) /*!< HLFIE14 (Bit 14) */
+#define ADC2_HIER_HLFIE14_Msk (0x4000UL) /*!< HLFIE14 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE13_Pos (13UL) /*!< HLFIE13 (Bit 13) */
+#define ADC2_HIER_HLFIE13_Msk (0x2000UL) /*!< HLFIE13 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE12_Pos (12UL) /*!< HLFIE12 (Bit 12) */
+#define ADC2_HIER_HLFIE12_Msk (0x1000UL) /*!< HLFIE12 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE11_Pos (11UL) /*!< HLFIE11 (Bit 11) */
+#define ADC2_HIER_HLFIE11_Msk (0x800UL) /*!< HLFIE11 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE10_Pos (10UL) /*!< HLFIE10 (Bit 10) */
+#define ADC2_HIER_HLFIE10_Msk (0x400UL) /*!< HLFIE10 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE9_Pos (9UL) /*!< HLFIE9 (Bit 9) */
+#define ADC2_HIER_HLFIE9_Msk (0x200UL) /*!< HLFIE9 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE8_Pos (8UL) /*!< HLFIE8 (Bit 8) */
+#define ADC2_HIER_HLFIE8_Msk (0x100UL) /*!< HLFIE8 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE7_Pos (7UL) /*!< HLFIE7 (Bit 7) */
+#define ADC2_HIER_HLFIE7_Msk (0x80UL) /*!< HLFIE7 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE6_Pos (6UL) /*!< HLFIE6 (Bit 6) */
+#define ADC2_HIER_HLFIE6_Msk (0x40UL) /*!< HLFIE6 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE5_Pos (5UL) /*!< HLFIE5 (Bit 5) */
+#define ADC2_HIER_HLFIE5_Msk (0x20UL) /*!< HLFIE5 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE4_Pos (4UL) /*!< HLFIE4 (Bit 4) */
+#define ADC2_HIER_HLFIE4_Msk (0x10UL) /*!< HLFIE4 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE3_Pos (3UL) /*!< HLFIE3 (Bit 3) */
+#define ADC2_HIER_HLFIE3_Msk (0x8UL) /*!< HLFIE3 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE2_Pos (2UL) /*!< HLFIE2 (Bit 2) */
+#define ADC2_HIER_HLFIE2_Msk (0x4UL) /*!< HLFIE2 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE1_Pos (1UL) /*!< HLFIE1 (Bit 1) */
+#define ADC2_HIER_HLFIE1_Msk (0x2UL) /*!< HLFIE1 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE0_Pos (0UL) /*!< HLFIE0 (Bit 0) */
+#define ADC2_HIER_HLFIE0_Msk (0x1UL) /*!< HLFIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FISR ========================================================== */
+#define ADC2_FISR_FUL19_Pos (19UL) /*!< FUL19 (Bit 19) */
+#define ADC2_FISR_FUL19_Msk (0x80000UL) /*!< FUL19 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL18_Pos (18UL) /*!< FUL18 (Bit 18) */
+#define ADC2_FISR_FUL18_Msk (0x40000UL) /*!< FUL18 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL17_Pos (17UL) /*!< FUL17 (Bit 17) */
+#define ADC2_FISR_FUL17_Msk (0x20000UL) /*!< FUL17 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL16_Pos (16UL) /*!< FUL16 (Bit 16) */
+#define ADC2_FISR_FUL16_Msk (0x10000UL) /*!< FUL16 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL15_Pos (15UL) /*!< FUL15 (Bit 15) */
+#define ADC2_FISR_FUL15_Msk (0x8000UL) /*!< FUL15 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL14_Pos (14UL) /*!< FUL14 (Bit 14) */
+#define ADC2_FISR_FUL14_Msk (0x4000UL) /*!< FUL14 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL13_Pos (13UL) /*!< FUL13 (Bit 13) */
+#define ADC2_FISR_FUL13_Msk (0x2000UL) /*!< FUL13 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL12_Pos (12UL) /*!< FUL12 (Bit 12) */
+#define ADC2_FISR_FUL12_Msk (0x1000UL) /*!< FUL12 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL11_Pos (11UL) /*!< FUL11 (Bit 11) */
+#define ADC2_FISR_FUL11_Msk (0x800UL) /*!< FUL11 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL10_Pos (10UL) /*!< FUL10 (Bit 10) */
+#define ADC2_FISR_FUL10_Msk (0x400UL) /*!< FUL10 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL9_Pos (9UL) /*!< FUL9 (Bit 9) */
+#define ADC2_FISR_FUL9_Msk (0x200UL) /*!< FUL9 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL8_Pos (8UL) /*!< FUL8 (Bit 8) */
+#define ADC2_FISR_FUL8_Msk (0x100UL) /*!< FUL8 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL7_Pos (7UL) /*!< FUL7 (Bit 7) */
+#define ADC2_FISR_FUL7_Msk (0x80UL) /*!< FUL7 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL6_Pos (6UL) /*!< FUL6 (Bit 6) */
+#define ADC2_FISR_FUL6_Msk (0x40UL) /*!< FUL6 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL5_Pos (5UL) /*!< FUL5 (Bit 5) */
+#define ADC2_FISR_FUL5_Msk (0x20UL) /*!< FUL5 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL4_Pos (4UL) /*!< FUL4 (Bit 4) */
+#define ADC2_FISR_FUL4_Msk (0x10UL) /*!< FUL4 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL3_Pos (3UL) /*!< FUL3 (Bit 3) */
+#define ADC2_FISR_FUL3_Msk (0x8UL) /*!< FUL3 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL2_Pos (2UL) /*!< FUL2 (Bit 2) */
+#define ADC2_FISR_FUL2_Msk (0x4UL) /*!< FUL2 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL1_Pos (1UL) /*!< FUL1 (Bit 1) */
+#define ADC2_FISR_FUL1_Msk (0x2UL) /*!< FUL1 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL0_Pos (0UL) /*!< FUL0 (Bit 0) */
+#define ADC2_FISR_FUL0_Msk (0x1UL) /*!< FUL0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FIER ========================================================== */
+#define ADC2_FIER_FULIE19_Pos (19UL) /*!< FULIE19 (Bit 19) */
+#define ADC2_FIER_FULIE19_Msk (0x80000UL) /*!< FULIE19 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE18_Pos (18UL) /*!< FULIE18 (Bit 18) */
+#define ADC2_FIER_FULIE18_Msk (0x40000UL) /*!< FULIE18 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE17_Pos (17UL) /*!< FULIE17 (Bit 17) */
+#define ADC2_FIER_FULIE17_Msk (0x20000UL) /*!< FULIE17 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE16_Pos (16UL) /*!< FULIE16 (Bit 16) */
+#define ADC2_FIER_FULIE16_Msk (0x10000UL) /*!< FULIE16 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE15_Pos (15UL) /*!< FULIE15 (Bit 15) */
+#define ADC2_FIER_FULIE15_Msk (0x8000UL) /*!< FULIE15 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE14_Pos (14UL) /*!< FULIE14 (Bit 14) */
+#define ADC2_FIER_FULIE14_Msk (0x4000UL) /*!< FULIE14 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE13_Pos (13UL) /*!< FULIE13 (Bit 13) */
+#define ADC2_FIER_FULIE13_Msk (0x2000UL) /*!< FULIE13 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE12_Pos (12UL) /*!< FULIE12 (Bit 12) */
+#define ADC2_FIER_FULIE12_Msk (0x1000UL) /*!< FULIE12 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE11_Pos (11UL) /*!< FULIE11 (Bit 11) */
+#define ADC2_FIER_FULIE11_Msk (0x800UL) /*!< FULIE11 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE10_Pos (10UL) /*!< FULIE10 (Bit 10) */
+#define ADC2_FIER_FULIE10_Msk (0x400UL) /*!< FULIE10 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE9_Pos (9UL) /*!< FULIE9 (Bit 9) */
+#define ADC2_FIER_FULIE9_Msk (0x200UL) /*!< FULIE9 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE8_Pos (8UL) /*!< FULIE8 (Bit 8) */
+#define ADC2_FIER_FULIE8_Msk (0x100UL) /*!< FULIE8 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE7_Pos (7UL) /*!< FULIE7 (Bit 7) */
+#define ADC2_FIER_FULIE7_Msk (0x80UL) /*!< FULIE7 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE6_Pos (6UL) /*!< FULIE6 (Bit 6) */
+#define ADC2_FIER_FULIE6_Msk (0x40UL) /*!< FULIE6 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE5_Pos (5UL) /*!< FULIE5 (Bit 5) */
+#define ADC2_FIER_FULIE5_Msk (0x20UL) /*!< FULIE5 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE4_Pos (4UL) /*!< FULIE4 (Bit 4) */
+#define ADC2_FIER_FULIE4_Msk (0x10UL) /*!< FULIE4 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE3_Pos (3UL) /*!< FULIE3 (Bit 3) */
+#define ADC2_FIER_FULIE3_Msk (0x8UL) /*!< FULIE3 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE2_Pos (2UL) /*!< FULIE2 (Bit 2) */
+#define ADC2_FIER_FULIE2_Msk (0x4UL) /*!< FULIE2 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE1_Pos (1UL) /*!< FULIE1 (Bit 1) */
+#define ADC2_FIER_FULIE1_Msk (0x2UL) /*!< FULIE1 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE0_Pos (0UL) /*!< FULIE0 (Bit 0) */
+#define ADC2_FIER_FULIE0_Msk (0x1UL) /*!< FULIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= TCR0 ========================================================== */
+#define ADC2_TCR0_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR0_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR0_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR0_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR0_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR0_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR0_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR0 ========================================================== */
+#define ADC2_TAR0_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR0_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR0 ========================================================== */
+#define ADC2_TLR0_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR0_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR1 ========================================================== */
+#define ADC2_TCR1_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR1_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR1_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR1_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR1_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR1_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR1_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR1 ========================================================== */
+#define ADC2_TAR1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR1_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR1 ========================================================== */
+#define ADC2_TLR1_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR1_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR2 ========================================================== */
+#define ADC2_TCR2_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR2_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR2_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR2_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR2_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR2_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR2_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR2 ========================================================== */
+#define ADC2_TAR2_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR2_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR2 ========================================================== */
+#define ADC2_TLR2_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR2_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR3 ========================================================== */
+#define ADC2_TCR3_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR3_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR3_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR3_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR3_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR3_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR3_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR3 ========================================================== */
+#define ADC2_TAR3_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR3_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR3 ========================================================== */
+#define ADC2_TLR3_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR3_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR4 ========================================================== */
+#define ADC2_TCR4_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR4_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR4_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR4_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR4_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR4_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR4_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR4_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR4 ========================================================== */
+#define ADC2_TAR4_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR4_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR4 ========================================================== */
+#define ADC2_TLR4_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR4_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR5 ========================================================== */
+#define ADC2_TCR5_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR5_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR5_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR5_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR5_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR5_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR5_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR5_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR5 ========================================================== */
+#define ADC2_TAR5_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR5_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR5 ========================================================== */
+#define ADC2_TLR5_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR5_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR6 ========================================================== */
+#define ADC2_TCR6_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR6_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR6_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR6_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR6_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR6_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR6_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR6_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR6 ========================================================== */
+#define ADC2_TAR6_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR6_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR6 ========================================================== */
+#define ADC2_TLR6_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR6_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR7 ========================================================== */
+#define ADC2_TCR7_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR7_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR7_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR7_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR7_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR7_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR7_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR7_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR7 ========================================================== */
+#define ADC2_TAR7_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR7_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR7 ========================================================== */
+#define ADC2_TLR7_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR7_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR8 ========================================================== */
+#define ADC2_TCR8_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR8_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR8_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR8_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR8_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR8_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR8_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR8_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR8 ========================================================== */
+#define ADC2_TAR8_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR8_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR8 ========================================================== */
+#define ADC2_TLR8_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR8_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR9 ========================================================== */
+#define ADC2_TCR9_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR9_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR9_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR9_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR9_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR9_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR9_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR9_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR9 ========================================================== */
+#define ADC2_TAR9_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR9_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR9 ========================================================== */
+#define ADC2_TLR9_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR9_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR10 ========================================================= */
+#define ADC2_TCR10_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR10_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR10_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR10_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR10_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR10_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR10_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR10_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR10 ========================================================= */
+#define ADC2_TAR10_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR10_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR10 ========================================================= */
+#define ADC2_TLR10_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR10_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR11 ========================================================= */
+#define ADC2_TCR11_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR11_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR11_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR11_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR11_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR11_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR11_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR11_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR11 ========================================================= */
+#define ADC2_TAR11_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR11_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR11 ========================================================= */
+#define ADC2_TLR11_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR11_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR12 ========================================================= */
+#define ADC2_TCR12_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR12_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR12_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR12_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR12_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR12_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR12_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR12_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR12 ========================================================= */
+#define ADC2_TAR12_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR12_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR12 ========================================================= */
+#define ADC2_TLR12_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR12_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR13 ========================================================= */
+#define ADC2_TCR13_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR13_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR13_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR13_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR13_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR13_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR13_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR13_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR13 ========================================================= */
+#define ADC2_TAR13_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR13_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR13 ========================================================= */
+#define ADC2_TLR13_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR13_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR14 ========================================================= */
+#define ADC2_TCR14_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR14_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR14_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR14_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR14_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR14_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR14_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR14_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR14 ========================================================= */
+#define ADC2_TAR14_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR14_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR14 ========================================================= */
+#define ADC2_TLR14_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR14_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR15 ========================================================= */
+#define ADC2_TCR15_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR15_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR15_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR15_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR15_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR15_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR15_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR15_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR15 ========================================================= */
+#define ADC2_TAR15_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR15_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR15 ========================================================= */
+#define ADC2_TLR15_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR15_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR16 ========================================================= */
+#define ADC2_TCR16_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR16_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR16_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR16_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR16_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR16_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR16_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR16_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR16 ========================================================= */
+#define ADC2_TAR16_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR16_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR16 ========================================================= */
+#define ADC2_TLR16_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR16_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR17 ========================================================= */
+#define ADC2_TCR17_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR17_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR17_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR17_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR17_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR17_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR17_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR17_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR17 ========================================================= */
+#define ADC2_TAR17_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR17_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR17 ========================================================= */
+#define ADC2_TLR17_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR17_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR18 ========================================================= */
+#define ADC2_TCR18_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR18_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR18_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR18_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR18_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR18_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR18_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR18_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR18 ========================================================= */
+#define ADC2_TAR18_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR18_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR18 ========================================================= */
+#define ADC2_TLR18_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR18_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR19 ========================================================= */
+#define ADC2_TCR19_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR19_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR19_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR19_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR19_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR19_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR19_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR19_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR19 ========================================================= */
+#define ADC2_TAR19_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR19_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR19 ========================================================= */
+#define ADC2_TLR19_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR19_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================== CCR ========================================================== */
+#define ADC2_CCR_DELAY_Pos (8UL) /*!< DELAY (Bit 8) */
+#define ADC2_CCR_DELAY_Msk (0x3ff00UL) /*!< DELAY (Bitfield-Mask: 0x3ff) */
+#define ADC2_CCR_DUAL_Pos (0UL) /*!< DUAL (Bit 0) */
+#define ADC2_CCR_DUAL_Msk (0xfUL) /*!< DUAL (Bitfield-Mask: 0x0f) */
+/* ========================================================== CSR ========================================================== */
+#define ADC2_CSR_EOSMP_SLV_Pos (25UL) /*!< EOSMP_SLV (Bit 25) */
+#define ADC2_CSR_EOSMP_SLV_Msk (0x2000000UL) /*!< EOSMP_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_ADRDY_SLV_Pos (24UL) /*!< ADRDY_SLV (Bit 24) */
+#define ADC2_CSR_ADRDY_SLV_Msk (0x1000000UL) /*!< ADRDY_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD2_SLV_Pos (23UL) /*!< AWD2_SLV (Bit 23) */
+#define ADC2_CSR_AWD2_SLV_Msk (0x800000UL) /*!< AWD2_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD1_SLV_Pos (22UL) /*!< AWD1_SLV (Bit 22) */
+#define ADC2_CSR_AWD1_SLV_Msk (0x400000UL) /*!< AWD1_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD0_SLV_Pos (21UL) /*!< AWD0_SLV (Bit 21) */
+#define ADC2_CSR_AWD0_SLV_Msk (0x200000UL) /*!< AWD0_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_OVR_SLV_Pos (20UL) /*!< OVR_SLV (Bit 20) */
+#define ADC2_CSR_OVR_SLV_Msk (0x100000UL) /*!< OVR_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_JEOS_SLV_Pos (19UL) /*!< JEOS_SLV (Bit 19) */
+#define ADC2_CSR_JEOS_SLV_Msk (0x80000UL) /*!< JEOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_JEOC_SLV_Pos (18UL) /*!< JEOC_SLV (Bit 18) */
+#define ADC2_CSR_JEOC_SLV_Msk (0x40000UL) /*!< JEOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_EOS_SLV_Pos (17UL) /*!< EOS_SLV (Bit 17) */
+#define ADC2_CSR_EOS_SLV_Msk (0x20000UL) /*!< EOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_EOC_SLV_Pos (16UL) /*!< EOC_SLV (Bit 16) */
+#define ADC2_CSR_EOC_SLV_Msk (0x10000UL) /*!< EOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_EOSMP_MST_Pos (9UL) /*!< EOSMP_MST (Bit 9) */
+#define ADC2_CSR_EOSMP_MST_Msk (0x200UL) /*!< EOSMP_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_ADRDY_MST_Pos (8UL) /*!< ADRDY_MST (Bit 8) */
+#define ADC2_CSR_ADRDY_MST_Msk (0x100UL) /*!< ADRDY_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD2_MST_Pos (7UL) /*!< AWD2_MST (Bit 7) */
+#define ADC2_CSR_AWD2_MST_Msk (0x80UL) /*!< AWD2_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD1_MST_Pos (6UL) /*!< AWD1_MST (Bit 6) */
+#define ADC2_CSR_AWD1_MST_Msk (0x40UL) /*!< AWD1_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD0_MST_Pos (5UL) /*!< AWD0_MST (Bit 5) */
+#define ADC2_CSR_AWD0_MST_Msk (0x20UL) /*!< AWD0_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_OVR_MST_Pos (4UL) /*!< OVR_MST (Bit 4) */
+#define ADC2_CSR_OVR_MST_Msk (0x10UL) /*!< OVR_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_JEOS_MST_Pos (3UL) /*!< JEOS_MST (Bit 3) */
+#define ADC2_CSR_JEOS_MST_Msk (0x8UL) /*!< JEOS_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_JEOC_MST_Pos (2UL) /*!< JEOC_MST (Bit 2) */
+#define ADC2_CSR_JEOC_MST_Msk (0x4UL) /*!< JEOC_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_EOS_MST_Pos (1UL) /*!< EOS_MST (Bit 1) */
+#define ADC2_CSR_EOS_MST_Msk (0x2UL) /*!< EOS_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_EOC_MST_Pos (0UL) /*!< EOC_MST (Bit 0) */
+#define ADC2_CSR_EOC_MST_Msk (0x1UL) /*!< EOC_MST (Bitfield-Mask: 0x01) */
+/* ========================================================== CDR ========================================================== */
+#define ADC2_CDR_RDATA_SLV_Pos (16UL) /*!< RDATA_SLV (Bit 16) */
+#define ADC2_CDR_RDATA_SLV_Msk (0xffff0000UL) /*!< RDATA_SLV (Bitfield-Mask: 0xffff) */
+#define ADC2_CDR_RDATA_MST_Pos (0UL) /*!< RDATA_MST (Bit 0) */
+#define ADC2_CDR_RDATA_MST_Msk (0xffffUL) /*!< RDATA_MST (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ ADC3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define ADC3_CR_ADCALDIF_Pos (7UL) /*!< ADCALDIF (Bit 7) */
+#define ADC3_CR_ADCALDIF_Msk (0x80UL) /*!< ADCALDIF (Bitfield-Mask: 0x01) */
+#define ADC3_CR_ADCAL_Pos (6UL) /*!< ADCAL (Bit 6) */
+#define ADC3_CR_ADCAL_Msk (0x40UL) /*!< ADCAL (Bitfield-Mask: 0x01) */
+#define ADC3_CR_JADSTP_Pos (5UL) /*!< JADSTP (Bit 5) */
+#define ADC3_CR_JADSTP_Msk (0x20UL) /*!< JADSTP (Bitfield-Mask: 0x01) */
+#define ADC3_CR_ADSTP_Pos (4UL) /*!< ADSTP (Bit 4) */
+#define ADC3_CR_ADSTP_Msk (0x10UL) /*!< ADSTP (Bitfield-Mask: 0x01) */
+#define ADC3_CR_JADSTART_Pos (3UL) /*!< JADSTART (Bit 3) */
+#define ADC3_CR_JADSTART_Msk (0x8UL) /*!< JADSTART (Bitfield-Mask: 0x01) */
+#define ADC3_CR_ADSTART_Pos (2UL) /*!< ADSTART (Bit 2) */
+#define ADC3_CR_ADSTART_Msk (0x4UL) /*!< ADSTART (Bitfield-Mask: 0x01) */
+#define ADC3_CR_ADDIS_Pos (1UL) /*!< ADDIS (Bit 1) */
+#define ADC3_CR_ADDIS_Msk (0x2UL) /*!< ADDIS (Bitfield-Mask: 0x01) */
+#define ADC3_CR_ADEN_Pos (0UL) /*!< ADEN (Bit 0) */
+#define ADC3_CR_ADEN_Msk (0x1UL) /*!< ADEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR0 ========================================================= */
+#define ADC3_CFGR0_OVSCAL_Pos (28UL) /*!< OVSCAL (Bit 28) */
+#define ADC3_CFGR0_OVSCAL_Msk (0x70000000UL) /*!< OVSCAL (Bitfield-Mask: 0x07) */
+#define ADC3_CFGR0_CONT_Pos (23UL) /*!< CONT (Bit 23) */
+#define ADC3_CFGR0_CONT_Msk (0x800000UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_JAUTO_Pos (22UL) /*!< JAUTO (Bit 22) */
+#define ADC3_CFGR0_JAUTO_Msk (0x400000UL) /*!< JAUTO (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_JDISCEN_Pos (20UL) /*!< JDISCEN (Bit 20) */
+#define ADC3_CFGR0_JDISCEN_Msk (0x100000UL) /*!< JDISCEN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_DISCNUM_Pos (17UL) /*!< DISCNUM (Bit 17) */
+#define ADC3_CFGR0_DISCNUM_Msk (0xe0000UL) /*!< DISCNUM (Bitfield-Mask: 0x07) */
+#define ADC3_CFGR0_DISCEN_Pos (16UL) /*!< DISCEN (Bit 16) */
+#define ADC3_CFGR0_DISCEN_Msk (0x10000UL) /*!< DISCEN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_OVRMOD_Pos (15UL) /*!< OVRMOD (Bit 15) */
+#define ADC3_CFGR0_OVRMOD_Msk (0x8000UL) /*!< OVRMOD (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_SDMAEN_Pos (14UL) /*!< SDMAEN (Bit 14) */
+#define ADC3_CFGR0_SDMAEN_Msk (0x4000UL) /*!< SDMAEN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_TROVS_Pos (12UL) /*!< TROVS (Bit 12) */
+#define ADC3_CFGR0_TROVS_Msk (0x1000UL) /*!< TROVS (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_OVSS_Pos (8UL) /*!< OVSS (Bit 8) */
+#define ADC3_CFGR0_OVSS_Msk (0xf00UL) /*!< OVSS (Bitfield-Mask: 0x0f) */
+#define ADC3_CFGR0_ROVSM_Pos (7UL) /*!< ROVSM (Bit 7) */
+#define ADC3_CFGR0_ROVSM_Msk (0x80UL) /*!< ROVSM (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_OVSR_Pos (4UL) /*!< OVSR (Bit 4) */
+#define ADC3_CFGR0_OVSR_Msk (0x70UL) /*!< OVSR (Bitfield-Mask: 0x07) */
+#define ADC3_CFGR0_JOVSE_Pos (1UL) /*!< JOVSE (Bit 1) */
+#define ADC3_CFGR0_JOVSE_Msk (0x2UL) /*!< JOVSE (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_ROVSE_Pos (0UL) /*!< ROVSE (Bit 0) */
+#define ADC3_CFGR0_ROVSE_Msk (0x1UL) /*!< ROVSE (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR1 ========================================================= */
+#define ADC3_CFGR1_JAWD2EN_Pos (14UL) /*!< JAWD2EN (Bit 14) */
+#define ADC3_CFGR1_JAWD2EN_Msk (0x4000UL) /*!< JAWD2EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_JAWD1EN_Pos (13UL) /*!< JAWD1EN (Bit 13) */
+#define ADC3_CFGR1_JAWD1EN_Msk (0x2000UL) /*!< JAWD1EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_JAWD0EN_Pos (12UL) /*!< JAWD0EN (Bit 12) */
+#define ADC3_CFGR1_JAWD0EN_Msk (0x1000UL) /*!< JAWD0EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_AWD2EN_Pos (10UL) /*!< AWD2EN (Bit 10) */
+#define ADC3_CFGR1_AWD2EN_Msk (0x400UL) /*!< AWD2EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_AWD1EN_Pos (9UL) /*!< AWD1EN (Bit 9) */
+#define ADC3_CFGR1_AWD1EN_Msk (0x200UL) /*!< AWD1EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_AWD0EN_Pos (8UL) /*!< AWD0EN (Bit 8) */
+#define ADC3_CFGR1_AWD0EN_Msk (0x100UL) /*!< AWD0EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_ISEL_Pos (4UL) /*!< ISEL (Bit 4) */
+#define ADC3_CFGR1_ISEL_Msk (0x30UL) /*!< ISEL (Bitfield-Mask: 0x03) */
+#define ADC3_CFGR1_CHEN_Pos (3UL) /*!< CHEN (Bit 3) */
+#define ADC3_CFGR1_CHEN_Msk (0x8UL) /*!< CHEN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_REFEN_Pos (1UL) /*!< REFEN (Bit 1) */
+#define ADC3_CFGR1_REFEN_Msk (0x2UL) /*!< REFEN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_BIASEN_Pos (0UL) /*!< BIASEN (Bit 0) */
+#define ADC3_CFGR1_BIASEN_Msk (0x1UL) /*!< BIASEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define ADC3_ISR_EOSMP_Pos (9UL) /*!< EOSMP (Bit 9) */
+#define ADC3_ISR_EOSMP_Msk (0x200UL) /*!< EOSMP (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_ADRDY_Pos (8UL) /*!< ADRDY (Bit 8) */
+#define ADC3_ISR_ADRDY_Msk (0x100UL) /*!< ADRDY (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_AWD2_Pos (7UL) /*!< AWD2 (Bit 7) */
+#define ADC3_ISR_AWD2_Msk (0x80UL) /*!< AWD2 (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_AWD1_Pos (6UL) /*!< AWD1 (Bit 6) */
+#define ADC3_ISR_AWD1_Msk (0x40UL) /*!< AWD1 (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_AWD0_Pos (5UL) /*!< AWD0 (Bit 5) */
+#define ADC3_ISR_AWD0_Msk (0x20UL) /*!< AWD0 (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_OVR_Pos (4UL) /*!< OVR (Bit 4) */
+#define ADC3_ISR_OVR_Msk (0x10UL) /*!< OVR (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_JEOS_Pos (3UL) /*!< JEOS (Bit 3) */
+#define ADC3_ISR_JEOS_Msk (0x8UL) /*!< JEOS (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_JEOC_Pos (2UL) /*!< JEOC (Bit 2) */
+#define ADC3_ISR_JEOC_Msk (0x4UL) /*!< JEOC (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */
+#define ADC3_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */
+#define ADC3_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define ADC3_IER_EOSMPIE_Pos (9UL) /*!< EOSMPIE (Bit 9) */
+#define ADC3_IER_EOSMPIE_Msk (0x200UL) /*!< EOSMPIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_ADRDYIE_Pos (8UL) /*!< ADRDYIE (Bit 8) */
+#define ADC3_IER_ADRDYIE_Msk (0x100UL) /*!< ADRDYIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_AWD2IE_Pos (7UL) /*!< AWD2IE (Bit 7) */
+#define ADC3_IER_AWD2IE_Msk (0x80UL) /*!< AWD2IE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_AWD1IE_Pos (6UL) /*!< AWD1IE (Bit 6) */
+#define ADC3_IER_AWD1IE_Msk (0x40UL) /*!< AWD1IE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_AWD0IE_Pos (5UL) /*!< AWD0IE (Bit 5) */
+#define ADC3_IER_AWD0IE_Msk (0x20UL) /*!< AWD0IE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_OVRIE_Pos (4UL) /*!< OVRIE (Bit 4) */
+#define ADC3_IER_OVRIE_Msk (0x10UL) /*!< OVRIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_JEOSIE_Pos (3UL) /*!< JEOSIE (Bit 3) */
+#define ADC3_IER_JEOSIE_Msk (0x8UL) /*!< JEOSIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_JEOCIE_Pos (2UL) /*!< JEOCIE (Bit 2) */
+#define ADC3_IER_JEOCIE_Msk (0x4UL) /*!< JEOCIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_EOSIE_Pos (1UL) /*!< EOSIE (Bit 1) */
+#define ADC3_IER_EOSIE_Msk (0x2UL) /*!< EOSIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_EOCIE_Pos (0UL) /*!< EOCIE (Bit 0) */
+#define ADC3_IER_EOCIE_Msk (0x1UL) /*!< EOCIE (Bitfield-Mask: 0x01) */
+/* ======================================================== SIGSEL ========================================================= */
+#define ADC3_SIGSEL_SIGSEL_Pos (0UL) /*!< SIGSEL (Bit 0) */
+#define ADC3_SIGSEL_SIGSEL_Msk (0xfffffUL) /*!< SIGSEL (Bitfield-Mask: 0xfffff) */
+/* ========================================================= SMPR0 ========================================================= */
+#define ADC3_SMPR0_SMP7_Pos (28UL) /*!< SMP7 (Bit 28) */
+#define ADC3_SMPR0_SMP7_Msk (0x70000000UL) /*!< SMP7 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP6_Pos (24UL) /*!< SMP6 (Bit 24) */
+#define ADC3_SMPR0_SMP6_Msk (0x7000000UL) /*!< SMP6 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP5_Pos (20UL) /*!< SMP5 (Bit 20) */
+#define ADC3_SMPR0_SMP5_Msk (0x700000UL) /*!< SMP5 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP4_Pos (16UL) /*!< SMP4 (Bit 16) */
+#define ADC3_SMPR0_SMP4_Msk (0x70000UL) /*!< SMP4 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP3_Pos (12UL) /*!< SMP3 (Bit 12) */
+#define ADC3_SMPR0_SMP3_Msk (0x7000UL) /*!< SMP3 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP2_Pos (8UL) /*!< SMP2 (Bit 8) */
+#define ADC3_SMPR0_SMP2_Msk (0x700UL) /*!< SMP2 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP1_Pos (4UL) /*!< SMP1 (Bit 4) */
+#define ADC3_SMPR0_SMP1_Msk (0x70UL) /*!< SMP1 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP0_Pos (0UL) /*!< SMP0 (Bit 0) */
+#define ADC3_SMPR0_SMP0_Msk (0x7UL) /*!< SMP0 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR1 ========================================================= */
+#define ADC3_SMPR1_SMP15_Pos (28UL) /*!< SMP15 (Bit 28) */
+#define ADC3_SMPR1_SMP15_Msk (0x70000000UL) /*!< SMP15 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP14_Pos (24UL) /*!< SMP14 (Bit 24) */
+#define ADC3_SMPR1_SMP14_Msk (0x7000000UL) /*!< SMP14 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP13_Pos (20UL) /*!< SMP13 (Bit 20) */
+#define ADC3_SMPR1_SMP13_Msk (0x700000UL) /*!< SMP13 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP12_Pos (16UL) /*!< SMP12 (Bit 16) */
+#define ADC3_SMPR1_SMP12_Msk (0x70000UL) /*!< SMP12 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP11_Pos (12UL) /*!< SMP11 (Bit 12) */
+#define ADC3_SMPR1_SMP11_Msk (0x7000UL) /*!< SMP11 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP10_Pos (8UL) /*!< SMP10 (Bit 8) */
+#define ADC3_SMPR1_SMP10_Msk (0x700UL) /*!< SMP10 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP9_Pos (4UL) /*!< SMP9 (Bit 4) */
+#define ADC3_SMPR1_SMP9_Msk (0x70UL) /*!< SMP9 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP8_Pos (0UL) /*!< SMP8 (Bit 0) */
+#define ADC3_SMPR1_SMP8_Msk (0x7UL) /*!< SMP8 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR2 ========================================================= */
+#define ADC3_SMPR2_SMP19_Pos (12UL) /*!< SMP19 (Bit 12) */
+#define ADC3_SMPR2_SMP19_Msk (0x7000UL) /*!< SMP19 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR2_SMP18_Pos (8UL) /*!< SMP18 (Bit 8) */
+#define ADC3_SMPR2_SMP18_Msk (0x700UL) /*!< SMP18 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR2_SMP17_Pos (4UL) /*!< SMP17 (Bit 4) */
+#define ADC3_SMPR2_SMP17_Msk (0x70UL) /*!< SMP17 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR2_SMP16_Pos (0UL) /*!< SMP16 (Bit 0) */
+#define ADC3_SMPR2_SMP16_Msk (0x7UL) /*!< SMP16 (Bitfield-Mask: 0x07) */
+/* ========================================================= CALR0 ========================================================= */
+#define ADC3_CALR0_SAT7_Pos (31UL) /*!< SAT7 (Bit 31) */
+#define ADC3_CALR0_SAT7_Msk (0x80000000UL) /*!< SAT7 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL7_Pos (28UL) /*!< CAL7 (Bit 28) */
+#define ADC3_CALR0_CAL7_Msk (0x30000000UL) /*!< CAL7 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT6_Pos (27UL) /*!< SAT6 (Bit 27) */
+#define ADC3_CALR0_SAT6_Msk (0x8000000UL) /*!< SAT6 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL6_Pos (24UL) /*!< CAL6 (Bit 24) */
+#define ADC3_CALR0_CAL6_Msk (0x3000000UL) /*!< CAL6 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT5_Pos (23UL) /*!< SAT5 (Bit 23) */
+#define ADC3_CALR0_SAT5_Msk (0x800000UL) /*!< SAT5 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL5_Pos (20UL) /*!< CAL5 (Bit 20) */
+#define ADC3_CALR0_CAL5_Msk (0x300000UL) /*!< CAL5 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT4_Pos (19UL) /*!< SAT4 (Bit 19) */
+#define ADC3_CALR0_SAT4_Msk (0x80000UL) /*!< SAT4 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL4_Pos (16UL) /*!< CAL4 (Bit 16) */
+#define ADC3_CALR0_CAL4_Msk (0x30000UL) /*!< CAL4 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT3_Pos (15UL) /*!< SAT3 (Bit 15) */
+#define ADC3_CALR0_SAT3_Msk (0x8000UL) /*!< SAT3 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL3_Pos (12UL) /*!< CAL3 (Bit 12) */
+#define ADC3_CALR0_CAL3_Msk (0x3000UL) /*!< CAL3 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT2_Pos (11UL) /*!< SAT2 (Bit 11) */
+#define ADC3_CALR0_SAT2_Msk (0x800UL) /*!< SAT2 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL2_Pos (8UL) /*!< CAL2 (Bit 8) */
+#define ADC3_CALR0_CAL2_Msk (0x300UL) /*!< CAL2 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT1_Pos (7UL) /*!< SAT1 (Bit 7) */
+#define ADC3_CALR0_SAT1_Msk (0x80UL) /*!< SAT1 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL1_Pos (4UL) /*!< CAL1 (Bit 4) */
+#define ADC3_CALR0_CAL1_Msk (0x30UL) /*!< CAL1 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT0_Pos (3UL) /*!< SAT0 (Bit 3) */
+#define ADC3_CALR0_SAT0_Msk (0x8UL) /*!< SAT0 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL0_Pos (0UL) /*!< CAL0 (Bit 0) */
+#define ADC3_CALR0_CAL0_Msk (0x3UL) /*!< CAL0 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR1 ========================================================= */
+#define ADC3_CALR1_SAT15_Pos (31UL) /*!< SAT15 (Bit 31) */
+#define ADC3_CALR1_SAT15_Msk (0x80000000UL) /*!< SAT15 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL15_Pos (28UL) /*!< CAL15 (Bit 28) */
+#define ADC3_CALR1_CAL15_Msk (0x30000000UL) /*!< CAL15 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT14_Pos (27UL) /*!< SAT14 (Bit 27) */
+#define ADC3_CALR1_SAT14_Msk (0x8000000UL) /*!< SAT14 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL14_Pos (24UL) /*!< CAL14 (Bit 24) */
+#define ADC3_CALR1_CAL14_Msk (0x3000000UL) /*!< CAL14 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT13_Pos (23UL) /*!< SAT13 (Bit 23) */
+#define ADC3_CALR1_SAT13_Msk (0x800000UL) /*!< SAT13 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL13_Pos (20UL) /*!< CAL13 (Bit 20) */
+#define ADC3_CALR1_CAL13_Msk (0x300000UL) /*!< CAL13 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT12_Pos (19UL) /*!< SAT12 (Bit 19) */
+#define ADC3_CALR1_SAT12_Msk (0x80000UL) /*!< SAT12 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL12_Pos (16UL) /*!< CAL12 (Bit 16) */
+#define ADC3_CALR1_CAL12_Msk (0x30000UL) /*!< CAL12 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT11_Pos (15UL) /*!< SAT11 (Bit 15) */
+#define ADC3_CALR1_SAT11_Msk (0x8000UL) /*!< SAT11 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL11_Pos (12UL) /*!< CAL11 (Bit 12) */
+#define ADC3_CALR1_CAL11_Msk (0x3000UL) /*!< CAL11 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT10_Pos (11UL) /*!< SAT10 (Bit 11) */
+#define ADC3_CALR1_SAT10_Msk (0x800UL) /*!< SAT10 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL10_Pos (8UL) /*!< CAL10 (Bit 8) */
+#define ADC3_CALR1_CAL10_Msk (0x300UL) /*!< CAL10 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT9_Pos (7UL) /*!< SAT9 (Bit 7) */
+#define ADC3_CALR1_SAT9_Msk (0x80UL) /*!< SAT9 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL9_Pos (4UL) /*!< CAL9 (Bit 4) */
+#define ADC3_CALR1_CAL9_Msk (0x30UL) /*!< CAL9 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT8_Pos (3UL) /*!< SAT8 (Bit 3) */
+#define ADC3_CALR1_SAT8_Msk (0x8UL) /*!< SAT8 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL8_Pos (0UL) /*!< CAL8 (Bit 0) */
+#define ADC3_CALR1_CAL8_Msk (0x3UL) /*!< CAL8 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR2 ========================================================= */
+#define ADC3_CALR2_SAT19_Pos (15UL) /*!< SAT19 (Bit 15) */
+#define ADC3_CALR2_SAT19_Msk (0x8000UL) /*!< SAT19 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR2_CAL19_Pos (12UL) /*!< CAL19 (Bit 12) */
+#define ADC3_CALR2_CAL19_Msk (0x3000UL) /*!< CAL19 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR2_SAT18_Pos (11UL) /*!< SAT18 (Bit 11) */
+#define ADC3_CALR2_SAT18_Msk (0x800UL) /*!< SAT18 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR2_CAL18_Pos (8UL) /*!< CAL18 (Bit 8) */
+#define ADC3_CALR2_CAL18_Msk (0x300UL) /*!< CAL18 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR2_SAT17_Pos (7UL) /*!< SAT17 (Bit 7) */
+#define ADC3_CALR2_SAT17_Msk (0x80UL) /*!< SAT17 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR2_CAL17_Pos (4UL) /*!< CAL17 (Bit 4) */
+#define ADC3_CALR2_CAL17_Msk (0x30UL) /*!< CAL17 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR2_SAT16_Pos (3UL) /*!< SAT16 (Bit 3) */
+#define ADC3_CALR2_SAT16_Msk (0x8UL) /*!< SAT16 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR2_CAL16_Pos (0UL) /*!< CAL16 (Bit 0) */
+#define ADC3_CALR2_CAL16_Msk (0x3UL) /*!< CAL16 (Bitfield-Mask: 0x03) */
+/* ========================================================= SQR0 ========================================================== */
+#define ADC3_SQR0_SQ5_Pos (24UL) /*!< SQ5 (Bit 24) */
+#define ADC3_SQR0_SQ5_Msk (0x1f000000UL) /*!< SQ5 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR0_SQ4_Pos (18UL) /*!< SQ4 (Bit 18) */
+#define ADC3_SQR0_SQ4_Msk (0x7c0000UL) /*!< SQ4 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR0_SQ3_Pos (12UL) /*!< SQ3 (Bit 12) */
+#define ADC3_SQR0_SQ3_Msk (0x1f000UL) /*!< SQ3 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR0_SQ2_Pos (6UL) /*!< SQ2 (Bit 6) */
+#define ADC3_SQR0_SQ2_Msk (0x7c0UL) /*!< SQ2 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR0_SQ1_Pos (0UL) /*!< SQ1 (Bit 0) */
+#define ADC3_SQR0_SQ1_Msk (0x1fUL) /*!< SQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR1 ========================================================== */
+#define ADC3_SQR1_SQ10_Pos (24UL) /*!< SQ10 (Bit 24) */
+#define ADC3_SQR1_SQ10_Msk (0x1f000000UL) /*!< SQ10 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR1_SQ9_Pos (18UL) /*!< SQ9 (Bit 18) */
+#define ADC3_SQR1_SQ9_Msk (0x7c0000UL) /*!< SQ9 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR1_SQ8_Pos (12UL) /*!< SQ8 (Bit 12) */
+#define ADC3_SQR1_SQ8_Msk (0x1f000UL) /*!< SQ8 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR1_SQ7_Pos (6UL) /*!< SQ7 (Bit 6) */
+#define ADC3_SQR1_SQ7_Msk (0x7c0UL) /*!< SQ7 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR1_SQ6_Pos (0UL) /*!< SQ6 (Bit 0) */
+#define ADC3_SQR1_SQ6_Msk (0x1fUL) /*!< SQ6 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR2 ========================================================== */
+#define ADC3_SQR2_SQ15_Pos (24UL) /*!< SQ15 (Bit 24) */
+#define ADC3_SQR2_SQ15_Msk (0x1f000000UL) /*!< SQ15 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR2_SQ14_Pos (18UL) /*!< SQ14 (Bit 18) */
+#define ADC3_SQR2_SQ14_Msk (0x7c0000UL) /*!< SQ14 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR2_SQ13_Pos (12UL) /*!< SQ13 (Bit 12) */
+#define ADC3_SQR2_SQ13_Msk (0x1f000UL) /*!< SQ13 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR2_SQ12_Pos (6UL) /*!< SQ12 (Bit 6) */
+#define ADC3_SQR2_SQ12_Msk (0x7c0UL) /*!< SQ12 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR2_SQ11_Pos (0UL) /*!< SQ11 (Bit 0) */
+#define ADC3_SQR2_SQ11_Msk (0x1fUL) /*!< SQ11 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR3 ========================================================== */
+#define ADC3_SQR3_SQ16_Pos (0UL) /*!< SQ16 (Bit 0) */
+#define ADC3_SQR3_SQ16_Msk (0x1fUL) /*!< SQ16 (Bitfield-Mask: 0x1f) */
+/* ========================================================== LR =========================================================== */
+#define ADC3_LR_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define ADC3_LR_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define ADC3_LR_EXTEN_Pos (6UL) /*!< EXTEN (Bit 6) */
+#define ADC3_LR_EXTEN_Msk (0xc0UL) /*!< EXTEN (Bitfield-Mask: 0x03) */
+#define ADC3_LR_EXTSEL_Pos (0UL) /*!< EXTSEL (Bit 0) */
+#define ADC3_LR_EXTSEL_Msk (0x1fUL) /*!< EXTSEL (Bitfield-Mask: 0x1f) */
+/* ========================================================== DR =========================================================== */
+#define ADC3_DR_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */
+#define ADC3_DR_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MAXDR ========================================================= */
+#define ADC3_MAXDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC3_MAXDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MINDR ========================================================= */
+#define ADC3_MINDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC3_MINDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JSQR ========================================================== */
+#define ADC3_JSQR_JSQ4_Pos (18UL) /*!< JSQ4 (Bit 18) */
+#define ADC3_JSQR_JSQ4_Msk (0x7c0000UL) /*!< JSQ4 (Bitfield-Mask: 0x1f) */
+#define ADC3_JSQR_JSQ3_Pos (12UL) /*!< JSQ3 (Bit 12) */
+#define ADC3_JSQR_JSQ3_Msk (0x1f000UL) /*!< JSQ3 (Bitfield-Mask: 0x1f) */
+#define ADC3_JSQR_JSQ2_Pos (6UL) /*!< JSQ2 (Bit 6) */
+#define ADC3_JSQR_JSQ2_Msk (0x7c0UL) /*!< JSQ2 (Bitfield-Mask: 0x1f) */
+#define ADC3_JSQR_JSQ1_Pos (0UL) /*!< JSQ1 (Bit 0) */
+#define ADC3_JSQR_JSQ1_Msk (0x1fUL) /*!< JSQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================== JLR ========================================================== */
+#define ADC3_JLR_JLEN_Pos (8UL) /*!< JLEN (Bit 8) */
+#define ADC3_JLR_JLEN_Msk (0x300UL) /*!< JLEN (Bitfield-Mask: 0x03) */
+#define ADC3_JLR_JEXTEN_Pos (6UL) /*!< JEXTEN (Bit 6) */
+#define ADC3_JLR_JEXTEN_Msk (0xc0UL) /*!< JEXTEN (Bitfield-Mask: 0x03) */
+#define ADC3_JLR_JEXTSEL_Pos (0UL) /*!< JEXTSEL (Bit 0) */
+#define ADC3_JLR_JEXTSEL_Msk (0x1fUL) /*!< JEXTSEL (Bitfield-Mask: 0x1f) */
+/* ======================================================== MAXJDR ========================================================= */
+#define ADC3_MAXJDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC3_MAXJDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ======================================================== MINJDR ========================================================= */
+#define ADC3_MINJDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC3_MINJDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR0 ========================================================== */
+#define ADC3_JDR0_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC3_JDR0_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR1 ========================================================== */
+#define ADC3_JDR1_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC3_JDR1_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR2 ========================================================== */
+#define ADC3_JDR2_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC3_JDR2_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR3 ========================================================== */
+#define ADC3_JDR3_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC3_JDR3_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR0 ========================================================== */
+#define ADC3_TR0_HT0_Pos (16UL) /*!< HT0 (Bit 16) */
+#define ADC3_TR0_HT0_Msk (0xffff0000UL) /*!< HT0 (Bitfield-Mask: 0xffff) */
+#define ADC3_TR0_LT0_Pos (0UL) /*!< LT0 (Bit 0) */
+#define ADC3_TR0_LT0_Msk (0xffffUL) /*!< LT0 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR1 ========================================================== */
+#define ADC3_TR1_HT1_Pos (16UL) /*!< HT1 (Bit 16) */
+#define ADC3_TR1_HT1_Msk (0xffff0000UL) /*!< HT1 (Bitfield-Mask: 0xffff) */
+#define ADC3_TR1_LT1_Pos (0UL) /*!< LT1 (Bit 0) */
+#define ADC3_TR1_LT1_Msk (0xffffUL) /*!< LT1 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR2 ========================================================== */
+#define ADC3_TR2_HT2_Pos (16UL) /*!< HT2 (Bit 16) */
+#define ADC3_TR2_HT2_Msk (0xffff0000UL) /*!< HT2 (Bitfield-Mask: 0xffff) */
+#define ADC3_TR2_LT2_Pos (0UL) /*!< LT2 (Bit 0) */
+#define ADC3_TR2_LT2_Msk (0xffffUL) /*!< LT2 (Bitfield-Mask: 0xffff) */
+/* ======================================================== AWD0CR ========================================================= */
+#define ADC3_AWD0CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC3_AWD0CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC3_AWD0CR_AW0CH_Pos (0UL) /*!< AW0CH (Bit 0) */
+#define ADC3_AWD0CR_AW0CH_Msk (0xfffffUL) /*!< AW0CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD1CR ========================================================= */
+#define ADC3_AWD1CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC3_AWD1CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC3_AWD1CR_AW1CH_Pos (0UL) /*!< AW1CH (Bit 0) */
+#define ADC3_AWD1CR_AW1CH_Msk (0xfffffUL) /*!< AW1CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD2CR ========================================================= */
+#define ADC3_AWD2CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC3_AWD2CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC3_AWD2CR_AW2CH_Pos (0UL) /*!< AW2CH (Bit 0) */
+#define ADC3_AWD2CR_AW2CH_Msk (0xfffffUL) /*!< AW2CH (Bitfield-Mask: 0xfffff) */
+/* ========================================================= OFR0 ========================================================== */
+#define ADC3_OFR0_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC3_OFR0_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR1 ========================================================== */
+#define ADC3_OFR1_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC3_OFR1_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR2 ========================================================== */
+#define ADC3_OFR2_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC3_OFR2_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR3 ========================================================== */
+#define ADC3_OFR3_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC3_OFR3_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= GCR0 ========================================================== */
+#define ADC3_GCR0_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC3_GCR0_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR1 ========================================================== */
+#define ADC3_GCR1_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC3_GCR1_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR2 ========================================================== */
+#define ADC3_GCR2_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC3_GCR2_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR3 ========================================================== */
+#define ADC3_GCR3_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC3_GCR3_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= DISR ========================================================== */
+#define ADC3_DISR_DON19_Pos (19UL) /*!< DON19 (Bit 19) */
+#define ADC3_DISR_DON19_Msk (0x80000UL) /*!< DON19 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON18_Pos (18UL) /*!< DON18 (Bit 18) */
+#define ADC3_DISR_DON18_Msk (0x40000UL) /*!< DON18 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON17_Pos (17UL) /*!< DON17 (Bit 17) */
+#define ADC3_DISR_DON17_Msk (0x20000UL) /*!< DON17 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON16_Pos (16UL) /*!< DON16 (Bit 16) */
+#define ADC3_DISR_DON16_Msk (0x10000UL) /*!< DON16 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON15_Pos (15UL) /*!< DON15 (Bit 15) */
+#define ADC3_DISR_DON15_Msk (0x8000UL) /*!< DON15 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON14_Pos (14UL) /*!< DON14 (Bit 14) */
+#define ADC3_DISR_DON14_Msk (0x4000UL) /*!< DON14 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON13_Pos (13UL) /*!< DON13 (Bit 13) */
+#define ADC3_DISR_DON13_Msk (0x2000UL) /*!< DON13 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON12_Pos (12UL) /*!< DON12 (Bit 12) */
+#define ADC3_DISR_DON12_Msk (0x1000UL) /*!< DON12 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON11_Pos (11UL) /*!< DON11 (Bit 11) */
+#define ADC3_DISR_DON11_Msk (0x800UL) /*!< DON11 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON10_Pos (10UL) /*!< DON10 (Bit 10) */
+#define ADC3_DISR_DON10_Msk (0x400UL) /*!< DON10 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON9_Pos (9UL) /*!< DON9 (Bit 9) */
+#define ADC3_DISR_DON9_Msk (0x200UL) /*!< DON9 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON8_Pos (8UL) /*!< DON8 (Bit 8) */
+#define ADC3_DISR_DON8_Msk (0x100UL) /*!< DON8 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON7_Pos (7UL) /*!< DON7 (Bit 7) */
+#define ADC3_DISR_DON7_Msk (0x80UL) /*!< DON7 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON6_Pos (6UL) /*!< DON6 (Bit 6) */
+#define ADC3_DISR_DON6_Msk (0x40UL) /*!< DON6 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON5_Pos (5UL) /*!< DON5 (Bit 5) */
+#define ADC3_DISR_DON5_Msk (0x20UL) /*!< DON5 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON4_Pos (4UL) /*!< DON4 (Bit 4) */
+#define ADC3_DISR_DON4_Msk (0x10UL) /*!< DON4 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON3_Pos (3UL) /*!< DON3 (Bit 3) */
+#define ADC3_DISR_DON3_Msk (0x8UL) /*!< DON3 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON2_Pos (2UL) /*!< DON2 (Bit 2) */
+#define ADC3_DISR_DON2_Msk (0x4UL) /*!< DON2 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON1_Pos (1UL) /*!< DON1 (Bit 1) */
+#define ADC3_DISR_DON1_Msk (0x2UL) /*!< DON1 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON0_Pos (0UL) /*!< DON0 (Bit 0) */
+#define ADC3_DISR_DON0_Msk (0x1UL) /*!< DON0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DIER ========================================================== */
+#define ADC3_DIER_DONIE19_Pos (19UL) /*!< DONIE19 (Bit 19) */
+#define ADC3_DIER_DONIE19_Msk (0x80000UL) /*!< DONIE19 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE18_Pos (18UL) /*!< DONIE18 (Bit 18) */
+#define ADC3_DIER_DONIE18_Msk (0x40000UL) /*!< DONIE18 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE17_Pos (17UL) /*!< DONIE17 (Bit 17) */
+#define ADC3_DIER_DONIE17_Msk (0x20000UL) /*!< DONIE17 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE16_Pos (16UL) /*!< DONIE16 (Bit 16) */
+#define ADC3_DIER_DONIE16_Msk (0x10000UL) /*!< DONIE16 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE15_Pos (15UL) /*!< DONIE15 (Bit 15) */
+#define ADC3_DIER_DONIE15_Msk (0x8000UL) /*!< DONIE15 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE14_Pos (14UL) /*!< DONIE14 (Bit 14) */
+#define ADC3_DIER_DONIE14_Msk (0x4000UL) /*!< DONIE14 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE13_Pos (13UL) /*!< DONIE13 (Bit 13) */
+#define ADC3_DIER_DONIE13_Msk (0x2000UL) /*!< DONIE13 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE12_Pos (12UL) /*!< DONIE12 (Bit 12) */
+#define ADC3_DIER_DONIE12_Msk (0x1000UL) /*!< DONIE12 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE11_Pos (11UL) /*!< DONIE11 (Bit 11) */
+#define ADC3_DIER_DONIE11_Msk (0x800UL) /*!< DONIE11 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE10_Pos (10UL) /*!< DONIE10 (Bit 10) */
+#define ADC3_DIER_DONIE10_Msk (0x400UL) /*!< DONIE10 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE9_Pos (9UL) /*!< DONIE9 (Bit 9) */
+#define ADC3_DIER_DONIE9_Msk (0x200UL) /*!< DONIE9 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE8_Pos (8UL) /*!< DONIE8 (Bit 8) */
+#define ADC3_DIER_DONIE8_Msk (0x100UL) /*!< DONIE8 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE7_Pos (7UL) /*!< DONIE7 (Bit 7) */
+#define ADC3_DIER_DONIE7_Msk (0x80UL) /*!< DONIE7 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE6_Pos (6UL) /*!< DONIE6 (Bit 6) */
+#define ADC3_DIER_DONIE6_Msk (0x40UL) /*!< DONIE6 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE5_Pos (5UL) /*!< DONIE5 (Bit 5) */
+#define ADC3_DIER_DONIE5_Msk (0x20UL) /*!< DONIE5 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE4_Pos (4UL) /*!< DONIE4 (Bit 4) */
+#define ADC3_DIER_DONIE4_Msk (0x10UL) /*!< DONIE4 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE3_Pos (3UL) /*!< DONIE3 (Bit 3) */
+#define ADC3_DIER_DONIE3_Msk (0x8UL) /*!< DONIE3 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE2_Pos (2UL) /*!< DONIE2 (Bit 2) */
+#define ADC3_DIER_DONIE2_Msk (0x4UL) /*!< DONIE2 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE1_Pos (1UL) /*!< DONIE1 (Bit 1) */
+#define ADC3_DIER_DONIE1_Msk (0x2UL) /*!< DONIE1 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE0_Pos (0UL) /*!< DONIE0 (Bit 0) */
+#define ADC3_DIER_DONIE0_Msk (0x1UL) /*!< DONIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= CDR0 ========================================================== */
+#define ADC3_CDR0_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR0_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR1 ========================================================== */
+#define ADC3_CDR1_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR1_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR2 ========================================================== */
+#define ADC3_CDR2_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR2_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR3 ========================================================== */
+#define ADC3_CDR3_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR3_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR4 ========================================================== */
+#define ADC3_CDR4_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR4_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR5 ========================================================== */
+#define ADC3_CDR5_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR5_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR6 ========================================================== */
+#define ADC3_CDR6_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR6_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR7 ========================================================== */
+#define ADC3_CDR7_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR7_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR8 ========================================================== */
+#define ADC3_CDR8_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR8_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR9 ========================================================== */
+#define ADC3_CDR9_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR9_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR10 ========================================================= */
+#define ADC3_CDR10_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR10_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR11 ========================================================= */
+#define ADC3_CDR11_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR11_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR12 ========================================================= */
+#define ADC3_CDR12_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR12_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR13 ========================================================= */
+#define ADC3_CDR13_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR13_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR14 ========================================================= */
+#define ADC3_CDR14_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR14_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR15 ========================================================= */
+#define ADC3_CDR15_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR15_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR16 ========================================================= */
+#define ADC3_CDR16_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR16_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR17 ========================================================= */
+#define ADC3_CDR17_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR17_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR18 ========================================================= */
+#define ADC3_CDR18_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR18_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR19 ========================================================= */
+#define ADC3_CDR19_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR19_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= HISR ========================================================== */
+#define ADC3_HISR_HLF19_Pos (19UL) /*!< HLF19 (Bit 19) */
+#define ADC3_HISR_HLF19_Msk (0x80000UL) /*!< HLF19 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF18_Pos (18UL) /*!< HLF18 (Bit 18) */
+#define ADC3_HISR_HLF18_Msk (0x40000UL) /*!< HLF18 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF17_Pos (17UL) /*!< HLF17 (Bit 17) */
+#define ADC3_HISR_HLF17_Msk (0x20000UL) /*!< HLF17 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF16_Pos (16UL) /*!< HLF16 (Bit 16) */
+#define ADC3_HISR_HLF16_Msk (0x10000UL) /*!< HLF16 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF15_Pos (15UL) /*!< HLF15 (Bit 15) */
+#define ADC3_HISR_HLF15_Msk (0x8000UL) /*!< HLF15 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF14_Pos (14UL) /*!< HLF14 (Bit 14) */
+#define ADC3_HISR_HLF14_Msk (0x4000UL) /*!< HLF14 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF13_Pos (13UL) /*!< HLF13 (Bit 13) */
+#define ADC3_HISR_HLF13_Msk (0x2000UL) /*!< HLF13 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF12_Pos (12UL) /*!< HLF12 (Bit 12) */
+#define ADC3_HISR_HLF12_Msk (0x1000UL) /*!< HLF12 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF11_Pos (11UL) /*!< HLF11 (Bit 11) */
+#define ADC3_HISR_HLF11_Msk (0x800UL) /*!< HLF11 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF10_Pos (10UL) /*!< HLF10 (Bit 10) */
+#define ADC3_HISR_HLF10_Msk (0x400UL) /*!< HLF10 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF9_Pos (9UL) /*!< HLF9 (Bit 9) */
+#define ADC3_HISR_HLF9_Msk (0x200UL) /*!< HLF9 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF8_Pos (8UL) /*!< HLF8 (Bit 8) */
+#define ADC3_HISR_HLF8_Msk (0x100UL) /*!< HLF8 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF7_Pos (7UL) /*!< HLF7 (Bit 7) */
+#define ADC3_HISR_HLF7_Msk (0x80UL) /*!< HLF7 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF6_Pos (6UL) /*!< HLF6 (Bit 6) */
+#define ADC3_HISR_HLF6_Msk (0x40UL) /*!< HLF6 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF5_Pos (5UL) /*!< HLF5 (Bit 5) */
+#define ADC3_HISR_HLF5_Msk (0x20UL) /*!< HLF5 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF4_Pos (4UL) /*!< HLF4 (Bit 4) */
+#define ADC3_HISR_HLF4_Msk (0x10UL) /*!< HLF4 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF3_Pos (3UL) /*!< HLF3 (Bit 3) */
+#define ADC3_HISR_HLF3_Msk (0x8UL) /*!< HLF3 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF2_Pos (2UL) /*!< HLF2 (Bit 2) */
+#define ADC3_HISR_HLF2_Msk (0x4UL) /*!< HLF2 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF1_Pos (1UL) /*!< HLF1 (Bit 1) */
+#define ADC3_HISR_HLF1_Msk (0x2UL) /*!< HLF1 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF0_Pos (0UL) /*!< HLF0 (Bit 0) */
+#define ADC3_HISR_HLF0_Msk (0x1UL) /*!< HLF0 (Bitfield-Mask: 0x01) */
+/* ========================================================= HIER ========================================================== */
+#define ADC3_HIER_HLFIE19_Pos (19UL) /*!< HLFIE19 (Bit 19) */
+#define ADC3_HIER_HLFIE19_Msk (0x80000UL) /*!< HLFIE19 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE18_Pos (18UL) /*!< HLFIE18 (Bit 18) */
+#define ADC3_HIER_HLFIE18_Msk (0x40000UL) /*!< HLFIE18 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE17_Pos (17UL) /*!< HLFIE17 (Bit 17) */
+#define ADC3_HIER_HLFIE17_Msk (0x20000UL) /*!< HLFIE17 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE16_Pos (16UL) /*!< HLFIE16 (Bit 16) */
+#define ADC3_HIER_HLFIE16_Msk (0x10000UL) /*!< HLFIE16 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE15_Pos (15UL) /*!< HLFIE15 (Bit 15) */
+#define ADC3_HIER_HLFIE15_Msk (0x8000UL) /*!< HLFIE15 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE14_Pos (14UL) /*!< HLFIE14 (Bit 14) */
+#define ADC3_HIER_HLFIE14_Msk (0x4000UL) /*!< HLFIE14 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE13_Pos (13UL) /*!< HLFIE13 (Bit 13) */
+#define ADC3_HIER_HLFIE13_Msk (0x2000UL) /*!< HLFIE13 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE12_Pos (12UL) /*!< HLFIE12 (Bit 12) */
+#define ADC3_HIER_HLFIE12_Msk (0x1000UL) /*!< HLFIE12 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE11_Pos (11UL) /*!< HLFIE11 (Bit 11) */
+#define ADC3_HIER_HLFIE11_Msk (0x800UL) /*!< HLFIE11 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE10_Pos (10UL) /*!< HLFIE10 (Bit 10) */
+#define ADC3_HIER_HLFIE10_Msk (0x400UL) /*!< HLFIE10 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE9_Pos (9UL) /*!< HLFIE9 (Bit 9) */
+#define ADC3_HIER_HLFIE9_Msk (0x200UL) /*!< HLFIE9 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE8_Pos (8UL) /*!< HLFIE8 (Bit 8) */
+#define ADC3_HIER_HLFIE8_Msk (0x100UL) /*!< HLFIE8 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE7_Pos (7UL) /*!< HLFIE7 (Bit 7) */
+#define ADC3_HIER_HLFIE7_Msk (0x80UL) /*!< HLFIE7 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE6_Pos (6UL) /*!< HLFIE6 (Bit 6) */
+#define ADC3_HIER_HLFIE6_Msk (0x40UL) /*!< HLFIE6 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE5_Pos (5UL) /*!< HLFIE5 (Bit 5) */
+#define ADC3_HIER_HLFIE5_Msk (0x20UL) /*!< HLFIE5 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE4_Pos (4UL) /*!< HLFIE4 (Bit 4) */
+#define ADC3_HIER_HLFIE4_Msk (0x10UL) /*!< HLFIE4 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE3_Pos (3UL) /*!< HLFIE3 (Bit 3) */
+#define ADC3_HIER_HLFIE3_Msk (0x8UL) /*!< HLFIE3 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE2_Pos (2UL) /*!< HLFIE2 (Bit 2) */
+#define ADC3_HIER_HLFIE2_Msk (0x4UL) /*!< HLFIE2 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE1_Pos (1UL) /*!< HLFIE1 (Bit 1) */
+#define ADC3_HIER_HLFIE1_Msk (0x2UL) /*!< HLFIE1 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE0_Pos (0UL) /*!< HLFIE0 (Bit 0) */
+#define ADC3_HIER_HLFIE0_Msk (0x1UL) /*!< HLFIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FISR ========================================================== */
+#define ADC3_FISR_FUL19_Pos (19UL) /*!< FUL19 (Bit 19) */
+#define ADC3_FISR_FUL19_Msk (0x80000UL) /*!< FUL19 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL18_Pos (18UL) /*!< FUL18 (Bit 18) */
+#define ADC3_FISR_FUL18_Msk (0x40000UL) /*!< FUL18 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL17_Pos (17UL) /*!< FUL17 (Bit 17) */
+#define ADC3_FISR_FUL17_Msk (0x20000UL) /*!< FUL17 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL16_Pos (16UL) /*!< FUL16 (Bit 16) */
+#define ADC3_FISR_FUL16_Msk (0x10000UL) /*!< FUL16 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL15_Pos (15UL) /*!< FUL15 (Bit 15) */
+#define ADC3_FISR_FUL15_Msk (0x8000UL) /*!< FUL15 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL14_Pos (14UL) /*!< FUL14 (Bit 14) */
+#define ADC3_FISR_FUL14_Msk (0x4000UL) /*!< FUL14 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL13_Pos (13UL) /*!< FUL13 (Bit 13) */
+#define ADC3_FISR_FUL13_Msk (0x2000UL) /*!< FUL13 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL12_Pos (12UL) /*!< FUL12 (Bit 12) */
+#define ADC3_FISR_FUL12_Msk (0x1000UL) /*!< FUL12 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL11_Pos (11UL) /*!< FUL11 (Bit 11) */
+#define ADC3_FISR_FUL11_Msk (0x800UL) /*!< FUL11 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL10_Pos (10UL) /*!< FUL10 (Bit 10) */
+#define ADC3_FISR_FUL10_Msk (0x400UL) /*!< FUL10 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL9_Pos (9UL) /*!< FUL9 (Bit 9) */
+#define ADC3_FISR_FUL9_Msk (0x200UL) /*!< FUL9 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL8_Pos (8UL) /*!< FUL8 (Bit 8) */
+#define ADC3_FISR_FUL8_Msk (0x100UL) /*!< FUL8 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL7_Pos (7UL) /*!< FUL7 (Bit 7) */
+#define ADC3_FISR_FUL7_Msk (0x80UL) /*!< FUL7 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL6_Pos (6UL) /*!< FUL6 (Bit 6) */
+#define ADC3_FISR_FUL6_Msk (0x40UL) /*!< FUL6 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL5_Pos (5UL) /*!< FUL5 (Bit 5) */
+#define ADC3_FISR_FUL5_Msk (0x20UL) /*!< FUL5 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL4_Pos (4UL) /*!< FUL4 (Bit 4) */
+#define ADC3_FISR_FUL4_Msk (0x10UL) /*!< FUL4 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL3_Pos (3UL) /*!< FUL3 (Bit 3) */
+#define ADC3_FISR_FUL3_Msk (0x8UL) /*!< FUL3 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL2_Pos (2UL) /*!< FUL2 (Bit 2) */
+#define ADC3_FISR_FUL2_Msk (0x4UL) /*!< FUL2 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL1_Pos (1UL) /*!< FUL1 (Bit 1) */
+#define ADC3_FISR_FUL1_Msk (0x2UL) /*!< FUL1 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL0_Pos (0UL) /*!< FUL0 (Bit 0) */
+#define ADC3_FISR_FUL0_Msk (0x1UL) /*!< FUL0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FIER ========================================================== */
+#define ADC3_FIER_FULIE19_Pos (19UL) /*!< FULIE19 (Bit 19) */
+#define ADC3_FIER_FULIE19_Msk (0x80000UL) /*!< FULIE19 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE18_Pos (18UL) /*!< FULIE18 (Bit 18) */
+#define ADC3_FIER_FULIE18_Msk (0x40000UL) /*!< FULIE18 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE17_Pos (17UL) /*!< FULIE17 (Bit 17) */
+#define ADC3_FIER_FULIE17_Msk (0x20000UL) /*!< FULIE17 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE16_Pos (16UL) /*!< FULIE16 (Bit 16) */
+#define ADC3_FIER_FULIE16_Msk (0x10000UL) /*!< FULIE16 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE15_Pos (15UL) /*!< FULIE15 (Bit 15) */
+#define ADC3_FIER_FULIE15_Msk (0x8000UL) /*!< FULIE15 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE14_Pos (14UL) /*!< FULIE14 (Bit 14) */
+#define ADC3_FIER_FULIE14_Msk (0x4000UL) /*!< FULIE14 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE13_Pos (13UL) /*!< FULIE13 (Bit 13) */
+#define ADC3_FIER_FULIE13_Msk (0x2000UL) /*!< FULIE13 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE12_Pos (12UL) /*!< FULIE12 (Bit 12) */
+#define ADC3_FIER_FULIE12_Msk (0x1000UL) /*!< FULIE12 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE11_Pos (11UL) /*!< FULIE11 (Bit 11) */
+#define ADC3_FIER_FULIE11_Msk (0x800UL) /*!< FULIE11 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE10_Pos (10UL) /*!< FULIE10 (Bit 10) */
+#define ADC3_FIER_FULIE10_Msk (0x400UL) /*!< FULIE10 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE9_Pos (9UL) /*!< FULIE9 (Bit 9) */
+#define ADC3_FIER_FULIE9_Msk (0x200UL) /*!< FULIE9 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE8_Pos (8UL) /*!< FULIE8 (Bit 8) */
+#define ADC3_FIER_FULIE8_Msk (0x100UL) /*!< FULIE8 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE7_Pos (7UL) /*!< FULIE7 (Bit 7) */
+#define ADC3_FIER_FULIE7_Msk (0x80UL) /*!< FULIE7 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE6_Pos (6UL) /*!< FULIE6 (Bit 6) */
+#define ADC3_FIER_FULIE6_Msk (0x40UL) /*!< FULIE6 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE5_Pos (5UL) /*!< FULIE5 (Bit 5) */
+#define ADC3_FIER_FULIE5_Msk (0x20UL) /*!< FULIE5 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE4_Pos (4UL) /*!< FULIE4 (Bit 4) */
+#define ADC3_FIER_FULIE4_Msk (0x10UL) /*!< FULIE4 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE3_Pos (3UL) /*!< FULIE3 (Bit 3) */
+#define ADC3_FIER_FULIE3_Msk (0x8UL) /*!< FULIE3 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE2_Pos (2UL) /*!< FULIE2 (Bit 2) */
+#define ADC3_FIER_FULIE2_Msk (0x4UL) /*!< FULIE2 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE1_Pos (1UL) /*!< FULIE1 (Bit 1) */
+#define ADC3_FIER_FULIE1_Msk (0x2UL) /*!< FULIE1 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE0_Pos (0UL) /*!< FULIE0 (Bit 0) */
+#define ADC3_FIER_FULIE0_Msk (0x1UL) /*!< FULIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= TCR0 ========================================================== */
+#define ADC3_TCR0_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR0_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR0_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR0_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR0_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR0_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR0_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR0 ========================================================== */
+#define ADC3_TAR0_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR0_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR0 ========================================================== */
+#define ADC3_TLR0_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR0_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR1 ========================================================== */
+#define ADC3_TCR1_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR1_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR1_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR1_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR1_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR1_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR1_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR1 ========================================================== */
+#define ADC3_TAR1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR1_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR1 ========================================================== */
+#define ADC3_TLR1_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR1_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR2 ========================================================== */
+#define ADC3_TCR2_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR2_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR2_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR2_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR2_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR2_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR2_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR2 ========================================================== */
+#define ADC3_TAR2_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR2_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR2 ========================================================== */
+#define ADC3_TLR2_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR2_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR3 ========================================================== */
+#define ADC3_TCR3_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR3_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR3_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR3_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR3_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR3_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR3_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR3 ========================================================== */
+#define ADC3_TAR3_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR3_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR3 ========================================================== */
+#define ADC3_TLR3_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR3_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR4 ========================================================== */
+#define ADC3_TCR4_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR4_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR4_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR4_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR4_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR4_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR4_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR4_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR4 ========================================================== */
+#define ADC3_TAR4_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR4_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR4 ========================================================== */
+#define ADC3_TLR4_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR4_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR5 ========================================================== */
+#define ADC3_TCR5_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR5_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR5_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR5_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR5_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR5_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR5_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR5_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR5 ========================================================== */
+#define ADC3_TAR5_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR5_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR5 ========================================================== */
+#define ADC3_TLR5_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR5_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR6 ========================================================== */
+#define ADC3_TCR6_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR6_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR6_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR6_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR6_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR6_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR6_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR6_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR6 ========================================================== */
+#define ADC3_TAR6_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR6_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR6 ========================================================== */
+#define ADC3_TLR6_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR6_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR7 ========================================================== */
+#define ADC3_TCR7_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR7_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR7_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR7_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR7_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR7_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR7_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR7_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR7 ========================================================== */
+#define ADC3_TAR7_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR7_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR7 ========================================================== */
+#define ADC3_TLR7_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR7_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR8 ========================================================== */
+#define ADC3_TCR8_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR8_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR8_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR8_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR8_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR8_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR8_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR8_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR8 ========================================================== */
+#define ADC3_TAR8_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR8_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR8 ========================================================== */
+#define ADC3_TLR8_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR8_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR9 ========================================================== */
+#define ADC3_TCR9_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR9_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR9_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR9_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR9_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR9_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR9_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR9_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR9 ========================================================== */
+#define ADC3_TAR9_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR9_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR9 ========================================================== */
+#define ADC3_TLR9_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR9_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR10 ========================================================= */
+#define ADC3_TCR10_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR10_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR10_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR10_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR10_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR10_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR10_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR10_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR10 ========================================================= */
+#define ADC3_TAR10_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR10_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR10 ========================================================= */
+#define ADC3_TLR10_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR10_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR11 ========================================================= */
+#define ADC3_TCR11_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR11_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR11_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR11_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR11_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR11_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR11_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR11_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR11 ========================================================= */
+#define ADC3_TAR11_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR11_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR11 ========================================================= */
+#define ADC3_TLR11_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR11_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR12 ========================================================= */
+#define ADC3_TCR12_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR12_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR12_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR12_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR12_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR12_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR12_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR12_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR12 ========================================================= */
+#define ADC3_TAR12_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR12_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR12 ========================================================= */
+#define ADC3_TLR12_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR12_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR13 ========================================================= */
+#define ADC3_TCR13_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR13_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR13_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR13_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR13_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR13_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR13_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR13_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR13 ========================================================= */
+#define ADC3_TAR13_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR13_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR13 ========================================================= */
+#define ADC3_TLR13_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR13_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR14 ========================================================= */
+#define ADC3_TCR14_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR14_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR14_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR14_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR14_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR14_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR14_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR14_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR14 ========================================================= */
+#define ADC3_TAR14_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR14_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR14 ========================================================= */
+#define ADC3_TLR14_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR14_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR15 ========================================================= */
+#define ADC3_TCR15_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR15_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR15_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR15_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR15_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR15_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR15_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR15_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR15 ========================================================= */
+#define ADC3_TAR15_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR15_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR15 ========================================================= */
+#define ADC3_TLR15_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR15_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR16 ========================================================= */
+#define ADC3_TCR16_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR16_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR16_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR16_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR16_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR16_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR16_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR16_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR16 ========================================================= */
+#define ADC3_TAR16_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR16_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR16 ========================================================= */
+#define ADC3_TLR16_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR16_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR17 ========================================================= */
+#define ADC3_TCR17_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR17_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR17_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR17_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR17_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR17_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR17_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR17_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR17 ========================================================= */
+#define ADC3_TAR17_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR17_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR17 ========================================================= */
+#define ADC3_TLR17_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR17_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR18 ========================================================= */
+#define ADC3_TCR18_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR18_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR18_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR18_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR18_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR18_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR18_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR18_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR18 ========================================================= */
+#define ADC3_TAR18_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR18_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR18 ========================================================= */
+#define ADC3_TLR18_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR18_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR19 ========================================================= */
+#define ADC3_TCR19_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR19_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR19_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR19_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR19_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR19_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR19_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR19_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR19 ========================================================= */
+#define ADC3_TAR19_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR19_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR19 ========================================================= */
+#define ADC3_TLR19_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR19_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================== CCR ========================================================== */
+#define ADC3_CCR_DELAY_Pos (8UL) /*!< DELAY (Bit 8) */
+#define ADC3_CCR_DELAY_Msk (0x3ff00UL) /*!< DELAY (Bitfield-Mask: 0x3ff) */
+#define ADC3_CCR_DUAL_Pos (0UL) /*!< DUAL (Bit 0) */
+#define ADC3_CCR_DUAL_Msk (0xfUL) /*!< DUAL (Bitfield-Mask: 0x0f) */
+/* ========================================================== CSR ========================================================== */
+#define ADC3_CSR_EOSMP_SLV_Pos (25UL) /*!< EOSMP_SLV (Bit 25) */
+#define ADC3_CSR_EOSMP_SLV_Msk (0x2000000UL) /*!< EOSMP_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_ADRDY_SLV_Pos (24UL) /*!< ADRDY_SLV (Bit 24) */
+#define ADC3_CSR_ADRDY_SLV_Msk (0x1000000UL) /*!< ADRDY_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD2_SLV_Pos (23UL) /*!< AWD2_SLV (Bit 23) */
+#define ADC3_CSR_AWD2_SLV_Msk (0x800000UL) /*!< AWD2_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD1_SLV_Pos (22UL) /*!< AWD1_SLV (Bit 22) */
+#define ADC3_CSR_AWD1_SLV_Msk (0x400000UL) /*!< AWD1_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD0_SLV_Pos (21UL) /*!< AWD0_SLV (Bit 21) */
+#define ADC3_CSR_AWD0_SLV_Msk (0x200000UL) /*!< AWD0_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_OVR_SLV_Pos (20UL) /*!< OVR_SLV (Bit 20) */
+#define ADC3_CSR_OVR_SLV_Msk (0x100000UL) /*!< OVR_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_JEOS_SLV_Pos (19UL) /*!< JEOS_SLV (Bit 19) */
+#define ADC3_CSR_JEOS_SLV_Msk (0x80000UL) /*!< JEOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_JEOC_SLV_Pos (18UL) /*!< JEOC_SLV (Bit 18) */
+#define ADC3_CSR_JEOC_SLV_Msk (0x40000UL) /*!< JEOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_EOS_SLV_Pos (17UL) /*!< EOS_SLV (Bit 17) */
+#define ADC3_CSR_EOS_SLV_Msk (0x20000UL) /*!< EOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_EOC_SLV_Pos (16UL) /*!< EOC_SLV (Bit 16) */
+#define ADC3_CSR_EOC_SLV_Msk (0x10000UL) /*!< EOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_EOSMP_MST_Pos (9UL) /*!< EOSMP_MST (Bit 9) */
+#define ADC3_CSR_EOSMP_MST_Msk (0x200UL) /*!< EOSMP_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_ADRDY_MST_Pos (8UL) /*!< ADRDY_MST (Bit 8) */
+#define ADC3_CSR_ADRDY_MST_Msk (0x100UL) /*!< ADRDY_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD2_MST_Pos (7UL) /*!< AWD2_MST (Bit 7) */
+#define ADC3_CSR_AWD2_MST_Msk (0x80UL) /*!< AWD2_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD1_MST_Pos (6UL) /*!< AWD1_MST (Bit 6) */
+#define ADC3_CSR_AWD1_MST_Msk (0x40UL) /*!< AWD1_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD0_MST_Pos (5UL) /*!< AWD0_MST (Bit 5) */
+#define ADC3_CSR_AWD0_MST_Msk (0x20UL) /*!< AWD0_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_OVR_MST_Pos (4UL) /*!< OVR_MST (Bit 4) */
+#define ADC3_CSR_OVR_MST_Msk (0x10UL) /*!< OVR_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_JEOS_MST_Pos (3UL) /*!< JEOS_MST (Bit 3) */
+#define ADC3_CSR_JEOS_MST_Msk (0x8UL) /*!< JEOS_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_JEOC_MST_Pos (2UL) /*!< JEOC_MST (Bit 2) */
+#define ADC3_CSR_JEOC_MST_Msk (0x4UL) /*!< JEOC_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_EOS_MST_Pos (1UL) /*!< EOS_MST (Bit 1) */
+#define ADC3_CSR_EOS_MST_Msk (0x2UL) /*!< EOS_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_EOC_MST_Pos (0UL) /*!< EOC_MST (Bit 0) */
+#define ADC3_CSR_EOC_MST_Msk (0x1UL) /*!< EOC_MST (Bitfield-Mask: 0x01) */
+/* ========================================================== CDR ========================================================== */
+#define ADC3_CDR_RDATA_SLV_Pos (16UL) /*!< RDATA_SLV (Bit 16) */
+#define ADC3_CDR_RDATA_SLV_Msk (0xffff0000UL) /*!< RDATA_SLV (Bitfield-Mask: 0xffff) */
+#define ADC3_CDR_RDATA_MST_Pos (0UL) /*!< RDATA_MST (Bit 0) */
+#define ADC3_CDR_RDATA_MST_Msk (0xffffUL) /*!< RDATA_MST (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR6 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR6_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR6_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR6_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR6_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR6_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR6_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== SCR ========================================================== */
+#define TMR6_SCR_EE_Pos (22UL) /*!< EE (Bit 22) */
+#define TMR6_SCR_EE_Msk (0x400000UL) /*!< EE (Bitfield-Mask: 0x01) */
+#define TMR6_SCR_EMS_Pos (20UL) /*!< EMS (Bit 20) */
+#define TMR6_SCR_EMS_Msk (0x300000UL) /*!< EMS (Bitfield-Mask: 0x03) */
+#define TMR6_SCR_EFS_Pos (16UL) /*!< EFS (Bit 16) */
+#define TMR6_SCR_EFS_Msk (0xf0000UL) /*!< EFS (Bitfield-Mask: 0x0f) */
+#define TMR6_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR6_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR6_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR6_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR6_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR6_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR6_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR6_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR6_IER_CIE_Pos (0UL) /*!< CIE (Bit 0) */
+#define TMR6_IER_CIE_Msk (0x1UL) /*!< CIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR6_SR_STS_Pos (18UL) /*!< STS (Bit 18) */
+#define TMR6_SR_STS_Msk (0x40000UL) /*!< STS (Bitfield-Mask: 0x01) */
+#define TMR6_SR_CUS_Pos (17UL) /*!< CUS (Bit 17) */
+#define TMR6_SR_CUS_Msk (0x20000UL) /*!< CUS (Bitfield-Mask: 0x01) */
+#define TMR6_SR_PUS_Pos (16UL) /*!< PUS (Bit 16) */
+#define TMR6_SR_PUS_Msk (0x10000UL) /*!< PUS (Bitfield-Mask: 0x01) */
+#define TMR6_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR6_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR6_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR6_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR6_SR_CIF_Pos (0UL) /*!< CIF (Bit 0) */
+#define TMR6_SR_CIF_Msk (0x1UL) /*!< CIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR6_UGR_SG_Pos (12UL) /*!< SG (Bit 12) */
+#define TMR6_UGR_SG_Msk (0x1000UL) /*!< SG (Bitfield-Mask: 0x01) */
+#define TMR6_UGR_CG_Pos (4UL) /*!< CG (Bit 4) */
+#define TMR6_UGR_CG_Msk (0x10UL) /*!< CG (Bitfield-Mask: 0x01) */
+#define TMR6_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR6_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR6_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR6_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR6_CCMR_RLD_Pos (2UL) /*!< RLD (Bit 2) */
+#define TMR6_CCMR_RLD_Msk (0x4UL) /*!< RLD (Bitfield-Mask: 0x01) */
+/* ========================================================= CCER ========================================================== */
+#define TMR6_CCER_CCP_Pos (2UL) /*!< CCP (Bit 2) */
+#define TMR6_CCER_CCP_Msk (0x4UL) /*!< CCP (Bitfield-Mask: 0x01) */
+#define TMR6_CCER_CCE_Pos (0UL) /*!< CCE (Bit 0) */
+#define TMR6_CCER_CCE_Msk (0x1UL) /*!< CCE (Bitfield-Mask: 0x01) */
+/* ========================================================== CPR ========================================================== */
+#define TMR6_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR6_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR6_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR6_PSCR_PSC_Msk (0xffUL) /*!< PSC (Bitfield-Mask: 0xff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR6_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR6_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR6_CC0R_CMP_Pos (0UL) /*!< CMP (Bit 0) */
+#define TMR6_CC0R_CMP_Msk (0xffffUL) /*!< CMP (Bitfield-Mask: 0xffff) */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MYCHIP_H */
+
+
+/** @} */ /* End of group myChip */
+
+/** @} */ /* End of group ARM Ltd. */
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Inc/myChip_struct.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Inc/myChip_struct.h
new file mode 100644
index 0000000000..611c568dd9
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Inc/myChip_struct.h
@@ -0,0 +1,50199 @@
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * @file myChip.h
+ * @brief CMSIS HeaderFile
+ * @version 1.2
+ * @date 02. November 2024
+ * @note Generated by SVDConv V3.3.35 on Saturday, 02.11.2024 11:59:18
+ * from File 'myChip.svd',
+ * last modified on Saturday, 02.11.2024 03:58:22
+ */
+
+
+
+/** @addtogroup ARM Ltd.
+ * @{
+ */
+
+
+/** @addtogroup myChip
+ * @{
+ */
+
+
+#ifndef MYCHIP_H
+#define MYCHIP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
+
+typedef enum {
+/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+/* =========================================== myChip Specific Interrupt Numbers =========================================== */
+ I2C0_IRQn = 0, /*!< 0 I2C0 */
+ I2C1_IRQn = 1, /*!< 1 I2C1 */
+ I2C2_IRQn = 2, /*!< 2 I2C2 */
+ UART0_IRQn = 3, /*!< 3 UART0 */
+ UART1_IRQn = 4, /*!< 4 UART1 */
+ UART2_IRQn = 5, /*!< 5 UART2 */
+ UART3_IRQn = 6, /*!< 6 UART3 */
+ UART4_IRQn = 7, /*!< 7 UART4 */
+ SPI0_IRQn = 8, /*!< 8 SPI0 */
+ SPI1_IRQn = 9, /*!< 9 SPI1 */
+ CAN0_IRQn = 10, /*!< 10 CAN0 */
+ CAN1_IRQn = 11, /*!< 11 CAN1 */
+ PDM0_IRQn = 12, /*!< 12 PDM0 */
+ PDM1_IRQn = 13, /*!< 13 PDM1 */
+ PDM2_IRQn = 14, /*!< 14 PDM2 */
+ PDM3_IRQn = 15, /*!< 15 PDM3 */
+ QEI0_IRQn = 16, /*!< 16 QEI0 */
+ QEI1_IRQn = 17, /*!< 17 QEI1 */
+ QEI2_IRQn = 18, /*!< 18 QEI2 */
+ DMA_CH0_IRQn = 19, /*!< 19 DMA_CH0 */
+ DMA_CH1_IRQn = 20, /*!< 20 DMA_CH1 */
+ DMA_CH2_IRQn = 21, /*!< 21 DMA_CH2 */
+ DMA_CH3_IRQn = 22, /*!< 22 DMA_CH3 */
+ DMA_CH4_IRQn = 23, /*!< 23 DMA_CH4 */
+ DMA_CH5_IRQn = 24, /*!< 24 DMA_CH5 */
+ TMR7_IRQn = 25, /*!< 25 TMR7 */
+ TMR8_IRQn = 26, /*!< 26 TMR8 */
+ TMR0_IRQn = 27, /*!< 27 TMR0 */
+ TMR1_IRQn = 28, /*!< 28 TMR1 */
+ TMR2_IRQn = 29, /*!< 29 TMR2 */
+ TMR3_IRQn = 30, /*!< 30 TMR3 */
+ TMR4_IRQn = 31, /*!< 31 TMR4 */
+ TMR9_BRK_IRQn = 32, /*!< 32 TMR9_BRK */
+ TMR9_UPD_IRQn = 33, /*!< 33 TMR9_UPD */
+ TMR9_TRG_IRQn = 34, /*!< 34 TMR9_TRG */
+ TMR9_CC_IRQn = 35, /*!< 35 TMR9_CC */
+ TMR10_BRK_IRQn = 36, /*!< 36 TMR10_BRK */
+ TMR10_UPD_IRQn = 37, /*!< 37 TMR10_UPD */
+ TMR10_TRG_IRQn = 38, /*!< 38 TMR10_TRG */
+ TMR10_CC_IRQn = 39, /*!< 39 TMR10_CC */
+ IWDG_IRQn = 40, /*!< 40 IWDG */
+ WWDG_IRQn = 41, /*!< 41 WWDG */
+ GPIOA_IRQn = 42, /*!< 42 GPIOA */
+ GPIOB_IRQn = 43, /*!< 43 GPIOB */
+ GPIOC_IRQn = 44, /*!< 44 GPIOC */
+ GPIOD_IRQn = 45, /*!< 45 GPIOD */
+ GPIOE_IRQn = 46, /*!< 46 GPIOE */
+ GPIOF_IRQn = 47, /*!< 47 GPIOF */
+ FLASH_IRQn = 48, /*!< 48 FLASH */
+ IIR_IRQn = 49, /*!< 49 IIR0_5 Interrupt Group */
+ CORDIC_IRQn = 50, /*!< 50 CORDIC */
+ CMPG0_IRQn = 51, /*!< 51 CMP0_2 Interrupt Group */
+ CMPG1_IRQn = 52, /*!< 52 CMP3_5 Interrupt Group */
+ CMPG2_IRQn = 53, /*!< 53 CMP6_8 Interrupt Group */
+ HRPWM_MST_IRQn = 54, /*!< 54 HRPWM_MST */
+ HRPWM_SLV0_IRQn = 55, /*!< 55 HRPWM_SLV0 */
+ HRPWM_SLV1_IRQn = 56, /*!< 56 HRPWM_SLV1 */
+ HRPWM_SLV2_IRQn = 57, /*!< 57 HRPWM_SLV2 */
+ HRPWM_SLV3_IRQn = 58, /*!< 58 HRPWM_SLV3 */
+ HRPWM_SLV4_IRQn = 59, /*!< 59 HRPWM_SLV4 */
+ HRPWM_SLV5_IRQn = 60, /*!< 60 HRPWM_SLV5 */
+ HRPWM_SLV6_IRQn = 61, /*!< 61 HRPWM_SLV6 */
+ HRPWM_SLV7_IRQn = 62, /*!< 62 HRPWM_SLV7 */
+ HRPWM_COM_IRQn = 63, /*!< 63 HRPWM_COM */
+ ADC0_NORM_IRQn = 64, /*!< 64 ADC0_NORM */
+ ADC0_SAMP_IRQn = 65, /*!< 65 ADC0_SAMP */
+ ADC0_HALF_IRQn = 66, /*!< 66 ADC0_HALF */
+ ADC0_FULL_IRQn = 67, /*!< 67 ADC0_FULL */
+ ADC1_NORM_IRQn = 68, /*!< 68 ADC1_NORM */
+ ADC1_SAMP_IRQn = 69, /*!< 69 ADC1_SAMP */
+ ADC1_HALF_IRQn = 70, /*!< 70 ADC1_HALF */
+ ADC1_FULL_IRQn = 71, /*!< 71 ADC1_FULL */
+ ADC2_NORM_IRQn = 72, /*!< 72 ADC2_NORM */
+ ADC2_SAMP_IRQn = 73, /*!< 73 ADC2_SAMP */
+ ADC2_HALF_IRQn = 74, /*!< 74 ADC2_HALF */
+ ADC2_FULL_IRQn = 75, /*!< 75 ADC2_FULL */
+ ADC3_NORM_IRQn = 76, /*!< 76 ADC3_NORM */
+ ADC3_SAMP_IRQn = 77, /*!< 77 ADC3_SAMP */
+ ADC3_HALF_IRQn = 78, /*!< 78 ADC3_HALF */
+ ADC3_FULL_IRQn = 79, /*!< 79 ADC3_FULL */
+ PMU_IRQn = 80, /*!< 80 PMU */
+ USB_PWR_IRQn = 81, /*!< 81 USB_PWR */
+ USB_DET_IRQn = 82, /*!< 82 USB_DET */
+ USB_EP_IRQn = 83, /*!< 83 USB_EP */
+ XIF_IRQn = 84, /*!< 84 XIF */
+ CAN0_INT1_IRQn = 85, /*!< 85 CAN0_INT1 */
+ CAN1_INT1_IRQn = 86, /*!< 86 CAN1_INT1 */
+ TMR6_IRQn = 87 /*!< 87 TMR6 */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
+#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 0 /*!< MPU present */
+#define __FPU_PRESENT 1 /*!< FPU present */
+#define __VTOR_PRESENT 1 /*!< VTOR present */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
+#include "system_myChip.h" /*!< myChip System */
+
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+#endif
+
+
+/* ======================================== Start of section using anonymous unions ======================================== */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+ #pragma clang diagnostic ignored "-Wnested-anon-types"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ XIF ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief XIF (XIF)
+ */
+
+typedef struct { /*!< (@ 0x40016000) XIF Structure */
+
+ union {
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) XIF Enable Register */
+
+ struct {
+ __IOM uint32_t ENABLE : 1; /*!< [0..0] XIF使能（XIF Enable） */
+ __IOM uint32_t DMAEN : 1; /*!< [1..1] XIF DMA接收使能（XIF DMA Enable） */
+ __IOM uint32_t SRST : 1; /*!< [2..2] XIF软复位（XIF Software Reset） */
+ __IOM uint32_t RELOAD : 1; /*!< [3..3] 重复模式（Reload Mode） */
+ __IOM uint32_t TXDEN : 1; /*!< [4..4] XIF DMA发送使能（XIF DMA Enable） */
+ __IOM uint32_t DIR : 1; /*!< [5..5] XIF传输方向 */
+ uint32_t : 26;
+ } ENABLE_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) XIF Control Register */
+
+ struct {
+ __IOM uint32_t DCNT : 8; /*!< [7..0] XIF传输数据量（The Count of DATA） */
+ __IOM uint32_t RXFTLR : 3; /*!< [10..8] RXFIFO满中断阈值（RXFIFO Full Watermark） */
+ uint32_t : 1;
+ __IOM uint32_t RXFIE : 1; /*!< [12..12] RXFI中断使能（RXFIFO Full Interrupt Enable） */
+ __IOM uint32_t RXOFIE : 1; /*!< [13..13] RXOFI中断使能（RXFIFO Overflow Interrupt Enable） */
+ __IOM uint32_t RXDIE : 1; /*!< [14..14] RXDI中断使能（XIF Rx Done Interrupt Enable） */
+ __IOM uint32_t BTOIE : 1; /*!< [15..15] BTOI中断使能（XIF Wait BUSY Timeout Interrupt
+ Enable） */
+ __IOM uint32_t DCS : 3; /*!< [18..16] XIF采样时间点延后选择（XIF Delay Chain Select） */
+ uint32_t : 1;
+ __IOM uint32_t TXFTLR : 3; /*!< [22..20] TXFIFO空中断阈值（TXFIFO Empty Watermark） */
+ uint32_t : 1;
+ __IOM uint32_t TXEIE : 1; /*!< [24..24] TXEI中断使能（TXFIFO Empty Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t TXDIE : 1; /*!< [26..26] TXDI中断使能（XIF Tx Done Interrupt Enable） */
+ uint32_t : 5;
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING; /*!< (@ 0x00000008) XIF Timing Register */
+
+ struct {
+ __IOM uint32_t RSTTIME : 8; /*!< [7..0] XIF RESET为高的时间长度（The Length Of Time For
+ RESET High） */
+ __IOM uint32_t CONLTIME : 8; /*!< [15..8] XIF CONVST为低的时间长度（The Length Of Time
+ For CONVST Low） */
+ __IOM uint32_t RDLTIME : 8; /*!< [23..16] XIF RD为低的时间长度（The Length Of Time For
+ RD Low） */
+ __IOM uint32_t RDHTIME : 8; /*!< [31..24] XIF RD为高的时间长度（The Length Of Time For
+ RD High） */
+ } TIMING_b;
+ } ;
+
+ union {
+ __IOM uint32_t TO; /*!< (@ 0x0000000C) XIF Timeout Register */
+
+ struct {
+ __IOM uint32_t PTOT : 16; /*!< [15..0] XIF超时设置（XIF BUSY TIMEOUT Timing） */
+ uint32_t : 16;
+ } TO_b;
+ } ;
+
+ union {
+ __IOM uint32_t DATA; /*!< (@ 0x00000010) XIF Read Data Registers */
+
+ struct {
+ __IM uint32_t DATA : 16; /*!< [15..0] 读取数据寄存器（FIFO Read DATA Register） */
+ uint32_t : 16;
+ } DATA_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000014) XIF Interrupt And Status Register */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] RXFIFO满中断（RXFIFO Full Interrupt） */
+ __IOM uint32_t RXOFI : 1; /*!< [1..1] RXFIFO上溢中断（RXFIFO Overflow Interrupt） */
+ __IOM uint32_t RXDI : 1; /*!< [2..2] XIF接收完成中断（XIF RX Done Interrupt） */
+ __IOM uint32_t BTOI : 1; /*!< [3..3] XIF等待BUSY超时中断（XIF Wait BUSY Timeout Interrupt
+ Enable） */
+ __IM uint32_t FE : 1; /*!< [4..4] RXFIFO空标志（RXFIFO Empty Flag） */
+ __IM uint32_t FF : 1; /*!< [5..5] RXFIFO满标志（RXFIFO Full Flag） */
+ uint32_t : 2;
+ __IM uint32_t RXFLR : 4; /*!< [11..8] RXFIFO实时剩余数据量（RXFIFO Level Register） */
+ __IM uint32_t TXFLR : 4; /*!< [15..12] TXFIFO实时剩余数据量（TXFIFO Level Register） */
+ __IM uint32_t TXEI : 1; /*!< [16..16] TXFIFO空中断（TXFIFO Empty Interrupt） */
+ uint32_t : 1;
+ __IOM uint32_t TXDI : 1; /*!< [18..18] XIF发送完成中断（XIF TX Done Interrupt） */
+ uint32_t : 1;
+ __IM uint32_t TFE : 1; /*!< [20..20] TXFIFO空标志（TXFIFO Empty Flag） */
+ __IM uint32_t TFF : 1; /*!< [21..21] TXFIFO满标志（TXFIFO Full Flag） */
+ uint32_t : 10;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WDATA; /*!< (@ 0x00000018) XIF Write Data Registers */
+
+ struct {
+ __IOM uint32_t WDATA : 16; /*!< [15..0] 写入数据寄存器（FIFO Write DATA Register） */
+ uint32_t : 16;
+ } WDATA_b;
+ } ;
+} XIF_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ WWDG ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief WWDG (WWDG)
+ */
+
+typedef struct { /*!< (@ 0x4000D000) WWDG Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) WWDG Control Register */
+
+ struct {
+ __IOM uint32_t WEN : 1; /*!< [0..0] WWDG使能位（WWDG Enable） */
+ __IOM uint32_t EWIE : 1; /*!< [1..1] WWDG提前唤醒中断使能位（WWDG Early Wakeup Interrupt
+ Enable） */
+ uint32_t : 30;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WVR; /*!< (@ 0x00000004) WWDG Window Register */
+
+ struct {
+ __IOM uint32_t WV : 16; /*!< [15..0] WWDG窗口比较值（WWDG Window Value） */
+ uint32_t : 16;
+ } WVR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CVR; /*!< (@ 0x00000008) WWDG Counter Register */
+
+ struct {
+ __IOM uint32_t CV : 16; /*!< [15..0] WWDG递减计数值（WWDG Counter Value） */
+ uint32_t : 16;
+ } CVR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x0000000C) WWDG Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 16; /*!< [15..0] WWDG预分频器（WWDG Prescaler divider） */
+ uint32_t : 16;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) WWDG Status Register */
+
+ struct {
+ __IOM uint32_t EWIF : 1; /*!< [0..0] WWDG提前唤醒中断标志位（WWDG Early Wakeup Interrupt
+ Flag） */
+ uint32_t : 31;
+ } ISR_b;
+ } ;
+} WWDG_Type; /*!< Size = 20 (0x14) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ USB ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief USB (USB)
+ */
+
+typedef struct { /*!< (@ 0x40035000) USB Structure */
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000000) USB Control Register Include Address And Power
+ Control */
+
+ struct {
+ __IOM uint32_t FADDR : 8; /*!< [7..0] 设备地址（address of the peripheral） */
+ uint32_t : 1;
+ __IOM uint32_t SUSMOD : 1; /*!< [9..9] 挂起使能（Suspend Enable） */
+ __IOM uint32_t RESUME : 1; /*!< [10..10] 唤醒使能（Resume Enable） */
+ __IM uint32_t RESET : 1; /*!< [11..11] 复位检测信号（Reset Detect Flag） */
+ uint32_t : 2;
+ __IOM uint32_t SCONN : 1; /*!< [14..14] 软件连接使能（Software Connect Enable） */
+ __IOM uint32_t ISOUP : 1; /*!< [15..15] ISO更新使能（ISO Upgrade Enable） */
+ uint32_t : 16;
+ } CTRL_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t INDEX; /*!< (@ 0x0000000C) USB Index And Frame Number Register */
+
+ struct {
+ __IM uint32_t FNUM : 16; /*!< [15..0] SOF帧号（SOF Frame Number） */
+ __IOM uint32_t INDEX : 4; /*!< [19..16] 端点索引寄存器（Endpoint Index Register） */
+ uint32_t : 12;
+ } INDEX_b;
+ } ;
+
+ union {
+ union {
+ __IOM uint32_t TX0CTRL; /*!< (@ 0x00000010) USB TX Endpoint 0 Control Register */
+
+ struct {
+ __IOM uint32_t TXMAXP : 16; /*!< [15..0] 端点TX最大数据量（Endpoint TX Max Data Number） */
+ __IOM uint32_t RXPR : 1; /*!< [16..16] 端点0 RX准备就绪（Endpoint 0 RX Ready） */
+ __IOM uint32_t TXPR : 1; /*!< [17..17] 端点0 TX准备就绪（Endpoint 0 TX Ready） */
+ __IOM uint32_t SENTSTA : 1; /*!< [18..18] 端点0发送完Stall标志（Sent Stall Flag） */
+ __IOM uint32_t DATAEND : 1; /*!< [19..19] 端点0数据结束标志（Last Data End Flag） */
+ __IOM uint32_t SETUPEND : 1; /*!< [20..20] 端点0 Setup结束标志（Setup Transfer End Flag） */
+ __IOM uint32_t SENDSTA : 1; /*!< [21..21] 端点0 发送Stall使能（Send Stall Enable） */
+ __IOM uint32_t SRPCLR : 1; /*!< [22..22] 端点0 RXPR清除（RxPktRdy Clear） */
+ __IOM uint32_t SSECLR : 1; /*!< [23..23] 端点0 SETUPEND位清除（SetupEnd Clear） */
+ __IOM uint32_t FLFIFO : 1; /*!< [24..24] 端点0 FIFO刷新使能（Flush FIFO Enable） */
+ uint32_t : 7;
+ } TX0CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t TXnCTRL; /*!< (@ 0x00000010) USB TX Endpoint n Control Register */
+
+ struct {
+ __IOM uint32_t TXMAXP : 16; /*!< [15..0] 端点TX最大数据量（Endpoint TX Max Data Number） */
+ __IOM uint32_t TXPR : 1; /*!< [16..16] 端点n TX准备就绪（Endpoint n TX Ready） */
+ __IM uint32_t FIFONE : 1; /*!< [17..17] 端点n FIFO非空（FIFO Not Empty） */
+ __IOM uint32_t UNRUN : 1; /*!< [18..18] 端点n欠限（Underrun） */
+ __IOM uint32_t FLFIFO : 1; /*!< [19..19] 端点n FIFO刷新使能（Flush FIFO Enable） */
+ __IOM uint32_t SENDSTA : 1; /*!< [20..20] 端点n发送STALL（Send STALL） */
+ __IOM uint32_t SENTSTA : 1; /*!< [21..21] 端点n发送完STALL（Send STALL End） */
+ __IOM uint32_t CLRDT : 1; /*!< [22..22] 端点n清除数据切换（Clear Data Toggle） */
+ uint32_t : 4;
+ __IOM uint32_t FRCDATTOG : 1; /*!< [27..27] 端点n强制数据切换（Force Data Toggle） */
+ uint32_t : 1;
+ __IOM uint32_t MODE : 1; /*!< [29..29] 端点n方向模式选择（Endpoint Direction Select） */
+ __IOM uint32_t ISO : 1; /*!< [30..30] 端点n ISO传输使能（ISO Transfer Enable） */
+ __IOM uint32_t AUTOSET : 1; /*!< [31..31] 端点n自动设置使能（Auto Set Enable） */
+ } TXnCTRL_b;
+ } ;
+ };
+
+ union {
+ __IOM uint32_t RXCTRL; /*!< (@ 0x00000014) USB RX Endpoint Control Register */
+
+ struct {
+ __IOM uint32_t RXMAXP : 16; /*!< [15..0] 端点RX最大数据量（Endpoint RX Max Data Number） */
+ __IOM uint32_t RXPR : 1; /*!< [16..16] 端点RX准备就绪（Endpoint RX Ready） */
+ __IM uint32_t FIFOFULL : 1; /*!< [17..17] FIFO满标志（FIFO Full Flag） */
+ __IOM uint32_t OVERRUN : 1; /*!< [18..18] RXFIFO溢出（RXFIFO Overrun） */
+ __IM uint32_t DATAERR : 1; /*!< [19..19] 数据包错误（Data Error Flag） */
+ __IOM uint32_t FLFIFO : 1; /*!< [20..20] FIFO刷新使能（Flush FIFO Enable） */
+ __IOM uint32_t SENDSTA : 1; /*!< [21..21] 发送Stall使能（Send Stall Enable） */
+ __IOM uint32_t SENTSTA : 1; /*!< [22..22] 发送完Stall标志（Sent Stall Flag） */
+ __IOM uint32_t CDATTOG : 1; /*!< [23..23] 清除数据切换（Clear Data Toggle） */
+ __IM uint32_t INCRX : 1; /*!< [24..24] 接收不完整数据包指示（Incomplete Data Flag） */
+ uint32_t : 5;
+ __IOM uint32_t ISO : 1; /*!< [30..30] ISO传输使能（ISO Transfer Enable） */
+ __IOM uint32_t AUTOCLR : 1; /*!< [31..31] 自动清除使能（Auto Clear Enable） */
+ } RXCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t RXCOUNT; /*!< (@ 0x00000018) USB Number of bytes to be read from RX endpoint
+ FIFO */
+
+ struct {
+ __IM uint32_t RXCOUNT : 14; /*!< [13..0] 收到的数据字节数（RX Data Count） */
+ uint32_t : 18;
+ } RXCOUNT_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIFOSIZE; /*!< (@ 0x0000001C) USB Returns the configured size of the selected
+ RX FIFO and TX FIFOs */
+
+ struct {
+ uint32_t : 24;
+ __IM uint32_t TXFIFOSIZE : 4; /*!< [27..24] TXFIFO大小（TXFIFO Size） */
+ __IM uint32_t RXFIFOSIZE : 4; /*!< [31..28] RXFIFO大小（RXFIFO Size） */
+ } FIFOSIZE_b;
+ } ;
+ __IM uint32_t RESERVED1[16];
+
+ union {
+ __IOM uint32_t FIFOSZ; /*!< (@ 0x00000060) The Dynamic FIFO registers */
+
+ struct {
+ uint32_t : 16;
+ __IOM uint32_t TXSZ : 4; /*!< [19..16] TX端点最大数据包大小（TX Endpoint Maximum
+ Packet Size） */
+ __IOM uint32_t TXDPB : 1; /*!< [20..20] TX端点双数据包缓冲使能（TX Endpoint Double
+ Packet Buffer Enable） */
+ uint32_t : 3;
+ __IOM uint32_t RXSZ : 4; /*!< [27..24] RX端点最大数据包大小（RX Endpoint Maximum
+ Packet Size） */
+ __IOM uint32_t RXDPB : 1; /*!< [28..28] RX端点双数据包缓冲使能（RX Endpoint Double
+ Packet Buffer Enable） */
+ uint32_t : 3;
+ } FIFOSZ_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIFOAD; /*!< (@ 0x00000064) USB FIFO Start Address Register */
+
+ struct {
+ __IOM uint32_t TXAD : 13; /*!< [12..0] TX端点FIFO的起始地址（Start Address Of TX Endpoint
+ FIFO） */
+ uint32_t : 3;
+ __IOM uint32_t RXAD : 13; /*!< [28..16] RX端点FIFO的起始地址（Start Address Of RX Endpoint
+ FIFO） */
+ uint32_t : 3;
+ } FIFOAD_b;
+ } ;
+ __IM uint32_t RESERVED2[230];
+
+ union {
+ __IOM uint32_t PINCTRL; /*!< (@ 0x00000400) USB DP/DM PIN Control Register */
+
+ struct {
+ __IOM uint32_t PHY_EN : 1; /*!< [0..0] PHY使能，USB使用就开 */
+ __IOM uint32_t TM1 : 1; /*!< [1..1] 测试模式使能 */
+ __IOM uint32_t CID : 1; /*!< [2..2] mini AB连接器ID引脚使能 */
+ __IOM uint32_t VBUSLO : 1; /*!< [3..3] Vbus超过会话结束阈值使能 */
+ __IOM uint32_t AVALID : 1; /*!< [4..4] Vbus高于Vbus A设备会话阈值使能 */
+ __IOM uint32_t VBUSVALID : 1; /*!< [5..5] Vbus高于VBusValid阈值使能 */
+ __IOM uint32_t Test_En : 1; /*!< [6..6] 设置为1时开启USB测试模式，DPDM会持续输出6MHz的时钟 */
+ uint32_t : 1;
+ __IOM uint32_t DPPU_EN : 1; /*!< [8..8] DP上拉软件使能（DP Software Pull Up Enable） */
+ __IOM uint32_t DPPU : 1; /*!< [9..9] DP上拉使能（DP Pull Up Enable） */
+ __IOM uint32_t DPPD_EN : 1; /*!< [10..10] DP下拉软件使能（DP Software Pull Down Enable） */
+ __IOM uint32_t DPPD : 1; /*!< [11..11] DP下拉使能（DP Pull Down Enable） */
+ __IOM uint32_t DMPU_EN : 1; /*!< [12..12] DM上拉软件使能（DM Software Pull Up Enable） */
+ __IOM uint32_t DMPU : 1; /*!< [13..13] DM上拉使能（DM Pull Up Enable） */
+ __IOM uint32_t DMPD_EN : 1; /*!< [14..14] DM下拉软件使能（DM Software Pull Down Enable） */
+ __IOM uint32_t DMPD : 1; /*!< [15..15] DM下拉使能（DM Pull Down Enable） */
+ __IOM uint32_t DPTRIM : 3; /*!< [18..16] DP端电阻修调（DP Resistor Trimming） */
+ __IOM uint32_t DPSR : 1; /*!< [19..19] DP PAD输出slewrate增强使能（DP Output Slewrate
+ Enhancement Enable） */
+ __IOM uint32_t DMTRIM : 3; /*!< [22..20] DM端电阻修调（DM Resistor Trimming） */
+ __IOM uint32_t DMSR : 1; /*!< [23..23] DM PAD输出slewrate增强使能（DM Output Slewrate
+ Enhancement Enable） */
+ __IOM uint32_t DPIE_EN : 1; /*!< [24..24] DP软件输入使能（DP Software Input Enable） */
+ __IOM uint32_t DPIE : 1; /*!< [25..25] DP输入使能（DP Input Enable） */
+ __IOM uint32_t DMIE_EN : 1; /*!< [26..26] DM软件输入使能（DM Software Input Enable） */
+ __IOM uint32_t DMIE : 1; /*!< [27..27] DM输入使能（DM Input Enable） */
+ __IOM uint32_t DPOE_EN : 1; /*!< [28..28] DP软件输出使能（DP Software Output Enable） */
+ __IOM uint32_t DPOE : 1; /*!< [29..29] DP输出使能（DP Output Enable） */
+ __IOM uint32_t DMOE_EN : 1; /*!< [30..30] DM软件输出使能（DM Software Output Enable） */
+ __IOM uint32_t DMOE : 1; /*!< [31..31] DM输出使能（DM Output Enable） */
+ } PINCTRL_b;
+ } ;
+ __IM uint32_t RESERVED3[3];
+
+ union {
+ __IOM uint32_t IUINTREN; /*!< (@ 0x00000410) USB Insert/Unplug Detect Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t ISDETIEN : 1; /*!< [0..0] USB插入检测中断使能（Insert Detect Interrupt
+ Enable） */
+ __IOM uint32_t UPDETIEN : 1; /*!< [1..1] USB拔出检测中断使能（Unplug Detect Interrupt
+ Enable） */
+ uint32_t : 2;
+ __IOM uint32_t DETDB : 12; /*!< [15..4] 去抖配置（Debounce Config) */
+ uint32_t : 16;
+ } IUINTREN_b;
+ } ;
+
+ union {
+ __IOM uint32_t EPINTREN; /*!< (@ 0x00000414) USB Endpoint Tx/Rx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t EP0INTEN : 1; /*!< [0..0] EP0INT中断使能（Endpoint 0 Interrupt Enable） */
+ __IOM uint32_t EP1TXINTEN : 1; /*!< [1..1] EP1TXINT中断使能（Endpoint 1 TX Interrupt Enable） */
+ __IOM uint32_t EP2TXINTEN : 1; /*!< [2..2] EP2TXINT中断使能（Endpoint 2 TX Interrupt Enable） */
+ uint32_t : 14;
+ __IOM uint32_t EP1RXINTEN : 1; /*!< [17..17] EP1RXINT中断使能（Endpoint 1 RX Interrupt Enable） */
+ __IOM uint32_t EP2RXINTEN : 1; /*!< [18..18] EP2RXINT中断使能（Endpoint 2 RX Interrupt Enable） */
+ uint32_t : 13;
+ } EPINTREN_b;
+ } ;
+
+ union {
+ __IOM uint32_t USBINTREN; /*!< (@ 0x00000418) USB Power Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t SUSPENDINTEN : 1; /*!< [0..0] SUSPEND中断使能（Suspend Interrupt Enable） */
+ __IOM uint32_t RESUMEINTEN : 1; /*!< [1..1] RESUME中断使能（Resume Interrupt Enable） */
+ __IOM uint32_t RESETINTEN : 1; /*!< [2..2] RESET中断使能（Detect Reset Interrupt Enable） */
+ __IOM uint32_t SOFINTEN : 1; /*!< [3..3] SOF中断使能（RX First SOF Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t DISCONINTEN : 1; /*!< [5..5] DISCON中断使能（Peripheral Disconnect Interrupt
+ Enable） */
+ uint32_t : 26;
+ } USBINTREN_b;
+ } ;
+ __IM uint32_t RESERVED4;
+
+ union {
+ __IOM uint32_t IUINTR; /*!< (@ 0x00000420) USB Insert/Unplug Detect Interrupt Register */
+
+ struct {
+ __IOM uint32_t ISDETI : 1; /*!< [0..0] USB插入检测中断（Insert Detect Interrupt） */
+ __IOM uint32_t UPDETI : 1; /*!< [1..1] USB拔出检测中断（Unplug Detect Interrupt） */
+ uint32_t : 30;
+ } IUINTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EPINTR; /*!< (@ 0x00000424) USB Endpoint Tx/Rx Interrupt Register */
+
+ struct {
+ __IM uint32_t EP0INT : 1; /*!< [0..0] 端点0中断（Endpoint 0 Interrupt） */
+ __IM uint32_t EP1TXINT : 1; /*!< [1..1] 端点1 TX中断（Endpoint 1 TX Interrupt） */
+ __IM uint32_t EP2TXINT : 1; /*!< [2..2] 端点2 TX中断（Endpoint 2 TX Interrupt） */
+ uint32_t : 14;
+ __IM uint32_t EP1RXINT : 1; /*!< [17..17] 端点1 RX中断（Endpoint 1 RX Interrupt） */
+ __IM uint32_t EP2RXINT : 1; /*!< [18..18] 端点2 RX中断（Endpoint 2 RX Interrupt） */
+ uint32_t : 13;
+ } EPINTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t USBINTR; /*!< (@ 0x00000428) USB Power Interrupt Register */
+
+ struct {
+ __IM uint32_t SUSPEND : 1; /*!< [0..0] 挂起中断（Suspend Interrupt） */
+ __IM uint32_t RESUME : 1; /*!< [1..1] 唤醒中断（Resume Interrupt） */
+ __IM uint32_t RESET : 1; /*!< [2..2] 检测到复位信号中断（Detect Reset Interrupt） */
+ __IM uint32_t SOF : 1; /*!< [3..3] 收到第一个SOF包中断（RX First SOF Interrupt） */
+ uint32_t : 1;
+ __IM uint32_t DISCON : 1; /*!< [5..5] 外设失去连接中断（Peripheral Disconnect Interrupt） */
+ uint32_t : 26;
+ } USBINTR_b;
+ } ;
+ __IM uint32_t RESERVED5[5];
+
+ union {
+ __IOM uint32_t FIFO0; /*!< (@ 0x00000440) FIFOs for Endpoints 0 */
+
+ struct {
+ __IOM uint32_t FIFO0 : 32; /*!< [31..0] 端点0的FIFO读写（Endpoint 0 FIFO Write/Read） */
+ } FIFO0_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIFO1; /*!< (@ 0x00000444) FIFOs for Endpoints 1 */
+
+ struct {
+ __IOM uint32_t FIFO1 : 32; /*!< [31..0] 端点1的FIFO读写（Endpoint 1 FIFO Write/Read） */
+ } FIFO1_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIFO2; /*!< (@ 0x00000448) FIFOs for Endpoints 2 */
+
+ struct {
+ __IOM uint32_t FIFO2 : 32; /*!< [31..0] 端点2的FIFO读写（Endpoint 2 FIFO Write/Read） */
+ } FIFO2_b;
+ } ;
+} USB_Type; /*!< Size = 1100 (0x44c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART0 (UART0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) UART0 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) UART Control Register0 */
+
+ struct {
+ __IOM uint32_t UE : 1; /*!< [0..0] UART使能（UART Enable） */
+ __IOM uint32_t RE : 1; /*!< [1..1] UART RX使能（UART RX Enable） */
+ __IOM uint32_t TE : 1; /*!< [2..2] UART TX使能（UART TX Enable） */
+ __IOM uint32_t RFR : 1; /*!< [3..3] UART RX-FIFO复位（UART RX-FIFO Reset） */
+ __IOM uint32_t TFR : 1; /*!< [4..4] UART TX-FIFO复位（UART TX-FIFO Reset） */
+ __IOM uint32_t DRE : 1; /*!< [5..5] UART RX-DMA使能（UART RX DMA Enable） */
+ __IOM uint32_t DTE : 1; /*!< [6..6] UART TX-DMA使能（UART TX DMA Enable） */
+ __IOM uint32_t OWE : 1; /*!< [7..7] UART单线模式使能（UART One-Wire Enable） */
+ __IOM uint32_t SWAP : 1; /*!< [8..8] UART TX和RX引脚交换使能（UART TX/RX Swap Enable） */
+ __IOM uint32_t RPOL : 1; /*!< [9..9] UART RX引脚极性选择（UART RX Polarity Select） */
+ __IOM uint32_t TPOL : 1; /*!< [10..10] UART TX引脚极性选择（UART TX Polarity Select） */
+ __IOM uint32_t RTOE : 1; /*!< [11..11] UART RX超时使能（UART RX Timeout Enable） */
+ __IOM uint32_t OVER8 : 1; /*!< [12..12] UART过采样模式选择 (UART Oversampling Mode Select) */
+ __IOM uint32_t NFE : 1; /*!< [13..13] UART非FIFO模式使能 (UART Non-FIFO Mode Enable) */
+ __IOM uint32_t RTOM : 1; /*!< [14..14] UART RTO模式选择 (UART RTO Mode Select) */
+ __IOM uint32_t ONEBIT : 1; /*!< [15..15] UART ONEBIT模式选择 (UART ONEBIT Mode Select) */
+ __IOM uint32_t LOOP : 1; /*!< [16..16] UART LOOPBACK模式选择 (UART LOOPBACK Mode Select) */
+ __IOM uint32_t OVDIS : 1; /*!< [17..17] UART RX-OVERDIS模式使能 (UART RX OVERDIS Enable) */
+ uint32_t : 2;
+ __IOM uint32_t ABRM : 2; /*!< [21..20] UART自动波特率检测模式（UART Auto Baud Rate
+ Mode） */
+ uint32_t : 10;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) UART Control Register1 */
+
+ struct {
+ __IOM uint32_t LEN : 2; /*!< [1..0] UART数据长度选择（UART Length Select） */
+ __IOM uint32_t STP : 1; /*!< [2..2] UART Stop位选择（UART Stop Select） */
+ __IOM uint32_t PEN : 1; /*!< [3..3] UART奇偶检验位使能（UART Parity Enable） */
+ __IOM uint32_t PSEL : 1; /*!< [4..4] UART奇偶检验选择（UART Parity Select） */
+ __IOM uint32_t SPE : 1; /*!< [5..5] UART强制校验使能位（UART Stick Parity Enable） */
+ uint32_t : 1;
+ __IOM uint32_t MSB : 1; /*!< [7..7] UART MSB使能（UART MSB Enable） */
+ __IOM uint32_t RS485E : 1; /*!< [8..8] UART RS485 功能使能（UART RS485 Enable） */
+ __IOM uint32_t REP : 1; /*!< [9..9] UART RE极性（UART RE Polarity） */
+ __IOM uint32_t DEP : 1; /*!< [10..10] UART DE极性（UART DE Polarity） */
+ uint32_t : 5;
+ __IOM uint32_t EBE : 1; /*!< [16..16] UART拓展位使能（UART Extend-Bit Enable） */
+ __IOM uint32_t REM : 1; /*!< [17..17] UART RX拓展模式选择（UART RX Extend-Mode Select） */
+ __IOM uint32_t TEM : 1; /*!< [18..18] UART TX拓展模式选择（UART TX Extend-Mode Select） */
+ __IOM uint32_t BKR : 1; /*!< [19..19] UART Break帧请求位（UART Break Request） */
+ __IOM uint32_t IDR : 1; /*!< [20..20] UART IDLE帧请求位（UART IDLE Request） */
+ __IOM uint32_t ABR : 1; /*!< [21..21] UART自动波特率检测使能（UART Auto Baud Rate
+ Enable） */
+ uint32_t : 10;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) UART Baud Rate Register */
+
+ struct {
+ __IOM uint32_t BAUD : 16; /*!< [15..0] UART波特率配置（UART Baud Rate） */
+ uint32_t : 16;
+ } BAUD_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) UART FIFO Control Register */
+
+ struct {
+ __IOM uint32_t RXFT : 4; /*!< [3..0] UART RXFIFO满中断阈值（UART RX-FIFO Level-Full
+ Threshold） */
+ __IOM uint32_t TXFT : 4; /*!< [7..4] UART TXFIFO空中断阈值（UART TXFIFO Level-Empty
+ Threshold） */
+ uint32_t : 24;
+ } FIFOCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING0; /*!< (@ 0x00000014) UART Timing Register0 */
+
+ struct {
+ __IOM uint32_t DEAT : 16; /*!< [15..0] UART DE驱动使能时间（UART DE Assertion Timing） */
+ __IOM uint32_t DEDT : 16; /*!< [31..16] UART DE驱动禁止时间（UART DE Deassertion Timing） */
+ } TIMING0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING1; /*!< (@ 0x00000018) UART Timing Register1 */
+
+ struct {
+ __IOM uint32_t RDET : 16; /*!< [15..0] UART RE到DE切换时间（UART RE2DE Turn-Around Timing） */
+ __IOM uint32_t DRET : 16; /*!< [31..16] UART DE到RE切换时间（UART DE2RE Turn-Around Timing） */
+ } TIMING1_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t TDR; /*!< (@ 0x00000020) UART Transmit Data Register */
+
+ struct {
+ __IOM uint32_t TD : 9; /*!< [8..0] UART TX数据寄存器（UART Transmit Data Register） */
+ uint32_t : 23;
+ } TDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000024) UART Receive Data Register */
+
+ struct {
+ __IM uint32_t RD : 9; /*!< [8..0] UART RX数据寄存器（UART Receive Data Register） */
+ __IM uint32_t PRST : 1; /*!< [9..9] UART RX奇偶校验位状态（UART RX Parity Status） */
+ __IM uint32_t FMST : 1; /*!< [10..10] UART RX帧状态（UART RX Frame Status） */
+ uint32_t : 5;
+ __IOM uint32_t OVDA : 11; /*!< [26..16] UART RX上溢数据寄存器（UART RX OVER DATA） */
+ uint32_t : 5;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR; /*!< (@ 0x00000028) UART Transmit Address Register */
+
+ struct {
+ __IOM uint32_t TAR : 8; /*!< [7..0] UART TX发送地址寄存器（UART Transmit Address
+ Register） */
+ uint32_t : 24;
+ } TAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RAR; /*!< (@ 0x0000002C) UART Receive Address Register */
+
+ struct {
+ __IOM uint32_t RAR : 8; /*!< [7..0] UART RX接收地址寄存器（UART Receive Address Register） */
+ uint32_t : 24;
+ } RAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RTO; /*!< (@ 0x00000030) UART Receiver Timeout Register */
+
+ struct {
+ __IOM uint32_t RTO : 16; /*!< [15..0] UART RX超时阈值（Receiver Timeout Timing） */
+ uint32_t : 16;
+ } RTO_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTEN; /*!< (@ 0x00000034) UART Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RFIE : 1; /*!< [0..0] UART RX-FIFO满中断使能（UART RX-FIFO Full Interrupt
+ Enable） */
+ __IOM uint32_t TEIE : 1; /*!< [1..1] UART TX-FIFO空中断使能（UART TX-FIFO Empty Interrupt
+ Enable） */
+ __IOM uint32_t ROIE : 1; /*!< [2..2] UART RX-FIFO上溢中断使能（UART RX-FIFO Overflow
+ Interrupt Enable） */
+ __IOM uint32_t RUIE : 1; /*!< [3..3] UART RX-FIFO下溢中断使能（UART RX-FIFO Underflow
+ Interrupt Enable） */
+ __IOM uint32_t TOIE : 1; /*!< [4..4] UART TX-FIFO上溢中断使能（UART TX-FIFO Overflow
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t IDIE : 1; /*!< [6..6] UART 空闲中断使能（UART Idle Interrupt Enable） */
+ __IOM uint32_t NOIE : 1; /*!< [7..7] UART 噪声检测中断使能（UART Noise Detection
+ Interrupt Enable） */
+ __IOM uint32_t PEIE : 1; /*!< [8..8] UART RX奇偶校验错误中断使能（UART Parity Error
+ Interrupt Enable） */
+ __IOM uint32_t FEIE : 1; /*!< [9..9] UART RX传输帧错误中断使能（UART Frame Error
+ Interrupt Enable） */
+ __IOM uint32_t BKIE : 1; /*!< [10..10] UART RX Break中断使能（UART RX Break Interrupt
+ Enable） */
+ __IOM uint32_t RTIE : 1; /*!< [11..11] UART RX传输超时中断使能（UART RX Timeout Interrupt
+ Enable） */
+ __IOM uint32_t TDIE : 1; /*!< [12..12] UART TX传输完成中断使能（UART TX Done Interrupt
+ Enable） */
+ __IOM uint32_t TBIE : 1; /*!< [13..13] UART TX Break完成中断使能（UART TX Break Done
+ Interrupt Enable） */
+ __IOM uint32_t IDLE : 1; /*!< [14..14] UART TX Idle完成中断使能（UART TX Idle Done
+ Interrupt Enable） */
+ __IOM uint32_t AMIE : 1; /*!< [15..15] UART RX地址匹配中断使能（UART RX Address Match
+ Interrupt Enable） */
+ __IOM uint32_t ABRE : 1; /*!< [16..16] UART 自动波特率检测错误中断使能（UART
+ Auto Baud Rate Error Interrupt Enable） */
+ uint32_t : 15;
+ } INTEN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INT; /*!< (@ 0x00000038) UART Interrupt Register */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] UART RX-FIFO阈值满中断标志（UART RX-FIFO Level-Full
+ Interrupt Flag） */
+ __IM uint32_t TXEI : 1; /*!< [1..1] UART TX-FIFO阈值空中断标志（UART TX-FIFO Level-Empty
+ Interrupt Flag） */
+ __IOM uint32_t ROIF : 1; /*!< [2..2] UART RX-FIFO上溢中断标志（UART RX-FIFO Overflow
+ Interrupt Flag） */
+ __IOM uint32_t RUIF : 1; /*!< [3..3] UART RX-FIFO下溢中断标志（UART RX-FIFO Underflow
+ Interrupt Flag） */
+ __IOM uint32_t TOIF : 1; /*!< [4..4] UART TX-FIFO上溢错误中断标志（UART TX-FIFO Overflow
+ Interrupt Flag） */
+ uint32_t : 1;
+ __IOM uint32_t IDIF : 1; /*!< [6..6] UART空闲中断标志（UART Idle Interrupt Flag） */
+ __IOM uint32_t NOIF : 1; /*!< [7..7] UART 噪声检测中断标志（UART Noise Detection
+ Interrupt Flag） */
+ __IOM uint32_t PEIF : 1; /*!< [8..8] UART奇偶校验错误中断标志（UART Parity Error
+ Interrupt Flag） */
+ __IOM uint32_t FEIF : 1; /*!< [9..9] UART RX帧错误中断标志（UART Frame Error Interrupt
+ Flag） */
+ __IOM uint32_t BKIF : 1; /*!< [10..10] UART RX BREAK中断标志（UART Break Interrupt Flag） */
+ __IOM uint32_t RTOI : 1; /*!< [11..11] UART RX传输超时中断标志（UART RX Timeout Interrupt
+ Flag） */
+ __IOM uint32_t TDIF : 1; /*!< [12..12] UART发送完成中断标志（UART TX Done Interrupt
+ Flag） */
+ __IOM uint32_t TBIF : 1; /*!< [13..13] UART TX Break完成中断标志（UART TX Break Done
+ Interrupt Flag） */
+ __IOM uint32_t IDLF : 1; /*!< [14..14] UART TX Idle完成中断标志（UART TX Idle Done
+ Interrupt Flag） */
+ __IOM uint32_t AMIF : 1; /*!< [15..15] UART RX地址匹配中断标志（UART RX Address Match
+ Interrupt Flag） */
+ __IOM uint32_t ABRF : 1; /*!< [16..16] UART 自动波特率检测错误中断标志（UART
+ Auto Baud Rate Error Interrupt Flag） */
+ uint32_t : 15;
+ } INT_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x0000003C) UART Status Register */
+
+ struct {
+ __IM uint32_t TBSY : 1; /*!< [0..0] UART TX总线忙碌标志（UART TX Busy Flag） */
+ __IM uint32_t TFE : 1; /*!< [1..1] UART TX发送FIFO空标志（UART TX-FIFO Empty Flag） */
+ __IM uint32_t TFF : 1; /*!< [2..2] UART TX发送FIFO满标志（UART TX-FIFO Full Flag） */
+ __IM uint32_t TFL : 5; /*!< [7..3] UART TX-FIFO实时剩余数据量（UART TX-FIFO Level
+ Register） */
+ __IM uint32_t RBSY : 1; /*!< [8..8] UART RX总线忙碌标志（UART RX Busy Flag） */
+ __IM uint32_t RFE : 1; /*!< [9..9] UART RX接收FIFO空标志（UART RX-FIFO Empty Flag） */
+ __IM uint32_t RFF : 1; /*!< [10..10] UART RX接收FIFO满标志（UART RX-FIFO Full Flag） */
+ __IM uint32_t RFL : 5; /*!< [15..11] UART RX-FIFO实时剩余数据量（UART RX-FIFO Level
+ Register） */
+ __IM uint32_t RSE : 1; /*!< [16..16] UART RX-Start错误标志位（UART RX-Start Error
+ Flag） */
+ uint32_t : 15;
+ } STATUS_b;
+ } ;
+} UART0_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART1 (UART1)
+ */
+
+typedef struct { /*!< (@ 0x40004000) UART1 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) UART Control Register0 */
+
+ struct {
+ __IOM uint32_t UE : 1; /*!< [0..0] UART使能（UART Enable） */
+ __IOM uint32_t RE : 1; /*!< [1..1] UART RX使能（UART RX Enable） */
+ __IOM uint32_t TE : 1; /*!< [2..2] UART TX使能（UART TX Enable） */
+ __IOM uint32_t RFR : 1; /*!< [3..3] UART RX-FIFO复位（UART RX-FIFO Reset） */
+ __IOM uint32_t TFR : 1; /*!< [4..4] UART TX-FIFO复位（UART TX-FIFO Reset） */
+ __IOM uint32_t DRE : 1; /*!< [5..5] UART RX-DMA使能（UART RX DMA Enable） */
+ __IOM uint32_t DTE : 1; /*!< [6..6] UART TX-DMA使能（UART TX DMA Enable） */
+ __IOM uint32_t OWE : 1; /*!< [7..7] UART单线模式使能（UART One-Wire Enable） */
+ __IOM uint32_t SWAP : 1; /*!< [8..8] UART TX和RX引脚交换使能（UART TX/RX Swap Enable） */
+ __IOM uint32_t RPOL : 1; /*!< [9..9] UART RX引脚极性选择（UART RX Polarity Select） */
+ __IOM uint32_t TPOL : 1; /*!< [10..10] UART TX引脚极性选择（UART TX Polarity Select） */
+ __IOM uint32_t RTOE : 1; /*!< [11..11] UART RX超时使能（UART RX Timeout Enable） */
+ __IOM uint32_t OVER8 : 1; /*!< [12..12] UART过采样模式选择 (UART Oversampling Mode Select) */
+ __IOM uint32_t NFE : 1; /*!< [13..13] UART非FIFO模式使能 (UART Non-FIFO Mode Enable) */
+ __IOM uint32_t RTOM : 1; /*!< [14..14] UART RTO模式选择 (UART RTO Mode Select) */
+ __IOM uint32_t ONEBIT : 1; /*!< [15..15] UART ONEBIT模式选择 (UART ONEBIT Mode Select) */
+ __IOM uint32_t LOOP : 1; /*!< [16..16] UART LOOPBACK模式选择 (UART LOOPBACK Mode Select) */
+ __IOM uint32_t OVDIS : 1; /*!< [17..17] UART RX-OVERDIS模式使能 (UART RX OVERDIS Enable) */
+ uint32_t : 2;
+ __IOM uint32_t ABRM : 2; /*!< [21..20] UART自动波特率检测模式（UART Auto Baud Rate
+ Mode） */
+ uint32_t : 10;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) UART Control Register1 */
+
+ struct {
+ __IOM uint32_t LEN : 2; /*!< [1..0] UART数据长度选择（UART Length Select） */
+ __IOM uint32_t STP : 1; /*!< [2..2] UART Stop位选择（UART Stop Select） */
+ __IOM uint32_t PEN : 1; /*!< [3..3] UART奇偶检验位使能（UART Parity Enable） */
+ __IOM uint32_t PSEL : 1; /*!< [4..4] UART奇偶检验选择（UART Parity Select） */
+ __IOM uint32_t SPE : 1; /*!< [5..5] UART强制校验使能位（UART Stick Parity Enable） */
+ uint32_t : 1;
+ __IOM uint32_t MSB : 1; /*!< [7..7] UART MSB使能（UART MSB Enable） */
+ __IOM uint32_t RS485E : 1; /*!< [8..8] UART RS485 功能使能（UART RS485 Enable） */
+ __IOM uint32_t REP : 1; /*!< [9..9] UART RE极性（UART RE Polarity） */
+ __IOM uint32_t DEP : 1; /*!< [10..10] UART DE极性（UART DE Polarity） */
+ uint32_t : 5;
+ __IOM uint32_t EBE : 1; /*!< [16..16] UART拓展位使能（UART Extend-Bit Enable） */
+ __IOM uint32_t REM : 1; /*!< [17..17] UART RX拓展模式选择（UART RX Extend-Mode Select） */
+ __IOM uint32_t TEM : 1; /*!< [18..18] UART TX拓展模式选择（UART TX Extend-Mode Select） */
+ __IOM uint32_t BKR : 1; /*!< [19..19] UART Break帧请求位（UART Break Request） */
+ __IOM uint32_t IDR : 1; /*!< [20..20] UART IDLE帧请求位（UART IDLE Request） */
+ __IOM uint32_t ABR : 1; /*!< [21..21] UART自动波特率检测使能（UART Auto Baud Rate
+ Enable） */
+ uint32_t : 10;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) UART Baud Rate Register */
+
+ struct {
+ __IOM uint32_t BAUD : 16; /*!< [15..0] UART波特率配置（UART Baud Rate） */
+ uint32_t : 16;
+ } BAUD_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) UART FIFO Control Register */
+
+ struct {
+ __IOM uint32_t RXFT : 4; /*!< [3..0] UART RXFIFO满中断阈值（UART RX-FIFO Level-Full
+ Threshold） */
+ __IOM uint32_t TXFT : 4; /*!< [7..4] UART TXFIFO空中断阈值（UART TXFIFO Level-Empty
+ Threshold） */
+ uint32_t : 24;
+ } FIFOCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING0; /*!< (@ 0x00000014) UART Timing Register0 */
+
+ struct {
+ __IOM uint32_t DEAT : 16; /*!< [15..0] UART DE驱动使能时间（UART DE Assertion Timing） */
+ __IOM uint32_t DEDT : 16; /*!< [31..16] UART DE驱动禁止时间（UART DE Deassertion Timing） */
+ } TIMING0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING1; /*!< (@ 0x00000018) UART Timing Register1 */
+
+ struct {
+ __IOM uint32_t RDET : 16; /*!< [15..0] UART RE到DE切换时间（UART RE2DE Turn-Around Timing） */
+ __IOM uint32_t DRET : 16; /*!< [31..16] UART DE到RE切换时间（UART DE2RE Turn-Around Timing） */
+ } TIMING1_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t TDR; /*!< (@ 0x00000020) UART Transmit Data Register */
+
+ struct {
+ __IOM uint32_t TD : 9; /*!< [8..0] UART TX数据寄存器（UART Transmit Data Register） */
+ uint32_t : 23;
+ } TDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000024) UART Receive Data Register */
+
+ struct {
+ __IM uint32_t RD : 9; /*!< [8..0] UART RX数据寄存器（UART Receive Data Register） */
+ __IM uint32_t PRST : 1; /*!< [9..9] UART RX奇偶校验位状态（UART RX Parity Status） */
+ __IM uint32_t FMST : 1; /*!< [10..10] UART RX帧状态（UART RX Frame Status） */
+ uint32_t : 5;
+ __IOM uint32_t OVDA : 11; /*!< [26..16] UART RX上溢数据寄存器（UART RX OVER DATA） */
+ uint32_t : 5;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR; /*!< (@ 0x00000028) UART Transmit Address Register */
+
+ struct {
+ __IOM uint32_t TAR : 8; /*!< [7..0] UART TX发送地址寄存器（UART Transmit Address
+ Register） */
+ uint32_t : 24;
+ } TAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RAR; /*!< (@ 0x0000002C) UART Receive Address Register */
+
+ struct {
+ __IOM uint32_t RAR : 8; /*!< [7..0] UART RX接收地址寄存器（UART Receive Address Register） */
+ uint32_t : 24;
+ } RAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RTO; /*!< (@ 0x00000030) UART Receiver Timeout Register */
+
+ struct {
+ __IOM uint32_t RTO : 16; /*!< [15..0] UART RX超时阈值（Receiver Timeout Timing） */
+ uint32_t : 16;
+ } RTO_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTEN; /*!< (@ 0x00000034) UART Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RFIE : 1; /*!< [0..0] UART RX-FIFO满中断使能（UART RX-FIFO Full Interrupt
+ Enable） */
+ __IOM uint32_t TEIE : 1; /*!< [1..1] UART TX-FIFO空中断使能（UART TX-FIFO Empty Interrupt
+ Enable） */
+ __IOM uint32_t ROIE : 1; /*!< [2..2] UART RX-FIFO上溢中断使能（UART RX-FIFO Overflow
+ Interrupt Enable） */
+ __IOM uint32_t RUIE : 1; /*!< [3..3] UART RX-FIFO下溢中断使能（UART RX-FIFO Underflow
+ Interrupt Enable） */
+ __IOM uint32_t TOIE : 1; /*!< [4..4] UART TX-FIFO上溢中断使能（UART TX-FIFO Overflow
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t IDIE : 1; /*!< [6..6] UART 空闲中断使能（UART Idle Interrupt Enable） */
+ __IOM uint32_t NOIE : 1; /*!< [7..7] UART 噪声检测中断使能（UART Noise Detection
+ Interrupt Enable） */
+ __IOM uint32_t PEIE : 1; /*!< [8..8] UART RX奇偶校验错误中断使能（UART Parity Error
+ Interrupt Enable） */
+ __IOM uint32_t FEIE : 1; /*!< [9..9] UART RX传输帧错误中断使能（UART Frame Error
+ Interrupt Enable） */
+ __IOM uint32_t BKIE : 1; /*!< [10..10] UART RX Break中断使能（UART RX Break Interrupt
+ Enable） */
+ __IOM uint32_t RTIE : 1; /*!< [11..11] UART RX传输超时中断使能（UART RX Timeout Interrupt
+ Enable） */
+ __IOM uint32_t TDIE : 1; /*!< [12..12] UART TX传输完成中断使能（UART TX Done Interrupt
+ Enable） */
+ __IOM uint32_t TBIE : 1; /*!< [13..13] UART TX Break完成中断使能（UART TX Break Done
+ Interrupt Enable） */
+ __IOM uint32_t IDLE : 1; /*!< [14..14] UART TX Idle完成中断使能（UART TX Idle Done
+ Interrupt Enable） */
+ __IOM uint32_t AMIE : 1; /*!< [15..15] UART RX地址匹配中断使能（UART RX Address Match
+ Interrupt Enable） */
+ __IOM uint32_t ABRE : 1; /*!< [16..16] UART 自动波特率检测错误中断使能（UART
+ Auto Baud Rate Error Interrupt Enable） */
+ uint32_t : 15;
+ } INTEN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INT; /*!< (@ 0x00000038) UART Interrupt Register */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] UART RX-FIFO阈值满中断标志（UART RX-FIFO Level-Full
+ Interrupt Flag） */
+ __IM uint32_t TXEI : 1; /*!< [1..1] UART TX-FIFO阈值空中断标志（UART TX-FIFO Level-Empty
+ Interrupt Flag） */
+ __IOM uint32_t ROIF : 1; /*!< [2..2] UART RX-FIFO上溢中断标志（UART RX-FIFO Overflow
+ Interrupt Flag） */
+ __IOM uint32_t RUIF : 1; /*!< [3..3] UART RX-FIFO下溢中断标志（UART RX-FIFO Underflow
+ Interrupt Flag） */
+ __IOM uint32_t TOIF : 1; /*!< [4..4] UART TX-FIFO上溢错误中断标志（UART TX-FIFO Overflow
+ Interrupt Flag） */
+ uint32_t : 1;
+ __IOM uint32_t IDIF : 1; /*!< [6..6] UART空闲中断标志（UART Idle Interrupt Flag） */
+ __IOM uint32_t NOIF : 1; /*!< [7..7] UART 噪声检测中断标志（UART Noise Detection
+ Interrupt Flag） */
+ __IOM uint32_t PEIF : 1; /*!< [8..8] UART奇偶校验错误中断标志（UART Parity Error
+ Interrupt Flag） */
+ __IOM uint32_t FEIF : 1; /*!< [9..9] UART RX帧错误中断标志（UART Frame Error Interrupt
+ Flag） */
+ __IOM uint32_t BKIF : 1; /*!< [10..10] UART RX BREAK中断标志（UART Break Interrupt Flag） */
+ __IOM uint32_t RTOI : 1; /*!< [11..11] UART RX传输超时中断标志（UART RX Timeout Interrupt
+ Flag） */
+ __IOM uint32_t TDIF : 1; /*!< [12..12] UART发送完成中断标志（UART TX Done Interrupt
+ Flag） */
+ __IOM uint32_t TBIF : 1; /*!< [13..13] UART TX Break完成中断标志（UART TX Break Done
+ Interrupt Flag） */
+ __IOM uint32_t IDLF : 1; /*!< [14..14] UART TX Idle完成中断标志（UART TX Idle Done
+ Interrupt Flag） */
+ __IOM uint32_t AMIF : 1; /*!< [15..15] UART RX地址匹配中断标志（UART RX Address Match
+ Interrupt Flag） */
+ __IOM uint32_t ABRF : 1; /*!< [16..16] UART 自动波特率检测错误中断标志（UART
+ Auto Baud Rate Error Interrupt Flag） */
+ uint32_t : 15;
+ } INT_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x0000003C) UART Status Register */
+
+ struct {
+ __IM uint32_t TBSY : 1; /*!< [0..0] UART TX总线忙碌标志（UART TX Busy Flag） */
+ __IM uint32_t TFE : 1; /*!< [1..1] UART TX发送FIFO空标志（UART TX-FIFO Empty Flag） */
+ __IM uint32_t TFF : 1; /*!< [2..2] UART TX发送FIFO满标志（UART TX-FIFO Full Flag） */
+ __IM uint32_t TFL : 5; /*!< [7..3] UART TX-FIFO实时剩余数据量（UART TX-FIFO Level
+ Register） */
+ __IM uint32_t RBSY : 1; /*!< [8..8] UART RX总线忙碌标志（UART RX Busy Flag） */
+ __IM uint32_t RFE : 1; /*!< [9..9] UART RX接收FIFO空标志（UART RX-FIFO Empty Flag） */
+ __IM uint32_t RFF : 1; /*!< [10..10] UART RX接收FIFO满标志（UART RX-FIFO Full Flag） */
+ __IM uint32_t RFL : 5; /*!< [15..11] UART RX-FIFO实时剩余数据量（UART RX-FIFO Level
+ Register） */
+ __IM uint32_t RSE : 1; /*!< [16..16] UART RX-Start错误标志位（UART RX-Start Error
+ Flag） */
+ uint32_t : 15;
+ } STATUS_b;
+ } ;
+} UART1_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART2 (UART2)
+ */
+
+typedef struct { /*!< (@ 0x40005000) UART2 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) UART Control Register0 */
+
+ struct {
+ __IOM uint32_t UE : 1; /*!< [0..0] UART使能（UART Enable） */
+ __IOM uint32_t RE : 1; /*!< [1..1] UART RX使能（UART RX Enable） */
+ __IOM uint32_t TE : 1; /*!< [2..2] UART TX使能（UART TX Enable） */
+ __IOM uint32_t RFR : 1; /*!< [3..3] UART RX-FIFO复位（UART RX-FIFO Reset） */
+ __IOM uint32_t TFR : 1; /*!< [4..4] UART TX-FIFO复位（UART TX-FIFO Reset） */
+ __IOM uint32_t DRE : 1; /*!< [5..5] UART RX-DMA使能（UART RX DMA Enable） */
+ __IOM uint32_t DTE : 1; /*!< [6..6] UART TX-DMA使能（UART TX DMA Enable） */
+ __IOM uint32_t OWE : 1; /*!< [7..7] UART单线模式使能（UART One-Wire Enable） */
+ __IOM uint32_t SWAP : 1; /*!< [8..8] UART TX和RX引脚交换使能（UART TX/RX Swap Enable） */
+ __IOM uint32_t RPOL : 1; /*!< [9..9] UART RX引脚极性选择（UART RX Polarity Select） */
+ __IOM uint32_t TPOL : 1; /*!< [10..10] UART TX引脚极性选择（UART TX Polarity Select） */
+ __IOM uint32_t RTOE : 1; /*!< [11..11] UART RX超时使能（UART RX Timeout Enable） */
+ __IOM uint32_t OVER8 : 1; /*!< [12..12] UART过采样模式选择 (UART Oversampling Mode Select) */
+ __IOM uint32_t NFE : 1; /*!< [13..13] UART非FIFO模式使能 (UART Non-FIFO Mode Enable) */
+ __IOM uint32_t RTOM : 1; /*!< [14..14] UART RTO模式选择 (UART RTO Mode Select) */
+ __IOM uint32_t ONEBIT : 1; /*!< [15..15] UART ONEBIT模式选择 (UART ONEBIT Mode Select) */
+ __IOM uint32_t LOOP : 1; /*!< [16..16] UART LOOPBACK模式选择 (UART LOOPBACK Mode Select) */
+ __IOM uint32_t OVDIS : 1; /*!< [17..17] UART RX-OVERDIS模式使能 (UART RX OVERDIS Enable) */
+ uint32_t : 2;
+ __IOM uint32_t ABRM : 2; /*!< [21..20] UART自动波特率检测模式（UART Auto Baud Rate
+ Mode） */
+ uint32_t : 10;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) UART Control Register1 */
+
+ struct {
+ __IOM uint32_t LEN : 2; /*!< [1..0] UART数据长度选择（UART Length Select） */
+ __IOM uint32_t STP : 1; /*!< [2..2] UART Stop位选择（UART Stop Select） */
+ __IOM uint32_t PEN : 1; /*!< [3..3] UART奇偶检验位使能（UART Parity Enable） */
+ __IOM uint32_t PSEL : 1; /*!< [4..4] UART奇偶检验选择（UART Parity Select） */
+ __IOM uint32_t SPE : 1; /*!< [5..5] UART强制校验使能位（UART Stick Parity Enable） */
+ uint32_t : 1;
+ __IOM uint32_t MSB : 1; /*!< [7..7] UART MSB使能（UART MSB Enable） */
+ __IOM uint32_t RS485E : 1; /*!< [8..8] UART RS485 功能使能（UART RS485 Enable） */
+ __IOM uint32_t REP : 1; /*!< [9..9] UART RE极性（UART RE Polarity） */
+ __IOM uint32_t DEP : 1; /*!< [10..10] UART DE极性（UART DE Polarity） */
+ uint32_t : 5;
+ __IOM uint32_t EBE : 1; /*!< [16..16] UART拓展位使能（UART Extend-Bit Enable） */
+ __IOM uint32_t REM : 1; /*!< [17..17] UART RX拓展模式选择（UART RX Extend-Mode Select） */
+ __IOM uint32_t TEM : 1; /*!< [18..18] UART TX拓展模式选择（UART TX Extend-Mode Select） */
+ __IOM uint32_t BKR : 1; /*!< [19..19] UART Break帧请求位（UART Break Request） */
+ __IOM uint32_t IDR : 1; /*!< [20..20] UART IDLE帧请求位（UART IDLE Request） */
+ __IOM uint32_t ABR : 1; /*!< [21..21] UART自动波特率检测使能（UART Auto Baud Rate
+ Enable） */
+ uint32_t : 10;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) UART Baud Rate Register */
+
+ struct {
+ __IOM uint32_t BAUD : 16; /*!< [15..0] UART波特率配置（UART Baud Rate） */
+ uint32_t : 16;
+ } BAUD_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) UART FIFO Control Register */
+
+ struct {
+ __IOM uint32_t RXFT : 4; /*!< [3..0] UART RXFIFO满中断阈值（UART RX-FIFO Level-Full
+ Threshold） */
+ __IOM uint32_t TXFT : 4; /*!< [7..4] UART TXFIFO空中断阈值（UART TXFIFO Level-Empty
+ Threshold） */
+ uint32_t : 24;
+ } FIFOCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING0; /*!< (@ 0x00000014) UART Timing Register0 */
+
+ struct {
+ __IOM uint32_t DEAT : 16; /*!< [15..0] UART DE驱动使能时间（UART DE Assertion Timing） */
+ __IOM uint32_t DEDT : 16; /*!< [31..16] UART DE驱动禁止时间（UART DE Deassertion Timing） */
+ } TIMING0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING1; /*!< (@ 0x00000018) UART Timing Register1 */
+
+ struct {
+ __IOM uint32_t RDET : 16; /*!< [15..0] UART RE到DE切换时间（UART RE2DE Turn-Around Timing） */
+ __IOM uint32_t DRET : 16; /*!< [31..16] UART DE到RE切换时间（UART DE2RE Turn-Around Timing） */
+ } TIMING1_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t TDR; /*!< (@ 0x00000020) UART Transmit Data Register */
+
+ struct {
+ __IOM uint32_t TD : 9; /*!< [8..0] UART TX数据寄存器（UART Transmit Data Register） */
+ uint32_t : 23;
+ } TDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000024) UART Receive Data Register */
+
+ struct {
+ __IM uint32_t RD : 9; /*!< [8..0] UART RX数据寄存器（UART Receive Data Register） */
+ __IM uint32_t PRST : 1; /*!< [9..9] UART RX奇偶校验位状态（UART RX Parity Status） */
+ __IM uint32_t FMST : 1; /*!< [10..10] UART RX帧状态（UART RX Frame Status） */
+ uint32_t : 5;
+ __IOM uint32_t OVDA : 11; /*!< [26..16] UART RX上溢数据寄存器（UART RX OVER DATA） */
+ uint32_t : 5;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR; /*!< (@ 0x00000028) UART Transmit Address Register */
+
+ struct {
+ __IOM uint32_t TAR : 8; /*!< [7..0] UART TX发送地址寄存器（UART Transmit Address
+ Register） */
+ uint32_t : 24;
+ } TAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RAR; /*!< (@ 0x0000002C) UART Receive Address Register */
+
+ struct {
+ __IOM uint32_t RAR : 8; /*!< [7..0] UART RX接收地址寄存器（UART Receive Address Register） */
+ uint32_t : 24;
+ } RAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RTO; /*!< (@ 0x00000030) UART Receiver Timeout Register */
+
+ struct {
+ __IOM uint32_t RTO : 16; /*!< [15..0] UART RX超时阈值（Receiver Timeout Timing） */
+ uint32_t : 16;
+ } RTO_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTEN; /*!< (@ 0x00000034) UART Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RFIE : 1; /*!< [0..0] UART RX-FIFO满中断使能（UART RX-FIFO Full Interrupt
+ Enable） */
+ __IOM uint32_t TEIE : 1; /*!< [1..1] UART TX-FIFO空中断使能（UART TX-FIFO Empty Interrupt
+ Enable） */
+ __IOM uint32_t ROIE : 1; /*!< [2..2] UART RX-FIFO上溢中断使能（UART RX-FIFO Overflow
+ Interrupt Enable） */
+ __IOM uint32_t RUIE : 1; /*!< [3..3] UART RX-FIFO下溢中断使能（UART RX-FIFO Underflow
+ Interrupt Enable） */
+ __IOM uint32_t TOIE : 1; /*!< [4..4] UART TX-FIFO上溢中断使能（UART TX-FIFO Overflow
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t IDIE : 1; /*!< [6..6] UART 空闲中断使能（UART Idle Interrupt Enable） */
+ __IOM uint32_t NOIE : 1; /*!< [7..7] UART 噪声检测中断使能（UART Noise Detection
+ Interrupt Enable） */
+ __IOM uint32_t PEIE : 1; /*!< [8..8] UART RX奇偶校验错误中断使能（UART Parity Error
+ Interrupt Enable） */
+ __IOM uint32_t FEIE : 1; /*!< [9..9] UART RX传输帧错误中断使能（UART Frame Error
+ Interrupt Enable） */
+ __IOM uint32_t BKIE : 1; /*!< [10..10] UART RX Break中断使能（UART RX Break Interrupt
+ Enable） */
+ __IOM uint32_t RTIE : 1; /*!< [11..11] UART RX传输超时中断使能（UART RX Timeout Interrupt
+ Enable） */
+ __IOM uint32_t TDIE : 1; /*!< [12..12] UART TX传输完成中断使能（UART TX Done Interrupt
+ Enable） */
+ __IOM uint32_t TBIE : 1; /*!< [13..13] UART TX Break完成中断使能（UART TX Break Done
+ Interrupt Enable） */
+ __IOM uint32_t IDLE : 1; /*!< [14..14] UART TX Idle完成中断使能（UART TX Idle Done
+ Interrupt Enable） */
+ __IOM uint32_t AMIE : 1; /*!< [15..15] UART RX地址匹配中断使能（UART RX Address Match
+ Interrupt Enable） */
+ __IOM uint32_t ABRE : 1; /*!< [16..16] UART 自动波特率检测错误中断使能（UART
+ Auto Baud Rate Error Interrupt Enable） */
+ uint32_t : 15;
+ } INTEN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INT; /*!< (@ 0x00000038) UART Interrupt Register */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] UART RX-FIFO阈值满中断标志（UART RX-FIFO Level-Full
+ Interrupt Flag） */
+ __IM uint32_t TXEI : 1; /*!< [1..1] UART TX-FIFO阈值空中断标志（UART TX-FIFO Level-Empty
+ Interrupt Flag） */
+ __IOM uint32_t ROIF : 1; /*!< [2..2] UART RX-FIFO上溢中断标志（UART RX-FIFO Overflow
+ Interrupt Flag） */
+ __IOM uint32_t RUIF : 1; /*!< [3..3] UART RX-FIFO下溢中断标志（UART RX-FIFO Underflow
+ Interrupt Flag） */
+ __IOM uint32_t TOIF : 1; /*!< [4..4] UART TX-FIFO上溢错误中断标志（UART TX-FIFO Overflow
+ Interrupt Flag） */
+ uint32_t : 1;
+ __IOM uint32_t IDIF : 1; /*!< [6..6] UART空闲中断标志（UART Idle Interrupt Flag） */
+ __IOM uint32_t NOIF : 1; /*!< [7..7] UART 噪声检测中断标志（UART Noise Detection
+ Interrupt Flag） */
+ __IOM uint32_t PEIF : 1; /*!< [8..8] UART奇偶校验错误中断标志（UART Parity Error
+ Interrupt Flag） */
+ __IOM uint32_t FEIF : 1; /*!< [9..9] UART RX帧错误中断标志（UART Frame Error Interrupt
+ Flag） */
+ __IOM uint32_t BKIF : 1; /*!< [10..10] UART RX BREAK中断标志（UART Break Interrupt Flag） */
+ __IOM uint32_t RTOI : 1; /*!< [11..11] UART RX传输超时中断标志（UART RX Timeout Interrupt
+ Flag） */
+ __IOM uint32_t TDIF : 1; /*!< [12..12] UART发送完成中断标志（UART TX Done Interrupt
+ Flag） */
+ __IOM uint32_t TBIF : 1; /*!< [13..13] UART TX Break完成中断标志（UART TX Break Done
+ Interrupt Flag） */
+ __IOM uint32_t IDLF : 1; /*!< [14..14] UART TX Idle完成中断标志（UART TX Idle Done
+ Interrupt Flag） */
+ __IOM uint32_t AMIF : 1; /*!< [15..15] UART RX地址匹配中断标志（UART RX Address Match
+ Interrupt Flag） */
+ __IOM uint32_t ABRF : 1; /*!< [16..16] UART 自动波特率检测错误中断标志（UART
+ Auto Baud Rate Error Interrupt Flag） */
+ uint32_t : 15;
+ } INT_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x0000003C) UART Status Register */
+
+ struct {
+ __IM uint32_t TBSY : 1; /*!< [0..0] UART TX总线忙碌标志（UART TX Busy Flag） */
+ __IM uint32_t TFE : 1; /*!< [1..1] UART TX发送FIFO空标志（UART TX-FIFO Empty Flag） */
+ __IM uint32_t TFF : 1; /*!< [2..2] UART TX发送FIFO满标志（UART TX-FIFO Full Flag） */
+ __IM uint32_t TFL : 5; /*!< [7..3] UART TX-FIFO实时剩余数据量（UART TX-FIFO Level
+ Register） */
+ __IM uint32_t RBSY : 1; /*!< [8..8] UART RX总线忙碌标志（UART RX Busy Flag） */
+ __IM uint32_t RFE : 1; /*!< [9..9] UART RX接收FIFO空标志（UART RX-FIFO Empty Flag） */
+ __IM uint32_t RFF : 1; /*!< [10..10] UART RX接收FIFO满标志（UART RX-FIFO Full Flag） */
+ __IM uint32_t RFL : 5; /*!< [15..11] UART RX-FIFO实时剩余数据量（UART RX-FIFO Level
+ Register） */
+ __IM uint32_t RSE : 1; /*!< [16..16] UART RX-Start错误标志位（UART RX-Start Error
+ Flag） */
+ uint32_t : 15;
+ } STATUS_b;
+ } ;
+} UART2_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART3 (UART3)
+ */
+
+typedef struct { /*!< (@ 0x40010000) UART3 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) UART Control Register0 */
+
+ struct {
+ __IOM uint32_t UE : 1; /*!< [0..0] UART使能（UART Enable） */
+ __IOM uint32_t RE : 1; /*!< [1..1] UART RX使能（UART RX Enable） */
+ __IOM uint32_t TE : 1; /*!< [2..2] UART TX使能（UART TX Enable） */
+ __IOM uint32_t RFR : 1; /*!< [3..3] UART RX-FIFO复位（UART RX-FIFO Reset） */
+ __IOM uint32_t TFR : 1; /*!< [4..4] UART TX-FIFO复位（UART TX-FIFO Reset） */
+ __IOM uint32_t DRE : 1; /*!< [5..5] UART RX-DMA使能（UART RX DMA Enable） */
+ __IOM uint32_t DTE : 1; /*!< [6..6] UART TX-DMA使能（UART TX DMA Enable） */
+ __IOM uint32_t OWE : 1; /*!< [7..7] UART单线模式使能（UART One-Wire Enable） */
+ __IOM uint32_t SWAP : 1; /*!< [8..8] UART TX和RX引脚交换使能（UART TX/RX Swap Enable） */
+ __IOM uint32_t RPOL : 1; /*!< [9..9] UART RX引脚极性选择（UART RX Polarity Select） */
+ __IOM uint32_t TPOL : 1; /*!< [10..10] UART TX引脚极性选择（UART TX Polarity Select） */
+ __IOM uint32_t RTOE : 1; /*!< [11..11] UART RX超时使能（UART RX Timeout Enable） */
+ __IOM uint32_t OVER8 : 1; /*!< [12..12] UART过采样模式选择 (UART Oversampling Mode Select) */
+ __IOM uint32_t NFE : 1; /*!< [13..13] UART非FIFO模式使能 (UART Non-FIFO Mode Enable) */
+ __IOM uint32_t RTOM : 1; /*!< [14..14] UART RTO模式选择 (UART RTO Mode Select) */
+ __IOM uint32_t ONEBIT : 1; /*!< [15..15] UART ONEBIT模式选择 (UART ONEBIT Mode Select) */
+ __IOM uint32_t LOOP : 1; /*!< [16..16] UART LOOPBACK模式选择 (UART LOOPBACK Mode Select) */
+ __IOM uint32_t OVDIS : 1; /*!< [17..17] UART RX-OVERDIS模式使能 (UART RX OVERDIS Enable) */
+ uint32_t : 2;
+ __IOM uint32_t ABRM : 2; /*!< [21..20] UART自动波特率检测模式（UART Auto Baud Rate
+ Mode） */
+ uint32_t : 10;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) UART Control Register1 */
+
+ struct {
+ __IOM uint32_t LEN : 2; /*!< [1..0] UART数据长度选择（UART Length Select） */
+ __IOM uint32_t STP : 1; /*!< [2..2] UART Stop位选择（UART Stop Select） */
+ __IOM uint32_t PEN : 1; /*!< [3..3] UART奇偶检验位使能（UART Parity Enable） */
+ __IOM uint32_t PSEL : 1; /*!< [4..4] UART奇偶检验选择（UART Parity Select） */
+ __IOM uint32_t SPE : 1; /*!< [5..5] UART强制校验使能位（UART Stick Parity Enable） */
+ uint32_t : 1;
+ __IOM uint32_t MSB : 1; /*!< [7..7] UART MSB使能（UART MSB Enable） */
+ __IOM uint32_t RS485E : 1; /*!< [8..8] UART RS485 功能使能（UART RS485 Enable） */
+ __IOM uint32_t REP : 1; /*!< [9..9] UART RE极性（UART RE Polarity） */
+ __IOM uint32_t DEP : 1; /*!< [10..10] UART DE极性（UART DE Polarity） */
+ uint32_t : 5;
+ __IOM uint32_t EBE : 1; /*!< [16..16] UART拓展位使能（UART Extend-Bit Enable） */
+ __IOM uint32_t REM : 1; /*!< [17..17] UART RX拓展模式选择（UART RX Extend-Mode Select） */
+ __IOM uint32_t TEM : 1; /*!< [18..18] UART TX拓展模式选择（UART TX Extend-Mode Select） */
+ __IOM uint32_t BKR : 1; /*!< [19..19] UART Break帧请求位（UART Break Request） */
+ __IOM uint32_t IDR : 1; /*!< [20..20] UART IDLE帧请求位（UART IDLE Request） */
+ __IOM uint32_t ABR : 1; /*!< [21..21] UART自动波特率检测使能（UART Auto Baud Rate
+ Enable） */
+ uint32_t : 10;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) UART Baud Rate Register */
+
+ struct {
+ __IOM uint32_t BAUD : 16; /*!< [15..0] UART波特率配置（UART Baud Rate） */
+ uint32_t : 16;
+ } BAUD_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) UART FIFO Control Register */
+
+ struct {
+ __IOM uint32_t RXFT : 4; /*!< [3..0] UART RXFIFO满中断阈值（UART RX-FIFO Level-Full
+ Threshold） */
+ __IOM uint32_t TXFT : 4; /*!< [7..4] UART TXFIFO空中断阈值（UART TXFIFO Level-Empty
+ Threshold） */
+ uint32_t : 24;
+ } FIFOCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING0; /*!< (@ 0x00000014) UART Timing Register0 */
+
+ struct {
+ __IOM uint32_t DEAT : 16; /*!< [15..0] UART DE驱动使能时间（UART DE Assertion Timing） */
+ __IOM uint32_t DEDT : 16; /*!< [31..16] UART DE驱动禁止时间（UART DE Deassertion Timing） */
+ } TIMING0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING1; /*!< (@ 0x00000018) UART Timing Register1 */
+
+ struct {
+ __IOM uint32_t RDET : 16; /*!< [15..0] UART RE到DE切换时间（UART RE2DE Turn-Around Timing） */
+ __IOM uint32_t DRET : 16; /*!< [31..16] UART DE到RE切换时间（UART DE2RE Turn-Around Timing） */
+ } TIMING1_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t TDR; /*!< (@ 0x00000020) UART Transmit Data Register */
+
+ struct {
+ __IOM uint32_t TD : 9; /*!< [8..0] UART TX数据寄存器（UART Transmit Data Register） */
+ uint32_t : 23;
+ } TDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000024) UART Receive Data Register */
+
+ struct {
+ __IM uint32_t RD : 9; /*!< [8..0] UART RX数据寄存器（UART Receive Data Register） */
+ __IM uint32_t PRST : 1; /*!< [9..9] UART RX奇偶校验位状态（UART RX Parity Status） */
+ __IM uint32_t FMST : 1; /*!< [10..10] UART RX帧状态（UART RX Frame Status） */
+ uint32_t : 5;
+ __IOM uint32_t OVDA : 11; /*!< [26..16] UART RX上溢数据寄存器（UART RX OVER DATA） */
+ uint32_t : 5;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR; /*!< (@ 0x00000028) UART Transmit Address Register */
+
+ struct {
+ __IOM uint32_t TAR : 8; /*!< [7..0] UART TX发送地址寄存器（UART Transmit Address
+ Register） */
+ uint32_t : 24;
+ } TAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RAR; /*!< (@ 0x0000002C) UART Receive Address Register */
+
+ struct {
+ __IOM uint32_t RAR : 8; /*!< [7..0] UART RX接收地址寄存器（UART Receive Address Register） */
+ uint32_t : 24;
+ } RAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RTO; /*!< (@ 0x00000030) UART Receiver Timeout Register */
+
+ struct {
+ __IOM uint32_t RTO : 16; /*!< [15..0] UART RX超时阈值（Receiver Timeout Timing） */
+ uint32_t : 16;
+ } RTO_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTEN; /*!< (@ 0x00000034) UART Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RFIE : 1; /*!< [0..0] UART RX-FIFO满中断使能（UART RX-FIFO Full Interrupt
+ Enable） */
+ __IOM uint32_t TEIE : 1; /*!< [1..1] UART TX-FIFO空中断使能（UART TX-FIFO Empty Interrupt
+ Enable） */
+ __IOM uint32_t ROIE : 1; /*!< [2..2] UART RX-FIFO上溢中断使能（UART RX-FIFO Overflow
+ Interrupt Enable） */
+ __IOM uint32_t RUIE : 1; /*!< [3..3] UART RX-FIFO下溢中断使能（UART RX-FIFO Underflow
+ Interrupt Enable） */
+ __IOM uint32_t TOIE : 1; /*!< [4..4] UART TX-FIFO上溢中断使能（UART TX-FIFO Overflow
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t IDIE : 1; /*!< [6..6] UART 空闲中断使能（UART Idle Interrupt Enable） */
+ __IOM uint32_t NOIE : 1; /*!< [7..7] UART 噪声检测中断使能（UART Noise Detection
+ Interrupt Enable） */
+ __IOM uint32_t PEIE : 1; /*!< [8..8] UART RX奇偶校验错误中断使能（UART Parity Error
+ Interrupt Enable） */
+ __IOM uint32_t FEIE : 1; /*!< [9..9] UART RX传输帧错误中断使能（UART Frame Error
+ Interrupt Enable） */
+ __IOM uint32_t BKIE : 1; /*!< [10..10] UART RX Break中断使能（UART RX Break Interrupt
+ Enable） */
+ __IOM uint32_t RTIE : 1; /*!< [11..11] UART RX传输超时中断使能（UART RX Timeout Interrupt
+ Enable） */
+ __IOM uint32_t TDIE : 1; /*!< [12..12] UART TX传输完成中断使能（UART TX Done Interrupt
+ Enable） */
+ __IOM uint32_t TBIE : 1; /*!< [13..13] UART TX Break完成中断使能（UART TX Break Done
+ Interrupt Enable） */
+ __IOM uint32_t IDLE : 1; /*!< [14..14] UART TX Idle完成中断使能（UART TX Idle Done
+ Interrupt Enable） */
+ __IOM uint32_t AMIE : 1; /*!< [15..15] UART RX地址匹配中断使能（UART RX Address Match
+ Interrupt Enable） */
+ __IOM uint32_t ABRE : 1; /*!< [16..16] UART 自动波特率检测错误中断使能（UART
+ Auto Baud Rate Error Interrupt Enable） */
+ uint32_t : 15;
+ } INTEN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INT; /*!< (@ 0x00000038) UART Interrupt Register */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] UART RX-FIFO阈值满中断标志（UART RX-FIFO Level-Full
+ Interrupt Flag） */
+ __IM uint32_t TXEI : 1; /*!< [1..1] UART TX-FIFO阈值空中断标志（UART TX-FIFO Level-Empty
+ Interrupt Flag） */
+ __IOM uint32_t ROIF : 1; /*!< [2..2] UART RX-FIFO上溢中断标志（UART RX-FIFO Overflow
+ Interrupt Flag） */
+ __IOM uint32_t RUIF : 1; /*!< [3..3] UART RX-FIFO下溢中断标志（UART RX-FIFO Underflow
+ Interrupt Flag） */
+ __IOM uint32_t TOIF : 1; /*!< [4..4] UART TX-FIFO上溢错误中断标志（UART TX-FIFO Overflow
+ Interrupt Flag） */
+ uint32_t : 1;
+ __IOM uint32_t IDIF : 1; /*!< [6..6] UART空闲中断标志（UART Idle Interrupt Flag） */
+ __IOM uint32_t NOIF : 1; /*!< [7..7] UART 噪声检测中断标志（UART Noise Detection
+ Interrupt Flag） */
+ __IOM uint32_t PEIF : 1; /*!< [8..8] UART奇偶校验错误中断标志（UART Parity Error
+ Interrupt Flag） */
+ __IOM uint32_t FEIF : 1; /*!< [9..9] UART RX帧错误中断标志（UART Frame Error Interrupt
+ Flag） */
+ __IOM uint32_t BKIF : 1; /*!< [10..10] UART RX BREAK中断标志（UART Break Interrupt Flag） */
+ __IOM uint32_t RTOI : 1; /*!< [11..11] UART RX传输超时中断标志（UART RX Timeout Interrupt
+ Flag） */
+ __IOM uint32_t TDIF : 1; /*!< [12..12] UART发送完成中断标志（UART TX Done Interrupt
+ Flag） */
+ __IOM uint32_t TBIF : 1; /*!< [13..13] UART TX Break完成中断标志（UART TX Break Done
+ Interrupt Flag） */
+ __IOM uint32_t IDLF : 1; /*!< [14..14] UART TX Idle完成中断标志（UART TX Idle Done
+ Interrupt Flag） */
+ __IOM uint32_t AMIF : 1; /*!< [15..15] UART RX地址匹配中断标志（UART RX Address Match
+ Interrupt Flag） */
+ __IOM uint32_t ABRF : 1; /*!< [16..16] UART 自动波特率检测错误中断标志（UART
+ Auto Baud Rate Error Interrupt Flag） */
+ uint32_t : 15;
+ } INT_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x0000003C) UART Status Register */
+
+ struct {
+ __IM uint32_t TBSY : 1; /*!< [0..0] UART TX总线忙碌标志（UART TX Busy Flag） */
+ __IM uint32_t TFE : 1; /*!< [1..1] UART TX发送FIFO空标志（UART TX-FIFO Empty Flag） */
+ __IM uint32_t TFF : 1; /*!< [2..2] UART TX发送FIFO满标志（UART TX-FIFO Full Flag） */
+ __IM uint32_t TFL : 5; /*!< [7..3] UART TX-FIFO实时剩余数据量（UART TX-FIFO Level
+ Register） */
+ __IM uint32_t RBSY : 1; /*!< [8..8] UART RX总线忙碌标志（UART RX Busy Flag） */
+ __IM uint32_t RFE : 1; /*!< [9..9] UART RX接收FIFO空标志（UART RX-FIFO Empty Flag） */
+ __IM uint32_t RFF : 1; /*!< [10..10] UART RX接收FIFO满标志（UART RX-FIFO Full Flag） */
+ __IM uint32_t RFL : 5; /*!< [15..11] UART RX-FIFO实时剩余数据量（UART RX-FIFO Level
+ Register） */
+ __IM uint32_t RSE : 1; /*!< [16..16] UART RX-Start错误标志位（UART RX-Start Error
+ Flag） */
+ uint32_t : 15;
+ } STATUS_b;
+ } ;
+} UART3_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART4 (UART4)
+ */
+
+typedef struct { /*!< (@ 0x40011000) UART4 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) UART Control Register0 */
+
+ struct {
+ __IOM uint32_t UE : 1; /*!< [0..0] UART使能（UART Enable） */
+ __IOM uint32_t RE : 1; /*!< [1..1] UART RX使能（UART RX Enable） */
+ __IOM uint32_t TE : 1; /*!< [2..2] UART TX使能（UART TX Enable） */
+ __IOM uint32_t RFR : 1; /*!< [3..3] UART RX-FIFO复位（UART RX-FIFO Reset） */
+ __IOM uint32_t TFR : 1; /*!< [4..4] UART TX-FIFO复位（UART TX-FIFO Reset） */
+ __IOM uint32_t DRE : 1; /*!< [5..5] UART RX-DMA使能（UART RX DMA Enable） */
+ __IOM uint32_t DTE : 1; /*!< [6..6] UART TX-DMA使能（UART TX DMA Enable） */
+ __IOM uint32_t OWE : 1; /*!< [7..7] UART单线模式使能（UART One-Wire Enable） */
+ __IOM uint32_t SWAP : 1; /*!< [8..8] UART TX和RX引脚交换使能（UART TX/RX Swap Enable） */
+ __IOM uint32_t RPOL : 1; /*!< [9..9] UART RX引脚极性选择（UART RX Polarity Select） */
+ __IOM uint32_t TPOL : 1; /*!< [10..10] UART TX引脚极性选择（UART TX Polarity Select） */
+ __IOM uint32_t RTOE : 1; /*!< [11..11] UART RX超时使能（UART RX Timeout Enable） */
+ __IOM uint32_t OVER8 : 1; /*!< [12..12] UART过采样模式选择 (UART Oversampling Mode Select) */
+ __IOM uint32_t NFE : 1; /*!< [13..13] UART非FIFO模式使能 (UART Non-FIFO Mode Enable) */
+ __IOM uint32_t RTOM : 1; /*!< [14..14] UART RTO模式选择 (UART RTO Mode Select) */
+ __IOM uint32_t ONEBIT : 1; /*!< [15..15] UART ONEBIT模式选择 (UART ONEBIT Mode Select) */
+ __IOM uint32_t LOOP : 1; /*!< [16..16] UART LOOPBACK模式选择 (UART LOOPBACK Mode Select) */
+ __IOM uint32_t OVDIS : 1; /*!< [17..17] UART RX-OVERDIS模式使能 (UART RX OVERDIS Enable) */
+ uint32_t : 2;
+ __IOM uint32_t ABRM : 2; /*!< [21..20] UART自动波特率检测模式（UART Auto Baud Rate
+ Mode） */
+ uint32_t : 10;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) UART Control Register1 */
+
+ struct {
+ __IOM uint32_t LEN : 2; /*!< [1..0] UART数据长度选择（UART Length Select） */
+ __IOM uint32_t STP : 1; /*!< [2..2] UART Stop位选择（UART Stop Select） */
+ __IOM uint32_t PEN : 1; /*!< [3..3] UART奇偶检验位使能（UART Parity Enable） */
+ __IOM uint32_t PSEL : 1; /*!< [4..4] UART奇偶检验选择（UART Parity Select） */
+ __IOM uint32_t SPE : 1; /*!< [5..5] UART强制校验使能位（UART Stick Parity Enable） */
+ uint32_t : 1;
+ __IOM uint32_t MSB : 1; /*!< [7..7] UART MSB使能（UART MSB Enable） */
+ __IOM uint32_t RS485E : 1; /*!< [8..8] UART RS485 功能使能（UART RS485 Enable） */
+ __IOM uint32_t REP : 1; /*!< [9..9] UART RE极性（UART RE Polarity） */
+ __IOM uint32_t DEP : 1; /*!< [10..10] UART DE极性（UART DE Polarity） */
+ uint32_t : 5;
+ __IOM uint32_t EBE : 1; /*!< [16..16] UART拓展位使能（UART Extend-Bit Enable） */
+ __IOM uint32_t REM : 1; /*!< [17..17] UART RX拓展模式选择（UART RX Extend-Mode Select） */
+ __IOM uint32_t TEM : 1; /*!< [18..18] UART TX拓展模式选择（UART TX Extend-Mode Select） */
+ __IOM uint32_t BKR : 1; /*!< [19..19] UART Break帧请求位（UART Break Request） */
+ __IOM uint32_t IDR : 1; /*!< [20..20] UART IDLE帧请求位（UART IDLE Request） */
+ __IOM uint32_t ABR : 1; /*!< [21..21] UART自动波特率检测使能（UART Auto Baud Rate
+ Enable） */
+ uint32_t : 10;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) UART Baud Rate Register */
+
+ struct {
+ __IOM uint32_t BAUD : 16; /*!< [15..0] UART波特率配置（UART Baud Rate） */
+ uint32_t : 16;
+ } BAUD_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) UART FIFO Control Register */
+
+ struct {
+ __IOM uint32_t RXFT : 4; /*!< [3..0] UART RXFIFO满中断阈值（UART RX-FIFO Level-Full
+ Threshold） */
+ __IOM uint32_t TXFT : 4; /*!< [7..4] UART TXFIFO空中断阈值（UART TXFIFO Level-Empty
+ Threshold） */
+ uint32_t : 24;
+ } FIFOCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING0; /*!< (@ 0x00000014) UART Timing Register0 */
+
+ struct {
+ __IOM uint32_t DEAT : 16; /*!< [15..0] UART DE驱动使能时间（UART DE Assertion Timing） */
+ __IOM uint32_t DEDT : 16; /*!< [31..16] UART DE驱动禁止时间（UART DE Deassertion Timing） */
+ } TIMING0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING1; /*!< (@ 0x00000018) UART Timing Register1 */
+
+ struct {
+ __IOM uint32_t RDET : 16; /*!< [15..0] UART RE到DE切换时间（UART RE2DE Turn-Around Timing） */
+ __IOM uint32_t DRET : 16; /*!< [31..16] UART DE到RE切换时间（UART DE2RE Turn-Around Timing） */
+ } TIMING1_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t TDR; /*!< (@ 0x00000020) UART Transmit Data Register */
+
+ struct {
+ __IOM uint32_t TD : 9; /*!< [8..0] UART TX数据寄存器（UART Transmit Data Register） */
+ uint32_t : 23;
+ } TDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000024) UART Receive Data Register */
+
+ struct {
+ __IM uint32_t RD : 9; /*!< [8..0] UART RX数据寄存器（UART Receive Data Register） */
+ __IM uint32_t PRST : 1; /*!< [9..9] UART RX奇偶校验位状态（UART RX Parity Status） */
+ __IM uint32_t FMST : 1; /*!< [10..10] UART RX帧状态（UART RX Frame Status） */
+ uint32_t : 5;
+ __IOM uint32_t OVDA : 11; /*!< [26..16] UART RX上溢数据寄存器（UART RX OVER DATA） */
+ uint32_t : 5;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR; /*!< (@ 0x00000028) UART Transmit Address Register */
+
+ struct {
+ __IOM uint32_t TAR : 8; /*!< [7..0] UART TX发送地址寄存器（UART Transmit Address
+ Register） */
+ uint32_t : 24;
+ } TAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RAR; /*!< (@ 0x0000002C) UART Receive Address Register */
+
+ struct {
+ __IOM uint32_t RAR : 8; /*!< [7..0] UART RX接收地址寄存器（UART Receive Address Register） */
+ uint32_t : 24;
+ } RAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RTO; /*!< (@ 0x00000030) UART Receiver Timeout Register */
+
+ struct {
+ __IOM uint32_t RTO : 16; /*!< [15..0] UART RX超时阈值（Receiver Timeout Timing） */
+ uint32_t : 16;
+ } RTO_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTEN; /*!< (@ 0x00000034) UART Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RFIE : 1; /*!< [0..0] UART RX-FIFO满中断使能（UART RX-FIFO Full Interrupt
+ Enable） */
+ __IOM uint32_t TEIE : 1; /*!< [1..1] UART TX-FIFO空中断使能（UART TX-FIFO Empty Interrupt
+ Enable） */
+ __IOM uint32_t ROIE : 1; /*!< [2..2] UART RX-FIFO上溢中断使能（UART RX-FIFO Overflow
+ Interrupt Enable） */
+ __IOM uint32_t RUIE : 1; /*!< [3..3] UART RX-FIFO下溢中断使能（UART RX-FIFO Underflow
+ Interrupt Enable） */
+ __IOM uint32_t TOIE : 1; /*!< [4..4] UART TX-FIFO上溢中断使能（UART TX-FIFO Overflow
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t IDIE : 1; /*!< [6..6] UART 空闲中断使能（UART Idle Interrupt Enable） */
+ __IOM uint32_t NOIE : 1; /*!< [7..7] UART 噪声检测中断使能（UART Noise Detection
+ Interrupt Enable） */
+ __IOM uint32_t PEIE : 1; /*!< [8..8] UART RX奇偶校验错误中断使能（UART Parity Error
+ Interrupt Enable） */
+ __IOM uint32_t FEIE : 1; /*!< [9..9] UART RX传输帧错误中断使能（UART Frame Error
+ Interrupt Enable） */
+ __IOM uint32_t BKIE : 1; /*!< [10..10] UART RX Break中断使能（UART RX Break Interrupt
+ Enable） */
+ __IOM uint32_t RTIE : 1; /*!< [11..11] UART RX传输超时中断使能（UART RX Timeout Interrupt
+ Enable） */
+ __IOM uint32_t TDIE : 1; /*!< [12..12] UART TX传输完成中断使能（UART TX Done Interrupt
+ Enable） */
+ __IOM uint32_t TBIE : 1; /*!< [13..13] UART TX Break完成中断使能（UART TX Break Done
+ Interrupt Enable） */
+ __IOM uint32_t IDLE : 1; /*!< [14..14] UART TX Idle完成中断使能（UART TX Idle Done
+ Interrupt Enable） */
+ __IOM uint32_t AMIE : 1; /*!< [15..15] UART RX地址匹配中断使能（UART RX Address Match
+ Interrupt Enable） */
+ __IOM uint32_t ABRE : 1; /*!< [16..16] UART 自动波特率检测错误中断使能（UART
+ Auto Baud Rate Error Interrupt Enable） */
+ uint32_t : 15;
+ } INTEN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INT; /*!< (@ 0x00000038) UART Interrupt Register */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] UART RX-FIFO阈值满中断标志（UART RX-FIFO Level-Full
+ Interrupt Flag） */
+ __IM uint32_t TXEI : 1; /*!< [1..1] UART TX-FIFO阈值空中断标志（UART TX-FIFO Level-Empty
+ Interrupt Flag） */
+ __IOM uint32_t ROIF : 1; /*!< [2..2] UART RX-FIFO上溢中断标志（UART RX-FIFO Overflow
+ Interrupt Flag） */
+ __IOM uint32_t RUIF : 1; /*!< [3..3] UART RX-FIFO下溢中断标志（UART RX-FIFO Underflow
+ Interrupt Flag） */
+ __IOM uint32_t TOIF : 1; /*!< [4..4] UART TX-FIFO上溢错误中断标志（UART TX-FIFO Overflow
+ Interrupt Flag） */
+ uint32_t : 1;
+ __IOM uint32_t IDIF : 1; /*!< [6..6] UART空闲中断标志（UART Idle Interrupt Flag） */
+ __IOM uint32_t NOIF : 1; /*!< [7..7] UART 噪声检测中断标志（UART Noise Detection
+ Interrupt Flag） */
+ __IOM uint32_t PEIF : 1; /*!< [8..8] UART奇偶校验错误中断标志（UART Parity Error
+ Interrupt Flag） */
+ __IOM uint32_t FEIF : 1; /*!< [9..9] UART RX帧错误中断标志（UART Frame Error Interrupt
+ Flag） */
+ __IOM uint32_t BKIF : 1; /*!< [10..10] UART RX BREAK中断标志（UART Break Interrupt Flag） */
+ __IOM uint32_t RTOI : 1; /*!< [11..11] UART RX传输超时中断标志（UART RX Timeout Interrupt
+ Flag） */
+ __IOM uint32_t TDIF : 1; /*!< [12..12] UART发送完成中断标志（UART TX Done Interrupt
+ Flag） */
+ __IOM uint32_t TBIF : 1; /*!< [13..13] UART TX Break完成中断标志（UART TX Break Done
+ Interrupt Flag） */
+ __IOM uint32_t IDLF : 1; /*!< [14..14] UART TX Idle完成中断标志（UART TX Idle Done
+ Interrupt Flag） */
+ __IOM uint32_t AMIF : 1; /*!< [15..15] UART RX地址匹配中断标志（UART RX Address Match
+ Interrupt Flag） */
+ __IOM uint32_t ABRF : 1; /*!< [16..16] UART 自动波特率检测错误中断标志（UART
+ Auto Baud Rate Error Interrupt Flag） */
+ uint32_t : 15;
+ } INT_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x0000003C) UART Status Register */
+
+ struct {
+ __IM uint32_t TBSY : 1; /*!< [0..0] UART TX总线忙碌标志（UART TX Busy Flag） */
+ __IM uint32_t TFE : 1; /*!< [1..1] UART TX发送FIFO空标志（UART TX-FIFO Empty Flag） */
+ __IM uint32_t TFF : 1; /*!< [2..2] UART TX发送FIFO满标志（UART TX-FIFO Full Flag） */
+ __IM uint32_t TFL : 5; /*!< [7..3] UART TX-FIFO实时剩余数据量（UART TX-FIFO Level
+ Register） */
+ __IM uint32_t RBSY : 1; /*!< [8..8] UART RX总线忙碌标志（UART RX Busy Flag） */
+ __IM uint32_t RFE : 1; /*!< [9..9] UART RX接收FIFO空标志（UART RX-FIFO Empty Flag） */
+ __IM uint32_t RFF : 1; /*!< [10..10] UART RX接收FIFO满标志（UART RX-FIFO Full Flag） */
+ __IM uint32_t RFL : 5; /*!< [15..11] UART RX-FIFO实时剩余数据量（UART RX-FIFO Level
+ Register） */
+ __IM uint32_t RSE : 1; /*!< [16..16] UART RX-Start错误标志位（UART RX-Start Error
+ Flag） */
+ uint32_t : 15;
+ } STATUS_b;
+ } ;
+} UART4_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SYSCTRL ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SYSCTRL (SYSCTRL)
+ */
+
+typedef struct { /*!< (@ 0x40021000) SYSCTRL Structure */
+
+ union {
+ __IOM uint32_t SYSDCR; /*!< (@ 0x00000000) System Debug Config Register */
+
+ struct {
+ __IOM uint32_t IWDGDEN : 1; /*!< [0..0] IWDG调试使能(IWDG Debug Enable) */
+ __IOM uint32_t WWDGDEN : 1; /*!< [1..1] WWDG调试使能(WWDG Debug Enable) */
+ __IOM uint32_t PWMDEN : 1; /*!< [2..2] HRPWM调试使能(HRPWM Debug Enable) */
+ __IOM uint32_t TMR7DEN : 1; /*!< [3..3] TMR7调试使能(TMR7 Debug Enable) */
+ __IOM uint32_t TMR8DEN : 1; /*!< [4..4] TMR8调试使能(TMR8 Debug Enable) */
+ __IOM uint32_t TMR0DEN : 1; /*!< [5..5] TMR0调试使能(TMR0 Debug Enable) */
+ __IOM uint32_t TMR1DEN : 1; /*!< [6..6] TMR1调试使能(TMR1 Debug Enable) */
+ __IOM uint32_t TMR2DEN : 1; /*!< [7..7] TMR2调试使能(TMR2 Debug Enable) */
+ __IOM uint32_t TMR3DEN : 1; /*!< [8..8] TMR3调试使能(TMR3 Debug Enable) */
+ __IOM uint32_t TMR4DEN : 1; /*!< [9..9] TMR4调试使能(TMR4 Debug Enable) */
+ __IOM uint32_t TMR9DEN : 1; /*!< [10..10] TMR9调试使能(TMR9 Debug Enable) */
+ __IOM uint32_t TMR10DEN : 1; /*!< [11..11] TMR10调试使能(TMR10 Debug Enable) */
+ uint32_t : 20;
+ } SYSDCR_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t SYSCR; /*!< (@ 0x00000008) System Config Register */
+
+ struct {
+ __IOM uint32_t ECCFE : 1; /*!< [0..0] FLASH多位ECC系统故障使能(FLASH nBits ECC Falut
+ Enable) */
+ __IOM uint32_t LKFE : 1; /*!< [1..1] CPU Lockup系统故障使能(CPU Lockup Falut Enable) */
+ __IOM uint32_t OSCFE : 1; /*!< [2..2] XOSC时钟异常系统故障使能(XOSC Loss Falut Enable) */
+ __IOM uint32_t PLLFE : 1; /*!< [3..3] PLL时钟失锁系统故障使能(PLL Lock Falut Enable) */
+ __IOM uint32_t QEI0FE : 1; /*!< [4..4] QEI0运行异常系统故障使能(QEI0 Falut Enable) */
+ __IOM uint32_t QEI1FE : 1; /*!< [5..5] QEI1运行异常系统故障使能(QEI1 Falut Enable) */
+ __IOM uint32_t QEI2FE : 1; /*!< [6..6] QEI2运行异常系统故障使能(QEI2 Falut Enable) */
+ uint32_t : 1;
+ __IOM uint32_t FBM : 1; /*!< [8..8] FLASH双Bank映射切换(FLASH Double Bank Mapping) */
+ uint32_t : 23;
+ } SYSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMARCR; /*!< (@ 0x0000000C) DMA Request Config Register */
+
+ struct {
+ uint32_t : 19;
+ __IOM uint32_t DRCR : 13; /*!< [31..19] DMA请求选择控制位(DMA Request Config Enable) */
+ } DMARCR_b;
+ } ;
+ __IM uint32_t RESERVED1[4];
+
+ union {
+ __IOM uint32_t SYSATR; /*!< (@ 0x00000020) System Analog Config Register */
+
+ struct {
+ uint32_t : 8;
+ __IOM uint32_t ABFEN : 1; /*!< [8..8] ADC Buffer使能(ADC Buffer Enable) */
+ __IOM uint32_t ABFBYP : 1; /*!< [9..9] ADC Buffer旁路使能(ADC Buffer Bypass Enable) */
+ __IOM uint32_t ABFSRC : 5; /*!< [14..10] ADC Buffer源选择(ADC Buffer Source Selection) */
+ uint32_t : 17;
+ } SYSATR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWRCR; /*!< (@ 0x00000024) PMU Power Config Register */
+
+ struct {
+ __IOM uint32_t TSE : 1; /*!< [0..0] 温度传感器使能控制（Temperature Sensor Enable） */
+ __IOM uint32_t AVDDEN : 1; /*!< [1..1] AVDD使能控制（AVDD Enable） */
+ __IOM uint32_t AVDDSET : 2; /*!< [3..2] AVDD电压控制(AVDD Voltage Config) */
+ __IOM uint32_t VDDSET : 4; /*!< [7..4] VDD电压控制(VDD Voltage Config) */
+ __IOM uint32_t AVDDDRD : 1; /*!< [8..8] AVDD的无电容LDO下拉配置选择（AVDD Drop Down） */
+ uint32_t : 23;
+ } PWRCR_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t PLCR; /*!< (@ 0x00000030) Power Limit Config Register */
+
+ struct {
+ __IOM uint32_t VDDLVE : 1; /*!< [0..0] VDD低电压监测使能(VDD LowVoltage Enable) */
+ __IOM uint32_t VCCLVE : 1; /*!< [1..1] VCC低电压监测使能(VCC LowVoltage Enable) */
+ __IOM uint32_t AVCCLVE : 1; /*!< [2..2] AVCC低电压监测使能(AVCC LowVoltage Enable) */
+ __IOM uint32_t VDDOCE : 1; /*!< [3..3] VDD过流监测使能(VDD OverCurrent Enable) */
+ __IOM uint32_t VDDLVS : 3; /*!< [6..4] VDD低电压阈值设置(VDD LowVoltage Limit Config) */
+ uint32_t : 3;
+ __IOM uint32_t AVCCLVL : 2; /*!< [11..10] AVCC低电压阈值设置(AVCC LowVoltage Limit Config) */
+ __IOM uint32_t VDDOCL : 2; /*!< [13..12] VDD过流阈值设置(VDD OverCurrent Limit Config) */
+ uint32_t : 18;
+ } PLCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PECR; /*!< (@ 0x00000034) Power Event Control Register */
+
+ struct {
+ __IOM uint32_t VDDLVIE : 1; /*!< [0..0] VDD低电压中断使能(VDD LowVoltage Interrupt Enable) */
+ __IOM uint32_t VCCLVIE : 1; /*!< [1..1] VCC低电压中断使能(VCC LowVoltage Interrupt Enable) */
+ __IOM uint32_t AVCCLVIE : 1; /*!< [2..2] AVCC低电压中断使能(AVCC LowVoltage Interrupt Enable) */
+ __IOM uint32_t VDDOCIE : 1; /*!< [3..3] VDD过流中断使能(VDD OverCurrent Interrupt Enable) */
+ __IOM uint32_t VDDLVRE : 1; /*!< [4..4] VDD低电压复位使能(VDD LowVoltage Reset Enable) */
+ __IOM uint32_t VCCLVRE : 1; /*!< [5..5] VCC低电压复位使能(VCC LowVoltage Reset Enable) */
+ __IOM uint32_t AVCCLVRE : 1; /*!< [6..6] AVCC低电压复位使能(AVCC LowVoltage Reset Enable) */
+ __IOM uint32_t VDDOCRE : 1; /*!< [7..7] VDD过流复位使能(VDD OverCurrent Reset Enable) */
+ __IOM uint32_t VDDLVBE : 1; /*!< [8..8] VDD低电压刹车使能(VDD LowVoltage Brake Enable) */
+ __IOM uint32_t VCCLVBE : 1; /*!< [9..9] VCC低电压刹车使能(VCC LowVoltage Brake Enable) */
+ __IOM uint32_t AVCCLVBE : 1; /*!< [10..10] AVCC低电压刹车使能(AVCC LowVoltage Brake Enable) */
+ __IOM uint32_t VDDOCBE : 1; /*!< [11..11] VDD过流刹车使能(VDD OverCurrent Brake Enable) */
+ uint32_t : 20;
+ } PECR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PSR; /*!< (@ 0x00000038) Power Status Register */
+
+ struct {
+ __IM uint32_t VDDLVS : 1; /*!< [0..0] VDD低电压状态位(VDD LowVoltage Status) */
+ __IM uint32_t VCCLVS : 1; /*!< [1..1] VCC低电压状态位(VCC LowVoltage Status) */
+ __IM uint32_t AVCCLVS : 1; /*!< [2..2] AVCC低电压状态位(AVCC LowVoltage Status) */
+ __IM uint32_t VDDOCS : 1; /*!< [3..3] VDD过流状态位(VDD OverCurrent Status) */
+ uint32_t : 28;
+ } PSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWRDR; /*!< (@ 0x0000003C) Power Debounce Register */
+
+ struct {
+ __IOM uint32_t VDDLVF : 4; /*!< [3..0] VDD欠压消抖配置(VDD LowVoltage Config) */
+ __IOM uint32_t VCCLVF : 4; /*!< [7..4] VCC欠压消抖配置(VCC LowVoltage Config) */
+ __IOM uint32_t AVCCLVF : 4; /*!< [11..8] AVCC欠压消抖配置(AVCC LowVoltage Config) */
+ __IOM uint32_t VDDOCF : 4; /*!< [15..12] VDD过流消抖配置(VDD OverCurrent Config) */
+ uint32_t : 16;
+ } PWRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CIDR; /*!< (@ 0x00000040) System ChipId Config Register */
+
+ struct {
+ __IM uint32_t CID : 16; /*!< [15..0] CHIP CID */
+ __IM uint32_t DCN : 8; /*!< [23..16] CHIP DCN */
+ uint32_t : 8;
+ } CIDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t KEYR; /*!< (@ 0x00000044) LockKey Register */
+
+ struct {
+ __IOM uint32_t KEY : 16; /*!< [15..0] 寄存器写保护(Register LockKey) */
+ __IOM uint32_t KST0 : 1; /*!< [16..16] 系统寄存器保护状态位 */
+ __IOM uint32_t KST1 : 1; /*!< [17..17] 校准寄存器保护状态位 */
+ uint32_t : 14;
+ } KEYR_b;
+ } ;
+ __IM uint32_t RESERVED3[2];
+
+ union {
+ __IOM uint32_t UID0; /*!< (@ 0x00000050) System UserID0 Register */
+
+ struct {
+ __IM uint32_t UID0 : 32; /*!< [31..0] System UID0 Register */
+ } UID0_b;
+ } ;
+
+ union {
+ __IOM uint32_t UID1; /*!< (@ 0x00000054) System UserID1 Register */
+
+ struct {
+ __IM uint32_t UID1 : 32; /*!< [31..0] System UID1 Register */
+ } UID1_b;
+ } ;
+
+ union {
+ __IOM uint32_t UID2; /*!< (@ 0x00000058) System UserID2 Register */
+
+ struct {
+ __IM uint32_t UID2 : 32; /*!< [31..0] System UID2 Register */
+ } UID2_b;
+ } ;
+
+ union {
+ __IOM uint32_t UID3; /*!< (@ 0x0000005C) System UserID3 Register */
+
+ struct {
+ __IM uint32_t UID3 : 32; /*!< [31..0] System UID3 Register */
+ } UID3_b;
+ } ;
+
+ union {
+ __IOM uint32_t ATCR; /*!< (@ 0x00000060) Analog Trim Config Register */
+
+ struct {
+ uint32_t : 1;
+ __IOM uint32_t REFVTRIM : 5; /*!< [5..1] REF参考电压校准 */
+ __IOM uint32_t REFITRIM : 6; /*!< [11..6] REF参考电流校准 */
+ __IOM uint32_t VBFEN : 1; /*!< [12..12] VREFBUF使能 */
+ __IOM uint32_t VBFSEL : 1; /*!< [13..13] VREFBUF输出电压选择 */
+ __IOM uint32_t VBFTRIM : 5; /*!< [18..14] VREFBUF输出电压校准 */
+ __IOM uint32_t VBFCL : 1; /*!< [19..19] VREFBUF启动限流使能 */
+ __IOM uint32_t BGV : 11; /*!< [30..20] 内部BGR电压 */
+ __IOM uint32_t VBFRDY : 1; /*!< [31..31] VREFBUF输出电压状态 */
+ } ATCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FCR0; /*!< (@ 0x00000064) System AutoLoad Register0 */
+
+ struct {
+ __IOM uint32_t ADC0TRIM : 5; /*!< [4..0] ADC0内部1/2VREF电压校准值 */
+ uint32_t : 3;
+ __IOM uint32_t ADC1TRIM : 5; /*!< [12..8] ADC1内部1/2VREF电压校准值 */
+ uint32_t : 3;
+ __IOM uint32_t ADC2TRIM : 5; /*!< [20..16] ADC2内部1/2VREF电压校准值 */
+ uint32_t : 3;
+ __IOM uint32_t ADC3TRIM : 5; /*!< [28..24] ADC3内部1/2VREF电压校准值 */
+ uint32_t : 3;
+ } FCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t FCR1; /*!< (@ 0x00000068) System AutoLoad Register1 */
+
+ struct {
+ uint32_t : 20;
+ __IOM uint32_t DAC0TRIM : 4; /*!< [23..20] DAC0输出BUF Offset校准 */
+ __IOM uint32_t DAC1TRIM : 4; /*!< [27..24] DAC1输出BUF Offset校准 */
+ __IOM uint32_t DAC2TRIM : 4; /*!< [31..28] DAC2输出BUF Offset校准 */
+ } FCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t FCR2; /*!< (@ 0x0000006C) System AutoLoad Register2 */
+
+ struct {
+ __IOM uint32_t PLL0BANDy : 2; /*!< [1..0] PLL0-200M校准BAND值 */
+ __IOM uint32_t PLL0BANDx : 2; /*!< [3..2] PLL0-180M校准BAND值 */
+ __IOM uint32_t ADCPVEN : 1; /*!< [4..4] ADC转换相位时钟使能 */
+ uint32_t : 3;
+ __IOM uint32_t RC8M : 24; /*!< [31..8] RC8M实际频率 */
+ } FCR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t FCR3; /*!< (@ 0x00000070) System AutoLoad Register3 */
+
+ struct {
+ __IOM uint32_t PLL0FRACy : 16; /*!< [15..0] PLL0-200M校准分频FRAC值 */
+ __IOM uint32_t PLL0INTy : 14; /*!< [29..16] PLL0-200M校准分频INT值 */
+ uint32_t : 2;
+ } FCR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t FCR4; /*!< (@ 0x00000074) System AutoLoad Register4 */
+
+ struct {
+ __IOM uint32_t PLL0FRACx : 16; /*!< [15..0] PLL0-180M校准分频FRAC值 */
+ __IOM uint32_t PLL0INTx : 14; /*!< [29..16] PLL0-180M校准分频INT值 */
+ uint32_t : 2;
+ } FCR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t FCR5; /*!< (@ 0x00000078) System AutoLoad Register5 */
+
+ struct {
+ __IOM uint32_t Tsensor : 16; /*!< [15..0] Tsensor温度传感校准值 */
+ __IOM uint32_t RC32K : 16; /*!< [31..16] RC32K实际频率 */
+ } FCR5_b;
+ } ;
+} SYSCTRL_Type; /*!< Size = 124 (0x7c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI0 (SPI0)
+ */
+
+typedef struct { /*!< (@ 0x40012000) SPI0 Structure */
+
+ union {
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) SPI Enable Register */
+
+ struct {
+ __IM uint32_t SPIEN : 1; /*!< [0..0] SPI使能位（SPI Enable） */
+ __IOM uint32_t RFR : 1; /*!< [1..1] SPI RXFIFO复位（SPI RXFIFO RESET） */
+ __IOM uint32_t TFR : 1; /*!< [2..2] SPI TXFIFO复位（SPI TXFIFO RESET） */
+ __IOM uint32_t TWE : 1; /*!< [3..3] SPI三线使能（SPI three-Wire Enable） */
+ __IOM uint32_t CSSEL : 1; /*!< [4..4] SPI NSS模式选择（SPI Negative Slave Select Mode
+ Select） */
+ __IOM uint32_t CSPOL : 1; /*!< [5..5] SPI NSS状态极性选择（SPI Negative Slave Select
+ Polarity Select） */
+ __IOM uint32_t SWAP : 1; /*!< [6..6] SPI MOSI和MISO引脚交换（SPI MOSI and MISO Pins
+ Swap Enable） */
+ __IOM uint32_t LOOP : 1; /*!< [7..7] SPI Loopback使能位（SPI Loopback Enable） */
+ __IOM uint32_t DRE : 1; /*!< [8..8] SPI接收DMA使能（SPI RX DMA Enable） */
+ __IOM uint32_t DTE : 1; /*!< [9..9] SPI发送DMA使能（SPI TX DMA Enable） */
+ uint32_t : 2;
+ __IOM uint32_t CSOS : 1; /*!< [12..12] SPI NSS输出选择（SPI Negative Slave Select Output
+ Select） */
+ __IOM uint32_t CSO : 1; /*!< [13..13] SPI NSS软件输出（SPI Negative Slave Select Software
+ Output） */
+ __IOM uint32_t CSIS : 1; /*!< [14..14] SPI NSS输入选择（SPI Negative Slave Select Input
+ Select） */
+ __IOM uint32_t CSI : 1; /*!< [15..15] SPI NSS软件输入（SPI Negative Slave Select Software
+ Input） */
+ uint32_t : 16;
+ } ENABLE_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) SPI Control Register */
+
+ struct {
+ __IOM uint32_t MSTEN : 1; /*!< [0..0] SPI的主机使能位（SPI Master Enable） */
+ __IOM uint32_t CPHA : 1; /*!< [1..1] SPI串行时钟相位（SPI SCLK Phase） */
+ __IOM uint32_t CPOL : 1; /*!< [2..2] SPI串行时钟极性（SPI SCLK Polarity） */
+ __IOM uint32_t SHZOE : 1; /*!< [3..3] SPI从机输出高阻态使能位（SPI Slave High-Z
+ Output Enable ） */
+ __IOM uint32_t TXEN : 1; /*!< [4..4] SPI发送使能（SPI TX Enable） */
+ __IOM uint32_t RXEN : 1; /*!< [5..5] SPI接收使能（SPI RX Enable） */
+ __IOM uint32_t LSB : 1; /*!< [6..6] SPI LSB使能（LSB Enable） */
+ __IOM uint32_t UDRCFG : 1; /*!< [7..7] SPI下溢条件时从机发送器行为 (SPI Behavior
+ of slave transmitter at underrun condition) */
+ __IOM uint32_t LEN : 4; /*!< [11..8] SPI串行数据长度（SPI Serial Data Length Select） */
+ uint32_t : 4;
+ __IOM uint32_t RXDLY : 3; /*!< [18..16] SPI接收数据采样延迟（SPI Master Rx Data Delay
+ Chain ） */
+ uint32_t : 13;
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) SPI Baud Rate Registers */
+
+ struct {
+ uint32_t : 1;
+ __IOM uint32_t BAUD : 11; /*!< [11..1] SPI时钟分频器（SPI Baud Rate） */
+ uint32_t : 20;
+ } BAUD_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) SPI FIFO Control Register */
+
+ struct {
+ __IOM uint32_t TXFTLR : 4; /*!< [3..0] SPI TXFIFO空中断阈值（SPI TXFIFO Empty Threshold） */
+ __IOM uint32_t RXFTLR : 4; /*!< [7..4] SPI RXFIFO满中断阈值（SPI RXFIFO Full Threshold） */
+ uint32_t : 24;
+ } FIFOCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNT; /*!< (@ 0x00000014) SPI Count Registers */
+
+ struct {
+ __IOM uint32_t DCNT : 16; /*!< [15..0] SPI主机传输数据量（SPI Transmittion Data Count） */
+ uint32_t : 16;
+ } CNT_b;
+ } ;
+
+ union {
+ __IOM uint32_t RCNT; /*!< (@ 0x00000018) SPI Remain Count Register */
+
+ struct {
+ __IM uint32_t RCNT : 16; /*!< [15..0] SPI主机传输剩余数据量（SPI Transmittion Remain
+ Count） */
+ uint32_t : 16;
+ } RCNT_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t START; /*!< (@ 0x00000020) SPI Count Start Register */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] SPI主机传输开始（SPI Master Transmittion Start） */
+ __IOM uint32_t STOP : 1; /*!< [1..1] SPI主机传输停止（SPI Master Transmittion Stop） */
+ uint32_t : 30;
+ } START_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING; /*!< (@ 0x00000024) SPI Timing Register */
+
+ struct {
+ __IOM uint32_t MIDI : 5; /*!< [4..0] SPI主模式数据间空闲 (SPI Master Inter-Data Idleness) */
+ uint32_t : 11;
+ __IOM uint32_t MCSI : 5; /*!< [20..16] SPI主模式NSS空闲 (SPI Master Negative Slave Select
+ Idleness) */
+ uint32_t : 11;
+ } TIMING_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t INTEN; /*!< (@ 0x00000030) SPI Interrupt Enable Registers */
+
+ struct {
+ __IOM uint32_t RXFIE : 1; /*!< [0..0] SPI RXFIFO满阈值中断使能（SPI RXFIFO Full Threshold
+ Interrupt Enable） */
+ __IOM uint32_t TXEIE : 1; /*!< [1..1] SPI TXFIFO空阈值中断使能（SPI TXFIFO Empty Threshold
+ Interrupt Enable） */
+ __IOM uint32_t RXOFIE : 1; /*!< [2..2] SPI RXFIFO溢出中断使能（SPI RXFIFO Overflow Interrupt
+ Enable） */
+ __IOM uint32_t RXUFIE : 1; /*!< [3..3] SPI RXFIFO下溢中断使能（SPI RXFIFO Underflow Interrupt
+ Enable） */
+ __IOM uint32_t TXOFIE : 1; /*!< [4..4] SPI TXFIFO溢出中断使能（SPI TXFIFO Overflow Interrupt
+ Enable） */
+ __IOM uint32_t TXUFIE : 1; /*!< [5..5] SPI从机发送模式下溢中断使能（SPI Slave Transmission
+ Mode Underflow Interrupt Enable） */
+ __IOM uint32_t OPFIE : 1; /*!< [6..6] SPI主从操作错误中断使能（SPI Transmission
+ Operation Fault Interrupt Enable） */
+ __IOM uint32_t MDFIE : 1; /*!< [7..7] SPI主从模式错误中断使能（SPI Transmission
+ Mode Fault Interrupt Enable） */
+ __IOM uint32_t TXDEIE : 1; /*!< [8..8] SPI发送完成中断使能（SPI TX Done Interrupt Enable） */
+ __IOM uint32_t RXDEIE : 1; /*!< [9..9] SPI接收完成中断使能（SPI RX Done Interrupt Enable） */
+ __IOM uint32_t TXCIE : 1; /*!< [10..10] SPI发送帧完成中断使能（SPI TX Complete Interrupt
+ Enable） */
+ __IOM uint32_t RXCIE : 1; /*!< [11..11] SPI接收帧完成中断使能（SPI RX Complete Interrupt
+ Enable） */
+ uint32_t : 20;
+ } INTEN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INT; /*!< (@ 0x00000034) SPI Interrupt Registers */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] SPI RXFIFO满阈值中断（SPI RXFIFO Full Threshold
+ Interrupt ） */
+ __IM uint32_t TXEI : 1; /*!< [1..1] SPI TXFIFO空阈值中断（SPI TXFIFO Empty Threshold
+ Interrupt ） */
+ __IOM uint32_t RXOFI : 1; /*!< [2..2] SPI RXFIFO溢出中断（SPI RXFIFO Overflow Interrupt） */
+ __IOM uint32_t RXUFI : 1; /*!< [3..3] SPI RXFIFO下溢中断（SPI RXFIFO Underflow Interrupt） */
+ __IOM uint32_t TXOFI : 1; /*!< [4..4] SPI TXFIFO溢出中断（SPI TXFIFO Overflow Interrupt） */
+ __IOM uint32_t TXUFI : 1; /*!< [5..5] SPI从机发送模式下溢中断（SPI Slave Transmission
+ Mode Underflow Interrupt） */
+ __IOM uint32_t OPFI : 1; /*!< [6..6] SPI主从机操作错误中断（SPI Transmission Operation
+ Fault Interrupt） */
+ __IOM uint32_t MDFI : 1; /*!< [7..7] SPI主从机模式错误中断（SPI Transmission Mode
+ Fault Interrupt） */
+ __IOM uint32_t TXDEI : 1; /*!< [8..8] SPI发送完成中断（SPI TX Done Interrupt ） */
+ __IOM uint32_t RXDEI : 1; /*!< [9..9] SPI接收完成中断（SPI RX Done Interrupt ） */
+ __IOM uint32_t TXCI : 1; /*!< [10..10] SPI发送帧完成中断（SPI TX Complete Interrupt） */
+ __IOM uint32_t RXCI : 1; /*!< [11..11] SPI接收帧完成中断（SPI RX Complete Interrupt） */
+ uint32_t : 20;
+ } INT_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x00000038) SPI Status Register */
+
+ struct {
+ __IM uint32_t BUSY : 1; /*!< [0..0] SPI状态机忙状态（SPI FSM Busy Status） */
+ uint32_t : 15;
+ __IM uint32_t TXFLR : 5; /*!< [20..16] SPI TXFIFO实时剩余数据量（SPI TXFIFO Level
+ Register） */
+ __IM uint32_t TFE : 1; /*!< [21..21] SPI TXFIFO空标志（SPI TXFIFO Empty Flag） */
+ __IM uint32_t TFF : 1; /*!< [22..22] SPI TXFIFO满标志（SPI TXFIFO Full Flag） */
+ uint32_t : 1;
+ __IM uint32_t RXFLR : 5; /*!< [28..24] SPI RXFIFO实时剩余数据量（SPI RXFIFO Level
+ Register） */
+ __IM uint32_t RFE : 1; /*!< [29..29] SPI RXFIFO空标志（SPI RXFIFO Empty Flag） */
+ __IM uint32_t RFF : 1; /*!< [30..30] SPI RXFIFO满标志（SPI RXFIFO Full Flag） */
+ uint32_t : 1;
+ } STATUS_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t TDR; /*!< (@ 0x00000040) SPI TXFIFO Data Registers */
+
+ struct {
+ __IOM uint32_t TD : 16; /*!< [15..0] SPI数据写寄存器（SPI Data Write Register） */
+ uint32_t : 16;
+ } TDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000044) SPI RXFIFO Data Registers */
+
+ struct {
+ __IM uint32_t RD : 16; /*!< [15..0] SPI数据读寄存器（SPI Data Read Register） */
+ uint32_t : 16;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDRDR; /*!< (@ 0x00000048) SPI Underrun Data Register */
+
+ struct {
+ __IOM uint32_t UDRDR : 16; /*!< [15..0] SPI从模式下溢时数据写寄存器 (SPI Data At
+ Slave Underflow Condition) */
+ uint32_t : 16;
+ } UDRDR_b;
+ } ;
+} SPI0_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI1 (SPI1)
+ */
+
+typedef struct { /*!< (@ 0x40013000) SPI1 Structure */
+
+ union {
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) SPI Enable Register */
+
+ struct {
+ __IM uint32_t SPIEN : 1; /*!< [0..0] SPI使能位（SPI Enable） */
+ __IOM uint32_t RFR : 1; /*!< [1..1] SPI RXFIFO复位（SPI RXFIFO RESET） */
+ __IOM uint32_t TFR : 1; /*!< [2..2] SPI TXFIFO复位（SPI TXFIFO RESET） */
+ __IOM uint32_t TWE : 1; /*!< [3..3] SPI三线使能（SPI three-Wire Enable） */
+ __IOM uint32_t CSSEL : 1; /*!< [4..4] SPI NSS模式选择（SPI Negative Slave Select Mode
+ Select） */
+ __IOM uint32_t CSPOL : 1; /*!< [5..5] SPI NSS状态极性选择（SPI Negative Slave Select
+ Polarity Select） */
+ __IOM uint32_t SWAP : 1; /*!< [6..6] SPI MOSI和MISO引脚交换（SPI MOSI and MISO Pins
+ Swap Enable） */
+ __IOM uint32_t LOOP : 1; /*!< [7..7] SPI Loopback使能位（SPI Loopback Enable） */
+ __IOM uint32_t DRE : 1; /*!< [8..8] SPI接收DMA使能（SPI RX DMA Enable） */
+ __IOM uint32_t DTE : 1; /*!< [9..9] SPI发送DMA使能（SPI TX DMA Enable） */
+ uint32_t : 2;
+ __IOM uint32_t CSOS : 1; /*!< [12..12] SPI NSS输出选择（SPI Negative Slave Select Output
+ Select） */
+ __IOM uint32_t CSO : 1; /*!< [13..13] SPI NSS软件输出（SPI Negative Slave Select Software
+ Output） */
+ __IOM uint32_t CSIS : 1; /*!< [14..14] SPI NSS输入选择（SPI Negative Slave Select Input
+ Select） */
+ __IOM uint32_t CSI : 1; /*!< [15..15] SPI NSS软件输入（SPI Negative Slave Select Software
+ Input） */
+ uint32_t : 16;
+ } ENABLE_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) SPI Control Register */
+
+ struct {
+ __IOM uint32_t MSTEN : 1; /*!< [0..0] SPI的主机使能位（SPI Master Enable） */
+ __IOM uint32_t CPHA : 1; /*!< [1..1] SPI串行时钟相位（SPI SCLK Phase） */
+ __IOM uint32_t CPOL : 1; /*!< [2..2] SPI串行时钟极性（SPI SCLK Polarity） */
+ __IOM uint32_t SHZOE : 1; /*!< [3..3] SPI从机输出高阻态使能位（SPI Slave High-Z
+ Output Enable ） */
+ __IOM uint32_t TXEN : 1; /*!< [4..4] SPI发送使能（SPI TX Enable） */
+ __IOM uint32_t RXEN : 1; /*!< [5..5] SPI接收使能（SPI RX Enable） */
+ __IOM uint32_t LSB : 1; /*!< [6..6] SPI LSB使能（LSB Enable） */
+ __IOM uint32_t UDRCFG : 1; /*!< [7..7] SPI下溢条件时从机发送器行为 (SPI Behavior
+ of slave transmitter at underrun condition) */
+ __IOM uint32_t LEN : 4; /*!< [11..8] SPI串行数据长度（SPI Serial Data Length Select） */
+ uint32_t : 4;
+ __IOM uint32_t RXDLY : 3; /*!< [18..16] SPI接收数据采样延迟（SPI Master Rx Data Delay
+ Chain ） */
+ uint32_t : 13;
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) SPI Baud Rate Registers */
+
+ struct {
+ uint32_t : 1;
+ __IOM uint32_t BAUD : 11; /*!< [11..1] SPI时钟分频器（SPI Baud Rate） */
+ uint32_t : 20;
+ } BAUD_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) SPI FIFO Control Register */
+
+ struct {
+ __IOM uint32_t TXFTLR : 4; /*!< [3..0] SPI TXFIFO空中断阈值（SPI TXFIFO Empty Threshold） */
+ __IOM uint32_t RXFTLR : 4; /*!< [7..4] SPI RXFIFO满中断阈值（SPI RXFIFO Full Threshold） */
+ uint32_t : 24;
+ } FIFOCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNT; /*!< (@ 0x00000014) SPI Count Registers */
+
+ struct {
+ __IOM uint32_t DCNT : 16; /*!< [15..0] SPI主机传输数据量（SPI Transmittion Data Count） */
+ uint32_t : 16;
+ } CNT_b;
+ } ;
+
+ union {
+ __IOM uint32_t RCNT; /*!< (@ 0x00000018) SPI Remain Count Register */
+
+ struct {
+ __IM uint32_t RCNT : 16; /*!< [15..0] SPI主机传输剩余数据量（SPI Transmittion Remain
+ Count） */
+ uint32_t : 16;
+ } RCNT_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t START; /*!< (@ 0x00000020) SPI Count Start Register */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] SPI主机传输开始（SPI Master Transmittion Start） */
+ __IOM uint32_t STOP : 1; /*!< [1..1] SPI主机传输停止（SPI Master Transmittion Stop） */
+ uint32_t : 30;
+ } START_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING; /*!< (@ 0x00000024) SPI Timing Register */
+
+ struct {
+ __IOM uint32_t MIDI : 5; /*!< [4..0] SPI主模式数据间空闲 (SPI Master Inter-Data Idleness) */
+ uint32_t : 11;
+ __IOM uint32_t MCSI : 5; /*!< [20..16] SPI主模式NSS空闲 (SPI Master Negative Slave Select
+ Idleness) */
+ uint32_t : 11;
+ } TIMING_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t INTEN; /*!< (@ 0x00000030) SPI Interrupt Enable Registers */
+
+ struct {
+ __IOM uint32_t RXFIE : 1; /*!< [0..0] SPI RXFIFO满阈值中断使能（SPI RXFIFO Full Threshold
+ Interrupt Enable） */
+ __IOM uint32_t TXEIE : 1; /*!< [1..1] SPI TXFIFO空阈值中断使能（SPI TXFIFO Empty Threshold
+ Interrupt Enable） */
+ __IOM uint32_t RXOFIE : 1; /*!< [2..2] SPI RXFIFO溢出中断使能（SPI RXFIFO Overflow Interrupt
+ Enable） */
+ __IOM uint32_t RXUFIE : 1; /*!< [3..3] SPI RXFIFO下溢中断使能（SPI RXFIFO Underflow Interrupt
+ Enable） */
+ __IOM uint32_t TXOFIE : 1; /*!< [4..4] SPI TXFIFO溢出中断使能（SPI TXFIFO Overflow Interrupt
+ Enable） */
+ __IOM uint32_t TXUFIE : 1; /*!< [5..5] SPI从机发送模式下溢中断使能（SPI Slave Transmission
+ Mode Underflow Interrupt Enable） */
+ __IOM uint32_t OPFIE : 1; /*!< [6..6] SPI主从操作错误中断使能（SPI Transmission
+ Operation Fault Interrupt Enable） */
+ __IOM uint32_t MDFIE : 1; /*!< [7..7] SPI主从模式错误中断使能（SPI Transmission
+ Mode Fault Interrupt Enable） */
+ __IOM uint32_t TXDEIE : 1; /*!< [8..8] SPI发送完成中断使能（SPI TX Done Interrupt Enable） */
+ __IOM uint32_t RXDEIE : 1; /*!< [9..9] SPI接收完成中断使能（SPI RX Done Interrupt Enable） */
+ __IOM uint32_t TXCIE : 1; /*!< [10..10] SPI发送帧完成中断使能（SPI TX Complete Interrupt
+ Enable） */
+ __IOM uint32_t RXCIE : 1; /*!< [11..11] SPI接收帧完成中断使能（SPI RX Complete Interrupt
+ Enable） */
+ uint32_t : 20;
+ } INTEN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INT; /*!< (@ 0x00000034) SPI Interrupt Registers */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] SPI RXFIFO满阈值中断（SPI RXFIFO Full Threshold
+ Interrupt ） */
+ __IM uint32_t TXEI : 1; /*!< [1..1] SPI TXFIFO空阈值中断（SPI TXFIFO Empty Threshold
+ Interrupt ） */
+ __IOM uint32_t RXOFI : 1; /*!< [2..2] SPI RXFIFO溢出中断（SPI RXFIFO Overflow Interrupt） */
+ __IOM uint32_t RXUFI : 1; /*!< [3..3] SPI RXFIFO下溢中断（SPI RXFIFO Underflow Interrupt） */
+ __IOM uint32_t TXOFI : 1; /*!< [4..4] SPI TXFIFO溢出中断（SPI TXFIFO Overflow Interrupt） */
+ __IOM uint32_t TXUFI : 1; /*!< [5..5] SPI从机发送模式下溢中断（SPI Slave Transmission
+ Mode Underflow Interrupt） */
+ __IOM uint32_t OPFI : 1; /*!< [6..6] SPI主从机操作错误中断（SPI Transmission Operation
+ Fault Interrupt） */
+ __IOM uint32_t MDFI : 1; /*!< [7..7] SPI主从机模式错误中断（SPI Transmission Mode
+ Fault Interrupt） */
+ __IOM uint32_t TXDEI : 1; /*!< [8..8] SPI发送完成中断（SPI TX Done Interrupt ） */
+ __IOM uint32_t RXDEI : 1; /*!< [9..9] SPI接收完成中断（SPI RX Done Interrupt ） */
+ __IOM uint32_t TXCI : 1; /*!< [10..10] SPI发送帧完成中断（SPI TX Complete Interrupt） */
+ __IOM uint32_t RXCI : 1; /*!< [11..11] SPI接收帧完成中断（SPI RX Complete Interrupt） */
+ uint32_t : 20;
+ } INT_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x00000038) SPI Status Register */
+
+ struct {
+ __IM uint32_t BUSY : 1; /*!< [0..0] SPI状态机忙状态（SPI FSM Busy Status） */
+ uint32_t : 15;
+ __IM uint32_t TXFLR : 5; /*!< [20..16] SPI TXFIFO实时剩余数据量（SPI TXFIFO Level
+ Register） */
+ __IM uint32_t TFE : 1; /*!< [21..21] SPI TXFIFO空标志（SPI TXFIFO Empty Flag） */
+ __IM uint32_t TFF : 1; /*!< [22..22] SPI TXFIFO满标志（SPI TXFIFO Full Flag） */
+ uint32_t : 1;
+ __IM uint32_t RXFLR : 5; /*!< [28..24] SPI RXFIFO实时剩余数据量（SPI RXFIFO Level
+ Register） */
+ __IM uint32_t RFE : 1; /*!< [29..29] SPI RXFIFO空标志（SPI RXFIFO Empty Flag） */
+ __IM uint32_t RFF : 1; /*!< [30..30] SPI RXFIFO满标志（SPI RXFIFO Full Flag） */
+ uint32_t : 1;
+ } STATUS_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t TDR; /*!< (@ 0x00000040) SPI TXFIFO Data Registers */
+
+ struct {
+ __IOM uint32_t TD : 16; /*!< [15..0] SPI数据写寄存器（SPI Data Write Register） */
+ uint32_t : 16;
+ } TDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000044) SPI RXFIFO Data Registers */
+
+ struct {
+ __IM uint32_t RD : 16; /*!< [15..0] SPI数据读寄存器（SPI Data Read Register） */
+ uint32_t : 16;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDRDR; /*!< (@ 0x00000048) SPI Underrun Data Register */
+
+ struct {
+ __IOM uint32_t UDRDR : 16; /*!< [15..0] SPI从模式下溢时数据写寄存器 (SPI Data At
+ Slave Underflow Condition) */
+ uint32_t : 16;
+ } UDRDR_b;
+ } ;
+} SPI1_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RCU ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief RCU (RCU)
+ */
+
+typedef struct { /*!< (@ 0x40020000) RCU Structure */
+
+ union {
+ __IOM uint32_t PLL0CR; /*!< (@ 0x00000000) PLL0 Control Register */
+
+ struct {
+ __IOM uint32_t RCS : 2; /*!< [1..0] PLL0参考时钟源(PLL0 Refer Clock Selection) */
+ __IOM uint32_t ARE : 1; /*!< [2..2] PLL0自动加载使能(PLL0 AutoReload Enable) */
+ __IOM uint32_t UG : 1; /*!< [3..3] PLL0倍频系数更新事件(PLL0 Update Generate) */
+ uint32_t : 4;
+ __IOM uint32_t BDS : 2; /*!< [9..8] PLL0 VCO振荡频率范围控制(PLL0 Band Selection) */
+ __IOM uint32_t LPF : 1; /*!< [10..10] PLL0 LPF配置(PLL0 LPF Config) */
+ __IOM uint32_t RFD : 1; /*!< [11..11] PLL0参考前除频(PLL0 Refer Clock Division) */
+ uint32_t : 18;
+ __IM uint32_t LKF : 1; /*!< [30..30] PLL0锁定标志(PLL0 Lock Flag) */
+ __IOM uint32_t EN : 1; /*!< [31..31] PLL0使能(PLL0 Enable) */
+ } PLL0CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PLL0FR; /*!< (@ 0x00000004) PLL0 Fractional Register */
+
+ struct {
+ __IOM uint32_t FRAC : 16; /*!< [15..0] PLL0倍频系数小数部分(PLL0 Fractional part of
+ multiplication factor) */
+ __IOM uint32_t INT : 14; /*!< [29..16] PLL0倍频系数整数部分(PLL0 Integer part of multiplication
+ factor) */
+ uint32_t : 2;
+ } PLL0FR_b;
+ } ;
+ __IM uint32_t RESERVED[10];
+
+ union {
+ __IOM uint32_t CCR; /*!< (@ 0x00000030) System Clock Config Register */
+
+ struct {
+ __IOM uint32_t SCS : 2; /*!< [1..0] 系统时钟源选择(System Clock Selection) */
+ __IOM uint32_t HPSC : 6; /*!< [7..2] AHB时钟分频配置(AHB Clock Prescale) */
+ __IOM uint32_t P0PSC : 4; /*!< [11..8] APB0时钟分频配置(APB0 Clock Prescale) */
+ __IOM uint32_t P1PSC : 4; /*!< [15..12] APB1时钟分频配置(APB1 Clock Prescale) */
+ uint32_t : 16;
+ } CCR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t PCSR; /*!< (@ 0x00000038) Peripheral Function Clock Source Register */
+
+ struct {
+ __IOM uint32_t PWMCS : 2; /*!< [1..0] PWM时钟源选择(PWM Clock Source Selection) */
+ __IOM uint32_t ADCCS : 2; /*!< [3..2] ADC时钟源选择(ADC Clock Source Selection) */
+ __IOM uint32_t USBCS : 2; /*!< [5..4] USB时钟源选择(USB Clock Source Selection) */
+ __IOM uint32_t CANCS : 2; /*!< [7..6] CAN时钟源选择(CAN Clock Source Selection) */
+ __IOM uint32_t TMR6CS : 2; /*!< [9..8] TMR6时钟源选择(TMR6 Clock Source Selection) */
+ uint32_t : 22;
+ } PCSR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t PCDR0; /*!< (@ 0x00000040) Peripheral Function Clock Division Register0 */
+
+ struct {
+ __IOM uint32_t PADIV : 8; /*!< [7..0] GPIOA消抖时钟分频(GPIOA Debounce Clock Division) */
+ __IOM uint32_t PBDIV : 8; /*!< [15..8] GPIOB消抖时钟分频(GPIOB Debounce Clock Division) */
+ __IOM uint32_t PCDIV : 8; /*!< [23..16] GPIOC消抖时钟分频(GPIOC Debounce Clock Division) */
+ __IOM uint32_t PDDIV : 8; /*!< [31..24] GPIOD消抖时钟分频(GPIOD Debounce Clock Division) */
+ } PCDR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t PCDR1; /*!< (@ 0x00000044) Peripheral Function Clock Division Register1 */
+
+ struct {
+ __IOM uint32_t PEDIV : 8; /*!< [7..0] GPIOE消抖时钟分频(GPIOE Debounce Clock Division) */
+ __IOM uint32_t PFDIV : 8; /*!< [15..8] GPIOF消抖时钟分频(GPIOF Debounce Clock Division) */
+ uint32_t : 16;
+ } PCDR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t PCDR2; /*!< (@ 0x00000048) Peripheral Function Clock Division Register2 */
+
+ struct {
+ __IOM uint32_t PWMDIV : 4; /*!< [3..0] PWM时钟分频选择(PWM Clock Division) */
+ __IOM uint32_t ADCDIV : 4; /*!< [7..4] ADC时钟分频选择(ADC Clock Division) */
+ __IOM uint32_t USBDIV : 4; /*!< [11..8] USB时钟分频选择(USB Clock Division) */
+ __IOM uint32_t CANDIV : 4; /*!< [15..12] CAN时钟分频选择(CAN Clock Division) */
+ uint32_t : 16;
+ } PCDR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t PCENR; /*!< (@ 0x0000004C) Peripheral Function Clock Enable Register */
+
+ struct {
+ __IOM uint32_t ADC0FEN : 1; /*!< [0..0] ADC0功能时钟使能(ADC0 Function Clock Enable) */
+ __IOM uint32_t ADC1FEN : 1; /*!< [1..1] ADC1功能时钟使能(ADC1 Function Clock Enable) */
+ __IOM uint32_t ADC2FEN : 1; /*!< [2..2] ADC2功能时钟使能(ADC2 Function Clock Enable) */
+ __IOM uint32_t ADC3FEN : 1; /*!< [3..3] ADC3功能时钟使能(ADC3 Function Clock Enable) */
+ __IOM uint32_t PWM0FEN : 1; /*!< [4..4] PWM0功能时钟使能(PWM0 Function Clock Enable) */
+ __IOM uint32_t PWM1FEN : 1; /*!< [5..5] PWM1功能时钟使能(PWM1 Function Clock Enable) */
+ __IOM uint32_t PWM2FEN : 1; /*!< [6..6] PWM2功能时钟使能(PWM2 Function Clock Enable) */
+ __IOM uint32_t PWM3FEN : 1; /*!< [7..7] PWM3功能时钟使能(PWM3 Function Clock Enable) */
+ __IOM uint32_t PWM4FEN : 1; /*!< [8..8] PWM4功能时钟使能(PWM4 Function Clock Enable) */
+ __IOM uint32_t PWM5FEN : 1; /*!< [9..9] PWM5功能时钟使能(PWM5 Function Clock Enable) */
+ __IOM uint32_t PWM6FEN : 1; /*!< [10..10] PWM6功能时钟使能(PWM6 Function Clock Enable) */
+ __IOM uint32_t PWM7FEN : 1; /*!< [11..11] PWM7功能时钟使能(PWM7 Function Clock Enable) */
+ __IOM uint32_t USBFEN : 1; /*!< [12..12] USB功能时钟使能(USB Function Clock Enable) */
+ __IOM uint32_t CAN0FEN : 1; /*!< [13..13] CAN0功能时钟使能(CAN0 Function Clock Enable) */
+ __IOM uint32_t CAN1FEN : 1; /*!< [14..14] CAN1功能时钟使能(CAN1 Function Clock Enable) */
+ __IOM uint32_t TMR6FEN : 1; /*!< [15..15] TMR6功能时钟使能(TMR6 Function Clock Enable) */
+ uint32_t : 16;
+ } PCENR_b;
+ } ;
+
+ union {
+ __IOM uint32_t APB0ENR; /*!< (@ 0x00000050) APB0 Peripheral Clock Enable Register */
+
+ struct {
+ __IOM uint32_t I2C0EN : 1; /*!< [0..0] I2C0时钟使能(I2C0 Clock Enable) */
+ __IOM uint32_t I2C1EN : 1; /*!< [1..1] I2C1时钟使能(I2C1 Clock Enable) */
+ __IOM uint32_t I2C2EN : 1; /*!< [2..2] I2C2时钟使能(I2C2 Clock Enable) */
+ __IOM uint32_t UART0EN : 1; /*!< [3..3] UART0时钟使能(UART0 Clock Enable) */
+ __IOM uint32_t UART1EN : 1; /*!< [4..4] UART1时钟使能(UART1 Clock Enable) */
+ __IOM uint32_t UART2EN : 1; /*!< [5..5] UART2时钟使能(UART2 Clock Enable) */
+ __IOM uint32_t TMR7EN : 1; /*!< [6..6] TMR7时钟使能(TMR7 Clock Enable) */
+ __IOM uint32_t TMR8EN : 1; /*!< [7..7] TMR8时钟使能(TMR8 Clock Enable) */
+ __IOM uint32_t TMR6EN : 1; /*!< [8..8] TMR6时钟使能(TMR6 Clock Enable) */
+ uint32_t : 23;
+ } APB0ENR_b;
+ } ;
+
+ union {
+ __IOM uint32_t APB1ENR; /*!< (@ 0x00000054) APB1 Peripheral Clock Enable Register */
+
+ struct {
+ __IOM uint32_t UART3EN : 1; /*!< [0..0] UART3时钟使能(UART3 Clock Enable) */
+ __IOM uint32_t UART4EN : 1; /*!< [1..1] UART4时钟使能(UART4 Clock Enable) */
+ __IOM uint32_t SPI0EN : 1; /*!< [2..2] SPI0时钟使能(SPI0 Clock Enable) */
+ __IOM uint32_t SPI1EN : 1; /*!< [3..3] SPI1时钟使能(SPI1 Clock Enable) */
+ __IOM uint32_t CAN0EN : 1; /*!< [4..4] CAN0时钟使能(CAN0 Clock Enable) */
+ __IOM uint32_t CAN1EN : 1; /*!< [5..5] CAN1时钟使能(CAN1 Clock Enable) */
+ __IOM uint32_t XIFEN : 1; /*!< [6..6] XIF时钟使能(XIF Clock Enable) */
+ __IOM uint32_t PDM0EN : 1; /*!< [7..7] PDM0时钟使能(PDM0 Clock Enable) */
+ __IOM uint32_t PDM1EN : 1; /*!< [8..8] PDM1时钟使能(PDM1 Clock Enable) */
+ __IOM uint32_t PDM2EN : 1; /*!< [9..9] PDM2时钟使能(PDM2 Clock Enable) */
+ __IOM uint32_t PDM3EN : 1; /*!< [10..10] PDM3时钟使能(PDM3 Clock Enable) */
+ __IOM uint32_t TMR0EN : 1; /*!< [11..11] TMR0时钟使能(TMR0 Clock Enable) */
+ __IOM uint32_t TMR1EN : 1; /*!< [12..12] TMR1时钟使能(TMR1 Clock Enable) */
+ __IOM uint32_t TMR2EN : 1; /*!< [13..13] TMR2时钟使能(TMR2 Clock Enable) */
+ uint32_t : 18;
+ } APB1ENR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AHB0ENR; /*!< (@ 0x00000058) AHB0 Peripheral Clock Enable Register */
+
+ struct {
+ __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA时钟使能(DMA Clock Enable) */
+ __IOM uint32_t FLSEN : 1; /*!< [1..1] FLASH时钟使能(FLASH Clock Enable) */
+ __IOM uint32_t PAEN : 1; /*!< [2..2] GPIOA时钟使能(GPIOA Clock Enable) */
+ __IOM uint32_t PBEN : 1; /*!< [3..3] GPIOB时钟使能(GPIOB Clock Enable) */
+ __IOM uint32_t PCEN : 1; /*!< [4..4] GPIOC时钟使能(GPIOC Clock Enable) */
+ __IOM uint32_t PDEN : 1; /*!< [5..5] GPIOD时钟使能(GPIOD Clock Enable) */
+ __IOM uint32_t PEEN : 1; /*!< [6..6] GPIOE时钟使能(GPIOE Clock Enable) */
+ __IOM uint32_t PFEN : 1; /*!< [7..7] GPIOF时钟使能(GPIOF Clock Enable) */
+ __IOM uint32_t TMR3EN : 1; /*!< [8..8] TMR3时钟使能(TMR3 Clock Enable) */
+ __IOM uint32_t TMR4EN : 1; /*!< [9..9] TMR4时钟使能(TMR4 Clock Enable) */
+ __IOM uint32_t QEI0EN : 1; /*!< [10..10] QEI0时钟使能(QEI0 Clock Enable) */
+ __IOM uint32_t QEI1EN : 1; /*!< [11..11] QEI1时钟使能(QEI1 Clock Enable) */
+ __IOM uint32_t QEI2EN : 1; /*!< [12..12] QEI2时钟使能(QEI2 Clock Enable) */
+ uint32_t : 19;
+ } AHB0ENR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AHB1ENR; /*!< (@ 0x0000005C) AHB1 Peripheral Clock Enable Register */
+
+ struct {
+ __IOM uint32_t TMR9EN : 1; /*!< [0..0] TMR9时钟使能(TMR9 Clock Enable) */
+ __IOM uint32_t TMR10EN : 1; /*!< [1..1] TMR10时钟使能(TMR10 Clock Enable) */
+ __IOM uint32_t USBEN : 1; /*!< [2..2] USB时钟使能(USB Clock Enable) */
+ __IOM uint32_t ADC0EN : 1; /*!< [3..3] ADC0时钟使能(ADC0 Clock Enable) */
+ __IOM uint32_t ADC1EN : 1; /*!< [4..4] ADC1时钟使能(ADC1 Clock Enable) */
+ __IOM uint32_t ADC2EN : 1; /*!< [5..5] ADC2时钟使能(ADC2 Clock Enable) */
+ __IOM uint32_t ADC3EN : 1; /*!< [6..6] ADC3时钟使能(ADC3 Clock Enable) */
+ __IOM uint32_t DACxEN : 1; /*!< [7..7] DACx时钟使能(DACx Clock Enable) */
+ __IOM uint32_t CMPxEN : 1; /*!< [8..8] CMPx时钟使能(CMPx Clock Enable) */
+ __IOM uint32_t PWM0EN : 1; /*!< [9..9] PWM0时钟使能(PWM0 Clock Enable) */
+ __IOM uint32_t PWM1EN : 1; /*!< [10..10] PWM1时钟使能(PWM1 Clock Enable) */
+ __IOM uint32_t PWM2EN : 1; /*!< [11..11] PWM2时钟使能(PWM2 Clock Enable) */
+ __IOM uint32_t PWM3EN : 1; /*!< [12..12] PWM3时钟使能(PWM3 Clock Enable) */
+ __IOM uint32_t PWM4EN : 1; /*!< [13..13] PWM4时钟使能(PWM4 Clock Enable) */
+ __IOM uint32_t PWM5EN : 1; /*!< [14..14] PWM5时钟使能(PWM5 Clock Enable) */
+ __IOM uint32_t PWM6EN : 1; /*!< [15..15] PWM6时钟使能(PWM6 Clock Enable) */
+ __IOM uint32_t PWM7EN : 1; /*!< [16..16] PWM7时钟使能(PWM7 Clock Enable) */
+ __IOM uint32_t IIR0EN : 1; /*!< [17..17] IIR0时钟使能(IIR0 Clock Enable) */
+ __IOM uint32_t IIR1EN : 1; /*!< [18..18] IIR1时钟使能(IIR1 Clock Enable) */
+ __IOM uint32_t IIR2EN : 1; /*!< [19..19] IIR2时钟使能(IIR2 Clock Enable) */
+ __IOM uint32_t IIR3EN : 1; /*!< [20..20] IIR3时钟使能(IIR3 Clock Enable) */
+ __IOM uint32_t IIR4EN : 1; /*!< [21..21] IIR4时钟使能(IIR4 Clock Enable) */
+ __IOM uint32_t IIR5EN : 1; /*!< [22..22] IIR5时钟使能(IIR5 Clock Enable) */
+ __IOM uint32_t CORDICEN : 1; /*!< [23..23] CORDIC时钟使能(CORDIC Clock Enable) */
+ uint32_t : 8;
+ } AHB1ENR_b;
+ } ;
+
+ union {
+ __IOM uint32_t APB0RSTR; /*!< (@ 0x00000060) APB0 Peripheral Reset Register */
+
+ struct {
+ __IOM uint32_t I2C0RST : 1; /*!< [0..0] I2C0复位控制(I2C0 Reset) */
+ __IOM uint32_t I2C1RST : 1; /*!< [1..1] I2C1复位控制(I2C1 Reset) */
+ __IOM uint32_t I2C2RST : 1; /*!< [2..2] I2C2复位控制(I2C2 Reset) */
+ __IOM uint32_t UART0RST : 1; /*!< [3..3] UART0复位控制(UART0 Reset) */
+ __IOM uint32_t UART1RST : 1; /*!< [4..4] UART1复位控制(UART1 Reset) */
+ __IOM uint32_t UART2RST : 1; /*!< [5..5] UART2复位控制(UART2 Reset) */
+ __IOM uint32_t TMR7RST : 1; /*!< [6..6] TMR7复位控制(TMR7 Reset) */
+ __IOM uint32_t TMR8RST : 1; /*!< [7..7] TMR8复位控制(TMR8 Reset) */
+ __IOM uint32_t TMR6RST : 1; /*!< [8..8] TMR6复位控制(TMR6 Reset) */
+ uint32_t : 23;
+ } APB0RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t APB1RSTR; /*!< (@ 0x00000064) APB1 Peripheral Reset Register */
+
+ struct {
+ __IOM uint32_t UART3RST : 1; /*!< [0..0] UART3复位控制(UART3 Reset) */
+ __IOM uint32_t UART4RST : 1; /*!< [1..1] UART4复位控制(UART4 Reset) */
+ __IOM uint32_t SPI0RST : 1; /*!< [2..2] SPI0复位控制(SPI0 Reset) */
+ __IOM uint32_t SPI1RST : 1; /*!< [3..3] SPI1复位控制(SPI1 Reset) */
+ __IOM uint32_t CAN0RST : 1; /*!< [4..4] CAN0复位控制(CAN0 Reset) */
+ __IOM uint32_t CAN1RST : 1; /*!< [5..5] CAN1复位控制(CAN1 Reset) */
+ __IOM uint32_t XIFRST : 1; /*!< [6..6] XIF复位控制(XIF Reset) */
+ __IOM uint32_t PDM0RST : 1; /*!< [7..7] PDM0复位控制(PDM0 Reset) */
+ __IOM uint32_t PDM1RST : 1; /*!< [8..8] PDM1复位控制(PDM1 Reset) */
+ __IOM uint32_t PDM2RST : 1; /*!< [9..9] PDM2复位控制(PDM2 Reset) */
+ __IOM uint32_t PDM3RST : 1; /*!< [10..10] PDM3复位控制(PDM3 Reset) */
+ __IOM uint32_t TMR0RST : 1; /*!< [11..11] TMR0复位控制(TMR0 Reset) */
+ __IOM uint32_t TMR1RST : 1; /*!< [12..12] TMR1复位控制(TMR1 Reset) */
+ __IOM uint32_t TMR2RST : 1; /*!< [13..13] TMR2复位控制(TMR1 Reset) */
+ uint32_t : 18;
+ } APB1RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AHB0RSTR; /*!< (@ 0x00000068) AHB0 Peripheral Reset Register */
+
+ struct {
+ __IOM uint32_t DMARST : 1; /*!< [0..0] DMA复位控制(DMA Reset) */
+ __IOM uint32_t FLSRST : 1; /*!< [1..1] FLASH复位控制(FLASH Reset) */
+ __IOM uint32_t PARST : 1; /*!< [2..2] GPIOA复位控制(GPIOA Reset) */
+ __IOM uint32_t PBRST : 1; /*!< [3..3] GPIOB复位控制(GPIOB Reset) */
+ __IOM uint32_t PCRST : 1; /*!< [4..4] GPIOC复位控制(GPIOC Reset) */
+ __IOM uint32_t PDRST : 1; /*!< [5..5] GPIOD复位控制(GPIOD Reset) */
+ __IOM uint32_t PERST : 1; /*!< [6..6] GPIOE复位控制(GPIOE Reset) */
+ __IOM uint32_t PFRST : 1; /*!< [7..7] GPIOF复位控制(GPIOF Reset) */
+ __IOM uint32_t TMR3RST : 1; /*!< [8..8] TMR3复位控制(TMR3 Reset) */
+ __IOM uint32_t TMR4RST : 1; /*!< [9..9] TMR4复位控制(TMR4 Reset) */
+ __IOM uint32_t QEI0RST : 1; /*!< [10..10] QEI0复位控制(QEI0 Reset) */
+ __IOM uint32_t QEI1RST : 1; /*!< [11..11] QEI1复位控制(QEI1 Reset) */
+ __IOM uint32_t QEI2RST : 1; /*!< [12..12] QEI2复位控制(QEI2 Reset) */
+ uint32_t : 19;
+ } AHB0RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AHB1RSTR; /*!< (@ 0x0000006C) AHB1 Peripheral Reset Register */
+
+ struct {
+ __IOM uint32_t TMR9RST : 1; /*!< [0..0] TMR9复位控制(TMR9 Reset) */
+ __IOM uint32_t TMR10RST : 1; /*!< [1..1] TMR10复位控制(TMR10 Reset) */
+ __IOM uint32_t USBRST : 1; /*!< [2..2] USB复位控制(USB Reset) */
+ __IOM uint32_t ADCRST : 1; /*!< [3..3] ADC复位控制(ADC Reset) */
+ __IOM uint32_t DACRST : 1; /*!< [4..4] DAC复位控制(DAC Reset) */
+ __IOM uint32_t CMPRST : 1; /*!< [5..5] CMP复位控制(CMP Reset) */
+ __IOM uint32_t PWMRST : 1; /*!< [6..6] PWM复位控制(PWM Reset) */
+ __IOM uint32_t IIR0RST : 1; /*!< [7..7] IIR0复位控制(IIR0 Reset) */
+ __IOM uint32_t IIR1RST : 1; /*!< [8..8] IIR1复位控制(IIR1 Reset) */
+ __IOM uint32_t IIR2RST : 1; /*!< [9..9] IIR2复位控制(IIR2 Reset) */
+ __IOM uint32_t IIR3RST : 1; /*!< [10..10] IIR3复位控制(IIR3 Reset) */
+ __IOM uint32_t IIR4RST : 1; /*!< [11..11] IIR4复位控制(IIR4 Reset) */
+ __IOM uint32_t IIR5RST : 1; /*!< [12..12] IIR5复位控制(IIR5 Reset) */
+ __IOM uint32_t CORDICRST : 1; /*!< [13..13] CORDIC复位控制(CORDIC Reset) */
+ uint32_t : 18;
+ } AHB1RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t XOSCCR; /*!< (@ 0x00000070) XOSC Control Register */
+
+ struct {
+ __IOM uint32_t XEN : 1; /*!< [0..0] HSE使能(HSE Enable) */
+ __IOM uint32_t XDR : 3; /*!< [3..1] HSE启动电流配置(HSE Charge Pump Selection) */
+ __IOM uint32_t HEN : 1; /*!< [4..4] HSI使能(HSI Enable) */
+ uint32_t : 27;
+ } XOSCCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CSSCR; /*!< (@ 0x00000074) Clock Secure Control Register */
+
+ struct {
+ __IOM uint32_t SWE : 1; /*!< [0..0] 外部晶振安全监测使能(XOSC Securce Switch Enable) */
+ __IOM uint32_t SSE : 1; /*!< [1..1] 系统时钟切换使能(SYSCLK Switch Enable) */
+ __IOM uint32_t LPE : 1; /*!< [2..2] 外部晶振异常NMI中断使能(XOSC Loss NMI Enable) */
+ __IM uint32_t LPD : 1; /*!< [3..3] 外部晶振异常NMI中断状态(XOSC Loss Pending) */
+ __IOM uint32_t WIN : 2; /*!< [5..4] XOSC计数窗口宽度调整(XOSC AutoSwitch Window Width) */
+ __IOM uint32_t LMT : 2; /*!< [7..6] XOSC比较阈值宽度(XOSC Limit Window Width) */
+ uint32_t : 24;
+ } CSSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DBGCR; /*!< (@ 0x00000078) Internal Clock Fanout Register */
+
+ struct {
+ __IOM uint32_t MCO : 3; /*!< [2..0] 芯片内部时钟输出源选择(Internal Clock Fanout
+ Source) */
+ uint32_t : 1;
+ __IOM uint32_t MCOEN : 1; /*!< [4..4] 芯片内部时钟输出使能(Internal Clock Fanout
+ Enable) */
+ __IOM uint32_t ECIE : 1; /*!< [5..5] 芯片外部时钟输入使能(External Clock Input Enable) */
+ uint32_t : 26;
+ } DBGCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRSTSR; /*!< (@ 0x0000007C) System RstStatus Register */
+
+ struct {
+ __IOM uint32_t MCR : 1; /*!< [0..0] MCLR复位标志位(MCLR Reset Status) */
+ __IOM uint32_t LPR : 1; /*!< [1..1] LVD复位标志位(LVD Reset Status) */
+ __IOM uint32_t SQR : 1; /*!< [2..2] SystemREQ复位标志位(SystemREQ Reset Status) */
+ __IOM uint32_t LKR : 1; /*!< [3..3] LOCKUP复位标志位(LOCKUP Reset Status) */
+ __IOM uint32_t IWR : 1; /*!< [4..4] IWDG复位标志位(IWDG Reset Status) */
+ __IOM uint32_t WWR : 1; /*!< [5..5] WWDG复位标志位(WWDG Reset Status) */
+ uint32_t : 2;
+ __IOM uint32_t SQRSTE : 1; /*!< [8..8] SystemREQ Reset Enable */
+ __IOM uint32_t LKRSTE : 1; /*!< [9..9] LKUP Reset Enable */
+ __IOM uint32_t WWRSTE : 1; /*!< [10..10] WWDG Reset Enable */
+ __IOM uint32_t IWRSTE : 1; /*!< [11..11] IWDG Reset Enable */
+ uint32_t : 20;
+ } SRSTSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t KEYR; /*!< (@ 0x00000080) LockKey Register */
+
+ struct {
+ __IOM uint32_t KEY : 1; /*!< [0..0] 寄存器写保护(Register LockKey) */
+ uint32_t : 31;
+ } KEYR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRSR; /*!< (@ 0x00000084) System Reset Status Register */
+
+ struct {
+ __IOM uint32_t MCR : 1; /*!< [0..0] MCLR复位标志位(MCLR Reset Status) */
+ __IOM uint32_t LPR : 1; /*!< [1..1] LVD复位标志位(LVD Reset Status) */
+ __IOM uint32_t SQR : 1; /*!< [2..2] SystemREQ复位标志位(SystemREQ Reset Status) */
+ __IOM uint32_t LKR : 1; /*!< [3..3] LOCKUP复位标志位(LOCKUP Reset Status) */
+ __IOM uint32_t IWR : 1; /*!< [4..4] IWDG复位标志位(IWDG Reset Status) */
+ __IOM uint32_t WWR : 1; /*!< [5..5] WWDG复位标志位(WWDG Reset Status) */
+ uint32_t : 26;
+ } SRSR_b;
+ } ;
+} RCU_Type; /*!< Size = 136 (0x88) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ QEI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief QEI0 (QEI0)
+ */
+
+typedef struct { /*!< (@ 0x4002D000) QEI0 Structure */
+
+ union {
+ __IOM uint32_t POSCNT; /*!< (@ 0x00000000) QEI Position Counter Register */
+
+ struct {
+ __IOM uint32_t POSCNT : 32; /*!< [31..0] QEI位置计数寄存器(QEI Position Counter Register) */
+ } POSCNT_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSINIT; /*!< (@ 0x00000004) QEI Position Counter Initial Register */
+
+ struct {
+ __IOM uint32_t POSINIT : 32; /*!< [31..0] QEI位置初始化寄存器(QEI Position Counter Initial
+ Register) */
+ } POSINIT_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSMAX; /*!< (@ 0x00000008) QEI Position Counter Max Register */
+
+ struct {
+ __IOM uint32_t POSMAX : 32; /*!< [31..0] QEI位置最大值寄存器(QEI Position Counter Max
+ Register) */
+ } POSMAX_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSCMP; /*!< (@ 0x0000000C) QEI Position Counter Compare Register */
+
+ struct {
+ __IOM uint32_t POSCMP : 32; /*!< [31..0] QEI位置比较值寄存器 (QEI Position Counter Compare
+ Register) */
+ } POSCMP_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSILAT; /*!< (@ 0x00000010) QEI Position Counter Index Latch Register */
+
+ struct {
+ __IM uint32_t POSILAT : 32; /*!< [31..0] QEI位置索引锁存寄存器 (QEI Position Counter
+ Index Latch Register) */
+ } POSILAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSLAT; /*!< (@ 0x00000014) QEI Position Counter Timer Latch Register */
+
+ struct {
+ __IM uint32_t POSLAT : 32; /*!< [31..0] QEI位置定时锁存寄存器 (QEI Position Counter
+ Timer Latch Register) */
+ } POSLAT_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t UTMR; /*!< (@ 0x00000020) QTIMER Counter Register */
+
+ struct {
+ __IOM uint32_t UTMR : 32; /*!< [31..0] QEI定时计数寄存器 (QEI Timer Counter Register） */
+ } UTMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UPRD; /*!< (@ 0x00000024) QTIMER Counter Period Register */
+
+ struct {
+ __IOM uint32_t UPRD : 32; /*!< [31..0] QEI定时周期寄存器 (QEI Timer Counter Period Register） */
+ } UPRD_b;
+ } ;
+ __IM uint32_t RESERVED1[2];
+
+ union {
+ __IOM uint32_t DECCTL; /*!< (@ 0x00000030) QEI Decoder Control Register */
+
+ struct {
+ __IOM uint32_t QIP : 1; /*!< [0..0] QEI Index信号输入极性选择（QEI Index Input Polarity） */
+ uint32_t : 1;
+ __IOM uint32_t QAP : 1; /*!< [2..2] QEI QEA信号输入极性选择（QEI QEA Input Polarity） */
+ __IOM uint32_t QBP : 1; /*!< [3..3] QEI QEB信号输入极性选择（QEI QEB Input Polarity） */
+ __IOM uint32_t SWAP : 1; /*!< [4..4] QEI正交时钟交换控制（QEI QEA/B SWAP Enable） */
+ __IOM uint32_t IGATE : 1; /*!< [5..5] QEI索引信号使能（QEI Index Gate Enable） */
+ __IOM uint32_t XCR : 1; /*!< [6..6] QEI时钟速率控制（QEI Clock Rate Control） */
+ uint32_t : 5;
+ __IOM uint32_t QSRC : 2; /*!< [13..12] QEI位置计数器源选择（QEI Position-counter
+ Source Selection） */
+ __IOM uint32_t DCM : 1; /*!< [14..14] QEI方向计数模式（QEI Direction Counter Mode） */
+ uint32_t : 1;
+ __IOM uint32_t DBC : 8; /*!< [23..16] QEI去抖窗口设置（QEI Debounce Value） */
+ uint32_t : 8;
+ } DECCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t QEPCTL; /*!< (@ 0x00000034) QEI Contorl Register */
+
+ struct {
+ __IOM uint32_t QPE : 1; /*!< [0..0] QEI使能（QEI Enable） */
+ __IOM uint32_t UTE : 1; /*!< [1..1] QEI Timer使能（QEI Timer Enable） */
+ uint32_t : 2;
+ __IOM uint32_t IEL : 2; /*!< [5..4] QEI位置计数器索引锁存选择（QEI Position Counter
+ Index Latch Selection） */
+ __IOM uint32_t IEI : 2; /*!< [7..6] QEI位置计数器索引初始选择（QEI Position Counter
+ Index Initial Selection） */
+ __IOM uint32_t SWI : 1; /*!< [8..8] QEI位置计数器初始化使能（QEI Position Counter
+ Software Initial Enable） */
+ uint32_t : 3;
+ __IOM uint32_t PCRM : 2; /*!< [13..12] QEI位置计数器复位选择（QEI Position Counter
+ Reset Selection） */
+ uint32_t : 18;
+ } QEPCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSCTL; /*!< (@ 0x00000038) QEI Position Contorl Register */
+
+ struct {
+ __IOM uint32_t CCE : 1; /*!< [0..0] QEI位置计数比较使能（QEI Position Counter Compare
+ Enable） */
+ __IOM uint32_t PSE : 1; /*!< [1..1] QEI位置计数比较影子寄存器使能（QEI Position
+ Counter Compare Shadow Enable） */
+ uint32_t : 30;
+ } POSCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPCTL; /*!< (@ 0x0000003C) QEI Capture Control Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] QEI捕获使能（QEI Capture Enable） */
+ __IOM uint32_t CMD : 1; /*!< [1..1] QEI捕获锁存模式（QEI Capture Latch Mode） */
+ uint32_t : 2;
+ __IOM uint32_t CCPS : 3; /*!< [6..4] QEI捕获定时器分频（QEI Capture Timer Clock Division） */
+ uint32_t : 1;
+ __IOM uint32_t UPPS : 4; /*!< [11..8] QEI捕获事件分频（QEI Capture Position Event Division） */
+ uint32_t : 20;
+ } CAPCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t QCTMR; /*!< (@ 0x00000040) QEI Capture Counter Register */
+
+ struct {
+ __IOM uint32_t CTMR : 32; /*!< [31..0] QEI捕获计数寄存器 (QEI Capture Counter Register） */
+ } QCTMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t QCPRD; /*!< (@ 0x00000044) QEI Capture Period Register */
+
+ struct {
+ __IM uint32_t CPRD : 32; /*!< [31..0] QEI捕获周期寄存器 (QEI Capture Period Register） */
+ } QCPRD_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTMRLAT; /*!< (@ 0x00000048) QEI Capture Counter Latch Register */
+
+ struct {
+ __IM uint32_t CTMRLAT : 32; /*!< [31..0] QEI捕获计数锁存寄存器 (QEI Compare Counter
+ Latch Register） */
+ } CTMRLAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPRDLAT; /*!< (@ 0x0000004C) QEI Capture Period Latch Register */
+
+ struct {
+ __IM uint32_t CPRDLAT : 32; /*!< [31..0] QEI捕获周期锁存寄存器 (QEI Capture Period Latch
+ Register） */
+ } CPRDLAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t IENR; /*!< (@ 0x00000050) QEI Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t PCE : 1; /*!< [0..0] QEI位置计数器错误中断使能（QEI Position Counter
+ Error Interrupt Enable） */
+ __IOM uint32_t QPE : 1; /*!< [1..1] QEI相位错误中断使能（QEI Phase Error Interrupt
+ Enable） */
+ __IOM uint32_t QDC : 1; /*!< [2..2] QEI正交方向变化中断使能（QEI Direction Change
+ Interrupt Enable） */
+ __IOM uint32_t PCU : 1; /*!< [3..3] QEI位置计数器下溢中断使能（QEI Position Counter
+ Underflow Interrupt Enable） */
+ __IOM uint32_t PCO : 1; /*!< [4..4] QEI位置计数器上溢中断使能（QEI Position Counter
+ Overflow Interrupt Enable） */
+ __IOM uint32_t PCM : 1; /*!< [5..5] QEI位置计数器比较中断使能（QEI Position Counter
+ Compare Interrupt Enable） */
+ __IOM uint32_t IEL : 1; /*!< [6..6] QEI位置计数器锁存中断使能（QEI Position Counter
+ Latch Interrupt Enable） */
+ __IOM uint32_t UTO : 1; /*!< [7..7] QEI定时器溢出中断使能（QEI Timer Overflow Interrupt
+ Enable） */
+ __IOM uint32_t PIE : 1; /*!< [8..8] QEI位置计数器初始化中断使能（QEI Position
+ Counter Initial Interrupt Enable） */
+ __IOM uint32_t PRE : 1; /*!< [9..9] QEI位置计数器复位中断使能（QEI Position Counter
+ Reset Interrupt Enable） */
+ __IOM uint32_t CDE : 1; /*!< [10..10] QEI Capture捕获成功中断使能（QEI Capture Done
+ Interrupt Enable） */
+ uint32_t : 21;
+ } IENR_b;
+ } ;
+
+ union {
+ __IOM uint32_t STSR; /*!< (@ 0x00000054) QEI Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t PCE : 1; /*!< [0..0] QEI位置计数器错误标志位（QEI Position Counter
+ Error Interrupt Status） */
+ __IOM uint32_t PHE : 1; /*!< [1..1] QEI相位错误标志位（QEI Phase Error Interrupt
+ Status） */
+ __IOM uint32_t QDC : 1; /*!< [2..2] QEI正交方向变化标志位（QEI Direction Change
+ Interrupt Status） */
+ __IOM uint32_t PCU : 1; /*!< [3..3] QEI位置计数器下溢标志位（QEI Position Counter
+ Underflow Interrupt Status） */
+ __IOM uint32_t PCO : 1; /*!< [4..4] QEI位置计数器上溢标志位（QEI Position Counter
+ Overflow Interrupt Status） */
+ __IOM uint32_t PCM : 1; /*!< [5..5] QEI位置计数器比较成功标志位（QEI Position
+ Counter Compare Interrupt Status） */
+ __IOM uint32_t IEL : 1; /*!< [6..6] QEI位置计数器锁存标志位（QEI Position Counter
+ Latch Interrupt Status） */
+ __IOM uint32_t UTO : 1; /*!< [7..7] QEI定时器溢出标志位（QEI Timer Overflow Interrupt
+ Status） */
+ __IOM uint32_t PIS : 1; /*!< [8..8] QEI位置计数器初始化标志位（QEI Position Counter
+ Initial Interrupt Status） */
+ __IOM uint32_t PRS : 1; /*!< [9..9] QEI位置计数器复位标志位（QEI Position Counter
+ Reset Interrupt Status） */
+ __IOM uint32_t CDS : 1; /*!< [10..10] QEI Capture捕获成功状态标志位（QEI Capture
+ Done Interrupt Status） */
+ __IM uint32_t FIS : 1; /*!< [11..11] QEI出现首次索引标志位（QEI The First Index
+ Status） */
+ __IOM uint32_t CDE : 1; /*!< [12..12] QEI捕获方向错误标志位（QEI Capture Direction
+ Error Status） */
+ __IOM uint32_t COE : 1; /*!< [13..13] QEI捕获上溢错误标志位（QEI Capture Overflow
+ Error Status） */
+ __IM uint32_t QDS : 1; /*!< [14..14] QEI实时电机转向标志位（QEI Direction Status） */
+ __IM uint32_t QDI : 1; /*!< [15..15] QEI每次电机转向标志位（QEI Direction Index
+ Latch Status） */
+ __IM uint32_t QDF : 1; /*!< [16..16] QEI首次电机转向标志位（QEI Direction First
+ Index Status） */
+ uint32_t : 15;
+ } STSR_b;
+ } ;
+} QEI0_Type; /*!< Size = 88 (0x58) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ QEI1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief QEI1 (QEI1)
+ */
+
+typedef struct { /*!< (@ 0x4002E000) QEI1 Structure */
+
+ union {
+ __IOM uint32_t POSCNT; /*!< (@ 0x00000000) QEI Position Counter Register */
+
+ struct {
+ __IOM uint32_t POSCNT : 32; /*!< [31..0] QEI位置计数寄存器(QEI Position Counter Register) */
+ } POSCNT_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSINIT; /*!< (@ 0x00000004) QEI Position Counter Initial Register */
+
+ struct {
+ __IOM uint32_t POSINIT : 32; /*!< [31..0] QEI位置初始化寄存器(QEI Position Counter Initial
+ Register) */
+ } POSINIT_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSMAX; /*!< (@ 0x00000008) QEI Position Counter Max Register */
+
+ struct {
+ __IOM uint32_t POSMAX : 32; /*!< [31..0] QEI位置最大值寄存器(QEI Position Counter Max
+ Register) */
+ } POSMAX_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSCMP; /*!< (@ 0x0000000C) QEI Position Counter Compare Register */
+
+ struct {
+ __IOM uint32_t POSCMP : 32; /*!< [31..0] QEI位置比较值寄存器 (QEI Position Counter Compare
+ Register) */
+ } POSCMP_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSILAT; /*!< (@ 0x00000010) QEI Position Counter Index Latch Register */
+
+ struct {
+ __IM uint32_t POSILAT : 32; /*!< [31..0] QEI位置索引锁存寄存器 (QEI Position Counter
+ Index Latch Register) */
+ } POSILAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSLAT; /*!< (@ 0x00000014) QEI Position Counter Timer Latch Register */
+
+ struct {
+ __IM uint32_t POSLAT : 32; /*!< [31..0] QEI位置定时锁存寄存器 (QEI Position Counter
+ Timer Latch Register) */
+ } POSLAT_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t UTMR; /*!< (@ 0x00000020) QTIMER Counter Register */
+
+ struct {
+ __IOM uint32_t UTMR : 32; /*!< [31..0] QEI定时计数寄存器 (QEI Timer Counter Register） */
+ } UTMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UPRD; /*!< (@ 0x00000024) QTIMER Counter Period Register */
+
+ struct {
+ __IOM uint32_t UPRD : 32; /*!< [31..0] QEI定时周期寄存器 (QEI Timer Counter Period Register） */
+ } UPRD_b;
+ } ;
+ __IM uint32_t RESERVED1[2];
+
+ union {
+ __IOM uint32_t DECCTL; /*!< (@ 0x00000030) QEI Decoder Control Register */
+
+ struct {
+ __IOM uint32_t QIP : 1; /*!< [0..0] QEI Index信号输入极性选择（QEI Index Input Polarity） */
+ uint32_t : 1;
+ __IOM uint32_t QAP : 1; /*!< [2..2] QEI QEA信号输入极性选择（QEI QEA Input Polarity） */
+ __IOM uint32_t QBP : 1; /*!< [3..3] QEI QEB信号输入极性选择（QEI QEB Input Polarity） */
+ __IOM uint32_t SWAP : 1; /*!< [4..4] QEI正交时钟交换控制（QEI QEA/B SWAP Enable） */
+ __IOM uint32_t IGATE : 1; /*!< [5..5] QEI索引信号使能（QEI Index Gate Enable） */
+ __IOM uint32_t XCR : 1; /*!< [6..6] QEI时钟速率控制（QEI Clock Rate Control） */
+ uint32_t : 5;
+ __IOM uint32_t QSRC : 2; /*!< [13..12] QEI位置计数器源选择（QEI Position-counter
+ Source Selection） */
+ __IOM uint32_t DCM : 1; /*!< [14..14] QEI方向计数模式（QEI Direction Counter Mode） */
+ uint32_t : 1;
+ __IOM uint32_t DBC : 8; /*!< [23..16] QEI去抖窗口设置（QEI Debounce Value） */
+ uint32_t : 8;
+ } DECCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t QEPCTL; /*!< (@ 0x00000034) QEI Contorl Register */
+
+ struct {
+ __IOM uint32_t QPE : 1; /*!< [0..0] QEI使能（QEI Enable） */
+ __IOM uint32_t UTE : 1; /*!< [1..1] QEI Timer使能（QEI Timer Enable） */
+ uint32_t : 2;
+ __IOM uint32_t IEL : 2; /*!< [5..4] QEI位置计数器索引锁存选择（QEI Position Counter
+ Index Latch Selection） */
+ __IOM uint32_t IEI : 2; /*!< [7..6] QEI位置计数器索引初始选择（QEI Position Counter
+ Index Initial Selection） */
+ __IOM uint32_t SWI : 1; /*!< [8..8] QEI位置计数器初始化使能（QEI Position Counter
+ Software Initial Enable） */
+ uint32_t : 3;
+ __IOM uint32_t PCRM : 2; /*!< [13..12] QEI位置计数器复位选择（QEI Position Counter
+ Reset Selection） */
+ uint32_t : 18;
+ } QEPCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSCTL; /*!< (@ 0x00000038) QEI Position Contorl Register */
+
+ struct {
+ __IOM uint32_t CCE : 1; /*!< [0..0] QEI位置计数比较使能（QEI Position Counter Compare
+ Enable） */
+ __IOM uint32_t PSE : 1; /*!< [1..1] QEI位置计数比较影子寄存器使能（QEI Position
+ Counter Compare Shadow Enable） */
+ uint32_t : 30;
+ } POSCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPCTL; /*!< (@ 0x0000003C) QEI Capture Control Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] QEI捕获使能（QEI Capture Enable） */
+ __IOM uint32_t CMD : 1; /*!< [1..1] QEI捕获锁存模式（QEI Capture Latch Mode） */
+ uint32_t : 2;
+ __IOM uint32_t CCPS : 3; /*!< [6..4] QEI捕获定时器分频（QEI Capture Timer Clock Division） */
+ uint32_t : 1;
+ __IOM uint32_t UPPS : 4; /*!< [11..8] QEI捕获事件分频（QEI Capture Position Event Division） */
+ uint32_t : 20;
+ } CAPCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t QCTMR; /*!< (@ 0x00000040) QEI Capture Counter Register */
+
+ struct {
+ __IOM uint32_t CTMR : 32; /*!< [31..0] QEI捕获计数寄存器 (QEI Capture Counter Register） */
+ } QCTMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t QCPRD; /*!< (@ 0x00000044) QEI Capture Period Register */
+
+ struct {
+ __IM uint32_t CPRD : 32; /*!< [31..0] QEI捕获周期寄存器 (QEI Capture Period Register） */
+ } QCPRD_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTMRLAT; /*!< (@ 0x00000048) QEI Capture Counter Latch Register */
+
+ struct {
+ __IM uint32_t CTMRLAT : 32; /*!< [31..0] QEI捕获计数锁存寄存器 (QEI Compare Counter
+ Latch Register） */
+ } CTMRLAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPRDLAT; /*!< (@ 0x0000004C) QEI Capture Period Latch Register */
+
+ struct {
+ __IM uint32_t CPRDLAT : 32; /*!< [31..0] QEI捕获周期锁存寄存器 (QEI Capture Period Latch
+ Register） */
+ } CPRDLAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t IENR; /*!< (@ 0x00000050) QEI Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t PCE : 1; /*!< [0..0] QEI位置计数器错误中断使能（QEI Position Counter
+ Error Interrupt Enable） */
+ __IOM uint32_t QPE : 1; /*!< [1..1] QEI相位错误中断使能（QEI Phase Error Interrupt
+ Enable） */
+ __IOM uint32_t QDC : 1; /*!< [2..2] QEI正交方向变化中断使能（QEI Direction Change
+ Interrupt Enable） */
+ __IOM uint32_t PCU : 1; /*!< [3..3] QEI位置计数器下溢中断使能（QEI Position Counter
+ Underflow Interrupt Enable） */
+ __IOM uint32_t PCO : 1; /*!< [4..4] QEI位置计数器上溢中断使能（QEI Position Counter
+ Overflow Interrupt Enable） */
+ __IOM uint32_t PCM : 1; /*!< [5..5] QEI位置计数器比较中断使能（QEI Position Counter
+ Compare Interrupt Enable） */
+ __IOM uint32_t IEL : 1; /*!< [6..6] QEI位置计数器锁存中断使能（QEI Position Counter
+ Latch Interrupt Enable） */
+ __IOM uint32_t UTO : 1; /*!< [7..7] QEI定时器溢出中断使能（QEI Timer Overflow Interrupt
+ Enable） */
+ __IOM uint32_t PIE : 1; /*!< [8..8] QEI位置计数器初始化中断使能（QEI Position
+ Counter Initial Interrupt Enable） */
+ __IOM uint32_t PRE : 1; /*!< [9..9] QEI位置计数器复位中断使能（QEI Position Counter
+ Reset Interrupt Enable） */
+ __IOM uint32_t CDE : 1; /*!< [10..10] QEI Capture捕获成功中断使能（QEI Capture Done
+ Interrupt Enable） */
+ uint32_t : 21;
+ } IENR_b;
+ } ;
+
+ union {
+ __IOM uint32_t STSR; /*!< (@ 0x00000054) QEI Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t PCE : 1; /*!< [0..0] QEI位置计数器错误标志位（QEI Position Counter
+ Error Interrupt Status） */
+ __IOM uint32_t PHE : 1; /*!< [1..1] QEI相位错误标志位（QEI Phase Error Interrupt
+ Status） */
+ __IOM uint32_t QDC : 1; /*!< [2..2] QEI正交方向变化标志位（QEI Direction Change
+ Interrupt Status） */
+ __IOM uint32_t PCU : 1; /*!< [3..3] QEI位置计数器下溢标志位（QEI Position Counter
+ Underflow Interrupt Status） */
+ __IOM uint32_t PCO : 1; /*!< [4..4] QEI位置计数器上溢标志位（QEI Position Counter
+ Overflow Interrupt Status） */
+ __IOM uint32_t PCM : 1; /*!< [5..5] QEI位置计数器比较成功标志位（QEI Position
+ Counter Compare Interrupt Status） */
+ __IOM uint32_t IEL : 1; /*!< [6..6] QEI位置计数器锁存标志位（QEI Position Counter
+ Latch Interrupt Status） */
+ __IOM uint32_t UTO : 1; /*!< [7..7] QEI定时器溢出标志位（QEI Timer Overflow Interrupt
+ Status） */
+ __IOM uint32_t PIS : 1; /*!< [8..8] QEI位置计数器初始化标志位（QEI Position Counter
+ Initial Interrupt Status） */
+ __IOM uint32_t PRS : 1; /*!< [9..9] QEI位置计数器复位标志位（QEI Position Counter
+ Reset Interrupt Status） */
+ __IOM uint32_t CDS : 1; /*!< [10..10] QEI Capture捕获成功状态标志位（QEI Capture
+ Done Interrupt Status） */
+ __IM uint32_t FIS : 1; /*!< [11..11] QEI出现首次索引标志位（QEI The First Index
+ Status） */
+ __IOM uint32_t CDE : 1; /*!< [12..12] QEI捕获方向错误标志位（QEI Capture Direction
+ Error Status） */
+ __IOM uint32_t COE : 1; /*!< [13..13] QEI捕获上溢错误标志位（QEI Capture Overflow
+ Error Status） */
+ __IM uint32_t QDS : 1; /*!< [14..14] QEI实时电机转向标志位（QEI Direction Status） */
+ __IM uint32_t QDI : 1; /*!< [15..15] QEI每次电机转向标志位（QEI Direction Index
+ Latch Status） */
+ __IM uint32_t QDF : 1; /*!< [16..16] QEI首次电机转向标志位（QEI Direction First
+ Index Status） */
+ uint32_t : 15;
+ } STSR_b;
+ } ;
+} QEI1_Type; /*!< Size = 88 (0x58) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ QEI2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief QEI2 (QEI2)
+ */
+
+typedef struct { /*!< (@ 0x4002F000) QEI2 Structure */
+
+ union {
+ __IOM uint32_t POSCNT; /*!< (@ 0x00000000) QEI Position Counter Register */
+
+ struct {
+ __IOM uint32_t POSCNT : 32; /*!< [31..0] QEI位置计数寄存器(QEI Position Counter Register) */
+ } POSCNT_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSINIT; /*!< (@ 0x00000004) QEI Position Counter Initial Register */
+
+ struct {
+ __IOM uint32_t POSINIT : 32; /*!< [31..0] QEI位置初始化寄存器(QEI Position Counter Initial
+ Register) */
+ } POSINIT_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSMAX; /*!< (@ 0x00000008) QEI Position Counter Max Register */
+
+ struct {
+ __IOM uint32_t POSMAX : 32; /*!< [31..0] QEI位置最大值寄存器(QEI Position Counter Max
+ Register) */
+ } POSMAX_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSCMP; /*!< (@ 0x0000000C) QEI Position Counter Compare Register */
+
+ struct {
+ __IOM uint32_t POSCMP : 32; /*!< [31..0] QEI位置比较值寄存器 (QEI Position Counter Compare
+ Register) */
+ } POSCMP_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSILAT; /*!< (@ 0x00000010) QEI Position Counter Index Latch Register */
+
+ struct {
+ __IM uint32_t POSILAT : 32; /*!< [31..0] QEI位置索引锁存寄存器 (QEI Position Counter
+ Index Latch Register) */
+ } POSILAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSLAT; /*!< (@ 0x00000014) QEI Position Counter Timer Latch Register */
+
+ struct {
+ __IM uint32_t POSLAT : 32; /*!< [31..0] QEI位置定时锁存寄存器 (QEI Position Counter
+ Timer Latch Register) */
+ } POSLAT_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t UTMR; /*!< (@ 0x00000020) QTIMER Counter Register */
+
+ struct {
+ __IOM uint32_t UTMR : 32; /*!< [31..0] QEI定时计数寄存器 (QEI Timer Counter Register） */
+ } UTMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UPRD; /*!< (@ 0x00000024) QTIMER Counter Period Register */
+
+ struct {
+ __IOM uint32_t UPRD : 32; /*!< [31..0] QEI定时周期寄存器 (QEI Timer Counter Period Register） */
+ } UPRD_b;
+ } ;
+ __IM uint32_t RESERVED1[2];
+
+ union {
+ __IOM uint32_t DECCTL; /*!< (@ 0x00000030) QEI Decoder Control Register */
+
+ struct {
+ __IOM uint32_t QIP : 1; /*!< [0..0] QEI Index信号输入极性选择（QEI Index Input Polarity） */
+ uint32_t : 1;
+ __IOM uint32_t QAP : 1; /*!< [2..2] QEI QEA信号输入极性选择（QEI QEA Input Polarity） */
+ __IOM uint32_t QBP : 1; /*!< [3..3] QEI QEB信号输入极性选择（QEI QEB Input Polarity） */
+ __IOM uint32_t SWAP : 1; /*!< [4..4] QEI正交时钟交换控制（QEI QEA/B SWAP Enable） */
+ __IOM uint32_t IGATE : 1; /*!< [5..5] QEI索引信号使能（QEI Index Gate Enable） */
+ __IOM uint32_t XCR : 1; /*!< [6..6] QEI时钟速率控制（QEI Clock Rate Control） */
+ uint32_t : 5;
+ __IOM uint32_t QSRC : 2; /*!< [13..12] QEI位置计数器源选择（QEI Position-counter
+ Source Selection） */
+ __IOM uint32_t DCM : 1; /*!< [14..14] QEI方向计数模式（QEI Direction Counter Mode） */
+ uint32_t : 1;
+ __IOM uint32_t DBC : 8; /*!< [23..16] QEI去抖窗口设置（QEI Debounce Value） */
+ uint32_t : 8;
+ } DECCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t QEPCTL; /*!< (@ 0x00000034) QEI Contorl Register */
+
+ struct {
+ __IOM uint32_t QPE : 1; /*!< [0..0] QEI使能（QEI Enable） */
+ __IOM uint32_t UTE : 1; /*!< [1..1] QEI Timer使能（QEI Timer Enable） */
+ uint32_t : 2;
+ __IOM uint32_t IEL : 2; /*!< [5..4] QEI位置计数器索引锁存选择（QEI Position Counter
+ Index Latch Selection） */
+ __IOM uint32_t IEI : 2; /*!< [7..6] QEI位置计数器索引初始选择（QEI Position Counter
+ Index Initial Selection） */
+ __IOM uint32_t SWI : 1; /*!< [8..8] QEI位置计数器初始化使能（QEI Position Counter
+ Software Initial Enable） */
+ uint32_t : 3;
+ __IOM uint32_t PCRM : 2; /*!< [13..12] QEI位置计数器复位选择（QEI Position Counter
+ Reset Selection） */
+ uint32_t : 18;
+ } QEPCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t POSCTL; /*!< (@ 0x00000038) QEI Position Contorl Register */
+
+ struct {
+ __IOM uint32_t CCE : 1; /*!< [0..0] QEI位置计数比较使能（QEI Position Counter Compare
+ Enable） */
+ __IOM uint32_t PSE : 1; /*!< [1..1] QEI位置计数比较影子寄存器使能（QEI Position
+ Counter Compare Shadow Enable） */
+ uint32_t : 30;
+ } POSCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPCTL; /*!< (@ 0x0000003C) QEI Capture Control Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] QEI捕获使能（QEI Capture Enable） */
+ __IOM uint32_t CMD : 1; /*!< [1..1] QEI捕获锁存模式（QEI Capture Latch Mode） */
+ uint32_t : 2;
+ __IOM uint32_t CCPS : 3; /*!< [6..4] QEI捕获定时器分频（QEI Capture Timer Clock Division） */
+ uint32_t : 1;
+ __IOM uint32_t UPPS : 4; /*!< [11..8] QEI捕获事件分频（QEI Capture Position Event Division） */
+ uint32_t : 20;
+ } CAPCTL_b;
+ } ;
+
+ union {
+ __IOM uint32_t QCTMR; /*!< (@ 0x00000040) QEI Capture Counter Register */
+
+ struct {
+ __IOM uint32_t CTMR : 32; /*!< [31..0] QEI捕获计数寄存器 (QEI Capture Counter Register） */
+ } QCTMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t QCPRD; /*!< (@ 0x00000044) QEI Capture Period Register */
+
+ struct {
+ __IM uint32_t CPRD : 32; /*!< [31..0] QEI捕获周期寄存器 (QEI Capture Period Register） */
+ } QCPRD_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTMRLAT; /*!< (@ 0x00000048) QEI Capture Counter Latch Register */
+
+ struct {
+ __IM uint32_t CTMRLAT : 32; /*!< [31..0] QEI捕获计数锁存寄存器 (QEI Compare Counter
+ Latch Register） */
+ } CTMRLAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPRDLAT; /*!< (@ 0x0000004C) QEI Capture Period Latch Register */
+
+ struct {
+ __IM uint32_t CPRDLAT : 32; /*!< [31..0] QEI捕获周期锁存寄存器 (QEI Capture Period Latch
+ Register） */
+ } CPRDLAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t IENR; /*!< (@ 0x00000050) QEI Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t PCE : 1; /*!< [0..0] QEI位置计数器错误中断使能（QEI Position Counter
+ Error Interrupt Enable） */
+ __IOM uint32_t QPE : 1; /*!< [1..1] QEI相位错误中断使能（QEI Phase Error Interrupt
+ Enable） */
+ __IOM uint32_t QDC : 1; /*!< [2..2] QEI正交方向变化中断使能（QEI Direction Change
+ Interrupt Enable） */
+ __IOM uint32_t PCU : 1; /*!< [3..3] QEI位置计数器下溢中断使能（QEI Position Counter
+ Underflow Interrupt Enable） */
+ __IOM uint32_t PCO : 1; /*!< [4..4] QEI位置计数器上溢中断使能（QEI Position Counter
+ Overflow Interrupt Enable） */
+ __IOM uint32_t PCM : 1; /*!< [5..5] QEI位置计数器比较中断使能（QEI Position Counter
+ Compare Interrupt Enable） */
+ __IOM uint32_t IEL : 1; /*!< [6..6] QEI位置计数器锁存中断使能（QEI Position Counter
+ Latch Interrupt Enable） */
+ __IOM uint32_t UTO : 1; /*!< [7..7] QEI定时器溢出中断使能（QEI Timer Overflow Interrupt
+ Enable） */
+ __IOM uint32_t PIE : 1; /*!< [8..8] QEI位置计数器初始化中断使能（QEI Position
+ Counter Initial Interrupt Enable） */
+ __IOM uint32_t PRE : 1; /*!< [9..9] QEI位置计数器复位中断使能（QEI Position Counter
+ Reset Interrupt Enable） */
+ __IOM uint32_t CDE : 1; /*!< [10..10] QEI Capture捕获成功中断使能（QEI Capture Done
+ Interrupt Enable） */
+ uint32_t : 21;
+ } IENR_b;
+ } ;
+
+ union {
+ __IOM uint32_t STSR; /*!< (@ 0x00000054) QEI Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t PCE : 1; /*!< [0..0] QEI位置计数器错误标志位（QEI Position Counter
+ Error Interrupt Status） */
+ __IOM uint32_t PHE : 1; /*!< [1..1] QEI相位错误标志位（QEI Phase Error Interrupt
+ Status） */
+ __IOM uint32_t QDC : 1; /*!< [2..2] QEI正交方向变化标志位（QEI Direction Change
+ Interrupt Status） */
+ __IOM uint32_t PCU : 1; /*!< [3..3] QEI位置计数器下溢标志位（QEI Position Counter
+ Underflow Interrupt Status） */
+ __IOM uint32_t PCO : 1; /*!< [4..4] QEI位置计数器上溢标志位（QEI Position Counter
+ Overflow Interrupt Status） */
+ __IOM uint32_t PCM : 1; /*!< [5..5] QEI位置计数器比较成功标志位（QEI Position
+ Counter Compare Interrupt Status） */
+ __IOM uint32_t IEL : 1; /*!< [6..6] QEI位置计数器锁存标志位（QEI Position Counter
+ Latch Interrupt Status） */
+ __IOM uint32_t UTO : 1; /*!< [7..7] QEI定时器溢出标志位（QEI Timer Overflow Interrupt
+ Status） */
+ __IOM uint32_t PIS : 1; /*!< [8..8] QEI位置计数器初始化标志位（QEI Position Counter
+ Initial Interrupt Status） */
+ __IOM uint32_t PRS : 1; /*!< [9..9] QEI位置计数器复位标志位（QEI Position Counter
+ Reset Interrupt Status） */
+ __IOM uint32_t CDS : 1; /*!< [10..10] QEI Capture捕获成功状态标志位（QEI Capture
+ Done Interrupt Status） */
+ __IM uint32_t FIS : 1; /*!< [11..11] QEI出现首次索引标志位（QEI The First Index
+ Status） */
+ __IOM uint32_t CDE : 1; /*!< [12..12] QEI捕获方向错误标志位（QEI Capture Direction
+ Error Status） */
+ __IOM uint32_t COE : 1; /*!< [13..13] QEI捕获上溢错误标志位（QEI Capture Overflow
+ Error Status） */
+ __IM uint32_t QDS : 1; /*!< [14..14] QEI实时电机转向标志位（QEI Direction Status） */
+ __IM uint32_t QDI : 1; /*!< [15..15] QEI每次电机转向标志位（QEI Direction Index
+ Latch Status） */
+ __IM uint32_t QDF : 1; /*!< [16..16] QEI首次电机转向标志位（QEI Direction First
+ Index Status） */
+ uint32_t : 15;
+ } STSR_b;
+ } ;
+} QEI2_Type; /*!< Size = 88 (0x58) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief PDM0 (PDM0)
+ */
+
+typedef struct { /*!< (@ 0x40017000) PDM0 Structure */
+
+ union {
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) PDM Enable Register */
+
+ struct {
+ __IOM uint32_t PDMEN : 1; /*!< [0..0] PDM使能位（PDM Enable） */
+ __IOM uint32_t INMOD : 1; /*!< [1..1] PDM 输入模式位（PDM Input Mode） */
+ uint32_t : 30;
+ } ENABLE_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) PDM Control Register */
+
+ struct {
+ __IOM uint32_t BAUD : 12; /*!< [11..0] 波特率配置（Baud Rate Configuration） */
+ uint32_t : 4;
+ __IOM uint32_t MSTEN : 1; /*!< [16..16] PDM主机使能位（PDM Master Enable） */
+ __IOM uint32_t SCPOL : 1; /*!< [17..17] 串行时钟极性（Serial Clock Polarity） */
+ __IOM uint32_t SAMPMODE : 1; /*!< [18..18] 从机时采样模式选择（Slave Sample Mode） */
+ __IOM uint32_t DMAEN : 1; /*!< [19..19] DMA使能位（DMA Enable） */
+ uint32_t : 8;
+ __IOM uint32_t RXDLY : 3; /*!< [30..28] SPI接收采样延迟（SPI RX Delay） */
+ uint32_t : 1;
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t DFCR; /*!< (@ 0x00000008) PDM Main Filter Control Register */
+
+ struct {
+ __IOM uint32_t DOSR : 8; /*!< [7..0] 主滤波器过采样值（Data filter Oversampling ratio） */
+ __IOM uint32_t DFEN : 1; /*!< [8..8] 主滤波器使能位（Data Filter Enable） */
+ __IOM uint32_t DFSST : 3; /*!< [11..9] 主滤波器类型（Data Filter Structure） */
+ __IOM uint32_t DFBYPASS : 1; /*!< [12..12] 主滤波器bypass使能（Data Filter Bypass Enable） */
+ __IOM uint32_t DFDR : 1; /*!< [13..13] 主滤波器输出数据位宽选择（Data Filter
+ Output Data Length） */
+ __IOM uint32_t SDSYNCEN : 1; /*!< [14..14] SDSYNC信号使能位（SDSYNC Enable） */
+ uint32_t : 1;
+ __IOM uint32_t SHIFT : 4; /*!< [19..16] 移位控制选择位（Shift Control Select） */
+ uint32_t : 12;
+ } DFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFCR; /*!< (@ 0x0000000C) PDM Compare Filter Control Register */
+
+ struct {
+ __IOM uint32_t COSR : 5; /*!< [4..0] 比较滤波器过采样值（Comparator filter Oversampling
+ ratio） */
+ __IOM uint32_t CFEN : 1; /*!< [5..5] 比较滤波器使能位（Comparator Filter Enable） */
+ __IOM uint32_t CFSST : 3; /*!< [8..6] 比较滤波器类型（Comparator Filter Structure） */
+ __IOM uint32_t CFBYPASS : 1; /*!< [9..9] 比较滤波器bypass使能位（Comparator Filter Bypass
+ Enable） */
+ __IOM uint32_t COMPSEL : 1; /*!< [10..10] 比较滤波器输出选择（Comparator Filter Output
+ Select） */
+ uint32_t : 21;
+ } CFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FCSR; /*!< (@ 0x00000010) PDM FIFO Control Register */
+
+ struct {
+ __IOM uint32_t PDMFIL : 3; /*!< [2..0] FIFO满中断阈值选择。 */
+ uint32_t : 5;
+ __IM uint32_t PDMFST : 4; /*!< [11..8] FIFO状态（FIFO Status） */
+ uint32_t : 4;
+ __IM uint32_t FIFOEMPTY : 1; /*!< [16..16] FIFO空标志（FIFO Empty Flag） */
+ __IM uint32_t FIFOFULL : 1; /*!< [17..17] FIFO满标志（FIFO Full Flag） */
+ __IOM uint32_t FIFORST : 1; /*!< [18..18] FIFO复位（FIFO Reset） */
+ uint32_t : 13;
+ } FCSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000014) PDM Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t HLIE : 1; /*!< [0..0] HLINTR中断使能（HLINTR Interrupt Enable） */
+ __IOM uint32_t LLIE : 1; /*!< [1..1] LLINTR中断使能（LLINTR Interrupt Enable） */
+ __IOM uint32_t DFIE : 1; /*!< [2..2] DFINTR中断使能（DFINTR Interrupt Enable） */
+ __IOM uint32_t DOFIE : 1; /*!< [3..3] DOINTR中断使能（DOINTR Interrupt Enable） */
+ __IOM uint32_t FIOIE : 1; /*!< [4..4] FIOINTR中断使能（FIOINTR Interrupt Enable） */
+ __IOM uint32_t FFIE : 1; /*!< [5..5] FIFINTR中断使能（FIFINTR Interrupt Enable） */
+ __IOM uint32_t CTIE : 1; /*!< [6..6] CTOINTR中断使能（CTOINTR Interrupt Enable） */
+ __IOM uint32_t FIUIE : 1; /*!< [7..7] FIUINTR中断使能（FIUINTR Interrupt Enable） */
+ uint32_t : 24;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) PDM Interrupt State Register */
+
+ struct {
+ __IOM uint32_t HLINTR : 1; /*!< [0..0] 高阈值中断（High Level Interrupt） */
+ __IOM uint32_t LLINTR : 1; /*!< [1..1] 低阈值中断（Low Level Interrupt） */
+ __IOM uint32_t DFINTR : 1; /*!< [2..2] 数据完成中断（Data Finish Interrupt） */
+ __IOM uint32_t DOINTR : 1; /*!< [3..3] 数据溢出中断（Data Overflow Interrupt） */
+ __IOM uint32_t FIOINTR : 1; /*!< [4..4] FIFO上溢中断（FIFO Overflow Interrupt） */
+ __IM uint32_t FIFINTR : 1; /*!< [5..5] FIFO满中断（FIFO Full Interrupt） */
+ __IOM uint32_t CTOINTR : 1; /*!< [6..6] 时钟超时中断（Clock Timeout Interrupt） */
+ __IOM uint32_t FIUINTR : 1; /*!< [7..7] FIFO下溢中断（FIFO Underflow Interrupt） */
+ uint32_t : 24;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DDAT; /*!< (@ 0x0000001C) PDM Main Filter Result Register */
+
+ struct {
+ __IM uint32_t DDAT : 24; /*!< [23..0] 主滤波器数据寄存器（Data Filter Data Register） */
+ uint32_t : 8;
+ } DDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDAT; /*!< (@ 0x00000020) PDM Compare Filter Result Register */
+
+ struct {
+ __IM uint32_t CDAT : 16; /*!< [15..0] 比较滤波器数据寄存器（Comparator Filter Data
+ Register） */
+ uint32_t : 16;
+ } CDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t FDAT; /*!< (@ 0x00000024) PDM FIFO Result Register */
+
+ struct {
+ __IM uint32_t FDAT : 24; /*!< [23..0] FIFO数据寄存器（FIFO Data Register） */
+ uint32_t : 8;
+ } FDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPH; /*!< (@ 0x00000028) PDM High-Level Compare Register */
+
+ struct {
+ __IOM uint32_t HLT : 16; /*!< [15..0] 比较滤波器的高阈值（Comparator High-Level
+ Data） */
+ uint32_t : 16;
+ } CMPH_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPL; /*!< (@ 0x0000002C) PDM Low-Level Compare Register */
+
+ struct {
+ __IOM uint32_t LLT : 16; /*!< [15..0] 比较滤波器的低阈值（Comparator Low-Level Data） */
+ uint32_t : 16;
+ } CMPL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLKTO; /*!< (@ 0x00000030) PDM Clock Timeout Register */
+
+ struct {
+ __IOM uint32_t CLKTOT : 18; /*!< [17..0] PDM时钟超时寄存器（Clock Timeout Register） */
+ uint32_t : 14;
+ } CLKTO_b;
+ } ;
+
+ union {
+ __IOM uint32_t SDSYNC; /*!< (@ 0x00000034) PDM Synchronization Control Register */
+
+ struct {
+ __IOM uint32_t SYNCSEL : 6; /*!< [5..0] SDSYNC选择（SDSYNC Select） */
+ __IOM uint32_t WTSYNCEN : 1; /*!< [6..6] FIFO在WTSYNFLG标志下的表现（The performance of
+ FIFO under the WTSYNFLG） */
+ __IM uint32_t WTSYNFLG : 1; /*!< [7..7] 收到SDSYNC标志（Receive SDSYNC Flag） */
+ __IOM uint32_t WTSYNCLR : 1; /*!< [8..8] WTSYNFLG清除位（WTSYNFLG Clear Enable） */
+ __IOM uint32_t FFSYNCCLREN : 1; /*!< [9..9] SDSYNC信号复位FIFO使能位（FIFO Reset By SDSYNC） */
+ __IOM uint32_t WTSCLREN : 1; /*!< [10..10] WTSYNFLG清除使能位（WTSYNFLG Clear Enable） */
+ uint32_t : 21;
+ } SDSYNC_b;
+ } ;
+
+ union {
+ __IOM uint32_t IDAT; /*!< (@ 0x00000038) PDM Input Data Register */
+
+ struct {
+ __IOM uint32_t IDAT : 16; /*!< [15..0] 输入数据寄存器（Input Data Register） */
+ uint32_t : 16;
+ } IDAT_b;
+ } ;
+} PDM0_Type; /*!< Size = 60 (0x3c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief PDM1 (PDM1)
+ */
+
+typedef struct { /*!< (@ 0x40017100) PDM1 Structure */
+
+ union {
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) PDM Enable Register */
+
+ struct {
+ __IOM uint32_t PDMEN : 1; /*!< [0..0] PDM使能位（PDM Enable） */
+ __IOM uint32_t INMOD : 1; /*!< [1..1] PDM 输入模式位（PDM Input Mode） */
+ uint32_t : 30;
+ } ENABLE_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) PDM Control Register */
+
+ struct {
+ __IOM uint32_t BAUD : 12; /*!< [11..0] 波特率配置（Baud Rate Configuration） */
+ uint32_t : 4;
+ __IOM uint32_t MSTEN : 1; /*!< [16..16] PDM主机使能位（PDM Master Enable） */
+ __IOM uint32_t SCPOL : 1; /*!< [17..17] 串行时钟极性（Serial Clock Polarity） */
+ __IOM uint32_t SAMPMODE : 1; /*!< [18..18] 从机时采样模式选择（Slave Sample Mode） */
+ __IOM uint32_t DMAEN : 1; /*!< [19..19] DMA使能位（DMA Enable） */
+ uint32_t : 8;
+ __IOM uint32_t RXDLY : 3; /*!< [30..28] SPI接收采样延迟（SPI RX Delay） */
+ uint32_t : 1;
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t DFCR; /*!< (@ 0x00000008) PDM Main Filter Control Register */
+
+ struct {
+ __IOM uint32_t DOSR : 8; /*!< [7..0] 主滤波器过采样值（Data filter Oversampling ratio） */
+ __IOM uint32_t DFEN : 1; /*!< [8..8] 主滤波器使能位（Data Filter Enable） */
+ __IOM uint32_t DFSST : 3; /*!< [11..9] 主滤波器类型（Data Filter Structure） */
+ __IOM uint32_t DFBYPASS : 1; /*!< [12..12] 主滤波器bypass使能（Data Filter Bypass Enable） */
+ __IOM uint32_t DFDR : 1; /*!< [13..13] 主滤波器输出数据位宽选择（Data Filter
+ Output Data Length） */
+ __IOM uint32_t SDSYNCEN : 1; /*!< [14..14] SDSYNC信号使能位（SDSYNC Enable） */
+ uint32_t : 1;
+ __IOM uint32_t SHIFT : 4; /*!< [19..16] 移位控制选择位（Shift Control Select） */
+ uint32_t : 12;
+ } DFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFCR; /*!< (@ 0x0000000C) PDM Compare Filter Control Register */
+
+ struct {
+ __IOM uint32_t COSR : 5; /*!< [4..0] 比较滤波器过采样值（Comparator filter Oversampling
+ ratio） */
+ __IOM uint32_t CFEN : 1; /*!< [5..5] 比较滤波器使能位（Comparator Filter Enable） */
+ __IOM uint32_t CFSST : 3; /*!< [8..6] 比较滤波器类型（Comparator Filter Structure） */
+ __IOM uint32_t CFBYPASS : 1; /*!< [9..9] 比较滤波器bypass使能位（Comparator Filter Bypass
+ Enable） */
+ __IOM uint32_t COMPSEL : 1; /*!< [10..10] 比较滤波器输出选择（Comparator Filter Output
+ Select） */
+ uint32_t : 21;
+ } CFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FCSR; /*!< (@ 0x00000010) PDM FIFO Control Register */
+
+ struct {
+ __IOM uint32_t PDMFIL : 3; /*!< [2..0] FIFO满中断阈值选择。 */
+ uint32_t : 5;
+ __IM uint32_t PDMFST : 4; /*!< [11..8] FIFO状态（FIFO Status） */
+ uint32_t : 4;
+ __IM uint32_t FIFOEMPTY : 1; /*!< [16..16] FIFO空标志（FIFO Empty Flag） */
+ __IM uint32_t FIFOFULL : 1; /*!< [17..17] FIFO满标志（FIFO Full Flag） */
+ __IOM uint32_t FIFORST : 1; /*!< [18..18] FIFO复位（FIFO Reset） */
+ uint32_t : 13;
+ } FCSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000014) PDM Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t HLIE : 1; /*!< [0..0] HLINTR中断使能（HLINTR Interrupt Enable） */
+ __IOM uint32_t LLIE : 1; /*!< [1..1] LLINTR中断使能（LLINTR Interrupt Enable） */
+ __IOM uint32_t DFIE : 1; /*!< [2..2] DFINTR中断使能（DFINTR Interrupt Enable） */
+ __IOM uint32_t DOFIE : 1; /*!< [3..3] DOINTR中断使能（DOINTR Interrupt Enable） */
+ __IOM uint32_t FIOIE : 1; /*!< [4..4] FIOINTR中断使能（FIOINTR Interrupt Enable） */
+ __IOM uint32_t FFIE : 1; /*!< [5..5] FIFINTR中断使能（FIFINTR Interrupt Enable） */
+ __IOM uint32_t CTIE : 1; /*!< [6..6] CTOINTR中断使能（CTOINTR Interrupt Enable） */
+ __IOM uint32_t FIUIE : 1; /*!< [7..7] FIUINTR中断使能（FIUINTR Interrupt Enable） */
+ uint32_t : 24;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) PDM Interrupt State Register */
+
+ struct {
+ __IOM uint32_t HLINTR : 1; /*!< [0..0] 高阈值中断（High Level Interrupt） */
+ __IOM uint32_t LLINTR : 1; /*!< [1..1] 低阈值中断（Low Level Interrupt） */
+ __IOM uint32_t DFINTR : 1; /*!< [2..2] 数据完成中断（Data Finish Interrupt） */
+ __IOM uint32_t DOINTR : 1; /*!< [3..3] 数据溢出中断（Data Overflow Interrupt） */
+ __IOM uint32_t FIOINTR : 1; /*!< [4..4] FIFO上溢中断（FIFO Overflow Interrupt） */
+ __IM uint32_t FIFINTR : 1; /*!< [5..5] FIFO满中断（FIFO Full Interrupt） */
+ __IOM uint32_t CTOINTR : 1; /*!< [6..6] 时钟超时中断（Clock Timeout Interrupt） */
+ __IOM uint32_t FIUINTR : 1; /*!< [7..7] FIFO下溢中断（FIFO Underflow Interrupt） */
+ uint32_t : 24;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DDAT; /*!< (@ 0x0000001C) PDM Main Filter Result Register */
+
+ struct {
+ __IM uint32_t DDAT : 24; /*!< [23..0] 主滤波器数据寄存器（Data Filter Data Register） */
+ uint32_t : 8;
+ } DDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDAT; /*!< (@ 0x00000020) PDM Compare Filter Result Register */
+
+ struct {
+ __IM uint32_t CDAT : 16; /*!< [15..0] 比较滤波器数据寄存器（Comparator Filter Data
+ Register） */
+ uint32_t : 16;
+ } CDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t FDAT; /*!< (@ 0x00000024) PDM FIFO Result Register */
+
+ struct {
+ __IM uint32_t FDAT : 24; /*!< [23..0] FIFO数据寄存器（FIFO Data Register） */
+ uint32_t : 8;
+ } FDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPH; /*!< (@ 0x00000028) PDM High-Level Compare Register */
+
+ struct {
+ __IOM uint32_t HLT : 16; /*!< [15..0] 比较滤波器的高阈值（Comparator High-Level
+ Data） */
+ uint32_t : 16;
+ } CMPH_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPL; /*!< (@ 0x0000002C) PDM Low-Level Compare Register */
+
+ struct {
+ __IOM uint32_t LLT : 16; /*!< [15..0] 比较滤波器的低阈值（Comparator Low-Level Data） */
+ uint32_t : 16;
+ } CMPL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLKTO; /*!< (@ 0x00000030) PDM Clock Timeout Register */
+
+ struct {
+ __IOM uint32_t CLKTOT : 18; /*!< [17..0] PDM时钟超时寄存器（Clock Timeout Register） */
+ uint32_t : 14;
+ } CLKTO_b;
+ } ;
+
+ union {
+ __IOM uint32_t SDSYNC; /*!< (@ 0x00000034) PDM Synchronization Control Register */
+
+ struct {
+ __IOM uint32_t SYNCSEL : 6; /*!< [5..0] SDSYNC选择（SDSYNC Select） */
+ __IOM uint32_t WTSYNCEN : 1; /*!< [6..6] FIFO在WTSYNFLG标志下的表现（The performance of
+ FIFO under the WTSYNFLG） */
+ __IM uint32_t WTSYNFLG : 1; /*!< [7..7] 收到SDSYNC标志（Receive SDSYNC Flag） */
+ __IOM uint32_t WTSYNCLR : 1; /*!< [8..8] WTSYNFLG清除位（WTSYNFLG Clear Enable） */
+ __IOM uint32_t FFSYNCCLREN : 1; /*!< [9..9] SDSYNC信号复位FIFO使能位（FIFO Reset By SDSYNC） */
+ __IOM uint32_t WTSCLREN : 1; /*!< [10..10] WTSYNFLG清除使能位（WTSYNFLG Clear Enable） */
+ uint32_t : 21;
+ } SDSYNC_b;
+ } ;
+
+ union {
+ __IOM uint32_t IDAT; /*!< (@ 0x00000038) PDM Input Data Register */
+
+ struct {
+ __IOM uint32_t IDAT : 16; /*!< [15..0] 输入数据寄存器（Input Data Register） */
+ uint32_t : 16;
+ } IDAT_b;
+ } ;
+} PDM1_Type; /*!< Size = 60 (0x3c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief PDM2 (PDM2)
+ */
+
+typedef struct { /*!< (@ 0x40017200) PDM2 Structure */
+
+ union {
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) PDM Enable Register */
+
+ struct {
+ __IOM uint32_t PDMEN : 1; /*!< [0..0] PDM使能位（PDM Enable） */
+ __IOM uint32_t INMOD : 1; /*!< [1..1] PDM 输入模式位（PDM Input Mode） */
+ uint32_t : 30;
+ } ENABLE_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) PDM Control Register */
+
+ struct {
+ __IOM uint32_t BAUD : 12; /*!< [11..0] 波特率配置（Baud Rate Configuration） */
+ uint32_t : 4;
+ __IOM uint32_t MSTEN : 1; /*!< [16..16] PDM主机使能位（PDM Master Enable） */
+ __IOM uint32_t SCPOL : 1; /*!< [17..17] 串行时钟极性（Serial Clock Polarity） */
+ __IOM uint32_t SAMPMODE : 1; /*!< [18..18] 从机时采样模式选择（Slave Sample Mode） */
+ __IOM uint32_t DMAEN : 1; /*!< [19..19] DMA使能位（DMA Enable） */
+ uint32_t : 8;
+ __IOM uint32_t RXDLY : 3; /*!< [30..28] SPI接收采样延迟（SPI RX Delay） */
+ uint32_t : 1;
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t DFCR; /*!< (@ 0x00000008) PDM Main Filter Control Register */
+
+ struct {
+ __IOM uint32_t DOSR : 8; /*!< [7..0] 主滤波器过采样值（Data filter Oversampling ratio） */
+ __IOM uint32_t DFEN : 1; /*!< [8..8] 主滤波器使能位（Data Filter Enable） */
+ __IOM uint32_t DFSST : 3; /*!< [11..9] 主滤波器类型（Data Filter Structure） */
+ __IOM uint32_t DFBYPASS : 1; /*!< [12..12] 主滤波器bypass使能（Data Filter Bypass Enable） */
+ __IOM uint32_t DFDR : 1; /*!< [13..13] 主滤波器输出数据位宽选择（Data Filter
+ Output Data Length） */
+ __IOM uint32_t SDSYNCEN : 1; /*!< [14..14] SDSYNC信号使能位（SDSYNC Enable） */
+ uint32_t : 1;
+ __IOM uint32_t SHIFT : 4; /*!< [19..16] 移位控制选择位（Shift Control Select） */
+ uint32_t : 12;
+ } DFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFCR; /*!< (@ 0x0000000C) PDM Compare Filter Control Register */
+
+ struct {
+ __IOM uint32_t COSR : 5; /*!< [4..0] 比较滤波器过采样值（Comparator filter Oversampling
+ ratio） */
+ __IOM uint32_t CFEN : 1; /*!< [5..5] 比较滤波器使能位（Comparator Filter Enable） */
+ __IOM uint32_t CFSST : 3; /*!< [8..6] 比较滤波器类型（Comparator Filter Structure） */
+ __IOM uint32_t CFBYPASS : 1; /*!< [9..9] 比较滤波器bypass使能位（Comparator Filter Bypass
+ Enable） */
+ __IOM uint32_t COMPSEL : 1; /*!< [10..10] 比较滤波器输出选择（Comparator Filter Output
+ Select） */
+ uint32_t : 21;
+ } CFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FCSR; /*!< (@ 0x00000010) PDM FIFO Control Register */
+
+ struct {
+ __IOM uint32_t PDMFIL : 3; /*!< [2..0] FIFO满中断阈值选择。 */
+ uint32_t : 5;
+ __IM uint32_t PDMFST : 4; /*!< [11..8] FIFO状态（FIFO Status） */
+ uint32_t : 4;
+ __IM uint32_t FIFOEMPTY : 1; /*!< [16..16] FIFO空标志（FIFO Empty Flag） */
+ __IM uint32_t FIFOFULL : 1; /*!< [17..17] FIFO满标志（FIFO Full Flag） */
+ __IOM uint32_t FIFORST : 1; /*!< [18..18] FIFO复位（FIFO Reset） */
+ uint32_t : 13;
+ } FCSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000014) PDM Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t HLIE : 1; /*!< [0..0] HLINTR中断使能（HLINTR Interrupt Enable） */
+ __IOM uint32_t LLIE : 1; /*!< [1..1] LLINTR中断使能（LLINTR Interrupt Enable） */
+ __IOM uint32_t DFIE : 1; /*!< [2..2] DFINTR中断使能（DFINTR Interrupt Enable） */
+ __IOM uint32_t DOFIE : 1; /*!< [3..3] DOINTR中断使能（DOINTR Interrupt Enable） */
+ __IOM uint32_t FIOIE : 1; /*!< [4..4] FIOINTR中断使能（FIOINTR Interrupt Enable） */
+ __IOM uint32_t FFIE : 1; /*!< [5..5] FIFINTR中断使能（FIFINTR Interrupt Enable） */
+ __IOM uint32_t CTIE : 1; /*!< [6..6] CTOINTR中断使能（CTOINTR Interrupt Enable） */
+ __IOM uint32_t FIUIE : 1; /*!< [7..7] FIUINTR中断使能（FIUINTR Interrupt Enable） */
+ uint32_t : 24;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) PDM Interrupt State Register */
+
+ struct {
+ __IOM uint32_t HLINTR : 1; /*!< [0..0] 高阈值中断（High Level Interrupt） */
+ __IOM uint32_t LLINTR : 1; /*!< [1..1] 低阈值中断（Low Level Interrupt） */
+ __IOM uint32_t DFINTR : 1; /*!< [2..2] 数据完成中断（Data Finish Interrupt） */
+ __IOM uint32_t DOINTR : 1; /*!< [3..3] 数据溢出中断（Data Overflow Interrupt） */
+ __IOM uint32_t FIOINTR : 1; /*!< [4..4] FIFO上溢中断（FIFO Overflow Interrupt） */
+ __IM uint32_t FIFINTR : 1; /*!< [5..5] FIFO满中断（FIFO Full Interrupt） */
+ __IOM uint32_t CTOINTR : 1; /*!< [6..6] 时钟超时中断（Clock Timeout Interrupt） */
+ __IOM uint32_t FIUINTR : 1; /*!< [7..7] FIFO下溢中断（FIFO Underflow Interrupt） */
+ uint32_t : 24;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DDAT; /*!< (@ 0x0000001C) PDM Main Filter Result Register */
+
+ struct {
+ __IM uint32_t DDAT : 24; /*!< [23..0] 主滤波器数据寄存器（Data Filter Data Register） */
+ uint32_t : 8;
+ } DDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDAT; /*!< (@ 0x00000020) PDM Compare Filter Result Register */
+
+ struct {
+ __IM uint32_t CDAT : 16; /*!< [15..0] 比较滤波器数据寄存器（Comparator Filter Data
+ Register） */
+ uint32_t : 16;
+ } CDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t FDAT; /*!< (@ 0x00000024) PDM FIFO Result Register */
+
+ struct {
+ __IM uint32_t FDAT : 24; /*!< [23..0] FIFO数据寄存器（FIFO Data Register） */
+ uint32_t : 8;
+ } FDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPH; /*!< (@ 0x00000028) PDM High-Level Compare Register */
+
+ struct {
+ __IOM uint32_t HLT : 16; /*!< [15..0] 比较滤波器的高阈值（Comparator High-Level
+ Data） */
+ uint32_t : 16;
+ } CMPH_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPL; /*!< (@ 0x0000002C) PDM Low-Level Compare Register */
+
+ struct {
+ __IOM uint32_t LLT : 16; /*!< [15..0] 比较滤波器的低阈值（Comparator Low-Level Data） */
+ uint32_t : 16;
+ } CMPL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLKTO; /*!< (@ 0x00000030) PDM Clock Timeout Register */
+
+ struct {
+ __IOM uint32_t CLKTOT : 18; /*!< [17..0] PDM时钟超时寄存器（Clock Timeout Register） */
+ uint32_t : 14;
+ } CLKTO_b;
+ } ;
+
+ union {
+ __IOM uint32_t SDSYNC; /*!< (@ 0x00000034) PDM Synchronization Control Register */
+
+ struct {
+ __IOM uint32_t SYNCSEL : 6; /*!< [5..0] SDSYNC选择（SDSYNC Select） */
+ __IOM uint32_t WTSYNCEN : 1; /*!< [6..6] FIFO在WTSYNFLG标志下的表现（The performance of
+ FIFO under the WTSYNFLG） */
+ __IM uint32_t WTSYNFLG : 1; /*!< [7..7] 收到SDSYNC标志（Receive SDSYNC Flag） */
+ __IOM uint32_t WTSYNCLR : 1; /*!< [8..8] WTSYNFLG清除位（WTSYNFLG Clear Enable） */
+ __IOM uint32_t FFSYNCCLREN : 1; /*!< [9..9] SDSYNC信号复位FIFO使能位（FIFO Reset By SDSYNC） */
+ __IOM uint32_t WTSCLREN : 1; /*!< [10..10] WTSYNFLG清除使能位（WTSYNFLG Clear Enable） */
+ uint32_t : 21;
+ } SDSYNC_b;
+ } ;
+
+ union {
+ __IOM uint32_t IDAT; /*!< (@ 0x00000038) PDM Input Data Register */
+
+ struct {
+ __IOM uint32_t IDAT : 16; /*!< [15..0] 输入数据寄存器（Input Data Register） */
+ uint32_t : 16;
+ } IDAT_b;
+ } ;
+} PDM2_Type; /*!< Size = 60 (0x3c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief PDM3 (PDM3)
+ */
+
+typedef struct { /*!< (@ 0x40017300) PDM3 Structure */
+
+ union {
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) PDM Enable Register */
+
+ struct {
+ __IOM uint32_t PDMEN : 1; /*!< [0..0] PDM使能位（PDM Enable） */
+ __IOM uint32_t INMOD : 1; /*!< [1..1] PDM 输入模式位（PDM Input Mode） */
+ uint32_t : 30;
+ } ENABLE_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) PDM Control Register */
+
+ struct {
+ __IOM uint32_t BAUD : 12; /*!< [11..0] 波特率配置（Baud Rate Configuration） */
+ uint32_t : 4;
+ __IOM uint32_t MSTEN : 1; /*!< [16..16] PDM主机使能位（PDM Master Enable） */
+ __IOM uint32_t SCPOL : 1; /*!< [17..17] 串行时钟极性（Serial Clock Polarity） */
+ __IOM uint32_t SAMPMODE : 1; /*!< [18..18] 从机时采样模式选择（Slave Sample Mode） */
+ __IOM uint32_t DMAEN : 1; /*!< [19..19] DMA使能位（DMA Enable） */
+ uint32_t : 8;
+ __IOM uint32_t RXDLY : 3; /*!< [30..28] SPI接收采样延迟（SPI RX Delay） */
+ uint32_t : 1;
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t DFCR; /*!< (@ 0x00000008) PDM Main Filter Control Register */
+
+ struct {
+ __IOM uint32_t DOSR : 8; /*!< [7..0] 主滤波器过采样值（Data filter Oversampling ratio） */
+ __IOM uint32_t DFEN : 1; /*!< [8..8] 主滤波器使能位（Data Filter Enable） */
+ __IOM uint32_t DFSST : 3; /*!< [11..9] 主滤波器类型（Data Filter Structure） */
+ __IOM uint32_t DFBYPASS : 1; /*!< [12..12] 主滤波器bypass使能（Data Filter Bypass Enable） */
+ __IOM uint32_t DFDR : 1; /*!< [13..13] 主滤波器输出数据位宽选择（Data Filter
+ Output Data Length） */
+ __IOM uint32_t SDSYNCEN : 1; /*!< [14..14] SDSYNC信号使能位（SDSYNC Enable） */
+ uint32_t : 1;
+ __IOM uint32_t SHIFT : 4; /*!< [19..16] 移位控制选择位（Shift Control Select） */
+ uint32_t : 12;
+ } DFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFCR; /*!< (@ 0x0000000C) PDM Compare Filter Control Register */
+
+ struct {
+ __IOM uint32_t COSR : 5; /*!< [4..0] 比较滤波器过采样值（Comparator filter Oversampling
+ ratio） */
+ __IOM uint32_t CFEN : 1; /*!< [5..5] 比较滤波器使能位（Comparator Filter Enable） */
+ __IOM uint32_t CFSST : 3; /*!< [8..6] 比较滤波器类型（Comparator Filter Structure） */
+ __IOM uint32_t CFBYPASS : 1; /*!< [9..9] 比较滤波器bypass使能位（Comparator Filter Bypass
+ Enable） */
+ __IOM uint32_t COMPSEL : 1; /*!< [10..10] 比较滤波器输出选择（Comparator Filter Output
+ Select） */
+ uint32_t : 21;
+ } CFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FCSR; /*!< (@ 0x00000010) PDM FIFO Control Register */
+
+ struct {
+ __IOM uint32_t PDMFIL : 3; /*!< [2..0] FIFO满中断阈值选择。 */
+ uint32_t : 5;
+ __IM uint32_t PDMFST : 4; /*!< [11..8] FIFO状态（FIFO Status） */
+ uint32_t : 4;
+ __IM uint32_t FIFOEMPTY : 1; /*!< [16..16] FIFO空标志（FIFO Empty Flag） */
+ __IM uint32_t FIFOFULL : 1; /*!< [17..17] FIFO满标志（FIFO Full Flag） */
+ __IOM uint32_t FIFORST : 1; /*!< [18..18] FIFO复位（FIFO Reset） */
+ uint32_t : 13;
+ } FCSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000014) PDM Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t HLIE : 1; /*!< [0..0] HLINTR中断使能（HLINTR Interrupt Enable） */
+ __IOM uint32_t LLIE : 1; /*!< [1..1] LLINTR中断使能（LLINTR Interrupt Enable） */
+ __IOM uint32_t DFIE : 1; /*!< [2..2] DFINTR中断使能（DFINTR Interrupt Enable） */
+ __IOM uint32_t DOFIE : 1; /*!< [3..3] DOINTR中断使能（DOINTR Interrupt Enable） */
+ __IOM uint32_t FIOIE : 1; /*!< [4..4] FIOINTR中断使能（FIOINTR Interrupt Enable） */
+ __IOM uint32_t FFIE : 1; /*!< [5..5] FIFINTR中断使能（FIFINTR Interrupt Enable） */
+ __IOM uint32_t CTIE : 1; /*!< [6..6] CTOINTR中断使能（CTOINTR Interrupt Enable） */
+ __IOM uint32_t FIUIE : 1; /*!< [7..7] FIUINTR中断使能（FIUINTR Interrupt Enable） */
+ uint32_t : 24;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) PDM Interrupt State Register */
+
+ struct {
+ __IOM uint32_t HLINTR : 1; /*!< [0..0] 高阈值中断（High Level Interrupt） */
+ __IOM uint32_t LLINTR : 1; /*!< [1..1] 低阈值中断（Low Level Interrupt） */
+ __IOM uint32_t DFINTR : 1; /*!< [2..2] 数据完成中断（Data Finish Interrupt） */
+ __IOM uint32_t DOINTR : 1; /*!< [3..3] 数据溢出中断（Data Overflow Interrupt） */
+ __IOM uint32_t FIOINTR : 1; /*!< [4..4] FIFO上溢中断（FIFO Overflow Interrupt） */
+ __IM uint32_t FIFINTR : 1; /*!< [5..5] FIFO满中断（FIFO Full Interrupt） */
+ __IOM uint32_t CTOINTR : 1; /*!< [6..6] 时钟超时中断（Clock Timeout Interrupt） */
+ __IOM uint32_t FIUINTR : 1; /*!< [7..7] FIFO下溢中断（FIFO Underflow Interrupt） */
+ uint32_t : 24;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DDAT; /*!< (@ 0x0000001C) PDM Main Filter Result Register */
+
+ struct {
+ __IM uint32_t DDAT : 24; /*!< [23..0] 主滤波器数据寄存器（Data Filter Data Register） */
+ uint32_t : 8;
+ } DDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDAT; /*!< (@ 0x00000020) PDM Compare Filter Result Register */
+
+ struct {
+ __IM uint32_t CDAT : 16; /*!< [15..0] 比较滤波器数据寄存器（Comparator Filter Data
+ Register） */
+ uint32_t : 16;
+ } CDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t FDAT; /*!< (@ 0x00000024) PDM FIFO Result Register */
+
+ struct {
+ __IM uint32_t FDAT : 24; /*!< [23..0] FIFO数据寄存器（FIFO Data Register） */
+ uint32_t : 8;
+ } FDAT_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPH; /*!< (@ 0x00000028) PDM High-Level Compare Register */
+
+ struct {
+ __IOM uint32_t HLT : 16; /*!< [15..0] 比较滤波器的高阈值（Comparator High-Level
+ Data） */
+ uint32_t : 16;
+ } CMPH_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPL; /*!< (@ 0x0000002C) PDM Low-Level Compare Register */
+
+ struct {
+ __IOM uint32_t LLT : 16; /*!< [15..0] 比较滤波器的低阈值（Comparator Low-Level Data） */
+ uint32_t : 16;
+ } CMPL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLKTO; /*!< (@ 0x00000030) PDM Clock Timeout Register */
+
+ struct {
+ __IOM uint32_t CLKTOT : 18; /*!< [17..0] PDM时钟超时寄存器（Clock Timeout Register） */
+ uint32_t : 14;
+ } CLKTO_b;
+ } ;
+
+ union {
+ __IOM uint32_t SDSYNC; /*!< (@ 0x00000034) PDM Synchronization Control Register */
+
+ struct {
+ __IOM uint32_t SYNCSEL : 6; /*!< [5..0] SDSYNC选择（SDSYNC Select） */
+ __IOM uint32_t WTSYNCEN : 1; /*!< [6..6] FIFO在WTSYNFLG标志下的表现（The performance of
+ FIFO under the WTSYNFLG） */
+ __IM uint32_t WTSYNFLG : 1; /*!< [7..7] 收到SDSYNC标志（Receive SDSYNC Flag） */
+ __IOM uint32_t WTSYNCLR : 1; /*!< [8..8] WTSYNFLG清除位（WTSYNFLG Clear Enable） */
+ __IOM uint32_t FFSYNCCLREN : 1; /*!< [9..9] SDSYNC信号复位FIFO使能位（FIFO Reset By SDSYNC） */
+ __IOM uint32_t WTSCLREN : 1; /*!< [10..10] WTSYNFLG清除使能位（WTSYNFLG Clear Enable） */
+ uint32_t : 21;
+ } SDSYNC_b;
+ } ;
+
+ union {
+ __IOM uint32_t IDAT; /*!< (@ 0x00000038) PDM Input Data Register */
+
+ struct {
+ __IOM uint32_t IDAT : 16; /*!< [15..0] 输入数据寄存器（Input Data Register） */
+ uint32_t : 16;
+ } IDAT_b;
+ } ;
+} PDM3_Type; /*!< Size = 60 (0x3c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IWDG ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IWDG (IWDG)
+ */
+
+typedef struct { /*!< (@ 0x4000C000) IWDG Structure */
+
+ union {
+ __IOM uint32_t KEYR; /*!< (@ 0x00000000) IWDG Key Register */
+
+ struct {
+ __IOM uint32_t KEY : 16; /*!< [15..0] IWDG键值（IWDG Key Value） */
+ uint32_t : 16;
+ } KEYR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000004) IWDG Control Register */
+
+ struct {
+ __IOM uint32_t MODE : 1; /*!< [0..0] IWDG模式配置位（IWDG Mode Config） */
+ __IOM uint32_t TOIE : 1; /*!< [1..1] IWDG超时中断使能位（IWDG Timeout Interrupt Enable） */
+ uint32_t : 30;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RLR; /*!< (@ 0x00000008) IWDG Reload Register */
+
+ struct {
+ __IOM uint32_t RLV : 16; /*!< [15..0] IWDG重载值（IWDG Reload Value） */
+ uint32_t : 16;
+ } RLR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x0000000C) IWDG Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 3; /*!< [2..0] IWDG预分频器（IWDG Prescaler Divider） */
+ uint32_t : 29;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) IWDG Status Register */
+
+ struct {
+ __IM uint32_t PSCUPD : 1; /*!< [0..0] IWDG预分频器值更新（IWDG Prescaler Update） */
+ __IM uint32_t RLVUPD : 1; /*!< [1..1] IWDG计数器重载值更新（IWDG Reload Value Update） */
+ __IOM uint32_t TOIF : 1; /*!< [2..2] IWDG超时中断标志位（IWDG Timeout Interrupt Flag） */
+ uint32_t : 29;
+ } SR_b;
+ } ;
+} IWDG_Type; /*!< Size = 20 (0x14) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR0 (IIR0)
+ */
+
+typedef struct { /*!< (@ 0x4003E000) IIR0 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+
+ struct {
+ __IOM uint32_t IEN : 1; /*!< [0..0] IIR使能(IIR Enable) */
+ uint32_t : 1;
+ __IOM uint32_t ORD : 2; /*!< [3..2] IIR阶数选择(IIR Order Selection) */
+ uint32_t : 3;
+ __IOM uint32_t IEE : 1; /*!< [7..7] IIR错误中断使能位(IIR Error Interrupt Enable) */
+ __IOM uint32_t RST : 1; /*!< [8..8] IIR软复位(IIR Soft Reset) */
+ uint32_t : 23;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+
+ struct {
+ __IOM uint32_t ERR : 1; /*!< [0..0] IIR错误中断标志(IIR Error Pending) */
+ __IM uint32_t BSY : 1; /*!< [1..1] IIR忙标志位(IIR Busy Status) */
+ uint32_t : 30;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+
+ struct {
+ __IOM uint32_t ID : 16; /*!< [15..0] IIR数据输入寄存器(IIR Data-In Register) */
+ uint32_t : 16;
+ } IDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+
+ struct {
+ __IM uint32_t OD : 16; /*!< [15..0] IIR数据输出寄存器(IIR Data-Out Register) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED[4];
+
+ union {
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+
+ struct {
+ __IOM uint32_t FSCL0 : 5; /*!< [4..0] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL0 : 5; /*!< [12..8] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ __IOM uint32_t FSCL1 : 5; /*!< [20..16] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL1 : 5; /*!< [28..24] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ } SCL_b;
+ } ;
+ __IM uint32_t RESERVED1[3];
+
+ union {
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B0COEF : 27; /*!< [26..0] IIR第0组B0系数设置(IIR Group 0 B0COEF RegNster) */
+ uint32_t : 5;
+ } G0B0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B1COEF : 27; /*!< [26..0] IIR第0组B1系数设置(IIR Group 0 B1COEF RegNster) */
+ uint32_t : 5;
+ } G0B1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B2COEF : 27; /*!< [26..0] IIR第0组B2系数设置(IIR Group 0 B2COEF RegNster) */
+ uint32_t : 5;
+ } G0B2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B3COEF : 27; /*!< [26..0] IIR第0组B3系数设置(IIR Group 0 B3COEF RegNster) */
+ uint32_t : 5;
+ } G0B3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B4COEF : 27; /*!< [26..0] IIR第0组B4系数设置(IIR Group 0 B4COEF RegNster) */
+ uint32_t : 5;
+ } G0B4R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B5COEF : 27; /*!< [26..0] IIR第0组B5系数设置(IIR Group 0 B5COEF RegNster) */
+ uint32_t : 5;
+ } G0B5R_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A1COEF : 27; /*!< [26..0] IIR第0组A1系数设置(IIR Group 0 A1COEF RegNster) */
+ uint32_t : 5;
+ } G0A1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A2COEF : 27; /*!< [26..0] IIR第0组A2系数设置(IIR Group 0 A2COEF RegNster) */
+ uint32_t : 5;
+ } G0A2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A3COEF : 27; /*!< [26..0] IIR第0组A3系数设置(IIR Group 0 A3COEF RegNster) */
+ uint32_t : 5;
+ } G0A3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A4COEF : 27; /*!< [26..0] IIR第0组A4系数设置(IIR Group 0 A4COEF RegNster) */
+ uint32_t : 5;
+ } G0A4R_b;
+ } ;
+} IIR0_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR1 (IIR1)
+ */
+
+typedef struct { /*!< (@ 0x4003E100) IIR1 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+
+ struct {
+ __IOM uint32_t IEN : 1; /*!< [0..0] IIR使能(IIR Enable) */
+ uint32_t : 1;
+ __IOM uint32_t ORD : 2; /*!< [3..2] IIR阶数选择(IIR Order Selection) */
+ uint32_t : 3;
+ __IOM uint32_t IEE : 1; /*!< [7..7] IIR错误中断使能位(IIR Error Interrupt Enable) */
+ __IOM uint32_t RST : 1; /*!< [8..8] IIR软复位(IIR Soft Reset) */
+ uint32_t : 23;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+
+ struct {
+ __IOM uint32_t ERR : 1; /*!< [0..0] IIR错误中断标志(IIR Error Pending) */
+ __IM uint32_t BSY : 1; /*!< [1..1] IIR忙标志位(IIR Busy Status) */
+ uint32_t : 30;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+
+ struct {
+ __IOM uint32_t ID : 16; /*!< [15..0] IIR数据输入寄存器(IIR Data-In Register) */
+ uint32_t : 16;
+ } IDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+
+ struct {
+ __IM uint32_t OD : 16; /*!< [15..0] IIR数据输出寄存器(IIR Data-Out Register) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED[4];
+
+ union {
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+
+ struct {
+ __IOM uint32_t FSCL0 : 5; /*!< [4..0] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL0 : 5; /*!< [12..8] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ __IOM uint32_t FSCL1 : 5; /*!< [20..16] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL1 : 5; /*!< [28..24] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ } SCL_b;
+ } ;
+ __IM uint32_t RESERVED1[3];
+
+ union {
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B0COEF : 27; /*!< [26..0] IIR第0组B0系数设置(IIR Group 0 B0COEF RegNster) */
+ uint32_t : 5;
+ } G0B0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B1COEF : 27; /*!< [26..0] IIR第0组B1系数设置(IIR Group 0 B1COEF RegNster) */
+ uint32_t : 5;
+ } G0B1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B2COEF : 27; /*!< [26..0] IIR第0组B2系数设置(IIR Group 0 B2COEF RegNster) */
+ uint32_t : 5;
+ } G0B2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B3COEF : 27; /*!< [26..0] IIR第0组B3系数设置(IIR Group 0 B3COEF RegNster) */
+ uint32_t : 5;
+ } G0B3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B4COEF : 27; /*!< [26..0] IIR第0组B4系数设置(IIR Group 0 B4COEF RegNster) */
+ uint32_t : 5;
+ } G0B4R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B5COEF : 27; /*!< [26..0] IIR第0组B5系数设置(IIR Group 0 B5COEF RegNster) */
+ uint32_t : 5;
+ } G0B5R_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A1COEF : 27; /*!< [26..0] IIR第0组A1系数设置(IIR Group 0 A1COEF RegNster) */
+ uint32_t : 5;
+ } G0A1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A2COEF : 27; /*!< [26..0] IIR第0组A2系数设置(IIR Group 0 A2COEF RegNster) */
+ uint32_t : 5;
+ } G0A2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A3COEF : 27; /*!< [26..0] IIR第0组A3系数设置(IIR Group 0 A3COEF RegNster) */
+ uint32_t : 5;
+ } G0A3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A4COEF : 27; /*!< [26..0] IIR第0组A4系数设置(IIR Group 0 A4COEF RegNster) */
+ uint32_t : 5;
+ } G0A4R_b;
+ } ;
+} IIR1_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR2 (IIR2)
+ */
+
+typedef struct { /*!< (@ 0x4003E200) IIR2 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+
+ struct {
+ __IOM uint32_t IEN : 1; /*!< [0..0] IIR使能(IIR Enable) */
+ uint32_t : 1;
+ __IOM uint32_t ORD : 2; /*!< [3..2] IIR阶数选择(IIR Order Selection) */
+ uint32_t : 3;
+ __IOM uint32_t IEE : 1; /*!< [7..7] IIR错误中断使能位(IIR Error Interrupt Enable) */
+ __IOM uint32_t RST : 1; /*!< [8..8] IIR软复位(IIR Soft Reset) */
+ uint32_t : 23;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+
+ struct {
+ __IOM uint32_t ERR : 1; /*!< [0..0] IIR错误中断标志(IIR Error Pending) */
+ __IM uint32_t BSY : 1; /*!< [1..1] IIR忙标志位(IIR Busy Status) */
+ uint32_t : 30;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+
+ struct {
+ __IOM uint32_t ID : 16; /*!< [15..0] IIR数据输入寄存器(IIR Data-In Register) */
+ uint32_t : 16;
+ } IDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+
+ struct {
+ __IM uint32_t OD : 16; /*!< [15..0] IIR数据输出寄存器(IIR Data-Out Register) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED[4];
+
+ union {
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+
+ struct {
+ __IOM uint32_t FSCL0 : 5; /*!< [4..0] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL0 : 5; /*!< [12..8] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ __IOM uint32_t FSCL1 : 5; /*!< [20..16] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL1 : 5; /*!< [28..24] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ } SCL_b;
+ } ;
+ __IM uint32_t RESERVED1[3];
+
+ union {
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B0COEF : 27; /*!< [26..0] IIR第0组B0系数设置(IIR Group 0 B0COEF RegNster) */
+ uint32_t : 5;
+ } G0B0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B1COEF : 27; /*!< [26..0] IIR第0组B1系数设置(IIR Group 0 B1COEF RegNster) */
+ uint32_t : 5;
+ } G0B1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B2COEF : 27; /*!< [26..0] IIR第0组B2系数设置(IIR Group 0 B2COEF RegNster) */
+ uint32_t : 5;
+ } G0B2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B3COEF : 27; /*!< [26..0] IIR第0组B3系数设置(IIR Group 0 B3COEF RegNster) */
+ uint32_t : 5;
+ } G0B3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B4COEF : 27; /*!< [26..0] IIR第0组B4系数设置(IIR Group 0 B4COEF RegNster) */
+ uint32_t : 5;
+ } G0B4R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B5COEF : 27; /*!< [26..0] IIR第0组B5系数设置(IIR Group 0 B5COEF RegNster) */
+ uint32_t : 5;
+ } G0B5R_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A1COEF : 27; /*!< [26..0] IIR第0组A1系数设置(IIR Group 0 A1COEF RegNster) */
+ uint32_t : 5;
+ } G0A1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A2COEF : 27; /*!< [26..0] IIR第0组A2系数设置(IIR Group 0 A2COEF RegNster) */
+ uint32_t : 5;
+ } G0A2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A3COEF : 27; /*!< [26..0] IIR第0组A3系数设置(IIR Group 0 A3COEF RegNster) */
+ uint32_t : 5;
+ } G0A3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A4COEF : 27; /*!< [26..0] IIR第0组A4系数设置(IIR Group 0 A4COEF RegNster) */
+ uint32_t : 5;
+ } G0A4R_b;
+ } ;
+} IIR2_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR3 (IIR3)
+ */
+
+typedef struct { /*!< (@ 0x4003E300) IIR3 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+
+ struct {
+ __IOM uint32_t IEN : 1; /*!< [0..0] IIR使能(IIR Enable) */
+ uint32_t : 1;
+ __IOM uint32_t ORD : 2; /*!< [3..2] IIR阶数选择(IIR Order Selection) */
+ uint32_t : 3;
+ __IOM uint32_t IEE : 1; /*!< [7..7] IIR错误中断使能位(IIR Error Interrupt Enable) */
+ __IOM uint32_t RST : 1; /*!< [8..8] IIR软复位(IIR Soft Reset) */
+ uint32_t : 23;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+
+ struct {
+ __IOM uint32_t ERR : 1; /*!< [0..0] IIR错误中断标志(IIR Error Pending) */
+ __IM uint32_t BSY : 1; /*!< [1..1] IIR忙标志位(IIR Busy Status) */
+ uint32_t : 30;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+
+ struct {
+ __IOM uint32_t ID : 16; /*!< [15..0] IIR数据输入寄存器(IIR Data-In Register) */
+ uint32_t : 16;
+ } IDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+
+ struct {
+ __IM uint32_t OD : 16; /*!< [15..0] IIR数据输出寄存器(IIR Data-Out Register) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED[4];
+
+ union {
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+
+ struct {
+ __IOM uint32_t FSCL0 : 5; /*!< [4..0] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL0 : 5; /*!< [12..8] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ __IOM uint32_t FSCL1 : 5; /*!< [20..16] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL1 : 5; /*!< [28..24] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ } SCL_b;
+ } ;
+ __IM uint32_t RESERVED1[3];
+
+ union {
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B0COEF : 27; /*!< [26..0] IIR第0组B0系数设置(IIR Group 0 B0COEF RegNster) */
+ uint32_t : 5;
+ } G0B0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B1COEF : 27; /*!< [26..0] IIR第0组B1系数设置(IIR Group 0 B1COEF RegNster) */
+ uint32_t : 5;
+ } G0B1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B2COEF : 27; /*!< [26..0] IIR第0组B2系数设置(IIR Group 0 B2COEF RegNster) */
+ uint32_t : 5;
+ } G0B2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B3COEF : 27; /*!< [26..0] IIR第0组B3系数设置(IIR Group 0 B3COEF RegNster) */
+ uint32_t : 5;
+ } G0B3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B4COEF : 27; /*!< [26..0] IIR第0组B4系数设置(IIR Group 0 B4COEF RegNster) */
+ uint32_t : 5;
+ } G0B4R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B5COEF : 27; /*!< [26..0] IIR第0组B5系数设置(IIR Group 0 B5COEF RegNster) */
+ uint32_t : 5;
+ } G0B5R_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A1COEF : 27; /*!< [26..0] IIR第0组A1系数设置(IIR Group 0 A1COEF RegNster) */
+ uint32_t : 5;
+ } G0A1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A2COEF : 27; /*!< [26..0] IIR第0组A2系数设置(IIR Group 0 A2COEF RegNster) */
+ uint32_t : 5;
+ } G0A2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A3COEF : 27; /*!< [26..0] IIR第0组A3系数设置(IIR Group 0 A3COEF RegNster) */
+ uint32_t : 5;
+ } G0A3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A4COEF : 27; /*!< [26..0] IIR第0组A4系数设置(IIR Group 0 A4COEF RegNster) */
+ uint32_t : 5;
+ } G0A4R_b;
+ } ;
+} IIR3_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR4 (IIR4)
+ */
+
+typedef struct { /*!< (@ 0x4003E400) IIR4 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+
+ struct {
+ __IOM uint32_t IEN : 1; /*!< [0..0] IIR使能(IIR Enable) */
+ uint32_t : 1;
+ __IOM uint32_t ORD : 2; /*!< [3..2] IIR阶数选择(IIR Order Selection) */
+ uint32_t : 3;
+ __IOM uint32_t IEE : 1; /*!< [7..7] IIR错误中断使能位(IIR Error Interrupt Enable) */
+ __IOM uint32_t RST : 1; /*!< [8..8] IIR软复位(IIR Soft Reset) */
+ uint32_t : 23;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+
+ struct {
+ __IOM uint32_t ERR : 1; /*!< [0..0] IIR错误中断标志(IIR Error Pending) */
+ __IM uint32_t BSY : 1; /*!< [1..1] IIR忙标志位(IIR Busy Status) */
+ uint32_t : 30;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+
+ struct {
+ __IOM uint32_t ID : 16; /*!< [15..0] IIR数据输入寄存器(IIR Data-In Register) */
+ uint32_t : 16;
+ } IDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+
+ struct {
+ __IM uint32_t OD : 16; /*!< [15..0] IIR数据输出寄存器(IIR Data-Out Register) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED[4];
+
+ union {
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+
+ struct {
+ __IOM uint32_t FSCL0 : 5; /*!< [4..0] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL0 : 5; /*!< [12..8] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ __IOM uint32_t FSCL1 : 5; /*!< [20..16] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL1 : 5; /*!< [28..24] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ } SCL_b;
+ } ;
+ __IM uint32_t RESERVED1[3];
+
+ union {
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B0COEF : 27; /*!< [26..0] IIR第0组B0系数设置(IIR Group 0 B0COEF RegNster) */
+ uint32_t : 5;
+ } G0B0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B1COEF : 27; /*!< [26..0] IIR第0组B1系数设置(IIR Group 0 B1COEF RegNster) */
+ uint32_t : 5;
+ } G0B1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B2COEF : 27; /*!< [26..0] IIR第0组B2系数设置(IIR Group 0 B2COEF RegNster) */
+ uint32_t : 5;
+ } G0B2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B3COEF : 27; /*!< [26..0] IIR第0组B3系数设置(IIR Group 0 B3COEF RegNster) */
+ uint32_t : 5;
+ } G0B3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B4COEF : 27; /*!< [26..0] IIR第0组B4系数设置(IIR Group 0 B4COEF RegNster) */
+ uint32_t : 5;
+ } G0B4R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B5COEF : 27; /*!< [26..0] IIR第0组B5系数设置(IIR Group 0 B5COEF RegNster) */
+ uint32_t : 5;
+ } G0B5R_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A1COEF : 27; /*!< [26..0] IIR第0组A1系数设置(IIR Group 0 A1COEF RegNster) */
+ uint32_t : 5;
+ } G0A1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A2COEF : 27; /*!< [26..0] IIR第0组A2系数设置(IIR Group 0 A2COEF RegNster) */
+ uint32_t : 5;
+ } G0A2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A3COEF : 27; /*!< [26..0] IIR第0组A3系数设置(IIR Group 0 A3COEF RegNster) */
+ uint32_t : 5;
+ } G0A3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A4COEF : 27; /*!< [26..0] IIR第0组A4系数设置(IIR Group 0 A4COEF RegNster) */
+ uint32_t : 5;
+ } G0A4R_b;
+ } ;
+} IIR4_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ IIR5 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief IIR5 (IIR5)
+ */
+
+typedef struct { /*!< (@ 0x4003E500) IIR5 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) IIR Control Register */
+
+ struct {
+ __IOM uint32_t IEN : 1; /*!< [0..0] IIR使能(IIR Enable) */
+ uint32_t : 1;
+ __IOM uint32_t ORD : 2; /*!< [3..2] IIR阶数选择(IIR Order Selection) */
+ uint32_t : 3;
+ __IOM uint32_t IEE : 1; /*!< [7..7] IIR错误中断使能位(IIR Error Interrupt Enable) */
+ __IOM uint32_t RST : 1; /*!< [8..8] IIR软复位(IIR Soft Reset) */
+ uint32_t : 23;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000004) IIR Status Register */
+
+ struct {
+ __IOM uint32_t ERR : 1; /*!< [0..0] IIR错误中断标志(IIR Error Pending) */
+ __IM uint32_t BSY : 1; /*!< [1..1] IIR忙标志位(IIR Busy Status) */
+ uint32_t : 30;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IDR; /*!< (@ 0x00000008) IIR Data-In Register */
+
+ struct {
+ __IOM uint32_t ID : 16; /*!< [15..0] IIR数据输入寄存器(IIR Data-In Register) */
+ uint32_t : 16;
+ } IDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x0000000C) IIR Data-Out Register */
+
+ struct {
+ __IM uint32_t OD : 16; /*!< [15..0] IIR数据输出寄存器(IIR Data-Out Register) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED[4];
+
+ union {
+ __IOM uint32_t SCL; /*!< (@ 0x00000020) IIR Scale Register */
+
+ struct {
+ __IOM uint32_t FSCL0 : 5; /*!< [4..0] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL0 : 5; /*!< [12..8] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ __IOM uint32_t FSCL1 : 5; /*!< [20..16] IIR反馈缩放控制位(IIR Feedback Scale) */
+ uint32_t : 3;
+ __IOM uint32_t OSCL1 : 5; /*!< [28..24] IIR输出缩放控制位(IIR Output Scale) */
+ uint32_t : 3;
+ } SCL_b;
+ } ;
+ __IM uint32_t RESERVED1[3];
+
+ union {
+ __IOM uint32_t G0B0R; /*!< (@ 0x00000030) IIR Group 0 B0COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B0COEF : 27; /*!< [26..0] IIR第0组B0系数设置(IIR Group 0 B0COEF RegNster) */
+ uint32_t : 5;
+ } G0B0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B1R; /*!< (@ 0x00000034) IIR Group 0 B1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B1COEF : 27; /*!< [26..0] IIR第0组B1系数设置(IIR Group 0 B1COEF RegNster) */
+ uint32_t : 5;
+ } G0B1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B2R; /*!< (@ 0x00000038) IIR Group 0 B2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B2COEF : 27; /*!< [26..0] IIR第0组B2系数设置(IIR Group 0 B2COEF RegNster) */
+ uint32_t : 5;
+ } G0B2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B3R; /*!< (@ 0x0000003C) IIR Group 0 B3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B3COEF : 27; /*!< [26..0] IIR第0组B3系数设置(IIR Group 0 B3COEF RegNster) */
+ uint32_t : 5;
+ } G0B3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B4R; /*!< (@ 0x00000040) IIR Group 0 B4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B4COEF : 27; /*!< [26..0] IIR第0组B4系数设置(IIR Group 0 B4COEF RegNster) */
+ uint32_t : 5;
+ } G0B4R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0B5R; /*!< (@ 0x00000044) IIR Group 0 B5COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0B5COEF : 27; /*!< [26..0] IIR第0组B5系数设置(IIR Group 0 B5COEF RegNster) */
+ uint32_t : 5;
+ } G0B5R_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t G0A1R; /*!< (@ 0x00000050) IIR Group 0 A1COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A1COEF : 27; /*!< [26..0] IIR第0组A1系数设置(IIR Group 0 A1COEF RegNster) */
+ uint32_t : 5;
+ } G0A1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A2R; /*!< (@ 0x00000054) IIR Group 0 A2COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A2COEF : 27; /*!< [26..0] IIR第0组A2系数设置(IIR Group 0 A2COEF RegNster) */
+ uint32_t : 5;
+ } G0A2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A3R; /*!< (@ 0x00000058) IIR Group 0 A3COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A3COEF : 27; /*!< [26..0] IIR第0组A3系数设置(IIR Group 0 A3COEF RegNster) */
+ uint32_t : 5;
+ } G0A3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t G0A4R; /*!< (@ 0x0000005C) IIR Group 0 A4COEF RegNster */
+
+ struct {
+ __IOM uint32_t G0A4COEF : 27; /*!< [26..0] IIR第0组A4系数设置(IIR Group 0 A4COEF RegNster) */
+ uint32_t : 5;
+ } G0A4R_b;
+ } ;
+} IIR5_Type; /*!< Size = 96 (0x60) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2C0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C0 (I2C0)
+ */
+
+typedef struct { /*!< (@ 0x40000000) I2C0 Structure */
+
+ union {
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) I2C Enable Register */
+
+ struct {
+ __IOM uint32_t I2CEN : 1; /*!< [0..0] I2C使能位（I2C Enable） */
+ __IOM uint32_t UDRCFG : 1; /*!< [1..1] I2C下溢条件时从机发送行为（I2C Behavior At
+ Slave Underrun Condition） */
+ __IOM uint32_t RFRST : 1; /*!< [2..2] I2C RXFIFO复位（RXFIFO Reset Flag） */
+ __IOM uint32_t TFRST : 1; /*!< [3..3] I2C TXFIFO复位（TXFIFO Reset Flag） */
+ __IOM uint32_t RLSCMD : 1; /*!< [4..4] I2C启动传输命令（I2C Release Command） */
+ __IOM uint32_t DMARXEN : 1; /*!< [5..5] I2C接收DMA使能位（I2C RX-DMA Enable） */
+ __IOM uint32_t DMATXEN : 1; /*!< [6..6] I2C发送DMA使能位（I2C TX-DMA Enable） */
+ __IOM uint32_t RFHSEN : 1; /*!< [7..7] I2C接收数据时钟延长模式位（I2C Receive Date
+ SCL Stretching Mode） */
+ __IM uint32_t MSTEN : 1; /*!< [8..8] I2C主机状态位（I2C Master Status） */
+ __IOM uint32_t A10BEN : 1; /*!< [9..9] I2C 10BIT地址使能位（I2C 10BIT Address Enable） */
+ __IOM uint32_t GCEN : 1; /*!< [10..10] I2C广播地址使能位（I2C General Call Address
+ Enable） */
+ __IOM uint32_t OSAEN : 1; /*!< [11..11] I2C可选从机地址使能（I2C Optional Slave Address
+ Register） */
+ __IOM uint32_t SMALEN : 1; /*!< [12..12] SMBUS报警功能使能位（SMBUS Alert Enable） */
+ __IOM uint32_t SMARPEN : 1; /*!< [13..13] SMBUS设备默认地址使能位（SMBUS Device Default
+ Address Enable） */
+ __IOM uint32_t SMHEN : 1; /*!< [14..14] SMBUS HOST地址使能位（SMBUS Host Address Enable） */
+ __IOM uint32_t SMTOEN : 1; /*!< [15..15] SMBUS超时功能使能（SMBUS Timeout Enable） */
+ __IOM uint32_t MSTCH : 1; /*!< [16..16] I2C接收数据时钟延长使能位（I2C Receive
+ Date SCL Stretching Enable） */
+ __IOM uint32_t NSTCH : 1; /*!< [17..17] I2C时钟延长禁止位（I2C SCL Stretching Disable） */
+ __IM uint32_t HDRX : 2; /*!< [19..18] I2C总线状态（I2C Bus Status） */
+ uint32_t : 12;
+ } ENABLE_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) I2C Transmission Control Register */
+
+ struct {
+ __IOM uint32_t I2CCNT : 8; /*!< [7..0] I2C传输字节数（I2C Number Of Data Byte Count） */
+ __IOM uint32_t DIRECT : 1; /*!< [8..8] I2C传输方向（I2C Direct Configuration） */
+ __IOM uint32_t STOP : 1; /*!< [9..9] I2C停止传输（I2C Stop Transmission） */
+ __IOM uint32_t START : 1; /*!< [10..10] I2C START生成（I2C START Generation） */
+ __IOM uint32_t NACK : 1; /*!< [11..11] I2C NACK生成（I2C NACK Generation） */
+ __IOM uint32_t PECBYTE : 1; /*!< [12..12] SMBUS数据包错误校验字节（SMBUS Packet Error
+ Checking Byte） */
+ __IOM uint32_t MODE10B : 1; /*!< [13..13] I2C 10BIT传输模式选择（I2C 10BIT Master-Read
+ Mode Select） */
+ __IOM uint32_t AUTOEND : 1; /*!< [14..14] I2C自动结束模式（I2C Automatic End Mode） */
+ uint32_t : 17;
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) I2C Baud Rate Register */
+
+ struct {
+ __IOM uint32_t SCLLCNT : 10; /*!< [9..0] I2C SCL低电平周期（I2C SCL Low Period） */
+ uint32_t : 6;
+ __IOM uint32_t SCLHCNT : 10; /*!< [25..16] I2C SCL高电平周期（I2C SCL High Period） */
+ uint32_t : 6;
+ } BAUD_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDRDR; /*!< (@ 0x0000000C) I2C Underrun Data Register */
+
+ struct {
+ __IOM uint32_t UDRDR : 8; /*!< [7..0] I2C从模式下溢时数据写寄存器（I2C Data At
+ Slave Underrun Condition） */
+ uint32_t : 24;
+ } UDRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) I2C FIFO Control Register */
+
+ struct {
+ __IOM uint32_t TXFTLR : 4; /*!< [3..0] I2C TXFIFO空中断阈值（I2C TXFIFO Empty Threshold） */
+ __IOM uint32_t RXFTLR : 4; /*!< [7..4] I2C RXFIFO满中断阈值（I2C RXFIFO Full Threshold） */
+ uint32_t : 24;
+ } FIFOCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR; /*!< (@ 0x00000014) I2C Target Address Register */
+
+ struct {
+ __IOM uint32_t TAR : 10; /*!< [9..0] I2C主机目标地址（I2C Target Address） */
+ uint32_t : 22;
+ } TAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SAR; /*!< (@ 0x00000018) I2C Slave Address Register */
+
+ struct {
+ __IOM uint32_t SAR : 10; /*!< [9..0] I2C从机地址（I2C Slave Address） */
+ uint32_t : 22;
+ } SAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t OSAR; /*!< (@ 0x0000001C) I2C Optional Slave Address Register */
+
+ struct {
+ __IOM uint32_t OSAR : 10; /*!< [9..0] I2C可选的从机地址（I2C Optional Slave Address
+ Register） */
+ uint32_t : 6;
+ __IOM uint32_t OSAM : 10; /*!< [25..16] I2C可选的从机地址屏蔽（I2C Optional Slave
+ Address Masks Register） */
+ uint32_t : 6;
+ } OSAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PEC; /*!< (@ 0x00000020) I2C RX PEC Register */
+
+ struct {
+ __IM uint32_t RXPEC : 8; /*!< [7..0] SMBUS接收PEC数据寄存器（SMBUS RX PEC Data Register） */
+ __IM uint32_t IDPEC : 8; /*!< [15..8] SMBUS自身PEC数据寄存器（SMBUS ID PEC Data Register） */
+ uint32_t : 16;
+ } PEC_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING; /*!< (@ 0x00000024) I2C Timing Register */
+
+ struct {
+ __IOM uint32_t HDDAT : 8; /*!< [7..0] I2C数据保持时间（Data Hold Time） */
+ __IOM uint32_t SUDAT : 8; /*!< [15..8] I2C数据建立时间（Data Setup Time） */
+ __IOM uint32_t SLVSUDAT : 8; /*!< [23..16] I2C从机数据建立时间（I2C Data Setup Time） */
+ __IOM uint32_t SPKLEN : 8; /*!< [31..24] I2C尖峰抑制寄存器（I2C Spike Suppression Limit
+ Register） */
+ } TIMING_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMEOUT; /*!< (@ 0x00000028) I2C Clock Extension Timeout Register */
+
+ struct {
+ __IOM uint32_t MEXTTO : 16; /*!< [15..0] I2C主机时钟扩展超时（I2C Master Clock Extension
+ Timeout Register） */
+ __IOM uint32_t SEXTTO : 16; /*!< [31..16] I2C从机时钟扩展超时（I2C Slave Clock Extension
+ Timeout Register） */
+ } TIMEOUT_b;
+ } ;
+
+ union {
+ __IOM uint32_t BUSTOUT; /*!< (@ 0x0000002C) I2C Bus Timeout Register */
+
+ struct {
+ __IOM uint32_t BTO : 16; /*!< [15..0] I2C总线超时（I2C Bus Timeout） */
+ uint32_t : 15;
+ __IOM uint32_t TOSEL : 1; /*!< [31..31] I2C空闲时钟超时选择（I2C Clock Timeout Select） */
+ } BUSTOUT_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTREN; /*!< (@ 0x00000030) I2C Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RXFIE : 1; /*!< [0..0] I2C RXFIFO满阈值中断使能（I2C RXFIFO Full Threshold
+ Interrupt Enable） */
+ __IOM uint32_t TXEIE : 1; /*!< [1..1] I2C TXFIFO空阈值中断使能（I2C TXFIFO Empty Threshold
+ Interrupt Enable） */
+ __IOM uint32_t RXOFIE : 1; /*!< [2..2] I2C RXFIFO上溢中断使能（I2C RXFIFO Overflow Interrupt
+ Enable） */
+ __IOM uint32_t RXUFIE : 1; /*!< [3..3] I2C RXFIFO下溢中断使能（I2C RXFIFO Underflow Interrupt
+ Enable） */
+ __IOM uint32_t TXOFIE : 1; /*!< [4..4] I2C TXFIFO上溢中断使能（I2C TXFIFO Overflow Interrupt
+ Enable） */
+ __IOM uint32_t TXUFIE : 1; /*!< [5..5] I2C 从机TXFIFO下溢中断使能（I2C Slave TXFIFO
+ Underflow Interrupt Enable） */
+ __IOM uint32_t ARBFIE : 1; /*!< [6..6] I2C仲裁失败中断使能（I2C Arbitration Fail Interrupt
+ Enable） */
+ __IOM uint32_t BUSEIE : 1; /*!< [7..7] I2C总线错误中断使能（I2C Bus Error Interrupt
+ Enable） */
+ __IOM uint32_t MDEIE : 1; /*!< [8..8] I2C传输完成中断使能（I2C Transmission Done Interrupt
+ Enable） */
+ __IOM uint32_t TXADIE : 1; /*!< [9..9] I2C从机地址匹配发送中断使能（I2C Slave Tx
+ Address Matching Interrupt Enable） */
+ __IOM uint32_t RXADIE : 1; /*!< [10..10] I2C从机地址匹配接收中断使能（I2C Slave
+ RX Address Matching Interrupt Enable） */
+ __IOM uint32_t STDETIE : 1; /*!< [11..11] I2C检测到START位中断使能（I2C Detected START/RESTART
+ Interrupt Enable） */
+ __IOM uint32_t SPDETIE : 1; /*!< [12..12] I2C检测到STOP位中断使能（I2C Detected STOP
+ Interrupt Enable） */
+ __IOM uint32_t RSDETIE : 1; /*!< [13..13] I2C检测到RESTART位中断使能（I2C Detected RESTART
+ Interrupt Enable） */
+ __IOM uint32_t NACKIE : 1; /*!< [14..14] I2C检测到NACK位中断使能（I2C Detected NACK
+ Interrupt Enable） */
+ __IOM uint32_t ALDETIE : 1; /*!< [15..15] I2C检测到ALERT信号中断使能（I2C Detected
+ ALERT Signal Interrupt Enable） */
+ __IOM uint32_t MEXTOIE : 1; /*!< [16..16] I2C Tmext超时中断使能（I2C Master Detected Timeout
+ Interrupt Enable） */
+ __IOM uint32_t SEXTOIE : 1; /*!< [17..17] I2C Tsext超时中断使能（I2C Slave Detected Timeout
+ Interrupt Enable） */
+ __IOM uint32_t PECRXIE : 1; /*!< [18..18] I2C收到PEC且校验错误中断使能（I2C Received
+ PEC Byte With Checksum Error Interrupt Enable） */
+ __IOM uint32_t RXGCIE : 1; /*!< [19..19] I2C从机接收广播地址中断使能（Slave RX
+ General Call Interrupt Enable） */
+ __IOM uint32_t MTXAIE : 1; /*!< [20..20] I2C主机发送地址完成中断使能（Master TX
+ Adderss Done Interrupt Enable） */
+ __IOM uint32_t SWTXIE : 1; /*!< [21..21] I2C从机等待数据拉住SCL为低中断使能（I2C
+ Slave Hold SCL Low For Waiting Data Interrupt Enable） */
+ __IOM uint32_t MOHIE : 1; /*!< [22..22] I2C主机挂起拉住SCL为低中断使能（I2C Master
+ Hold SCL Low Interrupt Enable） */
+ __IOM uint32_t BTOIE : 1; /*!< [23..23] I2C 总线超时中断使能（I2C Bus Timeout Interrupt
+ Enable） */
+ uint32_t : 8;
+ } INTREN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTR; /*!< (@ 0x00000034) I2C Interrupt Register */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] I2C RXFIFO满阈值中断（I2C RXFIFO Full Threshold
+ Interrupt） */
+ __IM uint32_t TXEI : 1; /*!< [1..1] I2C TXFIFO空阈值中断（I2C TXFIFO Empty Threshold
+ Interrupt） */
+ __IOM uint32_t RXOFI : 1; /*!< [2..2] I2C RXFIFO上溢中断（I2C RXFIFO Overflow Interrupt） */
+ __IOM uint32_t RXUFI : 1; /*!< [3..3] I2C RXFIFO下溢中断（I2C RXFIFO Underflow Interrupt） */
+ __IOM uint32_t TXOFI : 1; /*!< [4..4] I2C TXFIFO上溢中断（I2C TXFIFO Overflow Interrupt） */
+ __IOM uint32_t TXUFI : 1; /*!< [5..5] I2C 从机TXFIFO下溢中断（I2C Slave TXFIFO Underflow
+ Interrupt） */
+ __IOM uint32_t ARBFI : 1; /*!< [6..6] I2C仲裁失败中断（I2C Arbitration Fail Interrupt） */
+ __IOM uint32_t BUSEI : 1; /*!< [7..7] I2C总线错误中断（I2C Bus Error Interrupt） */
+ __IOM uint32_t MDEI : 1; /*!< [8..8] I2C传输完成中断（I2C Transmission Done Interrupt） */
+ __IOM uint32_t TXADI : 1; /*!< [9..9] I2C从机地址匹配发送中断（I2C Slave TX Address
+ Matching Interrupt） */
+ __IOM uint32_t RXADI : 1; /*!< [10..10] I2C从机地址匹配接收中断（I2C Slave RX Address
+ Matching Interrupt） */
+ __IOM uint32_t STDETI : 1; /*!< [11..11] I2C检测到START位中断（I2C Detected START/RESTART
+ Interrupt） */
+ __IOM uint32_t SPETI : 1; /*!< [12..12] I2C检测到STOP位中断（I2C Detected STOP Interrupt） */
+ __IOM uint32_t RSDETI : 1; /*!< [13..13] I2C检测到RESTART位中断（I2C Detected RESTART
+ Interrupt） */
+ __IOM uint32_t NACKI : 1; /*!< [14..14] I2C检测到NACK位中断（I2C Detected NACK Interrupt） */
+ __IOM uint32_t ALDETI : 1; /*!< [15..15] I2C检测到ALERT信号中断（I2C Detected ALERT
+ Signal Interrupt） */
+ __IOM uint32_t MEXTOI : 1; /*!< [16..16] I2C Tmext超时中断（I2C Master Detected Timeout
+ Interrupt） */
+ __IOM uint32_t SEXTOI : 1; /*!< [17..17] I2C Tsext超时中断（I2C Slave Detected Timeout
+ Interrupt） */
+ __IOM uint32_t PECRXI : 1; /*!< [18..18] I2C收到PEC且校验错误中断（I2C Received PEC
+ Byte with Checksum Error Interrupt） */
+ __IOM uint32_t RXGCI : 1; /*!< [19..19] 从机收到广播中断（Slave RX General Call Interrupt
+ ） */
+ __IOM uint32_t MTXAI : 1; /*!< [20..20] 主机发送地址完成中断（Master TX Adderss
+ Done Interrupt ） */
+ __IOM uint32_t SWTXI : 1; /*!< [21..21] I2C从机等待数据拉住SCL为低中断（I2C Slave
+ Hold SCL Low For Waiting Data Interrupt） */
+ __IM uint32_t MOHI : 1; /*!< [22..22] I2C主机挂起拉住SCL为低中断（I2C Master Hold
+ SCL Low Interrupt） */
+ __IOM uint32_t BTOI : 1; /*!< [23..23] I2C 总线超时中断（I2C Bus Timeout Interrupt） */
+ __IM uint32_t RCNT : 8; /*!< [31..24] I2C剩余数据计数状态（I2C Remain Data Count
+ Status） */
+ } INTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x00000038) I2C Status Register */
+
+ struct {
+ __IM uint32_t FSMBSY : 1; /*!< [0..0] I2C状态机忙碌状态（I2C State Busy Status） */
+ __IM uint32_t BUSBSY : 1; /*!< [1..1] I2C总线忙碌状态（I2C Bus Busy Status） */
+ __IM uint32_t ARBSTA : 2; /*!< [3..2] I2C仲裁失败状态（I2C Arbitration Fail Status） */
+ uint32_t : 12;
+ __IM uint32_t TXFLR : 5; /*!< [20..16] I2C TXFIFO剩余数据量（I2C TXFIFO Remaining Data
+ Number Status） */
+ __IM uint32_t TFE : 1; /*!< [21..21] I2C TXFIFO空标志（I2C TXFIFO Empty Status） */
+ __IM uint32_t TFF : 1; /*!< [22..22] I2C TXFIFO满标志（I2C TXFIFO Full Status） */
+ uint32_t : 1;
+ __IM uint32_t RXFLR : 5; /*!< [28..24] I2C RXFIFO剩余数据量（I2C RXFIFO Remaining Data
+ Number Status） */
+ __IM uint32_t RFE : 1; /*!< [29..29] I2C RXFIFO空标志（I2C RXFIFO Empty Status） */
+ __IM uint32_t RFF : 1; /*!< [30..30] I2C RXFIFO满标志（I2C RXFIFO Full Status） */
+ uint32_t : 1;
+ } STATUS_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t TXDATA; /*!< (@ 0x00000040) I2C TXFIFO Data Registers */
+
+ struct {
+ __IOM uint32_t TXDATA : 8; /*!< [7..0] I2C数据写寄存器（I2C Data For Transmiting Register） */
+ uint32_t : 24;
+ } TXDATA_b;
+ } ;
+
+ union {
+ __IOM uint32_t RXDATA; /*!< (@ 0x00000044) I2C RXFIFO Data Registers */
+
+ struct {
+ __IM uint32_t RXDATA : 8; /*!< [7..0] I2C数据读寄存器（I2C Data For Receiving Register） */
+ uint32_t : 24;
+ } RXDATA_b;
+ } ;
+
+ union {
+ __IOM uint32_t RXADDR; /*!< (@ 0x00000048) I2C RX ADDR Register */
+
+ struct {
+ __IM uint32_t DIR : 1; /*!< [0..0] I2C从机收到的传输方向（I2C Slave Received Direction
+ Status） */
+ __IM uint32_t ADDR : 7; /*!< [7..1] I2C从机收到的地址（I2C Slave Received Address
+ Status） */
+ uint32_t : 24;
+ } RXADDR_b;
+ } ;
+} I2C0_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2C1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C1 (I2C1)
+ */
+
+typedef struct { /*!< (@ 0x40001000) I2C1 Structure */
+
+ union {
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) I2C Enable Register */
+
+ struct {
+ __IOM uint32_t I2CEN : 1; /*!< [0..0] I2C使能位（I2C Enable） */
+ __IOM uint32_t UDRCFG : 1; /*!< [1..1] I2C下溢条件时从机发送行为（I2C Behavior At
+ Slave Underrun Condition） */
+ __IOM uint32_t RFRST : 1; /*!< [2..2] I2C RXFIFO复位（RXFIFO Reset Flag） */
+ __IOM uint32_t TFRST : 1; /*!< [3..3] I2C TXFIFO复位（TXFIFO Reset Flag） */
+ __IOM uint32_t RLSCMD : 1; /*!< [4..4] I2C启动传输命令（I2C Release Command） */
+ __IOM uint32_t DMARXEN : 1; /*!< [5..5] I2C接收DMA使能位（I2C RX-DMA Enable） */
+ __IOM uint32_t DMATXEN : 1; /*!< [6..6] I2C发送DMA使能位（I2C TX-DMA Enable） */
+ __IOM uint32_t RFHSEN : 1; /*!< [7..7] I2C接收数据时钟延长模式位（I2C Receive Date
+ SCL Stretching Mode） */
+ __IM uint32_t MSTEN : 1; /*!< [8..8] I2C主机状态位（I2C Master Status） */
+ __IOM uint32_t A10BEN : 1; /*!< [9..9] I2C 10BIT地址使能位（I2C 10BIT Address Enable） */
+ __IOM uint32_t GCEN : 1; /*!< [10..10] I2C广播地址使能位（I2C General Call Address
+ Enable） */
+ __IOM uint32_t OSAEN : 1; /*!< [11..11] I2C可选从机地址使能（I2C Optional Slave Address
+ Register） */
+ __IOM uint32_t SMALEN : 1; /*!< [12..12] SMBUS报警功能使能位（SMBUS Alert Enable） */
+ __IOM uint32_t SMARPEN : 1; /*!< [13..13] SMBUS设备默认地址使能位（SMBUS Device Default
+ Address Enable） */
+ __IOM uint32_t SMHEN : 1; /*!< [14..14] SMBUS HOST地址使能位（SMBUS Host Address Enable） */
+ __IOM uint32_t SMTOEN : 1; /*!< [15..15] SMBUS超时功能使能（SMBUS Timeout Enable） */
+ __IOM uint32_t MSTCH : 1; /*!< [16..16] I2C接收数据时钟延长使能位（I2C Receive
+ Date SCL Stretching Enable） */
+ __IOM uint32_t NSTCH : 1; /*!< [17..17] I2C时钟延长禁止位（I2C SCL Stretching Disable） */
+ __IM uint32_t HDRX : 2; /*!< [19..18] I2C总线状态（I2C Bus Status） */
+ uint32_t : 12;
+ } ENABLE_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) I2C Transmission Control Register */
+
+ struct {
+ __IOM uint32_t I2CCNT : 8; /*!< [7..0] I2C传输字节数（I2C Number Of Data Byte Count） */
+ __IOM uint32_t DIRECT : 1; /*!< [8..8] I2C传输方向（I2C Direct Configuration） */
+ __IOM uint32_t STOP : 1; /*!< [9..9] I2C停止传输（I2C Stop Transmission） */
+ __IOM uint32_t START : 1; /*!< [10..10] I2C START生成（I2C START Generation） */
+ __IOM uint32_t NACK : 1; /*!< [11..11] I2C NACK生成（I2C NACK Generation） */
+ __IOM uint32_t PECBYTE : 1; /*!< [12..12] SMBUS数据包错误校验字节（SMBUS Packet Error
+ Checking Byte） */
+ __IOM uint32_t MODE10B : 1; /*!< [13..13] I2C 10BIT传输模式选择（I2C 10BIT Master-Read
+ Mode Select） */
+ __IOM uint32_t AUTOEND : 1; /*!< [14..14] I2C自动结束模式（I2C Automatic End Mode） */
+ uint32_t : 17;
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) I2C Baud Rate Register */
+
+ struct {
+ __IOM uint32_t SCLLCNT : 10; /*!< [9..0] I2C SCL低电平周期（I2C SCL Low Period） */
+ uint32_t : 6;
+ __IOM uint32_t SCLHCNT : 10; /*!< [25..16] I2C SCL高电平周期（I2C SCL High Period） */
+ uint32_t : 6;
+ } BAUD_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDRDR; /*!< (@ 0x0000000C) I2C Underrun Data Register */
+
+ struct {
+ __IOM uint32_t UDRDR : 8; /*!< [7..0] I2C从模式下溢时数据写寄存器（I2C Data At
+ Slave Underrun Condition） */
+ uint32_t : 24;
+ } UDRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) I2C FIFO Control Register */
+
+ struct {
+ __IOM uint32_t TXFTLR : 4; /*!< [3..0] I2C TXFIFO空中断阈值（I2C TXFIFO Empty Threshold） */
+ __IOM uint32_t RXFTLR : 4; /*!< [7..4] I2C RXFIFO满中断阈值（I2C RXFIFO Full Threshold） */
+ uint32_t : 24;
+ } FIFOCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR; /*!< (@ 0x00000014) I2C Target Address Register */
+
+ struct {
+ __IOM uint32_t TAR : 10; /*!< [9..0] I2C主机目标地址（I2C Target Address） */
+ uint32_t : 22;
+ } TAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SAR; /*!< (@ 0x00000018) I2C Slave Address Register */
+
+ struct {
+ __IOM uint32_t SAR : 10; /*!< [9..0] I2C从机地址（I2C Slave Address） */
+ uint32_t : 22;
+ } SAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t OSAR; /*!< (@ 0x0000001C) I2C Optional Slave Address Register */
+
+ struct {
+ __IOM uint32_t OSAR : 10; /*!< [9..0] I2C可选的从机地址（I2C Optional Slave Address
+ Register） */
+ uint32_t : 6;
+ __IOM uint32_t OSAM : 10; /*!< [25..16] I2C可选的从机地址屏蔽（I2C Optional Slave
+ Address Masks Register） */
+ uint32_t : 6;
+ } OSAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PEC; /*!< (@ 0x00000020) I2C RX PEC Register */
+
+ struct {
+ __IM uint32_t RXPEC : 8; /*!< [7..0] SMBUS接收PEC数据寄存器（SMBUS RX PEC Data Register） */
+ __IM uint32_t IDPEC : 8; /*!< [15..8] SMBUS自身PEC数据寄存器（SMBUS ID PEC Data Register） */
+ uint32_t : 16;
+ } PEC_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING; /*!< (@ 0x00000024) I2C Timing Register */
+
+ struct {
+ __IOM uint32_t HDDAT : 8; /*!< [7..0] I2C数据保持时间（Data Hold Time） */
+ __IOM uint32_t SUDAT : 8; /*!< [15..8] I2C数据建立时间（Data Setup Time） */
+ __IOM uint32_t SLVSUDAT : 8; /*!< [23..16] I2C从机数据建立时间（I2C Data Setup Time） */
+ __IOM uint32_t SPKLEN : 8; /*!< [31..24] I2C尖峰抑制寄存器（I2C Spike Suppression Limit
+ Register） */
+ } TIMING_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMEOUT; /*!< (@ 0x00000028) I2C Clock Extension Timeout Register */
+
+ struct {
+ __IOM uint32_t MEXTTO : 16; /*!< [15..0] I2C主机时钟扩展超时（I2C Master Clock Extension
+ Timeout Register） */
+ __IOM uint32_t SEXTTO : 16; /*!< [31..16] I2C从机时钟扩展超时（I2C Slave Clock Extension
+ Timeout Register） */
+ } TIMEOUT_b;
+ } ;
+
+ union {
+ __IOM uint32_t BUSTOUT; /*!< (@ 0x0000002C) I2C Bus Timeout Register */
+
+ struct {
+ __IOM uint32_t BTO : 16; /*!< [15..0] I2C总线超时（I2C Bus Timeout） */
+ uint32_t : 15;
+ __IOM uint32_t TOSEL : 1; /*!< [31..31] I2C空闲时钟超时选择（I2C Clock Timeout Select） */
+ } BUSTOUT_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTREN; /*!< (@ 0x00000030) I2C Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RXFIE : 1; /*!< [0..0] I2C RXFIFO满阈值中断使能（I2C RXFIFO Full Threshold
+ Interrupt Enable） */
+ __IOM uint32_t TXEIE : 1; /*!< [1..1] I2C TXFIFO空阈值中断使能（I2C TXFIFO Empty Threshold
+ Interrupt Enable） */
+ __IOM uint32_t RXOFIE : 1; /*!< [2..2] I2C RXFIFO上溢中断使能（I2C RXFIFO Overflow Interrupt
+ Enable） */
+ __IOM uint32_t RXUFIE : 1; /*!< [3..3] I2C RXFIFO下溢中断使能（I2C RXFIFO Underflow Interrupt
+ Enable） */
+ __IOM uint32_t TXOFIE : 1; /*!< [4..4] I2C TXFIFO上溢中断使能（I2C TXFIFO Overflow Interrupt
+ Enable） */
+ __IOM uint32_t TXUFIE : 1; /*!< [5..5] I2C 从机TXFIFO下溢中断使能（I2C Slave TXFIFO
+ Underflow Interrupt Enable） */
+ __IOM uint32_t ARBFIE : 1; /*!< [6..6] I2C仲裁失败中断使能（I2C Arbitration Fail Interrupt
+ Enable） */
+ __IOM uint32_t BUSEIE : 1; /*!< [7..7] I2C总线错误中断使能（I2C Bus Error Interrupt
+ Enable） */
+ __IOM uint32_t MDEIE : 1; /*!< [8..8] I2C传输完成中断使能（I2C Transmission Done Interrupt
+ Enable） */
+ __IOM uint32_t TXADIE : 1; /*!< [9..9] I2C从机地址匹配发送中断使能（I2C Slave Tx
+ Address Matching Interrupt Enable） */
+ __IOM uint32_t RXADIE : 1; /*!< [10..10] I2C从机地址匹配接收中断使能（I2C Slave
+ RX Address Matching Interrupt Enable） */
+ __IOM uint32_t STDETIE : 1; /*!< [11..11] I2C检测到START位中断使能（I2C Detected START/RESTART
+ Interrupt Enable） */
+ __IOM uint32_t SPDETIE : 1; /*!< [12..12] I2C检测到STOP位中断使能（I2C Detected STOP
+ Interrupt Enable） */
+ __IOM uint32_t RSDETIE : 1; /*!< [13..13] I2C检测到RESTART位中断使能（I2C Detected RESTART
+ Interrupt Enable） */
+ __IOM uint32_t NACKIE : 1; /*!< [14..14] I2C检测到NACK位中断使能（I2C Detected NACK
+ Interrupt Enable） */
+ __IOM uint32_t ALDETIE : 1; /*!< [15..15] I2C检测到ALERT信号中断使能（I2C Detected
+ ALERT Signal Interrupt Enable） */
+ __IOM uint32_t MEXTOIE : 1; /*!< [16..16] I2C Tmext超时中断使能（I2C Master Detected Timeout
+ Interrupt Enable） */
+ __IOM uint32_t SEXTOIE : 1; /*!< [17..17] I2C Tsext超时中断使能（I2C Slave Detected Timeout
+ Interrupt Enable） */
+ __IOM uint32_t PECRXIE : 1; /*!< [18..18] I2C收到PEC且校验错误中断使能（I2C Received
+ PEC Byte With Checksum Error Interrupt Enable） */
+ __IOM uint32_t RXGCIE : 1; /*!< [19..19] I2C从机接收广播地址中断使能（Slave RX
+ General Call Interrupt Enable） */
+ __IOM uint32_t MTXAIE : 1; /*!< [20..20] I2C主机发送地址完成中断使能（Master TX
+ Adderss Done Interrupt Enable） */
+ __IOM uint32_t SWTXIE : 1; /*!< [21..21] I2C从机等待数据拉住SCL为低中断使能（I2C
+ Slave Hold SCL Low For Waiting Data Interrupt Enable） */
+ __IOM uint32_t MOHIE : 1; /*!< [22..22] I2C主机挂起拉住SCL为低中断使能（I2C Master
+ Hold SCL Low Interrupt Enable） */
+ __IOM uint32_t BTOIE : 1; /*!< [23..23] I2C 总线超时中断使能（I2C Bus Timeout Interrupt
+ Enable） */
+ uint32_t : 8;
+ } INTREN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTR; /*!< (@ 0x00000034) I2C Interrupt Register */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] I2C RXFIFO满阈值中断（I2C RXFIFO Full Threshold
+ Interrupt） */
+ __IM uint32_t TXEI : 1; /*!< [1..1] I2C TXFIFO空阈值中断（I2C TXFIFO Empty Threshold
+ Interrupt） */
+ __IOM uint32_t RXOFI : 1; /*!< [2..2] I2C RXFIFO上溢中断（I2C RXFIFO Overflow Interrupt） */
+ __IOM uint32_t RXUFI : 1; /*!< [3..3] I2C RXFIFO下溢中断（I2C RXFIFO Underflow Interrupt） */
+ __IOM uint32_t TXOFI : 1; /*!< [4..4] I2C TXFIFO上溢中断（I2C TXFIFO Overflow Interrupt） */
+ __IOM uint32_t TXUFI : 1; /*!< [5..5] I2C 从机TXFIFO下溢中断（I2C Slave TXFIFO Underflow
+ Interrupt） */
+ __IOM uint32_t ARBFI : 1; /*!< [6..6] I2C仲裁失败中断（I2C Arbitration Fail Interrupt） */
+ __IOM uint32_t BUSEI : 1; /*!< [7..7] I2C总线错误中断（I2C Bus Error Interrupt） */
+ __IOM uint32_t MDEI : 1; /*!< [8..8] I2C传输完成中断（I2C Transmission Done Interrupt） */
+ __IOM uint32_t TXADI : 1; /*!< [9..9] I2C从机地址匹配发送中断（I2C Slave TX Address
+ Matching Interrupt） */
+ __IOM uint32_t RXADI : 1; /*!< [10..10] I2C从机地址匹配接收中断（I2C Slave RX Address
+ Matching Interrupt） */
+ __IOM uint32_t STDETI : 1; /*!< [11..11] I2C检测到START位中断（I2C Detected START/RESTART
+ Interrupt） */
+ __IOM uint32_t SPETI : 1; /*!< [12..12] I2C检测到STOP位中断（I2C Detected STOP Interrupt） */
+ __IOM uint32_t RSDETI : 1; /*!< [13..13] I2C检测到RESTART位中断（I2C Detected RESTART
+ Interrupt） */
+ __IOM uint32_t NACKI : 1; /*!< [14..14] I2C检测到NACK位中断（I2C Detected NACK Interrupt） */
+ __IOM uint32_t ALDETI : 1; /*!< [15..15] I2C检测到ALERT信号中断（I2C Detected ALERT
+ Signal Interrupt） */
+ __IOM uint32_t MEXTOI : 1; /*!< [16..16] I2C Tmext超时中断（I2C Master Detected Timeout
+ Interrupt） */
+ __IOM uint32_t SEXTOI : 1; /*!< [17..17] I2C Tsext超时中断（I2C Slave Detected Timeout
+ Interrupt） */
+ __IOM uint32_t PECRXI : 1; /*!< [18..18] I2C收到PEC且校验错误中断（I2C Received PEC
+ Byte with Checksum Error Interrupt） */
+ __IOM uint32_t RXGCI : 1; /*!< [19..19] 从机收到广播中断（Slave RX General Call Interrupt
+ ） */
+ __IOM uint32_t MTXAI : 1; /*!< [20..20] 主机发送地址完成中断（Master TX Adderss
+ Done Interrupt ） */
+ __IOM uint32_t SWTXI : 1; /*!< [21..21] I2C从机等待数据拉住SCL为低中断（I2C Slave
+ Hold SCL Low For Waiting Data Interrupt） */
+ __IM uint32_t MOHI : 1; /*!< [22..22] I2C主机挂起拉住SCL为低中断（I2C Master Hold
+ SCL Low Interrupt） */
+ __IOM uint32_t BTOI : 1; /*!< [23..23] I2C 总线超时中断（I2C Bus Timeout Interrupt） */
+ __IM uint32_t RCNT : 8; /*!< [31..24] I2C剩余数据计数状态（I2C Remain Data Count
+ Status） */
+ } INTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x00000038) I2C Status Register */
+
+ struct {
+ __IM uint32_t FSMBSY : 1; /*!< [0..0] I2C状态机忙碌状态（I2C State Busy Status） */
+ __IM uint32_t BUSBSY : 1; /*!< [1..1] I2C总线忙碌状态（I2C Bus Busy Status） */
+ __IM uint32_t ARBSTA : 2; /*!< [3..2] I2C仲裁失败状态（I2C Arbitration Fail Status） */
+ uint32_t : 12;
+ __IM uint32_t TXFLR : 5; /*!< [20..16] I2C TXFIFO剩余数据量（I2C TXFIFO Remaining Data
+ Number Status） */
+ __IM uint32_t TFE : 1; /*!< [21..21] I2C TXFIFO空标志（I2C TXFIFO Empty Status） */
+ __IM uint32_t TFF : 1; /*!< [22..22] I2C TXFIFO满标志（I2C TXFIFO Full Status） */
+ uint32_t : 1;
+ __IM uint32_t RXFLR : 5; /*!< [28..24] I2C RXFIFO剩余数据量（I2C RXFIFO Remaining Data
+ Number Status） */
+ __IM uint32_t RFE : 1; /*!< [29..29] I2C RXFIFO空标志（I2C RXFIFO Empty Status） */
+ __IM uint32_t RFF : 1; /*!< [30..30] I2C RXFIFO满标志（I2C RXFIFO Full Status） */
+ uint32_t : 1;
+ } STATUS_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t TXDATA; /*!< (@ 0x00000040) I2C TXFIFO Data Registers */
+
+ struct {
+ __IOM uint32_t TXDATA : 8; /*!< [7..0] I2C数据写寄存器（I2C Data For Transmiting Register） */
+ uint32_t : 24;
+ } TXDATA_b;
+ } ;
+
+ union {
+ __IOM uint32_t RXDATA; /*!< (@ 0x00000044) I2C RXFIFO Data Registers */
+
+ struct {
+ __IM uint32_t RXDATA : 8; /*!< [7..0] I2C数据读寄存器（I2C Data For Receiving Register） */
+ uint32_t : 24;
+ } RXDATA_b;
+ } ;
+
+ union {
+ __IOM uint32_t RXADDR; /*!< (@ 0x00000048) I2C RX ADDR Register */
+
+ struct {
+ __IM uint32_t DIR : 1; /*!< [0..0] I2C从机收到的传输方向（I2C Slave Received Direction
+ Status） */
+ __IM uint32_t ADDR : 7; /*!< [7..1] I2C从机收到的地址（I2C Slave Received Address
+ Status） */
+ uint32_t : 24;
+ } RXADDR_b;
+ } ;
+} I2C1_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2C2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C2 (I2C2)
+ */
+
+typedef struct { /*!< (@ 0x40002000) I2C2 Structure */
+
+ union {
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000000) I2C Enable Register */
+
+ struct {
+ __IOM uint32_t I2CEN : 1; /*!< [0..0] I2C使能位（I2C Enable） */
+ __IOM uint32_t UDRCFG : 1; /*!< [1..1] I2C下溢条件时从机发送行为（I2C Behavior At
+ Slave Underrun Condition） */
+ __IOM uint32_t RFRST : 1; /*!< [2..2] I2C RXFIFO复位（RXFIFO Reset Flag） */
+ __IOM uint32_t TFRST : 1; /*!< [3..3] I2C TXFIFO复位（TXFIFO Reset Flag） */
+ __IOM uint32_t RLSCMD : 1; /*!< [4..4] I2C启动传输命令（I2C Release Command） */
+ __IOM uint32_t DMARXEN : 1; /*!< [5..5] I2C接收DMA使能位（I2C RX-DMA Enable） */
+ __IOM uint32_t DMATXEN : 1; /*!< [6..6] I2C发送DMA使能位（I2C TX-DMA Enable） */
+ __IOM uint32_t RFHSEN : 1; /*!< [7..7] I2C接收数据时钟延长模式位（I2C Receive Date
+ SCL Stretching Mode） */
+ __IM uint32_t MSTEN : 1; /*!< [8..8] I2C主机状态位（I2C Master Status） */
+ __IOM uint32_t A10BEN : 1; /*!< [9..9] I2C 10BIT地址使能位（I2C 10BIT Address Enable） */
+ __IOM uint32_t GCEN : 1; /*!< [10..10] I2C广播地址使能位（I2C General Call Address
+ Enable） */
+ __IOM uint32_t OSAEN : 1; /*!< [11..11] I2C可选从机地址使能（I2C Optional Slave Address
+ Register） */
+ __IOM uint32_t SMALEN : 1; /*!< [12..12] SMBUS报警功能使能位（SMBUS Alert Enable） */
+ __IOM uint32_t SMARPEN : 1; /*!< [13..13] SMBUS设备默认地址使能位（SMBUS Device Default
+ Address Enable） */
+ __IOM uint32_t SMHEN : 1; /*!< [14..14] SMBUS HOST地址使能位（SMBUS Host Address Enable） */
+ __IOM uint32_t SMTOEN : 1; /*!< [15..15] SMBUS超时功能使能（SMBUS Timeout Enable） */
+ __IOM uint32_t MSTCH : 1; /*!< [16..16] I2C接收数据时钟延长使能位（I2C Receive
+ Date SCL Stretching Enable） */
+ __IOM uint32_t NSTCH : 1; /*!< [17..17] I2C时钟延长禁止位（I2C SCL Stretching Disable） */
+ __IM uint32_t HDRX : 2; /*!< [19..18] I2C总线状态（I2C Bus Status） */
+ uint32_t : 12;
+ } ENABLE_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000004) I2C Transmission Control Register */
+
+ struct {
+ __IOM uint32_t I2CCNT : 8; /*!< [7..0] I2C传输字节数（I2C Number Of Data Byte Count） */
+ __IOM uint32_t DIRECT : 1; /*!< [8..8] I2C传输方向（I2C Direct Configuration） */
+ __IOM uint32_t STOP : 1; /*!< [9..9] I2C停止传输（I2C Stop Transmission） */
+ __IOM uint32_t START : 1; /*!< [10..10] I2C START生成（I2C START Generation） */
+ __IOM uint32_t NACK : 1; /*!< [11..11] I2C NACK生成（I2C NACK Generation） */
+ __IOM uint32_t PECBYTE : 1; /*!< [12..12] SMBUS数据包错误校验字节（SMBUS Packet Error
+ Checking Byte） */
+ __IOM uint32_t MODE10B : 1; /*!< [13..13] I2C 10BIT传输模式选择（I2C 10BIT Master-Read
+ Mode Select） */
+ __IOM uint32_t AUTOEND : 1; /*!< [14..14] I2C自动结束模式（I2C Automatic End Mode） */
+ uint32_t : 17;
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t BAUD; /*!< (@ 0x00000008) I2C Baud Rate Register */
+
+ struct {
+ __IOM uint32_t SCLLCNT : 10; /*!< [9..0] I2C SCL低电平周期（I2C SCL Low Period） */
+ uint32_t : 6;
+ __IOM uint32_t SCLHCNT : 10; /*!< [25..16] I2C SCL高电平周期（I2C SCL High Period） */
+ uint32_t : 6;
+ } BAUD_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDRDR; /*!< (@ 0x0000000C) I2C Underrun Data Register */
+
+ struct {
+ __IOM uint32_t UDRDR : 8; /*!< [7..0] I2C从模式下溢时数据写寄存器（I2C Data At
+ Slave Underrun Condition） */
+ uint32_t : 24;
+ } UDRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000010) I2C FIFO Control Register */
+
+ struct {
+ __IOM uint32_t TXFTLR : 4; /*!< [3..0] I2C TXFIFO空中断阈值（I2C TXFIFO Empty Threshold） */
+ __IOM uint32_t RXFTLR : 4; /*!< [7..4] I2C RXFIFO满中断阈值（I2C RXFIFO Full Threshold） */
+ uint32_t : 24;
+ } FIFOCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR; /*!< (@ 0x00000014) I2C Target Address Register */
+
+ struct {
+ __IOM uint32_t TAR : 10; /*!< [9..0] I2C主机目标地址（I2C Target Address） */
+ uint32_t : 22;
+ } TAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SAR; /*!< (@ 0x00000018) I2C Slave Address Register */
+
+ struct {
+ __IOM uint32_t SAR : 10; /*!< [9..0] I2C从机地址（I2C Slave Address） */
+ uint32_t : 22;
+ } SAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t OSAR; /*!< (@ 0x0000001C) I2C Optional Slave Address Register */
+
+ struct {
+ __IOM uint32_t OSAR : 10; /*!< [9..0] I2C可选的从机地址（I2C Optional Slave Address
+ Register） */
+ uint32_t : 6;
+ __IOM uint32_t OSAM : 10; /*!< [25..16] I2C可选的从机地址屏蔽（I2C Optional Slave
+ Address Masks Register） */
+ uint32_t : 6;
+ } OSAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PEC; /*!< (@ 0x00000020) I2C RX PEC Register */
+
+ struct {
+ __IM uint32_t RXPEC : 8; /*!< [7..0] SMBUS接收PEC数据寄存器（SMBUS RX PEC Data Register） */
+ __IM uint32_t IDPEC : 8; /*!< [15..8] SMBUS自身PEC数据寄存器（SMBUS ID PEC Data Register） */
+ uint32_t : 16;
+ } PEC_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMING; /*!< (@ 0x00000024) I2C Timing Register */
+
+ struct {
+ __IOM uint32_t HDDAT : 8; /*!< [7..0] I2C数据保持时间（Data Hold Time） */
+ __IOM uint32_t SUDAT : 8; /*!< [15..8] I2C数据建立时间（Data Setup Time） */
+ __IOM uint32_t SLVSUDAT : 8; /*!< [23..16] I2C从机数据建立时间（I2C Data Setup Time） */
+ __IOM uint32_t SPKLEN : 8; /*!< [31..24] I2C尖峰抑制寄存器（I2C Spike Suppression Limit
+ Register） */
+ } TIMING_b;
+ } ;
+
+ union {
+ __IOM uint32_t TIMEOUT; /*!< (@ 0x00000028) I2C Clock Extension Timeout Register */
+
+ struct {
+ __IOM uint32_t MEXTTO : 16; /*!< [15..0] I2C主机时钟扩展超时（I2C Master Clock Extension
+ Timeout Register） */
+ __IOM uint32_t SEXTTO : 16; /*!< [31..16] I2C从机时钟扩展超时（I2C Slave Clock Extension
+ Timeout Register） */
+ } TIMEOUT_b;
+ } ;
+
+ union {
+ __IOM uint32_t BUSTOUT; /*!< (@ 0x0000002C) I2C Bus Timeout Register */
+
+ struct {
+ __IOM uint32_t BTO : 16; /*!< [15..0] I2C总线超时（I2C Bus Timeout） */
+ uint32_t : 15;
+ __IOM uint32_t TOSEL : 1; /*!< [31..31] I2C空闲时钟超时选择（I2C Clock Timeout Select） */
+ } BUSTOUT_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTREN; /*!< (@ 0x00000030) I2C Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RXFIE : 1; /*!< [0..0] I2C RXFIFO满阈值中断使能（I2C RXFIFO Full Threshold
+ Interrupt Enable） */
+ __IOM uint32_t TXEIE : 1; /*!< [1..1] I2C TXFIFO空阈值中断使能（I2C TXFIFO Empty Threshold
+ Interrupt Enable） */
+ __IOM uint32_t RXOFIE : 1; /*!< [2..2] I2C RXFIFO上溢中断使能（I2C RXFIFO Overflow Interrupt
+ Enable） */
+ __IOM uint32_t RXUFIE : 1; /*!< [3..3] I2C RXFIFO下溢中断使能（I2C RXFIFO Underflow Interrupt
+ Enable） */
+ __IOM uint32_t TXOFIE : 1; /*!< [4..4] I2C TXFIFO上溢中断使能（I2C TXFIFO Overflow Interrupt
+ Enable） */
+ __IOM uint32_t TXUFIE : 1; /*!< [5..5] I2C 从机TXFIFO下溢中断使能（I2C Slave TXFIFO
+ Underflow Interrupt Enable） */
+ __IOM uint32_t ARBFIE : 1; /*!< [6..6] I2C仲裁失败中断使能（I2C Arbitration Fail Interrupt
+ Enable） */
+ __IOM uint32_t BUSEIE : 1; /*!< [7..7] I2C总线错误中断使能（I2C Bus Error Interrupt
+ Enable） */
+ __IOM uint32_t MDEIE : 1; /*!< [8..8] I2C传输完成中断使能（I2C Transmission Done Interrupt
+ Enable） */
+ __IOM uint32_t TXADIE : 1; /*!< [9..9] I2C从机地址匹配发送中断使能（I2C Slave Tx
+ Address Matching Interrupt Enable） */
+ __IOM uint32_t RXADIE : 1; /*!< [10..10] I2C从机地址匹配接收中断使能（I2C Slave
+ RX Address Matching Interrupt Enable） */
+ __IOM uint32_t STDETIE : 1; /*!< [11..11] I2C检测到START位中断使能（I2C Detected START/RESTART
+ Interrupt Enable） */
+ __IOM uint32_t SPDETIE : 1; /*!< [12..12] I2C检测到STOP位中断使能（I2C Detected STOP
+ Interrupt Enable） */
+ __IOM uint32_t RSDETIE : 1; /*!< [13..13] I2C检测到RESTART位中断使能（I2C Detected RESTART
+ Interrupt Enable） */
+ __IOM uint32_t NACKIE : 1; /*!< [14..14] I2C检测到NACK位中断使能（I2C Detected NACK
+ Interrupt Enable） */
+ __IOM uint32_t ALDETIE : 1; /*!< [15..15] I2C检测到ALERT信号中断使能（I2C Detected
+ ALERT Signal Interrupt Enable） */
+ __IOM uint32_t MEXTOIE : 1; /*!< [16..16] I2C Tmext超时中断使能（I2C Master Detected Timeout
+ Interrupt Enable） */
+ __IOM uint32_t SEXTOIE : 1; /*!< [17..17] I2C Tsext超时中断使能（I2C Slave Detected Timeout
+ Interrupt Enable） */
+ __IOM uint32_t PECRXIE : 1; /*!< [18..18] I2C收到PEC且校验错误中断使能（I2C Received
+ PEC Byte With Checksum Error Interrupt Enable） */
+ __IOM uint32_t RXGCIE : 1; /*!< [19..19] I2C从机接收广播地址中断使能（Slave RX
+ General Call Interrupt Enable） */
+ __IOM uint32_t MTXAIE : 1; /*!< [20..20] I2C主机发送地址完成中断使能（Master TX
+ Adderss Done Interrupt Enable） */
+ __IOM uint32_t SWTXIE : 1; /*!< [21..21] I2C从机等待数据拉住SCL为低中断使能（I2C
+ Slave Hold SCL Low For Waiting Data Interrupt Enable） */
+ __IOM uint32_t MOHIE : 1; /*!< [22..22] I2C主机挂起拉住SCL为低中断使能（I2C Master
+ Hold SCL Low Interrupt Enable） */
+ __IOM uint32_t BTOIE : 1; /*!< [23..23] I2C 总线超时中断使能（I2C Bus Timeout Interrupt
+ Enable） */
+ uint32_t : 8;
+ } INTREN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTR; /*!< (@ 0x00000034) I2C Interrupt Register */
+
+ struct {
+ __IM uint32_t RXFI : 1; /*!< [0..0] I2C RXFIFO满阈值中断（I2C RXFIFO Full Threshold
+ Interrupt） */
+ __IM uint32_t TXEI : 1; /*!< [1..1] I2C TXFIFO空阈值中断（I2C TXFIFO Empty Threshold
+ Interrupt） */
+ __IOM uint32_t RXOFI : 1; /*!< [2..2] I2C RXFIFO上溢中断（I2C RXFIFO Overflow Interrupt） */
+ __IOM uint32_t RXUFI : 1; /*!< [3..3] I2C RXFIFO下溢中断（I2C RXFIFO Underflow Interrupt） */
+ __IOM uint32_t TXOFI : 1; /*!< [4..4] I2C TXFIFO上溢中断（I2C TXFIFO Overflow Interrupt） */
+ __IOM uint32_t TXUFI : 1; /*!< [5..5] I2C 从机TXFIFO下溢中断（I2C Slave TXFIFO Underflow
+ Interrupt） */
+ __IOM uint32_t ARBFI : 1; /*!< [6..6] I2C仲裁失败中断（I2C Arbitration Fail Interrupt） */
+ __IOM uint32_t BUSEI : 1; /*!< [7..7] I2C总线错误中断（I2C Bus Error Interrupt） */
+ __IOM uint32_t MDEI : 1; /*!< [8..8] I2C传输完成中断（I2C Transmission Done Interrupt） */
+ __IOM uint32_t TXADI : 1; /*!< [9..9] I2C从机地址匹配发送中断（I2C Slave TX Address
+ Matching Interrupt） */
+ __IOM uint32_t RXADI : 1; /*!< [10..10] I2C从机地址匹配接收中断（I2C Slave RX Address
+ Matching Interrupt） */
+ __IOM uint32_t STDETI : 1; /*!< [11..11] I2C检测到START位中断（I2C Detected START/RESTART
+ Interrupt） */
+ __IOM uint32_t SPETI : 1; /*!< [12..12] I2C检测到STOP位中断（I2C Detected STOP Interrupt） */
+ __IOM uint32_t RSDETI : 1; /*!< [13..13] I2C检测到RESTART位中断（I2C Detected RESTART
+ Interrupt） */
+ __IOM uint32_t NACKI : 1; /*!< [14..14] I2C检测到NACK位中断（I2C Detected NACK Interrupt） */
+ __IOM uint32_t ALDETI : 1; /*!< [15..15] I2C检测到ALERT信号中断（I2C Detected ALERT
+ Signal Interrupt） */
+ __IOM uint32_t MEXTOI : 1; /*!< [16..16] I2C Tmext超时中断（I2C Master Detected Timeout
+ Interrupt） */
+ __IOM uint32_t SEXTOI : 1; /*!< [17..17] I2C Tsext超时中断（I2C Slave Detected Timeout
+ Interrupt） */
+ __IOM uint32_t PECRXI : 1; /*!< [18..18] I2C收到PEC且校验错误中断（I2C Received PEC
+ Byte with Checksum Error Interrupt） */
+ __IOM uint32_t RXGCI : 1; /*!< [19..19] 从机收到广播中断（Slave RX General Call Interrupt
+ ） */
+ __IOM uint32_t MTXAI : 1; /*!< [20..20] 主机发送地址完成中断（Master TX Adderss
+ Done Interrupt ） */
+ __IOM uint32_t SWTXI : 1; /*!< [21..21] I2C从机等待数据拉住SCL为低中断（I2C Slave
+ Hold SCL Low For Waiting Data Interrupt） */
+ __IM uint32_t MOHI : 1; /*!< [22..22] I2C主机挂起拉住SCL为低中断（I2C Master Hold
+ SCL Low Interrupt） */
+ __IOM uint32_t BTOI : 1; /*!< [23..23] I2C 总线超时中断（I2C Bus Timeout Interrupt） */
+ __IM uint32_t RCNT : 8; /*!< [31..24] I2C剩余数据计数状态（I2C Remain Data Count
+ Status） */
+ } INTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x00000038) I2C Status Register */
+
+ struct {
+ __IM uint32_t FSMBSY : 1; /*!< [0..0] I2C状态机忙碌状态（I2C State Busy Status） */
+ __IM uint32_t BUSBSY : 1; /*!< [1..1] I2C总线忙碌状态（I2C Bus Busy Status） */
+ __IM uint32_t ARBSTA : 2; /*!< [3..2] I2C仲裁失败状态（I2C Arbitration Fail Status） */
+ uint32_t : 12;
+ __IM uint32_t TXFLR : 5; /*!< [20..16] I2C TXFIFO剩余数据量（I2C TXFIFO Remaining Data
+ Number Status） */
+ __IM uint32_t TFE : 1; /*!< [21..21] I2C TXFIFO空标志（I2C TXFIFO Empty Status） */
+ __IM uint32_t TFF : 1; /*!< [22..22] I2C TXFIFO满标志（I2C TXFIFO Full Status） */
+ uint32_t : 1;
+ __IM uint32_t RXFLR : 5; /*!< [28..24] I2C RXFIFO剩余数据量（I2C RXFIFO Remaining Data
+ Number Status） */
+ __IM uint32_t RFE : 1; /*!< [29..29] I2C RXFIFO空标志（I2C RXFIFO Empty Status） */
+ __IM uint32_t RFF : 1; /*!< [30..30] I2C RXFIFO满标志（I2C RXFIFO Full Status） */
+ uint32_t : 1;
+ } STATUS_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t TXDATA; /*!< (@ 0x00000040) I2C TXFIFO Data Registers */
+
+ struct {
+ __IOM uint32_t TXDATA : 8; /*!< [7..0] I2C数据写寄存器（I2C Data For Transmiting Register） */
+ uint32_t : 24;
+ } TXDATA_b;
+ } ;
+
+ union {
+ __IOM uint32_t RXDATA; /*!< (@ 0x00000044) I2C RXFIFO Data Registers */
+
+ struct {
+ __IM uint32_t RXDATA : 8; /*!< [7..0] I2C数据读寄存器（I2C Data For Receiving Register） */
+ uint32_t : 24;
+ } RXDATA_b;
+ } ;
+
+ union {
+ __IOM uint32_t RXADDR; /*!< (@ 0x00000048) I2C RX ADDR Register */
+
+ struct {
+ __IM uint32_t DIR : 1; /*!< [0..0] I2C从机收到的传输方向（I2C Slave Received Direction
+ Status） */
+ __IM uint32_t ADDR : 7; /*!< [7..1] I2C从机收到的地址（I2C Slave Received Address
+ Status） */
+ uint32_t : 24;
+ } RXADDR_b;
+ } ;
+} I2C2_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV0 (HRPWM_SLV0)
+ */
+
+typedef struct { /*!< (@ 0x4003B100) HRPWM_SLV0 Structure */
+
+ union {
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+
+ struct {
+ __IOM uint32_t CKPSC : 3; /*!< [2..0] PWMx 时钟预分频比 */
+ __IOM uint32_t CONT : 1; /*!< [3..3] PWMx 连续模式 */
+ __IOM uint32_t RETRIG : 1; /*!< [4..4] PWMx 可重触发模式 */
+ __IOM uint32_t HALF : 1; /*!< [5..5] PWMx Half 模式 */
+ __IOM uint32_t INTLVD : 2; /*!< [7..6] PWMx Interleaved 模式 */
+ __IOM uint32_t PSHPLL : 1; /*!< [8..8] PWMx Push-pull 模式 */
+ __IOM uint32_t RSYNCU : 1; /*!< [9..9] PWMx 重同步更新 */
+ __IOM uint32_t SYNCRST : 1; /*!< [10..10] 同步事件复位 PWMx */
+ __IOM uint32_t SYNCSTRT : 1; /*!< [11..11] 同步事件启动 PWMx */
+ uint32_t : 4;
+ __IOM uint32_t DELCMPB : 2; /*!< [17..16] PWMx CMPB Auto-Delayed 模式 */
+ __IOM uint32_t DELCMPD : 2; /*!< [19..18] PWMx CMPD Auto-Delayed 模式 */
+ __IOM uint32_t TRGHLF : 1; /*!< [20..20] PWMx Triggered-half 模式 */
+ __IOM uint32_t GTCMPA : 1; /*!< [21..21] PWMx CMPA Greater Than 模式 */
+ __IOM uint32_t GTCMPC : 1; /*!< [22..22] PWMx CMPC Greater Than 模式 */
+ __IOM uint32_t DACSYNC : 2; /*!< [24..23] DAC Trigger同步 */
+ __IOM uint32_t PREEN : 1; /*!< [25..25] PWMx 预加载使能 */
+ __IOM uint32_t UPDRST : 1; /*!< [26..26] PWMx Reset 更新 */
+ __IOM uint32_t UPDREP : 1; /*!< [27..27] PWMx Repetition 更新 */
+ __IOM uint32_t UPDGAT : 4; /*!< [31..28] 更新门控 */
+ } PWMCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+
+ struct {
+ __IOM uint32_t DCDE : 1; /*!< [0..0] DAC Reset／Step Trigger 使能 */
+ __IOM uint32_t DCDS : 1; /*!< [1..1] DAC Step Trigger 来源 */
+ __IOM uint32_t DCDR : 1; /*!< [2..2] DAC Reset Trigger 来源 */
+ __IOM uint32_t CAPAM : 1; /*!< [3..3] Capture A 模式选择 */
+ __IOM uint32_t UDM : 1; /*!< [4..4] Up-Down 模式选择 */
+ __IOM uint32_t CAPBM : 1; /*!< [5..5] Capture B 模式选择 */
+ __IOM uint32_t ROM : 2; /*!< [7..6] Roll-Over 模式选择 */
+ __IOM uint32_t OUTROM : 2; /*!< [9..8] 输出 Roll-Over 模式选择 */
+ __IOM uint32_t ADROM : 2; /*!< [11..10] ADC Roll-Over 模式选择 */
+ __IOM uint32_t EEVROM : 2; /*!< [13..12] 事件 Roll-Over 模式选择 */
+ __IOM uint32_t FLTROM : 2; /*!< [15..14] 故障 Roll-Over 模式选择 */
+ __IOM uint32_t MUPD : 1; /*!< [16..16] Master PWM 更新 */
+ __IOM uint32_t UPD0 : 1; /*!< [17..17] PWM0 更新 */
+ __IOM uint32_t UPD1 : 1; /*!< [18..18] PWM1 更新 */
+ __IOM uint32_t UPD2 : 1; /*!< [19..19] PWM2 更新 */
+ __IOM uint32_t UPD3 : 1; /*!< [20..20] PWM3 更新 */
+ __IOM uint32_t UPD4 : 1; /*!< [21..21] PWM4 更新 */
+ __IOM uint32_t UPD5 : 1; /*!< [22..22] PWM5 更新 */
+ __IOM uint32_t UPD6 : 1; /*!< [23..23] PWM6 更新 */
+ __IOM uint32_t UPD7 : 1; /*!< [24..24] PWM7 更新 */
+ uint32_t : 6;
+ __IOM uint32_t BDMADIS : 1; /*!< [31..31] PWMx Burst DMA 禁止 */
+ } PWMCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t CMPA : 1; /*!< [0..0] Compare A 中断标志 */
+ __IOM uint32_t CMPB : 1; /*!< [1..1] Compare B 中断标志 */
+ __IOM uint32_t CMPC : 1; /*!< [2..2] Compare C 中断标志 */
+ __IOM uint32_t CMPD : 1; /*!< [3..3] Compare D 中断标志 */
+ __IOM uint32_t PER : 1; /*!< [4..4] Roll-Over 中断标志 */
+ __IOM uint32_t UPD : 1; /*!< [5..5] Update 中断标志 */
+ __IOM uint32_t SETA : 1; /*!< [6..6] Out A Set 中断标志 */
+ __IOM uint32_t CLRA : 1; /*!< [7..7] Out A Clear 中断标志 */
+ __IOM uint32_t SETB : 1; /*!< [8..8] Out B Set 中断标志 */
+ __IOM uint32_t CLRB : 1; /*!< [9..9] Out B Clear 中断标志 */
+ __IOM uint32_t RST : 1; /*!< [10..10] Reset 中断标志 */
+ __IOM uint32_t REP : 1; /*!< [11..11] Repetition 中断标志 */
+ __IOM uint32_t CAPA : 1; /*!< [12..12] Capture A 中断标志 */
+ __IOM uint32_t CAPB : 1; /*!< [13..13] Capture B 中断标志 */
+ __IOM uint32_t DLYPRT : 1; /*!< [14..14] Delayed Protection 中断标志 */
+ uint32_t : 1;
+ __IM uint32_t CPPSTA : 1; /*!< [16..16] PushPull 当前状态 */
+ __IM uint32_t IPPSTA : 1; /*!< [17..17] PushPull 输出状态（延迟空闲/均衡空闲保护发生时） */
+ __IM uint32_t OUTASTA : 1; /*!< [18..18] OUTA 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTBSTA : 1; /*!< [19..19] OUTB 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTA : 1; /*!< [20..20] OUTA 当前输出（输出级之前） */
+ __IM uint32_t OUTB : 1; /*!< [21..21] OUTB 当前输出（输出级之前） */
+ uint32_t : 10;
+ } PWMISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t CMPAIE : 1; /*!< [0..0] Compare A 中断使能 */
+ __IOM uint32_t CMPBIE : 1; /*!< [1..1] Compare B 中断使能 */
+ __IOM uint32_t CMPCIE : 1; /*!< [2..2] Compare C 中断使能 */
+ __IOM uint32_t CMPDIE : 1; /*!< [3..3] Compare D 中断使能 */
+ __IOM uint32_t PERIE : 1; /*!< [4..4] Roll-Over 中断使能 */
+ __IOM uint32_t UPDIE : 1; /*!< [5..5] Update 中断使能 */
+ __IOM uint32_t SETAIE : 1; /*!< [6..6] Out A Set 中断使能 */
+ __IOM uint32_t CLRAIE : 1; /*!< [7..7] Out A Clear 中断使能 */
+ __IOM uint32_t SETBIE : 1; /*!< [8..8] Out B Set 中断使能 */
+ __IOM uint32_t CLRBIE : 1; /*!< [9..9] Out B Clear 中断使能 */
+ __IOM uint32_t RSTIE : 1; /*!< [10..10] Reset 中断使能 */
+ __IOM uint32_t REPIE : 1; /*!< [11..11] Repetition 中断使能 */
+ __IOM uint32_t CAPAIE : 1; /*!< [12..12] Capture A 中断使能 */
+ __IOM uint32_t CAPBIE : 1; /*!< [13..13] Capture B 中断使能 */
+ __IOM uint32_t DLYPRTIE : 1; /*!< [14..14] Delayed Protection 中断使能 */
+ uint32_t : 1;
+ __IOM uint32_t CMPADE : 1; /*!< [16..16] Compare A DMA使能 */
+ __IOM uint32_t CMPBDE : 1; /*!< [17..17] Compare B DMA使能 */
+ __IOM uint32_t CMPCDE : 1; /*!< [18..18] Compare C DMA使能 */
+ __IOM uint32_t CMPDDE : 1; /*!< [19..19] Compare D DMA使能 */
+ __IOM uint32_t PERDE : 1; /*!< [20..20] Roll-Over DMA使能 */
+ __IOM uint32_t UPDDE : 1; /*!< [21..21] Update DMA使能 */
+ __IOM uint32_t SETADE : 1; /*!< [22..22] Out A Set DMA使能 */
+ __IOM uint32_t CLRADE : 1; /*!< [23..23] Out A Clear DMA使能 */
+ __IOM uint32_t SETBDE : 1; /*!< [24..24] Out B Set DMA使能 */
+ __IOM uint32_t CLRBDE : 1; /*!< [25..25] Out B Clear DMA使能 */
+ __IOM uint32_t RSTDE : 1; /*!< [26..26] Reset DMA使能 */
+ __IOM uint32_t REPDE : 1; /*!< [27..27] Repetition DMA使能 */
+ __IOM uint32_t CAPADE : 1; /*!< [28..28] Capture A DMA使能 */
+ __IOM uint32_t CAPBDE : 1; /*!< [29..29] Capture B DMA使能 */
+ __IOM uint32_t DLYPRTDE : 1; /*!< [30..30] Delayed Protection DMA使能 */
+ uint32_t : 1;
+ } PWMDIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] PWMx Counter 数值 */
+ uint32_t : 2;
+ __IOM uint32_t CNTRD : 1; /*!< [18..18] PWMx Counter 读取 */
+ __IOM uint32_t CNTWR : 1; /*!< [19..19] PWMx Counter 写入 */
+ uint32_t : 12;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+
+ struct {
+ __IOM uint32_t PER : 16; /*!< [15..0] PWMx Period 数值 */
+ uint32_t : 16;
+ } PERR_b;
+ } ;
+
+ union {
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] PWMx Repetition Period 数值 */
+ uint32_t : 24;
+ } REPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+
+ struct {
+ __IOM uint32_t CMPA : 16; /*!< [15..0] PWMx Compare A 数值 */
+ uint32_t : 16;
+ } CMPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+
+ struct {
+ __IOM uint32_t CMPB : 16; /*!< [15..0] PWMx Compare B 数值 */
+ uint32_t : 16;
+ } CMPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+
+ struct {
+ __IOM uint32_t CMPC : 16; /*!< [15..0] PWMx Compare C 数值 */
+ uint32_t : 16;
+ } CMPCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+
+ struct {
+ __IOM uint32_t CMPD : 16; /*!< [15..0] PWMx Compare D 数值 */
+ uint32_t : 16;
+ } CMPDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+
+ struct {
+ __IM uint32_t CAPA : 16; /*!< [15..0] 捕获 A 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 A 方向 */
+ uint32_t : 15;
+ } CAPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+
+ struct {
+ __IM uint32_t CAPB : 16; /*!< [15..0] 捕获 B 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 B 方向 */
+ uint32_t : 15;
+ } CAPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+
+ struct {
+ __IOM uint32_t DTR : 12; /*!< [11..0] 上升沿死区时间 */
+ __IOM uint32_t SDTR : 1; /*!< [12..12] 上升沿死区符号 */
+ uint32_t : 3;
+ __IOM uint32_t DTF : 12; /*!< [27..16] 下降沿死区时间 */
+ __IOM uint32_t SDTF : 1; /*!< [28..28] 下降沿死区符号 */
+ uint32_t : 3;
+ } DTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入有效状态 */
+ uint32_t : 9;
+ } SETAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入无效状态 */
+ uint32_t : 9;
+ } CLRAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入有效状态 */
+ uint32_t : 9;
+ } SETBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入无效状态 */
+ uint32_t : 9;
+ } CLRBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+
+ struct {
+ __IOM uint32_t EE0LTCH : 1; /*!< [0..0] Event 0 锁存位 */
+ __IOM uint32_t EE0FLTR : 4; /*!< [4..1] Event 0 滤波位 */
+ __IOM uint32_t EE1LTCH : 1; /*!< [5..5] Event 1 锁存位 */
+ __IOM uint32_t EE1FLTR : 4; /*!< [9..6] Event 1 滤波位 */
+ __IOM uint32_t EE2LTCH : 1; /*!< [10..10] Event 2 锁存位 */
+ __IOM uint32_t EE2FLTR : 4; /*!< [14..11] Event 2 滤波位 */
+ __IOM uint32_t EE3LTCH : 1; /*!< [15..15] Event 3 锁存位 */
+ __IOM uint32_t EE3FLTR : 4; /*!< [19..16] Event 3 滤波位 */
+ __IOM uint32_t EE4LTCH : 1; /*!< [20..20] Event 4 锁存位 */
+ __IOM uint32_t EE4FLTR : 4; /*!< [24..21] Event 4 滤波位 */
+ uint32_t : 7;
+ } EEFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+
+ struct {
+ __IOM uint32_t EE5LTCH : 1; /*!< [0..0] Event 5 锁存位 */
+ __IOM uint32_t EE5FLTR : 4; /*!< [4..1] Event 5 滤波位 */
+ __IOM uint32_t EE6LTCH : 1; /*!< [5..5] Event 6 锁存位 */
+ __IOM uint32_t EE6FLTR : 4; /*!< [9..6] Event 6 滤波位 */
+ __IOM uint32_t EE7LTCH : 1; /*!< [10..10] Event 7 锁存位 */
+ __IOM uint32_t EE7FLTR : 4; /*!< [14..11] Event 7 滤波位 */
+ __IOM uint32_t EE8LTCH : 1; /*!< [15..15] Event 8 锁存位 */
+ __IOM uint32_t EE8FLTR : 4; /*!< [19..16] Event 8 滤波位 */
+ __IOM uint32_t EE9LTCH : 1; /*!< [20..20] Event 9 锁存位 */
+ __IOM uint32_t EE9FLTR : 4; /*!< [24..21] Event 9 滤波位 */
+ uint32_t : 7;
+ } EEFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+
+ struct {
+ __IOM uint32_t EEVACE : 1; /*!< [0..0] Event A 计数使能 */
+ __IOM uint32_t EEVACRES : 1; /*!< [1..1] Event A 计数复位 */
+ __IOM uint32_t EEVARSTM : 1; /*!< [2..2] Event A计数复位模式 */
+ uint32_t : 1;
+ __IOM uint32_t EEVASEL : 4; /*!< [7..4] Event A 来源选择 */
+ __IOM uint32_t EEVACNT : 6; /*!< [13..8] Event A 计数阈值 */
+ uint32_t : 18;
+ } EEFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+
+ struct {
+ __IOM uint32_t SLV5CMPA : 1; /*!< [0..0] PWM5 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [1..1] Master PWM Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [2..2] Master PWM Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [3..3] Master PWM Compare C事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [4..4] Master PWM Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTPER : 1; /*!< [5..5] Master PWM Period事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [6..6] PWMx Event 0事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [7..7] PWMx Event 1事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [8..8] PWMx Event 2事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [9..9] PWMx Event 3事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [10..10] PWMx Event 4事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [11..11] PWMx Event 5事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [12..12] PWMx Event 6事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [13..13] PWMx Event 7事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [14..14] PWMx Event 8事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [15..15] PWMx Event 9事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVUPD : 1; /*!< [16..16] PWMx Update事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPB : 1; /*!< [17..17] PWMx Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPD : 1; /*!< [18..18] PWMx Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [19..19] PWM1 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [20..20] PWM1 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPD : 1; /*!< [21..21] PWM1 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPD : 1; /*!< [24..24] PWM2 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [25..25] PWM3 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [26..26] PWM3 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPD : 1; /*!< [27..27] PWM3 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [28..28] PWM4 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [29..29] PWM4 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPD : 1; /*!< [30..30] PWM4 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B事件使 PWMx 计数器复位 */
+ } RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6CMPA : 1; /*!< [0..0] PWM6 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [1..1] PWM6 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPD : 1; /*!< [2..2] PWM6 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [3..3] PWM7 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [4..4] PWM7 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPD : 1; /*!< [5..5] PWM7 Compare D事件使 PWMx 计数器复位 */
+ uint32_t : 26;
+ } RSTER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+
+ struct {
+ __IOM uint32_t CARFRQ : 4; /*!< [3..0] PWMx 载波频率值 */
+ uint32_t : 2;
+ __IOM uint32_t CARDTY : 3; /*!< [8..6] PWMx 斩波占空比值 */
+ uint32_t : 3;
+ __IOM uint32_t STRPW : 4; /*!< [15..12] PWMx 启动脉冲宽度 */
+ uint32_t : 16;
+ } CHPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture A 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [12..12] PWM1 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [13..13] PWM1 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [14..14] PWM1 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [15..15] PWM1 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [16..16] PWM2 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [17..17] PWM2 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [18..18] PWM2 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [19..19] PWM2 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [20..20] PWM3 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [21..21] PWM3 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [22..22] PWM3 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [23..23] PWM3 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [24..24] PWM4 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [25..25] PWM4 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [26..26] PWM4 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [27..27] PWM4 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5SETA : 1; /*!< [28..28] PWM5 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [29..29] PWM5 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [30..30] PWM5 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B 事件触发 Capture A 事件 */
+ } CAPACR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture A 事件 */
+ uint32_t : 24;
+ } CAPACER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture B 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [12..12] PWM1 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [13..13] PWM1 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [14..14] PWM1 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [15..15] PWM1 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [16..16] PWM2 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [17..17] PWM2 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [18..18] PWM2 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [19..19] PWM2 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [20..20] PWM3 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [21..21] PWM3 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [22..22] PWM3 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [23..23] PWM3 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [24..24] PWM4 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [25..25] PWM4 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [26..26] PWM4 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [27..27] PWM4 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5SETA : 1; /*!< [28..28] PWM5 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [29..29] PWM5 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [30..30] PWM5 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B 事件触发 Capture B 事件 */
+ } CAPBCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture B 事件 */
+ uint32_t : 24;
+ } CAPBCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+
+ struct {
+ __IOM uint32_t POLA : 1; /*!< [0..0] 输出 A 极性 */
+ __IOM uint32_t FAULTA : 2; /*!< [2..1] 输出 A 故障电平 */
+ __IOM uint32_t IDLESA : 1; /*!< [3..3] 输出 A 空闲状态 */
+ __IOM uint32_t CHPA : 1; /*!< [4..4] 输出 A 斩波使能 */
+ __IOM uint32_t IDLEMA : 1; /*!< [5..5] 输出 A 空闲模式 */
+ __IOM uint32_t DIDLA : 1; /*!< [6..6] 输出 A 空闲模式死区使能 */
+ uint32_t : 9;
+ __IOM uint32_t POLB : 1; /*!< [16..16] 输出 B 极性 */
+ __IOM uint32_t FAULTB : 2; /*!< [18..17] 输出 B 故障状态 */
+ __IOM uint32_t IDLESB : 1; /*!< [19..19] 输出 B 空闲状态 */
+ __IOM uint32_t CHPB : 1; /*!< [20..20] 输出 B 斩波使能 */
+ __IOM uint32_t IDLEMB : 1; /*!< [21..21] 输出 B 空闲模式 */
+ __IOM uint32_t DIDLB : 1; /*!< [22..22] 输出 B 空闲模式死区使能 */
+ uint32_t : 2;
+ __IOM uint32_t BIAR : 1; /*!< [25..25] 均衡空闲自动恢复 */
+ uint32_t : 1;
+ __IOM uint32_t DLYPRT : 3; /*!< [29..27] 延迟保护机制 */
+ __IOM uint32_t DLYPRTEN : 1; /*!< [30..30] 延迟保护使能 */
+ __IOM uint32_t DTEN : 1; /*!< [31..31] 死区使能 */
+ } OUTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+
+ struct {
+ __IOM uint32_t FLT0EN : 1; /*!< [0..0] Fault 0 使能 */
+ __IOM uint32_t FLT1EN : 1; /*!< [1..1] Fault 1 使能 */
+ __IOM uint32_t FLT2EN : 1; /*!< [2..2] Fault 2 使能 */
+ __IOM uint32_t FLT3EN : 1; /*!< [3..3] Fault 3 使能 */
+ __IOM uint32_t FLT4EN : 1; /*!< [4..4] Fault 4 使能 */
+ __IOM uint32_t FLT5EN : 1; /*!< [5..5] Fault 5 使能 */
+ __IOM uint32_t FLT6EN : 1; /*!< [6..6] Fault 6 使能 */
+ __IOM uint32_t FLT7EN : 1; /*!< [7..7] Fault 7 使能 */
+ uint32_t : 24;
+ } FLTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+
+ struct {
+ __IOM uint32_t PWMCR0 : 1; /*!< [0..0] PWMCR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMCR1 : 1; /*!< [1..1] PWMCR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMISR : 1; /*!< [2..2] PWMISR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMDIER : 1; /*!< [3..3] PWMDIER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CNTR : 1; /*!< [4..4] CNTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PERR : 1; /*!< [5..5] PERR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t REPR : 1; /*!< [6..6] REPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPAR : 1; /*!< [7..7] CMPAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPBR : 1; /*!< [8..8] CMPBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPCR : 1; /*!< [9..9] CMPCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPDR : 1; /*!< [10..10] CMPDR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPAR : 1; /*!< [11..11] CAPAR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t CAPBR : 1; /*!< [12..12] CAPBR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t DTR : 1; /*!< [13..13] DTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETAR : 1; /*!< [14..14] SETAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRAR : 1; /*!< [15..15] CLRAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETBR : 1; /*!< [16..16] SETBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRBR : 1; /*!< [17..17] CLRBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR0 : 1; /*!< [18..18] EEFR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR1 : 1; /*!< [19..19] EEFR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR2 : 1; /*!< [20..20] EEFR2 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTR : 1; /*!< [21..21] RSTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTER : 1; /*!< [22..22] RSTER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CHPR : 1; /*!< [23..23] CHPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACR : 1; /*!< [24..24] CAPACR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACER : 1; /*!< [25..25] CAPACER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCR : 1; /*!< [26..26] CAPBCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCER : 1; /*!< [27..27] CAPBCER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t OUTR : 1; /*!< [28..28] OUTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t FLTR : 1; /*!< [29..29] FLTR 寄存器支持 System DMA 写入DMADR并更新 */
+ uint32_t : 2;
+ } DMAUR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+
+ struct {
+ __IOM uint32_t DMADR : 32; /*!< [31..0] System DMA 数据地址 */
+ } DMADR_b;
+ } ;
+} HRPWM_SLV0_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV1 (HRPWM_SLV1)
+ */
+
+typedef struct { /*!< (@ 0x4003B200) HRPWM_SLV1 Structure */
+
+ union {
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+
+ struct {
+ __IOM uint32_t CKPSC : 3; /*!< [2..0] PWMx 时钟预分频比 */
+ __IOM uint32_t CONT : 1; /*!< [3..3] PWMx 连续模式 */
+ __IOM uint32_t RETRIG : 1; /*!< [4..4] PWMx 可重触发模式 */
+ __IOM uint32_t HALF : 1; /*!< [5..5] PWMx Half 模式 */
+ __IOM uint32_t INTLVD : 2; /*!< [7..6] PWMx Interleaved 模式 */
+ __IOM uint32_t PSHPLL : 1; /*!< [8..8] PWMx Push-pull 模式 */
+ __IOM uint32_t RSYNCU : 1; /*!< [9..9] PWMx 重同步更新 */
+ __IOM uint32_t SYNCRST : 1; /*!< [10..10] 同步事件复位 PWMx */
+ __IOM uint32_t SYNCSTRT : 1; /*!< [11..11] 同步事件启动 PWMx */
+ uint32_t : 4;
+ __IOM uint32_t DELCMPB : 2; /*!< [17..16] PWMx CMPB Auto-Delayed 模式 */
+ __IOM uint32_t DELCMPD : 2; /*!< [19..18] PWMx CMPD Auto-Delayed 模式 */
+ __IOM uint32_t TRGHLF : 1; /*!< [20..20] PWMx Triggered-half 模式 */
+ __IOM uint32_t GTCMPA : 1; /*!< [21..21] PWMx CMPA Greater Than 模式 */
+ __IOM uint32_t GTCMPC : 1; /*!< [22..22] PWMx CMPC Greater Than 模式 */
+ __IOM uint32_t DACSYNC : 2; /*!< [24..23] DAC Trigger同步 */
+ __IOM uint32_t PREEN : 1; /*!< [25..25] PWMx 预加载使能 */
+ __IOM uint32_t UPDRST : 1; /*!< [26..26] PWMx Reset 更新 */
+ __IOM uint32_t UPDREP : 1; /*!< [27..27] PWMx Repetition 更新 */
+ __IOM uint32_t UPDGAT : 4; /*!< [31..28] 更新门控 */
+ } PWMCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+
+ struct {
+ __IOM uint32_t DCDE : 1; /*!< [0..0] DAC Reset／Step Trigger 使能 */
+ __IOM uint32_t DCDS : 1; /*!< [1..1] DAC Step Trigger 来源 */
+ __IOM uint32_t DCDR : 1; /*!< [2..2] DAC Reset Trigger 来源 */
+ __IOM uint32_t CAPAM : 1; /*!< [3..3] Capture A 模式选择 */
+ __IOM uint32_t UDM : 1; /*!< [4..4] Up-Down 模式选择 */
+ __IOM uint32_t CAPBM : 1; /*!< [5..5] Capture B 模式选择 */
+ __IOM uint32_t ROM : 2; /*!< [7..6] Roll-Over 模式选择 */
+ __IOM uint32_t OUTROM : 2; /*!< [9..8] 输出 Roll-Over 模式选择 */
+ __IOM uint32_t ADROM : 2; /*!< [11..10] ADC Roll-Over 模式选择 */
+ __IOM uint32_t EEVROM : 2; /*!< [13..12] 事件 Roll-Over 模式选择 */
+ __IOM uint32_t FLTROM : 2; /*!< [15..14] 故障 Roll-Over 模式选择 */
+ __IOM uint32_t MUPD : 1; /*!< [16..16] Master PWM 更新 */
+ __IOM uint32_t UPD0 : 1; /*!< [17..17] PWM0 更新 */
+ __IOM uint32_t UPD1 : 1; /*!< [18..18] PWM1 更新 */
+ __IOM uint32_t UPD2 : 1; /*!< [19..19] PWM2 更新 */
+ __IOM uint32_t UPD3 : 1; /*!< [20..20] PWM3 更新 */
+ __IOM uint32_t UPD4 : 1; /*!< [21..21] PWM4 更新 */
+ __IOM uint32_t UPD5 : 1; /*!< [22..22] PWM5 更新 */
+ __IOM uint32_t UPD6 : 1; /*!< [23..23] PWM6 更新 */
+ __IOM uint32_t UPD7 : 1; /*!< [24..24] PWM7 更新 */
+ uint32_t : 6;
+ __IOM uint32_t BDMADIS : 1; /*!< [31..31] PWMx Burst DMA 禁止 */
+ } PWMCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t CMPA : 1; /*!< [0..0] Compare A 中断标志 */
+ __IOM uint32_t CMPB : 1; /*!< [1..1] Compare B 中断标志 */
+ __IOM uint32_t CMPC : 1; /*!< [2..2] Compare C 中断标志 */
+ __IOM uint32_t CMPD : 1; /*!< [3..3] Compare D 中断标志 */
+ __IOM uint32_t PER : 1; /*!< [4..4] Roll-Over 中断标志 */
+ __IOM uint32_t UPD : 1; /*!< [5..5] Update 中断标志 */
+ __IOM uint32_t SETA : 1; /*!< [6..6] Out A Set 中断标志 */
+ __IOM uint32_t CLRA : 1; /*!< [7..7] Out A Clear 中断标志 */
+ __IOM uint32_t SETB : 1; /*!< [8..8] Out B Set 中断标志 */
+ __IOM uint32_t CLRB : 1; /*!< [9..9] Out B Clear 中断标志 */
+ __IOM uint32_t RST : 1; /*!< [10..10] Reset 中断标志 */
+ __IOM uint32_t REP : 1; /*!< [11..11] Repetition 中断标志 */
+ __IOM uint32_t CAPA : 1; /*!< [12..12] Capture A 中断标志 */
+ __IOM uint32_t CAPB : 1; /*!< [13..13] Capture B 中断标志 */
+ __IOM uint32_t DLYPRT : 1; /*!< [14..14] Delayed Protection 中断标志 */
+ uint32_t : 1;
+ __IM uint32_t CPPSTA : 1; /*!< [16..16] PushPull 当前状态 */
+ __IM uint32_t IPPSTA : 1; /*!< [17..17] PushPull 输出状态（延迟空闲/均衡空闲保护发生时） */
+ __IM uint32_t OUTASTA : 1; /*!< [18..18] OUTA 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTBSTA : 1; /*!< [19..19] OUTB 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTA : 1; /*!< [20..20] OUTA 当前输出（输出级之前） */
+ __IM uint32_t OUTB : 1; /*!< [21..21] OUTB 当前输出（输出级之前） */
+ uint32_t : 10;
+ } PWMISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t CMPAIE : 1; /*!< [0..0] Compare A 中断使能 */
+ __IOM uint32_t CMPBIE : 1; /*!< [1..1] Compare B 中断使能 */
+ __IOM uint32_t CMPCIE : 1; /*!< [2..2] Compare C 中断使能 */
+ __IOM uint32_t CMPDIE : 1; /*!< [3..3] Compare D 中断使能 */
+ __IOM uint32_t PERIE : 1; /*!< [4..4] Roll-Over 中断使能 */
+ __IOM uint32_t UPDIE : 1; /*!< [5..5] Update 中断使能 */
+ __IOM uint32_t SETAIE : 1; /*!< [6..6] Out A Set 中断使能 */
+ __IOM uint32_t CLRAIE : 1; /*!< [7..7] Out A Clear 中断使能 */
+ __IOM uint32_t SETBIE : 1; /*!< [8..8] Out B Set 中断使能 */
+ __IOM uint32_t CLRBIE : 1; /*!< [9..9] Out B Clear 中断使能 */
+ __IOM uint32_t RSTIE : 1; /*!< [10..10] Reset 中断使能 */
+ __IOM uint32_t REPIE : 1; /*!< [11..11] Repetition 中断使能 */
+ __IOM uint32_t CAPAIE : 1; /*!< [12..12] Capture A 中断使能 */
+ __IOM uint32_t CAPBIE : 1; /*!< [13..13] Capture B 中断使能 */
+ __IOM uint32_t DLYPRTIE : 1; /*!< [14..14] Delayed Protection 中断使能 */
+ uint32_t : 1;
+ __IOM uint32_t CMPADE : 1; /*!< [16..16] Compare A DMA使能 */
+ __IOM uint32_t CMPBDE : 1; /*!< [17..17] Compare B DMA使能 */
+ __IOM uint32_t CMPCDE : 1; /*!< [18..18] Compare C DMA使能 */
+ __IOM uint32_t CMPDDE : 1; /*!< [19..19] Compare D DMA使能 */
+ __IOM uint32_t PERDE : 1; /*!< [20..20] Roll-Over DMA使能 */
+ __IOM uint32_t UPDDE : 1; /*!< [21..21] Update DMA使能 */
+ __IOM uint32_t SETADE : 1; /*!< [22..22] Out A Set DMA使能 */
+ __IOM uint32_t CLRADE : 1; /*!< [23..23] Out A Clear DMA使能 */
+ __IOM uint32_t SETBDE : 1; /*!< [24..24] Out B Set DMA使能 */
+ __IOM uint32_t CLRBDE : 1; /*!< [25..25] Out B Clear DMA使能 */
+ __IOM uint32_t RSTDE : 1; /*!< [26..26] Reset DMA使能 */
+ __IOM uint32_t REPDE : 1; /*!< [27..27] Repetition DMA使能 */
+ __IOM uint32_t CAPADE : 1; /*!< [28..28] Capture A DMA使能 */
+ __IOM uint32_t CAPBDE : 1; /*!< [29..29] Capture B DMA使能 */
+ __IOM uint32_t DLYPRTDE : 1; /*!< [30..30] Delayed Protection DMA使能 */
+ uint32_t : 1;
+ } PWMDIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] PWMx Counter 数值 */
+ uint32_t : 2;
+ __IOM uint32_t CNTRD : 1; /*!< [18..18] PWMx Counter 读取 */
+ __IOM uint32_t CNTWR : 1; /*!< [19..19] PWMx Counter 写入 */
+ uint32_t : 12;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+
+ struct {
+ __IOM uint32_t PER : 16; /*!< [15..0] PWMx Period 数值 */
+ uint32_t : 16;
+ } PERR_b;
+ } ;
+
+ union {
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] PWMx Repetition Period 数值 */
+ uint32_t : 24;
+ } REPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+
+ struct {
+ __IOM uint32_t CMPA : 16; /*!< [15..0] PWMx Compare A 数值 */
+ uint32_t : 16;
+ } CMPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+
+ struct {
+ __IOM uint32_t CMPB : 16; /*!< [15..0] PWMx Compare B 数值 */
+ uint32_t : 16;
+ } CMPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+
+ struct {
+ __IOM uint32_t CMPC : 16; /*!< [15..0] PWMx Compare C 数值 */
+ uint32_t : 16;
+ } CMPCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+
+ struct {
+ __IOM uint32_t CMPD : 16; /*!< [15..0] PWMx Compare D 数值 */
+ uint32_t : 16;
+ } CMPDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+
+ struct {
+ __IM uint32_t CAPA : 16; /*!< [15..0] 捕获 A 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 A 方向 */
+ uint32_t : 15;
+ } CAPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+
+ struct {
+ __IM uint32_t CAPB : 16; /*!< [15..0] 捕获 B 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 B 方向 */
+ uint32_t : 15;
+ } CAPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+
+ struct {
+ __IOM uint32_t DTR : 12; /*!< [11..0] 上升沿死区时间 */
+ __IOM uint32_t SDTR : 1; /*!< [12..12] 上升沿死区符号 */
+ uint32_t : 3;
+ __IOM uint32_t DTF : 12; /*!< [27..16] 下降沿死区时间 */
+ __IOM uint32_t SDTF : 1; /*!< [28..28] 下降沿死区符号 */
+ uint32_t : 3;
+ } DTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入有效状态 */
+ uint32_t : 9;
+ } SETAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入无效状态 */
+ uint32_t : 9;
+ } CLRAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入有效状态 */
+ uint32_t : 9;
+ } SETBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入无效状态 */
+ uint32_t : 9;
+ } CLRBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+
+ struct {
+ __IOM uint32_t EE0LTCH : 1; /*!< [0..0] Event 0 锁存位 */
+ __IOM uint32_t EE0FLTR : 4; /*!< [4..1] Event 0 滤波位 */
+ __IOM uint32_t EE1LTCH : 1; /*!< [5..5] Event 1 锁存位 */
+ __IOM uint32_t EE1FLTR : 4; /*!< [9..6] Event 1 滤波位 */
+ __IOM uint32_t EE2LTCH : 1; /*!< [10..10] Event 2 锁存位 */
+ __IOM uint32_t EE2FLTR : 4; /*!< [14..11] Event 2 滤波位 */
+ __IOM uint32_t EE3LTCH : 1; /*!< [15..15] Event 3 锁存位 */
+ __IOM uint32_t EE3FLTR : 4; /*!< [19..16] Event 3 滤波位 */
+ __IOM uint32_t EE4LTCH : 1; /*!< [20..20] Event 4 锁存位 */
+ __IOM uint32_t EE4FLTR : 4; /*!< [24..21] Event 4 滤波位 */
+ uint32_t : 7;
+ } EEFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+
+ struct {
+ __IOM uint32_t EE5LTCH : 1; /*!< [0..0] Event 5 锁存位 */
+ __IOM uint32_t EE5FLTR : 4; /*!< [4..1] Event 5 滤波位 */
+ __IOM uint32_t EE6LTCH : 1; /*!< [5..5] Event 6 锁存位 */
+ __IOM uint32_t EE6FLTR : 4; /*!< [9..6] Event 6 滤波位 */
+ __IOM uint32_t EE7LTCH : 1; /*!< [10..10] Event 7 锁存位 */
+ __IOM uint32_t EE7FLTR : 4; /*!< [14..11] Event 7 滤波位 */
+ __IOM uint32_t EE8LTCH : 1; /*!< [15..15] Event 8 锁存位 */
+ __IOM uint32_t EE8FLTR : 4; /*!< [19..16] Event 8 滤波位 */
+ __IOM uint32_t EE9LTCH : 1; /*!< [20..20] Event 9 锁存位 */
+ __IOM uint32_t EE9FLTR : 4; /*!< [24..21] Event 9 滤波位 */
+ uint32_t : 7;
+ } EEFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+
+ struct {
+ __IOM uint32_t EEVACE : 1; /*!< [0..0] Event A 计数使能 */
+ __IOM uint32_t EEVACRES : 1; /*!< [1..1] Event A 计数复位 */
+ __IOM uint32_t EEVARSTM : 1; /*!< [2..2] Event A计数复位模式 */
+ uint32_t : 1;
+ __IOM uint32_t EEVASEL : 4; /*!< [7..4] Event A 来源选择 */
+ __IOM uint32_t EEVACNT : 6; /*!< [13..8] Event A 计数阈值 */
+ uint32_t : 18;
+ } EEFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+
+ struct {
+ __IOM uint32_t SLV5CMPA : 1; /*!< [0..0] PWM5 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [1..1] Master PWM Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [2..2] Master PWM Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [3..3] Master PWM Compare C事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [4..4] Master PWM Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTPER : 1; /*!< [5..5] Master PWM Period事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [6..6] PWMx Event 0事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [7..7] PWMx Event 1事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [8..8] PWMx Event 2事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [9..9] PWMx Event 3事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [10..10] PWMx Event 4事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [11..11] PWMx Event 5事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [12..12] PWMx Event 6事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [13..13] PWMx Event 7事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [14..14] PWMx Event 8事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [15..15] PWMx Event 9事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVUPD : 1; /*!< [16..16] PWMx Update事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPB : 1; /*!< [17..17] PWMx Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPD : 1; /*!< [18..18] PWMx Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [19..19] PWM0 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [20..20] PWM0 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPD : 1; /*!< [21..21] PWM0 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPD : 1; /*!< [24..24] PWM2 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [25..25] PWM3 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [26..26] PWM3 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPD : 1; /*!< [27..27] PWM3 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [28..28] PWM4 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [29..29] PWM4 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPD : 1; /*!< [30..30] PWM4 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B事件使 PWMx 计数器复位 */
+ } RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6CMPA : 1; /*!< [0..0] PWM6 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [1..1] PWM6 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPD : 1; /*!< [2..2] PWM6 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [3..3] PWM7 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [4..4] PWM7 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPD : 1; /*!< [5..5] PWM7 Compare D事件使 PWMx 计数器复位 */
+ uint32_t : 26;
+ } RSTER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+
+ struct {
+ __IOM uint32_t CARFRQ : 4; /*!< [3..0] PWMx 载波频率值 */
+ uint32_t : 2;
+ __IOM uint32_t CARDTY : 3; /*!< [8..6] PWMx 斩波占空比值 */
+ uint32_t : 3;
+ __IOM uint32_t STRPW : 4; /*!< [15..12] PWMx 启动脉冲宽度 */
+ uint32_t : 16;
+ } CHPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture A 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [16..16] PWM2 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [17..17] PWM2 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [18..18] PWM2 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [19..19] PWM2 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [20..20] PWM3 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [21..21] PWM3 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [22..22] PWM3 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [23..23] PWM3 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [24..24] PWM4 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [25..25] PWM4 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [26..26] PWM4 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [27..27] PWM4 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5SETA : 1; /*!< [28..28] PWM5 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [29..29] PWM5 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [30..30] PWM5 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B 事件触发 Capture A 事件 */
+ } CAPACR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture A 事件 */
+ uint32_t : 24;
+ } CAPACER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture B 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [16..16] PWM2 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [17..17] PWM2 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [18..18] PWM2 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [19..19] PWM2 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [20..20] PWM3 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [21..21] PWM3 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [22..22] PWM3 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [23..23] PWM3 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [24..24] PWM4 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [25..25] PWM4 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [26..26] PWM4 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [27..27] PWM4 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5SETA : 1; /*!< [28..28] PWM5 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [29..29] PWM5 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [30..30] PWM5 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B 事件触发 Capture B 事件 */
+ } CAPBCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] Reserved */
+ uint32_t : 24;
+ } CAPBCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+
+ struct {
+ __IOM uint32_t POLA : 1; /*!< [0..0] 输出 A 极性 */
+ __IOM uint32_t FAULTA : 2; /*!< [2..1] 输出 A 故障电平 */
+ __IOM uint32_t IDLESA : 1; /*!< [3..3] 输出 A 空闲状态 */
+ __IOM uint32_t CHPA : 1; /*!< [4..4] 输出 A 斩波使能 */
+ __IOM uint32_t IDLEMA : 1; /*!< [5..5] 输出 A 空闲模式 */
+ __IOM uint32_t DIDLA : 1; /*!< [6..6] 输出 A 空闲模式死区使能 */
+ uint32_t : 9;
+ __IOM uint32_t POLB : 1; /*!< [16..16] 输出 B 极性 */
+ __IOM uint32_t FAULTB : 2; /*!< [18..17] 输出 B 故障状态 */
+ __IOM uint32_t IDLESB : 1; /*!< [19..19] 输出 B 空闲状态 */
+ __IOM uint32_t CHPB : 1; /*!< [20..20] 输出 B 斩波使能 */
+ __IOM uint32_t IDLEMB : 1; /*!< [21..21] 输出 B 空闲模式 */
+ __IOM uint32_t DIDLB : 1; /*!< [22..22] 输出 B 空闲模式死区使能 */
+ uint32_t : 2;
+ __IOM uint32_t BIAR : 1; /*!< [25..25] 均衡空闲自动恢复 */
+ uint32_t : 1;
+ __IOM uint32_t DLYPRT : 3; /*!< [29..27] 延迟保护机制 */
+ __IOM uint32_t DLYPRTEN : 1; /*!< [30..30] 延迟保护使能 */
+ __IOM uint32_t DTEN : 1; /*!< [31..31] 死区使能 */
+ } OUTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+
+ struct {
+ __IOM uint32_t FLT0EN : 1; /*!< [0..0] Fault 0 使能 */
+ __IOM uint32_t FLT1EN : 1; /*!< [1..1] Fault 1 使能 */
+ __IOM uint32_t FLT2EN : 1; /*!< [2..2] Fault 2 使能 */
+ __IOM uint32_t FLT3EN : 1; /*!< [3..3] Fault 3 使能 */
+ __IOM uint32_t FLT4EN : 1; /*!< [4..4] Fault 4 使能 */
+ __IOM uint32_t FLT5EN : 1; /*!< [5..5] Fault 5 使能 */
+ __IOM uint32_t FLT6EN : 1; /*!< [6..6] Fault 6 使能 */
+ __IOM uint32_t FLT7EN : 1; /*!< [7..7] Fault 7 使能 */
+ uint32_t : 24;
+ } FLTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+
+ struct {
+ __IOM uint32_t PWMCR0 : 1; /*!< [0..0] PWMCR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMCR1 : 1; /*!< [1..1] PWMCR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMISR : 1; /*!< [2..2] PWMISR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMDIER : 1; /*!< [3..3] PWMDIER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CNTR : 1; /*!< [4..4] CNTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PERR : 1; /*!< [5..5] PERR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t REPR : 1; /*!< [6..6] REPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPAR : 1; /*!< [7..7] CMPAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPBR : 1; /*!< [8..8] CMPBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPCR : 1; /*!< [9..9] CMPCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPDR : 1; /*!< [10..10] CMPDR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPAR : 1; /*!< [11..11] CAPAR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t CAPBR : 1; /*!< [12..12] CAPBR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t DTR : 1; /*!< [13..13] DTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETAR : 1; /*!< [14..14] SETAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRAR : 1; /*!< [15..15] CLRAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETBR : 1; /*!< [16..16] SETBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRBR : 1; /*!< [17..17] CLRBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR0 : 1; /*!< [18..18] EEFR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR1 : 1; /*!< [19..19] EEFR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR2 : 1; /*!< [20..20] EEFR2 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTR : 1; /*!< [21..21] RSTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTER : 1; /*!< [22..22] RSTER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CHPR : 1; /*!< [23..23] CHPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACR : 1; /*!< [24..24] CAPACR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACER : 1; /*!< [25..25] CAPACER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCR : 1; /*!< [26..26] CAPBCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCER : 1; /*!< [27..27] CAPBCER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t OUTR : 1; /*!< [28..28] OUTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t FLTR : 1; /*!< [29..29] FLTR 寄存器支持 System DMA 写入DMADR并更新 */
+ uint32_t : 2;
+ } DMAUR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+
+ struct {
+ __IOM uint32_t DMADR : 32; /*!< [31..0] System DMA 数据地址 */
+ } DMADR_b;
+ } ;
+} HRPWM_SLV1_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV2 (HRPWM_SLV2)
+ */
+
+typedef struct { /*!< (@ 0x4003B300) HRPWM_SLV2 Structure */
+
+ union {
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+
+ struct {
+ __IOM uint32_t CKPSC : 3; /*!< [2..0] PWMx 时钟预分频比 */
+ __IOM uint32_t CONT : 1; /*!< [3..3] PWMx 连续模式 */
+ __IOM uint32_t RETRIG : 1; /*!< [4..4] PWMx 可重触发模式 */
+ __IOM uint32_t HALF : 1; /*!< [5..5] PWMx Half 模式 */
+ __IOM uint32_t INTLVD : 2; /*!< [7..6] PWMx Interleaved 模式 */
+ __IOM uint32_t PSHPLL : 1; /*!< [8..8] PWMx Push-pull 模式 */
+ __IOM uint32_t RSYNCU : 1; /*!< [9..9] PWMx 重同步更新 */
+ __IOM uint32_t SYNCRST : 1; /*!< [10..10] 同步事件复位 PWMx */
+ __IOM uint32_t SYNCSTRT : 1; /*!< [11..11] 同步事件启动 PWMx */
+ uint32_t : 4;
+ __IOM uint32_t DELCMPB : 2; /*!< [17..16] PWMx CMPB Auto-Delayed 模式 */
+ __IOM uint32_t DELCMPD : 2; /*!< [19..18] PWMx CMPD Auto-Delayed 模式 */
+ __IOM uint32_t TRGHLF : 1; /*!< [20..20] PWMx Triggered-half 模式 */
+ __IOM uint32_t GTCMPA : 1; /*!< [21..21] PWMx CMPA Greater Than 模式 */
+ __IOM uint32_t GTCMPC : 1; /*!< [22..22] PWMx CMPC Greater Than 模式 */
+ __IOM uint32_t DACSYNC : 2; /*!< [24..23] DAC Trigger同步 */
+ __IOM uint32_t PREEN : 1; /*!< [25..25] PWMx 预加载使能 */
+ __IOM uint32_t UPDRST : 1; /*!< [26..26] PWMx Reset 更新 */
+ __IOM uint32_t UPDREP : 1; /*!< [27..27] PWMx Repetition 更新 */
+ __IOM uint32_t UPDGAT : 4; /*!< [31..28] 更新门控 */
+ } PWMCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+
+ struct {
+ __IOM uint32_t DCDE : 1; /*!< [0..0] DAC Reset／Step Trigger 使能 */
+ __IOM uint32_t DCDS : 1; /*!< [1..1] DAC Step Trigger 来源 */
+ __IOM uint32_t DCDR : 1; /*!< [2..2] DAC Reset Trigger 来源 */
+ __IOM uint32_t CAPAM : 1; /*!< [3..3] Capture A 模式选择 */
+ __IOM uint32_t UDM : 1; /*!< [4..4] Up-Down 模式选择 */
+ __IOM uint32_t CAPBM : 1; /*!< [5..5] Capture B 模式选择 */
+ __IOM uint32_t ROM : 2; /*!< [7..6] Roll-Over 模式选择 */
+ __IOM uint32_t OUTROM : 2; /*!< [9..8] 输出 Roll-Over 模式选择 */
+ __IOM uint32_t ADROM : 2; /*!< [11..10] ADC Roll-Over 模式选择 */
+ __IOM uint32_t EEVROM : 2; /*!< [13..12] 事件 Roll-Over 模式选择 */
+ __IOM uint32_t FLTROM : 2; /*!< [15..14] 故障 Roll-Over 模式选择 */
+ __IOM uint32_t MUPD : 1; /*!< [16..16] Master PWM 更新 */
+ __IOM uint32_t UPD0 : 1; /*!< [17..17] PWM0 更新 */
+ __IOM uint32_t UPD1 : 1; /*!< [18..18] PWM1 更新 */
+ __IOM uint32_t UPD2 : 1; /*!< [19..19] PWM2 更新 */
+ __IOM uint32_t UPD3 : 1; /*!< [20..20] PWM3 更新 */
+ __IOM uint32_t UPD4 : 1; /*!< [21..21] PWM4 更新 */
+ __IOM uint32_t UPD5 : 1; /*!< [22..22] PWM5 更新 */
+ __IOM uint32_t UPD6 : 1; /*!< [23..23] PWM6 更新 */
+ __IOM uint32_t UPD7 : 1; /*!< [24..24] PWM7 更新 */
+ uint32_t : 6;
+ __IOM uint32_t BDMADIS : 1; /*!< [31..31] PWMx Burst DMA 禁止 */
+ } PWMCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t CMPA : 1; /*!< [0..0] Compare A 中断标志 */
+ __IOM uint32_t CMPB : 1; /*!< [1..1] Compare B 中断标志 */
+ __IOM uint32_t CMPC : 1; /*!< [2..2] Compare C 中断标志 */
+ __IOM uint32_t CMPD : 1; /*!< [3..3] Compare D 中断标志 */
+ __IOM uint32_t PER : 1; /*!< [4..4] Roll-Over 中断标志 */
+ __IOM uint32_t UPD : 1; /*!< [5..5] Update 中断标志 */
+ __IOM uint32_t SETA : 1; /*!< [6..6] Out A Set 中断标志 */
+ __IOM uint32_t CLRA : 1; /*!< [7..7] Out A Clear 中断标志 */
+ __IOM uint32_t SETB : 1; /*!< [8..8] Out B Set 中断标志 */
+ __IOM uint32_t CLRB : 1; /*!< [9..9] Out B Clear 中断标志 */
+ __IOM uint32_t RST : 1; /*!< [10..10] Reset 中断标志 */
+ __IOM uint32_t REP : 1; /*!< [11..11] Repetition 中断标志 */
+ __IOM uint32_t CAPA : 1; /*!< [12..12] Capture A 中断标志 */
+ __IOM uint32_t CAPB : 1; /*!< [13..13] Capture B 中断标志 */
+ __IOM uint32_t DLYPRT : 1; /*!< [14..14] Delayed Protection 中断标志 */
+ uint32_t : 1;
+ __IM uint32_t CPPSTA : 1; /*!< [16..16] PushPull 当前状态 */
+ __IM uint32_t IPPSTA : 1; /*!< [17..17] PushPull 输出状态（延迟空闲/均衡空闲保护发生时） */
+ __IM uint32_t OUTASTA : 1; /*!< [18..18] OUTA 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTBSTA : 1; /*!< [19..19] OUTB 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTA : 1; /*!< [20..20] OUTA 当前输出（输出级之前） */
+ __IM uint32_t OUTB : 1; /*!< [21..21] OUTB 当前输出（输出级之前） */
+ uint32_t : 10;
+ } PWMISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t CMPAIE : 1; /*!< [0..0] Compare A 中断使能 */
+ __IOM uint32_t CMPBIE : 1; /*!< [1..1] Compare B 中断使能 */
+ __IOM uint32_t CMPCIE : 1; /*!< [2..2] Compare C 中断使能 */
+ __IOM uint32_t CMPDIE : 1; /*!< [3..3] Compare D 中断使能 */
+ __IOM uint32_t PERIE : 1; /*!< [4..4] Roll-Over 中断使能 */
+ __IOM uint32_t UPDIE : 1; /*!< [5..5] Update 中断使能 */
+ __IOM uint32_t SETAIE : 1; /*!< [6..6] Out A Set 中断使能 */
+ __IOM uint32_t CLRAIE : 1; /*!< [7..7] Out A Clear 中断使能 */
+ __IOM uint32_t SETBIE : 1; /*!< [8..8] Out B Set 中断使能 */
+ __IOM uint32_t CLRBIE : 1; /*!< [9..9] Out B Clear 中断使能 */
+ __IOM uint32_t RSTIE : 1; /*!< [10..10] Reset 中断使能 */
+ __IOM uint32_t REPIE : 1; /*!< [11..11] Repetition 中断使能 */
+ __IOM uint32_t CAPAIE : 1; /*!< [12..12] Capture A 中断使能 */
+ __IOM uint32_t CAPBIE : 1; /*!< [13..13] Capture B 中断使能 */
+ __IOM uint32_t DLYPRTIE : 1; /*!< [14..14] Delayed Protection 中断使能 */
+ uint32_t : 1;
+ __IOM uint32_t CMPADE : 1; /*!< [16..16] Compare A DMA使能 */
+ __IOM uint32_t CMPBDE : 1; /*!< [17..17] Compare B DMA使能 */
+ __IOM uint32_t CMPCDE : 1; /*!< [18..18] Compare C DMA使能 */
+ __IOM uint32_t CMPDDE : 1; /*!< [19..19] Compare D DMA使能 */
+ __IOM uint32_t PERDE : 1; /*!< [20..20] Roll-Over DMA使能 */
+ __IOM uint32_t UPDDE : 1; /*!< [21..21] Update DMA使能 */
+ __IOM uint32_t SETADE : 1; /*!< [22..22] Out A Set DMA使能 */
+ __IOM uint32_t CLRADE : 1; /*!< [23..23] Out A Clear DMA使能 */
+ __IOM uint32_t SETBDE : 1; /*!< [24..24] Out B Set DMA使能 */
+ __IOM uint32_t CLRBDE : 1; /*!< [25..25] Out B Clear DMA使能 */
+ __IOM uint32_t RSTDE : 1; /*!< [26..26] Reset DMA使能 */
+ __IOM uint32_t REPDE : 1; /*!< [27..27] Repetition DMA使能 */
+ __IOM uint32_t CAPADE : 1; /*!< [28..28] Capture A DMA使能 */
+ __IOM uint32_t CAPBDE : 1; /*!< [29..29] Capture B DMA使能 */
+ __IOM uint32_t DLYPRTDE : 1; /*!< [30..30] Delayed Protection DMA使能 */
+ uint32_t : 1;
+ } PWMDIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] PWMx Counter 数值 */
+ uint32_t : 2;
+ __IOM uint32_t CNTRD : 1; /*!< [18..18] PWMx Counter 读取 */
+ __IOM uint32_t CNTWR : 1; /*!< [19..19] PWMx Counter 写入 */
+ uint32_t : 12;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+
+ struct {
+ __IOM uint32_t PER : 16; /*!< [15..0] PWMx Period 数值 */
+ uint32_t : 16;
+ } PERR_b;
+ } ;
+
+ union {
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] PWMx Repetition Period 数值 */
+ uint32_t : 24;
+ } REPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+
+ struct {
+ __IOM uint32_t CMPA : 16; /*!< [15..0] PWMx Compare A 数值 */
+ uint32_t : 16;
+ } CMPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+
+ struct {
+ __IOM uint32_t CMPB : 16; /*!< [15..0] PWMx Compare B 数值 */
+ uint32_t : 16;
+ } CMPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+
+ struct {
+ __IOM uint32_t CMPC : 16; /*!< [15..0] PWMx Compare C 数值 */
+ uint32_t : 16;
+ } CMPCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+
+ struct {
+ __IOM uint32_t CMPD : 16; /*!< [15..0] PWMx Compare D 数值 */
+ uint32_t : 16;
+ } CMPDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+
+ struct {
+ __IM uint32_t CAPA : 16; /*!< [15..0] 捕获 A 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 A 方向 */
+ uint32_t : 15;
+ } CAPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+
+ struct {
+ __IM uint32_t CAPB : 16; /*!< [15..0] 捕获 B 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 B 方向 */
+ uint32_t : 15;
+ } CAPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+
+ struct {
+ __IOM uint32_t DTR : 12; /*!< [11..0] 上升沿死区时间 */
+ __IOM uint32_t SDTR : 1; /*!< [12..12] 上升沿死区符号 */
+ uint32_t : 3;
+ __IOM uint32_t DTF : 12; /*!< [27..16] 下降沿死区时间 */
+ __IOM uint32_t SDTF : 1; /*!< [28..28] 下降沿死区符号 */
+ uint32_t : 3;
+ } DTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入有效状态 */
+ uint32_t : 9;
+ } SETAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入无效状态 */
+ uint32_t : 9;
+ } CLRAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入有效状态 */
+ uint32_t : 9;
+ } SETBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入无效状态 */
+ uint32_t : 9;
+ } CLRBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+
+ struct {
+ __IOM uint32_t EE0LTCH : 1; /*!< [0..0] Event 0 锁存位 */
+ __IOM uint32_t EE0FLTR : 4; /*!< [4..1] Event 0 滤波位 */
+ __IOM uint32_t EE1LTCH : 1; /*!< [5..5] Event 1 锁存位 */
+ __IOM uint32_t EE1FLTR : 4; /*!< [9..6] Event 1 滤波位 */
+ __IOM uint32_t EE2LTCH : 1; /*!< [10..10] Event 2 锁存位 */
+ __IOM uint32_t EE2FLTR : 4; /*!< [14..11] Event 2 滤波位 */
+ __IOM uint32_t EE3LTCH : 1; /*!< [15..15] Event 3 锁存位 */
+ __IOM uint32_t EE3FLTR : 4; /*!< [19..16] Event 3 滤波位 */
+ __IOM uint32_t EE4LTCH : 1; /*!< [20..20] Event 4 锁存位 */
+ __IOM uint32_t EE4FLTR : 4; /*!< [24..21] Event 4 滤波位 */
+ uint32_t : 7;
+ } EEFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+
+ struct {
+ __IOM uint32_t EE5LTCH : 1; /*!< [0..0] Event 5 锁存位 */
+ __IOM uint32_t EE5FLTR : 4; /*!< [4..1] Event 5 滤波位 */
+ __IOM uint32_t EE6LTCH : 1; /*!< [5..5] Event 6 锁存位 */
+ __IOM uint32_t EE6FLTR : 4; /*!< [9..6] Event 6 滤波位 */
+ __IOM uint32_t EE7LTCH : 1; /*!< [10..10] Event 7 锁存位 */
+ __IOM uint32_t EE7FLTR : 4; /*!< [14..11] Event 7 滤波位 */
+ __IOM uint32_t EE8LTCH : 1; /*!< [15..15] Event 8 锁存位 */
+ __IOM uint32_t EE8FLTR : 4; /*!< [19..16] Event 8 滤波位 */
+ __IOM uint32_t EE9LTCH : 1; /*!< [20..20] Event 9 锁存位 */
+ __IOM uint32_t EE9FLTR : 4; /*!< [24..21] Event 9 滤波位 */
+ uint32_t : 7;
+ } EEFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+
+ struct {
+ __IOM uint32_t EEVACE : 1; /*!< [0..0] Event A 计数使能 */
+ __IOM uint32_t EEVACRES : 1; /*!< [1..1] Event A 计数复位 */
+ __IOM uint32_t EEVARSTM : 1; /*!< [2..2] Event A计数复位模式 */
+ uint32_t : 1;
+ __IOM uint32_t EEVASEL : 4; /*!< [7..4] Event A 来源选择 */
+ __IOM uint32_t EEVACNT : 6; /*!< [13..8] Event A 计数阈值 */
+ uint32_t : 18;
+ } EEFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+
+ struct {
+ __IOM uint32_t SLV5CMPA : 1; /*!< [0..0] PWM5 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [1..1] Master PWM Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [2..2] Master PWM Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [3..3] Master PWM Compare C事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [4..4] Master PWM Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTPER : 1; /*!< [5..5] Master PWM Period事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [6..6] PWMx Event 0事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [7..7] PWMx Event 1事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [8..8] PWMx Event 2事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [9..9] PWMx Event 3事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [10..10] PWMx Event 4事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [11..11] PWMx Event 5事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [12..12] PWMx Event 6事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [13..13] PWMx Event 7事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [14..14] PWMx Event 8事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [15..15] PWMx Event 9事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVUPD : 1; /*!< [16..16] PWMx Update事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPB : 1; /*!< [17..17] PWMx Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPD : 1; /*!< [18..18] PWMx Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [19..19] PWM0 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [20..20] PWM0 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPD : 1; /*!< [21..21] PWM0 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [22..22] PWM1 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [23..23] PWM1 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPD : 1; /*!< [24..24] PWM1 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [25..25] PWM3 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [26..26] PWM3 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPD : 1; /*!< [27..27] PWM3 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [28..28] PWM4 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [29..29] PWM4 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPD : 1; /*!< [30..30] PWM4 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B事件使 PWMx 计数器复位 */
+ } RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6CMPA : 1; /*!< [0..0] PWM6 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [1..1] PWM6 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPD : 1; /*!< [2..2] PWM6 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [3..3] PWM7 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [4..4] PWM7 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPD : 1; /*!< [5..5] PWM7 Compare D事件使 PWMx 计数器复位 */
+ uint32_t : 26;
+ } RSTER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+
+ struct {
+ __IOM uint32_t CARFRQ : 4; /*!< [3..0] PWMx 载波频率值 */
+ uint32_t : 2;
+ __IOM uint32_t CARDTY : 3; /*!< [8..6] PWMx 斩波占空比值 */
+ uint32_t : 3;
+ __IOM uint32_t STRPW : 4; /*!< [15..12] PWMx 启动脉冲宽度 */
+ uint32_t : 16;
+ } CHPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture A 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [20..20] PWM3 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [21..21] PWM3 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [22..22] PWM3 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [23..23] PWM3 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [24..24] PWM4 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [25..25] PWM4 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [26..26] PWM4 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [27..27] PWM4 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5SETA : 1; /*!< [28..28] PWM5 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [29..29] PWM5 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [30..30] PWM5 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B 事件触发 Capture A 事件 */
+ } CAPACR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture A 事件 */
+ uint32_t : 24;
+ } CAPACER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture B 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [20..20] PWM3 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [21..21] PWM3 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [22..22] PWM3 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [23..23] PWM3 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [24..24] PWM4 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [25..25] PWM4 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [26..26] PWM4 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [27..27] PWM4 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5SETA : 1; /*!< [28..28] PWM5 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [29..29] PWM5 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [30..30] PWM5 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B 事件触发 Capture B 事件 */
+ } CAPBCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture B 事件 */
+ uint32_t : 24;
+ } CAPBCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+
+ struct {
+ __IOM uint32_t POLA : 1; /*!< [0..0] 输出 A 极性 */
+ __IOM uint32_t FAULTA : 2; /*!< [2..1] 输出 A 故障电平 */
+ __IOM uint32_t IDLESA : 1; /*!< [3..3] 输出 A 空闲状态 */
+ __IOM uint32_t CHPA : 1; /*!< [4..4] 输出 A 斩波使能 */
+ __IOM uint32_t IDLEMA : 1; /*!< [5..5] 输出 A 空闲模式 */
+ __IOM uint32_t DIDLA : 1; /*!< [6..6] 输出 A 空闲模式死区使能 */
+ uint32_t : 9;
+ __IOM uint32_t POLB : 1; /*!< [16..16] 输出 B 极性 */
+ __IOM uint32_t FAULTB : 2; /*!< [18..17] 输出 B 故障状态 */
+ __IOM uint32_t IDLESB : 1; /*!< [19..19] 输出 B 空闲状态 */
+ __IOM uint32_t CHPB : 1; /*!< [20..20] 输出 B 斩波使能 */
+ __IOM uint32_t IDLEMB : 1; /*!< [21..21] 输出 B 空闲模式 */
+ __IOM uint32_t DIDLB : 1; /*!< [22..22] 输出 B 空闲模式死区使能 */
+ uint32_t : 2;
+ __IOM uint32_t BIAR : 1; /*!< [25..25] 均衡空闲自动恢复 */
+ uint32_t : 1;
+ __IOM uint32_t DLYPRT : 3; /*!< [29..27] 延迟保护机制 */
+ __IOM uint32_t DLYPRTEN : 1; /*!< [30..30] 延迟保护使能 */
+ __IOM uint32_t DTEN : 1; /*!< [31..31] 死区使能 */
+ } OUTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+
+ struct {
+ __IOM uint32_t FLT0EN : 1; /*!< [0..0] Fault 0 使能 */
+ __IOM uint32_t FLT1EN : 1; /*!< [1..1] Fault 1 使能 */
+ __IOM uint32_t FLT2EN : 1; /*!< [2..2] Fault 2 使能 */
+ __IOM uint32_t FLT3EN : 1; /*!< [3..3] Fault 3 使能 */
+ __IOM uint32_t FLT4EN : 1; /*!< [4..4] Fault 4 使能 */
+ __IOM uint32_t FLT5EN : 1; /*!< [5..5] Fault 5 使能 */
+ __IOM uint32_t FLT6EN : 1; /*!< [6..6] Fault 6 使能 */
+ __IOM uint32_t FLT7EN : 1; /*!< [7..7] Fault 7 使能 */
+ uint32_t : 24;
+ } FLTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+
+ struct {
+ __IOM uint32_t PWMCR0 : 1; /*!< [0..0] PWMCR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMCR1 : 1; /*!< [1..1] PWMCR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMISR : 1; /*!< [2..2] PWMISR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMDIER : 1; /*!< [3..3] PWMDIER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CNTR : 1; /*!< [4..4] CNTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PERR : 1; /*!< [5..5] PERR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t REPR : 1; /*!< [6..6] REPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPAR : 1; /*!< [7..7] CMPAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPBR : 1; /*!< [8..8] CMPBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPCR : 1; /*!< [9..9] CMPCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPDR : 1; /*!< [10..10] CMPDR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPAR : 1; /*!< [11..11] CAPAR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t CAPBR : 1; /*!< [12..12] CAPBR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t DTR : 1; /*!< [13..13] DTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETAR : 1; /*!< [14..14] SETAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRAR : 1; /*!< [15..15] CLRAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETBR : 1; /*!< [16..16] SETBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRBR : 1; /*!< [17..17] CLRBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR0 : 1; /*!< [18..18] EEFR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR1 : 1; /*!< [19..19] EEFR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR2 : 1; /*!< [20..20] EEFR2 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTR : 1; /*!< [21..21] RSTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTER : 1; /*!< [22..22] RSTER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CHPR : 1; /*!< [23..23] CHPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACR : 1; /*!< [24..24] CAPACR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACER : 1; /*!< [25..25] CAPACER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCR : 1; /*!< [26..26] CAPBCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCER : 1; /*!< [27..27] CAPBCER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t OUTR : 1; /*!< [28..28] OUTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t FLTR : 1; /*!< [29..29] FLTR 寄存器支持 System DMA 写入DMADR并更新 */
+ uint32_t : 2;
+ } DMAUR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+
+ struct {
+ __IOM uint32_t DMADR : 32; /*!< [31..0] System DMA 数据地址 */
+ } DMADR_b;
+ } ;
+} HRPWM_SLV2_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV3 (HRPWM_SLV3)
+ */
+
+typedef struct { /*!< (@ 0x4003B400) HRPWM_SLV3 Structure */
+
+ union {
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+
+ struct {
+ __IOM uint32_t CKPSC : 3; /*!< [2..0] PWMx 时钟预分频比 */
+ __IOM uint32_t CONT : 1; /*!< [3..3] PWMx 连续模式 */
+ __IOM uint32_t RETRIG : 1; /*!< [4..4] PWMx 可重触发模式 */
+ __IOM uint32_t HALF : 1; /*!< [5..5] PWMx Half 模式 */
+ __IOM uint32_t INTLVD : 2; /*!< [7..6] PWMx Interleaved 模式 */
+ __IOM uint32_t PSHPLL : 1; /*!< [8..8] PWMx Push-pull 模式 */
+ __IOM uint32_t RSYNCU : 1; /*!< [9..9] PWMx 重同步更新 */
+ __IOM uint32_t SYNCRST : 1; /*!< [10..10] 同步事件复位 PWMx */
+ __IOM uint32_t SYNCSTRT : 1; /*!< [11..11] 同步事件启动 PWMx */
+ uint32_t : 4;
+ __IOM uint32_t DELCMPB : 2; /*!< [17..16] PWMx CMPB Auto-Delayed 模式 */
+ __IOM uint32_t DELCMPD : 2; /*!< [19..18] PWMx CMPD Auto-Delayed 模式 */
+ __IOM uint32_t TRGHLF : 1; /*!< [20..20] PWMx Triggered-half 模式 */
+ __IOM uint32_t GTCMPA : 1; /*!< [21..21] PWMx CMPA Greater Than 模式 */
+ __IOM uint32_t GTCMPC : 1; /*!< [22..22] PWMx CMPC Greater Than 模式 */
+ __IOM uint32_t DACSYNC : 2; /*!< [24..23] DAC Trigger同步 */
+ __IOM uint32_t PREEN : 1; /*!< [25..25] PWMx 预加载使能 */
+ __IOM uint32_t UPDRST : 1; /*!< [26..26] PWMx Reset 更新 */
+ __IOM uint32_t UPDREP : 1; /*!< [27..27] PWMx Repetition 更新 */
+ __IOM uint32_t UPDGAT : 4; /*!< [31..28] 更新门控 */
+ } PWMCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+
+ struct {
+ __IOM uint32_t DCDE : 1; /*!< [0..0] DAC Reset／Step Trigger 使能 */
+ __IOM uint32_t DCDS : 1; /*!< [1..1] DAC Step Trigger 来源 */
+ __IOM uint32_t DCDR : 1; /*!< [2..2] DAC Reset Trigger 来源 */
+ __IOM uint32_t CAPAM : 1; /*!< [3..3] Capture A 模式选择 */
+ __IOM uint32_t UDM : 1; /*!< [4..4] Up-Down 模式选择 */
+ __IOM uint32_t CAPBM : 1; /*!< [5..5] Capture B 模式选择 */
+ __IOM uint32_t ROM : 2; /*!< [7..6] Roll-Over 模式选择 */
+ __IOM uint32_t OUTROM : 2; /*!< [9..8] 输出 Roll-Over 模式选择 */
+ __IOM uint32_t ADROM : 2; /*!< [11..10] ADC Roll-Over 模式选择 */
+ __IOM uint32_t EEVROM : 2; /*!< [13..12] 事件 Roll-Over 模式选择 */
+ __IOM uint32_t FLTROM : 2; /*!< [15..14] 故障 Roll-Over 模式选择 */
+ __IOM uint32_t MUPD : 1; /*!< [16..16] Master PWM 更新 */
+ __IOM uint32_t UPD0 : 1; /*!< [17..17] PWM0 更新 */
+ __IOM uint32_t UPD1 : 1; /*!< [18..18] PWM1 更新 */
+ __IOM uint32_t UPD2 : 1; /*!< [19..19] PWM2 更新 */
+ __IOM uint32_t UPD3 : 1; /*!< [20..20] PWM3 更新 */
+ __IOM uint32_t UPD4 : 1; /*!< [21..21] PWM4 更新 */
+ __IOM uint32_t UPD5 : 1; /*!< [22..22] PWM5 更新 */
+ __IOM uint32_t UPD6 : 1; /*!< [23..23] PWM6 更新 */
+ __IOM uint32_t UPD7 : 1; /*!< [24..24] PWM7 更新 */
+ uint32_t : 6;
+ __IOM uint32_t BDMADIS : 1; /*!< [31..31] PWMx Burst DMA 禁止 */
+ } PWMCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t CMPA : 1; /*!< [0..0] Compare A 中断标志 */
+ __IOM uint32_t CMPB : 1; /*!< [1..1] Compare B 中断标志 */
+ __IOM uint32_t CMPC : 1; /*!< [2..2] Compare C 中断标志 */
+ __IOM uint32_t CMPD : 1; /*!< [3..3] Compare D 中断标志 */
+ __IOM uint32_t PER : 1; /*!< [4..4] Roll-Over 中断标志 */
+ __IOM uint32_t UPD : 1; /*!< [5..5] Update 中断标志 */
+ __IOM uint32_t SETA : 1; /*!< [6..6] Out A Set 中断标志 */
+ __IOM uint32_t CLRA : 1; /*!< [7..7] Out A Clear 中断标志 */
+ __IOM uint32_t SETB : 1; /*!< [8..8] Out B Set 中断标志 */
+ __IOM uint32_t CLRB : 1; /*!< [9..9] Out B Clear 中断标志 */
+ __IOM uint32_t RST : 1; /*!< [10..10] Reset 中断标志 */
+ __IOM uint32_t REP : 1; /*!< [11..11] Repetition 中断标志 */
+ __IOM uint32_t CAPA : 1; /*!< [12..12] Capture A 中断标志 */
+ __IOM uint32_t CAPB : 1; /*!< [13..13] Capture B 中断标志 */
+ __IOM uint32_t DLYPRT : 1; /*!< [14..14] Delayed Protection 中断标志 */
+ uint32_t : 1;
+ __IM uint32_t CPPSTA : 1; /*!< [16..16] PushPull 当前状态 */
+ __IM uint32_t IPPSTA : 1; /*!< [17..17] PushPull 输出状态（延迟空闲/均衡空闲保护发生时） */
+ __IM uint32_t OUTASTA : 1; /*!< [18..18] OUTA 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTBSTA : 1; /*!< [19..19] OUTB 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTA : 1; /*!< [20..20] OUTA 当前输出（输出级之前） */
+ __IM uint32_t OUTB : 1; /*!< [21..21] OUTB 当前输出（输出级之前） */
+ uint32_t : 10;
+ } PWMISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t CMPAIE : 1; /*!< [0..0] Compare A 中断使能 */
+ __IOM uint32_t CMPBIE : 1; /*!< [1..1] Compare B 中断使能 */
+ __IOM uint32_t CMPCIE : 1; /*!< [2..2] Compare C 中断使能 */
+ __IOM uint32_t CMPDIE : 1; /*!< [3..3] Compare D 中断使能 */
+ __IOM uint32_t PERIE : 1; /*!< [4..4] Roll-Over 中断使能 */
+ __IOM uint32_t UPDIE : 1; /*!< [5..5] Update 中断使能 */
+ __IOM uint32_t SETAIE : 1; /*!< [6..6] Out A Set 中断使能 */
+ __IOM uint32_t CLRAIE : 1; /*!< [7..7] Out A Clear 中断使能 */
+ __IOM uint32_t SETBIE : 1; /*!< [8..8] Out B Set 中断使能 */
+ __IOM uint32_t CLRBIE : 1; /*!< [9..9] Out B Clear 中断使能 */
+ __IOM uint32_t RSTIE : 1; /*!< [10..10] Reset 中断使能 */
+ __IOM uint32_t REPIE : 1; /*!< [11..11] Repetition 中断使能 */
+ __IOM uint32_t CAPAIE : 1; /*!< [12..12] Capture A 中断使能 */
+ __IOM uint32_t CAPBIE : 1; /*!< [13..13] Capture B 中断使能 */
+ __IOM uint32_t DLYPRTIE : 1; /*!< [14..14] Delayed Protection 中断使能 */
+ uint32_t : 1;
+ __IOM uint32_t CMPADE : 1; /*!< [16..16] Compare A DMA使能 */
+ __IOM uint32_t CMPBDE : 1; /*!< [17..17] Compare B DMA使能 */
+ __IOM uint32_t CMPCDE : 1; /*!< [18..18] Compare C DMA使能 */
+ __IOM uint32_t CMPDDE : 1; /*!< [19..19] Compare D DMA使能 */
+ __IOM uint32_t PERDE : 1; /*!< [20..20] Roll-Over DMA使能 */
+ __IOM uint32_t UPDDE : 1; /*!< [21..21] Update DMA使能 */
+ __IOM uint32_t SETADE : 1; /*!< [22..22] Out A Set DMA使能 */
+ __IOM uint32_t CLRADE : 1; /*!< [23..23] Out A Clear DMA使能 */
+ __IOM uint32_t SETBDE : 1; /*!< [24..24] Out B Set DMA使能 */
+ __IOM uint32_t CLRBDE : 1; /*!< [25..25] Out B Clear DMA使能 */
+ __IOM uint32_t RSTDE : 1; /*!< [26..26] Reset DMA使能 */
+ __IOM uint32_t REPDE : 1; /*!< [27..27] Repetition DMA使能 */
+ __IOM uint32_t CAPADE : 1; /*!< [28..28] Capture A DMA使能 */
+ __IOM uint32_t CAPBDE : 1; /*!< [29..29] Capture B DMA使能 */
+ __IOM uint32_t DLYPRTDE : 1; /*!< [30..30] Delayed Protection DMA使能 */
+ uint32_t : 1;
+ } PWMDIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] PWMx Counter 数值 */
+ uint32_t : 2;
+ __IOM uint32_t CNTRD : 1; /*!< [18..18] PWMx Counter 读取 */
+ __IOM uint32_t CNTWR : 1; /*!< [19..19] PWMx Counter 写入 */
+ uint32_t : 12;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+
+ struct {
+ __IOM uint32_t PER : 16; /*!< [15..0] PWMx Period 数值 */
+ uint32_t : 16;
+ } PERR_b;
+ } ;
+
+ union {
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] PWMx Repetition Period 数值 */
+ uint32_t : 24;
+ } REPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+
+ struct {
+ __IOM uint32_t CMPA : 16; /*!< [15..0] PWMx Compare A 数值 */
+ uint32_t : 16;
+ } CMPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+
+ struct {
+ __IOM uint32_t CMPB : 16; /*!< [15..0] PWMx Compare B 数值 */
+ uint32_t : 16;
+ } CMPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+
+ struct {
+ __IOM uint32_t CMPC : 16; /*!< [15..0] PWMx Compare C 数值 */
+ uint32_t : 16;
+ } CMPCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+
+ struct {
+ __IOM uint32_t CMPD : 16; /*!< [15..0] PWMx Compare D 数值 */
+ uint32_t : 16;
+ } CMPDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+
+ struct {
+ __IM uint32_t CAPA : 16; /*!< [15..0] 捕获 A 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 A 方向 */
+ uint32_t : 15;
+ } CAPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+
+ struct {
+ __IM uint32_t CAPB : 16; /*!< [15..0] 捕获 B 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 B 方向 */
+ uint32_t : 15;
+ } CAPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+
+ struct {
+ __IOM uint32_t DTR : 12; /*!< [11..0] 上升沿死区时间 */
+ __IOM uint32_t SDTR : 1; /*!< [12..12] 上升沿死区符号 */
+ uint32_t : 3;
+ __IOM uint32_t DTF : 12; /*!< [27..16] 下降沿死区时间 */
+ __IOM uint32_t SDTF : 1; /*!< [28..28] 下降沿死区符号 */
+ uint32_t : 3;
+ } DTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入有效状态 */
+ uint32_t : 9;
+ } SETAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入无效状态 */
+ uint32_t : 9;
+ } CLRAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入有效状态 */
+ uint32_t : 9;
+ } SETBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入无效状态 */
+ uint32_t : 9;
+ } CLRBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+
+ struct {
+ __IOM uint32_t EE0LTCH : 1; /*!< [0..0] Event 0 锁存位 */
+ __IOM uint32_t EE0FLTR : 4; /*!< [4..1] Event 0 滤波位 */
+ __IOM uint32_t EE1LTCH : 1; /*!< [5..5] Event 1 锁存位 */
+ __IOM uint32_t EE1FLTR : 4; /*!< [9..6] Event 1 滤波位 */
+ __IOM uint32_t EE2LTCH : 1; /*!< [10..10] Event 2 锁存位 */
+ __IOM uint32_t EE2FLTR : 4; /*!< [14..11] Event 2 滤波位 */
+ __IOM uint32_t EE3LTCH : 1; /*!< [15..15] Event 3 锁存位 */
+ __IOM uint32_t EE3FLTR : 4; /*!< [19..16] Event 3 滤波位 */
+ __IOM uint32_t EE4LTCH : 1; /*!< [20..20] Event 4 锁存位 */
+ __IOM uint32_t EE4FLTR : 4; /*!< [24..21] Event 4 滤波位 */
+ uint32_t : 7;
+ } EEFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+
+ struct {
+ __IOM uint32_t EE5LTCH : 1; /*!< [0..0] Event 5 锁存位 */
+ __IOM uint32_t EE5FLTR : 4; /*!< [4..1] Event 5 滤波位 */
+ __IOM uint32_t EE6LTCH : 1; /*!< [5..5] Event 6 锁存位 */
+ __IOM uint32_t EE6FLTR : 4; /*!< [9..6] Event 6 滤波位 */
+ __IOM uint32_t EE7LTCH : 1; /*!< [10..10] Event 7 锁存位 */
+ __IOM uint32_t EE7FLTR : 4; /*!< [14..11] Event 7 滤波位 */
+ __IOM uint32_t EE8LTCH : 1; /*!< [15..15] Event 8 锁存位 */
+ __IOM uint32_t EE8FLTR : 4; /*!< [19..16] Event 8 滤波位 */
+ __IOM uint32_t EE9LTCH : 1; /*!< [20..20] Event 9 锁存位 */
+ __IOM uint32_t EE9FLTR : 4; /*!< [24..21] Event 9 滤波位 */
+ uint32_t : 7;
+ } EEFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+
+ struct {
+ __IOM uint32_t EEVACE : 1; /*!< [0..0] Event A 计数使能 */
+ __IOM uint32_t EEVACRES : 1; /*!< [1..1] Event A 计数复位 */
+ __IOM uint32_t EEVARSTM : 1; /*!< [2..2] Event A计数复位模式 */
+ uint32_t : 1;
+ __IOM uint32_t EEVASEL : 4; /*!< [7..4] Event A 来源选择 */
+ __IOM uint32_t EEVACNT : 6; /*!< [13..8] Event A 计数阈值 */
+ uint32_t : 18;
+ } EEFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+
+ struct {
+ __IOM uint32_t SLV5CMPA : 1; /*!< [0..0] PWM5 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [1..1] Master PWM Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [2..2] Master PWM Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [3..3] Master PWM Compare C事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [4..4] Master PWM Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTPER : 1; /*!< [5..5] Master PWM Period事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [6..6] PWMx Event 0事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [7..7] PWMx Event 1事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [8..8] PWMx Event 2事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [9..9] PWMx Event 3事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [10..10] PWMx Event 4事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [11..11] PWMx Event 5事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [12..12] PWMx Event 6事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [13..13] PWMx Event 7事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [14..14] PWMx Event 8事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [15..15] PWMx Event 9事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVUPD : 1; /*!< [16..16] PWMx Update事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPB : 1; /*!< [17..17] PWMx Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPD : 1; /*!< [18..18] PWMx Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [19..19] PWM0 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [20..20] PWM0 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPD : 1; /*!< [21..21] PWM0 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [22..22] PWM1 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [23..23] PWM1 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPD : 1; /*!< [24..24] PWM1 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [25..25] PWM2 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [26..26] PWM2 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPD : 1; /*!< [27..27] PWM2 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [28..28] PWM4 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [29..29] PWM4 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPD : 1; /*!< [30..30] PWM4 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B事件使 PWMx 计数器复位 */
+ } RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6CMPA : 1; /*!< [0..0] PWM6 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [1..1] PWM6 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPD : 1; /*!< [2..2] PWM6 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [3..3] PWM7 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [4..4] PWM7 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPD : 1; /*!< [5..5] PWM7 Compare D事件使 PWMx 计数器复位 */
+ uint32_t : 26;
+ } RSTER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+
+ struct {
+ __IOM uint32_t CARFRQ : 4; /*!< [3..0] PWMx 载波频率值 */
+ uint32_t : 2;
+ __IOM uint32_t CARDTY : 3; /*!< [8..6] PWMx 斩波占空比值 */
+ uint32_t : 3;
+ __IOM uint32_t STRPW : 4; /*!< [15..12] PWMx 启动脉冲宽度 */
+ uint32_t : 16;
+ } CHPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture A 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [20..20] PWM2 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [21..21] PWM2 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [24..24] PWM4 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [25..25] PWM4 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [26..26] PWM4 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [27..27] PWM4 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5SETA : 1; /*!< [28..28] PWM5 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [29..29] PWM5 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [30..30] PWM5 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B 事件触发 Capture A 事件 */
+ } CAPACR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture A 事件 */
+ uint32_t : 24;
+ } CAPACER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture B 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [20..20] PWM2 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [21..21] PWM2 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [24..24] PWM4 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [25..25] PWM4 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [26..26] PWM4 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [27..27] PWM4 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5SETA : 1; /*!< [28..28] PWM5 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [29..29] PWM5 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [30..30] PWM5 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B 事件触发 Capture B 事件 */
+ } CAPBCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture B 事件 */
+ uint32_t : 24;
+ } CAPBCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+
+ struct {
+ __IOM uint32_t POLA : 1; /*!< [0..0] 输出 A 极性 */
+ __IOM uint32_t FAULTA : 2; /*!< [2..1] 输出 A 故障电平 */
+ __IOM uint32_t IDLESA : 1; /*!< [3..3] 输出 A 空闲状态 */
+ __IOM uint32_t CHPA : 1; /*!< [4..4] 输出 A 斩波使能 */
+ __IOM uint32_t IDLEMA : 1; /*!< [5..5] 输出 A 空闲模式 */
+ __IOM uint32_t DIDLA : 1; /*!< [6..6] 输出 A 空闲模式死区使能 */
+ uint32_t : 9;
+ __IOM uint32_t POLB : 1; /*!< [16..16] 输出 B 极性 */
+ __IOM uint32_t FAULTB : 2; /*!< [18..17] 输出 B 故障状态 */
+ __IOM uint32_t IDLESB : 1; /*!< [19..19] 输出 B 空闲状态 */
+ __IOM uint32_t CHPB : 1; /*!< [20..20] 输出 B 斩波使能 */
+ __IOM uint32_t IDLEMB : 1; /*!< [21..21] 输出 B 空闲模式 */
+ __IOM uint32_t DIDLB : 1; /*!< [22..22] 输出 B 空闲模式死区使能 */
+ uint32_t : 2;
+ __IOM uint32_t BIAR : 1; /*!< [25..25] 均衡空闲自动恢复 */
+ uint32_t : 1;
+ __IOM uint32_t DLYPRT : 3; /*!< [29..27] 延迟保护机制 */
+ __IOM uint32_t DLYPRTEN : 1; /*!< [30..30] 延迟保护使能 */
+ __IOM uint32_t DTEN : 1; /*!< [31..31] 死区使能 */
+ } OUTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+
+ struct {
+ __IOM uint32_t FLT0EN : 1; /*!< [0..0] Fault 0 使能 */
+ __IOM uint32_t FLT1EN : 1; /*!< [1..1] Fault 1 使能 */
+ __IOM uint32_t FLT2EN : 1; /*!< [2..2] Fault 2 使能 */
+ __IOM uint32_t FLT3EN : 1; /*!< [3..3] Fault 3 使能 */
+ __IOM uint32_t FLT4EN : 1; /*!< [4..4] Fault 4 使能 */
+ __IOM uint32_t FLT5EN : 1; /*!< [5..5] Fault 5 使能 */
+ __IOM uint32_t FLT6EN : 1; /*!< [6..6] Fault 6 使能 */
+ __IOM uint32_t FLT7EN : 1; /*!< [7..7] Fault 7 使能 */
+ uint32_t : 24;
+ } FLTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+
+ struct {
+ __IOM uint32_t PWMCR0 : 1; /*!< [0..0] PWMCR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMCR1 : 1; /*!< [1..1] PWMCR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMISR : 1; /*!< [2..2] PWMISR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMDIER : 1; /*!< [3..3] PWMDIER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CNTR : 1; /*!< [4..4] CNTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PERR : 1; /*!< [5..5] PERR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t REPR : 1; /*!< [6..6] REPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPAR : 1; /*!< [7..7] CMPAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPBR : 1; /*!< [8..8] CMPBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPCR : 1; /*!< [9..9] CMPCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPDR : 1; /*!< [10..10] CMPDR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPAR : 1; /*!< [11..11] CAPAR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t CAPBR : 1; /*!< [12..12] CAPBR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t DTR : 1; /*!< [13..13] DTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETAR : 1; /*!< [14..14] SETAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRAR : 1; /*!< [15..15] CLRAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETBR : 1; /*!< [16..16] SETBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRBR : 1; /*!< [17..17] CLRBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR0 : 1; /*!< [18..18] EEFR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR1 : 1; /*!< [19..19] EEFR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR2 : 1; /*!< [20..20] EEFR2 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTR : 1; /*!< [21..21] RSTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTER : 1; /*!< [22..22] RSTER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CHPR : 1; /*!< [23..23] CHPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACR : 1; /*!< [24..24] CAPACR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACER : 1; /*!< [25..25] CAPACER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCR : 1; /*!< [26..26] CAPBCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCER : 1; /*!< [27..27] CAPBCER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t OUTR : 1; /*!< [28..28] OUTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t FLTR : 1; /*!< [29..29] FLTR 寄存器支持 System DMA 写入DMADR并更新 */
+ uint32_t : 2;
+ } DMAUR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+
+ struct {
+ __IOM uint32_t DMADR : 32; /*!< [31..0] System DMA 数据地址 */
+ } DMADR_b;
+ } ;
+} HRPWM_SLV3_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV4 (HRPWM_SLV4)
+ */
+
+typedef struct { /*!< (@ 0x4003B500) HRPWM_SLV4 Structure */
+
+ union {
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+
+ struct {
+ __IOM uint32_t CKPSC : 3; /*!< [2..0] PWMx 时钟预分频比 */
+ __IOM uint32_t CONT : 1; /*!< [3..3] PWMx 连续模式 */
+ __IOM uint32_t RETRIG : 1; /*!< [4..4] PWMx 可重触发模式 */
+ __IOM uint32_t HALF : 1; /*!< [5..5] PWMx Half 模式 */
+ __IOM uint32_t INTLVD : 2; /*!< [7..6] PWMx Interleaved 模式 */
+ __IOM uint32_t PSHPLL : 1; /*!< [8..8] PWMx Push-pull 模式 */
+ __IOM uint32_t RSYNCU : 1; /*!< [9..9] PWMx 重同步更新 */
+ __IOM uint32_t SYNCRST : 1; /*!< [10..10] 同步事件复位 PWMx */
+ __IOM uint32_t SYNCSTRT : 1; /*!< [11..11] 同步事件启动 PWMx */
+ uint32_t : 4;
+ __IOM uint32_t DELCMPB : 2; /*!< [17..16] PWMx CMPB Auto-Delayed 模式 */
+ __IOM uint32_t DELCMPD : 2; /*!< [19..18] PWMx CMPD Auto-Delayed 模式 */
+ __IOM uint32_t TRGHLF : 1; /*!< [20..20] PWMx Triggered-half 模式 */
+ __IOM uint32_t GTCMPA : 1; /*!< [21..21] PWMx CMPA Greater Than 模式 */
+ __IOM uint32_t GTCMPC : 1; /*!< [22..22] PWMx CMPC Greater Than 模式 */
+ __IOM uint32_t DACSYNC : 2; /*!< [24..23] DAC Trigger同步 */
+ __IOM uint32_t PREEN : 1; /*!< [25..25] PWMx 预加载使能 */
+ __IOM uint32_t UPDRST : 1; /*!< [26..26] PWMx Reset 更新 */
+ __IOM uint32_t UPDREP : 1; /*!< [27..27] PWMx Repetition 更新 */
+ __IOM uint32_t UPDGAT : 4; /*!< [31..28] 更新门控 */
+ } PWMCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+
+ struct {
+ __IOM uint32_t DCDE : 1; /*!< [0..0] DAC Reset／Step Trigger 使能 */
+ __IOM uint32_t DCDS : 1; /*!< [1..1] DAC Step Trigger 来源 */
+ __IOM uint32_t DCDR : 1; /*!< [2..2] DAC Reset Trigger 来源 */
+ __IOM uint32_t CAPAM : 1; /*!< [3..3] Capture A 模式选择 */
+ __IOM uint32_t UDM : 1; /*!< [4..4] Up-Down 模式选择 */
+ __IOM uint32_t CAPBM : 1; /*!< [5..5] Capture B 模式选择 */
+ __IOM uint32_t ROM : 2; /*!< [7..6] Roll-Over 模式选择 */
+ __IOM uint32_t OUTROM : 2; /*!< [9..8] 输出 Roll-Over 模式选择 */
+ __IOM uint32_t ADROM : 2; /*!< [11..10] ADC Roll-Over 模式选择 */
+ __IOM uint32_t EEVROM : 2; /*!< [13..12] 事件 Roll-Over 模式选择 */
+ __IOM uint32_t FLTROM : 2; /*!< [15..14] 故障 Roll-Over 模式选择 */
+ __IOM uint32_t MUPD : 1; /*!< [16..16] Master PWM 更新 */
+ __IOM uint32_t UPD0 : 1; /*!< [17..17] PWM0 更新 */
+ __IOM uint32_t UPD1 : 1; /*!< [18..18] PWM1 更新 */
+ __IOM uint32_t UPD2 : 1; /*!< [19..19] PWM2 更新 */
+ __IOM uint32_t UPD3 : 1; /*!< [20..20] PWM3 更新 */
+ __IOM uint32_t UPD4 : 1; /*!< [21..21] PWM4 更新 */
+ __IOM uint32_t UPD5 : 1; /*!< [22..22] PWM5 更新 */
+ __IOM uint32_t UPD6 : 1; /*!< [23..23] PWM6 更新 */
+ __IOM uint32_t UPD7 : 1; /*!< [24..24] PWM7 更新 */
+ uint32_t : 6;
+ __IOM uint32_t BDMADIS : 1; /*!< [31..31] PWMx Burst DMA 禁止 */
+ } PWMCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t CMPA : 1; /*!< [0..0] Compare A 中断标志 */
+ __IOM uint32_t CMPB : 1; /*!< [1..1] Compare B 中断标志 */
+ __IOM uint32_t CMPC : 1; /*!< [2..2] Compare C 中断标志 */
+ __IOM uint32_t CMPD : 1; /*!< [3..3] Compare D 中断标志 */
+ __IOM uint32_t PER : 1; /*!< [4..4] Roll-Over 中断标志 */
+ __IOM uint32_t UPD : 1; /*!< [5..5] Update 中断标志 */
+ __IOM uint32_t SETA : 1; /*!< [6..6] Out A Set 中断标志 */
+ __IOM uint32_t CLRA : 1; /*!< [7..7] Out A Clear 中断标志 */
+ __IOM uint32_t SETB : 1; /*!< [8..8] Out B Set 中断标志 */
+ __IOM uint32_t CLRB : 1; /*!< [9..9] Out B Clear 中断标志 */
+ __IOM uint32_t RST : 1; /*!< [10..10] Reset 中断标志 */
+ __IOM uint32_t REP : 1; /*!< [11..11] Repetition 中断标志 */
+ __IOM uint32_t CAPA : 1; /*!< [12..12] Capture A 中断标志 */
+ __IOM uint32_t CAPB : 1; /*!< [13..13] Capture B 中断标志 */
+ __IOM uint32_t DLYPRT : 1; /*!< [14..14] Delayed Protection 中断标志 */
+ uint32_t : 1;
+ __IM uint32_t CPPSTA : 1; /*!< [16..16] PushPull 当前状态 */
+ __IM uint32_t IPPSTA : 1; /*!< [17..17] PushPull 输出状态（延迟空闲/均衡空闲保护发生时） */
+ __IM uint32_t OUTASTA : 1; /*!< [18..18] OUTA 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTBSTA : 1; /*!< [19..19] OUTB 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTA : 1; /*!< [20..20] OUTA 当前输出（输出级之前） */
+ __IM uint32_t OUTB : 1; /*!< [21..21] OUTB 当前输出（输出级之前） */
+ uint32_t : 10;
+ } PWMISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t CMPAIE : 1; /*!< [0..0] Compare A 中断使能 */
+ __IOM uint32_t CMPBIE : 1; /*!< [1..1] Compare B 中断使能 */
+ __IOM uint32_t CMPCIE : 1; /*!< [2..2] Compare C 中断使能 */
+ __IOM uint32_t CMPDIE : 1; /*!< [3..3] Compare D 中断使能 */
+ __IOM uint32_t PERIE : 1; /*!< [4..4] Roll-Over 中断使能 */
+ __IOM uint32_t UPDIE : 1; /*!< [5..5] Update 中断使能 */
+ __IOM uint32_t SETAIE : 1; /*!< [6..6] Out A Set 中断使能 */
+ __IOM uint32_t CLRAIE : 1; /*!< [7..7] Out A Clear 中断使能 */
+ __IOM uint32_t SETBIE : 1; /*!< [8..8] Out B Set 中断使能 */
+ __IOM uint32_t CLRBIE : 1; /*!< [9..9] Out B Clear 中断使能 */
+ __IOM uint32_t RSTIE : 1; /*!< [10..10] Reset 中断使能 */
+ __IOM uint32_t REPIE : 1; /*!< [11..11] Repetition 中断使能 */
+ __IOM uint32_t CAPAIE : 1; /*!< [12..12] Capture A 中断使能 */
+ __IOM uint32_t CAPBIE : 1; /*!< [13..13] Capture B 中断使能 */
+ __IOM uint32_t DLYPRTIE : 1; /*!< [14..14] Delayed Protection 中断使能 */
+ uint32_t : 1;
+ __IOM uint32_t CMPADE : 1; /*!< [16..16] Compare A DMA使能 */
+ __IOM uint32_t CMPBDE : 1; /*!< [17..17] Compare B DMA使能 */
+ __IOM uint32_t CMPCDE : 1; /*!< [18..18] Compare C DMA使能 */
+ __IOM uint32_t CMPDDE : 1; /*!< [19..19] Compare D DMA使能 */
+ __IOM uint32_t PERDE : 1; /*!< [20..20] Roll-Over DMA使能 */
+ __IOM uint32_t UPDDE : 1; /*!< [21..21] Update DMA使能 */
+ __IOM uint32_t SETADE : 1; /*!< [22..22] Out A Set DMA使能 */
+ __IOM uint32_t CLRADE : 1; /*!< [23..23] Out A Clear DMA使能 */
+ __IOM uint32_t SETBDE : 1; /*!< [24..24] Out B Set DMA使能 */
+ __IOM uint32_t CLRBDE : 1; /*!< [25..25] Out B Clear DMA使能 */
+ __IOM uint32_t RSTDE : 1; /*!< [26..26] Reset DMA使能 */
+ __IOM uint32_t REPDE : 1; /*!< [27..27] Repetition DMA使能 */
+ __IOM uint32_t CAPADE : 1; /*!< [28..28] Capture A DMA使能 */
+ __IOM uint32_t CAPBDE : 1; /*!< [29..29] Capture B DMA使能 */
+ __IOM uint32_t DLYPRTDE : 1; /*!< [30..30] Delayed Protection DMA使能 */
+ uint32_t : 1;
+ } PWMDIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] PWMx Counter 数值 */
+ uint32_t : 2;
+ __IOM uint32_t CNTRD : 1; /*!< [18..18] PWMx Counter 读取 */
+ __IOM uint32_t CNTWR : 1; /*!< [19..19] PWMx Counter 写入 */
+ uint32_t : 12;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+
+ struct {
+ __IOM uint32_t PER : 16; /*!< [15..0] PWMx Period 数值 */
+ uint32_t : 16;
+ } PERR_b;
+ } ;
+
+ union {
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] PWMx Repetition Period 数值 */
+ uint32_t : 24;
+ } REPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+
+ struct {
+ __IOM uint32_t CMPA : 16; /*!< [15..0] PWMx Compare A 数值 */
+ uint32_t : 16;
+ } CMPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+
+ struct {
+ __IOM uint32_t CMPB : 16; /*!< [15..0] PWMx Compare B 数值 */
+ uint32_t : 16;
+ } CMPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+
+ struct {
+ __IOM uint32_t CMPC : 16; /*!< [15..0] PWMx Compare C 数值 */
+ uint32_t : 16;
+ } CMPCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+
+ struct {
+ __IOM uint32_t CMPD : 16; /*!< [15..0] PWMx Compare D 数值 */
+ uint32_t : 16;
+ } CMPDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+
+ struct {
+ __IM uint32_t CAPA : 16; /*!< [15..0] 捕获 A 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 A 方向 */
+ uint32_t : 15;
+ } CAPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+
+ struct {
+ __IM uint32_t CAPB : 16; /*!< [15..0] 捕获 B 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 B 方向 */
+ uint32_t : 15;
+ } CAPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+
+ struct {
+ __IOM uint32_t DTR : 12; /*!< [11..0] 上升沿死区时间 */
+ __IOM uint32_t SDTR : 1; /*!< [12..12] 上升沿死区符号 */
+ uint32_t : 3;
+ __IOM uint32_t DTF : 12; /*!< [27..16] 下降沿死区时间 */
+ __IOM uint32_t SDTF : 1; /*!< [28..28] 下降沿死区符号 */
+ uint32_t : 3;
+ } DTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入有效状态 */
+ uint32_t : 9;
+ } SETAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入无效状态 */
+ uint32_t : 9;
+ } CLRAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入有效状态 */
+ uint32_t : 9;
+ } SETBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入无效状态 */
+ uint32_t : 9;
+ } CLRBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+
+ struct {
+ __IOM uint32_t EE0LTCH : 1; /*!< [0..0] Event 0 锁存位 */
+ __IOM uint32_t EE0FLTR : 4; /*!< [4..1] Event 0 滤波位 */
+ __IOM uint32_t EE1LTCH : 1; /*!< [5..5] Event 1 锁存位 */
+ __IOM uint32_t EE1FLTR : 4; /*!< [9..6] Event 1 滤波位 */
+ __IOM uint32_t EE2LTCH : 1; /*!< [10..10] Event 2 锁存位 */
+ __IOM uint32_t EE2FLTR : 4; /*!< [14..11] Event 2 滤波位 */
+ __IOM uint32_t EE3LTCH : 1; /*!< [15..15] Event 3 锁存位 */
+ __IOM uint32_t EE3FLTR : 4; /*!< [19..16] Event 3 滤波位 */
+ __IOM uint32_t EE4LTCH : 1; /*!< [20..20] Event 4 锁存位 */
+ __IOM uint32_t EE4FLTR : 4; /*!< [24..21] Event 4 滤波位 */
+ uint32_t : 7;
+ } EEFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+
+ struct {
+ __IOM uint32_t EE5LTCH : 1; /*!< [0..0] Event 5 锁存位 */
+ __IOM uint32_t EE5FLTR : 4; /*!< [4..1] Event 5 滤波位 */
+ __IOM uint32_t EE6LTCH : 1; /*!< [5..5] Event 6 锁存位 */
+ __IOM uint32_t EE6FLTR : 4; /*!< [9..6] Event 6 滤波位 */
+ __IOM uint32_t EE7LTCH : 1; /*!< [10..10] Event 7 锁存位 */
+ __IOM uint32_t EE7FLTR : 4; /*!< [14..11] Event 7 滤波位 */
+ __IOM uint32_t EE8LTCH : 1; /*!< [15..15] Event 8 锁存位 */
+ __IOM uint32_t EE8FLTR : 4; /*!< [19..16] Event 8 滤波位 */
+ __IOM uint32_t EE9LTCH : 1; /*!< [20..20] Event 9 锁存位 */
+ __IOM uint32_t EE9FLTR : 4; /*!< [24..21] Event 9 滤波位 */
+ uint32_t : 7;
+ } EEFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+
+ struct {
+ __IOM uint32_t EEVACE : 1; /*!< [0..0] Event A 计数使能 */
+ __IOM uint32_t EEVACRES : 1; /*!< [1..1] Event A 计数复位 */
+ __IOM uint32_t EEVARSTM : 1; /*!< [2..2] Event A计数复位模式 */
+ uint32_t : 1;
+ __IOM uint32_t EEVASEL : 4; /*!< [7..4] Event A 来源选择 */
+ __IOM uint32_t EEVACNT : 6; /*!< [13..8] Event A 计数阈值 */
+ uint32_t : 18;
+ } EEFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+
+ struct {
+ __IOM uint32_t SLV5CMPA : 1; /*!< [0..0] PWM5 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [1..1] Master PWM Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [2..2] Master PWM Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [3..3] Master PWM Compare C事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [4..4] Master PWM Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTPER : 1; /*!< [5..5] Master PWM Period事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [6..6] PWMx Event 0事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [7..7] PWMx Event 1事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [8..8] PWMx Event 2事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [9..9] PWMx Event 3事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [10..10] PWMx Event 4事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [11..11] PWMx Event 5事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [12..12] PWMx Event 6事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [13..13] PWMx Event 7事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [14..14] PWMx Event 8事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [15..15] PWMx Event 9事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVUPD : 1; /*!< [16..16] PWMx Update事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPB : 1; /*!< [17..17] PWMx Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPD : 1; /*!< [18..18] PWMx Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [19..19] PWM0 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [20..20] PWM0 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPD : 1; /*!< [21..21] PWM0 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [22..22] PWM1 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [23..23] PWM1 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPD : 1; /*!< [24..24] PWM1 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [25..25] PWM2 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [26..26] PWM2 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPD : 1; /*!< [27..27] PWM2 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [28..28] PWM3 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [29..29] PWM3 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPD : 1; /*!< [30..30] PWM3 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B事件使 PWMx 计数器复位 */
+ } RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6CMPA : 1; /*!< [0..0] PWM6 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [1..1] PWM6 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPD : 1; /*!< [2..2] PWM6 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [3..3] PWM7 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [4..4] PWM7 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPD : 1; /*!< [5..5] PWM7 Compare D事件使 PWMx 计数器复位 */
+ uint32_t : 26;
+ } RSTER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+
+ struct {
+ __IOM uint32_t CARFRQ : 4; /*!< [3..0] PWMx 载波频率值 */
+ uint32_t : 2;
+ __IOM uint32_t CARDTY : 3; /*!< [8..6] PWMx 斩波占空比值 */
+ uint32_t : 3;
+ __IOM uint32_t STRPW : 4; /*!< [15..12] PWMx 启动脉冲宽度 */
+ uint32_t : 16;
+ } CHPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture A 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [20..20] PWM2 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [21..21] PWM2 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [24..24] PWM3 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [25..25] PWM3 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [26..26] PWM3 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [27..27] PWM3 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5SETA : 1; /*!< [28..28] PWM5 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [29..29] PWM5 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [30..30] PWM5 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B 事件触发 Capture A 事件 */
+ } CAPACR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture A 事件 */
+ uint32_t : 24;
+ } CAPACER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture B 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [20..20] PWM2 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [21..21] PWM2 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [24..24] PWM3 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [25..25] PWM3 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [26..26] PWM3 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [27..27] PWM3 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5SETA : 1; /*!< [28..28] PWM5 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [29..29] PWM5 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [30..30] PWM5 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [31..31] PWM5 Compare B 事件触发 Capture B 事件 */
+ } CAPBCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture B 事件 */
+ uint32_t : 24;
+ } CAPBCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+
+ struct {
+ __IOM uint32_t POLA : 1; /*!< [0..0] 输出 A 极性 */
+ __IOM uint32_t FAULTA : 2; /*!< [2..1] 输出 A 故障电平 */
+ __IOM uint32_t IDLESA : 1; /*!< [3..3] 输出 A 空闲状态 */
+ __IOM uint32_t CHPA : 1; /*!< [4..4] 输出 A 斩波使能 */
+ __IOM uint32_t IDLEMA : 1; /*!< [5..5] 输出 A 空闲模式 */
+ __IOM uint32_t DIDLA : 1; /*!< [6..6] 输出 A 空闲模式死区使能 */
+ uint32_t : 9;
+ __IOM uint32_t POLB : 1; /*!< [16..16] 输出 B 极性 */
+ __IOM uint32_t FAULTB : 2; /*!< [18..17] 输出 B 故障状态 */
+ __IOM uint32_t IDLESB : 1; /*!< [19..19] 输出 B 空闲状态 */
+ __IOM uint32_t CHPB : 1; /*!< [20..20] 输出 B 斩波使能 */
+ __IOM uint32_t IDLEMB : 1; /*!< [21..21] 输出 B 空闲模式 */
+ __IOM uint32_t DIDLB : 1; /*!< [22..22] 输出 B 空闲模式死区使能 */
+ uint32_t : 2;
+ __IOM uint32_t BIAR : 1; /*!< [25..25] 均衡空闲自动恢复 */
+ uint32_t : 1;
+ __IOM uint32_t DLYPRT : 3; /*!< [29..27] 延迟保护机制 */
+ __IOM uint32_t DLYPRTEN : 1; /*!< [30..30] 延迟保护使能 */
+ __IOM uint32_t DTEN : 1; /*!< [31..31] 死区使能 */
+ } OUTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+
+ struct {
+ __IOM uint32_t FLT0EN : 1; /*!< [0..0] Fault 0 使能 */
+ __IOM uint32_t FLT1EN : 1; /*!< [1..1] Fault 1 使能 */
+ __IOM uint32_t FLT2EN : 1; /*!< [2..2] Fault 2 使能 */
+ __IOM uint32_t FLT3EN : 1; /*!< [3..3] Fault 3 使能 */
+ __IOM uint32_t FLT4EN : 1; /*!< [4..4] Fault 4 使能 */
+ __IOM uint32_t FLT5EN : 1; /*!< [5..5] Fault 5 使能 */
+ __IOM uint32_t FLT6EN : 1; /*!< [6..6] Fault 6 使能 */
+ __IOM uint32_t FLT7EN : 1; /*!< [7..7] Fault 7 使能 */
+ uint32_t : 24;
+ } FLTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+
+ struct {
+ __IOM uint32_t PWMCR0 : 1; /*!< [0..0] PWMCR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMCR1 : 1; /*!< [1..1] PWMCR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMISR : 1; /*!< [2..2] PWMISR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMDIER : 1; /*!< [3..3] PWMDIER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CNTR : 1; /*!< [4..4] CNTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PERR : 1; /*!< [5..5] PERR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t REPR : 1; /*!< [6..6] REPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPAR : 1; /*!< [7..7] CMPAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPBR : 1; /*!< [8..8] CMPBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPCR : 1; /*!< [9..9] CMPCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPDR : 1; /*!< [10..10] CMPDR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPAR : 1; /*!< [11..11] CAPAR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t CAPBR : 1; /*!< [12..12] CAPBR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t DTR : 1; /*!< [13..13] DTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETAR : 1; /*!< [14..14] SETAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRAR : 1; /*!< [15..15] CLRAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETBR : 1; /*!< [16..16] SETBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRBR : 1; /*!< [17..17] CLRBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR0 : 1; /*!< [18..18] EEFR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR1 : 1; /*!< [19..19] EEFR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR2 : 1; /*!< [20..20] EEFR2 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTR : 1; /*!< [21..21] RSTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTER : 1; /*!< [22..22] RSTER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CHPR : 1; /*!< [23..23] CHPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACR : 1; /*!< [24..24] CAPACR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACER : 1; /*!< [25..25] CAPACER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCR : 1; /*!< [26..26] CAPBCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCER : 1; /*!< [27..27] CAPBCER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t OUTR : 1; /*!< [28..28] OUTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t FLTR : 1; /*!< [29..29] FLTR 寄存器支持 System DMA 写入DMADR并更新 */
+ uint32_t : 2;
+ } DMAUR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+
+ struct {
+ __IOM uint32_t DMADR : 32; /*!< [31..0] System DMA 数据地址 */
+ } DMADR_b;
+ } ;
+} HRPWM_SLV4_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV5 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV5 (HRPWM_SLV5)
+ */
+
+typedef struct { /*!< (@ 0x4003B600) HRPWM_SLV5 Structure */
+
+ union {
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+
+ struct {
+ __IOM uint32_t CKPSC : 3; /*!< [2..0] PWMx 时钟预分频比 */
+ __IOM uint32_t CONT : 1; /*!< [3..3] PWMx 连续模式 */
+ __IOM uint32_t RETRIG : 1; /*!< [4..4] PWMx 可重触发模式 */
+ __IOM uint32_t HALF : 1; /*!< [5..5] PWMx Half 模式 */
+ __IOM uint32_t INTLVD : 2; /*!< [7..6] PWMx Interleaved 模式 */
+ __IOM uint32_t PSHPLL : 1; /*!< [8..8] PWMx Push-pull 模式 */
+ __IOM uint32_t RSYNCU : 1; /*!< [9..9] PWMx 重同步更新 */
+ __IOM uint32_t SYNCRST : 1; /*!< [10..10] 同步事件复位 PWMx */
+ __IOM uint32_t SYNCSTRT : 1; /*!< [11..11] 同步事件启动 PWMx */
+ uint32_t : 4;
+ __IOM uint32_t DELCMPB : 2; /*!< [17..16] PWMx CMPB Auto-Delayed 模式 */
+ __IOM uint32_t DELCMPD : 2; /*!< [19..18] PWMx CMPD Auto-Delayed 模式 */
+ __IOM uint32_t TRGHLF : 1; /*!< [20..20] PWMx Triggered-half 模式 */
+ __IOM uint32_t GTCMPA : 1; /*!< [21..21] PWMx CMPA Greater Than 模式 */
+ __IOM uint32_t GTCMPC : 1; /*!< [22..22] PWMx CMPC Greater Than 模式 */
+ __IOM uint32_t DACSYNC : 2; /*!< [24..23] DAC Trigger同步 */
+ __IOM uint32_t PREEN : 1; /*!< [25..25] PWMx 预加载使能 */
+ __IOM uint32_t UPDRST : 1; /*!< [26..26] PWMx Reset 更新 */
+ __IOM uint32_t UPDREP : 1; /*!< [27..27] PWMx Repetition 更新 */
+ __IOM uint32_t UPDGAT : 4; /*!< [31..28] 更新门控 */
+ } PWMCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+
+ struct {
+ __IOM uint32_t DCDE : 1; /*!< [0..0] DAC Reset／Step Trigger 使能 */
+ __IOM uint32_t DCDS : 1; /*!< [1..1] DAC Step Trigger 来源 */
+ __IOM uint32_t DCDR : 1; /*!< [2..2] DAC Reset Trigger 来源 */
+ __IOM uint32_t CAPAM : 1; /*!< [3..3] Capture A 模式选择 */
+ __IOM uint32_t UDM : 1; /*!< [4..4] Up-Down 模式选择 */
+ __IOM uint32_t CAPBM : 1; /*!< [5..5] Capture B 模式选择 */
+ __IOM uint32_t ROM : 2; /*!< [7..6] Roll-Over 模式选择 */
+ __IOM uint32_t OUTROM : 2; /*!< [9..8] 输出 Roll-Over 模式选择 */
+ __IOM uint32_t ADROM : 2; /*!< [11..10] ADC Roll-Over 模式选择 */
+ __IOM uint32_t EEVROM : 2; /*!< [13..12] 事件 Roll-Over 模式选择 */
+ __IOM uint32_t FLTROM : 2; /*!< [15..14] 故障 Roll-Over 模式选择 */
+ __IOM uint32_t MUPD : 1; /*!< [16..16] Master PWM 更新 */
+ __IOM uint32_t UPD0 : 1; /*!< [17..17] PWM0 更新 */
+ __IOM uint32_t UPD1 : 1; /*!< [18..18] PWM1 更新 */
+ __IOM uint32_t UPD2 : 1; /*!< [19..19] PWM2 更新 */
+ __IOM uint32_t UPD3 : 1; /*!< [20..20] PWM3 更新 */
+ __IOM uint32_t UPD4 : 1; /*!< [21..21] PWM4 更新 */
+ __IOM uint32_t UPD5 : 1; /*!< [22..22] PWM5 更新 */
+ __IOM uint32_t UPD6 : 1; /*!< [23..23] PWM6 更新 */
+ __IOM uint32_t UPD7 : 1; /*!< [24..24] PWM7 更新 */
+ uint32_t : 6;
+ __IOM uint32_t BDMADIS : 1; /*!< [31..31] PWMx Burst DMA 禁止 */
+ } PWMCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t CMPA : 1; /*!< [0..0] Compare A 中断标志 */
+ __IOM uint32_t CMPB : 1; /*!< [1..1] Compare B 中断标志 */
+ __IOM uint32_t CMPC : 1; /*!< [2..2] Compare C 中断标志 */
+ __IOM uint32_t CMPD : 1; /*!< [3..3] Compare D 中断标志 */
+ __IOM uint32_t PER : 1; /*!< [4..4] Roll-Over 中断标志 */
+ __IOM uint32_t UPD : 1; /*!< [5..5] Update 中断标志 */
+ __IOM uint32_t SETA : 1; /*!< [6..6] Out A Set 中断标志 */
+ __IOM uint32_t CLRA : 1; /*!< [7..7] Out A Clear 中断标志 */
+ __IOM uint32_t SETB : 1; /*!< [8..8] Out B Set 中断标志 */
+ __IOM uint32_t CLRB : 1; /*!< [9..9] Out B Clear 中断标志 */
+ __IOM uint32_t RST : 1; /*!< [10..10] Reset 中断标志 */
+ __IOM uint32_t REP : 1; /*!< [11..11] Repetition 中断标志 */
+ __IOM uint32_t CAPA : 1; /*!< [12..12] Capture A 中断标志 */
+ __IOM uint32_t CAPB : 1; /*!< [13..13] Capture B 中断标志 */
+ __IOM uint32_t DLYPRT : 1; /*!< [14..14] Delayed Protection 中断标志 */
+ uint32_t : 1;
+ __IM uint32_t CPPSTA : 1; /*!< [16..16] PushPull 当前状态 */
+ __IM uint32_t IPPSTA : 1; /*!< [17..17] PushPull 输出状态（延迟空闲/均衡空闲保护发生时） */
+ __IM uint32_t OUTASTA : 1; /*!< [18..18] OUTA 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTBSTA : 1; /*!< [19..19] OUTB 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTA : 1; /*!< [20..20] OUTA 当前输出（输出级之前） */
+ __IM uint32_t OUTB : 1; /*!< [21..21] OUTB 当前输出（输出级之前） */
+ uint32_t : 10;
+ } PWMISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t CMPAIE : 1; /*!< [0..0] Compare A 中断使能 */
+ __IOM uint32_t CMPBIE : 1; /*!< [1..1] Compare B 中断使能 */
+ __IOM uint32_t CMPCIE : 1; /*!< [2..2] Compare C 中断使能 */
+ __IOM uint32_t CMPDIE : 1; /*!< [3..3] Compare D 中断使能 */
+ __IOM uint32_t PERIE : 1; /*!< [4..4] Roll-Over 中断使能 */
+ __IOM uint32_t UPDIE : 1; /*!< [5..5] Update 中断使能 */
+ __IOM uint32_t SETAIE : 1; /*!< [6..6] Out A Set 中断使能 */
+ __IOM uint32_t CLRAIE : 1; /*!< [7..7] Out A Clear 中断使能 */
+ __IOM uint32_t SETBIE : 1; /*!< [8..8] Out B Set 中断使能 */
+ __IOM uint32_t CLRBIE : 1; /*!< [9..9] Out B Clear 中断使能 */
+ __IOM uint32_t RSTIE : 1; /*!< [10..10] Reset 中断使能 */
+ __IOM uint32_t REPIE : 1; /*!< [11..11] Repetition 中断使能 */
+ __IOM uint32_t CAPAIE : 1; /*!< [12..12] Capture A 中断使能 */
+ __IOM uint32_t CAPBIE : 1; /*!< [13..13] Capture B 中断使能 */
+ __IOM uint32_t DLYPRTIE : 1; /*!< [14..14] Delayed Protection 中断使能 */
+ uint32_t : 1;
+ __IOM uint32_t CMPADE : 1; /*!< [16..16] Compare A DMA使能 */
+ __IOM uint32_t CMPBDE : 1; /*!< [17..17] Compare B DMA使能 */
+ __IOM uint32_t CMPCDE : 1; /*!< [18..18] Compare C DMA使能 */
+ __IOM uint32_t CMPDDE : 1; /*!< [19..19] Compare D DMA使能 */
+ __IOM uint32_t PERDE : 1; /*!< [20..20] Roll-Over DMA使能 */
+ __IOM uint32_t UPDDE : 1; /*!< [21..21] Update DMA使能 */
+ __IOM uint32_t SETADE : 1; /*!< [22..22] Out A Set DMA使能 */
+ __IOM uint32_t CLRADE : 1; /*!< [23..23] Out A Clear DMA使能 */
+ __IOM uint32_t SETBDE : 1; /*!< [24..24] Out B Set DMA使能 */
+ __IOM uint32_t CLRBDE : 1; /*!< [25..25] Out B Clear DMA使能 */
+ __IOM uint32_t RSTDE : 1; /*!< [26..26] Reset DMA使能 */
+ __IOM uint32_t REPDE : 1; /*!< [27..27] Repetition DMA使能 */
+ __IOM uint32_t CAPADE : 1; /*!< [28..28] Capture A DMA使能 */
+ __IOM uint32_t CAPBDE : 1; /*!< [29..29] Capture B DMA使能 */
+ __IOM uint32_t DLYPRTDE : 1; /*!< [30..30] Delayed Protection DMA使能 */
+ uint32_t : 1;
+ } PWMDIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] PWMx Counter 数值 */
+ uint32_t : 2;
+ __IOM uint32_t CNTRD : 1; /*!< [18..18] PWMx Counter 读取 */
+ __IOM uint32_t CNTWR : 1; /*!< [19..19] PWMx Counter 写入 */
+ uint32_t : 12;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+
+ struct {
+ __IOM uint32_t PER : 16; /*!< [15..0] PWMx Period 数值 */
+ uint32_t : 16;
+ } PERR_b;
+ } ;
+
+ union {
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] PWMx Repetition Period 数值 */
+ uint32_t : 24;
+ } REPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+
+ struct {
+ __IOM uint32_t CMPA : 16; /*!< [15..0] PWMx Compare A 数值 */
+ uint32_t : 16;
+ } CMPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+
+ struct {
+ __IOM uint32_t CMPB : 16; /*!< [15..0] PWMx Compare B 数值 */
+ uint32_t : 16;
+ } CMPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+
+ struct {
+ __IOM uint32_t CMPC : 16; /*!< [15..0] PWMx Compare C 数值 */
+ uint32_t : 16;
+ } CMPCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+
+ struct {
+ __IOM uint32_t CMPD : 16; /*!< [15..0] PWMx Compare D 数值 */
+ uint32_t : 16;
+ } CMPDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+
+ struct {
+ __IM uint32_t CAPA : 16; /*!< [15..0] 捕获 A 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 A 方向 */
+ uint32_t : 15;
+ } CAPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+
+ struct {
+ __IM uint32_t CAPB : 16; /*!< [15..0] 捕获 B 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 B 方向 */
+ uint32_t : 15;
+ } CAPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+
+ struct {
+ __IOM uint32_t DTR : 12; /*!< [11..0] 上升沿死区时间 */
+ __IOM uint32_t SDTR : 1; /*!< [12..12] 上升沿死区符号 */
+ uint32_t : 3;
+ __IOM uint32_t DTF : 12; /*!< [27..16] 下降沿死区时间 */
+ __IOM uint32_t SDTF : 1; /*!< [28..28] 下降沿死区符号 */
+ uint32_t : 3;
+ } DTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入有效状态 */
+ uint32_t : 9;
+ } SETAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入无效状态 */
+ uint32_t : 9;
+ } CLRAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入有效状态 */
+ uint32_t : 9;
+ } SETBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入无效状态 */
+ uint32_t : 9;
+ } CLRBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+
+ struct {
+ __IOM uint32_t EE0LTCH : 1; /*!< [0..0] Event 0 锁存位 */
+ __IOM uint32_t EE0FLTR : 4; /*!< [4..1] Event 0 滤波位 */
+ __IOM uint32_t EE1LTCH : 1; /*!< [5..5] Event 1 锁存位 */
+ __IOM uint32_t EE1FLTR : 4; /*!< [9..6] Event 1 滤波位 */
+ __IOM uint32_t EE2LTCH : 1; /*!< [10..10] Event 2 锁存位 */
+ __IOM uint32_t EE2FLTR : 4; /*!< [14..11] Event 2 滤波位 */
+ __IOM uint32_t EE3LTCH : 1; /*!< [15..15] Event 3 锁存位 */
+ __IOM uint32_t EE3FLTR : 4; /*!< [19..16] Event 3 滤波位 */
+ __IOM uint32_t EE4LTCH : 1; /*!< [20..20] Event 4 锁存位 */
+ __IOM uint32_t EE4FLTR : 4; /*!< [24..21] Event 4 滤波位 */
+ uint32_t : 7;
+ } EEFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+
+ struct {
+ __IOM uint32_t EE5LTCH : 1; /*!< [0..0] Event 5 锁存位 */
+ __IOM uint32_t EE5FLTR : 4; /*!< [4..1] Event 5 滤波位 */
+ __IOM uint32_t EE6LTCH : 1; /*!< [5..5] Event 6 锁存位 */
+ __IOM uint32_t EE6FLTR : 4; /*!< [9..6] Event 6 滤波位 */
+ __IOM uint32_t EE7LTCH : 1; /*!< [10..10] Event 7 锁存位 */
+ __IOM uint32_t EE7FLTR : 4; /*!< [14..11] Event 7 滤波位 */
+ __IOM uint32_t EE8LTCH : 1; /*!< [15..15] Event 8 锁存位 */
+ __IOM uint32_t EE8FLTR : 4; /*!< [19..16] Event 8 滤波位 */
+ __IOM uint32_t EE9LTCH : 1; /*!< [20..20] Event 9 锁存位 */
+ __IOM uint32_t EE9FLTR : 4; /*!< [24..21] Event 9 滤波位 */
+ uint32_t : 7;
+ } EEFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+
+ struct {
+ __IOM uint32_t EEVACE : 1; /*!< [0..0] Event A 计数使能 */
+ __IOM uint32_t EEVACRES : 1; /*!< [1..1] Event A 计数复位 */
+ __IOM uint32_t EEVARSTM : 1; /*!< [2..2] Event A计数复位模式 */
+ uint32_t : 1;
+ __IOM uint32_t EEVASEL : 4; /*!< [7..4] Event A 来源选择 */
+ __IOM uint32_t EEVACNT : 6; /*!< [13..8] Event A 计数阈值 */
+ uint32_t : 18;
+ } EEFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+
+ struct {
+ __IOM uint32_t SLV4CMPA : 1; /*!< [0..0] PWM4 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [1..1] Master PWM Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [2..2] Master PWM Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [3..3] Master PWM Compare C事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [4..4] Master PWM Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTPER : 1; /*!< [5..5] Master PWM Period事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [6..6] PWMx Event 0事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [7..7] PWMx Event 1事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [8..8] PWMx Event 2事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [9..9] PWMx Event 3事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [10..10] PWMx Event 4事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [11..11] PWMx Event 5事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [12..12] PWMx Event 6事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [13..13] PWMx Event 7事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [14..14] PWMx Event 8事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [15..15] PWMx Event 9事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVUPD : 1; /*!< [16..16] PWMx Update事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPB : 1; /*!< [17..17] PWMx Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPD : 1; /*!< [18..18] PWMx Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [19..19] PWM0 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [20..20] PWM0 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPD : 1; /*!< [21..21] PWM0 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [22..22] PWM1 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [23..23] PWM1 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPD : 1; /*!< [24..24] PWM1 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [25..25] PWM2 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [26..26] PWM2 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPD : 1; /*!< [27..27] PWM2 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [28..28] PWM3 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [29..29] PWM3 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPD : 1; /*!< [30..30] PWM3 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [31..31] PWM4 Compare B事件使 PWMx 计数器复位 */
+ } RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6CMPA : 1; /*!< [0..0] PWM6 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [1..1] PWM6 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPD : 1; /*!< [2..2] PWM6 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [3..3] PWM7 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [4..4] PWM7 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPD : 1; /*!< [5..5] PWM7 Compare D事件使 PWMx 计数器复位 */
+ uint32_t : 26;
+ } RSTER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+
+ struct {
+ __IOM uint32_t CARFRQ : 4; /*!< [3..0] PWMx 载波频率值 */
+ uint32_t : 2;
+ __IOM uint32_t CARDTY : 3; /*!< [8..6] PWMx 斩波占空比值 */
+ uint32_t : 3;
+ __IOM uint32_t STRPW : 4; /*!< [15..12] PWMx 启动脉冲宽度 */
+ uint32_t : 16;
+ } CHPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture A 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [20..20] PWM2 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [21..21] PWM2 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [24..24] PWM3 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [25..25] PWM3 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [26..26] PWM3 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [27..27] PWM3 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [28..28] PWM4 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [29..29] PWM4 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [30..30] PWM4 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [31..31] PWM4 Compare B 事件触发 Capture A 事件 */
+ } CAPACR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture A 事件 */
+ uint32_t : 24;
+ } CAPACER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture B 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [20..20] PWM2 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [21..21] PWM2 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [24..24] PWM3 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [25..25] PWM3 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [26..26] PWM3 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [27..27] PWM3 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [28..28] PWM4 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [29..29] PWM4 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [30..30] PWM4 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [31..31] PWM4 Compare B 事件触发 Capture B 事件 */
+ } CAPBCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV6SETA : 1; /*!< [0..0] PWM6 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [1..1] PWM6 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [2..2] PWM6 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [3..3] PWM6 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture B 事件 */
+ uint32_t : 24;
+ } CAPBCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+
+ struct {
+ __IOM uint32_t POLA : 1; /*!< [0..0] 输出 A 极性 */
+ __IOM uint32_t FAULTA : 2; /*!< [2..1] 输出 A 故障电平 */
+ __IOM uint32_t IDLESA : 1; /*!< [3..3] 输出 A 空闲状态 */
+ __IOM uint32_t CHPA : 1; /*!< [4..4] 输出 A 斩波使能 */
+ __IOM uint32_t IDLEMA : 1; /*!< [5..5] 输出 A 空闲模式 */
+ __IOM uint32_t DIDLA : 1; /*!< [6..6] 输出 A 空闲模式死区使能 */
+ uint32_t : 9;
+ __IOM uint32_t POLB : 1; /*!< [16..16] 输出 B 极性 */
+ __IOM uint32_t FAULTB : 2; /*!< [18..17] 输出 B 故障状态 */
+ __IOM uint32_t IDLESB : 1; /*!< [19..19] 输出 B 空闲状态 */
+ __IOM uint32_t CHPB : 1; /*!< [20..20] 输出 B 斩波使能 */
+ __IOM uint32_t IDLEMB : 1; /*!< [21..21] 输出 B 空闲模式 */
+ __IOM uint32_t DIDLB : 1; /*!< [22..22] 输出 B 空闲模式死区使能 */
+ uint32_t : 2;
+ __IOM uint32_t BIAR : 1; /*!< [25..25] 均衡空闲自动恢复 */
+ uint32_t : 1;
+ __IOM uint32_t DLYPRT : 3; /*!< [29..27] 延迟保护机制 */
+ __IOM uint32_t DLYPRTEN : 1; /*!< [30..30] 延迟保护使能 */
+ __IOM uint32_t DTEN : 1; /*!< [31..31] 死区使能 */
+ } OUTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+
+ struct {
+ __IOM uint32_t FLT0EN : 1; /*!< [0..0] Fault 0 使能 */
+ __IOM uint32_t FLT1EN : 1; /*!< [1..1] Fault 1 使能 */
+ __IOM uint32_t FLT2EN : 1; /*!< [2..2] Fault 2 使能 */
+ __IOM uint32_t FLT3EN : 1; /*!< [3..3] Fault 3 使能 */
+ __IOM uint32_t FLT4EN : 1; /*!< [4..4] Fault 4 使能 */
+ __IOM uint32_t FLT5EN : 1; /*!< [5..5] Fault 5 使能 */
+ __IOM uint32_t FLT6EN : 1; /*!< [6..6] Fault 6 使能 */
+ __IOM uint32_t FLT7EN : 1; /*!< [7..7] Fault 7 使能 */
+ uint32_t : 24;
+ } FLTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+
+ struct {
+ __IOM uint32_t PWMCR0 : 1; /*!< [0..0] PWMCR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMCR1 : 1; /*!< [1..1] PWMCR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMISR : 1; /*!< [2..2] PWMISR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMDIER : 1; /*!< [3..3] PWMDIER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CNTR : 1; /*!< [4..4] CNTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PERR : 1; /*!< [5..5] PERR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t REPR : 1; /*!< [6..6] REPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPAR : 1; /*!< [7..7] CMPAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPBR : 1; /*!< [8..8] CMPBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPCR : 1; /*!< [9..9] CMPCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPDR : 1; /*!< [10..10] CMPDR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPAR : 1; /*!< [11..11] CAPAR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t CAPBR : 1; /*!< [12..12] CAPBR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t DTR : 1; /*!< [13..13] DTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETAR : 1; /*!< [14..14] SETAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRAR : 1; /*!< [15..15] CLRAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETBR : 1; /*!< [16..16] SETBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRBR : 1; /*!< [17..17] CLRBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR0 : 1; /*!< [18..18] EEFR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR1 : 1; /*!< [19..19] EEFR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR2 : 1; /*!< [20..20] EEFR2 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTR : 1; /*!< [21..21] RSTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTER : 1; /*!< [22..22] RSTER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CHPR : 1; /*!< [23..23] CHPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACR : 1; /*!< [24..24] CAPACR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACER : 1; /*!< [25..25] CAPACER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCR : 1; /*!< [26..26] CAPBCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCER : 1; /*!< [27..27] CAPBCER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t OUTR : 1; /*!< [28..28] OUTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t FLTR : 1; /*!< [29..29] FLTR 寄存器支持 System DMA 写入DMADR并更新 */
+ uint32_t : 2;
+ } DMAUR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+
+ struct {
+ __IOM uint32_t DMADR : 32; /*!< [31..0] System DMA 数据地址 */
+ } DMADR_b;
+ } ;
+} HRPWM_SLV5_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV6 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV6 (HRPWM_SLV6)
+ */
+
+typedef struct { /*!< (@ 0x4003B700) HRPWM_SLV6 Structure */
+
+ union {
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+
+ struct {
+ __IOM uint32_t CKPSC : 3; /*!< [2..0] PWMx 时钟预分频比 */
+ __IOM uint32_t CONT : 1; /*!< [3..3] PWMx 连续模式 */
+ __IOM uint32_t RETRIG : 1; /*!< [4..4] PWMx 可重触发模式 */
+ __IOM uint32_t HALF : 1; /*!< [5..5] PWMx Half 模式 */
+ __IOM uint32_t INTLVD : 2; /*!< [7..6] PWMx Interleaved 模式 */
+ __IOM uint32_t PSHPLL : 1; /*!< [8..8] PWMx Push-pull 模式 */
+ __IOM uint32_t RSYNCU : 1; /*!< [9..9] PWMx 重同步更新 */
+ __IOM uint32_t SYNCRST : 1; /*!< [10..10] 同步事件复位 PWMx */
+ __IOM uint32_t SYNCSTRT : 1; /*!< [11..11] 同步事件启动 PWMx */
+ uint32_t : 4;
+ __IOM uint32_t DELCMPB : 2; /*!< [17..16] PWMx CMPB Auto-Delayed 模式 */
+ __IOM uint32_t DELCMPD : 2; /*!< [19..18] PWMx CMPD Auto-Delayed 模式 */
+ __IOM uint32_t TRGHLF : 1; /*!< [20..20] PWMx Triggered-half 模式 */
+ __IOM uint32_t GTCMPA : 1; /*!< [21..21] PWMx CMPA Greater Than 模式 */
+ __IOM uint32_t GTCMPC : 1; /*!< [22..22] PWMx CMPC Greater Than 模式 */
+ __IOM uint32_t DACSYNC : 2; /*!< [24..23] DAC Trigger同步 */
+ __IOM uint32_t PREEN : 1; /*!< [25..25] PWMx 预加载使能 */
+ __IOM uint32_t UPDRST : 1; /*!< [26..26] PWMx Reset 更新 */
+ __IOM uint32_t UPDREP : 1; /*!< [27..27] PWMx Repetition 更新 */
+ __IOM uint32_t UPDGAT : 4; /*!< [31..28] 更新门控 */
+ } PWMCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+
+ struct {
+ __IOM uint32_t DCDE : 1; /*!< [0..0] DAC Reset／Step Trigger 使能 */
+ __IOM uint32_t DCDS : 1; /*!< [1..1] DAC Step Trigger 来源 */
+ __IOM uint32_t DCDR : 1; /*!< [2..2] DAC Reset Trigger 来源 */
+ __IOM uint32_t CAPAM : 1; /*!< [3..3] Capture A 模式选择 */
+ __IOM uint32_t UDM : 1; /*!< [4..4] Up-Down 模式选择 */
+ __IOM uint32_t CAPBM : 1; /*!< [5..5] Capture B 模式选择 */
+ __IOM uint32_t ROM : 2; /*!< [7..6] Roll-Over 模式选择 */
+ __IOM uint32_t OUTROM : 2; /*!< [9..8] 输出 Roll-Over 模式选择 */
+ __IOM uint32_t ADROM : 2; /*!< [11..10] ADC Roll-Over 模式选择 */
+ __IOM uint32_t EEVROM : 2; /*!< [13..12] 事件 Roll-Over 模式选择 */
+ __IOM uint32_t FLTROM : 2; /*!< [15..14] 故障 Roll-Over 模式选择 */
+ __IOM uint32_t MUPD : 1; /*!< [16..16] Master PWM 更新 */
+ __IOM uint32_t UPD0 : 1; /*!< [17..17] PWM0 更新 */
+ __IOM uint32_t UPD1 : 1; /*!< [18..18] PWM1 更新 */
+ __IOM uint32_t UPD2 : 1; /*!< [19..19] PWM2 更新 */
+ __IOM uint32_t UPD3 : 1; /*!< [20..20] PWM3 更新 */
+ __IOM uint32_t UPD4 : 1; /*!< [21..21] PWM4 更新 */
+ __IOM uint32_t UPD5 : 1; /*!< [22..22] PWM5 更新 */
+ __IOM uint32_t UPD6 : 1; /*!< [23..23] PWM6 更新 */
+ __IOM uint32_t UPD7 : 1; /*!< [24..24] PWM7 更新 */
+ uint32_t : 6;
+ __IOM uint32_t BDMADIS : 1; /*!< [31..31] PWMx Burst DMA 禁止 */
+ } PWMCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t CMPA : 1; /*!< [0..0] Compare A 中断标志 */
+ __IOM uint32_t CMPB : 1; /*!< [1..1] Compare B 中断标志 */
+ __IOM uint32_t CMPC : 1; /*!< [2..2] Compare C 中断标志 */
+ __IOM uint32_t CMPD : 1; /*!< [3..3] Compare D 中断标志 */
+ __IOM uint32_t PER : 1; /*!< [4..4] Roll-Over 中断标志 */
+ __IOM uint32_t UPD : 1; /*!< [5..5] Update 中断标志 */
+ __IOM uint32_t SETA : 1; /*!< [6..6] Out A Set 中断标志 */
+ __IOM uint32_t CLRA : 1; /*!< [7..7] Out A Clear 中断标志 */
+ __IOM uint32_t SETB : 1; /*!< [8..8] Out B Set 中断标志 */
+ __IOM uint32_t CLRB : 1; /*!< [9..9] Out B Clear 中断标志 */
+ __IOM uint32_t RST : 1; /*!< [10..10] Reset 中断标志 */
+ __IOM uint32_t REP : 1; /*!< [11..11] Repetition 中断标志 */
+ __IOM uint32_t CAPA : 1; /*!< [12..12] Capture A 中断标志 */
+ __IOM uint32_t CAPB : 1; /*!< [13..13] Capture B 中断标志 */
+ __IOM uint32_t DLYPRT : 1; /*!< [14..14] Delayed Protection 中断标志 */
+ uint32_t : 1;
+ __IM uint32_t CPPSTA : 1; /*!< [16..16] PushPull 当前状态 */
+ __IM uint32_t IPPSTA : 1; /*!< [17..17] PushPull 输出状态（延迟空闲/均衡空闲保护发生时） */
+ __IM uint32_t OUTASTA : 1; /*!< [18..18] OUTA 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTBSTA : 1; /*!< [19..19] OUTB 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTA : 1; /*!< [20..20] OUTA 当前输出（输出级之前） */
+ __IM uint32_t OUTB : 1; /*!< [21..21] OUTB 当前输出（输出级之前） */
+ uint32_t : 10;
+ } PWMISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t CMPAIE : 1; /*!< [0..0] Compare A 中断使能 */
+ __IOM uint32_t CMPBIE : 1; /*!< [1..1] Compare B 中断使能 */
+ __IOM uint32_t CMPCIE : 1; /*!< [2..2] Compare C 中断使能 */
+ __IOM uint32_t CMPDIE : 1; /*!< [3..3] Compare D 中断使能 */
+ __IOM uint32_t PERIE : 1; /*!< [4..4] Roll-Over 中断使能 */
+ __IOM uint32_t UPDIE : 1; /*!< [5..5] Update 中断使能 */
+ __IOM uint32_t SETAIE : 1; /*!< [6..6] Out A Set 中断使能 */
+ __IOM uint32_t CLRAIE : 1; /*!< [7..7] Out A Clear 中断使能 */
+ __IOM uint32_t SETBIE : 1; /*!< [8..8] Out B Set 中断使能 */
+ __IOM uint32_t CLRBIE : 1; /*!< [9..9] Out B Clear 中断使能 */
+ __IOM uint32_t RSTIE : 1; /*!< [10..10] Reset 中断使能 */
+ __IOM uint32_t REPIE : 1; /*!< [11..11] Repetition 中断使能 */
+ __IOM uint32_t CAPAIE : 1; /*!< [12..12] Capture A 中断使能 */
+ __IOM uint32_t CAPBIE : 1; /*!< [13..13] Capture B 中断使能 */
+ __IOM uint32_t DLYPRTIE : 1; /*!< [14..14] Delayed Protection 中断使能 */
+ uint32_t : 1;
+ __IOM uint32_t CMPADE : 1; /*!< [16..16] Compare A DMA使能 */
+ __IOM uint32_t CMPBDE : 1; /*!< [17..17] Compare B DMA使能 */
+ __IOM uint32_t CMPCDE : 1; /*!< [18..18] Compare C DMA使能 */
+ __IOM uint32_t CMPDDE : 1; /*!< [19..19] Compare D DMA使能 */
+ __IOM uint32_t PERDE : 1; /*!< [20..20] Roll-Over DMA使能 */
+ __IOM uint32_t UPDDE : 1; /*!< [21..21] Update DMA使能 */
+ __IOM uint32_t SETADE : 1; /*!< [22..22] Out A Set DMA使能 */
+ __IOM uint32_t CLRADE : 1; /*!< [23..23] Out A Clear DMA使能 */
+ __IOM uint32_t SETBDE : 1; /*!< [24..24] Out B Set DMA使能 */
+ __IOM uint32_t CLRBDE : 1; /*!< [25..25] Out B Clear DMA使能 */
+ __IOM uint32_t RSTDE : 1; /*!< [26..26] Reset DMA使能 */
+ __IOM uint32_t REPDE : 1; /*!< [27..27] Repetition DMA使能 */
+ __IOM uint32_t CAPADE : 1; /*!< [28..28] Capture A DMA使能 */
+ __IOM uint32_t CAPBDE : 1; /*!< [29..29] Capture B DMA使能 */
+ __IOM uint32_t DLYPRTDE : 1; /*!< [30..30] Delayed Protection DMA使能 */
+ uint32_t : 1;
+ } PWMDIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] PWMx Counter 数值 */
+ uint32_t : 2;
+ __IOM uint32_t CNTRD : 1; /*!< [18..18] PWMx Counter 读取 */
+ __IOM uint32_t CNTWR : 1; /*!< [19..19] PWMx Counter 写入 */
+ uint32_t : 12;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+
+ struct {
+ __IOM uint32_t PER : 16; /*!< [15..0] PWMx Period 数值 */
+ uint32_t : 16;
+ } PERR_b;
+ } ;
+
+ union {
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] PWMx Repetition Period 数值 */
+ uint32_t : 24;
+ } REPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+
+ struct {
+ __IOM uint32_t CMPA : 16; /*!< [15..0] PWMx Compare A 数值 */
+ uint32_t : 16;
+ } CMPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+
+ struct {
+ __IOM uint32_t CMPB : 16; /*!< [15..0] PWMx Compare B 数值 */
+ uint32_t : 16;
+ } CMPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+
+ struct {
+ __IOM uint32_t CMPC : 16; /*!< [15..0] PWMx Compare C 数值 */
+ uint32_t : 16;
+ } CMPCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+
+ struct {
+ __IOM uint32_t CMPD : 16; /*!< [15..0] PWMx Compare D 数值 */
+ uint32_t : 16;
+ } CMPDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+
+ struct {
+ __IM uint32_t CAPA : 16; /*!< [15..0] 捕获 A 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 A 方向 */
+ uint32_t : 15;
+ } CAPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+
+ struct {
+ __IM uint32_t CAPB : 16; /*!< [15..0] 捕获 B 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 B 方向 */
+ uint32_t : 15;
+ } CAPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+
+ struct {
+ __IOM uint32_t DTR : 12; /*!< [11..0] 上升沿死区时间 */
+ __IOM uint32_t SDTR : 1; /*!< [12..12] 上升沿死区符号 */
+ uint32_t : 3;
+ __IOM uint32_t DTF : 12; /*!< [27..16] 下降沿死区时间 */
+ __IOM uint32_t SDTF : 1; /*!< [28..28] 下降沿死区符号 */
+ uint32_t : 3;
+ } DTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入有效状态 */
+ uint32_t : 9;
+ } SETAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入无效状态 */
+ uint32_t : 9;
+ } CLRAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入有效状态 */
+ uint32_t : 9;
+ } SETBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入无效状态 */
+ uint32_t : 9;
+ } CLRBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+
+ struct {
+ __IOM uint32_t EE0LTCH : 1; /*!< [0..0] Event 0 锁存位 */
+ __IOM uint32_t EE0FLTR : 4; /*!< [4..1] Event 0 滤波位 */
+ __IOM uint32_t EE1LTCH : 1; /*!< [5..5] Event 1 锁存位 */
+ __IOM uint32_t EE1FLTR : 4; /*!< [9..6] Event 1 滤波位 */
+ __IOM uint32_t EE2LTCH : 1; /*!< [10..10] Event 2 锁存位 */
+ __IOM uint32_t EE2FLTR : 4; /*!< [14..11] Event 2 滤波位 */
+ __IOM uint32_t EE3LTCH : 1; /*!< [15..15] Event 3 锁存位 */
+ __IOM uint32_t EE3FLTR : 4; /*!< [19..16] Event 3 滤波位 */
+ __IOM uint32_t EE4LTCH : 1; /*!< [20..20] Event 4 锁存位 */
+ __IOM uint32_t EE4FLTR : 4; /*!< [24..21] Event 4 滤波位 */
+ uint32_t : 7;
+ } EEFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+
+ struct {
+ __IOM uint32_t EE5LTCH : 1; /*!< [0..0] Event 5 锁存位 */
+ __IOM uint32_t EE5FLTR : 4; /*!< [4..1] Event 5 滤波位 */
+ __IOM uint32_t EE6LTCH : 1; /*!< [5..5] Event 6 锁存位 */
+ __IOM uint32_t EE6FLTR : 4; /*!< [9..6] Event 6 滤波位 */
+ __IOM uint32_t EE7LTCH : 1; /*!< [10..10] Event 7 锁存位 */
+ __IOM uint32_t EE7FLTR : 4; /*!< [14..11] Event 7 滤波位 */
+ __IOM uint32_t EE8LTCH : 1; /*!< [15..15] Event 8 锁存位 */
+ __IOM uint32_t EE8FLTR : 4; /*!< [19..16] Event 8 滤波位 */
+ __IOM uint32_t EE9LTCH : 1; /*!< [20..20] Event 9 锁存位 */
+ __IOM uint32_t EE9FLTR : 4; /*!< [24..21] Event 9 滤波位 */
+ uint32_t : 7;
+ } EEFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+
+ struct {
+ __IOM uint32_t EEVACE : 1; /*!< [0..0] Event A 计数使能 */
+ __IOM uint32_t EEVACRES : 1; /*!< [1..1] Event A 计数复位 */
+ __IOM uint32_t EEVARSTM : 1; /*!< [2..2] Event A计数复位模式 */
+ uint32_t : 1;
+ __IOM uint32_t EEVASEL : 4; /*!< [7..4] Event A 来源选择 */
+ __IOM uint32_t EEVACNT : 6; /*!< [13..8] Event A 计数阈值 */
+ uint32_t : 18;
+ } EEFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+
+ struct {
+ __IOM uint32_t SLV4CMPA : 1; /*!< [0..0] PWM4 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [1..1] Master PWM Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [2..2] Master PWM Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [3..3] Master PWM Compare C事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [4..4] Master PWM Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTPER : 1; /*!< [5..5] Master PWM Period事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [6..6] PWMx Event 0事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [7..7] PWMx Event 1事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [8..8] PWMx Event 2事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [9..9] PWMx Event 3事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [10..10] PWMx Event 4事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [11..11] PWMx Event 5事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [12..12] PWMx Event 6事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [13..13] PWMx Event 7事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [14..14] PWMx Event 8事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [15..15] PWMx Event 9事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVUPD : 1; /*!< [16..16] PWMx Update事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPB : 1; /*!< [17..17] PWMx Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPD : 1; /*!< [18..18] PWMx Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [19..19] PWM0 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [20..20] PWM0 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPD : 1; /*!< [21..21] PWM0 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [22..22] PWM1 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [23..23] PWM1 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPD : 1; /*!< [24..24] PWM1 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [25..25] PWM2 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [26..26] PWM2 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPD : 1; /*!< [27..27] PWM2 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [28..28] PWM3 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [29..29] PWM3 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPD : 1; /*!< [30..30] PWM3 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [31..31] PWM4 Compare B事件使 PWMx 计数器复位 */
+ } RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+
+ struct {
+ __IOM uint32_t SLV5CMPA : 1; /*!< [0..0] PWM5 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [1..1] PWM5 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV5CMPD : 1; /*!< [2..2] PWM5 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [3..3] PWM7 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [4..4] PWM7 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV7CMPD : 1; /*!< [5..5] PWM7 Compare D事件使 PWMx 计数器复位 */
+ uint32_t : 26;
+ } RSTER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+
+ struct {
+ __IOM uint32_t CARFRQ : 4; /*!< [3..0] PWMx 载波频率值 */
+ uint32_t : 2;
+ __IOM uint32_t CARDTY : 3; /*!< [8..6] PWMx 斩波占空比值 */
+ uint32_t : 3;
+ __IOM uint32_t STRPW : 4; /*!< [15..12] PWMx 启动脉冲宽度 */
+ uint32_t : 16;
+ } CHPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture A 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [20..20] PWM2 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [21..21] PWM2 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [24..24] PWM3 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [25..25] PWM3 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [26..26] PWM3 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [27..27] PWM3 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [28..28] PWM4 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [29..29] PWM4 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [30..30] PWM4 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [31..31] PWM4 Compare B 事件触发 Capture A 事件 */
+ } CAPACR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV5SETA : 1; /*!< [0..0] PWM5 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [1..1] PWM5 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [2..2] PWM5 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [3..3] PWM5 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture A 事件 */
+ uint32_t : 24;
+ } CAPACER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture B 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [20..20] PWM2 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [21..21] PWM2 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [24..24] PWM3 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [25..25] PWM3 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [26..26] PWM3 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [27..27] PWM3 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [28..28] PWM4 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [29..29] PWM4 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [30..30] PWM4 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [31..31] PWM4 Compare B 事件触发 Capture B 事件 */
+ } CAPBCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV5SETA : 1; /*!< [0..0] PWM5 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [1..1] PWM5 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [2..2] PWM5 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [3..3] PWM5 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7SETA : 1; /*!< [4..4] PWM7 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CLRA : 1; /*!< [5..5] PWM7 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPA : 1; /*!< [6..6] PWM7 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV7CMPB : 1; /*!< [7..7] PWM7 Compare B 事件触发 Capture B 事件 */
+ uint32_t : 24;
+ } CAPBCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+
+ struct {
+ __IOM uint32_t POLA : 1; /*!< [0..0] 输出 A 极性 */
+ __IOM uint32_t FAULTA : 2; /*!< [2..1] 输出 A 故障电平 */
+ __IOM uint32_t IDLESA : 1; /*!< [3..3] 输出 A 空闲状态 */
+ __IOM uint32_t CHPA : 1; /*!< [4..4] 输出 A 斩波使能 */
+ __IOM uint32_t IDLEMA : 1; /*!< [5..5] 输出 A 空闲模式 */
+ __IOM uint32_t DIDLA : 1; /*!< [6..6] 输出 A 空闲模式死区使能 */
+ uint32_t : 9;
+ __IOM uint32_t POLB : 1; /*!< [16..16] 输出 B 极性 */
+ __IOM uint32_t FAULTB : 2; /*!< [18..17] 输出 B 故障状态 */
+ __IOM uint32_t IDLESB : 1; /*!< [19..19] 输出 B 空闲状态 */
+ __IOM uint32_t CHPB : 1; /*!< [20..20] 输出 B 斩波使能 */
+ __IOM uint32_t IDLEMB : 1; /*!< [21..21] 输出 B 空闲模式 */
+ __IOM uint32_t DIDLB : 1; /*!< [22..22] 输出 B 空闲模式死区使能 */
+ uint32_t : 2;
+ __IOM uint32_t BIAR : 1; /*!< [25..25] 均衡空闲自动恢复 */
+ uint32_t : 1;
+ __IOM uint32_t DLYPRT : 3; /*!< [29..27] 延迟保护机制 */
+ __IOM uint32_t DLYPRTEN : 1; /*!< [30..30] 延迟保护使能 */
+ __IOM uint32_t DTEN : 1; /*!< [31..31] 死区使能 */
+ } OUTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+
+ struct {
+ __IOM uint32_t FLT0EN : 1; /*!< [0..0] Fault 0 使能 */
+ __IOM uint32_t FLT1EN : 1; /*!< [1..1] Fault 1 使能 */
+ __IOM uint32_t FLT2EN : 1; /*!< [2..2] Fault 2 使能 */
+ __IOM uint32_t FLT3EN : 1; /*!< [3..3] Fault 3 使能 */
+ __IOM uint32_t FLT4EN : 1; /*!< [4..4] Fault 4 使能 */
+ __IOM uint32_t FLT5EN : 1; /*!< [5..5] Fault 5 使能 */
+ __IOM uint32_t FLT6EN : 1; /*!< [6..6] Fault 6 使能 */
+ __IOM uint32_t FLT7EN : 1; /*!< [7..7] Fault 7 使能 */
+ uint32_t : 24;
+ } FLTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+
+ struct {
+ __IOM uint32_t PWMCR0 : 1; /*!< [0..0] PWMCR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMCR1 : 1; /*!< [1..1] PWMCR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMISR : 1; /*!< [2..2] PWMISR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMDIER : 1; /*!< [3..3] PWMDIER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CNTR : 1; /*!< [4..4] CNTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PERR : 1; /*!< [5..5] PERR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t REPR : 1; /*!< [6..6] REPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPAR : 1; /*!< [7..7] CMPAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPBR : 1; /*!< [8..8] CMPBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPCR : 1; /*!< [9..9] CMPCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPDR : 1; /*!< [10..10] CMPDR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPAR : 1; /*!< [11..11] CAPAR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t CAPBR : 1; /*!< [12..12] CAPBR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t DTR : 1; /*!< [13..13] DTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETAR : 1; /*!< [14..14] SETAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRAR : 1; /*!< [15..15] CLRAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETBR : 1; /*!< [16..16] SETBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRBR : 1; /*!< [17..17] CLRBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR0 : 1; /*!< [18..18] EEFR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR1 : 1; /*!< [19..19] EEFR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR2 : 1; /*!< [20..20] EEFR2 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTR : 1; /*!< [21..21] RSTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTER : 1; /*!< [22..22] RSTER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CHPR : 1; /*!< [23..23] CHPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACR : 1; /*!< [24..24] CAPACR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACER : 1; /*!< [25..25] CAPACER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCR : 1; /*!< [26..26] CAPBCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCER : 1; /*!< [27..27] CAPBCER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t OUTR : 1; /*!< [28..28] OUTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t FLTR : 1; /*!< [29..29] FLTR 寄存器支持 System DMA 写入DMADR并更新 */
+ uint32_t : 2;
+ } DMAUR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+
+ struct {
+ __IOM uint32_t DMADR : 32; /*!< [31..0] System DMA 数据地址 */
+ } DMADR_b;
+ } ;
+} HRPWM_SLV6_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV7 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_SLV7 (HRPWM_SLV7)
+ */
+
+typedef struct { /*!< (@ 0x4003B800) HRPWM_SLV7 Structure */
+
+ union {
+ __IOM uint32_t PWMCR0; /*!< (@ 0x00000000) HRPWM PWMx Control Register0 */
+
+ struct {
+ __IOM uint32_t CKPSC : 3; /*!< [2..0] PWMx 时钟预分频比 */
+ __IOM uint32_t CONT : 1; /*!< [3..3] PWMx 连续模式 */
+ __IOM uint32_t RETRIG : 1; /*!< [4..4] PWMx 可重触发模式 */
+ __IOM uint32_t HALF : 1; /*!< [5..5] PWMx Half 模式 */
+ __IOM uint32_t INTLVD : 2; /*!< [7..6] PWMx Interleaved 模式 */
+ __IOM uint32_t PSHPLL : 1; /*!< [8..8] PWMx Push-pull 模式 */
+ __IOM uint32_t RSYNCU : 1; /*!< [9..9] PWMx 重同步更新 */
+ __IOM uint32_t SYNCRST : 1; /*!< [10..10] 同步事件复位 PWMx */
+ __IOM uint32_t SYNCSTRT : 1; /*!< [11..11] 同步事件启动 PWMx */
+ uint32_t : 4;
+ __IOM uint32_t DELCMPB : 2; /*!< [17..16] PWMx CMPB Auto-Delayed 模式 */
+ __IOM uint32_t DELCMPD : 2; /*!< [19..18] PWMx CMPD Auto-Delayed 模式 */
+ __IOM uint32_t TRGHLF : 1; /*!< [20..20] PWMx Triggered-half 模式 */
+ __IOM uint32_t GTCMPA : 1; /*!< [21..21] PWMx CMPA Greater Than 模式 */
+ __IOM uint32_t GTCMPC : 1; /*!< [22..22] PWMx CMPC Greater Than 模式 */
+ __IOM uint32_t DACSYNC : 2; /*!< [24..23] DAC Trigger同步 */
+ __IOM uint32_t PREEN : 1; /*!< [25..25] PWMx 预加载使能 */
+ __IOM uint32_t UPDRST : 1; /*!< [26..26] PWMx Reset 更新 */
+ __IOM uint32_t UPDREP : 1; /*!< [27..27] PWMx Repetition 更新 */
+ __IOM uint32_t UPDGAT : 4; /*!< [31..28] 更新门控 */
+ } PWMCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMCR1; /*!< (@ 0x00000004) HRPWM PWMx Control Register1 */
+
+ struct {
+ __IOM uint32_t DCDE : 1; /*!< [0..0] DAC Reset／Step Trigger 使能 */
+ __IOM uint32_t DCDS : 1; /*!< [1..1] DAC Step Trigger 来源 */
+ __IOM uint32_t DCDR : 1; /*!< [2..2] DAC Reset Trigger 来源 */
+ __IOM uint32_t CAPAM : 1; /*!< [3..3] Capture A 模式选择 */
+ __IOM uint32_t UDM : 1; /*!< [4..4] Up-Down 模式选择 */
+ __IOM uint32_t CAPBM : 1; /*!< [5..5] Capture B 模式选择 */
+ __IOM uint32_t ROM : 2; /*!< [7..6] Roll-Over 模式选择 */
+ __IOM uint32_t OUTROM : 2; /*!< [9..8] 输出 Roll-Over 模式选择 */
+ __IOM uint32_t ADROM : 2; /*!< [11..10] ADC Roll-Over 模式选择 */
+ __IOM uint32_t EEVROM : 2; /*!< [13..12] 事件 Roll-Over 模式选择 */
+ __IOM uint32_t FLTROM : 2; /*!< [15..14] 故障 Roll-Over 模式选择 */
+ __IOM uint32_t MUPD : 1; /*!< [16..16] Master PWM 更新 */
+ __IOM uint32_t UPD0 : 1; /*!< [17..17] PWM0 更新 */
+ __IOM uint32_t UPD1 : 1; /*!< [18..18] PWM1 更新 */
+ __IOM uint32_t UPD2 : 1; /*!< [19..19] PWM2 更新 */
+ __IOM uint32_t UPD3 : 1; /*!< [20..20] PWM3 更新 */
+ __IOM uint32_t UPD4 : 1; /*!< [21..21] PWM4 更新 */
+ __IOM uint32_t UPD5 : 1; /*!< [22..22] PWM5 更新 */
+ __IOM uint32_t UPD6 : 1; /*!< [23..23] PWM6 更新 */
+ __IOM uint32_t UPD7 : 1; /*!< [24..24] PWM7 更新 */
+ uint32_t : 6;
+ __IOM uint32_t BDMADIS : 1; /*!< [31..31] PWMx Burst DMA 禁止 */
+ } PWMCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMISR; /*!< (@ 0x00000008) HRPWM PWMx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t CMPA : 1; /*!< [0..0] Compare A 中断标志 */
+ __IOM uint32_t CMPB : 1; /*!< [1..1] Compare B 中断标志 */
+ __IOM uint32_t CMPC : 1; /*!< [2..2] Compare C 中断标志 */
+ __IOM uint32_t CMPD : 1; /*!< [3..3] Compare D 中断标志 */
+ __IOM uint32_t PER : 1; /*!< [4..4] Roll-Over 中断标志 */
+ __IOM uint32_t UPD : 1; /*!< [5..5] Update 中断标志 */
+ __IOM uint32_t SETA : 1; /*!< [6..6] Out A Set 中断标志 */
+ __IOM uint32_t CLRA : 1; /*!< [7..7] Out A Clear 中断标志 */
+ __IOM uint32_t SETB : 1; /*!< [8..8] Out B Set 中断标志 */
+ __IOM uint32_t CLRB : 1; /*!< [9..9] Out B Clear 中断标志 */
+ __IOM uint32_t RST : 1; /*!< [10..10] Reset 中断标志 */
+ __IOM uint32_t REP : 1; /*!< [11..11] Repetition 中断标志 */
+ __IOM uint32_t CAPA : 1; /*!< [12..12] Capture A 中断标志 */
+ __IOM uint32_t CAPB : 1; /*!< [13..13] Capture B 中断标志 */
+ __IOM uint32_t DLYPRT : 1; /*!< [14..14] Delayed Protection 中断标志 */
+ uint32_t : 1;
+ __IM uint32_t CPPSTA : 1; /*!< [16..16] PushPull 当前状态 */
+ __IM uint32_t IPPSTA : 1; /*!< [17..17] PushPull 输出状态（延迟空闲/均衡空闲保护发生时） */
+ __IM uint32_t OUTASTA : 1; /*!< [18..18] OUTA 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTBSTA : 1; /*!< [19..19] OUTB 输出状态（延迟空闲保护发生时） */
+ __IM uint32_t OUTA : 1; /*!< [20..20] OUTA 当前输出（输出级之前） */
+ __IM uint32_t OUTB : 1; /*!< [21..21] OUTB 当前输出（输出级之前） */
+ uint32_t : 10;
+ } PWMISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PWMDIER; /*!< (@ 0x0000000C) HRPWM PWMx DMA Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t CMPAIE : 1; /*!< [0..0] Compare A 中断使能 */
+ __IOM uint32_t CMPBIE : 1; /*!< [1..1] Compare B 中断使能 */
+ __IOM uint32_t CMPCIE : 1; /*!< [2..2] Compare C 中断使能 */
+ __IOM uint32_t CMPDIE : 1; /*!< [3..3] Compare D 中断使能 */
+ __IOM uint32_t PERIE : 1; /*!< [4..4] Roll-Over 中断使能 */
+ __IOM uint32_t UPDIE : 1; /*!< [5..5] Update 中断使能 */
+ __IOM uint32_t SETAIE : 1; /*!< [6..6] Out A Set 中断使能 */
+ __IOM uint32_t CLRAIE : 1; /*!< [7..7] Out A Clear 中断使能 */
+ __IOM uint32_t SETBIE : 1; /*!< [8..8] Out B Set 中断使能 */
+ __IOM uint32_t CLRBIE : 1; /*!< [9..9] Out B Clear 中断使能 */
+ __IOM uint32_t RSTIE : 1; /*!< [10..10] Reset 中断使能 */
+ __IOM uint32_t REPIE : 1; /*!< [11..11] Repetition 中断使能 */
+ __IOM uint32_t CAPAIE : 1; /*!< [12..12] Capture A 中断使能 */
+ __IOM uint32_t CAPBIE : 1; /*!< [13..13] Capture B 中断使能 */
+ __IOM uint32_t DLYPRTIE : 1; /*!< [14..14] Delayed Protection 中断使能 */
+ uint32_t : 1;
+ __IOM uint32_t CMPADE : 1; /*!< [16..16] Compare A DMA使能 */
+ __IOM uint32_t CMPBDE : 1; /*!< [17..17] Compare B DMA使能 */
+ __IOM uint32_t CMPCDE : 1; /*!< [18..18] Compare C DMA使能 */
+ __IOM uint32_t CMPDDE : 1; /*!< [19..19] Compare D DMA使能 */
+ __IOM uint32_t PERDE : 1; /*!< [20..20] Roll-Over DMA使能 */
+ __IOM uint32_t UPDDE : 1; /*!< [21..21] Update DMA使能 */
+ __IOM uint32_t SETADE : 1; /*!< [22..22] Out A Set DMA使能 */
+ __IOM uint32_t CLRADE : 1; /*!< [23..23] Out A Clear DMA使能 */
+ __IOM uint32_t SETBDE : 1; /*!< [24..24] Out B Set DMA使能 */
+ __IOM uint32_t CLRBDE : 1; /*!< [25..25] Out B Clear DMA使能 */
+ __IOM uint32_t RSTDE : 1; /*!< [26..26] Reset DMA使能 */
+ __IOM uint32_t REPDE : 1; /*!< [27..27] Repetition DMA使能 */
+ __IOM uint32_t CAPADE : 1; /*!< [28..28] Capture A DMA使能 */
+ __IOM uint32_t CAPBDE : 1; /*!< [29..29] Capture B DMA使能 */
+ __IOM uint32_t DLYPRTDE : 1; /*!< [30..30] Delayed Protection DMA使能 */
+ uint32_t : 1;
+ } PWMDIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x00000010) HRPWM PWMx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] PWMx Counter 数值 */
+ uint32_t : 2;
+ __IOM uint32_t CNTRD : 1; /*!< [18..18] PWMx Counter 读取 */
+ __IOM uint32_t CNTWR : 1; /*!< [19..19] PWMx Counter 写入 */
+ uint32_t : 12;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PERR; /*!< (@ 0x00000014) HRPWM PWMx Period Register */
+
+ struct {
+ __IOM uint32_t PER : 16; /*!< [15..0] PWMx Period 数值 */
+ uint32_t : 16;
+ } PERR_b;
+ } ;
+
+ union {
+ __IOM uint32_t REPR; /*!< (@ 0x00000018) HRPWM PWMx Repetition Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] PWMx Repetition Period 数值 */
+ uint32_t : 24;
+ } REPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPAR; /*!< (@ 0x0000001C) HRPWM PWMx Compare A Register */
+
+ struct {
+ __IOM uint32_t CMPA : 16; /*!< [15..0] PWMx Compare A 数值 */
+ uint32_t : 16;
+ } CMPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPBR; /*!< (@ 0x00000020) HRPWM PWMx Compare B Register */
+
+ struct {
+ __IOM uint32_t CMPB : 16; /*!< [15..0] PWMx Compare B 数值 */
+ uint32_t : 16;
+ } CMPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPCR; /*!< (@ 0x00000024) HRPWM PWMx Compare C Register */
+
+ struct {
+ __IOM uint32_t CMPC : 16; /*!< [15..0] PWMx Compare C 数值 */
+ uint32_t : 16;
+ } CMPCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CMPDR; /*!< (@ 0x00000028) HRPWM PWMx Compare D Register */
+
+ struct {
+ __IOM uint32_t CMPD : 16; /*!< [15..0] PWMx Compare D 数值 */
+ uint32_t : 16;
+ } CMPDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPAR; /*!< (@ 0x0000002C) HRPWM PWMx Capture A Register */
+
+ struct {
+ __IM uint32_t CAPA : 16; /*!< [15..0] 捕获 A 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 A 方向 */
+ uint32_t : 15;
+ } CAPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBR; /*!< (@ 0x00000030) HRPWM PWMx Capture B Register */
+
+ struct {
+ __IM uint32_t CAPB : 16; /*!< [15..0] 捕获 B 数值 */
+ __IM uint32_t DIR : 1; /*!< [16..16] 捕获 B 方向 */
+ uint32_t : 15;
+ } CAPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTR; /*!< (@ 0x00000034) HRPWM PWMx DeadTime Register */
+
+ struct {
+ __IOM uint32_t DTR : 12; /*!< [11..0] 上升沿死区时间 */
+ __IOM uint32_t SDTR : 1; /*!< [12..12] 上升沿死区符号 */
+ uint32_t : 3;
+ __IOM uint32_t DTF : 12; /*!< [27..16] 下降沿死区时间 */
+ __IOM uint32_t SDTF : 1; /*!< [28..28] 下降沿死区符号 */
+ uint32_t : 3;
+ } DTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETAR; /*!< (@ 0x00000038) HRPWM PWMx Output A Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入有效状态 */
+ uint32_t : 9;
+ } SETAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRAR; /*!< (@ 0x0000003C) HRPWM PWMx Output A Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out A进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out A进入无效状态 */
+ uint32_t : 9;
+ } CLRAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SETBR; /*!< (@ 0x00000040) HRPWM PWMx Output B Set Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入有效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入有效状态 */
+ uint32_t : 9;
+ } SETBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CLRBR; /*!< (@ 0x00000044) HRPWM PWMx Output B Clear Register */
+
+ struct {
+ __IOM uint32_t SST : 1; /*!< [0..0] Software Set Trigger 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPA : 1; /*!< [1..1] PWMx Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPB : 1; /*!< [2..2] PWMx Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPC : 1; /*!< [3..3] PWMx Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t CMPD : 1; /*!< [4..4] PWMx Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t PER : 1; /*!< [5..5] PWMx Roll-Over 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [6..6] Master PWM Compare A 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [7..7] Master PWM Compare B 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [8..8] Master PWM Compare C 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [9..9] Master PWM Compare D 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t MSTPER : 1; /*!< [10..10] Master PWM Period 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT0 : 1; /*!< [11..11] PWMx Event 0 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT1 : 1; /*!< [12..12] PWMx Event 1 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT2 : 1; /*!< [13..13] PWMx Event 2 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT3 : 1; /*!< [14..14] PWMx Event 3 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT4 : 1; /*!< [15..15] PWMx Event 4 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT5 : 1; /*!< [16..16] PWMx Event 5 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT6 : 1; /*!< [17..17] PWMx Event 6 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT7 : 1; /*!< [18..18] PWMx Event 7 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT8 : 1; /*!< [19..19] PWMx Event 8 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t EXTEVNT9 : 1; /*!< [20..20] PWMx Event 9 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t RESYNC : 1; /*!< [21..21] Sync Input Event 事件使 PWMx Out B进入无效状态 */
+ __IOM uint32_t UPD : 1; /*!< [22..22] PWMx Update 事件使 PWMx Out B进入无效状态 */
+ uint32_t : 9;
+ } CLRBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR0; /*!< (@ 0x00000048) HRPWM PWMx External Event Register0 */
+
+ struct {
+ __IOM uint32_t EE0LTCH : 1; /*!< [0..0] Event 0 锁存位 */
+ __IOM uint32_t EE0FLTR : 4; /*!< [4..1] Event 0 滤波位 */
+ __IOM uint32_t EE1LTCH : 1; /*!< [5..5] Event 1 锁存位 */
+ __IOM uint32_t EE1FLTR : 4; /*!< [9..6] Event 1 滤波位 */
+ __IOM uint32_t EE2LTCH : 1; /*!< [10..10] Event 2 锁存位 */
+ __IOM uint32_t EE2FLTR : 4; /*!< [14..11] Event 2 滤波位 */
+ __IOM uint32_t EE3LTCH : 1; /*!< [15..15] Event 3 锁存位 */
+ __IOM uint32_t EE3FLTR : 4; /*!< [19..16] Event 3 滤波位 */
+ __IOM uint32_t EE4LTCH : 1; /*!< [20..20] Event 4 锁存位 */
+ __IOM uint32_t EE4FLTR : 4; /*!< [24..21] Event 4 滤波位 */
+ uint32_t : 7;
+ } EEFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR1; /*!< (@ 0x0000004C) HRPWM PWMx External Event Register1 */
+
+ struct {
+ __IOM uint32_t EE5LTCH : 1; /*!< [0..0] Event 5 锁存位 */
+ __IOM uint32_t EE5FLTR : 4; /*!< [4..1] Event 5 滤波位 */
+ __IOM uint32_t EE6LTCH : 1; /*!< [5..5] Event 6 锁存位 */
+ __IOM uint32_t EE6FLTR : 4; /*!< [9..6] Event 6 滤波位 */
+ __IOM uint32_t EE7LTCH : 1; /*!< [10..10] Event 7 锁存位 */
+ __IOM uint32_t EE7FLTR : 4; /*!< [14..11] Event 7 滤波位 */
+ __IOM uint32_t EE8LTCH : 1; /*!< [15..15] Event 8 锁存位 */
+ __IOM uint32_t EE8FLTR : 4; /*!< [19..16] Event 8 滤波位 */
+ __IOM uint32_t EE9LTCH : 1; /*!< [20..20] Event 9 锁存位 */
+ __IOM uint32_t EE9FLTR : 4; /*!< [24..21] Event 9 滤波位 */
+ uint32_t : 7;
+ } EEFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t EEFR2; /*!< (@ 0x00000050) HRPWM PWMx External Event Register2 */
+
+ struct {
+ __IOM uint32_t EEVACE : 1; /*!< [0..0] Event A 计数使能 */
+ __IOM uint32_t EEVACRES : 1; /*!< [1..1] Event A 计数复位 */
+ __IOM uint32_t EEVARSTM : 1; /*!< [2..2] Event A计数复位模式 */
+ uint32_t : 1;
+ __IOM uint32_t EEVASEL : 4; /*!< [7..4] Event A 来源选择 */
+ __IOM uint32_t EEVACNT : 6; /*!< [13..8] Event A 计数阈值 */
+ uint32_t : 18;
+ } EEFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTR; /*!< (@ 0x00000054) HRPWM PWMx Reset Register */
+
+ struct {
+ __IOM uint32_t SLV4CMPA : 1; /*!< [0..0] PWM4 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPA : 1; /*!< [1..1] Master PWM Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPB : 1; /*!< [2..2] Master PWM Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPC : 1; /*!< [3..3] Master PWM Compare C事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTCMPD : 1; /*!< [4..4] Master PWM Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t MSTPER : 1; /*!< [5..5] Master PWM Period事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [6..6] PWMx Event 0事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [7..7] PWMx Event 1事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [8..8] PWMx Event 2事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [9..9] PWMx Event 3事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [10..10] PWMx Event 4事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [11..11] PWMx Event 5事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [12..12] PWMx Event 6事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [13..13] PWMx Event 7事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [14..14] PWMx Event 8事件使 PWMx 计数器复位 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [15..15] PWMx Event 9事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVUPD : 1; /*!< [16..16] PWMx Update事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPB : 1; /*!< [17..17] PWMx Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLVCMPD : 1; /*!< [18..18] PWMx Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [19..19] PWM0 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [20..20] PWM0 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV0CMPD : 1; /*!< [21..21] PWM0 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [22..22] PWM1 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [23..23] PWM1 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV1CMPD : 1; /*!< [24..24] PWM1 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [25..25] PWM2 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [26..26] PWM2 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV2CMPD : 1; /*!< [27..27] PWM2 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [28..28] PWM3 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [29..29] PWM3 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV3CMPD : 1; /*!< [30..30] PWM3 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [31..31] PWM4 Compare B事件使 PWMx 计数器复位 */
+ } RSTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RSTER; /*!< (@ 0x00000058) HRPWM PWMx Reset Extended Register */
+
+ struct {
+ __IOM uint32_t SLV5CMPA : 1; /*!< [0..0] PWM5 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [1..1] PWM5 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV5CMPD : 1; /*!< [2..2] PWM5 Compare D事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [3..3] PWM6 Compare A事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [4..4] PWM6 Compare B事件使 PWMx 计数器复位 */
+ __IOM uint32_t SLV6CMPD : 1; /*!< [5..5] PWM6 Compare D事件使 PWMx 计数器复位 */
+ uint32_t : 26;
+ } RSTER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CHPR; /*!< (@ 0x0000005C) HRPWM PWMx Chopper Register */
+
+ struct {
+ __IOM uint32_t CARFRQ : 4; /*!< [3..0] PWMx 载波频率值 */
+ uint32_t : 2;
+ __IOM uint32_t CARDTY : 3; /*!< [8..6] PWMx 斩波占空比值 */
+ uint32_t : 3;
+ __IOM uint32_t STRPW : 4; /*!< [15..12] PWMx 启动脉冲宽度 */
+ uint32_t : 16;
+ } CHPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACR; /*!< (@ 0x00000060) HRPWM PWMx Capture A Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture A 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture A 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [20..20] PWM2 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [21..21] PWM2 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [24..24] PWM3 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [25..25] PWM3 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [26..26] PWM3 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [27..27] PWM3 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [28..28] PWM4 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [29..29] PWM4 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [30..30] PWM4 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [31..31] PWM4 Compare B 事件触发 Capture A 事件 */
+ } CAPACR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPACER; /*!< (@ 0x00000064) HRPWM PWMx Capture A Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV5SETA : 1; /*!< [0..0] PWM5 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [1..1] PWM5 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [2..2] PWM5 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [3..3] PWM5 Compare B 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6SETA : 1; /*!< [4..4] PWM6 OutA Set 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [5..5] PWM6 OutA Clr 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [6..6] PWM6 Compare A 事件触发 Capture A 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [7..7] PWM6 Compare B 事件触发 Capture A 事件 */
+ uint32_t : 24;
+ } CAPACER_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCR; /*!< (@ 0x00000068) HRPWM PWMx Capture B Control Register */
+
+ struct {
+ __IOM uint32_t SWCPT : 1; /*!< [0..0] Software Capture 事件触发 Capture B 事件 */
+ __IOM uint32_t UPDCPT : 1; /*!< [1..1] PWMx Update 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT0 : 1; /*!< [2..2] PWMx Event 0 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT1 : 1; /*!< [3..3] PWMx Event 1 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT2 : 1; /*!< [4..4] PWMx Event 2 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT3 : 1; /*!< [5..5] PWMx Event 3 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT4 : 1; /*!< [6..6] PWMx Event 4 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT5 : 1; /*!< [7..7] PWMx Event 5 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT6 : 1; /*!< [8..8] PWMx Event 6 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT7 : 1; /*!< [9..9] PWMx Event 7 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT8 : 1; /*!< [10..10] PWMx Event 8 事件触发 Capture B 事件 */
+ __IOM uint32_t EXTEVT9 : 1; /*!< [11..11] PWMx Event 9 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0SETA : 1; /*!< [12..12] PWM0 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CLRA : 1; /*!< [13..13] PWM0 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPA : 1; /*!< [14..14] PWM0 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV0CMPB : 1; /*!< [15..15] PWM0 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1SETA : 1; /*!< [16..16] PWM1 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CLRA : 1; /*!< [17..17] PWM1 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPA : 1; /*!< [18..18] PWM1 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV1CMPB : 1; /*!< [19..19] PWM1 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2SETA : 1; /*!< [20..20] PWM2 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CLRA : 1; /*!< [21..21] PWM2 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPA : 1; /*!< [22..22] PWM2 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV2CMPB : 1; /*!< [23..23] PWM2 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3SETA : 1; /*!< [24..24] PWM3 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CLRA : 1; /*!< [25..25] PWM3 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPA : 1; /*!< [26..26] PWM3 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV3CMPB : 1; /*!< [27..27] PWM3 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4SETA : 1; /*!< [28..28] PWM4 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CLRA : 1; /*!< [29..29] PWM4 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPA : 1; /*!< [30..30] PWM4 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV4CMPB : 1; /*!< [31..31] PWM4 Compare B 事件触发 Capture B 事件 */
+ } CAPBCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CAPBCER; /*!< (@ 0x0000006C) HRPWM PWMx Capture B Control Extended Register */
+
+ struct {
+ __IOM uint32_t SLV5SETA : 1; /*!< [0..0] PWM5 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CLRA : 1; /*!< [1..1] PWM5 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPA : 1; /*!< [2..2] PWM5 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV5CMPB : 1; /*!< [3..3] PWM5 Compare B 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6SETA : 1; /*!< [4..4] PWM6 OutA Set 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CLRA : 1; /*!< [5..5] PWM6 OutA Clr 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPA : 1; /*!< [6..6] PWM6 Compare A 事件触发 Capture B 事件 */
+ __IOM uint32_t SLV6CMPB : 1; /*!< [7..7] PWM6 Compare B 事件触发 Capture B 事件 */
+ uint32_t : 24;
+ } CAPBCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t OUTR; /*!< (@ 0x00000070) HRPWM PWMx Output Register */
+
+ struct {
+ __IOM uint32_t POLA : 1; /*!< [0..0] 输出 A 极性 */
+ __IOM uint32_t FAULTA : 2; /*!< [2..1] 输出 A 故障电平 */
+ __IOM uint32_t IDLESA : 1; /*!< [3..3] 输出 A 空闲状态 */
+ __IOM uint32_t CHPA : 1; /*!< [4..4] 输出 A 斩波使能 */
+ __IOM uint32_t IDLEMA : 1; /*!< [5..5] 输出 A 空闲模式 */
+ __IOM uint32_t DIDLA : 1; /*!< [6..6] 输出 A 空闲模式死区使能 */
+ uint32_t : 9;
+ __IOM uint32_t POLB : 1; /*!< [16..16] 输出 B 极性 */
+ __IOM uint32_t FAULTB : 2; /*!< [18..17] 输出 B 故障状态 */
+ __IOM uint32_t IDLESB : 1; /*!< [19..19] 输出 B 空闲状态 */
+ __IOM uint32_t CHPB : 1; /*!< [20..20] 输出 B 斩波使能 */
+ __IOM uint32_t IDLEMB : 1; /*!< [21..21] 输出 B 空闲模式 */
+ __IOM uint32_t DIDLB : 1; /*!< [22..22] 输出 B 空闲模式死区使能 */
+ uint32_t : 2;
+ __IOM uint32_t BIAR : 1; /*!< [25..25] 均衡空闲自动恢复 */
+ uint32_t : 1;
+ __IOM uint32_t DLYPRT : 3; /*!< [29..27] 延迟保护机制 */
+ __IOM uint32_t DLYPRTEN : 1; /*!< [30..30] 延迟保护使能 */
+ __IOM uint32_t DTEN : 1; /*!< [31..31] 死区使能 */
+ } OUTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTR; /*!< (@ 0x00000074) HRPWM PWMx Fault Register */
+
+ struct {
+ __IOM uint32_t FLT0EN : 1; /*!< [0..0] Fault 0 使能 */
+ __IOM uint32_t FLT1EN : 1; /*!< [1..1] Fault 1 使能 */
+ __IOM uint32_t FLT2EN : 1; /*!< [2..2] Fault 2 使能 */
+ __IOM uint32_t FLT3EN : 1; /*!< [3..3] Fault 3 使能 */
+ __IOM uint32_t FLT4EN : 1; /*!< [4..4] Fault 4 使能 */
+ __IOM uint32_t FLT5EN : 1; /*!< [5..5] Fault 5 使能 */
+ __IOM uint32_t FLT6EN : 1; /*!< [6..6] Fault 6 使能 */
+ __IOM uint32_t FLT7EN : 1; /*!< [7..7] Fault 7 使能 */
+ uint32_t : 24;
+ } FLTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMAUR; /*!< (@ 0x00000078) HRPWM PWMx System DMA Update Register */
+
+ struct {
+ __IOM uint32_t PWMCR0 : 1; /*!< [0..0] PWMCR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMCR1 : 1; /*!< [1..1] PWMCR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMISR : 1; /*!< [2..2] PWMISR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PWMDIER : 1; /*!< [3..3] PWMDIER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CNTR : 1; /*!< [4..4] CNTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t PERR : 1; /*!< [5..5] PERR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t REPR : 1; /*!< [6..6] REPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPAR : 1; /*!< [7..7] CMPAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPBR : 1; /*!< [8..8] CMPBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPCR : 1; /*!< [9..9] CMPCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CMPDR : 1; /*!< [10..10] CMPDR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPAR : 1; /*!< [11..11] CAPAR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t CAPBR : 1; /*!< [12..12] CAPBR 寄存器支持 System DMA 从DMADR读取数据 */
+ __IOM uint32_t DTR : 1; /*!< [13..13] DTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETAR : 1; /*!< [14..14] SETAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRAR : 1; /*!< [15..15] CLRAR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t SETBR : 1; /*!< [16..16] SETBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CLRBR : 1; /*!< [17..17] CLRBR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR0 : 1; /*!< [18..18] EEFR0 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR1 : 1; /*!< [19..19] EEFR1 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t EEFR2 : 1; /*!< [20..20] EEFR2 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTR : 1; /*!< [21..21] RSTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t RSTER : 1; /*!< [22..22] RSTER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CHPR : 1; /*!< [23..23] CHPR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACR : 1; /*!< [24..24] CAPACR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPACER : 1; /*!< [25..25] CAPACER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCR : 1; /*!< [26..26] CAPBCR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t CAPBCER : 1; /*!< [27..27] CAPBCER 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t OUTR : 1; /*!< [28..28] OUTR 寄存器支持 System DMA 写入DMADR并更新 */
+ __IOM uint32_t FLTR : 1; /*!< [29..29] FLTR 寄存器支持 System DMA 写入DMADR并更新 */
+ uint32_t : 2;
+ } DMAUR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DMADR; /*!< (@ 0x0000007C) HRPWM PWMx System DMA Data Register */
+
+ struct {
+ __IOM uint32_t DMADR : 32; /*!< [31..0] System DMA 数据地址 */
+ } DMADR_b;
+ } ;
+} HRPWM_SLV7_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_COM ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_COM (HRPWM_COM)
+ */
+
+typedef struct { /*!< (@ 0x4003BF00) HRPWM_COM Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) HRPWM Control Register0 */
+
+ struct {
+ __IOM uint32_t MUDIS : 1; /*!< [0..0] Master PWM 更新禁止 */
+ __IOM uint32_t UDIS0 : 1; /*!< [1..1] PWM0 更新禁止 */
+ __IOM uint32_t UDIS1 : 1; /*!< [2..2] PWM1 更新禁止 */
+ __IOM uint32_t UDIS2 : 1; /*!< [3..3] PWM2 更新禁止 */
+ __IOM uint32_t UDIS3 : 1; /*!< [4..4] PWM3 更新禁止 */
+ __IOM uint32_t UDIS4 : 1; /*!< [5..5] PWM4 更新禁止 */
+ __IOM uint32_t UDIS5 : 1; /*!< [6..6] PWM5 更新禁止 */
+ __IOM uint32_t UDIS6 : 1; /*!< [7..7] PWM6 更新禁止 */
+ __IOM uint32_t UDIS7 : 1; /*!< [8..8] PWM7 更新禁止 */
+ uint32_t : 6;
+ __IOM uint32_t BMUDIS : 1; /*!< [15..15] Burst Mode 更新禁止 */
+ __IOM uint32_t USRC0 : 4; /*!< [19..16] Adc Trigger 0 更新来源 */
+ __IOM uint32_t USRC1 : 4; /*!< [23..20] Adc Trigger 1 更新来源 */
+ __IOM uint32_t USRC2 : 4; /*!< [27..24] Adc Trigger 2 更新来源 */
+ __IOM uint32_t USRC3 : 4; /*!< [31..28] Adc Trigger 3 更新来源 */
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) HRPWM Control Register1 */
+
+ struct {
+ __IOM uint32_t SWP0 : 1; /*!< [0..0] PWM0 输出交换 */
+ __IOM uint32_t SWP1 : 1; /*!< [1..1] PWM1 输出交换 */
+ __IOM uint32_t SWP2 : 1; /*!< [2..2] PWM2 输出交换 */
+ __IOM uint32_t SWP3 : 1; /*!< [3..3] PWM3 输出交换 */
+ __IOM uint32_t SWP4 : 1; /*!< [4..4] PWM4 输出交换 */
+ __IOM uint32_t SWP5 : 1; /*!< [5..5] PWM5 输出交换 */
+ __IOM uint32_t SWP6 : 1; /*!< [6..6] PWM6 输出交换 */
+ __IOM uint32_t SWP7 : 1; /*!< [7..7] PWM7 输出交换 */
+ uint32_t : 8;
+ __IOM uint32_t TLEN0 : 4; /*!< [19..16] Adc Trigger 0 事件长度 */
+ __IOM uint32_t TLEN1 : 4; /*!< [23..20] Adc Trigger 1 事件长度 */
+ __IOM uint32_t TLEN2 : 4; /*!< [27..24] Adc Trigger 2 事件长度 */
+ __IOM uint32_t TLEN3 : 4; /*!< [31..28] Adc Trigger 3 事件长度 */
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR2; /*!< (@ 0x00000008) HRPWM Control Register2 */
+
+ struct {
+ __IOM uint32_t MSWU : 1; /*!< [0..0] Master PWM 软件更新 */
+ __IOM uint32_t SWU0 : 1; /*!< [1..1] PWM0 软件更新 */
+ __IOM uint32_t SWU1 : 1; /*!< [2..2] PWM1 软件更新 */
+ __IOM uint32_t SWU2 : 1; /*!< [3..3] PWM2 软件更新 */
+ __IOM uint32_t SWU3 : 1; /*!< [4..4] PWM3 软件更新 */
+ __IOM uint32_t SWU4 : 1; /*!< [5..5] PWM4 软件更新 */
+ __IOM uint32_t SWU5 : 1; /*!< [6..6] PWM5 软件更新 */
+ __IOM uint32_t SWU6 : 1; /*!< [7..7] PWM6 软件更新 */
+ __IOM uint32_t SWU7 : 1; /*!< [8..8] PWM7 软件更新 */
+ uint32_t : 7;
+ __IOM uint32_t MRST : 1; /*!< [16..16] Master PWM 软件复位 */
+ __IOM uint32_t RST0 : 1; /*!< [17..17] PWM0 软件复位 */
+ __IOM uint32_t RST1 : 1; /*!< [18..18] PWM1 软件复位 */
+ __IOM uint32_t RST2 : 1; /*!< [19..19] PWM2 软件复位 */
+ __IOM uint32_t RST3 : 1; /*!< [20..20] PWM3 软件复位 */
+ __IOM uint32_t RST4 : 1; /*!< [21..21] PWM4 软件复位 */
+ __IOM uint32_t RST5 : 1; /*!< [22..22] PWM5 软件复位 */
+ __IOM uint32_t RST6 : 1; /*!< [23..23] PWM6 软件复位 */
+ __IOM uint32_t RST7 : 1; /*!< [24..24] PWM7 软件复位 */
+ uint32_t : 7;
+ } CR2_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) HRPWM Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t SYSFLT : 1; /*!< [0..0] System Fault 中断标志 */
+ __IOM uint32_t FLT0 : 1; /*!< [1..1] Fault 0 中断标志 */
+ __IOM uint32_t FLT1 : 1; /*!< [2..2] Fault 1 中断标志 */
+ __IOM uint32_t FLT2 : 1; /*!< [3..3] Fault 2 中断标志 */
+ __IOM uint32_t FLT3 : 1; /*!< [4..4] Fault 3 中断标志 */
+ __IOM uint32_t FLT4 : 1; /*!< [5..5] Fault 4 中断标志 */
+ __IOM uint32_t FLT5 : 1; /*!< [6..6] Fault 5 中断标志 */
+ __IOM uint32_t FLT6 : 1; /*!< [7..7] Fault 6 中断标志 */
+ __IOM uint32_t FLT7 : 1; /*!< [8..8] Fault 7 中断标志 */
+ uint32_t : 6;
+ __IOM uint32_t BMPER : 1; /*!< [15..15] Burst Mode Period 中断标志 */
+ uint32_t : 16;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000014) HRPWM Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t SYSFLTIE : 1; /*!< [0..0] System Fault 中断使能 */
+ __IOM uint32_t FLT0IE : 1; /*!< [1..1] Fault 0 中断使能 */
+ __IOM uint32_t FLT1IE : 1; /*!< [2..2] Fault 1 中断使能 */
+ __IOM uint32_t FLT2IE : 1; /*!< [3..3] Fault 2 中断使能 */
+ __IOM uint32_t FLT3IE : 1; /*!< [4..4] Fault 3 中断使能 */
+ __IOM uint32_t FLT4IE : 1; /*!< [5..5] Fault 4 中断使能 */
+ __IOM uint32_t FLT5IE : 1; /*!< [6..6] Fault 5 中断使能 */
+ __IOM uint32_t FLT6IE : 1; /*!< [7..7] Fault 6 中断使能 */
+ __IOM uint32_t FLT7IE : 1; /*!< [8..8] Fault 7 中断使能 */
+ uint32_t : 6;
+ __IOM uint32_t BMPERIE : 1; /*!< [15..15] Burst Mode Period 中断使能 */
+ uint32_t : 16;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t OENR; /*!< (@ 0x00000018) HRPWM Output Enable Register */
+
+ struct {
+ __IOM uint32_t OEN0A : 1; /*!< [0..0] PWM0 Out A启动 */
+ __IOM uint32_t OEN0B : 1; /*!< [1..1] PWM0 Out B启动 */
+ __IOM uint32_t OEN1A : 1; /*!< [2..2] PWM1 Out A启动 */
+ __IOM uint32_t OEN1B : 1; /*!< [3..3] PWM1 Out B启动 */
+ __IOM uint32_t OEN2A : 1; /*!< [4..4] PWM2 Out A启动 */
+ __IOM uint32_t OEN2B : 1; /*!< [5..5] PWM2 Out B启动 */
+ __IOM uint32_t OEN3A : 1; /*!< [6..6] PWM3 Out A启动 */
+ __IOM uint32_t OEN3B : 1; /*!< [7..7] PWM3 Out B启动 */
+ __IOM uint32_t OEN4A : 1; /*!< [8..8] PWM4 Out A启动 */
+ __IOM uint32_t OEN4B : 1; /*!< [9..9] PWM4 Out B启动 */
+ __IOM uint32_t OEN5A : 1; /*!< [10..10] PWM5 Out A启动 */
+ __IOM uint32_t OEN5B : 1; /*!< [11..11] PWM5 Out B启动 */
+ __IOM uint32_t OEN6A : 1; /*!< [12..12] PWM6 Out A启动 */
+ __IOM uint32_t OEN6B : 1; /*!< [13..13] PWM6 Out B启动 */
+ __IOM uint32_t OEN7A : 1; /*!< [14..14] PWM7 Out A启动 */
+ __IOM uint32_t OEN7B : 1; /*!< [15..15] PWM7 Out B启动 */
+ uint32_t : 16;
+ } OENR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ODISR; /*!< (@ 0x0000001C) HRPWM Output Disable Register */
+
+ struct {
+ __IOM uint32_t ODIS0A : 1; /*!< [0..0] PWM0 Out A停止 */
+ __IOM uint32_t ODIS0B : 1; /*!< [1..1] PWM0 Out B停止 */
+ __IOM uint32_t ODIS1A : 1; /*!< [2..2] PWM1 Out A停止 */
+ __IOM uint32_t ODIS1B : 1; /*!< [3..3] PWM1 Out B停止 */
+ __IOM uint32_t ODIS2A : 1; /*!< [4..4] PWM2 Out A停止 */
+ __IOM uint32_t ODIS2B : 1; /*!< [5..5] PWM2 Out B停止 */
+ __IOM uint32_t ODIS3A : 1; /*!< [6..6] PWM3 Out A停止 */
+ __IOM uint32_t ODIS3B : 1; /*!< [7..7] PWM3 Out B停止 */
+ __IOM uint32_t ODIS4A : 1; /*!< [8..8] PWM4 Out A停止 */
+ __IOM uint32_t ODIS4B : 1; /*!< [9..9] PWM4 Out B停止 */
+ __IOM uint32_t ODIS5A : 1; /*!< [10..10] PWM5 Out A停止 */
+ __IOM uint32_t ODIS5B : 1; /*!< [11..11] PWM5 Out B停止 */
+ __IOM uint32_t ODIS6A : 1; /*!< [12..12] PWM6 Out A停止 */
+ __IOM uint32_t ODIS6B : 1; /*!< [13..13] PWM6 Out B停止 */
+ __IOM uint32_t ODIS7A : 1; /*!< [14..14] PWM7 Out A停止 */
+ __IOM uint32_t ODIS7B : 1; /*!< [15..15] PWM7 Out B停止 */
+ uint32_t : 16;
+ } ODISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EECR0; /*!< (@ 0x00000020) HRPWM External Event Control Register0 */
+
+ struct {
+ __IOM uint32_t EE0SRC : 2; /*!< [1..0] Event 0 输入来源 */
+ __IOM uint32_t EE0POL : 1; /*!< [2..2] Event 0 输入极性 */
+ __IOM uint32_t EE0SNS : 2; /*!< [4..3] Event 0 输入有效沿 */
+ __IOM uint32_t EE0FAST : 1; /*!< [5..5] Event 0 快速模式 */
+ __IOM uint32_t EE1SRC : 2; /*!< [7..6] Event 1 输入来源 */
+ __IOM uint32_t EE1POL : 1; /*!< [8..8] Event 1 输入极性 */
+ __IOM uint32_t EE1SNS : 2; /*!< [10..9] Event 1 输入有效沿 */
+ __IOM uint32_t EE1FAST : 1; /*!< [11..11] Event 1 快速模式 */
+ __IOM uint32_t EE2SRC : 2; /*!< [13..12] Event 2 输入来源 */
+ __IOM uint32_t EE2POL : 1; /*!< [14..14] Event 2 输入极性 */
+ __IOM uint32_t EE2SNS : 2; /*!< [16..15] Event 2 输入有效沿 */
+ __IOM uint32_t EE2FAST : 1; /*!< [17..17] Event 2 快速模式 */
+ __IOM uint32_t EE3SRC : 2; /*!< [19..18] Event 3 输入来源 */
+ __IOM uint32_t EE3POL : 1; /*!< [20..20] Event 3 输入极性 */
+ __IOM uint32_t EE3SNS : 2; /*!< [22..21] Event 3 输入有效沿 */
+ __IOM uint32_t EE3FAST : 1; /*!< [23..23] Event 3 快速模式 */
+ __IOM uint32_t EE4SRC : 2; /*!< [25..24] Event 4 输入来源 */
+ __IOM uint32_t EE4POL : 1; /*!< [26..26] Event 4 输入极性 */
+ __IOM uint32_t EE4SNS : 2; /*!< [28..27] Event 4 输入有效沿 */
+ __IOM uint32_t EE4FAST : 1; /*!< [29..29] Event 4 快速模式 */
+ uint32_t : 2;
+ } EECR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t EECR1; /*!< (@ 0x00000024) HRPWM External Event Control Register1 */
+
+ struct {
+ __IOM uint32_t EE5SRC : 2; /*!< [1..0] Event 5 输入来源 */
+ __IOM uint32_t EE5POL : 1; /*!< [2..2] Event 5 输入极性 */
+ __IOM uint32_t EE5SNS : 2; /*!< [4..3] Event 5 输入有效沿 */
+ __IOM uint32_t EE5FAST : 1; /*!< [5..5] Event 5 快速模式 */
+ __IOM uint32_t EE6SRC : 2; /*!< [7..6] Event 6 输入来源 */
+ __IOM uint32_t EE6POL : 1; /*!< [8..8] Event 6 输入极性 */
+ __IOM uint32_t EE6SNS : 2; /*!< [10..9] Event 6 输入有效沿 */
+ __IOM uint32_t EE6FAST : 1; /*!< [11..11] Event 6 快速模式 */
+ __IOM uint32_t EE7SRC : 2; /*!< [13..12] Event 7 输入来源 */
+ __IOM uint32_t EE7POL : 1; /*!< [14..14] Event 7 输入极性 */
+ __IOM uint32_t EE7SNS : 2; /*!< [16..15] Event 7 输入有效沿 */
+ __IOM uint32_t EE7FAST : 1; /*!< [17..17] Event 7 快速模式 */
+ __IOM uint32_t EE8SRC : 2; /*!< [19..18] Event 8 输入来源 */
+ __IOM uint32_t EE8POL : 1; /*!< [20..20] Event 8 输入极性 */
+ __IOM uint32_t EE8SNS : 2; /*!< [22..21] Event 8 输入有效沿 */
+ __IOM uint32_t EE8FAST : 1; /*!< [23..23] Event 8 快速模式 */
+ __IOM uint32_t EE9SRC : 2; /*!< [25..24] Event 9 输入来源 */
+ __IOM uint32_t EE9POL : 1; /*!< [26..26] Event 9 输入极性 */
+ __IOM uint32_t EE9SNS : 2; /*!< [28..27] Event 9 输入有效沿 */
+ __IOM uint32_t EE9FAST : 1; /*!< [29..29] Event 9 快速模式 */
+ uint32_t : 2;
+ } EECR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t EECR2; /*!< (@ 0x00000028) HRPWM External Event Control Register2 */
+
+ struct {
+ __IOM uint32_t EE0F : 4; /*!< [3..0] Event 0 滤波长度 */
+ __IOM uint32_t EE1F : 4; /*!< [7..4] Event 1 滤波长度 */
+ __IOM uint32_t EE2F : 4; /*!< [11..8] Event 2 滤波长度 */
+ __IOM uint32_t EE3F : 4; /*!< [15..12] Event 3 滤波长度 */
+ __IOM uint32_t EE4F : 4; /*!< [19..16] Event 4 滤波长度 */
+ uint32_t : 10;
+ __IOM uint32_t EEVSD : 2; /*!< [31..30] Event 采样时钟分频比例 */
+ } EECR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t EECR3; /*!< (@ 0x0000002C) HRPWM External Event Control Register3 */
+
+ struct {
+ __IOM uint32_t EE5F : 4; /*!< [3..0] Event 5 滤波长度 */
+ __IOM uint32_t EE6F : 4; /*!< [7..4] Event 6 滤波长度 */
+ __IOM uint32_t EE7F : 4; /*!< [11..8] Event 7 滤波长度 */
+ __IOM uint32_t EE8F : 4; /*!< [15..12] Event 8 滤波长度 */
+ __IOM uint32_t EE9F : 4; /*!< [19..16] Event 9 滤波长度 */
+ uint32_t : 12;
+ } EECR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADC0R; /*!< (@ 0x00000030) HRPWM ADC Trigger Register 0 */
+
+ struct {
+ __IOM uint32_t ADC0MCMPA : 1; /*!< [0..0] Master PWM Compare A事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0MCMPB : 1; /*!< [1..1] Master PWM Compare B事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0MCMPC : 1; /*!< [2..2] Master PWM Compare C事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0MCMPD : 1; /*!< [3..3] Master PWM Compare D事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0MPER : 1; /*!< [4..4] Master PWM Period事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0EEV0 : 1; /*!< [5..5] External Event 0事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0EEV1 : 1; /*!< [6..6] External Event 1事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0EEV2 : 1; /*!< [7..7] External Event 2事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0EEV3 : 1; /*!< [8..8] External Event 3事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0EEV4 : 1; /*!< [9..9] External Event 4事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPC0 : 1; /*!< [10..10] PWM0 Compare C事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPD0 : 1; /*!< [11..11] PWM0 Compare D事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0PER0 : 1; /*!< [12..12] PWM0 Period事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0RST0 : 1; /*!< [13..13] PWM0 Reset/RollOver事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPC1 : 1; /*!< [14..14] PWM1 Compare C事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPD1 : 1; /*!< [15..15] PWM1 Compare D事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0PER1 : 1; /*!< [16..16] PWM1 Period事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0RST1 : 1; /*!< [17..17] PWM1 Reset/RollOver事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPC2 : 1; /*!< [18..18] PWM2 Compare C事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPD2 : 1; /*!< [19..19] PWM2 Compare D事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0PER2 : 1; /*!< [20..20] PWM2 Period事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPC3 : 1; /*!< [21..21] PWM3 Compare C事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPD3 : 1; /*!< [22..22] PWM3 Compare D事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0PER3 : 1; /*!< [23..23] PWM3 Period事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPC4 : 1; /*!< [24..24] PWM4 Compare C事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPD4 : 1; /*!< [25..25] PWM4 Compare D事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0PER4 : 1; /*!< [26..26] PWM4 Period事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPB5 : 1; /*!< [27..27] PWM5 Compare B事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPC5 : 1; /*!< [28..28] PWM5 Compare C事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPD5 : 1; /*!< [29..29] PWM5 Compare D事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0PER5 : 1; /*!< [30..30] PWM5 Period事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0RST5 : 1; /*!< [31..31] PWM5 Reset/RollOver事件会产生Adc Trigger 0 */
+ } ADC0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADC0ER; /*!< (@ 0x00000034) HRPWM ADC Trigger Extended Register 0 */
+
+ struct {
+ __IOM uint32_t ADC0CMPC6 : 1; /*!< [0..0] PWM6 Compare C事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPD6 : 1; /*!< [1..1] PWM6 Compare D事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0PER6 : 1; /*!< [2..2] PWM6 Period事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0RST6 : 1; /*!< [3..3] PWM6 Reset/RollOver事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPC7 : 1; /*!< [4..4] PWM7 Compare C事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0CMPD7 : 1; /*!< [5..5] PWM7 Compare D事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0PER7 : 1; /*!< [6..6] PWM7 Period事件会产生Adc Trigger 0 */
+ __IOM uint32_t ADC0RST7 : 1; /*!< [7..7] PWM7 Reset/RollOver事件会产生Adc Trigger 0 */
+ uint32_t : 24;
+ } ADC0ER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADC1R; /*!< (@ 0x00000038) HRPWM ADC Trigger Register 1 */
+
+ struct {
+ __IOM uint32_t ADC1MCMPA : 1; /*!< [0..0] Master PWM Compare A事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1MCMPB : 1; /*!< [1..1] Master PWM Compare B事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1MCMPC : 1; /*!< [2..2] Master PWM Compare C事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1MCMPD : 1; /*!< [3..3] Master PWM Compare D事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1MPER : 1; /*!< [4..4] Master PWM Period事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1EEV5 : 1; /*!< [5..5] External Event 5事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1EEV6 : 1; /*!< [6..6] External Event 6事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1EEV7 : 1; /*!< [7..7] External Event 7事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1EEV8 : 1; /*!< [8..8] External Event 8事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1EEV9 : 1; /*!< [9..9] External Event 9事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPB0 : 1; /*!< [10..10] PWM0 Compare B事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPD0 : 1; /*!< [11..11] PWM0 Compare D事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1PER0 : 1; /*!< [12..12] PWM0 Period事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPB1 : 1; /*!< [13..13] PWM1 Compare B事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPD1 : 1; /*!< [14..14] PWM1 Compare D事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1PER1 : 1; /*!< [15..15] PWM1 Period事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPB2 : 1; /*!< [16..16] PWM2 Compare B事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPD2 : 1; /*!< [17..17] PWM2 Compare D事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1PER2 : 1; /*!< [18..18] PWM2 Period事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1RST2 : 1; /*!< [19..19] PWM2 Reset/RollOver事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPB3 : 1; /*!< [20..20] PWM3 Compare B事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPD3 : 1; /*!< [21..21] PWM3 Compare D事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1PER3 : 1; /*!< [22..22] PWM3 Period事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1RST3 : 1; /*!< [23..23] PWM3 Reset/RollOver事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPB4 : 1; /*!< [24..24] PWM4 Compare B事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPC4 : 1; /*!< [25..25] PWM4 Compare C事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPD4 : 1; /*!< [26..26] PWM4 Compare D事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1RST4 : 1; /*!< [27..27] PWM4 Reset/RollOver事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPB5 : 1; /*!< [28..28] PWM5 Compare B事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPC5 : 1; /*!< [29..29] PWM5 Compare C事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPD5 : 1; /*!< [30..30] PWM5 Compare D事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1PER5 : 1; /*!< [31..31] PWM5 Period事件会产生Adc Trigger 1 */
+ } ADC1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADC1ER; /*!< (@ 0x0000003C) HRPWM ADC Trigger Extended Register 1 */
+
+ struct {
+ __IOM uint32_t ADC1CMPB6 : 1; /*!< [0..0] PWM6 Compare B事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPD6 : 1; /*!< [1..1] PWM6 Compare D事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1PER6 : 1; /*!< [2..2] PWM6 Period事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1RST6 : 1; /*!< [3..3] PWM6 Reset/RollOver事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPB7 : 1; /*!< [4..4] PWM7 Compare B事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1CMPD7 : 1; /*!< [5..5] PWM7 Compare D事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1PER7 : 1; /*!< [6..6] PWM7 Period事件会产生Adc Trigger 1 */
+ __IOM uint32_t ADC1RST7 : 1; /*!< [7..7] PWM7 Reset/RollOver事件会产生Adc Trigger 1 */
+ uint32_t : 24;
+ } ADC1ER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADC2R; /*!< (@ 0x00000040) HRPWM ADC Trigger Register 2 */
+
+ struct {
+ __IOM uint32_t ADC2MCMPA : 1; /*!< [0..0] Master PWM Compare A事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2MCMPB : 1; /*!< [1..1] Master PWM Compare B事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2MCMPC : 1; /*!< [2..2] Master PWM Compare C事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2MCMPD : 1; /*!< [3..3] Master PWM Compare D事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2MPER : 1; /*!< [4..4] Master PWM Period事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2EEV0 : 1; /*!< [5..5] External Event 0事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2EEV1 : 1; /*!< [6..6] External Event 1事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2EEV2 : 1; /*!< [7..7] External Event 2事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2EEV3 : 1; /*!< [8..8] External Event 3事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2EEV4 : 1; /*!< [9..9] External Event 4事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPC0 : 1; /*!< [10..10] PWM0 Compare C事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPD0 : 1; /*!< [11..11] PWM0 Compare D事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2PER0 : 1; /*!< [12..12] PWM0 Period事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2RST0 : 1; /*!< [13..13] PWM0 Reset/RollOver事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPC1 : 1; /*!< [14..14] PWM1 Compare C事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPD1 : 1; /*!< [15..15] PWM1 Compare D事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2PER1 : 1; /*!< [16..16] PWM1 Period事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2RST1 : 1; /*!< [17..17] PWM1 Reset/RollOver事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPC2 : 1; /*!< [18..18] PWM2 Compare C事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPD2 : 1; /*!< [19..19] PWM2 Compare D事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2PER2 : 1; /*!< [20..20] PWM2 Period事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPC3 : 1; /*!< [21..21] PWM3 Compare C事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPD3 : 1; /*!< [22..22] PWM3 Compare D事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2PER3 : 1; /*!< [23..23] PWM3 Period事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPC4 : 1; /*!< [24..24] PWM4 Compare C事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPD4 : 1; /*!< [25..25] PWM4 Compare D事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2PER4 : 1; /*!< [26..26] PWM4 Period事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPB5 : 1; /*!< [27..27] PWM5 Compare B事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPC5 : 1; /*!< [28..28] PWM5 Compare C事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPD5 : 1; /*!< [29..29] PWM5 Compare D事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2PER5 : 1; /*!< [30..30] PWM5 Period事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2RST5 : 1; /*!< [31..31] PWM5 Reset/RollOver事件会产生Adc Trigger 2 */
+ } ADC2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADC2ER; /*!< (@ 0x00000044) HRPWM ADC Trigger Extended Register 2 */
+
+ struct {
+ __IOM uint32_t ADC2CMPC6 : 1; /*!< [0..0] PWM6 Compare C事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPD6 : 1; /*!< [1..1] PWM6 Compare D事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2PER6 : 1; /*!< [2..2] PWM6 Period事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2RST6 : 1; /*!< [3..3] PWM6 Reset/RollOver事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPC7 : 1; /*!< [4..4] PWM7 Compare C事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2CMPD7 : 1; /*!< [5..5] PWM7 Compare D事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2PER7 : 1; /*!< [6..6] PWM7 Period事件会产生Adc Trigger 2 */
+ __IOM uint32_t ADC2RST7 : 1; /*!< [7..7] PWM7 Reset/RollOver事件会产生Adc Trigger 2 */
+ uint32_t : 24;
+ } ADC2ER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADC3R; /*!< (@ 0x00000048) HRPWM ADC Trigger Register 3 */
+
+ struct {
+ __IOM uint32_t ADC3MCMPA : 1; /*!< [0..0] Master PWM Compare A事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3MCMPB : 1; /*!< [1..1] Master PWM Compare B事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3MCMPC : 1; /*!< [2..2] Master PWM Compare C事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3MCMPD : 1; /*!< [3..3] Master PWM Compare D事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3MPER : 1; /*!< [4..4] Master PWM Period事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3EEV5 : 1; /*!< [5..5] External Event 5事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3EEV6 : 1; /*!< [6..6] External Event 6事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3EEV7 : 1; /*!< [7..7] External Event 7事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3EEV8 : 1; /*!< [8..8] External Event 8事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3EEV9 : 1; /*!< [9..9] External Event 9事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPB0 : 1; /*!< [10..10] PWM0 Compare B事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPD0 : 1; /*!< [11..11] PWM0 Compare D事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3PER0 : 1; /*!< [12..12] PWM0 Period事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPB1 : 1; /*!< [13..13] PWM1 Compare B事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPD1 : 1; /*!< [14..14] PWM1 Compare D事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3PER1 : 1; /*!< [15..15] PWM1 Period事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPB2 : 1; /*!< [16..16] PWM2 Compare B事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPD2 : 1; /*!< [17..17] PWM2 Compare D事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3PER2 : 1; /*!< [18..18] PWM2 Period事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3RST2 : 1; /*!< [19..19] PWM2 Reset/RollOver事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPB3 : 1; /*!< [20..20] PWM3 Compare B事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPD3 : 1; /*!< [21..21] PWM3 Compare D事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3PER3 : 1; /*!< [22..22] PWM3 Period事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3RST3 : 1; /*!< [23..23] PWM3 Reset/RollOver事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPB4 : 1; /*!< [24..24] PWM4 Compare B事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPC4 : 1; /*!< [25..25] PWM4 Compare C事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPD4 : 1; /*!< [26..26] PWM4 Compare D事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3RST4 : 1; /*!< [27..27] PWM4 Reset/RollOver事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPB5 : 1; /*!< [28..28] PWM5 Compare B事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPC5 : 1; /*!< [29..29] PWM5 Compare C事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPD5 : 1; /*!< [30..30] PWM5 Compare D事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3PER5 : 1; /*!< [31..31] PWM5 Period事件会产生Adc Trigger 3 */
+ } ADC3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADC3ER; /*!< (@ 0x0000004C) HRPWM ADC Trigger Extended Register 3 */
+
+ struct {
+ __IOM uint32_t ADC3CMPB6 : 1; /*!< [0..0] PWM6 Compare B事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPD6 : 1; /*!< [1..1] PWM6 Compare D事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3PER6 : 1; /*!< [2..2] PWM6 Period事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3RST6 : 1; /*!< [3..3] PWM6 Reset/RollOver事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPB7 : 1; /*!< [4..4] PWM7 Compare B事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3CMPD7 : 1; /*!< [5..5] PWM7 Compare D事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3PER7 : 1; /*!< [6..6] PWM7 Period事件会产生Adc Trigger 3 */
+ __IOM uint32_t ADC3RST7 : 1; /*!< [7..7] PWM7 Reset/RollOver事件会产生Adc Trigger 3 */
+ uint32_t : 24;
+ } ADC3ER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADC4R; /*!< (@ 0x00000050) HRPWM ADC Trigger Register 4 */
+
+ struct {
+ __IOM uint32_t ADC4TRG : 6; /*!< [5..0] Adc Trigger 4 来源 */
+ uint32_t : 2;
+ __IOM uint32_t ADC5TRG : 6; /*!< [13..8] Adc Trigger 5 来源 */
+ uint32_t : 2;
+ __IOM uint32_t ADC6TRG : 6; /*!< [21..16] Adc Trigger 6 来源 */
+ uint32_t : 10;
+ } ADC4R_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADC5R; /*!< (@ 0x00000054) HRPWM ADC Trigger Register 5 */
+
+ struct {
+ __IOM uint32_t ADC7TRG : 6; /*!< [5..0] Adc Trigger 7 来源 */
+ uint32_t : 2;
+ __IOM uint32_t ADC8TRG : 6; /*!< [13..8] Adc Trigger 8 来源 */
+ uint32_t : 2;
+ __IOM uint32_t ADC9TRG : 6; /*!< [21..16] Adc Trigger 9 来源 */
+ uint32_t : 10;
+ } ADC5R_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADCUR; /*!< (@ 0x00000058) HRPWM ADC Update Register */
+
+ struct {
+ __IOM uint32_t USRC4 : 4; /*!< [3..0] Adc Trigger 4 更新来源 */
+ __IOM uint32_t USRC5 : 4; /*!< [7..4] Adc Trigger 5 更新来源 */
+ __IOM uint32_t USRC6 : 4; /*!< [11..8] Adc Trigger 6 更新来源 */
+ __IOM uint32_t USRC7 : 4; /*!< [15..12] Adc Trigger 7 更新来源 */
+ __IOM uint32_t USRC8 : 4; /*!< [19..16] Adc Trigger 8 更新来源 */
+ __IOM uint32_t USRC9 : 4; /*!< [23..20] Adc Trigger 9 更新来源 */
+ uint32_t : 8;
+ } ADCUR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADCLR; /*!< (@ 0x0000005C) HRPWM ADC Length Register */
+
+ struct {
+ __IOM uint32_t TLEN4 : 4; /*!< [3..0] Adc Trigger 4 事件长度 */
+ __IOM uint32_t TLEN5 : 4; /*!< [7..4] Adc Trigger 5 事件长度 */
+ __IOM uint32_t TLEN6 : 4; /*!< [11..8] Adc Trigger 6 事件长度 */
+ __IOM uint32_t TLEN7 : 4; /*!< [15..12] Adc Trigger 7 事件长度 */
+ __IOM uint32_t TLEN8 : 4; /*!< [19..16] Adc Trigger 8 事件长度 */
+ __IOM uint32_t TLEN9 : 4; /*!< [23..20] Adc Trigger 9 事件长度 */
+ uint32_t : 8;
+ } ADCLR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADPSR0; /*!< (@ 0x00000060) HRPWM ADC Trigger Post Scaler Register0 */
+
+ struct {
+ __IOM uint32_t PSC0 : 5; /*!< [4..0] Adc Trigger 0 降采样比例 */
+ uint32_t : 1;
+ __IOM uint32_t PSC1 : 5; /*!< [10..6] Adc Trigger 1 降采样比例 */
+ uint32_t : 1;
+ __IOM uint32_t PSC2 : 5; /*!< [16..12] Adc Trigger 2 降采样比例 */
+ uint32_t : 1;
+ __IOM uint32_t PSC3 : 5; /*!< [22..18] Adc Trigger 3 降采样比例 */
+ uint32_t : 1;
+ __IOM uint32_t PSC4 : 5; /*!< [28..24] Adc Trigger 4 降采样比例 */
+ uint32_t : 3;
+ } ADPSR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t ADPSR1; /*!< (@ 0x00000064) HRPWM ADC Trigger Post Scaler Register1 */
+
+ struct {
+ __IOM uint32_t PSC5 : 5; /*!< [4..0] Adc Trigger 5 降采样比例 */
+ uint32_t : 1;
+ __IOM uint32_t PSC6 : 5; /*!< [10..6] Adc Trigger 6 降采样比例 */
+ uint32_t : 1;
+ __IOM uint32_t PSC7 : 5; /*!< [16..12] Adc Trigger 7 降采样比例 */
+ uint32_t : 1;
+ __IOM uint32_t PSC8 : 5; /*!< [22..18] Adc Trigger 8 降采样比例 */
+ uint32_t : 1;
+ __IOM uint32_t PSC9 : 5; /*!< [28..24] Adc Trigger 9 降采样比例 */
+ uint32_t : 3;
+ } ADPSR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t DLLCR; /*!< (@ 0x00000068) HRPWM DLL Control Register */
+
+ struct {
+ __IOM uint32_t DLLEN : 1; /*!< [0..0] DLL 使能位 */
+ __IOM uint32_t DLLGCP : 2; /*!< [2..1] DLL 电流选择位 */
+ __IOM uint32_t DLLSTART : 1; /*!< [3..3] DLL 启动位 */
+ uint32_t : 2;
+ __IOM uint32_t DLLTHRES1 : 5; /*!< [10..6] DLL Clock Delay Threshold */
+ __IOM uint32_t DLLTHRES0 : 5; /*!< [15..11] DLL Clock Delay Threshold */
+ uint32_t : 15;
+ __IOM uint32_t DLLLCK : 1; /*!< [31..31] DLL Trim 寄存器属性 */
+ } DLLCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EECER; /*!< (@ 0x0000006C) HRPWM External Event Control Extended Register */
+
+ struct {
+ __IOM uint32_t EE0SRCH : 2; /*!< [1..0] Event 0 输入来源高位 */
+ __IOM uint32_t EE1SRCH : 2; /*!< [3..2] Event 1 输入来源高位 */
+ __IOM uint32_t EE2SRCH : 2; /*!< [5..4] Event 2 输入来源高位 */
+ __IOM uint32_t EE3SRCH : 2; /*!< [7..6] Event 3 输入来源高位 */
+ __IOM uint32_t EE4SRCH : 2; /*!< [9..8] Event 4 输入来源高位 */
+ __IOM uint32_t EE5SRCH : 2; /*!< [11..10] Event 5 输入来源高位 */
+ __IOM uint32_t EE6SRCH : 2; /*!< [13..12] Event 6 输入来源高位 */
+ __IOM uint32_t EE7SRCH : 2; /*!< [15..14] Event 7 输入来源高位 */
+ __IOM uint32_t EE8SRCH : 2; /*!< [17..16] Event 8 输入来源高位 */
+ __IOM uint32_t EE9SRCH : 2; /*!< [19..18] Event 9 输入来源高位 */
+ uint32_t : 12;
+ } EECER_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTINR0; /*!< (@ 0x00000070) HRPWM Fault Input Register0 */
+
+ struct {
+ __IOM uint32_t FLT0E : 1; /*!< [0..0] Fault 0 输入使能 */
+ __IOM uint32_t FLT0P : 1; /*!< [1..1] Fault 0 输入极性 */
+ __IOM uint32_t FLT0SRC : 2; /*!< [3..2] Fault 0 输入来源 */
+ __IOM uint32_t FLT1E : 1; /*!< [4..4] Fault 1 输入使能 */
+ __IOM uint32_t FLT1P : 1; /*!< [5..5] Fault 1 输入极性 */
+ __IOM uint32_t FLT1SRC : 2; /*!< [7..6] Fault 1 输入来源 */
+ __IOM uint32_t FLT2E : 1; /*!< [8..8] Fault 2 输入使能 */
+ __IOM uint32_t FLT2P : 1; /*!< [9..9] Fault 2 输入极性 */
+ __IOM uint32_t FLT2SRC : 2; /*!< [11..10] Fault 2 输入来源 */
+ __IOM uint32_t FLT3E : 1; /*!< [12..12] Fault 3 输入使能 */
+ __IOM uint32_t FLT3P : 1; /*!< [13..13] Fault 3 输入极性 */
+ __IOM uint32_t FLT3SRC : 2; /*!< [15..14] Fault 3 输入来源 */
+ __IOM uint32_t FLT4E : 1; /*!< [16..16] Fault 4 输入使能 */
+ __IOM uint32_t FLT4P : 1; /*!< [17..17] Fault 4 输入极性 */
+ __IOM uint32_t FLT4SRC : 2; /*!< [19..18] Fault 4 输入来源 */
+ __IOM uint32_t FLT5E : 1; /*!< [20..20] Fault 5 输入使能 */
+ __IOM uint32_t FLT5P : 1; /*!< [21..21] Fault 5 输入极性 */
+ __IOM uint32_t FLT5SRC : 2; /*!< [23..22] Fault 5 输入来源 */
+ __IOM uint32_t FLT6E : 1; /*!< [24..24] Fault 6 输入使能 */
+ __IOM uint32_t FLT6P : 1; /*!< [25..25] Fault 6 输入极性 */
+ __IOM uint32_t FLT6SRC : 2; /*!< [27..26] Fault 6 输入来源 */
+ __IOM uint32_t FLT7E : 1; /*!< [28..28] Fault 7 输入使能 */
+ __IOM uint32_t FLT7P : 1; /*!< [29..29] Fault 7 输入极性 */
+ __IOM uint32_t FLT7SRC : 2; /*!< [31..30] Fault 7 输入来源 */
+ } FLTINR0_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t FLTINR1; /*!< (@ 0x00000078) HRPWM Fault Input Register1 */
+
+ struct {
+ __IOM uint32_t FLT0F : 4; /*!< [3..0] Fault 0 滤波长度 */
+ __IOM uint32_t FLT1F : 4; /*!< [7..4] Fault 1 滤波长度 */
+ __IOM uint32_t FLT2F : 4; /*!< [11..8] Fault 2 滤波长度 */
+ __IOM uint32_t FLT3F : 4; /*!< [15..12] Fault 3 滤波长度 */
+ __IOM uint32_t FLT4F : 4; /*!< [19..16] Fault 4 滤波长度 */
+ __IOM uint32_t FLT5F : 4; /*!< [23..20] Fault 5 滤波长度 */
+ uint32_t : 6;
+ __IOM uint32_t FLTSD : 2; /*!< [31..30] Fault 采样时钟分频比例 */
+ } FLTINR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTINER; /*!< (@ 0x0000007C) HRPWM Fault Input Extend Register */
+
+ struct {
+ __IOM uint32_t FLT6F : 4; /*!< [3..0] Fault 6 滤波长度 */
+ __IOM uint32_t FLT7F : 4; /*!< [7..4] Fault 7 滤波长度 */
+ uint32_t : 24;
+ } FLTINER_b;
+ } ;
+
+ union {
+ __IOM uint32_t FLTINR2; /*!< (@ 0x00000080) HRPWM Fault Input Register2 */
+
+ struct {
+ __IOM uint32_t FLT0BLKE : 1; /*!< [0..0] Fault 0 消隐使能 */
+ __IOM uint32_t FLT0BLKS : 1; /*!< [1..1] Fault 0 消隐源（窗口大小由PWM0决定） */
+ __IOM uint32_t FLT0CRES : 1; /*!< [2..2] Fault 0 计数复位 */
+ __IOM uint32_t FLT0RSTM : 1; /*!< [3..3] Fault 0 复位模式 */
+ __IOM uint32_t FLT1BLKE : 1; /*!< [4..4] Fault 1 消隐使能 */
+ __IOM uint32_t FLT1BLKS : 1; /*!< [5..5] Fault 1 消隐源（窗口大小由PWM1决定） */
+ __IOM uint32_t FLT1CRES : 1; /*!< [6..6] Fault 1 计数复位 */
+ __IOM uint32_t FLT1RSTM : 1; /*!< [7..7] Fault 1 复位模式 */
+ __IOM uint32_t FLT2BLKE : 1; /*!< [8..8] Fault 2 消隐使能 */
+ __IOM uint32_t FLT2BLKS : 1; /*!< [9..9] Fault 2 消隐源（窗口大小由PWM2决定） */
+ __IOM uint32_t FLT2CRES : 1; /*!< [10..10] Fault 2 计数复位 */
+ __IOM uint32_t FLT2RSTM : 1; /*!< [11..11] Fault 2 复位模式 */
+ __IOM uint32_t FLT3BLKE : 1; /*!< [12..12] Fault 3 消隐使能 */
+ __IOM uint32_t FLT3BLKS : 1; /*!< [13..13] Fault 3 消隐源（窗口大小由PWM3决定） */
+ __IOM uint32_t FLT3CRES : 1; /*!< [14..14] Fault 3 计数复位 */
+ __IOM uint32_t FLT3RSTM : 1; /*!< [15..15] Fault 3 复位模式 */
+ __IOM uint32_t FLT4BLKE : 1; /*!< [16..16] Fault 4 消隐使能 */
+ __IOM uint32_t FLT4BLKS : 1; /*!< [17..17] Fault 4 消隐源（窗口大小由PWM4决定） */
+ __IOM uint32_t FLT4CRES : 1; /*!< [18..18] Fault 4 计数复位 */
+ __IOM uint32_t FLT4RSTM : 1; /*!< [19..19] Fault 4 复位模式 */
+ __IOM uint32_t FLT5BLKE : 1; /*!< [20..20] Fault 5 消隐使能 */
+ __IOM uint32_t FLT5BLKS : 1; /*!< [21..21] Fault 5 消隐源（窗口大小由PWM5决定） */
+ __IOM uint32_t FLT5CRES : 1; /*!< [22..22] Fault 5 计数复位 */
+ __IOM uint32_t FLT5RSTM : 1; /*!< [23..23] Fault 5 复位模式 */
+ __IOM uint32_t FLT6BLKE : 1; /*!< [24..24] Fault 6 消隐使能 */
+ __IOM uint32_t FLT6BLKS : 1; /*!< [25..25] Fault 6 消隐源（窗口大小由PWM6决定） */
+ __IOM uint32_t FLT6CRES : 1; /*!< [26..26] Fault 6 计数复位 */
+ __IOM uint32_t FLT6RSTM : 1; /*!< [27..27] Fault 6 复位模式 */
+ __IOM uint32_t FLT7BLKE : 1; /*!< [28..28] Fault 7 消隐使能 */
+ __IOM uint32_t FLT7BLKS : 1; /*!< [29..29] Fault 7 消隐源（窗口大小由PWM7决定） */
+ __IOM uint32_t FLT7CRES : 1; /*!< [30..30] Fault 7 计数复位 */
+ __IOM uint32_t FLT7RSTM : 1; /*!< [31..31] Fault 7 复位模式 */
+ } FLTINR2_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t FLTINR3; /*!< (@ 0x00000088) HRPWM Fault Input Register3 */
+
+ struct {
+ __IOM uint32_t FLT0CNT : 4; /*!< [3..0] Fault 0 计数阈值 */
+ __IOM uint32_t FLT1CNT : 4; /*!< [7..4] Fault 1 计数阈值 */
+ __IOM uint32_t FLT2CNT : 4; /*!< [11..8] Fault 2 计数阈值 */
+ __IOM uint32_t FLT3CNT : 4; /*!< [15..12] Fault 3 计数阈值 */
+ __IOM uint32_t FLT4CNT : 4; /*!< [19..16] Fault 4 计数阈值 */
+ __IOM uint32_t FLT5CNT : 4; /*!< [23..20] Fault 5 计数阈值 */
+ __IOM uint32_t FLT6CNT : 4; /*!< [27..24] Fault 6 计数阈值 */
+ __IOM uint32_t FLT7CNT : 4; /*!< [31..28] Fault 7 计数阈值 */
+ } FLTINR3_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t BMCR; /*!< (@ 0x00000090) HRPWM Burst Mode Control Register */
+
+ struct {
+ __IOM uint32_t BME : 1; /*!< [0..0] Burst Mode 使能 */
+ __IOM uint32_t BMOM : 1; /*!< [1..1] Burst Mode 工作模式 */
+ __IOM uint32_t BMCLK : 4; /*!< [5..2] Burst Mode 时钟来源 */
+ __IOM uint32_t BMPRSC : 4; /*!< [9..6] Burst Mode 预分频 */
+ __IOM uint32_t BMPREN : 1; /*!< [10..10] Burst Mode 预加载使能 */
+ __IOM uint32_t BMTM : 1; /*!< [11..11] Burst Mode 触发模式 */
+ uint32_t : 4;
+ __IOM uint32_t MBMDIS : 1; /*!< [16..16] Burst Mode下Master PWM 计数停止 */
+ __IOM uint32_t BMDIS0 : 1; /*!< [17..17] Burst Mode下PWM0 计数停止 */
+ __IOM uint32_t BMDIS1 : 1; /*!< [18..18] Burst Mode下PWM1 计数停止 */
+ __IOM uint32_t BMDIS2 : 1; /*!< [19..19] Burst Mode下PWM2 计数停止 */
+ __IOM uint32_t BMDIS3 : 1; /*!< [20..20] Burst Mode下PWM3 计数停止 */
+ __IOM uint32_t BMDIS4 : 1; /*!< [21..21] Burst Mode下PWM4 计数停止 */
+ __IOM uint32_t BMDIS5 : 1; /*!< [22..22] Burst Mode下PWM5 计数停止 */
+ __IOM uint32_t BMDIS6 : 1; /*!< [23..23] Burst Mode下PWM6 计数停止 */
+ __IOM uint32_t BMDIS7 : 1; /*!< [24..24] Burst Mode下PWM7 计数停止 */
+ uint32_t : 5;
+ __IOM uint32_t BMEXIT : 1; /*!< [30..30] Burst Mode 强制退出 */
+ __IM uint32_t BMSTAT : 1; /*!< [31..31] Burst Mode状态 */
+ } BMCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BMTRGR0; /*!< (@ 0x00000094) HRPWM Burst Mode Trigger Register 0 */
+
+ struct {
+ __IOM uint32_t SW : 1; /*!< [0..0] Software 事件启动 Burst Mode */
+ __IOM uint32_t MRST : 1; /*!< [1..1] Master PWM Reset/Rollover事件会启动 Burst Mode */
+ __IOM uint32_t MREP : 1; /*!< [2..2] Master PWM Repet事件会启动 Burst Mode */
+ __IOM uint32_t MCMPA : 1; /*!< [3..3] Master PWM Compare A事件会启动 Burst Mode */
+ __IOM uint32_t MCMPB : 1; /*!< [4..4] Master PWM Compare B事件会启动 Burst Mode */
+ __IOM uint32_t MCMPC : 1; /*!< [5..5] Master PWM Compare C事件会启动 Burst Mode */
+ __IOM uint32_t MCMPD : 1; /*!< [6..6] Master PWM Compare D事件会启动 Burst Mode */
+ __IOM uint32_t RST0 : 1; /*!< [7..7] PWM0 Reset/RollOver 事件会启动 Burst Mode */
+ __IOM uint32_t REP0 : 1; /*!< [8..8] PWM0 Repet 事件会启动 Burst Mode */
+ __IOM uint32_t CMPA0 : 1; /*!< [9..9] PWM0 Compare A 事件会启动 Burst Mode */
+ __IOM uint32_t CMPB0 : 1; /*!< [10..10] PWM0 Compare B 事件会启动 Burst Mode */
+ __IOM uint32_t RST1 : 1; /*!< [11..11] PWM1 Reset/RollOver 事件会启动 Burst Mode */
+ __IOM uint32_t REP1 : 1; /*!< [12..12] PWM1 Repet 事件会启动 Burst Mode */
+ __IOM uint32_t CMPA1 : 1; /*!< [13..13] PWM1 Compare A 事件会启动 Burst Mode */
+ __IOM uint32_t CMPB1 : 1; /*!< [14..14] PWM1 Compare B 事件会启动 Burst Mode */
+ __IOM uint32_t RST2 : 1; /*!< [15..15] PWM2 Reset/RollOver 事件会启动 Burst Mode */
+ __IOM uint32_t REP2 : 1; /*!< [16..16] PWM2 Repet 事件会启动 Burst Mode */
+ __IOM uint32_t CMPA2 : 1; /*!< [17..17] PWM2 Compare A 事件会启动 Burst Mode */
+ __IOM uint32_t RST3 : 1; /*!< [18..18] PWM3 Reset/RollOver 事件会启动 Burst Mode */
+ __IOM uint32_t REP3 : 1; /*!< [19..19] PWM3 Repet 事件会启动 Burst Mode */
+ __IOM uint32_t CMPB3 : 1; /*!< [20..20] PWM3 Compare A 事件会启动 Burst Mode */
+ __IOM uint32_t REP4 : 1; /*!< [21..21] PWM4 Repet 事件会启动 Burst Mode */
+ __IOM uint32_t CMPA4 : 1; /*!< [22..22] PWM4 Compare A 事件会启动 Burst Mode */
+ __IOM uint32_t CMPB4 : 1; /*!< [23..23] PWM4 Compare B 事件会启动 Burst Mode */
+ __IOM uint32_t RST5 : 1; /*!< [24..24] PWM5 Reset/RollOver 事件会启动 Burst Mode */
+ __IOM uint32_t REP5 : 1; /*!< [25..25] PWM5 Repet 事件会启动 Burst Mode */
+ __IOM uint32_t CMPA5 : 1; /*!< [26..26] PWM5 Compare A 事件会启动 Burst Mode */
+ __IOM uint32_t PER0EEV7 : 1; /*!< [27..27] PWM0 Event 7 事件后的 Period 事件会启动 Burst
+ Mode */
+ __IOM uint32_t PER4EEV8 : 1; /*!< [28..28] PWM4 Event 8 事件后的 Period 事件会启动 Burst
+ Mode */
+ __IOM uint32_t EEV7 : 1; /*!< [29..29] PWM0 Event 7 事件会启动 Burst Mode */
+ __IOM uint32_t EEV8 : 1; /*!< [30..30] PWM4 Event 8 事件会启动 Burst Mode */
+ __IOM uint32_t OCHPEV : 1; /*!< [31..31] TMR8_TRGO 事件会启动 Burst Mode */
+ } BMTRGR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t BMTRGR1; /*!< (@ 0x00000098) HRPWM Burst Mode Trigger Register 1 */
+
+ struct {
+ __IOM uint32_t RST6 : 1; /*!< [0..0] PWM6 Reset/RollOver 事件会启动 Burst Mode */
+ __IOM uint32_t REP6 : 1; /*!< [1..1] PWM6 Repet 事件会启动 Burst Mode */
+ __IOM uint32_t CMPA6 : 1; /*!< [2..2] PWM6 Compare A 事件会启动 Burst Mode */
+ __IOM uint32_t CMPB6 : 1; /*!< [3..3] PWM6 Compare B 事件会启动 Burst Mode */
+ __IOM uint32_t RST7 : 1; /*!< [4..4] PWM7 Reset/RollOver 事件会启动 Burst Mode */
+ __IOM uint32_t REP7 : 1; /*!< [5..5] PWM7 Repet 事件会启动 Burst Mode */
+ __IOM uint32_t CMPA7 : 1; /*!< [6..6] PWM7 Compare A 事件会启动 Burst Mode */
+ __IOM uint32_t CMPB7 : 1; /*!< [7..7] PWM7 Compare B 事件会启动 Burst Mode */
+ uint32_t : 24;
+ } BMTRGR1_b;
+ } ;
+ __IM uint32_t RESERVED4;
+
+ union {
+ __IOM uint32_t BMPER; /*!< (@ 0x000000A0) HRPWM Burst Mode Period Register */
+
+ struct {
+ __IOM uint32_t BMPER : 16; /*!< [15..0] Burst Mode Period 数值 */
+ uint32_t : 16;
+ } BMPER_b;
+ } ;
+
+ union {
+ __IOM uint32_t BMCMPR; /*!< (@ 0x000000A4) HRPWM Burst Mode Compare Register */
+
+ struct {
+ __IOM uint32_t BMCMP : 16; /*!< [15..0] Burst Mode Compare 数值 */
+ uint32_t : 16;
+ } BMCMPR_b;
+ } ;
+ __IM uint32_t RESERVED5[2];
+
+ union {
+ __IOM uint32_t BDMUPR; /*!< (@ 0x000000B0) HRPWM Burst DMA Master Update Register */
+
+ struct {
+ __IOM uint32_t MCR0 : 1; /*!< [0..0] MCR0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t MCR1 : 1; /*!< [1..1] MCR1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t MISR : 1; /*!< [2..2] MISR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t MDIER : 1; /*!< [3..3] MDIER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t MCNTR : 1; /*!< [4..4] MCNTR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t MPER : 1; /*!< [5..5] MPER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t MREP : 1; /*!< [6..6] MREP 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t MCMPAR : 1; /*!< [7..7] MCMPAR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t MCMPBR : 1; /*!< [8..8] MCMPBR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t MCMPCR : 1; /*!< [9..9] MCMPCR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t MCMPDR : 1; /*!< [10..10] MCMPDR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ uint32_t : 21;
+ } BDMUPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BDUPR0; /*!< (@ 0x000000B4) HRPWM Burst DMA Update Register 0 */
+
+ struct {
+ __IOM uint32_t PWM0CR0 : 1; /*!< [0..0] PWM0CR0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM0CR1 : 1; /*!< [1..1] PWM0CR1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM0ISR : 1; /*!< [2..2] PWM0ISR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM0DIER : 1; /*!< [3..3] PWM0DIER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CNT0R : 1; /*!< [4..4] CNT0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PER0R : 1; /*!< [5..5] PER0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t REP0R : 1; /*!< [6..6] REP0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPA0R : 1; /*!< [7..7] CMPA0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPB0R : 1; /*!< [8..8] CMPB0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPC0R : 1; /*!< [9..9] CMPC0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPD0R : 1; /*!< [10..10] CMPD0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA0R : 1; /*!< [11..11] CAPA0R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t CAPB0R : 1; /*!< [12..12] CAPB0R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t DT0R : 1; /*!< [13..13] DT0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET0AR : 1; /*!< [14..14] SET0AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR0AR : 1; /*!< [15..15] CLR0AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET0BR : 1; /*!< [16..16] SET0BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR0BR : 1; /*!< [17..17] CLR0BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF0R0 : 1; /*!< [18..18] EEF0R0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF0R1 : 1; /*!< [19..19] EEF0R1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF0R2 : 1; /*!< [20..20] EEF0R2 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST0R : 1; /*!< [21..21] RST0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST0ER : 1; /*!< [22..22] RST0ER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CHP0R : 1; /*!< [23..23] CHP0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA0CR : 1; /*!< [24..24] CAPA0CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA0CER : 1; /*!< [25..25] CAPA0CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB0CR : 1; /*!< [26..26] CAPB0CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB0CER : 1; /*!< [27..27] CAPB0CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t OUT0R : 1; /*!< [28..28] OUT0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t FLT0R : 1; /*!< [29..29] FLT0R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ uint32_t : 2;
+ } BDUPR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t BDUPR1; /*!< (@ 0x000000B8) HRPWM Burst DMA Update Register 1 */
+
+ struct {
+ __IOM uint32_t PWM1CR0 : 1; /*!< [0..0] PWM1CR0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM1CR1 : 1; /*!< [1..1] PWM1CR1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM1ISR : 1; /*!< [2..2] PWM1ISR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM1DIER : 1; /*!< [3..3] PWM1DIER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CNT1R : 1; /*!< [4..4] CNT1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PER1R : 1; /*!< [5..5] PER1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t REP1R : 1; /*!< [6..6] REP1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPA1R : 1; /*!< [7..7] CMPA1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPB1R : 1; /*!< [8..8] CMPB1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPC1R : 1; /*!< [9..9] CMPC1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPD1R : 1; /*!< [10..10] CMPD1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA1R : 1; /*!< [11..11] CAPA1R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t CAPB1R : 1; /*!< [12..12] CAPB1R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t DT1R : 1; /*!< [13..13] DT1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET1AR : 1; /*!< [14..14] SET1AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR1AR : 1; /*!< [15..15] CLR1AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET1BR : 1; /*!< [16..16] SET1BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR1BR : 1; /*!< [17..17] CLR1BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF1R0 : 1; /*!< [18..18] EEF1R0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF1R1 : 1; /*!< [19..19] EEF1R1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF1R2 : 1; /*!< [20..20] EEF1R2 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST1R : 1; /*!< [21..21] RST1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST1ER : 1; /*!< [22..22] RST1ER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CHP1R : 1; /*!< [23..23] CHP1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA1CR : 1; /*!< [24..24] CAPA1CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA1CER : 1; /*!< [25..25] CAPA1CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB1CR : 1; /*!< [26..26] CAPB1CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB1CER : 1; /*!< [27..27] CAPB1CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t OUT1R : 1; /*!< [28..28] OUT1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t FLT1R : 1; /*!< [29..29] FLT1R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ uint32_t : 2;
+ } BDUPR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t BDUPR2; /*!< (@ 0x000000BC) HRPWM Burst DMA Update Register 2 */
+
+ struct {
+ __IOM uint32_t PWM2CR0 : 1; /*!< [0..0] PWM2CR0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM2CR1 : 1; /*!< [1..1] PWM2CR1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM2ISR : 1; /*!< [2..2] PWM2ISR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM2DIER : 1; /*!< [3..3] PWM2DIER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CNT2R : 1; /*!< [4..4] CNT2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PER2R : 1; /*!< [5..5] PER2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t REP2R : 1; /*!< [6..6] REP2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPA2R : 1; /*!< [7..7] CMPA2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPB2R : 1; /*!< [8..8] CMPB2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPC2R : 1; /*!< [9..9] CMPC2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPD2R : 1; /*!< [10..10] CMPD2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA2R : 1; /*!< [11..11] CAPA2R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t CAPB2R : 1; /*!< [12..12] CAPB2R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t DT2R : 1; /*!< [13..13] DT2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET2AR : 1; /*!< [14..14] SET2AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR2AR : 1; /*!< [15..15] CLR2AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET2BR : 1; /*!< [16..16] SET2BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR2BR : 1; /*!< [17..17] CLR2BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF2R0 : 1; /*!< [18..18] EEF2R0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF2R1 : 1; /*!< [19..19] EEF2R1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF2R2 : 1; /*!< [20..20] EEF2R2 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST2R : 1; /*!< [21..21] RST2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST2ER : 1; /*!< [22..22] RST2ER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CHP2R : 1; /*!< [23..23] CHP2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA2CR : 1; /*!< [24..24] CAPA2CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA2CER : 1; /*!< [25..25] CAPA2CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB2CR : 1; /*!< [26..26] CAPB2CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB2CER : 1; /*!< [27..27] CAPB2CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t OUT2R : 1; /*!< [28..28] OUT2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t FLT2R : 1; /*!< [29..29] FLT2R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ uint32_t : 2;
+ } BDUPR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t BDUPR3; /*!< (@ 0x000000C0) HRPWM Burst DMA Update Register 3 */
+
+ struct {
+ __IOM uint32_t PWM3CR0 : 1; /*!< [0..0] PWM3CR0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM3CR1 : 1; /*!< [1..1] PWM3CR1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM3ISR : 1; /*!< [2..2] PWM3ISR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM3DIER : 1; /*!< [3..3] PWM3DIER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CNT3R : 1; /*!< [4..4] CNT3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PER3R : 1; /*!< [5..5] PER3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t REP3R : 1; /*!< [6..6] REP3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPA3R : 1; /*!< [7..7] CMPA3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPB3R : 1; /*!< [8..8] CMPB3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPC3R : 1; /*!< [9..9] CMPC3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPD3R : 1; /*!< [10..10] CMPD3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA3R : 1; /*!< [11..11] CAPA3R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t CAPB3R : 1; /*!< [12..12] CAPB3R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t DT3R : 1; /*!< [13..13] DT3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET3AR : 1; /*!< [14..14] SET3AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR3AR : 1; /*!< [15..15] CLR3AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET3BR : 1; /*!< [16..16] SET3BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR3BR : 1; /*!< [17..17] CLR3BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF3R0 : 1; /*!< [18..18] EEF3R0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF3R1 : 1; /*!< [19..19] EEF3R1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF3R2 : 1; /*!< [20..20] EEF3R2 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST3R : 1; /*!< [21..21] RST3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST3ER : 1; /*!< [22..22] RST3ER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CHP3R : 1; /*!< [23..23] CHP3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA3CR : 1; /*!< [24..24] CAPA3CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA3CER : 1; /*!< [25..25] CAPA3CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB3CR : 1; /*!< [26..26] CAPB3CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB3CER : 1; /*!< [27..27] CAPB3CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t OUT3R : 1; /*!< [28..28] OUT3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t FLT3R : 1; /*!< [29..29] FLT3R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ uint32_t : 2;
+ } BDUPR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t BDUPR4; /*!< (@ 0x000000C4) HRPWM Burst DMA Update Register 4 */
+
+ struct {
+ __IOM uint32_t PWM4CR0 : 1; /*!< [0..0] PWM4CR0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM4CR1 : 1; /*!< [1..1] PWM4CR1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM4ISR : 1; /*!< [2..2] PWM4ISR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM4DIER : 1; /*!< [3..3] PWM4DIER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CNT4R : 1; /*!< [4..4] CNT4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PER4R : 1; /*!< [5..5] PER4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t REP4R : 1; /*!< [6..6] REP4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPA4R : 1; /*!< [7..7] CMPA4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPB4R : 1; /*!< [8..8] CMPB4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPC4R : 1; /*!< [9..9] CMPC4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPD4R : 1; /*!< [10..10] CMPD4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA4R : 1; /*!< [11..11] CAPA4R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t CAPB4R : 1; /*!< [12..12] CAPB4R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t DT4R : 1; /*!< [13..13] DT4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET4AR : 1; /*!< [14..14] SET4AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR4AR : 1; /*!< [15..15] CLR4AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET4BR : 1; /*!< [16..16] SET4BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR4BR : 1; /*!< [17..17] CLR4BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF4R0 : 1; /*!< [18..18] EEF4R0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF4R1 : 1; /*!< [19..19] EEF4R1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF4R2 : 1; /*!< [20..20] EEF4R2 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST4R : 1; /*!< [21..21] RST4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST4ER : 1; /*!< [22..22] RST4ER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CHP4R : 1; /*!< [23..23] CHP4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA4CR : 1; /*!< [24..24] CAPA4CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA4CER : 1; /*!< [25..25] CAPA4CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB4CR : 1; /*!< [26..26] CAPB4CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB4CER : 1; /*!< [27..27] CAPB4CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t OUT4R : 1; /*!< [28..28] OUT4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t FLT4R : 1; /*!< [29..29] FLT4R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ uint32_t : 2;
+ } BDUPR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t BDUPR5; /*!< (@ 0x000000C8) HRPWM Burst DMA Update Register 5 */
+
+ struct {
+ __IOM uint32_t PWM5CR0 : 1; /*!< [0..0] PWM5CR0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM5CR1 : 1; /*!< [1..1] PWM5CR1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM5ISR : 1; /*!< [2..2] PWM5ISR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM5DIER : 1; /*!< [3..3] PWM5DIER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CNT5R : 1; /*!< [4..4] CNT5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PER5R : 1; /*!< [5..5] PER5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t REP5R : 1; /*!< [6..6] REP5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPA5R : 1; /*!< [7..7] CMPA5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPB5R : 1; /*!< [8..8] CMPB5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPC5R : 1; /*!< [9..9] CMPC5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPD5R : 1; /*!< [10..10] CMPD5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA5R : 1; /*!< [11..11] CAPA5R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t CAPB5R : 1; /*!< [12..12] CAPB5R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t DT5R : 1; /*!< [13..13] DT5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET5AR : 1; /*!< [14..14] SET5AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR5AR : 1; /*!< [15..15] CLR5AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET5BR : 1; /*!< [16..16] SET5BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR5BR : 1; /*!< [17..17] CLR5BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF5R0 : 1; /*!< [18..18] EEF5R0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF5R1 : 1; /*!< [19..19] EEF5R1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF5R2 : 1; /*!< [20..20] EEF5R2 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST5R : 1; /*!< [21..21] RST5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST5ER : 1; /*!< [22..22] RST5ER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CHP5R : 1; /*!< [23..23] CHP5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA5CR : 1; /*!< [24..24] CAPA5CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA5CER : 1; /*!< [25..25] CAPA5CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB5CR : 1; /*!< [26..26] CAPB5CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB5CER : 1; /*!< [27..27] CAPB5CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t OUT5R : 1; /*!< [28..28] OUT5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t FLT5R : 1; /*!< [29..29] FLT5R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ uint32_t : 2;
+ } BDUPR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t BDUPR6; /*!< (@ 0x000000CC) HRPWM Burst DMA Update Register 6 */
+
+ struct {
+ __IOM uint32_t PWM6CR0 : 1; /*!< [0..0] PWM6CR0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM6CR1 : 1; /*!< [1..1] PWM6CR1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM6ISR : 1; /*!< [2..2] PWM6ISR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM6DIER : 1; /*!< [3..3] PWM6DIER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CNT6R : 1; /*!< [4..4] CNT6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PER6R : 1; /*!< [5..5] PER6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t REP6R : 1; /*!< [6..6] REP6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPA6R : 1; /*!< [7..7] CMPA6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPB6R : 1; /*!< [8..8] CMPB6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPC6R : 1; /*!< [9..9] CMPC6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPD6R : 1; /*!< [10..10] CMPD6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA6R : 1; /*!< [11..11] CAPA6R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t CAPB6R : 1; /*!< [12..12] CAPB6R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t DT6R : 1; /*!< [13..13] DT6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET6AR : 1; /*!< [14..14] SET6AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR6AR : 1; /*!< [15..15] CLR6AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET6BR : 1; /*!< [16..16] SET6BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR6BR : 1; /*!< [17..17] CLR6BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF6R0 : 1; /*!< [18..18] EEF6R0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF6R1 : 1; /*!< [19..19] EEF6R1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF6R2 : 1; /*!< [20..20] EEF6R2 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST6R : 1; /*!< [21..21] RST6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST6ER : 1; /*!< [22..22] RST6ER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CHP6R : 1; /*!< [23..23] CHP6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA6CR : 1; /*!< [24..24] CAPA6CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA6CER : 1; /*!< [25..25] CAPA6CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB6CR : 1; /*!< [26..26] CAPB6CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB6CER : 1; /*!< [27..27] CAPB6CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t OUT6R : 1; /*!< [28..28] OUT6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t FLT6R : 1; /*!< [29..29] FLT6R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ uint32_t : 2;
+ } BDUPR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t BDUPR7; /*!< (@ 0x000000D0) HRPWM Burst DMA Update Register 7 */
+
+ struct {
+ __IOM uint32_t PWM7CR0 : 1; /*!< [0..0] PWM7CR0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM7CR1 : 1; /*!< [1..1] PWM7CR1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM7ISR : 1; /*!< [2..2] PWM7ISR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PWM7DIER : 1; /*!< [3..3] PWM7DIER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CNT7R : 1; /*!< [4..4] CNT7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t PER7R : 1; /*!< [5..5] PER7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t REP7R : 1; /*!< [6..6] REP7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPA7R : 1; /*!< [7..7] CMPA7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPB7R : 1; /*!< [8..8] CMPB7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPC7R : 1; /*!< [9..9] CMPC7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CMPD7R : 1; /*!< [10..10] CMPD7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA7R : 1; /*!< [11..11] CAPA7R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t CAPB7R : 1; /*!< [12..12] CAPB7R 寄存器支持 Burst DMA 将寄存器值写入缓存 */
+ __IOM uint32_t DT7R : 1; /*!< [13..13] DT7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET7AR : 1; /*!< [14..14] SET7AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR7AR : 1; /*!< [15..15] CLR7AR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t SET7BR : 1; /*!< [16..16] SET7BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CLR7BR : 1; /*!< [17..17] CLR7BR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF7R0 : 1; /*!< [18..18] EEF7R0 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF7R1 : 1; /*!< [19..19] EEF7R1 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t EEF7R2 : 1; /*!< [20..20] EEF7R2 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST7R : 1; /*!< [21..21] RST7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t RST7ER : 1; /*!< [22..22] RST7ER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CHP7R : 1; /*!< [23..23] CHP7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA7CR : 1; /*!< [24..24] CAPA7CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPA7CER : 1; /*!< [25..25] CAPA7CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB7CR : 1; /*!< [26..26] CAPB7CR 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t CAPB7CER : 1; /*!< [27..27] CAPB7CER 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t OUT7R : 1; /*!< [28..28] OUT7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ __IOM uint32_t FLT7R : 1; /*!< [29..29] FLT7R 寄存器支持 Burst DMA 读取缓存数据并更新 */
+ uint32_t : 2;
+ } BDUPR7_b;
+ } ;
+ __IM uint32_t RESERVED6[3];
+
+ union {
+ __IOM uint32_t BDMWADR; /*!< (@ 0x000000E0) HRPWM Burst DMA Write Address Register */
+
+ struct {
+ __IOM uint32_t BDMADR : 32; /*!< [31..0] Burst DMA 写起始地址 */
+ } BDMWADR_b;
+ } ;
+ __IM uint32_t RESERVED7[3];
+
+ union {
+ __IOM uint32_t BDMADR; /*!< (@ 0x000000F0) HRPWM Burst DMA Read Address Register */
+
+ struct {
+ __IOM uint32_t BDMADR : 32; /*!< [31..0] Burst DMA 读起始地址 */
+ } BDMADR_b;
+ } ;
+} HRPWM_COM_Type; /*!< Size = 244 (0xf4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_MST ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief HRPWM_MST (HRPWM_MST)
+ */
+
+typedef struct { /*!< (@ 0x4003B000) HRPWM_MST Structure */
+
+ union {
+ __IOM uint32_t MCR0; /*!< (@ 0x00000000) HRPWM Master PWM Control Register0 */
+
+ struct {
+ __IOM uint32_t CKPSC : 3; /*!< [2..0] Master PWM 时钟预分频比 */
+ __IOM uint32_t CONT : 1; /*!< [3..3] Master PWM 连续模式 */
+ __IOM uint32_t RETRIG : 1; /*!< [4..4] Master PWM 可重触发模式 */
+ __IOM uint32_t HALF : 1; /*!< [5..5] Master PWM Half 模式 */
+ __IOM uint32_t INTLVD : 2; /*!< [7..6] Master PWM Interleaved 模式 */
+ __IOM uint32_t SYNCINSRC : 1; /*!< [8..8] 同步事件输入来源 */
+ __IOM uint32_t SYNCINEN : 1; /*!< [9..9] 同步事件输入使能 */
+ __IOM uint32_t SYNCRSTM : 1; /*!< [10..10] 同步事件复位 Master PWM */
+ __IOM uint32_t SYNCSTRTM : 1; /*!< [11..11] 同步事件启动 Master PWM */
+ __IOM uint32_t SYNCOUTPOL : 1; /*!< [12..12] 同步事件输出极性 */
+ __IOM uint32_t SYNCOUTEN : 1; /*!< [13..13] 同步事件输出使能 */
+ __IOM uint32_t SYNCOUTSRC : 2; /*!< [15..14] 同步事件输出来源 */
+ uint32_t : 7;
+ __IOM uint32_t DACSYNC : 2; /*!< [24..23] DAC Trigger同步 */
+ __IOM uint32_t PREEN : 1; /*!< [25..25] Master PWM 预加载使能 */
+ __IOM uint32_t MRSTU : 1; /*!< [26..26] Master PWM Reset/RollOver 更新 */
+ __IOM uint32_t MREPU : 1; /*!< [27..27] Master PWM Repetition 更新 */
+ uint32_t : 2;
+ __IOM uint32_t BRSTDMA : 2; /*!< [31..30] Burst DMA 更新 */
+ } MCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t MCR1; /*!< (@ 0x00000004) HRPWM Master PWM Control Register1 */
+
+ struct {
+ uint32_t : 16;
+ __IOM uint32_t MCEN : 1; /*!< [16..16] Master PWM 使能 */
+ __IOM uint32_t CEN0 : 1; /*!< [17..17] PWM0 使能 */
+ __IOM uint32_t CEN1 : 1; /*!< [18..18] PWM1 使能 */
+ __IOM uint32_t CEN2 : 1; /*!< [19..19] PWM2 使能 */
+ __IOM uint32_t CEN3 : 1; /*!< [20..20] PWM3 使能 */
+ __IOM uint32_t CEN4 : 1; /*!< [21..21] PWM4 使能 */
+ __IOM uint32_t CEN5 : 1; /*!< [22..22] PWM5 使能 */
+ __IOM uint32_t CEN6 : 1; /*!< [23..23] PWM6 使能 */
+ __IOM uint32_t CEN7 : 1; /*!< [24..24] PWM7 使能 */
+ uint32_t : 6;
+ __IOM uint32_t BDMADIS : 1; /*!< [31..31] Master PWM Burst DMA 禁止 */
+ } MCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t MISR; /*!< (@ 0x00000008) HRPWM Master PWM Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t MCMPA : 1; /*!< [0..0] Master Compare A 中断标志 */
+ __IOM uint32_t MCMPB : 1; /*!< [1..1] Master Compare B 中断标志 */
+ __IOM uint32_t MCMPC : 1; /*!< [2..2] Master Compare C 中断标志 */
+ __IOM uint32_t MCMPD : 1; /*!< [3..3] Master Compare D 中断标志 */
+ __IOM uint32_t MPER : 1; /*!< [4..4] Master Period 中断标志 */
+ __IOM uint32_t SYNC : 1; /*!< [5..5] Sync Input 中断标志 */
+ __IOM uint32_t MUPD : 1; /*!< [6..6] Master Update 中断标志 */
+ __IOM uint32_t MRST : 1; /*!< [7..7] Master Reset 中断标志 */
+ __IOM uint32_t MREP : 1; /*!< [8..8] Master Repetition 中断标志 */
+ uint32_t : 23;
+ } MISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MDIER; /*!< (@ 0x0000000C) HRPWM Master PWM DMA Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t MCMPAIE : 1; /*!< [0..0] Master Compare A 中断使能 */
+ __IOM uint32_t MCMPBIE : 1; /*!< [1..1] Master Compare B 中断使能 */
+ __IOM uint32_t MCMPCIE : 1; /*!< [2..2] Master Compare C 中断使能 */
+ __IOM uint32_t MCMPDIE : 1; /*!< [3..3] Master Compare D 中断使能 */
+ __IOM uint32_t MPERIE : 1; /*!< [4..4] Master Period 中断使能 */
+ __IOM uint32_t SYNCIE : 1; /*!< [5..5] Sync Input 中断使能 */
+ __IOM uint32_t MUPDIE : 1; /*!< [6..6] Master Update 中断使能 */
+ __IOM uint32_t MRSTIE : 1; /*!< [7..7] Master Reset 中断使能 */
+ __IOM uint32_t MREPIE : 1; /*!< [8..8] Master Repetition 中断使能 */
+ uint32_t : 7;
+ __IOM uint32_t MCMPADE : 1; /*!< [16..16] Master Compare A DMA使能 */
+ __IOM uint32_t MCMPBDE : 1; /*!< [17..17] Master Compare B DMA使能 */
+ __IOM uint32_t MCMPCDE : 1; /*!< [18..18] Master Compare C DMA使能 */
+ __IOM uint32_t MCMPDDE : 1; /*!< [19..19] Master Compare D DMA使能 */
+ __IOM uint32_t MPERDE : 1; /*!< [20..20] Master Period DMA使能 */
+ __IOM uint32_t SYNCDE : 1; /*!< [21..21] Sync Input DMA使能 */
+ __IOM uint32_t MUPDDE : 1; /*!< [22..22] Master Update DMA使能 */
+ __IOM uint32_t MRSTDE : 1; /*!< [23..23] Master Reset DMA使能 */
+ __IOM uint32_t MREPDE : 1; /*!< [24..24] Master Repetition DMA使能 */
+ uint32_t : 7;
+ } MDIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t MCNTR; /*!< (@ 0x00000010) HRPWM Master PWM Counter Register */
+
+ struct {
+ __IOM uint32_t MCNT : 16; /*!< [15..0] Master PWM Counter 数值 */
+ uint32_t : 2;
+ __IOM uint32_t CNTRD : 1; /*!< [18..18] Master PWM Counter 读取 */
+ __IOM uint32_t CNTWR : 1; /*!< [19..19] Master PWM Counter 写入 */
+ uint32_t : 12;
+ } MCNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MPER; /*!< (@ 0x00000014) HRPWM Master PWM Period Register */
+
+ struct {
+ __IOM uint32_t MPER : 16; /*!< [15..0] Master PWM Period 数值 */
+ uint32_t : 16;
+ } MPER_b;
+ } ;
+
+ union {
+ __IOM uint32_t MREP; /*!< (@ 0x00000018) HRPWM Master PWM Repetition Register */
+
+ struct {
+ __IOM uint32_t MREP : 8; /*!< [7..0] Master PWM Repetition Period 数值 */
+ uint32_t : 24;
+ } MREP_b;
+ } ;
+
+ union {
+ __IOM uint32_t MCMPAR; /*!< (@ 0x0000001C) HRPWM Master PWM Compare A Register */
+
+ struct {
+ __IOM uint32_t MCMPA : 16; /*!< [15..0] Master PWM Compare A 数值 */
+ uint32_t : 16;
+ } MCMPAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MCMPBR; /*!< (@ 0x00000020) HRPWM Master PWM Compare B Register */
+
+ struct {
+ __IOM uint32_t MCMPB : 16; /*!< [15..0] Master PWM Compare B 数值 */
+ uint32_t : 16;
+ } MCMPBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MCMPCR; /*!< (@ 0x00000024) HRPWM Master PWM Compare C Register */
+
+ struct {
+ __IOM uint32_t MCMPC : 16; /*!< [15..0] Master PWM Compare C 数值 */
+ uint32_t : 16;
+ } MCMPCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MCMPDR; /*!< (@ 0x00000028) HRPWM Master PWM Compare D Register */
+
+ struct {
+ __IOM uint32_t MCMPD : 16; /*!< [15..0] Master PWM Compare D 数值 */
+ uint32_t : 16;
+ } MCMPDR_b;
+ } ;
+ __IM uint32_t RESERVED[19];
+
+ union {
+ __IOM uint32_t MDMAUR; /*!< (@ 0x00000078) HRPWM Master PWM System DMA Update Register */
+
+ struct {
+ __IOM uint32_t MCR0 : 1; /*!< [0..0] MCR0 寄存器支持 System DMA 写入MDMADR并更新 */
+ __IOM uint32_t MCR1 : 1; /*!< [1..1] MCR1 寄存器支持 System DMA 写入MDMADR并更新 */
+ __IOM uint32_t MISR : 1; /*!< [2..2] MISR 寄存器支持 System DMA 写入MDMADR并更新 */
+ __IOM uint32_t MDIER : 1; /*!< [3..3] MDIER 寄存器支持 System DMA 写入MDMADR并更新 */
+ __IOM uint32_t MCNTR : 1; /*!< [4..4] MCNTR 寄存器支持 System DMA 写入MDMADR并更新 */
+ __IOM uint32_t MPER : 1; /*!< [5..5] MPER 寄存器支持 System DMA 写入MDMADR并更新 */
+ __IOM uint32_t MREP : 1; /*!< [6..6] MREP 寄存器支持 System DMA 写入MDMADR并更新 */
+ __IOM uint32_t MCMPAR : 1; /*!< [7..7] MCMPAR 寄存器支持 System DMA 写入MDMADR并更新 */
+ __IOM uint32_t MCMPBR : 1; /*!< [8..8] MCMPBR 寄存器支持 System DMA 写入MDMADR并更新 */
+ __IOM uint32_t MCMPCR : 1; /*!< [9..9] MCMPCR 寄存器支持 System DMA 写入MDMADR并更新 */
+ __IOM uint32_t MCMPDR : 1; /*!< [10..10] MCMPDR 寄存器支持 System DMA 写入MDMADR并更新 */
+ uint32_t : 21;
+ } MDMAUR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MDMADR; /*!< (@ 0x0000007C) HRPWM Master PWM System DMA Data Register */
+
+ struct {
+ __IOM uint32_t MDMADR : 32; /*!< [31..0] System DMA 数据地址 */
+ } MDMADR_b;
+ } ;
+} HRPWM_MST_Type; /*!< Size = 128 (0x80) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR3 (TMR3)
+ */
+
+typedef struct { /*!< (@ 0x4002A000) TMR3 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 计数器使能位(Counter Enable) */
+ __IOM uint32_t UDIS : 1; /*!< [1..1] 更新禁止位(Update Disable) */
+ __IOM uint32_t URS : 1; /*!< [2..2] 更新事件源(Update Request Source) */
+ __IOM uint32_t OPM : 1; /*!< [3..3] 单脉冲模式(One Pulse Mode) */
+ __IOM uint32_t DIR : 1; /*!< [4..4] 计数方向(Counter Direction) */
+ __IOM uint32_t CMS : 2; /*!< [6..5] 中心对齐模式(Center-Aligned Mode Selection) */
+ __IOM uint32_t ARE : 1; /*!< [7..7] 自动重载使能(AutoReload Enable) */
+ __IOM uint32_t DCD : 2; /*!< [9..8] 时钟分频(Clock Division) */
+ __IOM uint32_t TI0S : 1; /*!< [10..10] TI0输入选择(TI0 Input Selection) */
+ uint32_t : 21;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+
+ struct {
+ __IOM uint32_t MMS : 3; /*!< [2..0] 主模式选择(Master Mode Selection) */
+ uint32_t : 29;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+
+ struct {
+ __IOM uint32_t SMS : 4; /*!< [3..0] 从模式选择(Slave Mode Selection) */
+ uint32_t : 4;
+ __IOM uint32_t TS : 5; /*!< [12..8] 触发选择(Trigger Selection) */
+ uint32_t : 3;
+ __IOM uint32_t EFS : 4; /*!< [19..16] ETR滤波选择(ETR Filter Selection) */
+ __IOM uint32_t EMS : 2; /*!< [21..20] ETR模式选择(ETR Mode Selection) */
+ __IOM uint32_t EE : 1; /*!< [22..22] ETR控制模式选择(ETR Mode Selection) */
+ uint32_t : 9;
+ } SCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t C0MIE : 1; /*!< [0..0] CH0比较中断使能(CH0 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C0OIE : 1; /*!< [1..1] CH0重复捕获中断使能(CH0 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t C1MIE : 1; /*!< [2..2] CH1比较中断使能(CH1 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C1OIE : 1; /*!< [3..3] CH1重复捕获中断使能(CH1 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t C2MIE : 1; /*!< [4..4] CH2比较中断使能(CH2 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C2OIE : 1; /*!< [5..5] CH2重复捕获中断使能(CH2 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t C3MIE : 1; /*!< [6..6] CH3比较中断使能(CH3 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C3OIE : 1; /*!< [7..7] CH3重复捕获中断使能(CH3 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t UIE : 1; /*!< [8..8] 更新中断使能(Update Interrupt Enable) */
+ __IOM uint32_t OVIE : 1; /*!< [9..9] 计数上溢中断使能(Overflow Interrupt Enable) */
+ __IOM uint32_t TIE : 1; /*!< [10..10] 触发中断使能(Trigger Interrupt Enable) */
+ uint32_t : 21;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+
+ struct {
+ __IOM uint32_t CC0MIF : 1; /*!< [0..0] CC0比较成功中断标志位(CC0 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC0OIF : 1; /*!< [1..1] CC0重复捕获成功中断标志位(CC0 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC1MIF : 1; /*!< [2..2] CC1比较成功中断标志位(CC1 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC1OIF : 1; /*!< [3..3] CC1重复捕获成功中断标志位(CC1 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC2MIF : 1; /*!< [4..4] CC2比较成功中断标志位(CC2 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC2OIF : 1; /*!< [5..5] CC2重复捕获成功中断标志位(CC2 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC3MIF : 1; /*!< [6..6] CC3比较成功中断标志位(CC3 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC3OIF : 1; /*!< [7..7] CC3重复捕获成功中断标志位(CC3 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t UIF : 1; /*!< [8..8] 更新中断标志(Update Interrupt Flag) */
+ __IOM uint32_t OVIF : 1; /*!< [9..9] 计数器上溢中断标志位(Counter Overflow Interrupt
+ Flag) */
+ __IOM uint32_t TIF : 1; /*!< [10..10] 触发中断标志(Trigger Interrupt Flag) */
+ uint32_t : 21;
+ } SR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+
+ struct {
+ __IOM uint32_t UG : 1; /*!< [0..0] 更新事件生成(Update Generation) */
+ __IOM uint32_t TG : 1; /*!< [1..1] 触发事件生成(Trigger Generation) */
+ uint32_t : 2;
+ __IOM uint32_t CC0UG : 1; /*!< [4..4] CC0捕获/比较更新事件生成(CC0 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC1UG : 1; /*!< [5..5] CC1捕获/比较更新事件生成(CC1 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC2UG : 1; /*!< [6..6] CC2捕获/比较更新事件生成(CC2 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC3UG : 1; /*!< [7..7] CC3捕获/比较更新事件生成(CC3 Capture/Compare
+ Update Generation) */
+ uint32_t : 24;
+ } UGR_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+
+ struct {
+ __IOM uint32_t CC0S : 2; /*!< [1..0] CC0捕获/比较方向选择(CC0 Capture Compare Selection) */
+ __IOM uint32_t CC0PE : 2; /*!< [3..2] CC0输入捕获分频/比较自动加载使能(CC0 Compare
+ Auto-Realod Enable) */
+ __IOM uint32_t OC0M : 4; /*!< [7..4] CC0输入滤波/输出比较模式选择(CC0 Input Filter/Output
+ Compare Mode) */
+ __IOM uint32_t CC1S : 2; /*!< [9..8] CC1捕获/比较方向选择(CC1 Capture Compare Selection) */
+ __IOM uint32_t CC1PE : 2; /*!< [11..10] CC1输入捕获分频/比较自动加载使能(CC1
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC1M : 4; /*!< [15..12] CC1输入滤波/输出比较模式选择(CC1 Input
+ Filter/Output Compare Mode) */
+ __IOM uint32_t CC2S : 2; /*!< [17..16] CC2捕获/比较方向选择(CC2 Capture Compare Selection) */
+ __IOM uint32_t CC2PE : 2; /*!< [19..18] CC2输入捕获分频/比较自动加载使能(CC2
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC2M : 4; /*!< [23..20] CC2输入滤波/输出比较模式选择(CC2 Input
+ Filter/Output Compare Mode) */
+ __IOM uint32_t CC3S : 2; /*!< [25..24] CC3捕获/比较方向选择(CC3 Capture Compare Selection) */
+ __IOM uint32_t CC3PE : 2; /*!< [27..26] CC3输入捕获分频/比较自动加载使能(CC3
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC3M : 4; /*!< [31..28] CC3输入滤波/输出比较模式选择(CC3 Input
+ Filter/Output Compare Mode) */
+ } CCMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+
+ struct {
+ __IOM uint32_t CC0E : 1; /*!< [0..0] CC0捕获/比较通道使能(CC0 Capture/Compare Enable) */
+ uint32_t : 1;
+ __IOM uint32_t CC0P : 2; /*!< [3..2] CC0捕获/比较极性选择(CC0 Compare/Capture Polarity) */
+ __IOM uint32_t CC1E : 1; /*!< [4..4] CC1捕获/比较通道使能(CC1 Capture/Compare Enable) */
+ uint32_t : 1;
+ __IOM uint32_t CC1P : 2; /*!< [7..6] CC1捕获/比较极性选择(CC1 Compare/Capture Polarity) */
+ __IOM uint32_t CC2E : 1; /*!< [8..8] CC2捕获/比较通道使能(CC2 Capture/Compare Enable) */
+ uint32_t : 1;
+ __IOM uint32_t CC2P : 2; /*!< [11..10] CC2捕获/比较极性选择(CC2 Compare/Capture Polarity) */
+ __IOM uint32_t CC3E : 1; /*!< [12..12] CC3捕获/比较通道使能(CC3 Capture/Compare Enable) */
+ uint32_t : 1;
+ __IOM uint32_t CC3P : 2; /*!< [15..14] CC3捕获/比较极性选择(CC3 Compare/Capture Polarity) */
+ uint32_t : 16;
+ } CCER_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+
+ struct {
+ __IOM uint32_t TOW : 4; /*!< [3..0] TRGO脉冲宽度控制(Trigger Output Width) */
+ __IOM uint32_t TCW : 4; /*!< [7..4] TRGCC脉冲宽度控制(Trigger Compare/Caputre Width) */
+ __IOM uint32_t TC0E : 1; /*!< [8..8] TRGO CH0输出使能(Trigger CH0 Enable) */
+ __IOM uint32_t TC1E : 1; /*!< [9..9] TRGO CH1输出使能(Trigger CH1 Enable) */
+ __IOM uint32_t TC2E : 1; /*!< [10..10] TRGO CH2输出使能(Trigger CH2 Enable) */
+ __IOM uint32_t TC3E : 1; /*!< [11..11] TRGO CH3输出使能(Trigger CH3 Enable) */
+ uint32_t : 20;
+ } TTCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+
+ struct {
+ __IOM uint32_t CPV : 32; /*!< [31..0] 计数周期值(Counter Period Value) */
+ } CPR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 16; /*!< [15..0] 预分频寄存器（Prescaler Value) */
+ uint32_t : 16;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 32; /*!< [31..0] 定时器计数值(Counter Value) */
+ } CNTR_b;
+ } ;
+ __IM uint32_t RESERVED3[4];
+
+ union {
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+
+ struct {
+ __IOM uint32_t CC0V : 32; /*!< [31..0] CC0捕获/比较值(CC0 Capture/Compare Value) */
+ } CC0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+
+ struct {
+ __IOM uint32_t CC1V : 32; /*!< [31..0] CC1捕获/比较值(CC1 Capture/Compare Value) */
+ } CC1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC2R; /*!< (@ 0x00000058) TMRx Capture Compare Register2 */
+
+ struct {
+ __IOM uint32_t CC2V : 32; /*!< [31..0] CC2捕获/比较值(CC2 Capture/Compare Value) */
+ } CC2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC3R; /*!< (@ 0x0000005C) TMRx Capture Compare Register3 */
+
+ struct {
+ __IOM uint32_t CC3V : 32; /*!< [31..0] CC3捕获/比较值(CC3 Capture/Compare Value) */
+ } CC3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+
+ struct {
+ __IOM uint32_t C0TIS : 4; /*!< [3..0] CH0触发输入选择(CH0 Trigger Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C1TIS : 4; /*!< [11..8] CH1触发输入选择(CH1 Capture Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C2TIS : 4; /*!< [19..16] CH2触发输入选择(CH2 Capture Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C3TIS : 4; /*!< [27..24] CH3触发输入选择(CH3 Capture Input Selection) */
+ uint32_t : 4;
+ } CIR_b;
+ } ;
+} TMR3_Type; /*!< Size = 100 (0x64) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR4 (TMR4)
+ */
+
+typedef struct { /*!< (@ 0x4002B000) TMR4 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 计数器使能位(Counter Enable) */
+ __IOM uint32_t UDIS : 1; /*!< [1..1] 更新禁止位(Update Disable) */
+ __IOM uint32_t URS : 1; /*!< [2..2] 更新事件源(Update Request Source) */
+ __IOM uint32_t OPM : 1; /*!< [3..3] 单脉冲模式(One Pulse Mode) */
+ __IOM uint32_t DIR : 1; /*!< [4..4] 计数方向(Counter Direction) */
+ __IOM uint32_t CMS : 2; /*!< [6..5] 中心对齐模式(Center-Aligned Mode Selection) */
+ __IOM uint32_t ARE : 1; /*!< [7..7] 自动重载使能(AutoReload Enable) */
+ __IOM uint32_t DCD : 2; /*!< [9..8] 时钟分频(Clock Division) */
+ __IOM uint32_t TI0S : 1; /*!< [10..10] TI0输入选择(TI0 Input Selection) */
+ uint32_t : 21;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+
+ struct {
+ __IOM uint32_t MMS : 3; /*!< [2..0] 主模式选择(Master Mode Selection) */
+ uint32_t : 29;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+
+ struct {
+ __IOM uint32_t SMS : 4; /*!< [3..0] 从模式选择(Slave Mode Selection) */
+ uint32_t : 4;
+ __IOM uint32_t TS : 5; /*!< [12..8] 触发选择(Trigger Selection) */
+ uint32_t : 3;
+ __IOM uint32_t EFS : 4; /*!< [19..16] ETR滤波选择(ETR Filter Selection) */
+ __IOM uint32_t EMS : 2; /*!< [21..20] ETR模式选择(ETR Mode Selection) */
+ __IOM uint32_t EE : 1; /*!< [22..22] ETR控制模式选择(ETR Mode Selection) */
+ uint32_t : 9;
+ } SCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t C0MIE : 1; /*!< [0..0] CH0比较中断使能(CH0 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C0OIE : 1; /*!< [1..1] CH0重复捕获中断使能(CH0 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t C1MIE : 1; /*!< [2..2] CH1比较中断使能(CH1 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C1OIE : 1; /*!< [3..3] CH1重复捕获中断使能(CH1 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t C2MIE : 1; /*!< [4..4] CH2比较中断使能(CH2 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C2OIE : 1; /*!< [5..5] CH2重复捕获中断使能(CH2 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t C3MIE : 1; /*!< [6..6] CH3比较中断使能(CH3 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C3OIE : 1; /*!< [7..7] CH3重复捕获中断使能(CH3 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t UIE : 1; /*!< [8..8] 更新中断使能(Update Interrupt Enable) */
+ __IOM uint32_t OVIE : 1; /*!< [9..9] 计数上溢中断使能(Overflow Interrupt Enable) */
+ __IOM uint32_t TIE : 1; /*!< [10..10] 触发中断使能(Trigger Interrupt Enable) */
+ uint32_t : 21;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+
+ struct {
+ __IOM uint32_t CC0MIF : 1; /*!< [0..0] CC0比较成功中断标志位(CC0 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC0OIF : 1; /*!< [1..1] CC0重复捕获成功中断标志位(CC0 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC1MIF : 1; /*!< [2..2] CC1比较成功中断标志位(CC1 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC1OIF : 1; /*!< [3..3] CC1重复捕获成功中断标志位(CC1 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC2MIF : 1; /*!< [4..4] CC2比较成功中断标志位(CC2 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC2OIF : 1; /*!< [5..5] CC2重复捕获成功中断标志位(CC2 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC3MIF : 1; /*!< [6..6] CC3比较成功中断标志位(CC3 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC3OIF : 1; /*!< [7..7] CC3重复捕获成功中断标志位(CC3 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t UIF : 1; /*!< [8..8] 更新中断标志(Update Interrupt Flag) */
+ __IOM uint32_t OVIF : 1; /*!< [9..9] 计数器上溢中断标志位(Counter Overflow Interrupt
+ Flag) */
+ __IOM uint32_t TIF : 1; /*!< [10..10] 触发中断标志(Trigger Interrupt Flag) */
+ uint32_t : 21;
+ } SR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+
+ struct {
+ __IOM uint32_t UG : 1; /*!< [0..0] 更新事件生成(Update Generation) */
+ __IOM uint32_t TG : 1; /*!< [1..1] 触发事件生成(Trigger Generation) */
+ uint32_t : 2;
+ __IOM uint32_t CC0UG : 1; /*!< [4..4] CC0捕获/比较更新事件生成(CC0 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC1UG : 1; /*!< [5..5] CC1捕获/比较更新事件生成(CC1 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC2UG : 1; /*!< [6..6] CC2捕获/比较更新事件生成(CC2 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC3UG : 1; /*!< [7..7] CC3捕获/比较更新事件生成(CC3 Capture/Compare
+ Update Generation) */
+ uint32_t : 24;
+ } UGR_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+
+ struct {
+ __IOM uint32_t CC0S : 2; /*!< [1..0] CC0捕获/比较方向选择(CC0 Capture Compare Selection) */
+ __IOM uint32_t CC0PE : 2; /*!< [3..2] CC0输入捕获分频/比较自动加载使能(CC0 Compare
+ Auto-Realod Enable) */
+ __IOM uint32_t OC0M : 4; /*!< [7..4] CC0输入滤波/输出比较模式选择(CC0 Input Filter/Output
+ Compare Mode) */
+ __IOM uint32_t CC1S : 2; /*!< [9..8] CC1捕获/比较方向选择(CC1 Capture Compare Selection) */
+ __IOM uint32_t CC1PE : 2; /*!< [11..10] CC1输入捕获分频/比较自动加载使能(CC1
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC1M : 4; /*!< [15..12] CC1输入滤波/输出比较模式选择(CC1 Input
+ Filter/Output Compare Mode) */
+ __IOM uint32_t CC2S : 2; /*!< [17..16] CC2捕获/比较方向选择(CC2 Capture Compare Selection) */
+ __IOM uint32_t CC2PE : 2; /*!< [19..18] CC2输入捕获分频/比较自动加载使能(CC2
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC2M : 4; /*!< [23..20] CC2输入滤波/输出比较模式选择(CC2 Input
+ Filter/Output Compare Mode) */
+ __IOM uint32_t CC3S : 2; /*!< [25..24] CC3捕获/比较方向选择(CC3 Capture Compare Selection) */
+ __IOM uint32_t CC3PE : 2; /*!< [27..26] CC3输入捕获分频/比较自动加载使能(CC3
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC3M : 4; /*!< [31..28] CC3输入滤波/输出比较模式选择(CC3 Input
+ Filter/Output Compare Mode) */
+ } CCMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+
+ struct {
+ __IOM uint32_t CC0E : 1; /*!< [0..0] CC0捕获/比较通道使能(CC0 Capture/Compare Enable) */
+ uint32_t : 1;
+ __IOM uint32_t CC0P : 2; /*!< [3..2] CC0捕获/比较极性选择(CC0 Compare/Capture Polarity) */
+ __IOM uint32_t CC1E : 1; /*!< [4..4] CC1捕获/比较通道使能(CC1 Capture/Compare Enable) */
+ uint32_t : 1;
+ __IOM uint32_t CC1P : 2; /*!< [7..6] CC1捕获/比较极性选择(CC1 Compare/Capture Polarity) */
+ __IOM uint32_t CC2E : 1; /*!< [8..8] CC2捕获/比较通道使能(CC2 Capture/Compare Enable) */
+ uint32_t : 1;
+ __IOM uint32_t CC2P : 2; /*!< [11..10] CC2捕获/比较极性选择(CC2 Compare/Capture Polarity) */
+ __IOM uint32_t CC3E : 1; /*!< [12..12] CC3捕获/比较通道使能(CC3 Capture/Compare Enable) */
+ uint32_t : 1;
+ __IOM uint32_t CC3P : 2; /*!< [15..14] CC3捕获/比较极性选择(CC3 Compare/Capture Polarity) */
+ uint32_t : 16;
+ } CCER_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+
+ struct {
+ __IOM uint32_t TOW : 4; /*!< [3..0] TRGO脉冲宽度控制(Trigger Output Width) */
+ __IOM uint32_t TCW : 4; /*!< [7..4] TRGCC脉冲宽度控制(Trigger Compare/Caputre Width) */
+ __IOM uint32_t TC0E : 1; /*!< [8..8] TRGO CH0输出使能(Trigger CH0 Enable) */
+ __IOM uint32_t TC1E : 1; /*!< [9..9] TRGO CH1输出使能(Trigger CH1 Enable) */
+ __IOM uint32_t TC2E : 1; /*!< [10..10] TRGO CH2输出使能(Trigger CH2 Enable) */
+ __IOM uint32_t TC3E : 1; /*!< [11..11] TRGO CH3输出使能(Trigger CH3 Enable) */
+ uint32_t : 20;
+ } TTCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+
+ struct {
+ __IOM uint32_t CPV : 32; /*!< [31..0] 计数周期值(Counter Period Value) */
+ } CPR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 16; /*!< [15..0] 预分频寄存器（Prescaler Value) */
+ uint32_t : 16;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 32; /*!< [31..0] 定时器计数值(Counter Value) */
+ } CNTR_b;
+ } ;
+ __IM uint32_t RESERVED3[4];
+
+ union {
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+
+ struct {
+ __IOM uint32_t CC0V : 32; /*!< [31..0] CC0捕获/比较值(CC0 Capture/Compare Value) */
+ } CC0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+
+ struct {
+ __IOM uint32_t CC1V : 32; /*!< [31..0] CC1捕获/比较值(CC1 Capture/Compare Value) */
+ } CC1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC2R; /*!< (@ 0x00000058) TMRx Capture Compare Register2 */
+
+ struct {
+ __IOM uint32_t CC2V : 32; /*!< [31..0] CC2捕获/比较值(CC2 Capture/Compare Value) */
+ } CC2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC3R; /*!< (@ 0x0000005C) TMRx Capture Compare Register3 */
+
+ struct {
+ __IOM uint32_t CC3V : 32; /*!< [31..0] CC3捕获/比较值(CC3 Capture/Compare Value) */
+ } CC3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+
+ struct {
+ __IOM uint32_t C0TIS : 4; /*!< [3..0] CH0触发输入选择(CH0 Trigger Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C1TIS : 4; /*!< [11..8] CH1触发输入选择(CH1 Capture Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C2TIS : 4; /*!< [19..16] CH2触发输入选择(CH2 Capture Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C3TIS : 4; /*!< [27..24] CH3触发输入选择(CH3 Capture Input Selection) */
+ uint32_t : 4;
+ } CIR_b;
+ } ;
+} TMR4_Type; /*!< Size = 100 (0x64) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR0 (TMR0)
+ */
+
+typedef struct { /*!< (@ 0x40018000) TMR0 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 计数器使能位(Counter Enable) */
+ __IOM uint32_t UDIS : 1; /*!< [1..1] 更新禁止位(Update Disable) */
+ __IOM uint32_t URS : 1; /*!< [2..2] 更新事件源(Update Request Source) */
+ __IOM uint32_t OPM : 1; /*!< [3..3] 单脉冲模式(One Pulse Mode) */
+ uint32_t : 3;
+ __IOM uint32_t ARE : 1; /*!< [7..7] 自动重载使能(AutoReload Enable) */
+ __IOM uint32_t DCD : 2; /*!< [9..8] 时钟分频(Clock Division) */
+ __IOM uint32_t TI0S : 1; /*!< [10..10] TI0输入选择(TI0 Input Selection) */
+ uint32_t : 21;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+
+ struct {
+ __IOM uint32_t MMS : 3; /*!< [2..0] 主模式选择(Master Mode Selection) */
+ uint32_t : 5;
+ __IOM uint32_t OIS0 : 1; /*!< [8..8] CH0空闲状态输出电平(CH0 Output Idle-State) */
+ __IOM uint32_t OIS0N : 1; /*!< [9..9] CH0N空闲状态输出电平(CH0N Output Idle-State) */
+ __IOM uint32_t OIS1 : 1; /*!< [10..10] CH1空闲状态输出电平(CH1 Output Idle-State) */
+ __IOM uint32_t OIS1N : 1; /*!< [11..11] CH1N空闲状态输出电平(CH1N Output Idle-State) */
+ uint32_t : 20;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+
+ struct {
+ __IOM uint32_t SMS : 4; /*!< [3..0] 从模式选择(Slave Mode Selection) */
+ uint32_t : 3;
+ __IOM uint32_t FE : 1; /*!< [7..7] 主从快速同步使能(Master/Slave Fast-Sync Enable) */
+ __IOM uint32_t TS : 5; /*!< [12..8] 触发选择(Trigger Selection) */
+ uint32_t : 19;
+ } SCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t C0MIE : 1; /*!< [0..0] CH0比较中断使能(CH0 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C0OIE : 1; /*!< [1..1] CH0重复捕获中断使能(CH0 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t C1MIE : 1; /*!< [2..2] CH1比较中断使能(CH1 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C1OIE : 1; /*!< [3..3] CH1重复捕获中断使能(CH1 OverCapture Interrupt
+ Enable) */
+ uint32_t : 4;
+ __IOM uint32_t UIE : 1; /*!< [8..8] 更新中断使能(Update Interrupt Enable) */
+ __IOM uint32_t OVIE : 1; /*!< [9..9] 计数上溢中断使能(Overflow Interrupt Enable) */
+ __IOM uint32_t TIE : 1; /*!< [10..10] 触发中断使能(Trigger Interrupt Enable) */
+ __IOM uint32_t BIE : 1; /*!< [11..11] 断路中断使能(Break Interrupt Enable) */
+ uint32_t : 20;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+
+ struct {
+ __IOM uint32_t CC0MIF : 1; /*!< [0..0] CC0比较成功中断标志位(CC0 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC0OIF : 1; /*!< [1..1] CC0重复捕获成功中断标志位(CC0 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC1MIF : 1; /*!< [2..2] CC1比较成功中断标志位(CC1 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC1OIF : 1; /*!< [3..3] CC1重复捕获成功中断标志位(CC1 OverCapture
+ Interrupt Flag) */
+ uint32_t : 4;
+ __IOM uint32_t UIF : 1; /*!< [8..8] 更新中断标志(Update Interrupt Flag) */
+ __IOM uint32_t OVIF : 1; /*!< [9..9] 计数器上溢中断标志位(Counter Overflow Interrupt
+ Flag) */
+ __IOM uint32_t TIF : 1; /*!< [10..10] 触发中断标志(Trigger Interrupt Flag) */
+ __IOM uint32_t BIF : 1; /*!< [11..11] 断路中断标志位(Break Interrupt Flag) */
+ __IOM uint32_t SBIF : 1; /*!< [12..12] 系统断路中断标志位(System Fault Break Interrupt
+ Flag) */
+ uint32_t : 19;
+ } SR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+
+ struct {
+ __IOM uint32_t UG : 1; /*!< [0..0] 更新事件生成(Update Generation) */
+ __IOM uint32_t TG : 1; /*!< [1..1] 触发事件生成(Trigger Generation) */
+ __IOM uint32_t BG : 1; /*!< [2..2] 断路事件生成(Break Generation) */
+ uint32_t : 1;
+ __IOM uint32_t CC0UG : 1; /*!< [4..4] CC0捕获/比较更新事件生成(CC0 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC1UG : 1; /*!< [5..5] CC1捕获/比较更新事件生成(CC1 Capture/Compare
+ Update Generation) */
+ uint32_t : 26;
+ } UGR_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+
+ struct {
+ __IOM uint32_t CC0S : 2; /*!< [1..0] CC0捕获/比较方向选择(CC0 Capture Compare Selection) */
+ __IOM uint32_t CC0PE : 2; /*!< [3..2] CC0输入捕获分频/比较自动加载使能(CC0 Compare
+ Auto-Realod Enable) */
+ __IOM uint32_t OC0M : 4; /*!< [7..4] CC0输入滤波/输出比较模式选择(CC0 Input Filter/Output
+ Compare Mode) */
+ __IOM uint32_t CC1S : 2; /*!< [9..8] CC1捕获/比较方向选择(CC1 Capture Compare Selection) */
+ __IOM uint32_t CC1PE : 2; /*!< [11..10] CC1输入捕获分频/比较自动加载使能(CC1
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC1M : 4; /*!< [15..12] CC1输入滤波/输出比较模式选择(CC1 Input
+ Filter/Output Compare Mode) */
+ uint32_t : 16;
+ } CCMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+
+ struct {
+ __IOM uint32_t CC0E : 1; /*!< [0..0] CC0捕获/比较通道使能(CC0 Capture/Compare Enable) */
+ __IOM uint32_t CC0NE : 1; /*!< [1..1] CC0N捕获/比较互补通道使能(CC0N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC0P : 2; /*!< [3..2] CC0捕获/比较极性选择(CC0 Compare/Capture Polarity) */
+ __IOM uint32_t CC1E : 1; /*!< [4..4] CC1捕获/比较通道使能(CC1 Capture/Compare Enable) */
+ __IOM uint32_t CC1NE : 1; /*!< [5..5] CC1N捕获/比较互补通道使能(CC1N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC1P : 2; /*!< [7..6] CC1捕获/比较极性选择(CC1 Compare/Capture Polarity) */
+ uint32_t : 24;
+ } CCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DCR; /*!< (@ 0x00000028) TMRx Dead-Time Contorl Register */
+
+ struct {
+ __IOM uint32_t DTG : 8; /*!< [7..0] 配置死区时间选择(Dead-Time Generator Setup) */
+ __IOM uint32_t OSSI : 1; /*!< [8..8] 空闲模式下关闭状态选择(Off-State Selection
+ for Idle-Mode) */
+ __IOM uint32_t OSSR : 1; /*!< [9..9] 运行模式下关闭状态选择(Off-State Selection
+ for Run-Mode) */
+ __IOM uint32_t AOE : 1; /*!< [10..10] 自动输出使能(Automatic Output Enable) */
+ __IOM uint32_t MOE : 1; /*!< [11..11] 主路输出使能(Main Output Enable) */
+ __IOM uint32_t BKE : 1; /*!< [12..12] 断路控制使能(Break Enable) */
+ __IOM uint32_t BKP : 1; /*!< [13..13] 断路输入极性(Break Polarity) */
+ __IOM uint32_t BKF : 8; /*!< [21..14] 断路滤波器(Break Filter) */
+ uint32_t : 10;
+ } DCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+
+ struct {
+ __IOM uint32_t TOW : 4; /*!< [3..0] TRGO脉冲宽度控制(Trigger Output Width) */
+ __IOM uint32_t TCW : 4; /*!< [7..4] TRGCC脉冲宽度控制(Trigger Compare/Caputre Width) */
+ __IOM uint32_t TC0E : 1; /*!< [8..8] TRGO CH0输出使能(Trigger CH0 Enable) */
+ __IOM uint32_t TC1E : 1; /*!< [9..9] TRGO CH1输出使能(Trigger CH1 Enable) */
+ uint32_t : 22;
+ } TTCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+
+ struct {
+ __IOM uint32_t CPV : 16; /*!< [15..0] 计数周期值(Counter Period Value) */
+ uint32_t : 16;
+ } CPR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 16; /*!< [15..0] 预分频寄存器（Prescaler Value) */
+ uint32_t : 16;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] 定时器计数值(Counter Value) */
+ uint32_t : 16;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CRR; /*!< (@ 0x00000040) TMRx Counter Repeat Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] 重复计数值(Counter Repeat Value) */
+ uint32_t : 24;
+ } CRR_b;
+ } ;
+ __IM uint32_t RESERVED2[3];
+
+ union {
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+
+ struct {
+ __IOM uint32_t CC0V : 16; /*!< [15..0] CC0捕获/比较值(CC0 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+
+ struct {
+ __IOM uint32_t CC1V : 16; /*!< [15..0] CC1捕获/比较值(CC1 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC1R_b;
+ } ;
+ __IM uint32_t RESERVED3[2];
+
+ union {
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+
+ struct {
+ __IOM uint32_t C0TIS : 4; /*!< [3..0] CH0触发输入选择(CH0 Trigger Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C1TIS : 4; /*!< [11..8] CH1触发输入选择(CH1 Capture Input Selection) */
+ uint32_t : 20;
+ } CIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BPR; /*!< (@ 0x00000064) TMRx Break Polarity Register */
+
+ struct {
+ __IOM uint32_t BPOL : 16; /*!< [15..0] Break输入极性选择(Break Input Polarity Selection) */
+ uint32_t : 16;
+ } BPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BER; /*!< (@ 0x00000068) TMRx Break Enable Register */
+
+ struct {
+ __IOM uint32_t BIEN : 16; /*!< [15..0] Break输入使能控制(Break Input Enable) */
+ uint32_t : 16;
+ } BER_b;
+ } ;
+} TMR0_Type; /*!< Size = 108 (0x6c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR1 (TMR1)
+ */
+
+typedef struct { /*!< (@ 0x40019000) TMR1 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 计数器使能位(Counter Enable) */
+ __IOM uint32_t UDIS : 1; /*!< [1..1] 更新禁止位(Update Disable) */
+ __IOM uint32_t URS : 1; /*!< [2..2] 更新事件源(Update Request Source) */
+ __IOM uint32_t OPM : 1; /*!< [3..3] 单脉冲模式(One Pulse Mode) */
+ uint32_t : 3;
+ __IOM uint32_t ARE : 1; /*!< [7..7] 自动重载使能(AutoReload Enable) */
+ __IOM uint32_t DCD : 2; /*!< [9..8] 时钟分频(Clock Division) */
+ __IOM uint32_t TI0S : 1; /*!< [10..10] TI0输入选择(TI0 Input Selection) */
+ uint32_t : 21;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+
+ struct {
+ __IOM uint32_t MMS : 3; /*!< [2..0] 主模式选择(Master Mode Selection) */
+ uint32_t : 5;
+ __IOM uint32_t OIS0 : 1; /*!< [8..8] CH0空闲状态输出电平(CH0 Output Idle-State) */
+ __IOM uint32_t OIS0N : 1; /*!< [9..9] CH0N空闲状态输出电平(CH0N Output Idle-State) */
+ __IOM uint32_t OIS1 : 1; /*!< [10..10] CH1空闲状态输出电平(CH1 Output Idle-State) */
+ __IOM uint32_t OIS1N : 1; /*!< [11..11] CH1N空闲状态输出电平(CH1N Output Idle-State) */
+ uint32_t : 20;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+
+ struct {
+ __IOM uint32_t SMS : 4; /*!< [3..0] 从模式选择(Slave Mode Selection) */
+ uint32_t : 3;
+ __IOM uint32_t FE : 1; /*!< [7..7] 主从快速同步使能(Master/Slave Fast-Sync Enable) */
+ __IOM uint32_t TS : 5; /*!< [12..8] 触发选择(Trigger Selection) */
+ uint32_t : 19;
+ } SCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t C0MIE : 1; /*!< [0..0] CH0比较中断使能(CH0 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C0OIE : 1; /*!< [1..1] CH0重复捕获中断使能(CH0 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t C1MIE : 1; /*!< [2..2] CH1比较中断使能(CH1 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C1OIE : 1; /*!< [3..3] CH1重复捕获中断使能(CH1 OverCapture Interrupt
+ Enable) */
+ uint32_t : 4;
+ __IOM uint32_t UIE : 1; /*!< [8..8] 更新中断使能(Update Interrupt Enable) */
+ __IOM uint32_t OVIE : 1; /*!< [9..9] 计数上溢中断使能(Overflow Interrupt Enable) */
+ __IOM uint32_t TIE : 1; /*!< [10..10] 触发中断使能(Trigger Interrupt Enable) */
+ __IOM uint32_t BIE : 1; /*!< [11..11] 断路中断使能(Break Interrupt Enable) */
+ uint32_t : 20;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+
+ struct {
+ __IOM uint32_t CC0MIF : 1; /*!< [0..0] CC0比较成功中断标志位(CC0 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC0OIF : 1; /*!< [1..1] CC0重复捕获成功中断标志位(CC0 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC1MIF : 1; /*!< [2..2] CC1比较成功中断标志位(CC1 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC1OIF : 1; /*!< [3..3] CC1重复捕获成功中断标志位(CC1 OverCapture
+ Interrupt Flag) */
+ uint32_t : 4;
+ __IOM uint32_t UIF : 1; /*!< [8..8] 更新中断标志(Update Interrupt Flag) */
+ __IOM uint32_t OVIF : 1; /*!< [9..9] 计数器上溢中断标志位(Counter Overflow Interrupt
+ Flag) */
+ __IOM uint32_t TIF : 1; /*!< [10..10] 触发中断标志(Trigger Interrupt Flag) */
+ __IOM uint32_t BIF : 1; /*!< [11..11] 断路中断标志位(Break Interrupt Flag) */
+ __IOM uint32_t SBIF : 1; /*!< [12..12] 系统断路中断标志位(System Fault Break Interrupt
+ Flag) */
+ uint32_t : 19;
+ } SR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+
+ struct {
+ __IOM uint32_t UG : 1; /*!< [0..0] 更新事件生成(Update Generation) */
+ __IOM uint32_t TG : 1; /*!< [1..1] 触发事件生成(Trigger Generation) */
+ __IOM uint32_t BG : 1; /*!< [2..2] 断路事件生成(Break Generation) */
+ uint32_t : 1;
+ __IOM uint32_t CC0UG : 1; /*!< [4..4] CC0捕获/比较更新事件生成(CC0 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC1UG : 1; /*!< [5..5] CC1捕获/比较更新事件生成(CC1 Capture/Compare
+ Update Generation) */
+ uint32_t : 26;
+ } UGR_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+
+ struct {
+ __IOM uint32_t CC0S : 2; /*!< [1..0] CC0捕获/比较方向选择(CC0 Capture Compare Selection) */
+ __IOM uint32_t CC0PE : 2; /*!< [3..2] CC0输入捕获分频/比较自动加载使能(CC0 Compare
+ Auto-Realod Enable) */
+ __IOM uint32_t OC0M : 4; /*!< [7..4] CC0输入滤波/输出比较模式选择(CC0 Input Filter/Output
+ Compare Mode) */
+ __IOM uint32_t CC1S : 2; /*!< [9..8] CC1捕获/比较方向选择(CC1 Capture Compare Selection) */
+ __IOM uint32_t CC1PE : 2; /*!< [11..10] CC1输入捕获分频/比较自动加载使能(CC1
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC1M : 4; /*!< [15..12] CC1输入滤波/输出比较模式选择(CC1 Input
+ Filter/Output Compare Mode) */
+ uint32_t : 16;
+ } CCMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+
+ struct {
+ __IOM uint32_t CC0E : 1; /*!< [0..0] CC0捕获/比较通道使能(CC0 Capture/Compare Enable) */
+ __IOM uint32_t CC0NE : 1; /*!< [1..1] CC0N捕获/比较互补通道使能(CC0N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC0P : 2; /*!< [3..2] CC0捕获/比较极性选择(CC0 Compare/Capture Polarity) */
+ __IOM uint32_t CC1E : 1; /*!< [4..4] CC1捕获/比较通道使能(CC1 Capture/Compare Enable) */
+ __IOM uint32_t CC1NE : 1; /*!< [5..5] CC1N捕获/比较互补通道使能(CC1N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC1P : 2; /*!< [7..6] CC1捕获/比较极性选择(CC1 Compare/Capture Polarity) */
+ uint32_t : 24;
+ } CCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DCR; /*!< (@ 0x00000028) TMRx Dead-Time Contorl Register */
+
+ struct {
+ __IOM uint32_t DTG : 8; /*!< [7..0] 配置死区时间选择(Dead-Time Generator Setup) */
+ __IOM uint32_t OSSI : 1; /*!< [8..8] 空闲模式下关闭状态选择(Off-State Selection
+ for Idle-Mode) */
+ __IOM uint32_t OSSR : 1; /*!< [9..9] 运行模式下关闭状态选择(Off-State Selection
+ for Run-Mode) */
+ __IOM uint32_t AOE : 1; /*!< [10..10] 自动输出使能(Automatic Output Enable) */
+ __IOM uint32_t MOE : 1; /*!< [11..11] 主路输出使能(Main Output Enable) */
+ __IOM uint32_t BKE : 1; /*!< [12..12] 断路控制使能(Break Enable) */
+ __IOM uint32_t BKP : 1; /*!< [13..13] 断路输入极性(Break Polarity) */
+ __IOM uint32_t BKF : 8; /*!< [21..14] 断路滤波器(Break Filter) */
+ uint32_t : 10;
+ } DCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+
+ struct {
+ __IOM uint32_t TOW : 4; /*!< [3..0] TRGO脉冲宽度控制(Trigger Output Width) */
+ __IOM uint32_t TCW : 4; /*!< [7..4] TRGCC脉冲宽度控制(Trigger Compare/Caputre Width) */
+ __IOM uint32_t TC0E : 1; /*!< [8..8] TRGO CH0输出使能(Trigger CH0 Enable) */
+ __IOM uint32_t TC1E : 1; /*!< [9..9] TRGO CH1输出使能(Trigger CH1 Enable) */
+ uint32_t : 22;
+ } TTCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+
+ struct {
+ __IOM uint32_t CPV : 16; /*!< [15..0] 计数周期值(Counter Period Value) */
+ uint32_t : 16;
+ } CPR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 16; /*!< [15..0] 预分频寄存器（Prescaler Value) */
+ uint32_t : 16;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] 定时器计数值(Counter Value) */
+ uint32_t : 16;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CRR; /*!< (@ 0x00000040) TMRx Counter Repeat Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] 重复计数值(Counter Repeat Value) */
+ uint32_t : 24;
+ } CRR_b;
+ } ;
+ __IM uint32_t RESERVED2[3];
+
+ union {
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+
+ struct {
+ __IOM uint32_t CC0V : 16; /*!< [15..0] CC0捕获/比较值(CC0 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+
+ struct {
+ __IOM uint32_t CC1V : 16; /*!< [15..0] CC1捕获/比较值(CC1 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC1R_b;
+ } ;
+ __IM uint32_t RESERVED3[2];
+
+ union {
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+
+ struct {
+ __IOM uint32_t C0TIS : 4; /*!< [3..0] CH0触发输入选择(CH0 Trigger Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C1TIS : 4; /*!< [11..8] CH1触发输入选择(CH1 Capture Input Selection) */
+ uint32_t : 20;
+ } CIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BPR; /*!< (@ 0x00000064) TMRx Break Polarity Register */
+
+ struct {
+ __IOM uint32_t BPOL : 16; /*!< [15..0] Break输入极性选择(Break Input Polarity Selection) */
+ uint32_t : 16;
+ } BPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BER; /*!< (@ 0x00000068) TMRx Break Enable Register */
+
+ struct {
+ __IOM uint32_t BIEN : 16; /*!< [15..0] Break输入使能控制(Break Input Enable) */
+ uint32_t : 16;
+ } BER_b;
+ } ;
+} TMR1_Type; /*!< Size = 108 (0x6c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR2 (TMR2)
+ */
+
+typedef struct { /*!< (@ 0x4001A000) TMR2 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 计数器使能位(Counter Enable) */
+ __IOM uint32_t UDIS : 1; /*!< [1..1] 更新禁止位(Update Disable) */
+ __IOM uint32_t URS : 1; /*!< [2..2] 更新事件源(Update Request Source) */
+ __IOM uint32_t OPM : 1; /*!< [3..3] 单脉冲模式(One Pulse Mode) */
+ uint32_t : 3;
+ __IOM uint32_t ARE : 1; /*!< [7..7] 自动重载使能(AutoReload Enable) */
+ __IOM uint32_t DCD : 2; /*!< [9..8] 时钟分频(Clock Division) */
+ __IOM uint32_t TI0S : 1; /*!< [10..10] TI0输入选择(TI0 Input Selection) */
+ uint32_t : 21;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+
+ struct {
+ __IOM uint32_t MMS : 3; /*!< [2..0] 主模式选择(Master Mode Selection) */
+ uint32_t : 5;
+ __IOM uint32_t OIS0 : 1; /*!< [8..8] CH0空闲状态输出电平(CH0 Output Idle-State) */
+ __IOM uint32_t OIS0N : 1; /*!< [9..9] CH0N空闲状态输出电平(CH0N Output Idle-State) */
+ __IOM uint32_t OIS1 : 1; /*!< [10..10] CH1空闲状态输出电平(CH1 Output Idle-State) */
+ __IOM uint32_t OIS1N : 1; /*!< [11..11] CH1N空闲状态输出电平(CH1N Output Idle-State) */
+ uint32_t : 20;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+
+ struct {
+ __IOM uint32_t SMS : 4; /*!< [3..0] 从模式选择(Slave Mode Selection) */
+ uint32_t : 3;
+ __IOM uint32_t FE : 1; /*!< [7..7] 主从快速同步使能(Master/Slave Fast-Sync Enable) */
+ __IOM uint32_t TS : 5; /*!< [12..8] 触发选择(Trigger Selection) */
+ uint32_t : 19;
+ } SCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t C0MIE : 1; /*!< [0..0] CH0比较中断使能(CH0 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C0OIE : 1; /*!< [1..1] CH0重复捕获中断使能(CH0 OverCapture Interrupt
+ Enable) */
+ __IOM uint32_t C1MIE : 1; /*!< [2..2] CH1比较中断使能(CH1 Capture/Compare Interrupt Enable) */
+ __IOM uint32_t C1OIE : 1; /*!< [3..3] CH1重复捕获中断使能(CH1 OverCapture Interrupt
+ Enable) */
+ uint32_t : 4;
+ __IOM uint32_t UIE : 1; /*!< [8..8] 更新中断使能(Update Interrupt Enable) */
+ __IOM uint32_t OVIE : 1; /*!< [9..9] 计数上溢中断使能(Overflow Interrupt Enable) */
+ __IOM uint32_t TIE : 1; /*!< [10..10] 触发中断使能(Trigger Interrupt Enable) */
+ __IOM uint32_t BIE : 1; /*!< [11..11] 断路中断使能(Break Interrupt Enable) */
+ uint32_t : 20;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+
+ struct {
+ __IOM uint32_t CC0MIF : 1; /*!< [0..0] CC0比较成功中断标志位(CC0 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC0OIF : 1; /*!< [1..1] CC0重复捕获成功中断标志位(CC0 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC1MIF : 1; /*!< [2..2] CC1比较成功中断标志位(CC1 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC1OIF : 1; /*!< [3..3] CC1重复捕获成功中断标志位(CC1 OverCapture
+ Interrupt Flag) */
+ uint32_t : 4;
+ __IOM uint32_t UIF : 1; /*!< [8..8] 更新中断标志(Update Interrupt Flag) */
+ __IOM uint32_t OVIF : 1; /*!< [9..9] 计数器上溢中断标志位(Counter Overflow Interrupt
+ Flag) */
+ __IOM uint32_t TIF : 1; /*!< [10..10] 触发中断标志(Trigger Interrupt Flag) */
+ __IOM uint32_t BIF : 1; /*!< [11..11] 断路中断标志位(Break Interrupt Flag) */
+ __IOM uint32_t SBIF : 1; /*!< [12..12] 系统断路中断标志位(System Fault Break Interrupt
+ Flag) */
+ uint32_t : 19;
+ } SR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+
+ struct {
+ __IOM uint32_t UG : 1; /*!< [0..0] 更新事件生成(Update Generation) */
+ __IOM uint32_t TG : 1; /*!< [1..1] 触发事件生成(Trigger Generation) */
+ __IOM uint32_t BG : 1; /*!< [2..2] 断路事件生成(Break Generation) */
+ uint32_t : 1;
+ __IOM uint32_t CC0UG : 1; /*!< [4..4] CC0捕获/比较更新事件生成(CC0 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC1UG : 1; /*!< [5..5] CC1捕获/比较更新事件生成(CC1 Capture/Compare
+ Update Generation) */
+ uint32_t : 26;
+ } UGR_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+
+ struct {
+ __IOM uint32_t CC0S : 2; /*!< [1..0] CC0捕获/比较方向选择(CC0 Capture Compare Selection) */
+ __IOM uint32_t CC0PE : 2; /*!< [3..2] CC0输入捕获分频/比较自动加载使能(CC0 Compare
+ Auto-Realod Enable) */
+ __IOM uint32_t OC0M : 4; /*!< [7..4] CC0输入滤波/输出比较模式选择(CC0 Input Filter/Output
+ Compare Mode) */
+ __IOM uint32_t CC1S : 2; /*!< [9..8] CC1捕获/比较方向选择(CC1 Capture Compare Selection) */
+ __IOM uint32_t CC1PE : 2; /*!< [11..10] CC1输入捕获分频/比较自动加载使能(CC1
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC1M : 4; /*!< [15..12] CC1输入滤波/输出比较模式选择(CC1 Input
+ Filter/Output Compare Mode) */
+ uint32_t : 16;
+ } CCMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+
+ struct {
+ __IOM uint32_t CC0E : 1; /*!< [0..0] CC0捕获/比较通道使能(CC0 Capture/Compare Enable) */
+ __IOM uint32_t CC0NE : 1; /*!< [1..1] CC0N捕获/比较互补通道使能(CC0N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC0P : 2; /*!< [3..2] CC0捕获/比较极性选择(CC0 Compare/Capture Polarity) */
+ __IOM uint32_t CC1E : 1; /*!< [4..4] CC1捕获/比较通道使能(CC1 Capture/Compare Enable) */
+ __IOM uint32_t CC1NE : 1; /*!< [5..5] CC1N捕获/比较互补通道使能(CC1N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC1P : 2; /*!< [7..6] CC1捕获/比较极性选择(CC1 Compare/Capture Polarity) */
+ uint32_t : 24;
+ } CCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DCR; /*!< (@ 0x00000028) TMRx Dead-Time Contorl Register */
+
+ struct {
+ __IOM uint32_t DTG : 8; /*!< [7..0] 配置死区时间选择(Dead-Time Generator Setup) */
+ __IOM uint32_t OSSI : 1; /*!< [8..8] 空闲模式下关闭状态选择(Off-State Selection
+ for Idle-Mode) */
+ __IOM uint32_t OSSR : 1; /*!< [9..9] 运行模式下关闭状态选择(Off-State Selection
+ for Run-Mode) */
+ __IOM uint32_t AOE : 1; /*!< [10..10] 自动输出使能(Automatic Output Enable) */
+ __IOM uint32_t MOE : 1; /*!< [11..11] 主路输出使能(Main Output Enable) */
+ __IOM uint32_t BKE : 1; /*!< [12..12] 断路控制使能(Break Enable) */
+ __IOM uint32_t BKP : 1; /*!< [13..13] 断路输入极性(Break Polarity) */
+ __IOM uint32_t BKF : 8; /*!< [21..14] 断路滤波器(Break Filter) */
+ uint32_t : 10;
+ } DCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+
+ struct {
+ __IOM uint32_t TOW : 4; /*!< [3..0] TRGO脉冲宽度控制(Trigger Output Width) */
+ __IOM uint32_t TCW : 4; /*!< [7..4] TRGCC脉冲宽度控制(Trigger Compare/Caputre Width) */
+ __IOM uint32_t TC0E : 1; /*!< [8..8] TRGO CH0输出使能(Trigger CH0 Enable) */
+ __IOM uint32_t TC1E : 1; /*!< [9..9] TRGO CH1输出使能(Trigger CH1 Enable) */
+ uint32_t : 22;
+ } TTCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+
+ struct {
+ __IOM uint32_t CPV : 16; /*!< [15..0] 计数周期值(Counter Period Value) */
+ uint32_t : 16;
+ } CPR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 16; /*!< [15..0] 预分频寄存器（Prescaler Value) */
+ uint32_t : 16;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] 定时器计数值(Counter Value) */
+ uint32_t : 16;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CRR; /*!< (@ 0x00000040) TMRx Counter Repeat Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] 重复计数值(Counter Repeat Value) */
+ uint32_t : 24;
+ } CRR_b;
+ } ;
+ __IM uint32_t RESERVED2[3];
+
+ union {
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+
+ struct {
+ __IOM uint32_t CC0V : 16; /*!< [15..0] CC0捕获/比较值(CC0 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+
+ struct {
+ __IOM uint32_t CC1V : 16; /*!< [15..0] CC1捕获/比较值(CC1 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC1R_b;
+ } ;
+ __IM uint32_t RESERVED3[2];
+
+ union {
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+
+ struct {
+ __IOM uint32_t C0TIS : 4; /*!< [3..0] CH0触发输入选择(CH0 Trigger Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C1TIS : 4; /*!< [11..8] CH1触发输入选择(CH1 Capture Input Selection) */
+ uint32_t : 20;
+ } CIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BPR; /*!< (@ 0x00000064) TMRx Break Polarity Register */
+
+ struct {
+ __IOM uint32_t BPOL : 16; /*!< [15..0] Break输入极性选择(Break Input Polarity Selection) */
+ uint32_t : 16;
+ } BPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BER; /*!< (@ 0x00000068) TMRx Break Enable Register */
+
+ struct {
+ __IOM uint32_t BIEN : 16; /*!< [15..0] Break输入使能控制(Break Input Enable) */
+ uint32_t : 16;
+ } BER_b;
+ } ;
+} TMR2_Type; /*!< Size = 108 (0x6c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOA ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOA (GPIOA)
+ */
+
+typedef struct { /*!< (@ 0x40024000) GPIOA Structure */
+
+ union {
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+
+ struct {
+ __IOM uint32_t BSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BRn0 : 1; /*!< [16..16] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn1 : 1; /*!< [17..17] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn2 : 1; /*!< [18..18] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn3 : 1; /*!< [19..19] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn4 : 1; /*!< [20..20] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn5 : 1; /*!< [21..21] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn6 : 1; /*!< [22..22] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn7 : 1; /*!< [23..23] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn8 : 1; /*!< [24..24] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn9 : 1; /*!< [25..25] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn10 : 1; /*!< [26..26] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn11 : 1; /*!< [27..27] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn12 : 1; /*!< [28..28] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn13 : 1; /*!< [29..29] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn14 : 1; /*!< [30..30] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn15 : 1; /*!< [31..31] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ } BSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+
+ struct {
+ __IM uint32_t DIn0 : 1; /*!< [0..0] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn1 : 1; /*!< [1..1] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn2 : 1; /*!< [2..2] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn3 : 1; /*!< [3..3] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn4 : 1; /*!< [4..4] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn5 : 1; /*!< [5..5] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn6 : 1; /*!< [6..6] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn7 : 1; /*!< [7..7] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn8 : 1; /*!< [8..8] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn9 : 1; /*!< [9..9] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn10 : 1; /*!< [10..10] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn11 : 1; /*!< [11..11] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn12 : 1; /*!< [12..12] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn13 : 1; /*!< [13..13] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn14 : 1; /*!< [14..14] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn15 : 1; /*!< [15..15] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ uint32_t : 16;
+ } DIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+
+ struct {
+ __IOM uint32_t DOn0 : 1; /*!< [0..0] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn1 : 1; /*!< [1..1] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn2 : 1; /*!< [2..2] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn3 : 1; /*!< [3..3] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn4 : 1; /*!< [4..4] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn5 : 1; /*!< [5..5] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn6 : 1; /*!< [6..6] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn7 : 1; /*!< [7..7] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn8 : 1; /*!< [8..8] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn9 : 1; /*!< [9..9] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn10 : 1; /*!< [10..10] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn11 : 1; /*!< [11..11] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn12 : 1; /*!< [12..12] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn13 : 1; /*!< [13..13] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn14 : 1; /*!< [14..14] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn15 : 1; /*!< [15..15] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ uint32_t : 16;
+ } DOR_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t IEn0 : 1; /*!< [0..0] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn1 : 1; /*!< [1..1] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn2 : 1; /*!< [2..2] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn3 : 1; /*!< [3..3] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn4 : 1; /*!< [4..4] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn5 : 1; /*!< [5..5] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn6 : 1; /*!< [6..6] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn7 : 1; /*!< [7..7] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn8 : 1; /*!< [8..8] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn9 : 1; /*!< [9..9] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn10 : 1; /*!< [10..10] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn11 : 1; /*!< [11..11] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn12 : 1; /*!< [12..12] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn13 : 1; /*!< [13..13] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn14 : 1; /*!< [14..14] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn15 : 1; /*!< [15..15] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ uint32_t : 16;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+
+ struct {
+ __IOM uint32_t IMn0 : 2; /*!< [1..0] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn1 : 2; /*!< [3..2] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn2 : 2; /*!< [5..4] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn3 : 2; /*!< [7..6] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn4 : 2; /*!< [9..8] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn5 : 2; /*!< [11..10] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn6 : 2; /*!< [13..12] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn7 : 2; /*!< [15..14] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn8 : 2; /*!< [17..16] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn9 : 2; /*!< [19..18] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn10 : 2; /*!< [21..20] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn11 : 2; /*!< [23..22] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn12 : 2; /*!< [25..24] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn13 : 2; /*!< [27..26] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn14 : 2; /*!< [29..28] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn15 : 2; /*!< [31..30] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ } IMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+
+ struct {
+ __IOM uint32_t ISn0 : 1; /*!< [0..0] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn1 : 1; /*!< [1..1] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn2 : 1; /*!< [2..2] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn3 : 1; /*!< [3..3] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn4 : 1; /*!< [4..4] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn5 : 1; /*!< [5..5] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn6 : 1; /*!< [6..6] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn7 : 1; /*!< [7..7] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn8 : 1; /*!< [8..8] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn9 : 1; /*!< [9..9] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn10 : 1; /*!< [10..10] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn11 : 1; /*!< [11..11] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn12 : 1; /*!< [12..12] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn13 : 1; /*!< [13..13] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn14 : 1; /*!< [14..14] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn15 : 1; /*!< [15..15] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ uint32_t : 16;
+ } ISR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+
+ struct {
+ __IOM uint32_t PMn0 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn1 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn2 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn3 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn4 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn5 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn6 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn7 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+
+ struct {
+ __IOM uint32_t PMn8 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn9 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn10 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn11 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn12 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn13 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn14 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn15 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+
+ struct {
+ __IOM uint32_t SEn0 : 1; /*!< [0..0] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn1 : 1; /*!< [1..1] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn2 : 1; /*!< [2..2] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn3 : 1; /*!< [3..3] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn4 : 1; /*!< [4..4] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn5 : 1; /*!< [5..5] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn6 : 1; /*!< [6..6] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn7 : 1; /*!< [7..7] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn8 : 1; /*!< [8..8] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn9 : 1; /*!< [9..9] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn10 : 1; /*!< [10..10] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn11 : 1; /*!< [11..11] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn12 : 1; /*!< [12..12] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn13 : 1; /*!< [13..13] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn14 : 1; /*!< [14..14] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn15 : 1; /*!< [15..15] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ uint32_t : 16;
+ } SER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEn0 : 1; /*!< [0..0] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn1 : 1; /*!< [1..1] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn2 : 1; /*!< [2..2] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn3 : 1; /*!< [3..3] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn4 : 1; /*!< [4..4] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn5 : 1; /*!< [5..5] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn6 : 1; /*!< [6..6] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn7 : 1; /*!< [7..7] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn8 : 1; /*!< [8..8] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn9 : 1; /*!< [9..9] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn10 : 1; /*!< [10..10] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn11 : 1; /*!< [11..11] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn12 : 1; /*!< [12..12] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn13 : 1; /*!< [13..13] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn14 : 1; /*!< [14..14] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn15 : 1; /*!< [15..15] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ uint32_t : 16;
+ } DER_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+
+ struct {
+ __IOM uint32_t UDn0 : 2; /*!< [1..0] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn1 : 2; /*!< [3..2] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn2 : 2; /*!< [5..4] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn3 : 2; /*!< [7..6] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn4 : 2; /*!< [9..8] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn5 : 2; /*!< [11..10] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn6 : 2; /*!< [13..12] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn7 : 2; /*!< [15..14] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn8 : 2; /*!< [17..16] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn9 : 2; /*!< [19..18] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn10 : 2; /*!< [21..20] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn11 : 2; /*!< [23..22] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn12 : 2; /*!< [25..24] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn13 : 2; /*!< [27..26] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn14 : 2; /*!< [29..28] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn15 : 2; /*!< [31..30] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ } UDR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+
+ struct {
+ __IOM uint32_t ODn0 : 1; /*!< [0..0] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn1 : 1; /*!< [1..1] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn2 : 1; /*!< [2..2] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn3 : 1; /*!< [3..3] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn4 : 1; /*!< [4..4] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn5 : 1; /*!< [5..5] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn6 : 1; /*!< [6..6] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn7 : 1; /*!< [7..7] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn8 : 1; /*!< [8..8] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn9 : 1; /*!< [9..9] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn10 : 1; /*!< [10..10] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn11 : 1; /*!< [11..11] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn12 : 1; /*!< [12..12] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn13 : 1; /*!< [13..13] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn14 : 1; /*!< [14..14] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn15 : 1; /*!< [15..15] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+
+ struct {
+ __IOM uint32_t DRx0 : 1; /*!< [0..0] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx1 : 1; /*!< [1..1] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx2 : 1; /*!< [2..2] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx3 : 1; /*!< [3..3] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx4 : 1; /*!< [4..4] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx5 : 1; /*!< [5..5] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx6 : 1; /*!< [6..6] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx7 : 1; /*!< [7..7] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx8 : 1; /*!< [8..8] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx9 : 1; /*!< [9..9] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx10 : 1; /*!< [10..10] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx11 : 1; /*!< [11..11] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx12 : 1; /*!< [12..12] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx13 : 1; /*!< [13..13] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx14 : 1; /*!< [14..14] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx15 : 1; /*!< [15..15] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRy0 : 1; /*!< [16..16] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy1 : 1; /*!< [17..17] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy2 : 1; /*!< [18..18] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy3 : 1; /*!< [19..19] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy4 : 1; /*!< [20..20] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy5 : 1; /*!< [21..21] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy6 : 1; /*!< [22..22] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy7 : 1; /*!< [23..23] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy8 : 1; /*!< [24..24] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy9 : 1; /*!< [25..25] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy10 : 1; /*!< [26..26] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy11 : 1; /*!< [27..27] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy12 : 1; /*!< [28..28] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy13 : 1; /*!< [29..29] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy14 : 1; /*!< [30..30] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy15 : 1; /*!< [31..31] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ } DHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+
+ struct {
+ __IOM uint32_t IDn0 : 1; /*!< [0..0] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn1 : 1; /*!< [1..1] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn2 : 1; /*!< [2..2] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn3 : 1; /*!< [3..3] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn4 : 1; /*!< [4..4] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn5 : 1; /*!< [5..5] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn6 : 1; /*!< [6..6] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn7 : 1; /*!< [7..7] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn8 : 1; /*!< [8..8] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn9 : 1; /*!< [9..9] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn10 : 1; /*!< [10..10] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn11 : 1; /*!< [11..11] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn12 : 1; /*!< [12..12] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn13 : 1; /*!< [13..13] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn14 : 1; /*!< [14..14] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn15 : 1; /*!< [15..15] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ uint32_t : 16;
+ } IHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+
+ struct {
+ __IOM uint32_t OSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ uint32_t : 16;
+ } OSR_b;
+ } ;
+} GPIOA_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOB ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOB (GPIOB)
+ */
+
+typedef struct { /*!< (@ 0x40025000) GPIOB Structure */
+
+ union {
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+
+ struct {
+ __IOM uint32_t BSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BRn0 : 1; /*!< [16..16] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn1 : 1; /*!< [17..17] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn2 : 1; /*!< [18..18] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn3 : 1; /*!< [19..19] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn4 : 1; /*!< [20..20] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn5 : 1; /*!< [21..21] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn6 : 1; /*!< [22..22] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn7 : 1; /*!< [23..23] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn8 : 1; /*!< [24..24] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn9 : 1; /*!< [25..25] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn10 : 1; /*!< [26..26] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn11 : 1; /*!< [27..27] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn12 : 1; /*!< [28..28] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn13 : 1; /*!< [29..29] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn14 : 1; /*!< [30..30] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn15 : 1; /*!< [31..31] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ } BSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+
+ struct {
+ __IM uint32_t DIn0 : 1; /*!< [0..0] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn1 : 1; /*!< [1..1] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn2 : 1; /*!< [2..2] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn3 : 1; /*!< [3..3] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn4 : 1; /*!< [4..4] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn5 : 1; /*!< [5..5] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn6 : 1; /*!< [6..6] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn7 : 1; /*!< [7..7] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn8 : 1; /*!< [8..8] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn9 : 1; /*!< [9..9] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn10 : 1; /*!< [10..10] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn11 : 1; /*!< [11..11] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn12 : 1; /*!< [12..12] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn13 : 1; /*!< [13..13] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn14 : 1; /*!< [14..14] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn15 : 1; /*!< [15..15] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ uint32_t : 16;
+ } DIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+
+ struct {
+ __IOM uint32_t DOn0 : 1; /*!< [0..0] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn1 : 1; /*!< [1..1] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn2 : 1; /*!< [2..2] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn3 : 1; /*!< [3..3] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn4 : 1; /*!< [4..4] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn5 : 1; /*!< [5..5] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn6 : 1; /*!< [6..6] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn7 : 1; /*!< [7..7] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn8 : 1; /*!< [8..8] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn9 : 1; /*!< [9..9] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn10 : 1; /*!< [10..10] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn11 : 1; /*!< [11..11] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn12 : 1; /*!< [12..12] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn13 : 1; /*!< [13..13] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn14 : 1; /*!< [14..14] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn15 : 1; /*!< [15..15] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ uint32_t : 16;
+ } DOR_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t IEn0 : 1; /*!< [0..0] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn1 : 1; /*!< [1..1] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn2 : 1; /*!< [2..2] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn3 : 1; /*!< [3..3] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn4 : 1; /*!< [4..4] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn5 : 1; /*!< [5..5] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn6 : 1; /*!< [6..6] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn7 : 1; /*!< [7..7] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn8 : 1; /*!< [8..8] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn9 : 1; /*!< [9..9] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn10 : 1; /*!< [10..10] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn11 : 1; /*!< [11..11] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn12 : 1; /*!< [12..12] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn13 : 1; /*!< [13..13] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn14 : 1; /*!< [14..14] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn15 : 1; /*!< [15..15] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ uint32_t : 16;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+
+ struct {
+ __IOM uint32_t IMn0 : 2; /*!< [1..0] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn1 : 2; /*!< [3..2] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn2 : 2; /*!< [5..4] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn3 : 2; /*!< [7..6] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn4 : 2; /*!< [9..8] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn5 : 2; /*!< [11..10] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn6 : 2; /*!< [13..12] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn7 : 2; /*!< [15..14] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn8 : 2; /*!< [17..16] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn9 : 2; /*!< [19..18] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn10 : 2; /*!< [21..20] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn11 : 2; /*!< [23..22] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn12 : 2; /*!< [25..24] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn13 : 2; /*!< [27..26] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn14 : 2; /*!< [29..28] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn15 : 2; /*!< [31..30] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ } IMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+
+ struct {
+ __IOM uint32_t ISn0 : 1; /*!< [0..0] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn1 : 1; /*!< [1..1] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn2 : 1; /*!< [2..2] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn3 : 1; /*!< [3..3] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn4 : 1; /*!< [4..4] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn5 : 1; /*!< [5..5] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn6 : 1; /*!< [6..6] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn7 : 1; /*!< [7..7] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn8 : 1; /*!< [8..8] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn9 : 1; /*!< [9..9] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn10 : 1; /*!< [10..10] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn11 : 1; /*!< [11..11] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn12 : 1; /*!< [12..12] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn13 : 1; /*!< [13..13] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn14 : 1; /*!< [14..14] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn15 : 1; /*!< [15..15] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ uint32_t : 16;
+ } ISR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+
+ struct {
+ __IOM uint32_t PMn0 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn1 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn2 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn3 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn4 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn5 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn6 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn7 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+
+ struct {
+ __IOM uint32_t PMn8 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn9 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn10 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn11 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn12 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn13 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn14 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn15 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+
+ struct {
+ __IOM uint32_t SEn0 : 1; /*!< [0..0] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn1 : 1; /*!< [1..1] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn2 : 1; /*!< [2..2] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn3 : 1; /*!< [3..3] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn4 : 1; /*!< [4..4] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn5 : 1; /*!< [5..5] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn6 : 1; /*!< [6..6] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn7 : 1; /*!< [7..7] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn8 : 1; /*!< [8..8] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn9 : 1; /*!< [9..9] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn10 : 1; /*!< [10..10] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn11 : 1; /*!< [11..11] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn12 : 1; /*!< [12..12] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn13 : 1; /*!< [13..13] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn14 : 1; /*!< [14..14] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn15 : 1; /*!< [15..15] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ uint32_t : 16;
+ } SER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEn0 : 1; /*!< [0..0] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn1 : 1; /*!< [1..1] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn2 : 1; /*!< [2..2] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn3 : 1; /*!< [3..3] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn4 : 1; /*!< [4..4] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn5 : 1; /*!< [5..5] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn6 : 1; /*!< [6..6] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn7 : 1; /*!< [7..7] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn8 : 1; /*!< [8..8] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn9 : 1; /*!< [9..9] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn10 : 1; /*!< [10..10] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn11 : 1; /*!< [11..11] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn12 : 1; /*!< [12..12] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn13 : 1; /*!< [13..13] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn14 : 1; /*!< [14..14] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn15 : 1; /*!< [15..15] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ uint32_t : 16;
+ } DER_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+
+ struct {
+ __IOM uint32_t UDn0 : 2; /*!< [1..0] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn1 : 2; /*!< [3..2] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn2 : 2; /*!< [5..4] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn3 : 2; /*!< [7..6] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn4 : 2; /*!< [9..8] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn5 : 2; /*!< [11..10] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn6 : 2; /*!< [13..12] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn7 : 2; /*!< [15..14] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn8 : 2; /*!< [17..16] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn9 : 2; /*!< [19..18] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn10 : 2; /*!< [21..20] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn11 : 2; /*!< [23..22] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn12 : 2; /*!< [25..24] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn13 : 2; /*!< [27..26] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn14 : 2; /*!< [29..28] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn15 : 2; /*!< [31..30] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ } UDR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+
+ struct {
+ __IOM uint32_t ODn0 : 1; /*!< [0..0] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn1 : 1; /*!< [1..1] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn2 : 1; /*!< [2..2] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn3 : 1; /*!< [3..3] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn4 : 1; /*!< [4..4] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn5 : 1; /*!< [5..5] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn6 : 1; /*!< [6..6] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn7 : 1; /*!< [7..7] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn8 : 1; /*!< [8..8] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn9 : 1; /*!< [9..9] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn10 : 1; /*!< [10..10] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn11 : 1; /*!< [11..11] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn12 : 1; /*!< [12..12] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn13 : 1; /*!< [13..13] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn14 : 1; /*!< [14..14] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn15 : 1; /*!< [15..15] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+
+ struct {
+ __IOM uint32_t DRx0 : 1; /*!< [0..0] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx1 : 1; /*!< [1..1] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx2 : 1; /*!< [2..2] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx3 : 1; /*!< [3..3] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx4 : 1; /*!< [4..4] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx5 : 1; /*!< [5..5] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx6 : 1; /*!< [6..6] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx7 : 1; /*!< [7..7] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx8 : 1; /*!< [8..8] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx9 : 1; /*!< [9..9] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx10 : 1; /*!< [10..10] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx11 : 1; /*!< [11..11] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx12 : 1; /*!< [12..12] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx13 : 1; /*!< [13..13] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx14 : 1; /*!< [14..14] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx15 : 1; /*!< [15..15] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRy0 : 1; /*!< [16..16] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy1 : 1; /*!< [17..17] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy2 : 1; /*!< [18..18] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy3 : 1; /*!< [19..19] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy4 : 1; /*!< [20..20] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy5 : 1; /*!< [21..21] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy6 : 1; /*!< [22..22] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy7 : 1; /*!< [23..23] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy8 : 1; /*!< [24..24] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy9 : 1; /*!< [25..25] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy10 : 1; /*!< [26..26] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy11 : 1; /*!< [27..27] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy12 : 1; /*!< [28..28] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy13 : 1; /*!< [29..29] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy14 : 1; /*!< [30..30] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy15 : 1; /*!< [31..31] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ } DHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+
+ struct {
+ __IOM uint32_t IDn0 : 1; /*!< [0..0] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn1 : 1; /*!< [1..1] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn2 : 1; /*!< [2..2] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn3 : 1; /*!< [3..3] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn4 : 1; /*!< [4..4] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn5 : 1; /*!< [5..5] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn6 : 1; /*!< [6..6] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn7 : 1; /*!< [7..7] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn8 : 1; /*!< [8..8] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn9 : 1; /*!< [9..9] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn10 : 1; /*!< [10..10] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn11 : 1; /*!< [11..11] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn12 : 1; /*!< [12..12] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn13 : 1; /*!< [13..13] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn14 : 1; /*!< [14..14] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn15 : 1; /*!< [15..15] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ uint32_t : 16;
+ } IHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+
+ struct {
+ __IOM uint32_t OSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ uint32_t : 16;
+ } OSR_b;
+ } ;
+} GPIOB_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOC (GPIOC)
+ */
+
+typedef struct { /*!< (@ 0x40026000) GPIOC Structure */
+
+ union {
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+
+ struct {
+ __IOM uint32_t BSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BRn0 : 1; /*!< [16..16] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn1 : 1; /*!< [17..17] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn2 : 1; /*!< [18..18] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn3 : 1; /*!< [19..19] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn4 : 1; /*!< [20..20] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn5 : 1; /*!< [21..21] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn6 : 1; /*!< [22..22] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn7 : 1; /*!< [23..23] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn8 : 1; /*!< [24..24] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn9 : 1; /*!< [25..25] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn10 : 1; /*!< [26..26] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn11 : 1; /*!< [27..27] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn12 : 1; /*!< [28..28] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn13 : 1; /*!< [29..29] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn14 : 1; /*!< [30..30] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn15 : 1; /*!< [31..31] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ } BSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+
+ struct {
+ __IM uint32_t DIn0 : 1; /*!< [0..0] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn1 : 1; /*!< [1..1] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn2 : 1; /*!< [2..2] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn3 : 1; /*!< [3..3] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn4 : 1; /*!< [4..4] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn5 : 1; /*!< [5..5] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn6 : 1; /*!< [6..6] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn7 : 1; /*!< [7..7] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn8 : 1; /*!< [8..8] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn9 : 1; /*!< [9..9] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn10 : 1; /*!< [10..10] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn11 : 1; /*!< [11..11] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn12 : 1; /*!< [12..12] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn13 : 1; /*!< [13..13] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn14 : 1; /*!< [14..14] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn15 : 1; /*!< [15..15] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ uint32_t : 16;
+ } DIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+
+ struct {
+ __IOM uint32_t DOn0 : 1; /*!< [0..0] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn1 : 1; /*!< [1..1] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn2 : 1; /*!< [2..2] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn3 : 1; /*!< [3..3] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn4 : 1; /*!< [4..4] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn5 : 1; /*!< [5..5] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn6 : 1; /*!< [6..6] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn7 : 1; /*!< [7..7] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn8 : 1; /*!< [8..8] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn9 : 1; /*!< [9..9] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn10 : 1; /*!< [10..10] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn11 : 1; /*!< [11..11] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn12 : 1; /*!< [12..12] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn13 : 1; /*!< [13..13] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn14 : 1; /*!< [14..14] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn15 : 1; /*!< [15..15] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ uint32_t : 16;
+ } DOR_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t IEn0 : 1; /*!< [0..0] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn1 : 1; /*!< [1..1] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn2 : 1; /*!< [2..2] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn3 : 1; /*!< [3..3] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn4 : 1; /*!< [4..4] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn5 : 1; /*!< [5..5] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn6 : 1; /*!< [6..6] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn7 : 1; /*!< [7..7] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn8 : 1; /*!< [8..8] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn9 : 1; /*!< [9..9] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn10 : 1; /*!< [10..10] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn11 : 1; /*!< [11..11] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn12 : 1; /*!< [12..12] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn13 : 1; /*!< [13..13] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn14 : 1; /*!< [14..14] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn15 : 1; /*!< [15..15] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ uint32_t : 16;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+
+ struct {
+ __IOM uint32_t IMn0 : 2; /*!< [1..0] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn1 : 2; /*!< [3..2] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn2 : 2; /*!< [5..4] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn3 : 2; /*!< [7..6] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn4 : 2; /*!< [9..8] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn5 : 2; /*!< [11..10] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn6 : 2; /*!< [13..12] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn7 : 2; /*!< [15..14] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn8 : 2; /*!< [17..16] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn9 : 2; /*!< [19..18] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn10 : 2; /*!< [21..20] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn11 : 2; /*!< [23..22] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn12 : 2; /*!< [25..24] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn13 : 2; /*!< [27..26] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn14 : 2; /*!< [29..28] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn15 : 2; /*!< [31..30] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ } IMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+
+ struct {
+ __IOM uint32_t ISn0 : 1; /*!< [0..0] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn1 : 1; /*!< [1..1] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn2 : 1; /*!< [2..2] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn3 : 1; /*!< [3..3] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn4 : 1; /*!< [4..4] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn5 : 1; /*!< [5..5] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn6 : 1; /*!< [6..6] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn7 : 1; /*!< [7..7] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn8 : 1; /*!< [8..8] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn9 : 1; /*!< [9..9] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn10 : 1; /*!< [10..10] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn11 : 1; /*!< [11..11] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn12 : 1; /*!< [12..12] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn13 : 1; /*!< [13..13] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn14 : 1; /*!< [14..14] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn15 : 1; /*!< [15..15] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ uint32_t : 16;
+ } ISR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+
+ struct {
+ __IOM uint32_t PMn0 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn1 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn2 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn3 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn4 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn5 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn6 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn7 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+
+ struct {
+ __IOM uint32_t PMn8 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn9 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn10 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn11 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn12 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn13 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn14 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn15 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+
+ struct {
+ __IOM uint32_t SEn0 : 1; /*!< [0..0] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn1 : 1; /*!< [1..1] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn2 : 1; /*!< [2..2] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn3 : 1; /*!< [3..3] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn4 : 1; /*!< [4..4] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn5 : 1; /*!< [5..5] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn6 : 1; /*!< [6..6] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn7 : 1; /*!< [7..7] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn8 : 1; /*!< [8..8] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn9 : 1; /*!< [9..9] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn10 : 1; /*!< [10..10] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn11 : 1; /*!< [11..11] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn12 : 1; /*!< [12..12] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn13 : 1; /*!< [13..13] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn14 : 1; /*!< [14..14] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn15 : 1; /*!< [15..15] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ uint32_t : 16;
+ } SER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEn0 : 1; /*!< [0..0] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn1 : 1; /*!< [1..1] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn2 : 1; /*!< [2..2] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn3 : 1; /*!< [3..3] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn4 : 1; /*!< [4..4] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn5 : 1; /*!< [5..5] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn6 : 1; /*!< [6..6] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn7 : 1; /*!< [7..7] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn8 : 1; /*!< [8..8] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn9 : 1; /*!< [9..9] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn10 : 1; /*!< [10..10] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn11 : 1; /*!< [11..11] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn12 : 1; /*!< [12..12] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn13 : 1; /*!< [13..13] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn14 : 1; /*!< [14..14] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn15 : 1; /*!< [15..15] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ uint32_t : 16;
+ } DER_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+
+ struct {
+ __IOM uint32_t UDn0 : 2; /*!< [1..0] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn1 : 2; /*!< [3..2] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn2 : 2; /*!< [5..4] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn3 : 2; /*!< [7..6] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn4 : 2; /*!< [9..8] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn5 : 2; /*!< [11..10] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn6 : 2; /*!< [13..12] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn7 : 2; /*!< [15..14] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn8 : 2; /*!< [17..16] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn9 : 2; /*!< [19..18] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn10 : 2; /*!< [21..20] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn11 : 2; /*!< [23..22] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn12 : 2; /*!< [25..24] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn13 : 2; /*!< [27..26] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn14 : 2; /*!< [29..28] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn15 : 2; /*!< [31..30] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ } UDR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+
+ struct {
+ __IOM uint32_t ODn0 : 1; /*!< [0..0] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn1 : 1; /*!< [1..1] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn2 : 1; /*!< [2..2] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn3 : 1; /*!< [3..3] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn4 : 1; /*!< [4..4] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn5 : 1; /*!< [5..5] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn6 : 1; /*!< [6..6] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn7 : 1; /*!< [7..7] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn8 : 1; /*!< [8..8] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn9 : 1; /*!< [9..9] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn10 : 1; /*!< [10..10] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn11 : 1; /*!< [11..11] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn12 : 1; /*!< [12..12] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn13 : 1; /*!< [13..13] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn14 : 1; /*!< [14..14] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn15 : 1; /*!< [15..15] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+
+ struct {
+ __IOM uint32_t DRx0 : 1; /*!< [0..0] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx1 : 1; /*!< [1..1] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx2 : 1; /*!< [2..2] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx3 : 1; /*!< [3..3] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx4 : 1; /*!< [4..4] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx5 : 1; /*!< [5..5] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx6 : 1; /*!< [6..6] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx7 : 1; /*!< [7..7] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx8 : 1; /*!< [8..8] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx9 : 1; /*!< [9..9] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx10 : 1; /*!< [10..10] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx11 : 1; /*!< [11..11] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx12 : 1; /*!< [12..12] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx13 : 1; /*!< [13..13] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx14 : 1; /*!< [14..14] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx15 : 1; /*!< [15..15] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRy0 : 1; /*!< [16..16] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy1 : 1; /*!< [17..17] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy2 : 1; /*!< [18..18] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy3 : 1; /*!< [19..19] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy4 : 1; /*!< [20..20] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy5 : 1; /*!< [21..21] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy6 : 1; /*!< [22..22] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy7 : 1; /*!< [23..23] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy8 : 1; /*!< [24..24] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy9 : 1; /*!< [25..25] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy10 : 1; /*!< [26..26] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy11 : 1; /*!< [27..27] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy12 : 1; /*!< [28..28] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy13 : 1; /*!< [29..29] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy14 : 1; /*!< [30..30] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy15 : 1; /*!< [31..31] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ } DHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+
+ struct {
+ __IOM uint32_t IDn0 : 1; /*!< [0..0] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn1 : 1; /*!< [1..1] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn2 : 1; /*!< [2..2] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn3 : 1; /*!< [3..3] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn4 : 1; /*!< [4..4] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn5 : 1; /*!< [5..5] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn6 : 1; /*!< [6..6] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn7 : 1; /*!< [7..7] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn8 : 1; /*!< [8..8] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn9 : 1; /*!< [9..9] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn10 : 1; /*!< [10..10] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn11 : 1; /*!< [11..11] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn12 : 1; /*!< [12..12] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn13 : 1; /*!< [13..13] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn14 : 1; /*!< [14..14] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn15 : 1; /*!< [15..15] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ uint32_t : 16;
+ } IHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+
+ struct {
+ __IOM uint32_t OSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ uint32_t : 16;
+ } OSR_b;
+ } ;
+} GPIOC_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOD ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOD (GPIOD)
+ */
+
+typedef struct { /*!< (@ 0x40027000) GPIOD Structure */
+
+ union {
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+
+ struct {
+ __IOM uint32_t BSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BRn0 : 1; /*!< [16..16] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn1 : 1; /*!< [17..17] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn2 : 1; /*!< [18..18] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn3 : 1; /*!< [19..19] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn4 : 1; /*!< [20..20] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn5 : 1; /*!< [21..21] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn6 : 1; /*!< [22..22] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn7 : 1; /*!< [23..23] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn8 : 1; /*!< [24..24] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn9 : 1; /*!< [25..25] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn10 : 1; /*!< [26..26] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn11 : 1; /*!< [27..27] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn12 : 1; /*!< [28..28] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn13 : 1; /*!< [29..29] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn14 : 1; /*!< [30..30] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn15 : 1; /*!< [31..31] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ } BSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+
+ struct {
+ __IM uint32_t DIn0 : 1; /*!< [0..0] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn1 : 1; /*!< [1..1] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn2 : 1; /*!< [2..2] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn3 : 1; /*!< [3..3] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn4 : 1; /*!< [4..4] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn5 : 1; /*!< [5..5] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn6 : 1; /*!< [6..6] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn7 : 1; /*!< [7..7] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn8 : 1; /*!< [8..8] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn9 : 1; /*!< [9..9] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn10 : 1; /*!< [10..10] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn11 : 1; /*!< [11..11] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn12 : 1; /*!< [12..12] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn13 : 1; /*!< [13..13] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn14 : 1; /*!< [14..14] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn15 : 1; /*!< [15..15] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ uint32_t : 16;
+ } DIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+
+ struct {
+ __IOM uint32_t DOn0 : 1; /*!< [0..0] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn1 : 1; /*!< [1..1] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn2 : 1; /*!< [2..2] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn3 : 1; /*!< [3..3] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn4 : 1; /*!< [4..4] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn5 : 1; /*!< [5..5] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn6 : 1; /*!< [6..6] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn7 : 1; /*!< [7..7] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn8 : 1; /*!< [8..8] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn9 : 1; /*!< [9..9] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn10 : 1; /*!< [10..10] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn11 : 1; /*!< [11..11] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn12 : 1; /*!< [12..12] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn13 : 1; /*!< [13..13] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn14 : 1; /*!< [14..14] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn15 : 1; /*!< [15..15] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ uint32_t : 16;
+ } DOR_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t IEn0 : 1; /*!< [0..0] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn1 : 1; /*!< [1..1] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn2 : 1; /*!< [2..2] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn3 : 1; /*!< [3..3] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn4 : 1; /*!< [4..4] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn5 : 1; /*!< [5..5] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn6 : 1; /*!< [6..6] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn7 : 1; /*!< [7..7] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn8 : 1; /*!< [8..8] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn9 : 1; /*!< [9..9] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn10 : 1; /*!< [10..10] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn11 : 1; /*!< [11..11] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn12 : 1; /*!< [12..12] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn13 : 1; /*!< [13..13] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn14 : 1; /*!< [14..14] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn15 : 1; /*!< [15..15] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ uint32_t : 16;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+
+ struct {
+ __IOM uint32_t IMn0 : 2; /*!< [1..0] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn1 : 2; /*!< [3..2] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn2 : 2; /*!< [5..4] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn3 : 2; /*!< [7..6] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn4 : 2; /*!< [9..8] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn5 : 2; /*!< [11..10] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn6 : 2; /*!< [13..12] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn7 : 2; /*!< [15..14] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn8 : 2; /*!< [17..16] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn9 : 2; /*!< [19..18] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn10 : 2; /*!< [21..20] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn11 : 2; /*!< [23..22] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn12 : 2; /*!< [25..24] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn13 : 2; /*!< [27..26] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn14 : 2; /*!< [29..28] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn15 : 2; /*!< [31..30] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ } IMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+
+ struct {
+ __IOM uint32_t ISn0 : 1; /*!< [0..0] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn1 : 1; /*!< [1..1] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn2 : 1; /*!< [2..2] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn3 : 1; /*!< [3..3] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn4 : 1; /*!< [4..4] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn5 : 1; /*!< [5..5] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn6 : 1; /*!< [6..6] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn7 : 1; /*!< [7..7] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn8 : 1; /*!< [8..8] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn9 : 1; /*!< [9..9] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn10 : 1; /*!< [10..10] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn11 : 1; /*!< [11..11] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn12 : 1; /*!< [12..12] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn13 : 1; /*!< [13..13] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn14 : 1; /*!< [14..14] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn15 : 1; /*!< [15..15] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ uint32_t : 16;
+ } ISR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+
+ struct {
+ __IOM uint32_t PMn0 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn1 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn2 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn3 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn4 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn5 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn6 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn7 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+
+ struct {
+ __IOM uint32_t PMn8 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn9 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn10 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn11 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn12 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn13 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn14 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn15 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+
+ struct {
+ __IOM uint32_t SEn0 : 1; /*!< [0..0] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn1 : 1; /*!< [1..1] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn2 : 1; /*!< [2..2] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn3 : 1; /*!< [3..3] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn4 : 1; /*!< [4..4] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn5 : 1; /*!< [5..5] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn6 : 1; /*!< [6..6] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn7 : 1; /*!< [7..7] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn8 : 1; /*!< [8..8] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn9 : 1; /*!< [9..9] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn10 : 1; /*!< [10..10] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn11 : 1; /*!< [11..11] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn12 : 1; /*!< [12..12] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn13 : 1; /*!< [13..13] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn14 : 1; /*!< [14..14] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn15 : 1; /*!< [15..15] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ uint32_t : 16;
+ } SER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEn0 : 1; /*!< [0..0] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn1 : 1; /*!< [1..1] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn2 : 1; /*!< [2..2] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn3 : 1; /*!< [3..3] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn4 : 1; /*!< [4..4] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn5 : 1; /*!< [5..5] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn6 : 1; /*!< [6..6] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn7 : 1; /*!< [7..7] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn8 : 1; /*!< [8..8] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn9 : 1; /*!< [9..9] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn10 : 1; /*!< [10..10] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn11 : 1; /*!< [11..11] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn12 : 1; /*!< [12..12] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn13 : 1; /*!< [13..13] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn14 : 1; /*!< [14..14] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn15 : 1; /*!< [15..15] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ uint32_t : 16;
+ } DER_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+
+ struct {
+ __IOM uint32_t UDn0 : 2; /*!< [1..0] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn1 : 2; /*!< [3..2] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn2 : 2; /*!< [5..4] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn3 : 2; /*!< [7..6] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn4 : 2; /*!< [9..8] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn5 : 2; /*!< [11..10] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn6 : 2; /*!< [13..12] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn7 : 2; /*!< [15..14] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn8 : 2; /*!< [17..16] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn9 : 2; /*!< [19..18] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn10 : 2; /*!< [21..20] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn11 : 2; /*!< [23..22] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn12 : 2; /*!< [25..24] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn13 : 2; /*!< [27..26] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn14 : 2; /*!< [29..28] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn15 : 2; /*!< [31..30] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ } UDR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+
+ struct {
+ __IOM uint32_t ODn0 : 1; /*!< [0..0] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn1 : 1; /*!< [1..1] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn2 : 1; /*!< [2..2] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn3 : 1; /*!< [3..3] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn4 : 1; /*!< [4..4] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn5 : 1; /*!< [5..5] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn6 : 1; /*!< [6..6] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn7 : 1; /*!< [7..7] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn8 : 1; /*!< [8..8] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn9 : 1; /*!< [9..9] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn10 : 1; /*!< [10..10] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn11 : 1; /*!< [11..11] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn12 : 1; /*!< [12..12] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn13 : 1; /*!< [13..13] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn14 : 1; /*!< [14..14] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn15 : 1; /*!< [15..15] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+
+ struct {
+ __IOM uint32_t DRx0 : 1; /*!< [0..0] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx1 : 1; /*!< [1..1] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx2 : 1; /*!< [2..2] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx3 : 1; /*!< [3..3] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx4 : 1; /*!< [4..4] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx5 : 1; /*!< [5..5] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx6 : 1; /*!< [6..6] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx7 : 1; /*!< [7..7] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx8 : 1; /*!< [8..8] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx9 : 1; /*!< [9..9] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx10 : 1; /*!< [10..10] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx11 : 1; /*!< [11..11] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx12 : 1; /*!< [12..12] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx13 : 1; /*!< [13..13] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx14 : 1; /*!< [14..14] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx15 : 1; /*!< [15..15] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRy0 : 1; /*!< [16..16] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy1 : 1; /*!< [17..17] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy2 : 1; /*!< [18..18] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy3 : 1; /*!< [19..19] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy4 : 1; /*!< [20..20] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy5 : 1; /*!< [21..21] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy6 : 1; /*!< [22..22] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy7 : 1; /*!< [23..23] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy8 : 1; /*!< [24..24] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy9 : 1; /*!< [25..25] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy10 : 1; /*!< [26..26] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy11 : 1; /*!< [27..27] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy12 : 1; /*!< [28..28] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy13 : 1; /*!< [29..29] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy14 : 1; /*!< [30..30] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy15 : 1; /*!< [31..31] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ } DHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+
+ struct {
+ __IOM uint32_t IDn0 : 1; /*!< [0..0] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn1 : 1; /*!< [1..1] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn2 : 1; /*!< [2..2] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn3 : 1; /*!< [3..3] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn4 : 1; /*!< [4..4] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn5 : 1; /*!< [5..5] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn6 : 1; /*!< [6..6] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn7 : 1; /*!< [7..7] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn8 : 1; /*!< [8..8] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn9 : 1; /*!< [9..9] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn10 : 1; /*!< [10..10] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn11 : 1; /*!< [11..11] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn12 : 1; /*!< [12..12] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn13 : 1; /*!< [13..13] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn14 : 1; /*!< [14..14] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn15 : 1; /*!< [15..15] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ uint32_t : 16;
+ } IHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+
+ struct {
+ __IOM uint32_t OSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ uint32_t : 16;
+ } OSR_b;
+ } ;
+} GPIOD_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOE ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOE (GPIOE)
+ */
+
+typedef struct { /*!< (@ 0x40028000) GPIOE Structure */
+
+ union {
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+
+ struct {
+ __IOM uint32_t BSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BRn0 : 1; /*!< [16..16] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn1 : 1; /*!< [17..17] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn2 : 1; /*!< [18..18] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn3 : 1; /*!< [19..19] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn4 : 1; /*!< [20..20] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn5 : 1; /*!< [21..21] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn6 : 1; /*!< [22..22] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn7 : 1; /*!< [23..23] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn8 : 1; /*!< [24..24] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn9 : 1; /*!< [25..25] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn10 : 1; /*!< [26..26] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn11 : 1; /*!< [27..27] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn12 : 1; /*!< [28..28] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn13 : 1; /*!< [29..29] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn14 : 1; /*!< [30..30] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn15 : 1; /*!< [31..31] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ } BSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+
+ struct {
+ __IM uint32_t DIn0 : 1; /*!< [0..0] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn1 : 1; /*!< [1..1] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn2 : 1; /*!< [2..2] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn3 : 1; /*!< [3..3] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn4 : 1; /*!< [4..4] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn5 : 1; /*!< [5..5] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn6 : 1; /*!< [6..6] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn7 : 1; /*!< [7..7] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn8 : 1; /*!< [8..8] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn9 : 1; /*!< [9..9] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn10 : 1; /*!< [10..10] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn11 : 1; /*!< [11..11] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn12 : 1; /*!< [12..12] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn13 : 1; /*!< [13..13] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn14 : 1; /*!< [14..14] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn15 : 1; /*!< [15..15] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ uint32_t : 16;
+ } DIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+
+ struct {
+ __IOM uint32_t DOn0 : 1; /*!< [0..0] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn1 : 1; /*!< [1..1] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn2 : 1; /*!< [2..2] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn3 : 1; /*!< [3..3] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn4 : 1; /*!< [4..4] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn5 : 1; /*!< [5..5] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn6 : 1; /*!< [6..6] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn7 : 1; /*!< [7..7] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn8 : 1; /*!< [8..8] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn9 : 1; /*!< [9..9] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn10 : 1; /*!< [10..10] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn11 : 1; /*!< [11..11] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn12 : 1; /*!< [12..12] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn13 : 1; /*!< [13..13] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn14 : 1; /*!< [14..14] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn15 : 1; /*!< [15..15] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ uint32_t : 16;
+ } DOR_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t IEn0 : 1; /*!< [0..0] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn1 : 1; /*!< [1..1] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn2 : 1; /*!< [2..2] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn3 : 1; /*!< [3..3] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn4 : 1; /*!< [4..4] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn5 : 1; /*!< [5..5] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn6 : 1; /*!< [6..6] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn7 : 1; /*!< [7..7] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn8 : 1; /*!< [8..8] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn9 : 1; /*!< [9..9] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn10 : 1; /*!< [10..10] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn11 : 1; /*!< [11..11] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn12 : 1; /*!< [12..12] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn13 : 1; /*!< [13..13] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn14 : 1; /*!< [14..14] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn15 : 1; /*!< [15..15] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ uint32_t : 16;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+
+ struct {
+ __IOM uint32_t IMn0 : 2; /*!< [1..0] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn1 : 2; /*!< [3..2] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn2 : 2; /*!< [5..4] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn3 : 2; /*!< [7..6] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn4 : 2; /*!< [9..8] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn5 : 2; /*!< [11..10] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn6 : 2; /*!< [13..12] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn7 : 2; /*!< [15..14] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn8 : 2; /*!< [17..16] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn9 : 2; /*!< [19..18] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn10 : 2; /*!< [21..20] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn11 : 2; /*!< [23..22] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn12 : 2; /*!< [25..24] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn13 : 2; /*!< [27..26] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn14 : 2; /*!< [29..28] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn15 : 2; /*!< [31..30] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ } IMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+
+ struct {
+ __IOM uint32_t ISn0 : 1; /*!< [0..0] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn1 : 1; /*!< [1..1] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn2 : 1; /*!< [2..2] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn3 : 1; /*!< [3..3] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn4 : 1; /*!< [4..4] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn5 : 1; /*!< [5..5] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn6 : 1; /*!< [6..6] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn7 : 1; /*!< [7..7] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn8 : 1; /*!< [8..8] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn9 : 1; /*!< [9..9] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn10 : 1; /*!< [10..10] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn11 : 1; /*!< [11..11] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn12 : 1; /*!< [12..12] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn13 : 1; /*!< [13..13] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn14 : 1; /*!< [14..14] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn15 : 1; /*!< [15..15] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ uint32_t : 16;
+ } ISR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+
+ struct {
+ __IOM uint32_t PMn0 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn1 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn2 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn3 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn4 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn5 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn6 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn7 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+
+ struct {
+ __IOM uint32_t PMn8 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn9 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn10 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn11 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn12 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn13 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn14 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn15 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+
+ struct {
+ __IOM uint32_t SEn0 : 1; /*!< [0..0] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn1 : 1; /*!< [1..1] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn2 : 1; /*!< [2..2] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn3 : 1; /*!< [3..3] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn4 : 1; /*!< [4..4] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn5 : 1; /*!< [5..5] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn6 : 1; /*!< [6..6] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn7 : 1; /*!< [7..7] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn8 : 1; /*!< [8..8] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn9 : 1; /*!< [9..9] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn10 : 1; /*!< [10..10] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn11 : 1; /*!< [11..11] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn12 : 1; /*!< [12..12] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn13 : 1; /*!< [13..13] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn14 : 1; /*!< [14..14] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn15 : 1; /*!< [15..15] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ uint32_t : 16;
+ } SER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEn0 : 1; /*!< [0..0] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn1 : 1; /*!< [1..1] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn2 : 1; /*!< [2..2] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn3 : 1; /*!< [3..3] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn4 : 1; /*!< [4..4] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn5 : 1; /*!< [5..5] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn6 : 1; /*!< [6..6] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn7 : 1; /*!< [7..7] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn8 : 1; /*!< [8..8] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn9 : 1; /*!< [9..9] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn10 : 1; /*!< [10..10] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn11 : 1; /*!< [11..11] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn12 : 1; /*!< [12..12] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn13 : 1; /*!< [13..13] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn14 : 1; /*!< [14..14] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn15 : 1; /*!< [15..15] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ uint32_t : 16;
+ } DER_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+
+ struct {
+ __IOM uint32_t UDn0 : 2; /*!< [1..0] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn1 : 2; /*!< [3..2] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn2 : 2; /*!< [5..4] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn3 : 2; /*!< [7..6] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn4 : 2; /*!< [9..8] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn5 : 2; /*!< [11..10] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn6 : 2; /*!< [13..12] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn7 : 2; /*!< [15..14] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn8 : 2; /*!< [17..16] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn9 : 2; /*!< [19..18] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn10 : 2; /*!< [21..20] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn11 : 2; /*!< [23..22] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn12 : 2; /*!< [25..24] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn13 : 2; /*!< [27..26] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn14 : 2; /*!< [29..28] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn15 : 2; /*!< [31..30] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ } UDR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+
+ struct {
+ __IOM uint32_t ODn0 : 1; /*!< [0..0] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn1 : 1; /*!< [1..1] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn2 : 1; /*!< [2..2] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn3 : 1; /*!< [3..3] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn4 : 1; /*!< [4..4] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn5 : 1; /*!< [5..5] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn6 : 1; /*!< [6..6] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn7 : 1; /*!< [7..7] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn8 : 1; /*!< [8..8] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn9 : 1; /*!< [9..9] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn10 : 1; /*!< [10..10] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn11 : 1; /*!< [11..11] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn12 : 1; /*!< [12..12] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn13 : 1; /*!< [13..13] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn14 : 1; /*!< [14..14] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn15 : 1; /*!< [15..15] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+
+ struct {
+ __IOM uint32_t DRx0 : 1; /*!< [0..0] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx1 : 1; /*!< [1..1] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx2 : 1; /*!< [2..2] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx3 : 1; /*!< [3..3] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx4 : 1; /*!< [4..4] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx5 : 1; /*!< [5..5] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx6 : 1; /*!< [6..6] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx7 : 1; /*!< [7..7] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx8 : 1; /*!< [8..8] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx9 : 1; /*!< [9..9] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx10 : 1; /*!< [10..10] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx11 : 1; /*!< [11..11] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx12 : 1; /*!< [12..12] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx13 : 1; /*!< [13..13] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx14 : 1; /*!< [14..14] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx15 : 1; /*!< [15..15] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRy0 : 1; /*!< [16..16] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy1 : 1; /*!< [17..17] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy2 : 1; /*!< [18..18] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy3 : 1; /*!< [19..19] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy4 : 1; /*!< [20..20] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy5 : 1; /*!< [21..21] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy6 : 1; /*!< [22..22] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy7 : 1; /*!< [23..23] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy8 : 1; /*!< [24..24] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy9 : 1; /*!< [25..25] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy10 : 1; /*!< [26..26] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy11 : 1; /*!< [27..27] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy12 : 1; /*!< [28..28] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy13 : 1; /*!< [29..29] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy14 : 1; /*!< [30..30] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy15 : 1; /*!< [31..31] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ } DHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+
+ struct {
+ __IOM uint32_t IDn0 : 1; /*!< [0..0] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn1 : 1; /*!< [1..1] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn2 : 1; /*!< [2..2] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn3 : 1; /*!< [3..3] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn4 : 1; /*!< [4..4] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn5 : 1; /*!< [5..5] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn6 : 1; /*!< [6..6] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn7 : 1; /*!< [7..7] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn8 : 1; /*!< [8..8] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn9 : 1; /*!< [9..9] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn10 : 1; /*!< [10..10] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn11 : 1; /*!< [11..11] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn12 : 1; /*!< [12..12] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn13 : 1; /*!< [13..13] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn14 : 1; /*!< [14..14] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn15 : 1; /*!< [15..15] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ uint32_t : 16;
+ } IHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+
+ struct {
+ __IOM uint32_t OSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ uint32_t : 16;
+ } OSR_b;
+ } ;
+} GPIOE_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOF ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief GPIOF (GPIOF)
+ */
+
+typedef struct { /*!< (@ 0x40029000) GPIOF Structure */
+
+ union {
+ __IOM uint32_t BSR; /*!< (@ 0x00000000) GPIOx Bit Set/Reset Register */
+
+ struct {
+ __IOM uint32_t BSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出置位(GPIO Bit Set Control) */
+ __IOM uint32_t BRn0 : 1; /*!< [16..16] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn1 : 1; /*!< [17..17] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn2 : 1; /*!< [18..18] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn3 : 1; /*!< [19..19] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn4 : 1; /*!< [20..20] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn5 : 1; /*!< [21..21] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn6 : 1; /*!< [22..22] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn7 : 1; /*!< [23..23] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn8 : 1; /*!< [24..24] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn9 : 1; /*!< [25..25] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn10 : 1; /*!< [26..26] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn11 : 1; /*!< [27..27] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn12 : 1; /*!< [28..28] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn13 : 1; /*!< [29..29] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn14 : 1; /*!< [30..30] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ __IOM uint32_t BRn15 : 1; /*!< [31..31] GPIO端口x引脚n输出复位(GPIO Bit Reset Control) */
+ } BSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DIR; /*!< (@ 0x00000004) GPIOx Data Input Register */
+
+ struct {
+ __IM uint32_t DIn0 : 1; /*!< [0..0] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn1 : 1; /*!< [1..1] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn2 : 1; /*!< [2..2] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn3 : 1; /*!< [3..3] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn4 : 1; /*!< [4..4] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn5 : 1; /*!< [5..5] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn6 : 1; /*!< [6..6] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn7 : 1; /*!< [7..7] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn8 : 1; /*!< [8..8] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn9 : 1; /*!< [9..9] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn10 : 1; /*!< [10..10] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn11 : 1; /*!< [11..11] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn12 : 1; /*!< [12..12] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn13 : 1; /*!< [13..13] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn14 : 1; /*!< [14..14] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ __IM uint32_t DIn15 : 1; /*!< [15..15] GPIO端口x引脚n输入数据寄存器(GPIO Data Input) */
+ uint32_t : 16;
+ } DIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DOR; /*!< (@ 0x00000008) GPIOx Data Output Register */
+
+ struct {
+ __IOM uint32_t DOn0 : 1; /*!< [0..0] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn1 : 1; /*!< [1..1] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn2 : 1; /*!< [2..2] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn3 : 1; /*!< [3..3] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn4 : 1; /*!< [4..4] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn5 : 1; /*!< [5..5] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn6 : 1; /*!< [6..6] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn7 : 1; /*!< [7..7] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn8 : 1; /*!< [8..8] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn9 : 1; /*!< [9..9] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn10 : 1; /*!< [10..10] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn11 : 1; /*!< [11..11] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn12 : 1; /*!< [12..12] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn13 : 1; /*!< [13..13] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn14 : 1; /*!< [14..14] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ __IOM uint32_t DOn15 : 1; /*!< [15..15] GPIO端口x引脚n输出数据寄存器(GPIO Data Output) */
+ uint32_t : 16;
+ } DOR_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000010) GPIOx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t IEn0 : 1; /*!< [0..0] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn1 : 1; /*!< [1..1] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn2 : 1; /*!< [2..2] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn3 : 1; /*!< [3..3] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn4 : 1; /*!< [4..4] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn5 : 1; /*!< [5..5] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn6 : 1; /*!< [6..6] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn7 : 1; /*!< [7..7] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn8 : 1; /*!< [8..8] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn9 : 1; /*!< [9..9] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn10 : 1; /*!< [10..10] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn11 : 1; /*!< [11..11] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn12 : 1; /*!< [12..12] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn13 : 1; /*!< [13..13] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn14 : 1; /*!< [14..14] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ __IOM uint32_t IEn15 : 1; /*!< [15..15] GPIO端口x引脚n中断使能位(GPIO Interrupt Enable) */
+ uint32_t : 16;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t IMR; /*!< (@ 0x00000014) GPIOx Interrupt Mode Register */
+
+ struct {
+ __IOM uint32_t IMn0 : 2; /*!< [1..0] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn1 : 2; /*!< [3..2] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn2 : 2; /*!< [5..4] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn3 : 2; /*!< [7..6] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn4 : 2; /*!< [9..8] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn5 : 2; /*!< [11..10] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn6 : 2; /*!< [13..12] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn7 : 2; /*!< [15..14] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn8 : 2; /*!< [17..16] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn9 : 2; /*!< [19..18] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn10 : 2; /*!< [21..20] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn11 : 2; /*!< [23..22] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn12 : 2; /*!< [25..24] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn13 : 2; /*!< [27..26] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn14 : 2; /*!< [29..28] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ __IOM uint32_t IMn15 : 2; /*!< [31..30] GPIO端口x引脚n中断模式选择位(GPIO Interrupt
+ Mode) */
+ } IMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000018) GPIOx Pending Register */
+
+ struct {
+ __IOM uint32_t ISn0 : 1; /*!< [0..0] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn1 : 1; /*!< [1..1] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn2 : 1; /*!< [2..2] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn3 : 1; /*!< [3..3] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn4 : 1; /*!< [4..4] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn5 : 1; /*!< [5..5] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn6 : 1; /*!< [6..6] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn7 : 1; /*!< [7..7] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn8 : 1; /*!< [8..8] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn9 : 1; /*!< [9..9] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn10 : 1; /*!< [10..10] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn11 : 1; /*!< [11..11] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn12 : 1; /*!< [12..12] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn13 : 1; /*!< [13..13] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn14 : 1; /*!< [14..14] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ __IOM uint32_t ISn15 : 1; /*!< [15..15] GPIO端口x引脚n中断标志位(GPIO Interrupt Flag) */
+ uint32_t : 16;
+ } ISR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t MR0; /*!< (@ 0x00000020) GPIOx Mux Register0 */
+
+ struct {
+ __IOM uint32_t PMn0 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn1 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn2 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn3 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn4 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn5 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn6 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn7 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t MR1; /*!< (@ 0x00000024) GPIOx Mux Register1 */
+
+ struct {
+ __IOM uint32_t PMn8 : 4; /*!< [3..0] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn9 : 4; /*!< [7..4] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn10 : 4; /*!< [11..8] GPIO端口x引脚n功能复用配置寄存器(GPIO MUX
+ Selection) */
+ __IOM uint32_t PMn11 : 4; /*!< [15..12] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn12 : 4; /*!< [19..16] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn13 : 4; /*!< [23..20] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn14 : 4; /*!< [27..24] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ __IOM uint32_t PMn15 : 4; /*!< [31..28] GPIO端口x引脚n功能复用配置寄存器(GPIO
+ MUX Selection) */
+ } MR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SER; /*!< (@ 0x00000028) GPIOx Sync Register */
+
+ struct {
+ __IOM uint32_t SEn0 : 1; /*!< [0..0] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn1 : 1; /*!< [1..1] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn2 : 1; /*!< [2..2] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn3 : 1; /*!< [3..3] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn4 : 1; /*!< [4..4] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn5 : 1; /*!< [5..5] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn6 : 1; /*!< [6..6] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn7 : 1; /*!< [7..7] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn8 : 1; /*!< [8..8] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn9 : 1; /*!< [9..9] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn10 : 1; /*!< [10..10] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn11 : 1; /*!< [11..11] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn12 : 1; /*!< [12..12] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn13 : 1; /*!< [13..13] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn14 : 1; /*!< [14..14] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ __IOM uint32_t SEn15 : 1; /*!< [15..15] GPIO端口x引脚n同步使能控制位(GPIO Sync Enable) */
+ uint32_t : 16;
+ } SER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DER; /*!< (@ 0x0000002C) GPIOx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEn0 : 1; /*!< [0..0] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn1 : 1; /*!< [1..1] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn2 : 1; /*!< [2..2] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn3 : 1; /*!< [3..3] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn4 : 1; /*!< [4..4] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn5 : 1; /*!< [5..5] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn6 : 1; /*!< [6..6] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn7 : 1; /*!< [7..7] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn8 : 1; /*!< [8..8] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn9 : 1; /*!< [9..9] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn10 : 1; /*!< [10..10] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn11 : 1; /*!< [11..11] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn12 : 1; /*!< [12..12] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn13 : 1; /*!< [13..13] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn14 : 1; /*!< [14..14] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ __IOM uint32_t DEn15 : 1; /*!< [15..15] GPIO端口x引脚n消抖使能控制位(GPIO Debounce
+ Enable) */
+ uint32_t : 16;
+ } DER_b;
+ } ;
+
+ union {
+ __IOM uint32_t UDR; /*!< (@ 0x00000030) GPIOx Pull Up/Down Register */
+
+ struct {
+ __IOM uint32_t UDn0 : 2; /*!< [1..0] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn1 : 2; /*!< [3..2] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn2 : 2; /*!< [5..4] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn3 : 2; /*!< [7..6] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn4 : 2; /*!< [9..8] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn5 : 2; /*!< [11..10] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn6 : 2; /*!< [13..12] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn7 : 2; /*!< [15..14] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn8 : 2; /*!< [17..16] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn9 : 2; /*!< [19..18] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn10 : 2; /*!< [21..20] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn11 : 2; /*!< [23..22] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn12 : 2; /*!< [25..24] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn13 : 2; /*!< [27..26] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn14 : 2; /*!< [29..28] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ __IOM uint32_t UDn15 : 2; /*!< [31..30] GPIO端口x引脚n上下拉使能控制位(GPIO Pull
+ Up/Down Enable) */
+ } UDR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t ODR; /*!< (@ 0x00000038) GPIOx Open Drain Register */
+
+ struct {
+ __IOM uint32_t ODn0 : 1; /*!< [0..0] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn1 : 1; /*!< [1..1] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn2 : 1; /*!< [2..2] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn3 : 1; /*!< [3..3] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn4 : 1; /*!< [4..4] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn5 : 1; /*!< [5..5] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn6 : 1; /*!< [6..6] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn7 : 1; /*!< [7..7] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn8 : 1; /*!< [8..8] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn9 : 1; /*!< [9..9] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn10 : 1; /*!< [10..10] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn11 : 1; /*!< [11..11] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn12 : 1; /*!< [12..12] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn13 : 1; /*!< [13..13] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn14 : 1; /*!< [14..14] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ __IOM uint32_t ODn15 : 1; /*!< [15..15] GPIO端口x引脚n开漏使能控制位(GPIO Open Drain
+ Enable) */
+ uint32_t : 16;
+ } ODR_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t DHR; /*!< (@ 0x00000040) GPIOx Driver Register */
+
+ struct {
+ __IOM uint32_t DRx0 : 1; /*!< [0..0] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx1 : 1; /*!< [1..1] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx2 : 1; /*!< [2..2] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx3 : 1; /*!< [3..3] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx4 : 1; /*!< [4..4] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx5 : 1; /*!< [5..5] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx6 : 1; /*!< [6..6] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx7 : 1; /*!< [7..7] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx8 : 1; /*!< [8..8] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx9 : 1; /*!< [9..9] GPIO端口x引脚n驱动能力选择x(GPIO Driverx Selection) */
+ __IOM uint32_t DRx10 : 1; /*!< [10..10] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx11 : 1; /*!< [11..11] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx12 : 1; /*!< [12..12] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx13 : 1; /*!< [13..13] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx14 : 1; /*!< [14..14] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRx15 : 1; /*!< [15..15] GPIO端口x引脚n驱动能力选择x(GPIO Driverx
+ Selection) */
+ __IOM uint32_t DRy0 : 1; /*!< [16..16] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy1 : 1; /*!< [17..17] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy2 : 1; /*!< [18..18] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy3 : 1; /*!< [19..19] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy4 : 1; /*!< [20..20] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy5 : 1; /*!< [21..21] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy6 : 1; /*!< [22..22] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy7 : 1; /*!< [23..23] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy8 : 1; /*!< [24..24] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy9 : 1; /*!< [25..25] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy10 : 1; /*!< [26..26] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy11 : 1; /*!< [27..27] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy12 : 1; /*!< [28..28] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy13 : 1; /*!< [29..29] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy14 : 1; /*!< [30..30] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ __IOM uint32_t DRy15 : 1; /*!< [31..31] GPIO端口x引脚n驱动能力选择y(GPIO Drivery
+ Selection) */
+ } DHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IHR; /*!< (@ 0x00000044) GPIOx Hysteresis Register */
+
+ struct {
+ __IOM uint32_t IDn0 : 1; /*!< [0..0] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn1 : 1; /*!< [1..1] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn2 : 1; /*!< [2..2] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn3 : 1; /*!< [3..3] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn4 : 1; /*!< [4..4] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn5 : 1; /*!< [5..5] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn6 : 1; /*!< [6..6] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn7 : 1; /*!< [7..7] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn8 : 1; /*!< [8..8] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn9 : 1; /*!< [9..9] GPIO端口x引脚n输入迟滞使能控制位(GPIO Input
+ Hysteresis Enable) */
+ __IOM uint32_t IDn10 : 1; /*!< [10..10] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn11 : 1; /*!< [11..11] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn12 : 1; /*!< [12..12] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn13 : 1; /*!< [13..13] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn14 : 1; /*!< [14..14] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ __IOM uint32_t IDn15 : 1; /*!< [15..15] GPIO端口x引脚n输入迟滞使能控制位(GPIO
+ Input Hysteresis Enable) */
+ uint32_t : 16;
+ } IHR_b;
+ } ;
+
+ union {
+ __IOM uint32_t OSR; /*!< (@ 0x00000048) GPIOx Slew Register */
+
+ struct {
+ __IOM uint32_t OSn0 : 1; /*!< [0..0] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn1 : 1; /*!< [1..1] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn2 : 1; /*!< [2..2] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn3 : 1; /*!< [3..3] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn4 : 1; /*!< [4..4] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn5 : 1; /*!< [5..5] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn6 : 1; /*!< [6..6] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn7 : 1; /*!< [7..7] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn8 : 1; /*!< [8..8] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn9 : 1; /*!< [9..9] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn10 : 1; /*!< [10..10] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn11 : 1; /*!< [11..11] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn12 : 1; /*!< [12..12] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn13 : 1; /*!< [13..13] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn14 : 1; /*!< [14..14] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ __IOM uint32_t OSn15 : 1; /*!< [15..15] GPIO端口x引脚n输出速率选择(GPIO Slew Selection) */
+ uint32_t : 16;
+ } OSR_b;
+ } ;
+} GPIOF_Type; /*!< Size = 76 (0x4c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ FLASH ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief FLASH (FLASH)
+ */
+
+typedef struct { /*!< (@ 0x40023000) FLASH Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) Flash Control Register */
+
+ struct {
+ __IOM uint32_t PS : 1; /*!< [0..0] FLASH编程启动位(Flash Program Start) */
+ __IOM uint32_t ES : 1; /*!< [1..1] FLASH擦除启动位(Flash Erase Start) */
+ uint32_t : 1;
+ __IOM uint32_t CRS : 1; /*!< [3..3] FLASH缓存刷新控制(Flash Cache Refresh) */
+ __IOM uint32_t IPE : 1; /*!< [4..4] FLASH I总线预取使能(Flash Ibus Prefetch Enable) */
+ __IOM uint32_t DPE : 1; /*!< [5..5] FLASH D总线预取使能(Flash Dbus Prefetch Enable) */
+ __IOM uint32_t FLE : 1; /*!< [6..6] FLASH保护更新使能(Flash Launch Enable) */
+ __IOM uint32_t EIE : 1; /*!< [7..7] FLASH中断使能(Flash Interrupt Enable) */
+ uint32_t : 2;
+ __IOM uint32_t NMIE : 1; /*!< [10..10] FLASH多位ECC异常NMI中断使能(FLASH nBits ECC
+ NMI Enable) */
+ uint32_t : 20;
+ __IOM uint32_t LCK : 1; /*!< [31..31] FLASH解锁标志位(Flash Lock Flag) */
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t LPR; /*!< (@ 0x00000004) Flash Lowpower Register */
+
+ struct {
+ __IOM uint32_t LS : 1; /*!< [0..0] FLASH低功耗进入使能(Flash Lowpower Start) */
+ __IOM uint32_t LW : 1; /*!< [1..1] FLASH低功耗唤醒使能(Flash Lowpower Wakeup) */
+ __IOM uint32_t SEL : 2; /*!< [3..2] FLASH低功耗BANK选择(Flash Lowpower Bank Selection) */
+ uint32_t : 27;
+ __IOM uint32_t LCK : 1; /*!< [31..31] FLASH低功耗模式解锁位(Flash Wakeup/Standby
+ Unlock Bit) */
+ } LPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000008) Flash Status Register */
+
+ struct {
+ __IOM uint32_t OES : 1; /*!< [0..0] FLASH操作错误状态(Flash Operation Error Status) */
+ __IOM uint32_t WPS : 1; /*!< [1..1] FLASH写保护错误状态(Flash Write Protect Error
+ Status) */
+ __IOM uint32_t IOS : 1; /*!< [2..2] FLASH非法操作错误状态(Flash Illegal Operation
+ Error Status) */
+ __IM uint32_t BSY : 1; /*!< [3..3] FLASH选项字节修改状态位(Flash OPDR Operation
+ Status) */
+ __IOM uint32_t SBC : 1; /*!< [4..4] FLASH单个Bit错误标志位(Flash Single Bit Error
+ Pending) */
+ __IOM uint32_t DBC : 1; /*!< [5..5] FLASH多个Bit错误标志位(Flash Double Bit Error
+ Pending) */
+ __IM uint32_t WM : 1; /*!< [6..6] FLASH工作模式标志位(Flash WorkMode Status) */
+ __IM uint32_t BM : 1; /*!< [7..7] FLASH选项字节Bank标志位(Flash Option BankMap Status) */
+ __IOM uint32_t PGE : 1; /*!< [8..8] FLASH写错误标志位(Flash Program Error Status) */
+ __IOM uint32_t PES : 1; /*!< [9..9] FLASH擦写操作错误状态(Flash Program/Erase Operation
+ Error Status) */
+ __IOM uint32_t OPE : 1; /*!< [10..10] FLASH选项字节操作错误状态(Flash OPDR Operation
+ Error Status) */
+ uint32_t : 19;
+ __IM uint32_t BMS : 1; /*!< [30..30] FLASH工作Bank标志位(Flash BankMap Status) */
+ __IM uint32_t BST : 1; /*!< [31..31] FLASH修改状态标志位(Flash In Busy Status) */
+ } SR_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t PDR0; /*!< (@ 0x00000010) Flash Data Register0 */
+
+ struct {
+ __IOM uint32_t PD0 : 32; /*!< [31..0] FLASH编程数据(Flash Program Data) */
+ } PDR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t PDR1; /*!< (@ 0x00000014) Flash Data Register1 */
+
+ struct {
+ __IOM uint32_t PD1 : 32; /*!< [31..0] FLASH编程数据(Flash Program Data) */
+ } PDR1_b;
+ } ;
+ __IM uint32_t RESERVED1[2];
+
+ union {
+ __IOM uint32_t PAR; /*!< (@ 0x00000020) Flash Address Register */
+
+ struct {
+ __IOM uint32_t PA : 19; /*!< [18..0] FLASH编程/擦除地址(Flash Program/Erase Address) */
+ uint32_t : 1;
+ __IOM uint32_t EM : 2; /*!< [21..20] FLASH擦写模式(Flash Erase Mode) */
+ uint32_t : 10;
+ } PAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t KR; /*!< (@ 0x00000024) Flash Key Register */
+
+ struct {
+ __IOM uint32_t KEY : 16; /*!< [15..0] FLASH秘钥寄存器(Flash Key Reigster) */
+ __IOM uint32_t PLK : 1; /*!< [16..16] FLASH读写保护锁(Flash Read/Write Protect Lock) */
+ uint32_t : 15;
+ } KR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RPR; /*!< (@ 0x00000028) Flash Read Protect Register */
+
+ struct {
+ __IOM uint32_t RPLV : 8; /*!< [7..0] FLASH读保护等级设置(Flash Read Protect Level) */
+ uint32_t : 24;
+ } RPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WPR; /*!< (@ 0x0000002C) Flash Write Protect Register */
+
+ struct {
+ __IOM uint32_t WRPC : 32; /*!< [31..0] FLASH写保护设置(Flash Write Protect Level) */
+ } WPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR; /*!< (@ 0x00000030) Flash Timing Register */
+
+ struct {
+ __IOM uint32_t RC : 4; /*!< [3..0] FLASH读操作Timing设置(Flash Read Cycle Timing) */
+ __IOM uint32_t UNIT : 8; /*!< [11..4] FLASH Us单位(Flash Us Unit Timing) */
+ __IOM uint32_t APG : 10; /*!< [21..12] FLASH编程Timimg设置(Flash Program Cycle Timing) */
+ uint32_t : 10;
+ } TR_b;
+ } ;
+ __IM uint32_t RESERVED2[3];
+
+ union {
+ __IOM uint32_t OPDR; /*!< (@ 0x00000040) Flash Option Data Register */
+
+ struct {
+ __IOM uint32_t BLK : 4; /*!< [3..0] BOOT锁定配置位(Boot Lock Config) */
+ __IOM uint32_t BSEL : 3; /*!< [6..4] BOOT选择配置位(Boot Selection) */
+ uint32_t : 1;
+ __IOM uint32_t BORLV : 2; /*!< [9..8] BOR电压阈值设置(BOR Voltage Limit Config) */
+ uint32_t : 2;
+ __IOM uint32_t EBP : 4; /*!< [15..12] FLASH上电ECC错误控制(FLASH Power On ECC Bypass) */
+ __IOM uint32_t IWEN : 4; /*!< [19..16] IWDG默认使能位(IWDG Enable) */
+ __IOM uint32_t WWEN : 4; /*!< [23..20] WWDG默认使能位(WWDG Enable) */
+ __IOM uint32_t BMD : 4; /*!< [27..24] FLASH双Bank模式配置(FLASH BANK Mode Config) */
+ __IOM uint32_t MAP : 4; /*!< [31..28] FLASH双Bank Map设置(FLASH BANK Mapping Config) */
+ } OPDR_b;
+ } ;
+ __IM uint32_t RESERVED3[3];
+
+ union {
+ __IOM uint32_t EAR0; /*!< (@ 0x00000050) Flash ECC 1Bit Addr Register */
+
+ struct {
+ __IM uint32_t EAD1 : 32; /*!< [31..0] Flash ECC 1Bit Addr Register */
+ } EAR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t EAR1; /*!< (@ 0x00000054) Flash ECC nBit Addr Register */
+
+ struct {
+ __IM uint32_t EADn : 32; /*!< [31..0] Flash ECC nBit Addr Register */
+ } EAR1_b;
+ } ;
+} FLASH_Type; /*!< Size = 88 (0x58) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA0 (DMA0)
+ */
+
+typedef struct { /*!< (@ 0x40022000) DMA0 Structure */
+
+ union {
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+
+ struct {
+ __IOM uint32_t SAR : 32; /*!< [31..0] DMA传输的源地址（DMA Transfer Source Address） */
+ } SAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+
+ struct {
+ __IOM uint32_t DAR : 32; /*!< [31..0] DMA传输的目的地址（DMA Transfer Destination
+ Address） */
+ } DAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+
+ struct {
+ __IOM uint32_t BL : 12; /*!< [11..0] DMA传输数量长度（DMA Transfer Data Length） */
+ uint32_t : 20;
+ } DBL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+
+ struct {
+ __IOM uint32_t PRI : 3; /*!< [2..0] DMA通道优先级设置（DMA Channel Priority Control）(根据通道
+ ��目) */
+ __IOM uint32_t TM : 1; /*!< [3..3] DMA传输模式控制（DMA Transfer Mode Control） */
+ __IOM uint32_t TC : 2; /*!< [5..4] DMA传输类型控制（DMA Transfer Type Control） */
+ __IOM uint32_t SAI : 1; /*!< [6..6] DMA源端地址控制位（DMA Source Address Control） */
+ __IOM uint32_t DAI : 1; /*!< [7..7] DMA目的端地址控制位（DMA Destination Address
+ Control） */
+ __IOM uint32_t EIE : 1; /*!< [8..8] DMA错误中断使能位（DMA Error Interrupt Enable） */
+ __IOM uint32_t HCIE : 1; /*!< [9..9] DMA传输一半完成中断使能位（DMA Transfer half
+ Completed Interrupt Enable） */
+ __IOM uint32_t CIE : 1; /*!< [10..10] DMA传输完成中断使能位（DMA Transfer Complete
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t SDS : 2; /*!< [13..12] DMA源端传输位宽选择（DMA Source Data Width
+ Select） */
+ __IOM uint32_t DDS : 2; /*!< [15..14] DMA目的端传输位宽选择（DMA Destination Data
+ Width Select） */
+ __IOM uint32_t SHF : 5; /*!< [20..16] DMA源端硬件握手接口索引（DMA Source Handshake
+ Index） */
+ __IOM uint32_t DHF : 5; /*!< [25..21] DMA目的端硬件握手接口索引（DMA Destination
+ Handshake Index） */
+ __IOM uint32_t SBL : 2; /*!< [27..26] DMA源端Burst长度设置（DMA Source Burst Length） */
+ __IOM uint32_t DBL : 2; /*!< [29..28] DMA目的端Burst长度设置（DMA Destination Burst
+ Length） */
+ __IOM uint32_t SMS : 1; /*!< [30..30] DMA源端设备接口控制位（DMA Source Master
+ Select） */
+ __IOM uint32_t DMS : 1; /*!< [31..31] DMA目的端设备接口控制位（DMA Destination
+ Master Select） */
+ } CTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] DMA传输使能（DMA Enable） */
+ uint32_t : 31;
+ } CER_b;
+ } ;
+
+ union {
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+
+ struct {
+ __IOM uint32_t ES : 1; /*!< [0..0] DMA错误中断状态位（DMA Error Interrupt Status） */
+ __IOM uint32_t HS : 1; /*!< [1..1] DMA传输一半完成中断状态位（DMA Transfer Half
+ Completed Interrupt Status） */
+ __IOM uint32_t CS : 1; /*!< [2..2] DMA传输完成中断状态位（DMA Transfer Completed
+ Interrupt Status） */
+ __IM uint32_t BUSY : 1; /*!< [3..3] DMA传输状态标志位（DMA Transfer Status） */
+ uint32_t : 28;
+ } STR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+
+ struct {
+ __IOM uint32_t DTR : 32; /*!< [31..0] DMA数据传输长度地址（DMA Transfer Length Register） */
+ } DTL_b;
+ } ;
+} DMA0_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA1 (DMA1)
+ */
+
+typedef struct { /*!< (@ 0x40022020) DMA1 Structure */
+
+ union {
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+
+ struct {
+ __IOM uint32_t SAR : 32; /*!< [31..0] DMA传输的源地址（DMA Transfer Source Address） */
+ } SAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+
+ struct {
+ __IOM uint32_t DAR : 32; /*!< [31..0] DMA传输的目的地址（DMA Transfer Destination
+ Address） */
+ } DAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+
+ struct {
+ __IOM uint32_t BL : 12; /*!< [11..0] DMA传输数量长度（DMA Transfer Data Length） */
+ uint32_t : 20;
+ } DBL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+
+ struct {
+ __IOM uint32_t PRI : 3; /*!< [2..0] DMA通道优先级设置（DMA Channel Priority Control）(根据通道
+ ��目) */
+ __IOM uint32_t TM : 1; /*!< [3..3] DMA传输模式控制（DMA Transfer Mode Control） */
+ __IOM uint32_t TC : 2; /*!< [5..4] DMA传输类型控制（DMA Transfer Type Control） */
+ __IOM uint32_t SAI : 1; /*!< [6..6] DMA源端地址控制位（DMA Source Address Control） */
+ __IOM uint32_t DAI : 1; /*!< [7..7] DMA目的端地址控制位（DMA Destination Address
+ Control） */
+ __IOM uint32_t EIE : 1; /*!< [8..8] DMA错误中断使能位（DMA Error Interrupt Enable） */
+ __IOM uint32_t HCIE : 1; /*!< [9..9] DMA传输一半完成中断使能位（DMA Transfer half
+ Completed Interrupt Enable） */
+ __IOM uint32_t CIE : 1; /*!< [10..10] DMA传输完成中断使能位（DMA Transfer Complete
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t SDS : 2; /*!< [13..12] DMA源端传输位宽选择（DMA Source Data Width
+ Select） */
+ __IOM uint32_t DDS : 2; /*!< [15..14] DMA目的端传输位宽选择（DMA Destination Data
+ Width Select） */
+ __IOM uint32_t SHF : 5; /*!< [20..16] DMA源端硬件握手接口索引（DMA Source Handshake
+ Index） */
+ __IOM uint32_t DHF : 5; /*!< [25..21] DMA目的端硬件握手接口索引（DMA Destination
+ Handshake Index） */
+ __IOM uint32_t SBL : 2; /*!< [27..26] DMA源端Burst长度设置（DMA Source Burst Length） */
+ __IOM uint32_t DBL : 2; /*!< [29..28] DMA目的端Burst长度设置（DMA Destination Burst
+ Length） */
+ __IOM uint32_t SMS : 1; /*!< [30..30] DMA源端设备接口控制位（DMA Source Master
+ Select） */
+ __IOM uint32_t DMS : 1; /*!< [31..31] DMA目的端设备接口控制位（DMA Destination
+ Master Select） */
+ } CTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] DMA传输使能（DMA Enable） */
+ uint32_t : 31;
+ } CER_b;
+ } ;
+
+ union {
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+
+ struct {
+ __IOM uint32_t ES : 1; /*!< [0..0] DMA错误中断状态位（DMA Error Interrupt Status） */
+ __IOM uint32_t HS : 1; /*!< [1..1] DMA传输一半完成中断状态位（DMA Transfer Half
+ Completed Interrupt Status） */
+ __IOM uint32_t CS : 1; /*!< [2..2] DMA传输完成中断状态位（DMA Transfer Completed
+ Interrupt Status） */
+ __IM uint32_t BUSY : 1; /*!< [3..3] DMA传输状态标志位（DMA Transfer Status） */
+ uint32_t : 28;
+ } STR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+
+ struct {
+ __IOM uint32_t DTR : 32; /*!< [31..0] DMA数据传输长度地址（DMA Transfer Length Register） */
+ } DTL_b;
+ } ;
+} DMA1_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA2 (DMA2)
+ */
+
+typedef struct { /*!< (@ 0x40022040) DMA2 Structure */
+
+ union {
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+
+ struct {
+ __IOM uint32_t SAR : 32; /*!< [31..0] DMA传输的源地址（DMA Transfer Source Address） */
+ } SAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+
+ struct {
+ __IOM uint32_t DAR : 32; /*!< [31..0] DMA传输的目的地址（DMA Transfer Destination
+ Address） */
+ } DAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+
+ struct {
+ __IOM uint32_t BL : 12; /*!< [11..0] DMA传输数量长度（DMA Transfer Data Length） */
+ uint32_t : 20;
+ } DBL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+
+ struct {
+ __IOM uint32_t PRI : 3; /*!< [2..0] DMA通道优先级设置（DMA Channel Priority Control）(根据通道
+ ��目) */
+ __IOM uint32_t TM : 1; /*!< [3..3] DMA传输模式控制（DMA Transfer Mode Control） */
+ __IOM uint32_t TC : 2; /*!< [5..4] DMA传输类型控制（DMA Transfer Type Control） */
+ __IOM uint32_t SAI : 1; /*!< [6..6] DMA源端地址控制位（DMA Source Address Control） */
+ __IOM uint32_t DAI : 1; /*!< [7..7] DMA目的端地址控制位（DMA Destination Address
+ Control） */
+ __IOM uint32_t EIE : 1; /*!< [8..8] DMA错误中断使能位（DMA Error Interrupt Enable） */
+ __IOM uint32_t HCIE : 1; /*!< [9..9] DMA传输一半完成中断使能位（DMA Transfer half
+ Completed Interrupt Enable） */
+ __IOM uint32_t CIE : 1; /*!< [10..10] DMA传输完成中断使能位（DMA Transfer Complete
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t SDS : 2; /*!< [13..12] DMA源端传输位宽选择（DMA Source Data Width
+ Select） */
+ __IOM uint32_t DDS : 2; /*!< [15..14] DMA目的端传输位宽选择（DMA Destination Data
+ Width Select） */
+ __IOM uint32_t SHF : 5; /*!< [20..16] DMA源端硬件握手接口索引（DMA Source Handshake
+ Index） */
+ __IOM uint32_t DHF : 5; /*!< [25..21] DMA目的端硬件握手接口索引（DMA Destination
+ Handshake Index） */
+ __IOM uint32_t SBL : 2; /*!< [27..26] DMA源端Burst长度设置（DMA Source Burst Length） */
+ __IOM uint32_t DBL : 2; /*!< [29..28] DMA目的端Burst长度设置（DMA Destination Burst
+ Length） */
+ __IOM uint32_t SMS : 1; /*!< [30..30] DMA源端设备接口控制位（DMA Source Master
+ Select） */
+ __IOM uint32_t DMS : 1; /*!< [31..31] DMA目的端设备接口控制位（DMA Destination
+ Master Select） */
+ } CTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] DMA传输使能（DMA Enable） */
+ uint32_t : 31;
+ } CER_b;
+ } ;
+
+ union {
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+
+ struct {
+ __IOM uint32_t ES : 1; /*!< [0..0] DMA错误中断状态位（DMA Error Interrupt Status） */
+ __IOM uint32_t HS : 1; /*!< [1..1] DMA传输一半完成中断状态位（DMA Transfer Half
+ Completed Interrupt Status） */
+ __IOM uint32_t CS : 1; /*!< [2..2] DMA传输完成中断状态位（DMA Transfer Completed
+ Interrupt Status） */
+ __IM uint32_t BUSY : 1; /*!< [3..3] DMA传输状态标志位（DMA Transfer Status） */
+ uint32_t : 28;
+ } STR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+
+ struct {
+ __IOM uint32_t DTR : 32; /*!< [31..0] DMA数据传输长度地址（DMA Transfer Length Register） */
+ } DTL_b;
+ } ;
+} DMA2_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA3 (DMA3)
+ */
+
+typedef struct { /*!< (@ 0x40022060) DMA3 Structure */
+
+ union {
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+
+ struct {
+ __IOM uint32_t SAR : 32; /*!< [31..0] DMA传输的源地址（DMA Transfer Source Address） */
+ } SAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+
+ struct {
+ __IOM uint32_t DAR : 32; /*!< [31..0] DMA传输的目的地址（DMA Transfer Destination
+ Address） */
+ } DAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+
+ struct {
+ __IOM uint32_t BL : 12; /*!< [11..0] DMA传输数量长度（DMA Transfer Data Length） */
+ uint32_t : 20;
+ } DBL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+
+ struct {
+ __IOM uint32_t PRI : 3; /*!< [2..0] DMA通道优先级设置（DMA Channel Priority Control）(根据通道
+ ��目) */
+ __IOM uint32_t TM : 1; /*!< [3..3] DMA传输模式控制（DMA Transfer Mode Control） */
+ __IOM uint32_t TC : 2; /*!< [5..4] DMA传输类型控制（DMA Transfer Type Control） */
+ __IOM uint32_t SAI : 1; /*!< [6..6] DMA源端地址控制位（DMA Source Address Control） */
+ __IOM uint32_t DAI : 1; /*!< [7..7] DMA目的端地址控制位（DMA Destination Address
+ Control） */
+ __IOM uint32_t EIE : 1; /*!< [8..8] DMA错误中断使能位（DMA Error Interrupt Enable） */
+ __IOM uint32_t HCIE : 1; /*!< [9..9] DMA传输一半完成中断使能位（DMA Transfer half
+ Completed Interrupt Enable） */
+ __IOM uint32_t CIE : 1; /*!< [10..10] DMA传输完成中断使能位（DMA Transfer Complete
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t SDS : 2; /*!< [13..12] DMA源端传输位宽选择（DMA Source Data Width
+ Select） */
+ __IOM uint32_t DDS : 2; /*!< [15..14] DMA目的端传输位宽选择（DMA Destination Data
+ Width Select） */
+ __IOM uint32_t SHF : 5; /*!< [20..16] DMA源端硬件握手接口索引（DMA Source Handshake
+ Index） */
+ __IOM uint32_t DHF : 5; /*!< [25..21] DMA目的端硬件握手接口索引（DMA Destination
+ Handshake Index） */
+ __IOM uint32_t SBL : 2; /*!< [27..26] DMA源端Burst长度设置（DMA Source Burst Length） */
+ __IOM uint32_t DBL : 2; /*!< [29..28] DMA目的端Burst长度设置（DMA Destination Burst
+ Length） */
+ __IOM uint32_t SMS : 1; /*!< [30..30] DMA源端设备接口控制位（DMA Source Master
+ Select） */
+ __IOM uint32_t DMS : 1; /*!< [31..31] DMA目的端设备接口控制位（DMA Destination
+ Master Select） */
+ } CTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] DMA传输使能（DMA Enable） */
+ uint32_t : 31;
+ } CER_b;
+ } ;
+
+ union {
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+
+ struct {
+ __IOM uint32_t ES : 1; /*!< [0..0] DMA错误中断状态位（DMA Error Interrupt Status） */
+ __IOM uint32_t HS : 1; /*!< [1..1] DMA传输一半完成中断状态位（DMA Transfer Half
+ Completed Interrupt Status） */
+ __IOM uint32_t CS : 1; /*!< [2..2] DMA传输完成中断状态位（DMA Transfer Completed
+ Interrupt Status） */
+ __IM uint32_t BUSY : 1; /*!< [3..3] DMA传输状态标志位（DMA Transfer Status） */
+ uint32_t : 28;
+ } STR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+
+ struct {
+ __IOM uint32_t DTR : 32; /*!< [31..0] DMA数据传输长度地址（DMA Transfer Length Register） */
+ } DTL_b;
+ } ;
+} DMA3_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA4 (DMA4)
+ */
+
+typedef struct { /*!< (@ 0x40022080) DMA4 Structure */
+
+ union {
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+
+ struct {
+ __IOM uint32_t SAR : 32; /*!< [31..0] DMA传输的源地址（DMA Transfer Source Address） */
+ } SAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+
+ struct {
+ __IOM uint32_t DAR : 32; /*!< [31..0] DMA传输的目的地址（DMA Transfer Destination
+ Address） */
+ } DAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+
+ struct {
+ __IOM uint32_t BL : 12; /*!< [11..0] DMA传输数量长度（DMA Transfer Data Length） */
+ uint32_t : 20;
+ } DBL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+
+ struct {
+ __IOM uint32_t PRI : 3; /*!< [2..0] DMA通道优先级设置（DMA Channel Priority Control）(根据通道
+ ��目) */
+ __IOM uint32_t TM : 1; /*!< [3..3] DMA传输模式控制（DMA Transfer Mode Control） */
+ __IOM uint32_t TC : 2; /*!< [5..4] DMA传输类型控制（DMA Transfer Type Control） */
+ __IOM uint32_t SAI : 1; /*!< [6..6] DMA源端地址控制位（DMA Source Address Control） */
+ __IOM uint32_t DAI : 1; /*!< [7..7] DMA目的端地址控制位（DMA Destination Address
+ Control） */
+ __IOM uint32_t EIE : 1; /*!< [8..8] DMA错误中断使能位（DMA Error Interrupt Enable） */
+ __IOM uint32_t HCIE : 1; /*!< [9..9] DMA传输一半完成中断使能位（DMA Transfer half
+ Completed Interrupt Enable） */
+ __IOM uint32_t CIE : 1; /*!< [10..10] DMA传输完成中断使能位（DMA Transfer Complete
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t SDS : 2; /*!< [13..12] DMA源端传输位宽选择（DMA Source Data Width
+ Select） */
+ __IOM uint32_t DDS : 2; /*!< [15..14] DMA目的端传输位宽选择（DMA Destination Data
+ Width Select） */
+ __IOM uint32_t SHF : 5; /*!< [20..16] DMA源端硬件握手接口索引（DMA Source Handshake
+ Index） */
+ __IOM uint32_t DHF : 5; /*!< [25..21] DMA目的端硬件握手接口索引（DMA Destination
+ Handshake Index） */
+ __IOM uint32_t SBL : 2; /*!< [27..26] DMA源端Burst长度设置（DMA Source Burst Length） */
+ __IOM uint32_t DBL : 2; /*!< [29..28] DMA目的端Burst长度设置（DMA Destination Burst
+ Length） */
+ __IOM uint32_t SMS : 1; /*!< [30..30] DMA源端设备接口控制位（DMA Source Master
+ Select） */
+ __IOM uint32_t DMS : 1; /*!< [31..31] DMA目的端设备接口控制位（DMA Destination
+ Master Select） */
+ } CTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] DMA传输使能（DMA Enable） */
+ uint32_t : 31;
+ } CER_b;
+ } ;
+
+ union {
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+
+ struct {
+ __IOM uint32_t ES : 1; /*!< [0..0] DMA错误中断状态位（DMA Error Interrupt Status） */
+ __IOM uint32_t HS : 1; /*!< [1..1] DMA传输一半完成中断状态位（DMA Transfer Half
+ Completed Interrupt Status） */
+ __IOM uint32_t CS : 1; /*!< [2..2] DMA传输完成中断状态位（DMA Transfer Completed
+ Interrupt Status） */
+ __IM uint32_t BUSY : 1; /*!< [3..3] DMA传输状态标志位（DMA Transfer Status） */
+ uint32_t : 28;
+ } STR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+
+ struct {
+ __IOM uint32_t DTR : 32; /*!< [31..0] DMA数据传输长度地址（DMA Transfer Length Register） */
+ } DTL_b;
+ } ;
+} DMA4_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DMA5 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DMA5 (DMA5)
+ */
+
+typedef struct { /*!< (@ 0x400220A0) DMA5 Structure */
+
+ union {
+ __IOM uint32_t SAR; /*!< (@ 0x00000000) DMA Source Address Register */
+
+ struct {
+ __IOM uint32_t SAR : 32; /*!< [31..0] DMA传输的源地址（DMA Transfer Source Address） */
+ } SAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DAR; /*!< (@ 0x00000004) DMA Destination Address Register */
+
+ struct {
+ __IOM uint32_t DAR : 32; /*!< [31..0] DMA传输的目的地址（DMA Transfer Destination
+ Address） */
+ } DAR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DBL; /*!< (@ 0x00000008) DMA Block Length Register */
+
+ struct {
+ __IOM uint32_t BL : 12; /*!< [11..0] DMA传输数量长度（DMA Transfer Data Length） */
+ uint32_t : 20;
+ } DBL_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTR; /*!< (@ 0x0000000C) DMA Control Register */
+
+ struct {
+ __IOM uint32_t PRI : 3; /*!< [2..0] DMA通道优先级设置（DMA Channel Priority Control）(根据通道
+ ��目) */
+ __IOM uint32_t TM : 1; /*!< [3..3] DMA传输模式控制（DMA Transfer Mode Control） */
+ __IOM uint32_t TC : 2; /*!< [5..4] DMA传输类型控制（DMA Transfer Type Control） */
+ __IOM uint32_t SAI : 1; /*!< [6..6] DMA源端地址控制位（DMA Source Address Control） */
+ __IOM uint32_t DAI : 1; /*!< [7..7] DMA目的端地址控制位（DMA Destination Address
+ Control） */
+ __IOM uint32_t EIE : 1; /*!< [8..8] DMA错误中断使能位（DMA Error Interrupt Enable） */
+ __IOM uint32_t HCIE : 1; /*!< [9..9] DMA传输一半完成中断使能位（DMA Transfer half
+ Completed Interrupt Enable） */
+ __IOM uint32_t CIE : 1; /*!< [10..10] DMA传输完成中断使能位（DMA Transfer Complete
+ Interrupt Enable） */
+ uint32_t : 1;
+ __IOM uint32_t SDS : 2; /*!< [13..12] DMA源端传输位宽选择（DMA Source Data Width
+ Select） */
+ __IOM uint32_t DDS : 2; /*!< [15..14] DMA目的端传输位宽选择（DMA Destination Data
+ Width Select） */
+ __IOM uint32_t SHF : 5; /*!< [20..16] DMA源端硬件握手接口索引（DMA Source Handshake
+ Index） */
+ __IOM uint32_t DHF : 5; /*!< [25..21] DMA目的端硬件握手接口索引（DMA Destination
+ Handshake Index） */
+ __IOM uint32_t SBL : 2; /*!< [27..26] DMA源端Burst长度设置（DMA Source Burst Length） */
+ __IOM uint32_t DBL : 2; /*!< [29..28] DMA目的端Burst长度设置（DMA Destination Burst
+ Length） */
+ __IOM uint32_t SMS : 1; /*!< [30..30] DMA源端设备接口控制位（DMA Source Master
+ Select） */
+ __IOM uint32_t DMS : 1; /*!< [31..31] DMA目的端设备接口控制位（DMA Destination
+ Master Select） */
+ } CTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CER; /*!< (@ 0x00000010) DMA Channel Enable Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] DMA传输使能（DMA Enable） */
+ uint32_t : 31;
+ } CER_b;
+ } ;
+
+ union {
+ __IOM uint32_t STR; /*!< (@ 0x00000014) DMA Status Register */
+
+ struct {
+ __IOM uint32_t ES : 1; /*!< [0..0] DMA错误中断状态位（DMA Error Interrupt Status） */
+ __IOM uint32_t HS : 1; /*!< [1..1] DMA传输一半完成中断状态位（DMA Transfer Half
+ Completed Interrupt Status） */
+ __IOM uint32_t CS : 1; /*!< [2..2] DMA传输完成中断状态位（DMA Transfer Completed
+ Interrupt Status） */
+ __IM uint32_t BUSY : 1; /*!< [3..3] DMA传输状态标志位（DMA Transfer Status） */
+ uint32_t : 28;
+ } STR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DTL; /*!< (@ 0x00000018) DMA Transfer Length Register */
+
+ struct {
+ __IOM uint32_t DTR : 32; /*!< [31..0] DMA数据传输长度地址（DMA Transfer Length Register） */
+ } DTL_b;
+ } ;
+} DMA5_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC0 (DAC0)
+ */
+
+typedef struct { /*!< (@ 0x40039000) DAC0 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+
+ struct {
+ __IOM uint32_t PEN : 1; /*!< [0..0] DAC使能位 */
+ __IOM uint32_t BEN : 1; /*!< [1..1] DAC Bypass Buffer输出使能位 */
+ __IOM uint32_t OEN : 1; /*!< [2..2] DAC Buffer输出使能位 */
+ __IOM uint32_t TEN : 1; /*!< [3..3] DAC触发转换使能位 */
+ __IOM uint32_t TGTRIG : 4; /*!< [7..4] 三角波触发源选择位 */
+ __IOM uint32_t TGAMP : 4; /*!< [11..8] 三角波增长最大幅度选择位 */
+ __IOM uint32_t TGDIR : 1; /*!< [12..12] 三角波起始方向选择 */
+ __IOM uint32_t TGE : 1; /*!< [13..13] 三角波产生使能位 */
+ uint32_t : 2;
+ __IOM uint32_t STRSTTRIG : 4; /*!< [19..16] 锯齿波复位触发源选择位 */
+ __IOM uint32_t STINCTRIG : 4; /*!< [23..20] 锯齿波步进触发源选择位 */
+ __IOM uint32_t STDIR : 1; /*!< [24..24] 锯齿波步进方向选择位 */
+ __IOM uint32_t STE : 1; /*!< [25..25] 锯齿波产生使能位 */
+ uint32_t : 5;
+ __IOM uint32_t STM : 1; /*!< [31..31] 锯齿波更新模式位 */
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+
+ struct {
+ __IOM uint32_t WDAT : 12; /*!< [11..0] DAC写入输出数据 */
+ uint32_t : 20;
+ } WDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+
+ struct {
+ __IM uint32_t RDAT : 12; /*!< [11..0] DAC读取输出数据（斜坡补偿后） */
+ uint32_t : 20;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+
+ struct {
+ __IOM uint32_t SID : 16; /*!< [15..0] DAC锯齿波形增量数据 */
+ uint32_t : 16;
+ } SIDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+
+ struct {
+ __IM uint32_t SRDL : 4; /*!< [3..0] DAC锯齿波形复位数据（小数部分） */
+ __IOM uint32_t SRD : 12; /*!< [15..4] DAC锯齿波形复位数据（整数部分） */
+ uint32_t : 16;
+ } SRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+
+ struct {
+ __IOM uint32_t SWT : 1; /*!< [0..0] DAC 软件触发SWT事件 */
+ __IOM uint32_t SWTB : 1; /*!< [1..1] DAC 软件触发SWTB事件 */
+ uint32_t : 30;
+ } SWTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+
+ struct {
+ __IOM uint32_t DON : 1; /*!< [0..0] DAC DON中断标志位 */
+ __IOM uint32_t DONB : 1; /*!< [1..1] DAC DONB标志位 */
+ uint32_t : 30;
+ } SR_b;
+ } ;
+} DAC0_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC1 (DAC1)
+ */
+
+typedef struct { /*!< (@ 0x40039100) DAC1 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+
+ struct {
+ __IOM uint32_t PEN : 1; /*!< [0..0] DAC使能位 */
+ __IOM uint32_t BEN : 1; /*!< [1..1] DAC Bypass Buffer输出使能位 */
+ __IOM uint32_t OEN : 1; /*!< [2..2] DAC Buffer输出使能位 */
+ __IOM uint32_t TEN : 1; /*!< [3..3] DAC触发转换使能位 */
+ __IOM uint32_t TGTRIG : 4; /*!< [7..4] 三角波触发源选择位 */
+ __IOM uint32_t TGAMP : 4; /*!< [11..8] 三角波增长最大幅度选择位 */
+ __IOM uint32_t TGDIR : 1; /*!< [12..12] 三角波起始方向选择 */
+ __IOM uint32_t TGE : 1; /*!< [13..13] 三角波产生使能位 */
+ uint32_t : 2;
+ __IOM uint32_t STRSTTRIG : 4; /*!< [19..16] 锯齿波复位触发源选择位 */
+ __IOM uint32_t STINCTRIG : 4; /*!< [23..20] 锯齿波步进触发源选择位 */
+ __IOM uint32_t STDIR : 1; /*!< [24..24] 锯齿波步进方向选择位 */
+ __IOM uint32_t STE : 1; /*!< [25..25] 锯齿波产生使能位 */
+ uint32_t : 5;
+ __IOM uint32_t STM : 1; /*!< [31..31] 锯齿波更新模式位 */
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+
+ struct {
+ __IOM uint32_t WDAT : 12; /*!< [11..0] DAC写入输出数据 */
+ uint32_t : 20;
+ } WDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+
+ struct {
+ __IM uint32_t RDAT : 12; /*!< [11..0] DAC读取输出数据（斜坡补偿后） */
+ uint32_t : 20;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+
+ struct {
+ __IOM uint32_t SID : 16; /*!< [15..0] DAC锯齿波形增量数据 */
+ uint32_t : 16;
+ } SIDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+
+ struct {
+ __IM uint32_t SRDL : 4; /*!< [3..0] DAC锯齿波形复位数据（小数部分） */
+ __IOM uint32_t SRD : 12; /*!< [15..4] DAC锯齿波形复位数据（整数部分） */
+ uint32_t : 16;
+ } SRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+
+ struct {
+ __IOM uint32_t SWT : 1; /*!< [0..0] DAC 软件触发SWT事件 */
+ __IOM uint32_t SWTB : 1; /*!< [1..1] DAC 软件触发SWTB事件 */
+ uint32_t : 30;
+ } SWTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+
+ struct {
+ __IOM uint32_t DON : 1; /*!< [0..0] DAC DON中断标志位 */
+ __IOM uint32_t DONB : 1; /*!< [1..1] DAC DONB标志位 */
+ uint32_t : 30;
+ } SR_b;
+ } ;
+} DAC1_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC2 (DAC2)
+ */
+
+typedef struct { /*!< (@ 0x40039200) DAC2 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+
+ struct {
+ __IOM uint32_t PEN : 1; /*!< [0..0] DAC使能位 */
+ __IOM uint32_t BEN : 1; /*!< [1..1] DAC Bypass Buffer输出使能位 */
+ __IOM uint32_t OEN : 1; /*!< [2..2] DAC Buffer输出使能位 */
+ __IOM uint32_t TEN : 1; /*!< [3..3] DAC触发转换使能位 */
+ __IOM uint32_t TGTRIG : 4; /*!< [7..4] 三角波触发源选择位 */
+ __IOM uint32_t TGAMP : 4; /*!< [11..8] 三角波增长最大幅度选择位 */
+ __IOM uint32_t TGDIR : 1; /*!< [12..12] 三角波起始方向选择 */
+ __IOM uint32_t TGE : 1; /*!< [13..13] 三角波产生使能位 */
+ uint32_t : 2;
+ __IOM uint32_t STRSTTRIG : 4; /*!< [19..16] 锯齿波复位触发源选择位 */
+ __IOM uint32_t STINCTRIG : 4; /*!< [23..20] 锯齿波步进触发源选择位 */
+ __IOM uint32_t STDIR : 1; /*!< [24..24] 锯齿波步进方向选择位 */
+ __IOM uint32_t STE : 1; /*!< [25..25] 锯齿波产生使能位 */
+ uint32_t : 5;
+ __IOM uint32_t STM : 1; /*!< [31..31] 锯齿波更新模式位 */
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+
+ struct {
+ __IOM uint32_t WDAT : 12; /*!< [11..0] DAC写入输出数据 */
+ uint32_t : 20;
+ } WDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+
+ struct {
+ __IM uint32_t RDAT : 12; /*!< [11..0] DAC读取输出数据（斜坡补偿后） */
+ uint32_t : 20;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+
+ struct {
+ __IOM uint32_t SID : 16; /*!< [15..0] DAC锯齿波形增量数据 */
+ uint32_t : 16;
+ } SIDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+
+ struct {
+ __IM uint32_t SRDL : 4; /*!< [3..0] DAC锯齿波形复位数据（小数部分） */
+ __IOM uint32_t SRD : 12; /*!< [15..4] DAC锯齿波形复位数据（整数部分） */
+ uint32_t : 16;
+ } SRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+
+ struct {
+ __IOM uint32_t SWT : 1; /*!< [0..0] DAC 软件触发SWT事件 */
+ __IOM uint32_t SWTB : 1; /*!< [1..1] DAC 软件触发SWTB事件 */
+ uint32_t : 30;
+ } SWTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+
+ struct {
+ __IOM uint32_t DON : 1; /*!< [0..0] DAC DON中断标志位 */
+ __IOM uint32_t DONB : 1; /*!< [1..1] DAC DONB标志位 */
+ uint32_t : 30;
+ } SR_b;
+ } ;
+} DAC2_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC3 (DAC3)
+ */
+
+typedef struct { /*!< (@ 0x40039300) DAC3 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+
+ struct {
+ __IOM uint32_t PEN : 1; /*!< [0..0] DAC使能位 */
+ __IOM uint32_t BEN : 1; /*!< [1..1] DAC Bypass Buffer输出使能位 */
+ __IOM uint32_t OEN : 1; /*!< [2..2] DAC Buffer输出使能位 */
+ __IOM uint32_t TEN : 1; /*!< [3..3] DAC触发转换使能位 */
+ __IOM uint32_t TGTRIG : 4; /*!< [7..4] 三角波触发源选择位 */
+ __IOM uint32_t TGAMP : 4; /*!< [11..8] 三角波增长最大幅度选择位 */
+ __IOM uint32_t TGDIR : 1; /*!< [12..12] 三角波起始方向选择 */
+ __IOM uint32_t TGE : 1; /*!< [13..13] 三角波产生使能位 */
+ uint32_t : 2;
+ __IOM uint32_t STRSTTRIG : 4; /*!< [19..16] 锯齿波复位触发源选择位 */
+ __IOM uint32_t STINCTRIG : 4; /*!< [23..20] 锯齿波步进触发源选择位 */
+ __IOM uint32_t STDIR : 1; /*!< [24..24] 锯齿波步进方向选择位 */
+ __IOM uint32_t STE : 1; /*!< [25..25] 锯齿波产生使能位 */
+ uint32_t : 5;
+ __IOM uint32_t STM : 1; /*!< [31..31] 锯齿波更新模式位 */
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+
+ struct {
+ __IOM uint32_t WDAT : 12; /*!< [11..0] DAC写入输出数据 */
+ uint32_t : 20;
+ } WDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+
+ struct {
+ __IM uint32_t RDAT : 12; /*!< [11..0] DAC读取输出数据（斜坡补偿后） */
+ uint32_t : 20;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+
+ struct {
+ __IOM uint32_t SID : 16; /*!< [15..0] DAC锯齿波形增量数据 */
+ uint32_t : 16;
+ } SIDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+
+ struct {
+ __IM uint32_t SRDL : 4; /*!< [3..0] DAC锯齿波形复位数据（小数部分） */
+ __IOM uint32_t SRD : 12; /*!< [15..4] DAC锯齿波形复位数据（整数部分） */
+ uint32_t : 16;
+ } SRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+
+ struct {
+ __IOM uint32_t SWT : 1; /*!< [0..0] DAC 软件触发SWT事件 */
+ __IOM uint32_t SWTB : 1; /*!< [1..1] DAC 软件触发SWTB事件 */
+ uint32_t : 30;
+ } SWTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+
+ struct {
+ __IOM uint32_t DON : 1; /*!< [0..0] DAC DON中断标志位 */
+ __IOM uint32_t DONB : 1; /*!< [1..1] DAC DONB标志位 */
+ uint32_t : 30;
+ } SR_b;
+ } ;
+} DAC3_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC4 (DAC4)
+ */
+
+typedef struct { /*!< (@ 0x40039400) DAC4 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+
+ struct {
+ __IOM uint32_t PEN : 1; /*!< [0..0] DAC使能位 */
+ __IOM uint32_t BEN : 1; /*!< [1..1] DAC Bypass Buffer输出使能位 */
+ __IOM uint32_t OEN : 1; /*!< [2..2] DAC Buffer输出使能位 */
+ __IOM uint32_t TEN : 1; /*!< [3..3] DAC触发转换使能位 */
+ __IOM uint32_t TGTRIG : 4; /*!< [7..4] 三角波触发源选择位 */
+ __IOM uint32_t TGAMP : 4; /*!< [11..8] 三角波增长最大幅度选择位 */
+ __IOM uint32_t TGDIR : 1; /*!< [12..12] 三角波起始方向选择 */
+ __IOM uint32_t TGE : 1; /*!< [13..13] 三角波产生使能位 */
+ uint32_t : 2;
+ __IOM uint32_t STRSTTRIG : 4; /*!< [19..16] 锯齿波复位触发源选择位 */
+ __IOM uint32_t STINCTRIG : 4; /*!< [23..20] 锯齿波步进触发源选择位 */
+ __IOM uint32_t STDIR : 1; /*!< [24..24] 锯齿波步进方向选择位 */
+ __IOM uint32_t STE : 1; /*!< [25..25] 锯齿波产生使能位 */
+ uint32_t : 5;
+ __IOM uint32_t STM : 1; /*!< [31..31] 锯齿波更新模式位 */
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+
+ struct {
+ __IOM uint32_t WDAT : 12; /*!< [11..0] DAC写入输出数据 */
+ uint32_t : 20;
+ } WDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+
+ struct {
+ __IM uint32_t RDAT : 12; /*!< [11..0] DAC读取输出数据（斜坡补偿后） */
+ uint32_t : 20;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+
+ struct {
+ __IOM uint32_t SID : 16; /*!< [15..0] DAC锯齿波形增量数据 */
+ uint32_t : 16;
+ } SIDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+
+ struct {
+ __IM uint32_t SRDL : 4; /*!< [3..0] DAC锯齿波形复位数据（小数部分） */
+ __IOM uint32_t SRD : 12; /*!< [15..4] DAC锯齿波形复位数据（整数部分） */
+ uint32_t : 16;
+ } SRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+
+ struct {
+ __IOM uint32_t SWT : 1; /*!< [0..0] DAC 软件触发SWT事件 */
+ __IOM uint32_t SWTB : 1; /*!< [1..1] DAC 软件触发SWTB事件 */
+ uint32_t : 30;
+ } SWTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+
+ struct {
+ __IOM uint32_t DON : 1; /*!< [0..0] DAC DON中断标志位 */
+ __IOM uint32_t DONB : 1; /*!< [1..1] DAC DONB标志位 */
+ uint32_t : 30;
+ } SR_b;
+ } ;
+} DAC4_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC5 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC5 (DAC5)
+ */
+
+typedef struct { /*!< (@ 0x40039500) DAC5 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+
+ struct {
+ __IOM uint32_t PEN : 1; /*!< [0..0] DAC使能位 */
+ __IOM uint32_t BEN : 1; /*!< [1..1] DAC Bypass Buffer输出使能位 */
+ __IOM uint32_t OEN : 1; /*!< [2..2] DAC Buffer输出使能位 */
+ __IOM uint32_t TEN : 1; /*!< [3..3] DAC触发转换使能位 */
+ __IOM uint32_t TGTRIG : 4; /*!< [7..4] 三角波触发源选择位 */
+ __IOM uint32_t TGAMP : 4; /*!< [11..8] 三角波增长最大幅度选择位 */
+ __IOM uint32_t TGDIR : 1; /*!< [12..12] 三角波起始方向选择 */
+ __IOM uint32_t TGE : 1; /*!< [13..13] 三角波产生使能位 */
+ uint32_t : 2;
+ __IOM uint32_t STRSTTRIG : 4; /*!< [19..16] 锯齿波复位触发源选择位 */
+ __IOM uint32_t STINCTRIG : 4; /*!< [23..20] 锯齿波步进触发源选择位 */
+ __IOM uint32_t STDIR : 1; /*!< [24..24] 锯齿波步进方向选择位 */
+ __IOM uint32_t STE : 1; /*!< [25..25] 锯齿波产生使能位 */
+ uint32_t : 5;
+ __IOM uint32_t STM : 1; /*!< [31..31] 锯齿波更新模式位 */
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+
+ struct {
+ __IOM uint32_t WDAT : 12; /*!< [11..0] DAC写入输出数据 */
+ uint32_t : 20;
+ } WDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+
+ struct {
+ __IM uint32_t RDAT : 12; /*!< [11..0] DAC读取输出数据（斜坡补偿后） */
+ uint32_t : 20;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+
+ struct {
+ __IOM uint32_t SID : 16; /*!< [15..0] DAC锯齿波形增量数据 */
+ uint32_t : 16;
+ } SIDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+
+ struct {
+ __IM uint32_t SRDL : 4; /*!< [3..0] DAC锯齿波形复位数据（小数部分） */
+ __IOM uint32_t SRD : 12; /*!< [15..4] DAC锯齿波形复位数据（整数部分） */
+ uint32_t : 16;
+ } SRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+
+ struct {
+ __IOM uint32_t SWT : 1; /*!< [0..0] DAC 软件触发SWT事件 */
+ __IOM uint32_t SWTB : 1; /*!< [1..1] DAC 软件触发SWTB事件 */
+ uint32_t : 30;
+ } SWTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+
+ struct {
+ __IOM uint32_t DON : 1; /*!< [0..0] DAC DON中断标志位 */
+ __IOM uint32_t DONB : 1; /*!< [1..1] DAC DONB标志位 */
+ uint32_t : 30;
+ } SR_b;
+ } ;
+} DAC5_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC6 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC6 (DAC6)
+ */
+
+typedef struct { /*!< (@ 0x40039600) DAC6 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+
+ struct {
+ __IOM uint32_t PEN : 1; /*!< [0..0] DAC使能位 */
+ __IOM uint32_t BEN : 1; /*!< [1..1] DAC Bypass Buffer输出使能位 */
+ __IOM uint32_t OEN : 1; /*!< [2..2] DAC Buffer输出使能位 */
+ __IOM uint32_t TEN : 1; /*!< [3..3] DAC触发转换使能位 */
+ __IOM uint32_t TGTRIG : 4; /*!< [7..4] 三角波触发源选择位 */
+ __IOM uint32_t TGAMP : 4; /*!< [11..8] 三角波增长最大幅度选择位 */
+ __IOM uint32_t TGDIR : 1; /*!< [12..12] 三角波起始方向选择 */
+ __IOM uint32_t TGE : 1; /*!< [13..13] 三角波产生使能位 */
+ uint32_t : 2;
+ __IOM uint32_t STRSTTRIG : 4; /*!< [19..16] 锯齿波复位触发源选择位 */
+ __IOM uint32_t STINCTRIG : 4; /*!< [23..20] 锯齿波步进触发源选择位 */
+ __IOM uint32_t STDIR : 1; /*!< [24..24] 锯齿波步进方向选择位 */
+ __IOM uint32_t STE : 1; /*!< [25..25] 锯齿波产生使能位 */
+ uint32_t : 5;
+ __IOM uint32_t STM : 1; /*!< [31..31] 锯齿波更新模式位 */
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+
+ struct {
+ __IOM uint32_t WDAT : 12; /*!< [11..0] DAC写入输出数据 */
+ uint32_t : 20;
+ } WDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+
+ struct {
+ __IM uint32_t RDAT : 12; /*!< [11..0] DAC读取输出数据（斜坡补偿后） */
+ uint32_t : 20;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+
+ struct {
+ __IOM uint32_t SID : 16; /*!< [15..0] DAC锯齿波形增量数据 */
+ uint32_t : 16;
+ } SIDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+
+ struct {
+ __IM uint32_t SRDL : 4; /*!< [3..0] DAC锯齿波形复位数据（小数部分） */
+ __IOM uint32_t SRD : 12; /*!< [15..4] DAC锯齿波形复位数据（整数部分） */
+ uint32_t : 16;
+ } SRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+
+ struct {
+ __IOM uint32_t SWT : 1; /*!< [0..0] DAC 软件触发SWT事件 */
+ __IOM uint32_t SWTB : 1; /*!< [1..1] DAC 软件触发SWTB事件 */
+ uint32_t : 30;
+ } SWTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+
+ struct {
+ __IOM uint32_t DON : 1; /*!< [0..0] DAC DON中断标志位 */
+ __IOM uint32_t DONB : 1; /*!< [1..1] DAC DONB标志位 */
+ uint32_t : 30;
+ } SR_b;
+ } ;
+} DAC6_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC7 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC7 (DAC7)
+ */
+
+typedef struct { /*!< (@ 0x40039700) DAC7 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+
+ struct {
+ __IOM uint32_t PEN : 1; /*!< [0..0] DAC使能位 */
+ __IOM uint32_t BEN : 1; /*!< [1..1] DAC Bypass Buffer输出使能位 */
+ __IOM uint32_t OEN : 1; /*!< [2..2] DAC Buffer输出使能位 */
+ __IOM uint32_t TEN : 1; /*!< [3..3] DAC触发转换使能位 */
+ __IOM uint32_t TGTRIG : 4; /*!< [7..4] 三角波触发源选择位 */
+ __IOM uint32_t TGAMP : 4; /*!< [11..8] 三角波增长最大幅度选择位 */
+ __IOM uint32_t TGDIR : 1; /*!< [12..12] 三角波起始方向选择 */
+ __IOM uint32_t TGE : 1; /*!< [13..13] 三角波产生使能位 */
+ uint32_t : 2;
+ __IOM uint32_t STRSTTRIG : 4; /*!< [19..16] 锯齿波复位触发源选择位 */
+ __IOM uint32_t STINCTRIG : 4; /*!< [23..20] 锯齿波步进触发源选择位 */
+ __IOM uint32_t STDIR : 1; /*!< [24..24] 锯齿波步进方向选择位 */
+ __IOM uint32_t STE : 1; /*!< [25..25] 锯齿波产生使能位 */
+ uint32_t : 5;
+ __IOM uint32_t STM : 1; /*!< [31..31] 锯齿波更新模式位 */
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+
+ struct {
+ __IOM uint32_t WDAT : 12; /*!< [11..0] DAC写入输出数据 */
+ uint32_t : 20;
+ } WDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+
+ struct {
+ __IM uint32_t RDAT : 12; /*!< [11..0] DAC读取输出数据（斜坡补偿后） */
+ uint32_t : 20;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+
+ struct {
+ __IOM uint32_t SID : 16; /*!< [15..0] DAC锯齿波形增量数据 */
+ uint32_t : 16;
+ } SIDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+
+ struct {
+ __IM uint32_t SRDL : 4; /*!< [3..0] DAC锯齿波形复位数据（小数部分） */
+ __IOM uint32_t SRD : 12; /*!< [15..4] DAC锯齿波形复位数据（整数部分） */
+ uint32_t : 16;
+ } SRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+
+ struct {
+ __IOM uint32_t SWT : 1; /*!< [0..0] DAC 软件触发SWT事件 */
+ __IOM uint32_t SWTB : 1; /*!< [1..1] DAC 软件触发SWTB事件 */
+ uint32_t : 30;
+ } SWTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+
+ struct {
+ __IOM uint32_t DON : 1; /*!< [0..0] DAC DON中断标志位 */
+ __IOM uint32_t DONB : 1; /*!< [1..1] DAC DONB标志位 */
+ uint32_t : 30;
+ } SR_b;
+ } ;
+} DAC7_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ DAC8 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief DAC8 (DAC8)
+ */
+
+typedef struct { /*!< (@ 0x40039800) DAC8 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) DACx Config Register */
+
+ struct {
+ __IOM uint32_t PEN : 1; /*!< [0..0] DAC使能位 */
+ __IOM uint32_t BEN : 1; /*!< [1..1] DAC Bypass Buffer输出使能位 */
+ __IOM uint32_t OEN : 1; /*!< [2..2] DAC Buffer输出使能位 */
+ __IOM uint32_t TEN : 1; /*!< [3..3] DAC触发转换使能位 */
+ __IOM uint32_t TGTRIG : 4; /*!< [7..4] 三角波触发源选择位 */
+ __IOM uint32_t TGAMP : 4; /*!< [11..8] 三角波增长最大幅度选择位 */
+ __IOM uint32_t TGDIR : 1; /*!< [12..12] 三角波起始方向选择 */
+ __IOM uint32_t TGE : 1; /*!< [13..13] 三角波产生使能位 */
+ uint32_t : 2;
+ __IOM uint32_t STRSTTRIG : 4; /*!< [19..16] 锯齿波复位触发源选择位 */
+ __IOM uint32_t STINCTRIG : 4; /*!< [23..20] 锯齿波步进触发源选择位 */
+ __IOM uint32_t STDIR : 1; /*!< [24..24] 锯齿波步进方向选择位 */
+ __IOM uint32_t STE : 1; /*!< [25..25] 锯齿波产生使能位 */
+ uint32_t : 5;
+ __IOM uint32_t STM : 1; /*!< [31..31] 锯齿波更新模式位 */
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t WDR; /*!< (@ 0x00000004) DACx Write Data Register */
+
+ struct {
+ __IOM uint32_t WDAT : 12; /*!< [11..0] DAC写入输出数据 */
+ uint32_t : 20;
+ } WDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RDR; /*!< (@ 0x00000008) DACx Read Data Register */
+
+ struct {
+ __IM uint32_t RDAT : 12; /*!< [11..0] DAC读取输出数据（斜坡补偿后） */
+ uint32_t : 20;
+ } RDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIDR; /*!< (@ 0x0000000C) DACx Sawtooth Increment Register */
+
+ struct {
+ __IOM uint32_t SID : 16; /*!< [15..0] DAC锯齿波形增量数据 */
+ uint32_t : 16;
+ } SIDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SRDR; /*!< (@ 0x00000010) DACx Sawtooth Reset Register */
+
+ struct {
+ __IM uint32_t SRDL : 4; /*!< [3..0] DAC锯齿波形复位数据（小数部分） */
+ __IOM uint32_t SRD : 12; /*!< [15..4] DAC锯齿波形复位数据（整数部分） */
+ uint32_t : 16;
+ } SRDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SWTR; /*!< (@ 0x00000014) DACx Software Trigger Register */
+
+ struct {
+ __IOM uint32_t SWT : 1; /*!< [0..0] DAC 软件触发SWT事件 */
+ __IOM uint32_t SWTB : 1; /*!< [1..1] DAC 软件触发SWTB事件 */
+ uint32_t : 30;
+ } SWTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000018) DACx Status Register */
+
+ struct {
+ __IOM uint32_t DON : 1; /*!< [0..0] DAC DON中断标志位 */
+ __IOM uint32_t DONB : 1; /*!< [1..1] DAC DONB标志位 */
+ uint32_t : 30;
+ } SR_b;
+ } ;
+} DAC8_Type; /*!< Size = 28 (0x1c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CORDIC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CORDIC (CORDIC)
+ */
+
+typedef struct { /*!< (@ 0x4003F000) CORDIC Structure */
+
+ union {
+ __IOM uint32_t CSR0; /*!< (@ 0x00000000) CORDIC Control / Status register0 */
+
+ struct {
+ __IOM uint32_t FUNC : 4; /*!< [3..0] cordic计算的函数(Function) */
+ uint32_t : 4;
+ __IOM uint32_t SCALE : 5; /*!< [12..8] CORDIC比例因子设置(CORDIC Scale Setting) */
+ uint32_t : 3;
+ __IOM uint32_t RRDYIEN : 1; /*!< [16..16] 计算结果完成中断使能（Result Ready Interrupt
+ Enable) */
+ __IOM uint32_t ERRIEN : 1; /*!< [17..17] 错误中断使能(Error Interrupt Enable) */
+ uint32_t : 1;
+ __IOM uint32_t NRES : 1; /*!< [19..19] 输出数据的个数(Output Result Number) */
+ __IOM uint32_t NARGS : 1; /*!< [20..20] 输入数据的个数(Input Argument Number) */
+ __IOM uint32_t RESSIZE : 1; /*!< [21..21] 输出数据的宽度(Output Result Size) */
+ __IOM uint32_t ARGSIZE : 1; /*!< [22..22] 输入数据的宽度(Input Argument Size) */
+ uint32_t : 5;
+ __IOM uint32_t ERRCLR : 1; /*!< [28..28] 错误中断清除(Error Interrupt Clear) */
+ __IOM uint32_t RRDYCLR : 1; /*!< [29..29] 计算结果完成中断清除(Result Ready Interrupt
+ Clear) */
+ __IM uint32_t ERR : 1; /*!< [30..30] 错误中断状态(Error Interrupt Status) */
+ __IM uint32_t RRDY : 1; /*!< [31..31] 计算结果完成中断状态（Result Ready Interrupt
+ Status) */
+ } CSR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t ARX0; /*!< (@ 0x00000004) CORDIC Argument / Result register0 */
+
+ struct {
+ __IOM uint32_t ARGRESX : 32; /*!< [31..0] 数据寄存器X（Argument/Result Data Register X） */
+ } ARX0_b;
+ } ;
+
+ union {
+ __IOM uint32_t ARY0; /*!< (@ 0x00000008) CORDIC Argument / Result register0 */
+
+ struct {
+ __IOM uint32_t ARGRESY : 32; /*!< [31..0] 数据寄存器Y（Argument/Result Data Register Y） */
+ } ARY0_b;
+ } ;
+ __IM uint32_t RESERVED[5];
+
+ union {
+ __IOM uint32_t CSR1; /*!< (@ 0x00000020) CORDIC Control / Status register1 */
+
+ struct {
+ __IOM uint32_t FUNC : 4; /*!< [3..0] cordic计算的函数(Function) */
+ uint32_t : 4;
+ __IOM uint32_t SCALE : 5; /*!< [12..8] CORDIC比例因子设置(CORDIC Scale Setting) */
+ uint32_t : 3;
+ __IOM uint32_t RRDYIEN : 1; /*!< [16..16] 计算结果完成中断使能（Result Ready Interrupt
+ Enable) */
+ __IOM uint32_t ERRIEN : 1; /*!< [17..17] 错误中断使能(Error Interrupt Enable) */
+ uint32_t : 1;
+ __IOM uint32_t NRES : 1; /*!< [19..19] 输出数据的个数(Output Result Number) */
+ __IOM uint32_t NARGS : 1; /*!< [20..20] 输入数据的个数(Input Argument Number) */
+ __IOM uint32_t RESSIZE : 1; /*!< [21..21] 输出数据的宽度(Output Result Size) */
+ __IOM uint32_t ARGSIZE : 1; /*!< [22..22] 输入数据的宽度(Input Argument Size) */
+ uint32_t : 5;
+ __IOM uint32_t ERRCLR : 1; /*!< [28..28] 错误中断清除(Error Interrupt Clear) */
+ __IOM uint32_t RRDYCLR : 1; /*!< [29..29] 计算结果完成中断清除(Result Ready Interrupt
+ Clear) */
+ __IM uint32_t ERR : 1; /*!< [30..30] 错误中断状态(Error Interrupt Status) */
+ __IM uint32_t RRDY : 1; /*!< [31..31] 计算结果完成中断状态（Result Ready Interrupt
+ Status) */
+ } CSR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t ARX1; /*!< (@ 0x00000024) CORDIC Argument / Result register1 */
+
+ struct {
+ __IOM uint32_t ARGRESX : 32; /*!< [31..0] 数据寄存器X（Argument/Result Data Register X） */
+ } ARX1_b;
+ } ;
+
+ union {
+ __IOM uint32_t ARY1; /*!< (@ 0x00000028) CORDIC Argument / Result register1 */
+
+ struct {
+ __IOM uint32_t ARGRESY : 32; /*!< [31..0] 数据寄存器Y（Argument/Result Data Register Y） */
+ } ARY1_b;
+ } ;
+} CORDIC_Type; /*!< Size = 44 (0x2c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP0 (CMP0)
+ */
+
+typedef struct { /*!< (@ 0x4003A000) CMP0 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 比较使能 */
+ uint32_t : 1;
+ __IOM uint32_t CBLK : 1; /*!< [2..2] 软件消隐选择 */
+ __IOM uint32_t INP : 1; /*!< [3..3] 比较正端源选择 */
+ __IOM uint32_t HYST : 2; /*!< [5..4] 比较迟滞 */
+ __IOM uint32_t INM : 2; /*!< [7..6] 比较负端源选择 */
+ __IOM uint32_t BLANKING : 3; /*!< [10..8] 比较消隐事件选择 */
+ __IOM uint32_t ODEB : 1; /*!< [11..11] 比较输出同步选择 */
+ __IOM uint32_t OPOL : 1; /*!< [12..12] 比较输出极性选择 */
+ uint32_t : 19;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEB : 8; /*!< [7..0] 比较输出消抖值 */
+ uint32_t : 24;
+ } DEBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RISIE : 1; /*!< [0..0] 比较上升沿中断使能 */
+ __IOM uint32_t FALIE : 1; /*!< [1..1] 比较下降沿中断使能 */
+ uint32_t : 30;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t RIS : 1; /*!< [0..0] 比较上升沿中断标志位 */
+ __IOM uint32_t FAL : 1; /*!< [1..1] 比较下降沿中断标志位 */
+ __IM uint32_t OVAL : 1; /*!< [2..2] 比较输出状态 */
+ uint32_t : 29;
+ } ISR_b;
+ } ;
+} CMP0_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP1 (CMP1)
+ */
+
+typedef struct { /*!< (@ 0x4003A100) CMP1 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 比较使能 */
+ uint32_t : 1;
+ __IOM uint32_t CBLK : 1; /*!< [2..2] 软件消隐选择 */
+ __IOM uint32_t INP : 1; /*!< [3..3] 比较正端源选择 */
+ __IOM uint32_t HYST : 2; /*!< [5..4] 比较迟滞 */
+ __IOM uint32_t INM : 2; /*!< [7..6] 比较负端源选择 */
+ __IOM uint32_t BLANKING : 3; /*!< [10..8] 比较消隐事件选择 */
+ __IOM uint32_t ODEB : 1; /*!< [11..11] 比较输出同步选择 */
+ __IOM uint32_t OPOL : 1; /*!< [12..12] 比较输出极性选择 */
+ uint32_t : 19;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEB : 8; /*!< [7..0] 比较输出消抖值 */
+ uint32_t : 24;
+ } DEBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RISIE : 1; /*!< [0..0] 比较上升沿中断使能 */
+ __IOM uint32_t FALIE : 1; /*!< [1..1] 比较下降沿中断使能 */
+ uint32_t : 30;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t RIS : 1; /*!< [0..0] 比较上升沿中断标志位 */
+ __IOM uint32_t FAL : 1; /*!< [1..1] 比较下降沿中断标志位 */
+ __IM uint32_t OVAL : 1; /*!< [2..2] 比较输出状态 */
+ uint32_t : 29;
+ } ISR_b;
+ } ;
+} CMP1_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP2 (CMP2)
+ */
+
+typedef struct { /*!< (@ 0x4003A200) CMP2 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 比较使能 */
+ uint32_t : 1;
+ __IOM uint32_t CBLK : 1; /*!< [2..2] 软件消隐选择 */
+ __IOM uint32_t INP : 1; /*!< [3..3] 比较正端源选择 */
+ __IOM uint32_t HYST : 2; /*!< [5..4] 比较迟滞 */
+ __IOM uint32_t INM : 2; /*!< [7..6] 比较负端源选择 */
+ __IOM uint32_t BLANKING : 3; /*!< [10..8] 比较消隐事件选择 */
+ __IOM uint32_t ODEB : 1; /*!< [11..11] 比较输出同步选择 */
+ __IOM uint32_t OPOL : 1; /*!< [12..12] 比较输出极性选择 */
+ uint32_t : 19;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEB : 8; /*!< [7..0] 比较输出消抖值 */
+ uint32_t : 24;
+ } DEBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RISIE : 1; /*!< [0..0] 比较上升沿中断使能 */
+ __IOM uint32_t FALIE : 1; /*!< [1..1] 比较下降沿中断使能 */
+ uint32_t : 30;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t RIS : 1; /*!< [0..0] 比较上升沿中断标志位 */
+ __IOM uint32_t FAL : 1; /*!< [1..1] 比较下降沿中断标志位 */
+ __IM uint32_t OVAL : 1; /*!< [2..2] 比较输出状态 */
+ uint32_t : 29;
+ } ISR_b;
+ } ;
+} CMP2_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP3 (CMP3)
+ */
+
+typedef struct { /*!< (@ 0x4003A300) CMP3 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 比较使能 */
+ uint32_t : 1;
+ __IOM uint32_t CBLK : 1; /*!< [2..2] 软件消隐选择 */
+ __IOM uint32_t INP : 1; /*!< [3..3] 比较正端源选择 */
+ __IOM uint32_t HYST : 2; /*!< [5..4] 比较迟滞 */
+ __IOM uint32_t INM : 2; /*!< [7..6] 比较负端源选择 */
+ __IOM uint32_t BLANKING : 3; /*!< [10..8] 比较消隐事件选择 */
+ __IOM uint32_t ODEB : 1; /*!< [11..11] 比较输出同步选择 */
+ __IOM uint32_t OPOL : 1; /*!< [12..12] 比较输出极性选择 */
+ uint32_t : 19;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEB : 8; /*!< [7..0] 比较输出消抖值 */
+ uint32_t : 24;
+ } DEBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RISIE : 1; /*!< [0..0] 比较上升沿中断使能 */
+ __IOM uint32_t FALIE : 1; /*!< [1..1] 比较下降沿中断使能 */
+ uint32_t : 30;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t RIS : 1; /*!< [0..0] 比较上升沿中断标志位 */
+ __IOM uint32_t FAL : 1; /*!< [1..1] 比较下降沿中断标志位 */
+ __IM uint32_t OVAL : 1; /*!< [2..2] 比较输出状态 */
+ uint32_t : 29;
+ } ISR_b;
+ } ;
+} CMP3_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP4 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP4 (CMP4)
+ */
+
+typedef struct { /*!< (@ 0x4003A400) CMP4 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 比较使能 */
+ uint32_t : 1;
+ __IOM uint32_t CBLK : 1; /*!< [2..2] 软件消隐选择 */
+ __IOM uint32_t INP : 1; /*!< [3..3] 比较正端源选择 */
+ __IOM uint32_t HYST : 2; /*!< [5..4] 比较迟滞 */
+ __IOM uint32_t INM : 2; /*!< [7..6] 比较负端源选择 */
+ __IOM uint32_t BLANKING : 3; /*!< [10..8] 比较消隐事件选择 */
+ __IOM uint32_t ODEB : 1; /*!< [11..11] 比较输出同步选择 */
+ __IOM uint32_t OPOL : 1; /*!< [12..12] 比较输出极性选择 */
+ uint32_t : 19;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEB : 8; /*!< [7..0] 比较输出消抖值 */
+ uint32_t : 24;
+ } DEBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RISIE : 1; /*!< [0..0] 比较上升沿中断使能 */
+ __IOM uint32_t FALIE : 1; /*!< [1..1] 比较下降沿中断使能 */
+ uint32_t : 30;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t RIS : 1; /*!< [0..0] 比较上升沿中断标志位 */
+ __IOM uint32_t FAL : 1; /*!< [1..1] 比较下降沿中断标志位 */
+ __IM uint32_t OVAL : 1; /*!< [2..2] 比较输出状态 */
+ uint32_t : 29;
+ } ISR_b;
+ } ;
+} CMP4_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP5 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP5 (CMP5)
+ */
+
+typedef struct { /*!< (@ 0x4003A500) CMP5 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 比较使能 */
+ uint32_t : 1;
+ __IOM uint32_t CBLK : 1; /*!< [2..2] 软件消隐选择 */
+ __IOM uint32_t INP : 1; /*!< [3..3] 比较正端源选择 */
+ __IOM uint32_t HYST : 2; /*!< [5..4] 比较迟滞 */
+ __IOM uint32_t INM : 2; /*!< [7..6] 比较负端源选择 */
+ __IOM uint32_t BLANKING : 3; /*!< [10..8] 比较消隐事件选择 */
+ __IOM uint32_t ODEB : 1; /*!< [11..11] 比较输出同步选择 */
+ __IOM uint32_t OPOL : 1; /*!< [12..12] 比较输出极性选择 */
+ uint32_t : 19;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEB : 8; /*!< [7..0] 比较输出消抖值 */
+ uint32_t : 24;
+ } DEBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RISIE : 1; /*!< [0..0] 比较上升沿中断使能 */
+ __IOM uint32_t FALIE : 1; /*!< [1..1] 比较下降沿中断使能 */
+ uint32_t : 30;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t RIS : 1; /*!< [0..0] 比较上升沿中断标志位 */
+ __IOM uint32_t FAL : 1; /*!< [1..1] 比较下降沿中断标志位 */
+ __IM uint32_t OVAL : 1; /*!< [2..2] 比较输出状态 */
+ uint32_t : 29;
+ } ISR_b;
+ } ;
+} CMP5_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP6 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP6 (CMP6)
+ */
+
+typedef struct { /*!< (@ 0x4003A600) CMP6 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 比较使能 */
+ uint32_t : 1;
+ __IOM uint32_t CBLK : 1; /*!< [2..2] 软件消隐选择 */
+ __IOM uint32_t INP : 1; /*!< [3..3] 比较正端源选择 */
+ __IOM uint32_t HYST : 2; /*!< [5..4] 比较迟滞 */
+ __IOM uint32_t INM : 2; /*!< [7..6] 比较负端源选择 */
+ __IOM uint32_t BLANKING : 3; /*!< [10..8] 比较消隐事件选择 */
+ __IOM uint32_t ODEB : 1; /*!< [11..11] 比较输出同步选择 */
+ __IOM uint32_t OPOL : 1; /*!< [12..12] 比较输出极性选择 */
+ uint32_t : 19;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEB : 8; /*!< [7..0] 比较输出消抖值 */
+ uint32_t : 24;
+ } DEBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RISIE : 1; /*!< [0..0] 比较上升沿中断使能 */
+ __IOM uint32_t FALIE : 1; /*!< [1..1] 比较下降沿中断使能 */
+ uint32_t : 30;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t RIS : 1; /*!< [0..0] 比较上升沿中断标志位 */
+ __IOM uint32_t FAL : 1; /*!< [1..1] 比较下降沿中断标志位 */
+ __IM uint32_t OVAL : 1; /*!< [2..2] 比较输出状态 */
+ uint32_t : 29;
+ } ISR_b;
+ } ;
+} CMP6_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP7 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP7 (CMP7)
+ */
+
+typedef struct { /*!< (@ 0x4003A700) CMP7 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 比较使能 */
+ uint32_t : 1;
+ __IOM uint32_t CBLK : 1; /*!< [2..2] 软件消隐选择 */
+ __IOM uint32_t INP : 1; /*!< [3..3] 比较正端源选择 */
+ __IOM uint32_t HYST : 2; /*!< [5..4] 比较迟滞 */
+ __IOM uint32_t INM : 2; /*!< [7..6] 比较负端源选择 */
+ __IOM uint32_t BLANKING : 3; /*!< [10..8] 比较消隐事件选择 */
+ __IOM uint32_t ODEB : 1; /*!< [11..11] 比较输出同步选择 */
+ __IOM uint32_t OPOL : 1; /*!< [12..12] 比较输出极性选择 */
+ uint32_t : 19;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEB : 8; /*!< [7..0] 比较输出消抖值 */
+ uint32_t : 24;
+ } DEBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RISIE : 1; /*!< [0..0] 比较上升沿中断使能 */
+ __IOM uint32_t FALIE : 1; /*!< [1..1] 比较下降沿中断使能 */
+ uint32_t : 30;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t RIS : 1; /*!< [0..0] 比较上升沿中断标志位 */
+ __IOM uint32_t FAL : 1; /*!< [1..1] 比较下降沿中断标志位 */
+ __IM uint32_t OVAL : 1; /*!< [2..2] 比较输出状态 */
+ uint32_t : 29;
+ } ISR_b;
+ } ;
+} CMP7_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CMP8 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CMP8 (CMP8)
+ */
+
+typedef struct { /*!< (@ 0x4003A800) CMP8 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) CMPx Config Register */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 比较使能 */
+ uint32_t : 1;
+ __IOM uint32_t CBLK : 1; /*!< [2..2] 软件消隐选择 */
+ __IOM uint32_t INP : 1; /*!< [3..3] 比较正端源选择 */
+ __IOM uint32_t HYST : 2; /*!< [5..4] 比较迟滞 */
+ __IOM uint32_t INM : 2; /*!< [7..6] 比较负端源选择 */
+ __IOM uint32_t BLANKING : 3; /*!< [10..8] 比较消隐事件选择 */
+ __IOM uint32_t ODEB : 1; /*!< [11..11] 比较输出同步选择 */
+ __IOM uint32_t OPOL : 1; /*!< [12..12] 比较输出极性选择 */
+ uint32_t : 19;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DEBR; /*!< (@ 0x00000004) CMPx Debounce Register */
+
+ struct {
+ __IOM uint32_t DEB : 8; /*!< [7..0] 比较输出消抖值 */
+ uint32_t : 24;
+ } DEBR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000008) CMPx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t RISIE : 1; /*!< [0..0] 比较上升沿中断使能 */
+ __IOM uint32_t FALIE : 1; /*!< [1..1] 比较下降沿中断使能 */
+ uint32_t : 30;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x0000000C) CMPx Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t RIS : 1; /*!< [0..0] 比较上升沿中断标志位 */
+ __IOM uint32_t FAL : 1; /*!< [1..1] 比较下降沿中断标志位 */
+ __IM uint32_t OVAL : 1; /*!< [2..2] 比较输出状态 */
+ uint32_t : 29;
+ } ISR_b;
+ } ;
+} CMP8_Type; /*!< Size = 16 (0x10) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CAN0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CAN0 (CAN0)
+ */
+
+typedef struct { /*!< (@ 0x40014000) CAN0 Structure */
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000000) CAN Control Register */
+
+ struct {
+ __IOM uint32_t TSSS : 1; /*!< [0..0] STB的单发传输模式（Transmission Secondary Single
+ Shot mode for STB） */
+ __IOM uint32_t TPSS : 1; /*!< [1..1] PTB的单发传输模式（Transmission Primary Single
+ Shot mode for PTB） */
+ __IOM uint32_t LBMI : 1; /*!< [2..2] 内部的环回模式（Internal Loop Back） */
+ __IOM uint32_t LBME : 1; /*!< [3..3] 外部的环回模式（External Loop Back） */
+ __IOM uint32_t RESET : 1; /*!< [4..4] CAN复位控制位（RESET request bit） */
+ __IOM uint32_t TSA : 1; /*!< [5..5] STB传输中止（Transmit STB Abort） */
+ __IOM uint32_t TSALL : 1; /*!< [6..6] STB传输所有帧（STB Transmit All Frames） */
+ __IOM uint32_t TSONE : 1; /*!< [7..7] STB传输下一帧（STB Transmit One Frame） */
+ __IOM uint32_t TPA : 1; /*!< [8..8] PTB传送中止（PTB Transmit Abort） */
+ __IOM uint32_t TPE : 1; /*!< [9..9] PTB传输启用（PTB Transceiver Enable） */
+ uint32_t : 1;
+ __IOM uint32_t LOM : 1; /*!< [11..11] 仅收听模式（Listen Only Mode） */
+ __IOM uint32_t TBSEL : 1; /*!< [12..12] 发送缓冲器选择（Transmit Buffer Select） */
+ __IOM uint32_t MUXSEL : 1; /*!< [13..13] CAN输入信号通路选择（Receive Multiplexer Select） */
+ uint32_t : 1;
+ __IOM uint32_t PEDT : 1; /*!< [15..15] CAN FD协议异常检测禁止（Protocol Exception
+ Detect） */
+ __IOM uint32_t TSNEXT : 1; /*!< [16..16] STB发送缓冲区下一个使能（Transmit Buffer
+ Secondary Next） */
+ __IOM uint32_t FD_ISO : 1; /*!< [17..17] CAN FD ISO使能（CAN FD ISO Enable） */
+ __IOM uint32_t FD_EN : 1; /*!< [18..18] CAN FD使能（CAN FD Enable） */
+ uint32_t : 1;
+ __IOM uint32_t RREL : 1; /*!< [20..20] PRB接收缓冲区释放（Receive Buffer Release） */
+ __IOM uint32_t SREL : 1; /*!< [21..21] SRB接收缓冲区释放（Receive Buffer Release） */
+ __IOM uint32_t EREL : 1; /*!< [22..22] ETB接收缓冲区释放（Receive Buffer Release） */
+ uint32_t : 1;
+ __IOM uint32_t EWL : 4; /*!< [27..24] 错误警告极限（Error Warning Limit） */
+ __IOM uint32_t AFWL : 4; /*!< [31..28] PRB接收缓冲区几乎满限制（PRB Almost Full
+ Warning Limit） */
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x00000004) CAN Status Register */
+
+ struct {
+ __IM uint32_t BUSOFF : 1; /*!< [0..0] 总线启动状态位（Bus Status bit） */
+ __IM uint32_t TACTIVE : 1; /*!< [1..1] 发送状态位（Transmit Status bit） */
+ __IM uint32_t RACTIVE : 1; /*!< [2..2] 接收状态位（Receive Status bit） */
+ uint32_t : 2;
+ __IM uint32_t ESTAT : 2; /*!< [6..5] ETB接收缓冲区状态（ETB Receive Buffer Status） */
+ __IM uint32_t EOV : 1; /*!< [7..7] ETB接收缓冲区溢出（ETB Receive Buffer Overflow） */
+ __IM uint32_t TSSTAT : 5; /*!< [12..8] STB传输buffer状态位（Transmission Secondary Status
+ bits） */
+ __IM uint32_t SSTAT : 2; /*!< [14..13] SRB接收缓冲区状态（SRB Receive Buffer Status） */
+ __IM uint32_t SOV : 1; /*!< [15..15] SRB接收缓冲区溢出（SRB Receive Buffer Overflow） */
+ __IM uint32_t RSTAT : 2; /*!< [17..16] PRB接收缓冲区状态（PRB Receive Buffer Status） */
+ __IM uint32_t ROV : 1; /*!< [18..18] PRB接收缓冲区溢出（PRB Receive Buffer Overflow） */
+ uint32_t : 1;
+ __IOM uint32_t AEWL : 4; /*!< [23..20] STB发送缓冲区几乎空限制（STB Almost Empty
+ Warning Limit） */
+ __IOM uint32_t EAFWL : 4; /*!< [27..24] ETB接收缓冲区几乎满限制（ETB Almost Full
+ Warning Limit） */
+ __IOM uint32_t SAFWL : 4; /*!< [31..28] SRB接收缓冲区几乎满限制（SRB Almost Full
+ Warning Limit） */
+ } STATUS_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTREN; /*!< (@ 0x00000008) CAN Interrupt Enable Register */
+
+ struct {
+ __IM uint32_t TSFF : 1; /*!< [0..0] 发送辅助缓冲区满标志（Transmit Secondary Buffer
+ Full Flag） */
+ __IOM uint32_t EIE : 1; /*!< [1..1] 出错中断使能位（Error Interrupt Enable） */
+ __IOM uint32_t TSIE : 1; /*!< [2..2] STB传输中断使能位（STB Transmission Interrupt
+ Enable） */
+ __IOM uint32_t TPIE : 1; /*!< [3..3] PTB传输中断使能位（PTB Transmission Interrupt
+ Enable） */
+ __IOM uint32_t RAFIE : 1; /*!< [4..4] PRB将满中断使能位（PRB Almost Full Interrupt
+ Enable） */
+ __IOM uint32_t RFIE : 1; /*!< [5..5] PRB已满中断使能位（PRB Full Interrupt Enable） */
+ __IOM uint32_t ROIE : 1; /*!< [6..6] PRB溢出中断使能位（PRB Overrun Interrupt Enable） */
+ __IOM uint32_t RIE : 1; /*!< [7..7] PRB接收中断使能位（PRB Receive Interrupt Enable） */
+ __IOM uint32_t BEIE : 1; /*!< [8..8] 总线错误中断使能位（Bus Error Interrupt Enable） */
+ __IOM uint32_t ALIE : 1; /*!< [9..9] 仲裁丢失中断使能位（Arbitration Lost Interrupt
+ Enable） */
+ __IOM uint32_t EPIE : 1; /*!< [10..10] 被动错误中断使能位（Error Passive Interrupt
+ Enable） */
+ __IOM uint32_t ECIE : 1; /*!< [11..11] 错误计数中断使能位（Error Counter Interrupt
+ Enable） */
+ __IOM uint32_t ERIE : 1; /*!< [12..12] ETB接收中断使能位（ETB Receive Interrupt Enable） */
+ __IOM uint32_t SRIE : 1; /*!< [13..13] SRB接收中断使能位（SRB Receive Interrupt Enable） */
+ uint32_t : 3;
+ __IOM uint32_t AIE : 1; /*!< [17..17] 中止中断使能位（Abort Interrupt Enable） */
+ __IOM uint32_t EAFIE : 1; /*!< [18..18] ETB将满中断使能位（ETB Almost Full Interrupt
+ Enable） */
+ __IOM uint32_t EFIE : 1; /*!< [19..19] ETB已满中断使能位（ETB Full Interrupt Enable） */
+ __IOM uint32_t EOIE : 1; /*!< [20..20] ETB溢出中断使能位（ETB Overrun Interrupt Enable） */
+ __IOM uint32_t SAFIE : 1; /*!< [21..21] SRB将满中断使能位（SRB Almost Full Interrupt
+ Enable） */
+ __IOM uint32_t SFIE : 1; /*!< [22..22] SRB已满中断使能位（SRB Full Interrupt Enable） */
+ __IOM uint32_t SOIE : 1; /*!< [23..23] SRB溢出中断使能位（SRB Overrun Interrupt Enable） */
+ __IOM uint32_t CTOIE : 1; /*!< [24..24] 连续计数超时中断使能位（Cont Timeout Interrupt
+ Enable） */
+ __IOM uint32_t ETOIE : 1; /*!< [25..25] ETB接收超时中断使能位（ETB Timeout Interrupt
+ Enable） */
+ __IOM uint32_t STOIE : 1; /*!< [26..26] SRB接收超时中断使能位（SRB Timeout Interrupt
+ Enable） */
+ __IOM uint32_t RTOIE : 1; /*!< [27..27] PRB接收超时中断使能位（PRB Timeout Interrupt
+ Enable） */
+ __IOM uint32_t TSCIE : 1; /*!< [28..28] 时间戳计数中断使能位（Timestamp Interrupt
+ Enable） */
+ __IOM uint32_t PMIE : 1; /*!< [29..29] 优先级消息中断使能位（Priority Message Interrupt
+ Enable） */
+ __IOM uint32_t TAEIE : 1; /*!< [30..30] STB将空中断使能位（STB Almost Empty Interrupt
+ Enable） */
+ __IOM uint32_t TEIE : 1; /*!< [31..31] STB已空中断使能位（STB Empty Interrupt Enable） */
+ } INTREN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTRST; /*!< (@ 0x0000000C) CAN Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t AIF : 1; /*!< [0..0] 中止中断标志（Abort Interrupt Flag） */
+ __IOM uint32_t EIF : 1; /*!< [1..1] 错误中断标志（Error Interrupt Flag） */
+ __IOM uint32_t TSIF : 1; /*!< [2..2] STB传输中断标志（STB Transmission Interrupt Flag） */
+ __IOM uint32_t TPIF : 1; /*!< [3..3] PTB传输中断标志（PTB Transmission Interrupt Flag） */
+ __IOM uint32_t RAFIF : 1; /*!< [4..4] PRB几乎满中断标志（PRB Almost Full Interrupt
+ Flag） */
+ __IOM uint32_t RFIF : 1; /*!< [5..5] PRB满中断标志（PRB Full Interrupt Flag） */
+ __IOM uint32_t ROIF : 1; /*!< [6..6] PRB溢出中断标志（PRB Overflow Interrupt Flag） */
+ __IOM uint32_t RIF : 1; /*!< [7..7] PRB接收中断标志（PRB Receive Interrupt Flag） */
+ __IOM uint32_t BEIF : 1; /*!< [8..8] 总线错误中断标志（Bus Error Interrupt Flag） */
+ __IOM uint32_t ALIF : 1; /*!< [9..9] 仲裁丢失中断标志（Arbitration Lost Interrupt
+ Flag） */
+ __IOM uint32_t EPIF : 1; /*!< [10..10] 错误被动中断标志（Error Passive Interrupt
+ Flag） */
+ __IOM uint32_t ECIF : 1; /*!< [11..11] 错误计数中断标志（Error Counter Interrupt
+ Flag） */
+ __IOM uint32_t ERIF : 1; /*!< [12..12] ETB接收中断标志（ETB Receive Interrupt Flag） */
+ __IOM uint32_t SRIF : 1; /*!< [13..13] SRB接收中断标志（SRB Receive Interrupt Flag） */
+ uint32_t : 2;
+ __IM uint32_t EPASS : 1; /*!< [16..16] 错误被动模式有效（Error Passive Mode Active） */
+ __IM uint32_t EWARN : 1; /*!< [17..17] 达到错误警告限制（Error Warning Limit Reached） */
+ __IOM uint32_t EAFIF : 1; /*!< [18..18] ETB几乎满中断标志（ETB Almost Full Interrupt
+ Flag） */
+ __IOM uint32_t EFIF : 1; /*!< [19..19] ETB满中断标志（ETB Full Interrupt Flag） */
+ __IOM uint32_t EOIF : 1; /*!< [20..20] ETB溢出中断标志（ETB Overflow Interrupt Flag） */
+ __IOM uint32_t SAFIF : 1; /*!< [21..21] SRB几乎满中断标志（SRB Almost Full Interrupt
+ Flag） */
+ __IOM uint32_t SFIF : 1; /*!< [22..22] SRB满中断标志（SRB Full Interrupt Flag） */
+ __IOM uint32_t SOIF : 1; /*!< [23..23] SRB溢出中断标志（SRB Overflow Interrupt Flag） */
+ __IOM uint32_t CTOIF : 1; /*!< [24..24] 连续计数超时中断标志（Cont Timeout Interrupt
+ Flag） */
+ __IOM uint32_t ETOIF : 1; /*!< [25..25] ETB接收超时中断标志（ETB Timeout Interrupt
+ Flag） */
+ __IOM uint32_t STOIF : 1; /*!< [26..26] SRB接收超时中断标志（SRB Timeout Interrupt
+ Flag） */
+ __IOM uint32_t RTOIF : 1; /*!< [27..27] PRB接收超时中断标志（PRB Timeout Interrupt
+ Flag） */
+ __IOM uint32_t TSCIF : 1; /*!< [28..28] 时间戳计数中断标志（Timestamp Interrupt Flag） */
+ __IOM uint32_t PMIF : 1; /*!< [29..29] 优先级消息中断标志（Priority Message Interrupt
+ Flag） */
+ __IM uint32_t TAEIF : 1; /*!< [30..30] STB将空中断标志（STB Almost Empty Interrupt
+ Flag） */
+ __IM uint32_t TEIF : 1; /*!< [31..31] STB已空中断标志（STB Empty Interrupt Flag） */
+ } INTRST_b;
+ } ;
+
+ union {
+ __IOM uint32_t BITTIME; /*!< (@ 0x00000010) CAN Bittime Setting Register */
+
+ struct {
+ __IOM uint32_t S_SEG1 : 6; /*!< [5..0] 慢速模式下的位定时段1（Bit Timing Segment
+ 1 (slow speed)） */
+ __IOM uint32_t F_SJW : 2; /*!< [7..6] 快速模式下的同步跳转宽度（Synchronization
+ Jump Width (fast speed)） */
+ __IOM uint32_t S_SEG2 : 5; /*!< [12..8] 慢速模式小的为定时段2（Bit Timing Segment
+ 2(slow speed)） */
+ __IOM uint32_t F_SEG2 : 3; /*!< [15..13] 快速模式下的位定时段2（Bit Timing Segment
+ 2 (fast speed)） */
+ __IOM uint32_t S_SJW : 4; /*!< [19..16] 慢速模式下的同步跳转宽度（Synchronization
+ Jump Width (slow speed)） */
+ __IOM uint32_t F_SEG1 : 4; /*!< [23..20] 快速模式下的位定时段1（Bit Timing Segment
+ 1 (fast speed)） */
+ uint32_t : 8;
+ } BITTIME_b;
+ } ;
+
+ union {
+ __IOM uint32_t PRESC; /*!< (@ 0x00000014) CAN Prescaler Registers */
+
+ struct {
+ __IOM uint32_t S_PRESC : 8; /*!< [7..0] 低速模式下的预分频（Prescaler (slow speed)） */
+ __IOM uint32_t F_PRESC : 8; /*!< [15..8] 快速模式下的预分频（Prescaler (fast speed)） */
+ __IOM uint32_t SSPOFF : 5; /*!< [20..16] 第二采样点偏移控制位（Secondary Sample Point
+ OFFset） */
+ uint32_t : 2;
+ __IOM uint32_t TDCEN : 1; /*!< [23..23] 发送延时补偿使能位（Transmitter Delay Compensation
+ Enable） */
+ uint32_t : 8;
+ } PRESC_b;
+ } ;
+
+ union {
+ __IOM uint32_t ERRST; /*!< (@ 0x00000018) CAN Error Status Register */
+
+ struct {
+ __IM uint32_t ALC : 5; /*!< [4..0] 仲裁丢失捕获（Arbitration Lost Capture） */
+ __IM uint32_t KOER : 3; /*!< [7..5] 错误类型标志位(Kind Of Error (Error code)) */
+ __IM uint32_t ECNT : 8; /*!< [15..8] 错误计数（number of errors） */
+ __IM uint32_t TECNT : 8; /*!< [23..16] 发送错误计数（number of errors during transmission） */
+ __IM uint32_t RECNT : 8; /*!< [31..24] 接收错误计数（number of errors during reception） */
+ } ERRST_b;
+ } ;
+
+ union {
+ __IOM uint32_t PRTST; /*!< (@ 0x0000001C) CAN Protocol Status Register */
+
+ struct {
+ __IM uint32_t RBSTS : 2; /*!< [1..0] CAN接收帧存储方式（CAN RX Buffer Status） */
+ __IM uint32_t NDSTS : 2; /*!< [3..2] CAN节点状态（CAN Node Status） */
+ __IM uint32_t FDSTS : 4; /*!< [7..4] CAN接收的FD控制信息（CAN RX FD Status） */
+ __IM uint32_t DKOER : 3; /*!< [10..8] 数据场错误类型标志位(Data Kind Of Error (Error
+ code)) */
+ uint32_t : 21;
+ } PRTST_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTRLS; /*!< (@ 0x00000020) CAN Interrupt Line Select Register */
+
+ struct {
+ __IOM uint32_t AILS : 1; /*!< [0..0] 中止中断线选择位（Abort Interrupt Line Select） */
+ __IOM uint32_t EILS : 1; /*!< [1..1] 出错中断线选择位（Error Interrupt Line Select） */
+ __IOM uint32_t TSILS : 1; /*!< [2..2] STB传输中断线选择位（STB Transmission Interrupt
+ Line Select） */
+ __IOM uint32_t TPILS : 1; /*!< [3..3] PTB传输中断线选择位（PTB Transmission Interrupt
+ Line Select） */
+ __IOM uint32_t RAFILS : 1; /*!< [4..4] PRB将满中断线选择位（PRB Almost Full Interrupt
+ Line Select） */
+ __IOM uint32_t RFILS : 1; /*!< [5..5] PRB已满中断线选择位（PRB Full Interrupt Line
+ Select） */
+ __IOM uint32_t ROILS : 1; /*!< [6..6] PRB溢出中断线选择位（PRB Overrun Interrupt Line
+ Select） */
+ __IOM uint32_t RILS : 1; /*!< [7..7] PRB接收中断线选择位（PRB Receive Interrupt Line
+ Select） */
+ __IOM uint32_t BEILS : 1; /*!< [8..8] 总线错误中断线选择位（Bus Error Interrupt
+ Line Select） */
+ __IOM uint32_t ALILS : 1; /*!< [9..9] 仲裁丢失中断线选择位（Arbitration Lost Interrupt
+ Line Select） */
+ __IOM uint32_t EPILS : 1; /*!< [10..10] 被动错误中断线选择位（Error Passive Interrupt
+ Line Select） */
+ __IOM uint32_t ECILS : 1; /*!< [11..11] 错误计数中断线选择位（Error Counter Interrupt
+ Line Select） */
+ __IOM uint32_t ERILS : 1; /*!< [12..12] ETB接收中断线选择位（ETB Receive Interrupt
+ Line Select） */
+ __IOM uint32_t SRILS : 1; /*!< [13..13] SRB接收中断线选择位（SRB Receive Interrupt
+ Line Select） */
+ uint32_t : 4;
+ __IOM uint32_t EAFILS : 1; /*!< [18..18] ETB将满中断线选择位（ETB Almost Full Interrupt
+ Line Select） */
+ __IOM uint32_t EFILS : 1; /*!< [19..19] ETB已满中断线选择位（ETB Full Interrupt Line
+ Select） */
+ __IOM uint32_t EOILS : 1; /*!< [20..20] ETB溢出中断线选择位（ETB Overrun Interrupt
+ Line Select） */
+ __IOM uint32_t SAFILS : 1; /*!< [21..21] SRB将满中断线选择位（SRB Almost Full Interrupt
+ Line Select） */
+ __IOM uint32_t SFILS : 1; /*!< [22..22] SRB已满中断线选择位（SRB Full Interrupt Line
+ Select） */
+ __IOM uint32_t SOILS : 1; /*!< [23..23] SRB溢出中断线选择位（SRB Overrun Interrupt
+ Line Select） */
+ __IOM uint32_t CTOILS : 1; /*!< [24..24] 连续计数超时中断线选择位（Cont Timeout
+ Interrupt Line Select） */
+ __IOM uint32_t ETOILS : 1; /*!< [25..25] ETB接收超时中断线选择位（ETB Timeout Interrupt
+ Line Select） */
+ __IOM uint32_t STOILS : 1; /*!< [26..26] SRB接收超时中断线选择位（SRB Timeout Interrupt
+ Line Select） */
+ __IOM uint32_t RTOILS : 1; /*!< [27..27] PRB接收超时中断线选择位（PRB Timeout Interrupt
+ Line Select） */
+ __IOM uint32_t TSCILS : 1; /*!< [28..28] 时间戳计数中断线选择位（Timestamp Interrupt
+ Line Select） */
+ __IOM uint32_t PMILS : 1; /*!< [29..29] 优先级消息中断线选择位（Priority Message
+ Interrupt Line Select） */
+ __IOM uint32_t TAEILS : 1; /*!< [30..30] STB将空中断线选择位（STB Almost Empty Interrupt
+ Line Select） */
+ __IOM uint32_t TEILS : 1; /*!< [31..31] STB已空中断线选择位（STB Empty Interrupt Line
+ Select） */
+ } INTRLS_b;
+ } ;
+
+ union {
+ __IOM uint32_t GFCR; /*!< (@ 0x00000024) CAN Global Filter Control Register */
+
+ struct {
+ __IOM uint32_t SRBM : 1; /*!< [0..0] SRB工作模式（SRB Working Mode） */
+ __IOM uint32_t PRBM : 1; /*!< [1..1] PRB工作模式（PRB Working Mode） */
+ uint32_t : 4;
+ __IOM uint32_t ERFR : 1; /*!< [6..6] 拓展远程帧屏蔽（Extended Remote Frames Reject） */
+ __IOM uint32_t SRFR : 1; /*!< [7..7] 常规远程帧屏蔽（Standard Remote Frames Reject） */
+ uint32_t : 24;
+ } GFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EMCR; /*!< (@ 0x00000028) CAN Extended Mask Control Register */
+
+ struct {
+ __IOM uint32_t EIDM : 29; /*!< [28..0] 拓展帧全局掩码（Extended ID Mask） */
+ uint32_t : 3;
+ } EMCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PMST; /*!< (@ 0x0000002C) CAN Priority Message Status Register */
+
+ struct {
+ __IM uint32_t PMIS : 1; /*!< [0..0] 高优先级消息IDE状态（Priority Message IDE Status） */
+ __IM uint32_t PMBS : 2; /*!< [2..1] 高优先级消息存储状态（Priority Message Buffer
+ Status） */
+ uint32_t : 1;
+ __IM uint32_t PMAS : 4; /*!< [7..4] 高优先级消息验收状态（Priority Message Acceptance
+ Status） */
+ uint32_t : 24;
+ } PMST_b;
+ } ;
+
+ union {
+ __IOM uint32_t ACFEN; /*!< (@ 0x00000030) CAN ACF Enable */
+
+ struct {
+ __IOM uint32_t AE0 : 1; /*!< [0..0] 验收滤波器0启用（Acceptance filter 0 Enable） */
+ __IOM uint32_t AE1 : 1; /*!< [1..1] 验收滤波器1启用（Acceptance filter 1 Enable） */
+ __IOM uint32_t AE2 : 1; /*!< [2..2] 验收滤波器2启用（Acceptance filter 2 Enable） */
+ __IOM uint32_t AE3 : 1; /*!< [3..3] 验收滤波器3启用（Acceptance filter 3 Enable） */
+ __IOM uint32_t AE4 : 1; /*!< [4..4] 验收滤波器4启用（Acceptance filter 4 Enable） */
+ __IOM uint32_t AE5 : 1; /*!< [5..5] 验收滤波器5启用（Acceptance filter 5 Enable） */
+ __IOM uint32_t AE6 : 1; /*!< [6..6] 验收滤波器6启用（Acceptance filter 6 Enable） */
+ __IOM uint32_t AE7 : 1; /*!< [7..7] 验收滤波器7启用（Acceptance filter 7 Enable） */
+ __IOM uint32_t AE8 : 1; /*!< [8..8] 验收滤波器8启用（Acceptance filter 8 Enable） */
+ __IOM uint32_t AE9 : 1; /*!< [9..9] 验收滤波器9启用（Acceptance filter 9 Enable） */
+ __IOM uint32_t AE10 : 1; /*!< [10..10] 验收滤波器10启用（Acceptance filter 10 Enable） */
+ __IOM uint32_t AE11 : 1; /*!< [11..11] 验收滤波器11启用（Acceptance filter 11 Enable） */
+ __IOM uint32_t AE12 : 1; /*!< [12..12] 验收滤波器12启用（Acceptance filter 12 Enable） */
+ __IOM uint32_t AE13 : 1; /*!< [13..13] 验收滤波器13启用（Acceptance filter 13 Enable） */
+ __IOM uint32_t AE14 : 1; /*!< [14..14] 验收滤波器14启用（Acceptance filter 14 Enable） */
+ __IOM uint32_t AE15 : 1; /*!< [15..15] 验收滤波器15启用（Acceptance filter 15 Enable） */
+ uint32_t : 16;
+ } ACFEN_b;
+ } ;
+
+ union {
+ __IOM uint32_t ACFCTRL; /*!< (@ 0x00000034) CAN ACF Control Register */
+
+ struct {
+ __IOM uint32_t ACFADR : 4; /*!< [3..0] 验收滤波器的地址（acceptance filter address） */
+ uint32_t : 1;
+ __IOM uint32_t SELMASK : 1; /*!< [5..5] 验收码和屏蔽码的选择位（Select acceptance
+ MASK） */
+ uint32_t : 26;
+ } ACFCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t ACF; /*!< (@ 0x00000038) CAN ACF Data Register */
+
+ struct {
+ __IOM uint32_t ACF_X : 29; /*!< [28..0] 当SELMASK=0： */
+ __IOM uint32_t AIDE : 1; /*!< [29..29] 验收掩码IDE位的控制位（Acceptance mask IDE
+ bit value） */
+ __IOM uint32_t AIDEE : 1; /*!< [30..30] 验收掩码IDE位的检查使能位（Acceptance mask
+ IDE bit check enable） */
+ uint32_t : 1;
+ } ACF_b;
+ } ;
+
+ union {
+ __IOM uint32_t ACFE; /*!< (@ 0x0000003C) CAN ACF Data Extended Register */
+
+ struct {
+ __IOM uint32_t ACF_C : 4; /*!< [3..0] CAN验收滤波器的控制信息（CAN Acceptance Control） */
+ __IOM uint32_t ACF_M : 4; /*!< [7..4] CAN验收滤波器的模式信息（CAN Acceptance Mode） */
+ uint32_t : 24;
+ } ACFE_b;
+ } ;
+
+ union {
+ __IOM uint32_t RBUFID; /*!< (@ 0x00000040) CAN RX Buffer Read Register(ID) */
+
+ struct {
+ __IM uint32_t RXD_ID : 32; /*!< [31..0] CAN接收的ID信息（CAN RX Identifier Data） */
+ } RBUFID_b;
+ } ;
+
+ union {
+ __IOM uint32_t RBUFCR; /*!< (@ 0x00000044) CAN RX Buffer Read Register(Control) */
+
+ struct {
+ __IM uint32_t RXD_DLC : 4; /*!< [3..0] CAN接收的数据量（CAN RX DATA Count） */
+ __IM uint32_t RXD_CR : 4; /*!< [7..4] CAN接收的控制信息（CAN RX Control Data） */
+ __IM uint32_t RXD_TS : 16; /*!< [23..8] CAN接收的时间戳（CAN RX Data Timestamp） */
+ __IM uint32_t RXD_ACF : 4; /*!< [27..24] CAN接收的验收滤波信息（CAN RX Acceptance
+ Data） */
+ uint32_t : 4;
+ } RBUFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RBUFDT[16]; /*!< (@ 0x00000048) CAN RX Buffer Read Register(Data) */
+
+ struct {
+ __IM uint32_t RXD_BYTE0 : 8; /*!< [7..0] CAN接收的数据字节0（CAN RX Data Byte 0） */
+ __IM uint32_t RXD_BYTE1 : 8; /*!< [15..8] CAN接收的数据字节1（CAN RX Data Byte 1） */
+ __IM uint32_t RXD_BYTE2 : 8; /*!< [23..16] CAN接收的数据字节2（CAN RX Data Byte 2） */
+ __IM uint32_t RXD_BYTE3 : 8; /*!< [31..24] CAN接收的数据字节3（CAN RX Data Byte 3） */
+ } RBUFDT_b[16];
+ } ;
+
+ union {
+ __IOM uint32_t TBUFID; /*!< (@ 0x00000088) CAN TX Buffer Write Register(ID) */
+
+ struct {
+ __IOM uint32_t TXD_ID : 32; /*!< [31..0] CAN发送的ID信息（CAN TX Identifier Data） */
+ } TBUFID_b;
+ } ;
+
+ union {
+ __IOM uint32_t TBUFCR; /*!< (@ 0x0000008C) CAN TX Buffer Write Register(Control) */
+
+ struct {
+ __IOM uint32_t TXD_DLC : 4; /*!< [3..0] CAN发送的数据量（CAN TX DATA Count） */
+ __IOM uint32_t TXD_CR : 4; /*!< [7..4] CAN发送的控制信息（CAN TX Control Data） */
+ __IOM uint32_t TXD_MM : 8; /*!< [15..8] CAN发送的帧标记（CAN TX Data Message Marker） */
+ uint32_t : 15;
+ __IOM uint32_t TXD_ETB : 1; /*!< [31..31] CAN发送的信息是否写入ETB（CAN TX Event Buffer） */
+ } TBUFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TBUFDT[16]; /*!< (@ 0x00000090) CAN TX Buffer Write Register(Data) */
+
+ struct {
+ __IOM uint32_t TXD_BYTE0 : 8; /*!< [7..0] CAN发送的数据字节0（CAN TX Data Byte 0） */
+ __IOM uint32_t TXD_BYTE1 : 8; /*!< [15..8] CAN发送的数据字节1（CAN TX Data Byte 1） */
+ __IOM uint32_t TXD_BYTE2 : 8; /*!< [23..16] CAN发送的数据字节2（CAN TX Data Byte 2） */
+ __IOM uint32_t TXD_BYTE3 : 8; /*!< [31..24] CAN发送的数据字节3（CAN TX Data Byte 3） */
+ } TBUFDT_b[16];
+ } ;
+ __IM uint32_t RESERVED[26];
+
+ union {
+ __IOM uint32_t EBUFID; /*!< (@ 0x00000138) CAN ETB Buffer Read Register(ID) */
+
+ struct {
+ __IM uint32_t TXD_ID : 32; /*!< [31..0] CAN发送的ID信息（CAN TX Identifier Data） */
+ } EBUFID_b;
+ } ;
+
+ union {
+ __IOM uint32_t EBUFDT; /*!< (@ 0x0000013C) CAN ETB Buffer Read Register(Data) */
+
+ struct {
+ __IM uint32_t TXD_DLC : 4; /*!< [3..0] CAN发送的数据量（CAN TX DATA Count） */
+ __IM uint32_t TXD_CR : 4; /*!< [7..4] CAN发送的控制信息（CAN TX Control Data） */
+ __IM uint32_t TXD_TS : 16; /*!< [23..8] CAN发送的时间戳（CAN TX Data Timestamp） */
+ __IM uint32_t TXD_MM : 8; /*!< [31..24] CAN发送的帧标记（CAN TX Data Message Marker） */
+ } EBUFDT_b;
+ } ;
+
+ union {
+ __IOM uint32_t SBUFID; /*!< (@ 0x00000140) CAN SRB Buffer Read Register(ID) */
+
+ struct {
+ __IM uint32_t RXD_ID : 32; /*!< [31..0] CAN接收的ID信息（CAN RX Identifier Data） */
+ } SBUFID_b;
+ } ;
+
+ union {
+ __IOM uint32_t SBUFCR; /*!< (@ 0x00000144) CAN SRB Buffer Read Register(Control) */
+
+ struct {
+ __IM uint32_t RXD_DLC : 4; /*!< [3..0] CAN接收的数据量（CAN RX DATA Count） */
+ __IM uint32_t RXD_CR : 4; /*!< [7..4] CAN接收的控制信息（CAN RX Control Data） */
+ __IM uint32_t RXD_TS : 16; /*!< [23..8] CAN接收的时间戳（CAN RX Data Timestamp） */
+ __IM uint32_t RXD_ACF : 4; /*!< [27..24] CAN接收的验收滤波信息（CAN RX Acceptance
+ Data） */
+ uint32_t : 4;
+ } SBUFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SBUFDT[16]; /*!< (@ 0x00000148) CAN SRB Buffer Read Register(Data) */
+
+ struct {
+ __IM uint32_t RXD_BYTE0 : 8; /*!< [7..0] CAN接收的数据字节0（CAN RX Data Byte 0） */
+ __IM uint32_t RXD_BYTE1 : 8; /*!< [15..8] CAN接收的数据字节1（CAN RX Data Byte 1） */
+ __IM uint32_t RXD_BYTE2 : 8; /*!< [23..16] CAN接收的数据字节2（CAN RX Data Byte 2） */
+ __IM uint32_t RXD_BYTE3 : 8; /*!< [31..24] CAN接收的数据字节3（CAN RX Data Byte 3） */
+ } SBUFDT_b[16];
+ } ;
+ __IM uint32_t RESERVED1[158];
+
+ union {
+ __IOM uint32_t TSCR; /*!< (@ 0x00000400) Timestamp Counter Control Register */
+
+ struct {
+ uint32_t : 16;
+ __IOM uint32_t TSS : 4; /*!< [19..16] 时间戳选择（Timestamp Select） */
+ __IOM uint32_t TSP : 4; /*!< [23..20] 时间戳预分频（Timestamp Prescaler） */
+ uint32_t : 8;
+ } TSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TSC; /*!< (@ 0x00000404) Timestamp Counter Value Register */
+
+ struct {
+ __IM uint32_t TSC : 16; /*!< [15..0] 时间戳计数（Timestamp Counter） */
+ uint32_t : 16;
+ } TSC_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t RTOP; /*!< (@ 0x00000410) PRB Timeout Counter Period Register */
+
+ struct {
+ __IOM uint32_t RTOP : 16; /*!< [15..0] PRB超时功能周期（PRB Timeout Period） */
+ uint32_t : 8;
+ __IOM uint32_t RTOE : 1; /*!< [24..24] PRB超时功能使能（PRB Timeout Enable） */
+ uint32_t : 7;
+ } RTOP_b;
+ } ;
+
+ union {
+ __IOM uint32_t RTOC; /*!< (@ 0x00000414) PRB Timeout Counter Value Register */
+
+ struct {
+ __IM uint32_t RTOC : 16; /*!< [15..0] PRB超时功能计数（PRB Timeout Counter） */
+ uint32_t : 16;
+ } RTOC_b;
+ } ;
+ __IM uint32_t RESERVED3[2];
+
+ union {
+ __IOM uint32_t STOP; /*!< (@ 0x00000420) SRB Timeout Counter Period Register */
+
+ struct {
+ __IOM uint32_t STOP : 16; /*!< [15..0] SRB超时功能周期（SRB Timeout Period） */
+ uint32_t : 8;
+ __IOM uint32_t STOE : 1; /*!< [24..24] SRB超时功能使能（SRB Timeout Enable） */
+ uint32_t : 7;
+ } STOP_b;
+ } ;
+
+ union {
+ __IOM uint32_t STOC; /*!< (@ 0x00000424) SRB Timeout Counter Value Register */
+
+ struct {
+ __IM uint32_t STOC : 16; /*!< [15..0] SRB超时功能计数（SRB Timeout Counter） */
+ uint32_t : 16;
+ } STOC_b;
+ } ;
+ __IM uint32_t RESERVED4[2];
+
+ union {
+ __IOM uint32_t ETOP; /*!< (@ 0x00000430) ETB Timeout Counter Period Register */
+
+ struct {
+ __IOM uint32_t ETOP : 16; /*!< [15..0] ETB超时功能周期（ETB Timeout Period） */
+ uint32_t : 8;
+ __IOM uint32_t ETOE : 1; /*!< [24..24] ETB超时功能使能（ETB Timeout Enable） */
+ uint32_t : 7;
+ } ETOP_b;
+ } ;
+
+ union {
+ __IOM uint32_t ETOC; /*!< (@ 0x00000434) ETB Timeout Counter Value Register */
+
+ struct {
+ __IM uint32_t ETOC : 16; /*!< [15..0] ETB超时功能计数（ETB Timeout Counter） */
+ uint32_t : 16;
+ } ETOC_b;
+ } ;
+ __IM uint32_t RESERVED5[2];
+
+ union {
+ __IOM uint32_t CTOP; /*!< (@ 0x00000440) Continuous Timeout Counter Period Register */
+
+ struct {
+ __IOM uint32_t CTOP : 16; /*!< [15..0] 连续超时功能周期（Cont Timeout Period） */
+ uint32_t : 8;
+ __IOM uint32_t CTOE : 1; /*!< [24..24] 连续超时功能使能（Cont Timeout Enable） */
+ uint32_t : 7;
+ } CTOP_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTOC; /*!< (@ 0x00000444) Continuous Timeout Counter Value Register */
+
+ struct {
+ __IM uint32_t CTOC : 16; /*!< [15..0] 连续超时功能计数（Cont Timeout Counter） */
+ uint32_t : 16;
+ } CTOC_b;
+ } ;
+} CAN0_Type; /*!< Size = 1096 (0x448) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CAN1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief CAN1 (CAN1)
+ */
+
+typedef struct { /*!< (@ 0x40015000) CAN1 Structure */
+
+ union {
+ __IOM uint32_t CTRL; /*!< (@ 0x00000000) CAN Control Register */
+
+ struct {
+ __IOM uint32_t TSSS : 1; /*!< [0..0] STB的单发传输模式（Transmission Secondary Single
+ Shot mode for STB） */
+ __IOM uint32_t TPSS : 1; /*!< [1..1] PTB的单发传输模式（Transmission Primary Single
+ Shot mode for PTB） */
+ __IOM uint32_t LBMI : 1; /*!< [2..2] 内部的环回模式（Internal Loop Back） */
+ __IOM uint32_t LBME : 1; /*!< [3..3] 外部的环回模式（External Loop Back） */
+ __IOM uint32_t RESET : 1; /*!< [4..4] CAN复位控制位（RESET request bit） */
+ __IOM uint32_t TSA : 1; /*!< [5..5] STB传输中止（Transmit STB Abort） */
+ __IOM uint32_t TSALL : 1; /*!< [6..6] STB传输所有帧（STB Transmit All Frames） */
+ __IOM uint32_t TSONE : 1; /*!< [7..7] STB传输下一帧（STB Transmit One Frame） */
+ __IOM uint32_t TPA : 1; /*!< [8..8] PTB传送中止（PTB Transmit Abort） */
+ __IOM uint32_t TPE : 1; /*!< [9..9] PTB传输启用（PTB Transceiver Enable） */
+ uint32_t : 1;
+ __IOM uint32_t LOM : 1; /*!< [11..11] 仅收听模式（Listen Only Mode） */
+ __IOM uint32_t TBSEL : 1; /*!< [12..12] 发送缓冲器选择（Transmit Buffer Select） */
+ __IOM uint32_t MUXSEL : 1; /*!< [13..13] CAN输入信号通路选择（Receive Multiplexer Select） */
+ uint32_t : 1;
+ __IOM uint32_t PEDT : 1; /*!< [15..15] CAN FD协议异常检测禁止（Protocol Exception
+ Detect） */
+ __IOM uint32_t TSNEXT : 1; /*!< [16..16] STB发送缓冲区下一个使能（Transmit Buffer
+ Secondary Next） */
+ __IOM uint32_t FD_ISO : 1; /*!< [17..17] CAN FD ISO使能（CAN FD ISO Enable） */
+ __IOM uint32_t FD_EN : 1; /*!< [18..18] CAN FD使能（CAN FD Enable） */
+ uint32_t : 1;
+ __IOM uint32_t RREL : 1; /*!< [20..20] PRB接收缓冲区释放（Receive Buffer Release） */
+ __IOM uint32_t SREL : 1; /*!< [21..21] SRB接收缓冲区释放（Receive Buffer Release） */
+ __IOM uint32_t EREL : 1; /*!< [22..22] ETB接收缓冲区释放（Receive Buffer Release） */
+ uint32_t : 1;
+ __IOM uint32_t EWL : 4; /*!< [27..24] 错误警告极限（Error Warning Limit） */
+ __IOM uint32_t AFWL : 4; /*!< [31..28] PRB接收缓冲区几乎满限制（PRB Almost Full
+ Warning Limit） */
+ } CTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t STATUS; /*!< (@ 0x00000004) CAN Status Register */
+
+ struct {
+ __IM uint32_t BUSOFF : 1; /*!< [0..0] 总线启动状态位（Bus Status bit） */
+ __IM uint32_t TACTIVE : 1; /*!< [1..1] 发送状态位（Transmit Status bit） */
+ __IM uint32_t RACTIVE : 1; /*!< [2..2] 接收状态位（Receive Status bit） */
+ uint32_t : 2;
+ __IM uint32_t ESTAT : 2; /*!< [6..5] ETB接收缓冲区状态（ETB Receive Buffer Status） */
+ __IM uint32_t EOV : 1; /*!< [7..7] ETB接收缓冲区溢出（ETB Receive Buffer Overflow） */
+ __IM uint32_t TSSTAT : 5; /*!< [12..8] STB传输buffer状态位（Transmission Secondary Status
+ bits） */
+ __IM uint32_t SSTAT : 2; /*!< [14..13] SRB接收缓冲区状态（SRB Receive Buffer Status） */
+ __IM uint32_t SOV : 1; /*!< [15..15] SRB接收缓冲区溢出（SRB Receive Buffer Overflow） */
+ __IM uint32_t RSTAT : 2; /*!< [17..16] PRB接收缓冲区状态（PRB Receive Buffer Status） */
+ __IM uint32_t ROV : 1; /*!< [18..18] PRB接收缓冲区溢出（PRB Receive Buffer Overflow） */
+ uint32_t : 1;
+ __IOM uint32_t AEWL : 4; /*!< [23..20] STB发送缓冲区几乎空限制（STB Almost Empty
+ Warning Limit） */
+ __IOM uint32_t EAFWL : 4; /*!< [27..24] ETB接收缓冲区几乎满限制（ETB Almost Full
+ Warning Limit） */
+ __IOM uint32_t SAFWL : 4; /*!< [31..28] SRB接收缓冲区几乎满限制（SRB Almost Full
+ Warning Limit） */
+ } STATUS_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTREN; /*!< (@ 0x00000008) CAN Interrupt Enable Register */
+
+ struct {
+ __IM uint32_t TSFF : 1; /*!< [0..0] 发送辅助缓冲区满标志（Transmit Secondary Buffer
+ Full Flag） */
+ __IOM uint32_t EIE : 1; /*!< [1..1] 出错中断使能位（Error Interrupt Enable） */
+ __IOM uint32_t TSIE : 1; /*!< [2..2] STB传输中断使能位（STB Transmission Interrupt
+ Enable） */
+ __IOM uint32_t TPIE : 1; /*!< [3..3] PTB传输中断使能位（PTB Transmission Interrupt
+ Enable） */
+ __IOM uint32_t RAFIE : 1; /*!< [4..4] PRB将满中断使能位（PRB Almost Full Interrupt
+ Enable） */
+ __IOM uint32_t RFIE : 1; /*!< [5..5] PRB已满中断使能位（PRB Full Interrupt Enable） */
+ __IOM uint32_t ROIE : 1; /*!< [6..6] PRB溢出中断使能位（PRB Overrun Interrupt Enable） */
+ __IOM uint32_t RIE : 1; /*!< [7..7] PRB接收中断使能位（PRB Receive Interrupt Enable） */
+ __IOM uint32_t BEIE : 1; /*!< [8..8] 总线错误中断使能位（Bus Error Interrupt Enable） */
+ __IOM uint32_t ALIE : 1; /*!< [9..9] 仲裁丢失中断使能位（Arbitration Lost Interrupt
+ Enable） */
+ __IOM uint32_t EPIE : 1; /*!< [10..10] 被动错误中断使能位（Error Passive Interrupt
+ Enable） */
+ __IOM uint32_t ECIE : 1; /*!< [11..11] 错误计数中断使能位（Error Counter Interrupt
+ Enable） */
+ __IOM uint32_t ERIE : 1; /*!< [12..12] ETB接收中断使能位（ETB Receive Interrupt Enable） */
+ __IOM uint32_t SRIE : 1; /*!< [13..13] SRB接收中断使能位（SRB Receive Interrupt Enable） */
+ uint32_t : 3;
+ __IOM uint32_t AIE : 1; /*!< [17..17] 中止中断使能位（Abort Interrupt Enable） */
+ __IOM uint32_t EAFIE : 1; /*!< [18..18] ETB将满中断使能位（ETB Almost Full Interrupt
+ Enable） */
+ __IOM uint32_t EFIE : 1; /*!< [19..19] ETB已满中断使能位（ETB Full Interrupt Enable） */
+ __IOM uint32_t EOIE : 1; /*!< [20..20] ETB溢出中断使能位（ETB Overrun Interrupt Enable） */
+ __IOM uint32_t SAFIE : 1; /*!< [21..21] SRB将满中断使能位（SRB Almost Full Interrupt
+ Enable） */
+ __IOM uint32_t SFIE : 1; /*!< [22..22] SRB已满中断使能位（SRB Full Interrupt Enable） */
+ __IOM uint32_t SOIE : 1; /*!< [23..23] SRB溢出中断使能位（SRB Overrun Interrupt Enable） */
+ __IOM uint32_t CTOIE : 1; /*!< [24..24] 连续计数超时中断使能位（Cont Timeout Interrupt
+ Enable） */
+ __IOM uint32_t ETOIE : 1; /*!< [25..25] ETB接收超时中断使能位（ETB Timeout Interrupt
+ Enable） */
+ __IOM uint32_t STOIE : 1; /*!< [26..26] SRB接收超时中断使能位（SRB Timeout Interrupt
+ Enable） */
+ __IOM uint32_t RTOIE : 1; /*!< [27..27] PRB接收超时中断使能位（PRB Timeout Interrupt
+ Enable） */
+ __IOM uint32_t TSCIE : 1; /*!< [28..28] 时间戳计数中断使能位（Timestamp Interrupt
+ Enable） */
+ __IOM uint32_t PMIE : 1; /*!< [29..29] 优先级消息中断使能位（Priority Message Interrupt
+ Enable） */
+ __IOM uint32_t TAEIE : 1; /*!< [30..30] STB将空中断使能位（STB Almost Empty Interrupt
+ Enable） */
+ __IOM uint32_t TEIE : 1; /*!< [31..31] STB已空中断使能位（STB Empty Interrupt Enable） */
+ } INTREN_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTRST; /*!< (@ 0x0000000C) CAN Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t AIF : 1; /*!< [0..0] 中止中断标志（Abort Interrupt Flag） */
+ __IOM uint32_t EIF : 1; /*!< [1..1] 错误中断标志（Error Interrupt Flag） */
+ __IOM uint32_t TSIF : 1; /*!< [2..2] STB传输中断标志（STB Transmission Interrupt Flag） */
+ __IOM uint32_t TPIF : 1; /*!< [3..3] PTB传输中断标志（PTB Transmission Interrupt Flag） */
+ __IOM uint32_t RAFIF : 1; /*!< [4..4] PRB几乎满中断标志（PRB Almost Full Interrupt
+ Flag） */
+ __IOM uint32_t RFIF : 1; /*!< [5..5] PRB满中断标志（PRB Full Interrupt Flag） */
+ __IOM uint32_t ROIF : 1; /*!< [6..6] PRB溢出中断标志（PRB Overflow Interrupt Flag） */
+ __IOM uint32_t RIF : 1; /*!< [7..7] PRB接收中断标志（PRB Receive Interrupt Flag） */
+ __IOM uint32_t BEIF : 1; /*!< [8..8] 总线错误中断标志（Bus Error Interrupt Flag） */
+ __IOM uint32_t ALIF : 1; /*!< [9..9] 仲裁丢失中断标志（Arbitration Lost Interrupt
+ Flag） */
+ __IOM uint32_t EPIF : 1; /*!< [10..10] 错误被动中断标志（Error Passive Interrupt
+ Flag） */
+ __IOM uint32_t ECIF : 1; /*!< [11..11] 错误计数中断标志（Error Counter Interrupt
+ Flag） */
+ __IOM uint32_t ERIF : 1; /*!< [12..12] ETB接收中断标志（ETB Receive Interrupt Flag） */
+ __IOM uint32_t SRIF : 1; /*!< [13..13] SRB接收中断标志（SRB Receive Interrupt Flag） */
+ uint32_t : 2;
+ __IM uint32_t EPASS : 1; /*!< [16..16] 错误被动模式有效（Error Passive Mode Active） */
+ __IM uint32_t EWARN : 1; /*!< [17..17] 达到错误警告限制（Error Warning Limit Reached） */
+ __IOM uint32_t EAFIF : 1; /*!< [18..18] ETB几乎满中断标志（ETB Almost Full Interrupt
+ Flag） */
+ __IOM uint32_t EFIF : 1; /*!< [19..19] ETB满中断标志（ETB Full Interrupt Flag） */
+ __IOM uint32_t EOIF : 1; /*!< [20..20] ETB溢出中断标志（ETB Overflow Interrupt Flag） */
+ __IOM uint32_t SAFIF : 1; /*!< [21..21] SRB几乎满中断标志（SRB Almost Full Interrupt
+ Flag） */
+ __IOM uint32_t SFIF : 1; /*!< [22..22] SRB满中断标志（SRB Full Interrupt Flag） */
+ __IOM uint32_t SOIF : 1; /*!< [23..23] SRB溢出中断标志（SRB Overflow Interrupt Flag） */
+ __IOM uint32_t CTOIF : 1; /*!< [24..24] 连续计数超时中断标志（Cont Timeout Interrupt
+ Flag） */
+ __IOM uint32_t ETOIF : 1; /*!< [25..25] ETB接收超时中断标志（ETB Timeout Interrupt
+ Flag） */
+ __IOM uint32_t STOIF : 1; /*!< [26..26] SRB接收超时中断标志（SRB Timeout Interrupt
+ Flag） */
+ __IOM uint32_t RTOIF : 1; /*!< [27..27] PRB接收超时中断标志（PRB Timeout Interrupt
+ Flag） */
+ __IOM uint32_t TSCIF : 1; /*!< [28..28] 时间戳计数中断标志（Timestamp Interrupt Flag） */
+ __IOM uint32_t PMIF : 1; /*!< [29..29] 优先级消息中断标志（Priority Message Interrupt
+ Flag） */
+ __IM uint32_t TAEIF : 1; /*!< [30..30] STB将空中断标志（STB Almost Empty Interrupt
+ Flag） */
+ __IM uint32_t TEIF : 1; /*!< [31..31] STB已空中断标志（STB Empty Interrupt Flag） */
+ } INTRST_b;
+ } ;
+
+ union {
+ __IOM uint32_t BITTIME; /*!< (@ 0x00000010) CAN Bittime Setting Register */
+
+ struct {
+ __IOM uint32_t S_SEG1 : 6; /*!< [5..0] 慢速模式下的位定时段1（Bit Timing Segment
+ 1 (slow speed)） */
+ __IOM uint32_t F_SJW : 2; /*!< [7..6] 快速模式下的同步跳转宽度（Synchronization
+ Jump Width (fast speed)） */
+ __IOM uint32_t S_SEG2 : 5; /*!< [12..8] 慢速模式小的为定时段2（Bit Timing Segment
+ 2(slow speed)） */
+ __IOM uint32_t F_SEG2 : 3; /*!< [15..13] 快速模式下的位定时段2（Bit Timing Segment
+ 2 (fast speed)） */
+ __IOM uint32_t S_SJW : 4; /*!< [19..16] 慢速模式下的同步跳转宽度（Synchronization
+ Jump Width (slow speed)） */
+ __IOM uint32_t F_SEG1 : 4; /*!< [23..20] 快速模式下的位定时段1（Bit Timing Segment
+ 1 (fast speed)） */
+ uint32_t : 8;
+ } BITTIME_b;
+ } ;
+
+ union {
+ __IOM uint32_t PRESC; /*!< (@ 0x00000014) CAN Prescaler Registers */
+
+ struct {
+ __IOM uint32_t S_PRESC : 8; /*!< [7..0] 低速模式下的预分频（Prescaler (slow speed)） */
+ __IOM uint32_t F_PRESC : 8; /*!< [15..8] 快速模式下的预分频（Prescaler (fast speed)） */
+ __IOM uint32_t SSPOFF : 5; /*!< [20..16] 第二采样点偏移控制位（Secondary Sample Point
+ OFFset） */
+ uint32_t : 2;
+ __IOM uint32_t TDCEN : 1; /*!< [23..23] 发送延时补偿使能位（Transmitter Delay Compensation
+ Enable） */
+ uint32_t : 8;
+ } PRESC_b;
+ } ;
+
+ union {
+ __IOM uint32_t ERRST; /*!< (@ 0x00000018) CAN Error Status Register */
+
+ struct {
+ __IM uint32_t ALC : 5; /*!< [4..0] 仲裁丢失捕获（Arbitration Lost Capture） */
+ __IM uint32_t KOER : 3; /*!< [7..5] 错误类型标志位(Kind Of Error (Error code)) */
+ __IM uint32_t ECNT : 8; /*!< [15..8] 错误计数（number of errors） */
+ __IM uint32_t TECNT : 8; /*!< [23..16] 发送错误计数（number of errors during transmission） */
+ __IM uint32_t RECNT : 8; /*!< [31..24] 接收错误计数（number of errors during reception） */
+ } ERRST_b;
+ } ;
+
+ union {
+ __IOM uint32_t PRTST; /*!< (@ 0x0000001C) CAN Protocol Status Register */
+
+ struct {
+ __IM uint32_t RBSTS : 2; /*!< [1..0] CAN接收帧存储方式（CAN RX Buffer Status） */
+ __IM uint32_t NDSTS : 2; /*!< [3..2] CAN节点状态（CAN Node Status） */
+ __IM uint32_t FDSTS : 4; /*!< [7..4] CAN接收的FD控制信息（CAN RX FD Status） */
+ __IM uint32_t DKOER : 3; /*!< [10..8] 数据场错误类型标志位(Data Kind Of Error (Error
+ code)) */
+ uint32_t : 21;
+ } PRTST_b;
+ } ;
+
+ union {
+ __IOM uint32_t INTRLS; /*!< (@ 0x00000020) CAN Interrupt Line Select Register */
+
+ struct {
+ __IOM uint32_t AILS : 1; /*!< [0..0] 中止中断线选择位（Abort Interrupt Line Select） */
+ __IOM uint32_t EILS : 1; /*!< [1..1] 出错中断线选择位（Error Interrupt Line Select） */
+ __IOM uint32_t TSILS : 1; /*!< [2..2] STB传输中断线选择位（STB Transmission Interrupt
+ Line Select） */
+ __IOM uint32_t TPILS : 1; /*!< [3..3] PTB传输中断线选择位（PTB Transmission Interrupt
+ Line Select） */
+ __IOM uint32_t RAFILS : 1; /*!< [4..4] PRB将满中断线选择位（PRB Almost Full Interrupt
+ Line Select） */
+ __IOM uint32_t RFILS : 1; /*!< [5..5] PRB已满中断线选择位（PRB Full Interrupt Line
+ Select） */
+ __IOM uint32_t ROILS : 1; /*!< [6..6] PRB溢出中断线选择位（PRB Overrun Interrupt Line
+ Select） */
+ __IOM uint32_t RILS : 1; /*!< [7..7] PRB接收中断线选择位（PRB Receive Interrupt Line
+ Select） */
+ __IOM uint32_t BEILS : 1; /*!< [8..8] 总线错误中断线选择位（Bus Error Interrupt
+ Line Select） */
+ __IOM uint32_t ALILS : 1; /*!< [9..9] 仲裁丢失中断线选择位（Arbitration Lost Interrupt
+ Line Select） */
+ __IOM uint32_t EPILS : 1; /*!< [10..10] 被动错误中断线选择位（Error Passive Interrupt
+ Line Select） */
+ __IOM uint32_t ECILS : 1; /*!< [11..11] 错误计数中断线选择位（Error Counter Interrupt
+ Line Select） */
+ __IOM uint32_t ERILS : 1; /*!< [12..12] ETB接收中断线选择位（ETB Receive Interrupt
+ Line Select） */
+ __IOM uint32_t SRILS : 1; /*!< [13..13] SRB接收中断线选择位（SRB Receive Interrupt
+ Line Select） */
+ uint32_t : 4;
+ __IOM uint32_t EAFILS : 1; /*!< [18..18] ETB将满中断线选择位（ETB Almost Full Interrupt
+ Line Select） */
+ __IOM uint32_t EFILS : 1; /*!< [19..19] ETB已满中断线选择位（ETB Full Interrupt Line
+ Select） */
+ __IOM uint32_t EOILS : 1; /*!< [20..20] ETB溢出中断线选择位（ETB Overrun Interrupt
+ Line Select） */
+ __IOM uint32_t SAFILS : 1; /*!< [21..21] SRB将满中断线选择位（SRB Almost Full Interrupt
+ Line Select） */
+ __IOM uint32_t SFILS : 1; /*!< [22..22] SRB已满中断线选择位（SRB Full Interrupt Line
+ Select） */
+ __IOM uint32_t SOILS : 1; /*!< [23..23] SRB溢出中断线选择位（SRB Overrun Interrupt
+ Line Select） */
+ __IOM uint32_t CTOILS : 1; /*!< [24..24] 连续计数超时中断线选择位（Cont Timeout
+ Interrupt Line Select） */
+ __IOM uint32_t ETOILS : 1; /*!< [25..25] ETB接收超时中断线选择位（ETB Timeout Interrupt
+ Line Select） */
+ __IOM uint32_t STOILS : 1; /*!< [26..26] SRB接收超时中断线选择位（SRB Timeout Interrupt
+ Line Select） */
+ __IOM uint32_t RTOILS : 1; /*!< [27..27] PRB接收超时中断线选择位（PRB Timeout Interrupt
+ Line Select） */
+ __IOM uint32_t TSCILS : 1; /*!< [28..28] 时间戳计数中断线选择位（Timestamp Interrupt
+ Line Select） */
+ __IOM uint32_t PMILS : 1; /*!< [29..29] 优先级消息中断线选择位（Priority Message
+ Interrupt Line Select） */
+ __IOM uint32_t TAEILS : 1; /*!< [30..30] STB将空中断线选择位（STB Almost Empty Interrupt
+ Line Select） */
+ __IOM uint32_t TEILS : 1; /*!< [31..31] STB已空中断线选择位（STB Empty Interrupt Line
+ Select） */
+ } INTRLS_b;
+ } ;
+
+ union {
+ __IOM uint32_t GFCR; /*!< (@ 0x00000024) CAN Global Filter Control Register */
+
+ struct {
+ __IOM uint32_t SRBM : 1; /*!< [0..0] SRB工作模式（SRB Working Mode） */
+ __IOM uint32_t PRBM : 1; /*!< [1..1] PRB工作模式（PRB Working Mode） */
+ uint32_t : 4;
+ __IOM uint32_t ERFR : 1; /*!< [6..6] 拓展远程帧屏蔽（Extended Remote Frames Reject） */
+ __IOM uint32_t SRFR : 1; /*!< [7..7] 常规远程帧屏蔽（Standard Remote Frames Reject） */
+ uint32_t : 24;
+ } GFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t EMCR; /*!< (@ 0x00000028) CAN Extended Mask Control Register */
+
+ struct {
+ __IOM uint32_t EIDM : 29; /*!< [28..0] 拓展帧全局掩码（Extended ID Mask） */
+ uint32_t : 3;
+ } EMCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t PMST; /*!< (@ 0x0000002C) CAN Priority Message Status Register */
+
+ struct {
+ __IM uint32_t PMIS : 1; /*!< [0..0] 高优先级消息IDE状态（Priority Message IDE Status） */
+ __IM uint32_t PMBS : 2; /*!< [2..1] 高优先级消息存储状态（Priority Message Buffer
+ Status） */
+ uint32_t : 1;
+ __IM uint32_t PMAS : 4; /*!< [7..4] 高优先级消息验收状态（Priority Message Acceptance
+ Status） */
+ uint32_t : 24;
+ } PMST_b;
+ } ;
+
+ union {
+ __IOM uint32_t ACFEN; /*!< (@ 0x00000030) CAN ACF Enable */
+
+ struct {
+ __IOM uint32_t AE0 : 1; /*!< [0..0] 验收滤波器0启用（Acceptance filter 0 Enable） */
+ __IOM uint32_t AE1 : 1; /*!< [1..1] 验收滤波器1启用（Acceptance filter 1 Enable） */
+ __IOM uint32_t AE2 : 1; /*!< [2..2] 验收滤波器2启用（Acceptance filter 2 Enable） */
+ __IOM uint32_t AE3 : 1; /*!< [3..3] 验收滤波器3启用（Acceptance filter 3 Enable） */
+ __IOM uint32_t AE4 : 1; /*!< [4..4] 验收滤波器4启用（Acceptance filter 4 Enable） */
+ __IOM uint32_t AE5 : 1; /*!< [5..5] 验收滤波器5启用（Acceptance filter 5 Enable） */
+ __IOM uint32_t AE6 : 1; /*!< [6..6] 验收滤波器6启用（Acceptance filter 6 Enable） */
+ __IOM uint32_t AE7 : 1; /*!< [7..7] 验收滤波器7启用（Acceptance filter 7 Enable） */
+ __IOM uint32_t AE8 : 1; /*!< [8..8] 验收滤波器8启用（Acceptance filter 8 Enable） */
+ __IOM uint32_t AE9 : 1; /*!< [9..9] 验收滤波器9启用（Acceptance filter 9 Enable） */
+ __IOM uint32_t AE10 : 1; /*!< [10..10] 验收滤波器10启用（Acceptance filter 10 Enable） */
+ __IOM uint32_t AE11 : 1; /*!< [11..11] 验收滤波器11启用（Acceptance filter 11 Enable） */
+ __IOM uint32_t AE12 : 1; /*!< [12..12] 验收滤波器12启用（Acceptance filter 12 Enable） */
+ __IOM uint32_t AE13 : 1; /*!< [13..13] 验收滤波器13启用（Acceptance filter 13 Enable） */
+ __IOM uint32_t AE14 : 1; /*!< [14..14] 验收滤波器14启用（Acceptance filter 14 Enable） */
+ __IOM uint32_t AE15 : 1; /*!< [15..15] 验收滤波器15启用（Acceptance filter 15 Enable） */
+ uint32_t : 16;
+ } ACFEN_b;
+ } ;
+
+ union {
+ __IOM uint32_t ACFCTRL; /*!< (@ 0x00000034) CAN ACF Control Register */
+
+ struct {
+ __IOM uint32_t ACFADR : 4; /*!< [3..0] 验收滤波器的地址（acceptance filter address） */
+ uint32_t : 1;
+ __IOM uint32_t SELMASK : 1; /*!< [5..5] 验收码和屏蔽码的选择位（Select acceptance
+ MASK） */
+ uint32_t : 26;
+ } ACFCTRL_b;
+ } ;
+
+ union {
+ __IOM uint32_t ACF; /*!< (@ 0x00000038) CAN ACF Data Register */
+
+ struct {
+ __IOM uint32_t ACF_X : 29; /*!< [28..0] 当SELMASK=0： */
+ __IOM uint32_t AIDE : 1; /*!< [29..29] 验收掩码IDE位的控制位（Acceptance mask IDE
+ bit value） */
+ __IOM uint32_t AIDEE : 1; /*!< [30..30] 验收掩码IDE位的检查使能位（Acceptance mask
+ IDE bit check enable） */
+ uint32_t : 1;
+ } ACF_b;
+ } ;
+
+ union {
+ __IOM uint32_t ACFE; /*!< (@ 0x0000003C) CAN ACF Data Extended Register */
+
+ struct {
+ __IOM uint32_t ACF_C : 4; /*!< [3..0] CAN验收滤波器的控制信息（CAN Acceptance Control） */
+ __IOM uint32_t ACF_M : 4; /*!< [7..4] CAN验收滤波器的模式信息（CAN Acceptance Mode） */
+ uint32_t : 24;
+ } ACFE_b;
+ } ;
+
+ union {
+ __IOM uint32_t RBUFID; /*!< (@ 0x00000040) CAN RX Buffer Read Register(ID) */
+
+ struct {
+ __IM uint32_t RXD_ID : 32; /*!< [31..0] CAN接收的ID信息（CAN RX Identifier Data） */
+ } RBUFID_b;
+ } ;
+
+ union {
+ __IOM uint32_t RBUFCR; /*!< (@ 0x00000044) CAN RX Buffer Read Register(Control) */
+
+ struct {
+ __IM uint32_t RXD_DLC : 4; /*!< [3..0] CAN接收的数据量（CAN RX DATA Count） */
+ __IM uint32_t RXD_CR : 4; /*!< [7..4] CAN接收的控制信息（CAN RX Control Data） */
+ __IM uint32_t RXD_TS : 16; /*!< [23..8] CAN接收的时间戳（CAN RX Data Timestamp） */
+ __IM uint32_t RXD_ACF : 4; /*!< [27..24] CAN接收的验收滤波信息（CAN RX Acceptance
+ Data） */
+ uint32_t : 4;
+ } RBUFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t RBUFDT[16]; /*!< (@ 0x00000048) CAN RX Buffer Read Register(Data) */
+
+ struct {
+ __IM uint32_t RXD_BYTE0 : 8; /*!< [7..0] CAN接收的数据字节0（CAN RX Data Byte 0） */
+ __IM uint32_t RXD_BYTE1 : 8; /*!< [15..8] CAN接收的数据字节1（CAN RX Data Byte 1） */
+ __IM uint32_t RXD_BYTE2 : 8; /*!< [23..16] CAN接收的数据字节2（CAN RX Data Byte 2） */
+ __IM uint32_t RXD_BYTE3 : 8; /*!< [31..24] CAN接收的数据字节3（CAN RX Data Byte 3） */
+ } RBUFDT_b[16];
+ } ;
+
+ union {
+ __IOM uint32_t TBUFID; /*!< (@ 0x00000088) CAN TX Buffer Write Register(ID) */
+
+ struct {
+ __IOM uint32_t TXD_ID : 32; /*!< [31..0] CAN发送的ID信息（CAN TX Identifier Data） */
+ } TBUFID_b;
+ } ;
+
+ union {
+ __IOM uint32_t TBUFCR; /*!< (@ 0x0000008C) CAN TX Buffer Write Register(Control) */
+
+ struct {
+ __IOM uint32_t TXD_DLC : 4; /*!< [3..0] CAN发送的数据量（CAN TX DATA Count） */
+ __IOM uint32_t TXD_CR : 4; /*!< [7..4] CAN发送的控制信息（CAN TX Control Data） */
+ __IOM uint32_t TXD_MM : 8; /*!< [15..8] CAN发送的帧标记（CAN TX Data Message Marker） */
+ uint32_t : 15;
+ __IOM uint32_t TXD_ETB : 1; /*!< [31..31] CAN发送的信息是否写入ETB（CAN TX Event Buffer） */
+ } TBUFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TBUFDT[16]; /*!< (@ 0x00000090) CAN TX Buffer Write Register(Data) */
+
+ struct {
+ __IOM uint32_t TXD_BYTE0 : 8; /*!< [7..0] CAN发送的数据字节0（CAN TX Data Byte 0） */
+ __IOM uint32_t TXD_BYTE1 : 8; /*!< [15..8] CAN发送的数据字节1（CAN TX Data Byte 1） */
+ __IOM uint32_t TXD_BYTE2 : 8; /*!< [23..16] CAN发送的数据字节2（CAN TX Data Byte 2） */
+ __IOM uint32_t TXD_BYTE3 : 8; /*!< [31..24] CAN发送的数据字节3（CAN TX Data Byte 3） */
+ } TBUFDT_b[16];
+ } ;
+ __IM uint32_t RESERVED[26];
+
+ union {
+ __IOM uint32_t EBUFID; /*!< (@ 0x00000138) CAN ETB Buffer Read Register(ID) */
+
+ struct {
+ __IM uint32_t TXD_ID : 32; /*!< [31..0] CAN发送的ID信息（CAN TX Identifier Data） */
+ } EBUFID_b;
+ } ;
+
+ union {
+ __IOM uint32_t EBUFDT; /*!< (@ 0x0000013C) CAN ETB Buffer Read Register(Data) */
+
+ struct {
+ __IM uint32_t TXD_DLC : 4; /*!< [3..0] CAN发送的数据量（CAN TX DATA Count） */
+ __IM uint32_t TXD_CR : 4; /*!< [7..4] CAN发送的控制信息（CAN TX Control Data） */
+ __IM uint32_t TXD_TS : 16; /*!< [23..8] CAN发送的时间戳（CAN TX Data Timestamp） */
+ __IM uint32_t TXD_MM : 8; /*!< [31..24] CAN发送的帧标记（CAN TX Data Message Marker） */
+ } EBUFDT_b;
+ } ;
+
+ union {
+ __IOM uint32_t SBUFID; /*!< (@ 0x00000140) CAN SRB Buffer Read Register(ID) */
+
+ struct {
+ __IM uint32_t RXD_ID : 32; /*!< [31..0] CAN接收的ID信息（CAN RX Identifier Data） */
+ } SBUFID_b;
+ } ;
+
+ union {
+ __IOM uint32_t SBUFCR; /*!< (@ 0x00000144) CAN SRB Buffer Read Register(Control) */
+
+ struct {
+ __IM uint32_t RXD_DLC : 4; /*!< [3..0] CAN接收的数据量（CAN RX DATA Count） */
+ __IM uint32_t RXD_CR : 4; /*!< [7..4] CAN接收的控制信息（CAN RX Control Data） */
+ __IM uint32_t RXD_TS : 16; /*!< [23..8] CAN接收的时间戳（CAN RX Data Timestamp） */
+ __IM uint32_t RXD_ACF : 4; /*!< [27..24] CAN接收的验收滤波信息（CAN RX Acceptance
+ Data） */
+ uint32_t : 4;
+ } SBUFCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t SBUFDT[16]; /*!< (@ 0x00000148) CAN SRB Buffer Read Register(Data) */
+
+ struct {
+ __IM uint32_t RXD_BYTE0 : 8; /*!< [7..0] CAN接收的数据字节0（CAN RX Data Byte 0） */
+ __IM uint32_t RXD_BYTE1 : 8; /*!< [15..8] CAN接收的数据字节1（CAN RX Data Byte 1） */
+ __IM uint32_t RXD_BYTE2 : 8; /*!< [23..16] CAN接收的数据字节2（CAN RX Data Byte 2） */
+ __IM uint32_t RXD_BYTE3 : 8; /*!< [31..24] CAN接收的数据字节3（CAN RX Data Byte 3） */
+ } SBUFDT_b[16];
+ } ;
+ __IM uint32_t RESERVED1[158];
+
+ union {
+ __IOM uint32_t TSCR; /*!< (@ 0x00000400) Timestamp Counter Control Register */
+
+ struct {
+ uint32_t : 16;
+ __IOM uint32_t TSS : 4; /*!< [19..16] 时间戳选择（Timestamp Select） */
+ __IOM uint32_t TSP : 4; /*!< [23..20] 时间戳预分频（Timestamp Prescaler） */
+ uint32_t : 8;
+ } TSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TSC; /*!< (@ 0x00000404) Timestamp Counter Value Register */
+
+ struct {
+ __IM uint32_t TSC : 16; /*!< [15..0] 时间戳计数（Timestamp Counter） */
+ uint32_t : 16;
+ } TSC_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t RTOP; /*!< (@ 0x00000410) PRB Timeout Counter Period Register */
+
+ struct {
+ __IOM uint32_t RTOP : 16; /*!< [15..0] PRB超时功能周期（PRB Timeout Period） */
+ uint32_t : 8;
+ __IOM uint32_t RTOE : 1; /*!< [24..24] PRB超时功能使能（PRB Timeout Enable） */
+ uint32_t : 7;
+ } RTOP_b;
+ } ;
+
+ union {
+ __IOM uint32_t RTOC; /*!< (@ 0x00000414) PRB Timeout Counter Value Register */
+
+ struct {
+ __IM uint32_t RTOC : 16; /*!< [15..0] PRB超时功能计数（PRB Timeout Counter） */
+ uint32_t : 16;
+ } RTOC_b;
+ } ;
+ __IM uint32_t RESERVED3[2];
+
+ union {
+ __IOM uint32_t STOP; /*!< (@ 0x00000420) SRB Timeout Counter Period Register */
+
+ struct {
+ __IOM uint32_t STOP : 16; /*!< [15..0] SRB超时功能周期（SRB Timeout Period） */
+ uint32_t : 8;
+ __IOM uint32_t STOE : 1; /*!< [24..24] SRB超时功能使能（SRB Timeout Enable） */
+ uint32_t : 7;
+ } STOP_b;
+ } ;
+
+ union {
+ __IOM uint32_t STOC; /*!< (@ 0x00000424) SRB Timeout Counter Value Register */
+
+ struct {
+ __IM uint32_t STOC : 16; /*!< [15..0] SRB超时功能计数（SRB Timeout Counter） */
+ uint32_t : 16;
+ } STOC_b;
+ } ;
+ __IM uint32_t RESERVED4[2];
+
+ union {
+ __IOM uint32_t ETOP; /*!< (@ 0x00000430) ETB Timeout Counter Period Register */
+
+ struct {
+ __IOM uint32_t ETOP : 16; /*!< [15..0] ETB超时功能周期（ETB Timeout Period） */
+ uint32_t : 8;
+ __IOM uint32_t ETOE : 1; /*!< [24..24] ETB超时功能使能（ETB Timeout Enable） */
+ uint32_t : 7;
+ } ETOP_b;
+ } ;
+
+ union {
+ __IOM uint32_t ETOC; /*!< (@ 0x00000434) ETB Timeout Counter Value Register */
+
+ struct {
+ __IM uint32_t ETOC : 16; /*!< [15..0] ETB超时功能计数（ETB Timeout Counter） */
+ uint32_t : 16;
+ } ETOC_b;
+ } ;
+ __IM uint32_t RESERVED5[2];
+
+ union {
+ __IOM uint32_t CTOP; /*!< (@ 0x00000440) Continuous Timeout Counter Period Register */
+
+ struct {
+ __IOM uint32_t CTOP : 16; /*!< [15..0] 连续超时功能周期（Cont Timeout Period） */
+ uint32_t : 8;
+ __IOM uint32_t CTOE : 1; /*!< [24..24] 连续超时功能使能（Cont Timeout Enable） */
+ uint32_t : 7;
+ } CTOP_b;
+ } ;
+
+ union {
+ __IOM uint32_t CTOC; /*!< (@ 0x00000444) Continuous Timeout Counter Value Register */
+
+ struct {
+ __IM uint32_t CTOC : 16; /*!< [15..0] 连续超时功能计数（Cont Timeout Counter） */
+ uint32_t : 16;
+ } CTOC_b;
+ } ;
+} CAN1_Type; /*!< Size = 1096 (0x448) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR7 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR7 (TMR7)
+ */
+
+typedef struct { /*!< (@ 0x40008000) TMR7 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 计数器使能位(Counter Enable) */
+ __IOM uint32_t UDIS : 1; /*!< [1..1] 更新禁止位(Update Disable) */
+ __IOM uint32_t URS : 1; /*!< [2..2] 更新事件源(Update Request Source) */
+ __IOM uint32_t OPM : 1; /*!< [3..3] 单脉冲模式(One Pulse Mode) */
+ uint32_t : 3;
+ __IOM uint32_t ARE : 1; /*!< [7..7] 自动重载使能(AutoReload Enable) */
+ uint32_t : 24;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+
+ struct {
+ __IOM uint32_t MMS : 2; /*!< [1..0] 主模式选择(Master Mode Selection) */
+ uint32_t : 30;
+ } CR1_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+
+ struct {
+ uint32_t : 8;
+ __IOM uint32_t UIE : 1; /*!< [8..8] 更新中断使能(Update Interrupt Enable) */
+ __IOM uint32_t OVIE : 1; /*!< [9..9] 计数上溢中断使能(Overflow Interrupt Enable) */
+ uint32_t : 22;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+
+ struct {
+ uint32_t : 8;
+ __IOM uint32_t UIF : 1; /*!< [8..8] 更新中断标志(Update Interrupt Flag) */
+ __IOM uint32_t OVIF : 1; /*!< [9..9] 计数器上溢中断标志位(Counter Overflow Interrupt
+ Flag) */
+ uint32_t : 22;
+ } SR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+
+ struct {
+ __IOM uint32_t UG : 1; /*!< [0..0] 更新事件生成(Update Generation)： */
+ uint32_t : 31;
+ } UGR_b;
+ } ;
+ __IM uint32_t RESERVED1[5];
+
+ union {
+ __IOM uint32_t TCR; /*!< (@ 0x0000002C) TMRx Trigger Control Register */
+
+ struct {
+ __IOM uint32_t TOW : 4; /*!< [3..0] TRGO脉冲宽度控制(Trigger Output Width) */
+ uint32_t : 28;
+ } TCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+
+ struct {
+ __IOM uint32_t CPV : 16; /*!< [15..0] 计数周期值(Counter Period Value) */
+ uint32_t : 16;
+ } CPR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 16; /*!< [15..0] 预分频寄存器（Prescaler Value) */
+ uint32_t : 16;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] 定时器计数值(Counter Value) */
+ uint32_t : 16;
+ } CNTR_b;
+ } ;
+} TMR7_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR8 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR8 (TMR8)
+ */
+
+typedef struct { /*!< (@ 0x40009000) TMR8 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 计数器使能位(Counter Enable) */
+ __IOM uint32_t UDIS : 1; /*!< [1..1] 更新禁止位(Update Disable) */
+ __IOM uint32_t URS : 1; /*!< [2..2] 更新事件源(Update Request Source) */
+ __IOM uint32_t OPM : 1; /*!< [3..3] 单脉冲模式(One Pulse Mode) */
+ uint32_t : 3;
+ __IOM uint32_t ARE : 1; /*!< [7..7] 自动重载使能(AutoReload Enable) */
+ uint32_t : 24;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+
+ struct {
+ __IOM uint32_t MMS : 2; /*!< [1..0] 主模式选择(Master Mode Selection) */
+ uint32_t : 30;
+ } CR1_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+
+ struct {
+ uint32_t : 8;
+ __IOM uint32_t UIE : 1; /*!< [8..8] 更新中断使能(Update Interrupt Enable) */
+ __IOM uint32_t OVIE : 1; /*!< [9..9] 计数上溢中断使能(Overflow Interrupt Enable) */
+ uint32_t : 22;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+
+ struct {
+ uint32_t : 8;
+ __IOM uint32_t UIF : 1; /*!< [8..8] 更新中断标志(Update Interrupt Flag) */
+ __IOM uint32_t OVIF : 1; /*!< [9..9] 计数器上溢中断标志位(Counter Overflow Interrupt
+ Flag) */
+ uint32_t : 22;
+ } SR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+
+ struct {
+ __IOM uint32_t UG : 1; /*!< [0..0] 更新事件生成(Update Generation)： */
+ uint32_t : 31;
+ } UGR_b;
+ } ;
+ __IM uint32_t RESERVED1[5];
+
+ union {
+ __IOM uint32_t TCR; /*!< (@ 0x0000002C) TMRx Trigger Control Register */
+
+ struct {
+ __IOM uint32_t TOW : 4; /*!< [3..0] TRGO脉冲宽度控制(Trigger Output Width) */
+ uint32_t : 28;
+ } TCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+
+ struct {
+ __IOM uint32_t CPV : 16; /*!< [15..0] 计数周期值(Counter Period Value) */
+ uint32_t : 16;
+ } CPR_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 16; /*!< [15..0] 预分频寄存器（Prescaler Value) */
+ uint32_t : 16;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] 定时器计数值(Counter Value) */
+ uint32_t : 16;
+ } CNTR_b;
+ } ;
+} TMR8_Type; /*!< Size = 64 (0x40) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR9 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR9 (TMR9)
+ */
+
+typedef struct { /*!< (@ 0x40030000) TMR9 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 计数器使能位(Counter Enable): */
+ __IOM uint32_t UDIS : 1; /*!< [1..1] 更新禁止位(Update Disable) */
+ __IOM uint32_t URS : 1; /*!< [2..2] 更新事件源(Update Request Source) */
+ __IOM uint32_t OPM : 1; /*!< [3..3] 单脉冲模式(One Pulse Mode) */
+ __IOM uint32_t DIR : 1; /*!< [4..4] 计数方向(Counter Direction) */
+ __IOM uint32_t CMS : 2; /*!< [6..5] 中心对齐模式(Center-Aligned Mode Selection) */
+ __IOM uint32_t ARE : 1; /*!< [7..7] 自动重载使能(AutoReload Enable) */
+ __IOM uint32_t DCD : 2; /*!< [9..8] 时钟分频(Clock Division) */
+ __IOM uint32_t TI0S : 1; /*!< [10..10] TI0输入选择(TI0 Input Selection) */
+ uint32_t : 21;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+
+ struct {
+ __IOM uint32_t MMS : 3; /*!< [2..0] 主模式选择(Master Mode Selection): */
+ uint32_t : 5;
+ __IOM uint32_t OIS0 : 1; /*!< [8..8] CH0空闲状态输出电平(CH0 Output Idle-State): */
+ __IOM uint32_t OIS0N : 1; /*!< [9..9] CH0N空闲状态输出电平(CH0N Output Idle-State): */
+ __IOM uint32_t OIS1 : 1; /*!< [10..10] CH1空闲状态输出电平(CH1 Output Idle-State): */
+ __IOM uint32_t OIS1N : 1; /*!< [11..11] CH1N空闲状态输出电平(CH1N Output Idle-State): */
+ __IOM uint32_t OIS2 : 1; /*!< [12..12] CH2空闲状态输出电平(CH2 Output Idle-State): */
+ __IOM uint32_t OIS2N : 1; /*!< [13..13] CH2N空闲状态输出电平(CH2N Output Idle-State): */
+ __IOM uint32_t OIS3 : 1; /*!< [14..14] CH3空闲状态输出电平(CH3 Output Idle-State): */
+ __IOM uint32_t OIS3N : 1; /*!< [15..15] CH3N空闲状态输出电平(CH3N Output Idle-State): */
+ uint32_t : 16;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+
+ struct {
+ __IOM uint32_t SMS : 4; /*!< [3..0] 从模式选择(Slave Mode Selection): */
+ uint32_t : 3;
+ __IOM uint32_t FE : 1; /*!< [7..7] 主从快速同步使能(Master/Slave Fast-Sync Enable) */
+ __IOM uint32_t TS : 5; /*!< [12..8] 触发选择(Trigger Selection) */
+ uint32_t : 3;
+ __IOM uint32_t EFS : 4; /*!< [19..16] ETR滤波选择(ETR Filter Selection) */
+ __IOM uint32_t EMS : 2; /*!< [21..20] ETR边沿模式选择(ETR Edge-Mode Selection) */
+ __IOM uint32_t EE : 1; /*!< [22..22] ETR控制模式选择(ETR Mode Selection) */
+ uint32_t : 1;
+ __IOM uint32_t ETS : 4; /*!< [27..24] ETR输入源选择(ETR Input Shource Selection) */
+ uint32_t : 4;
+ } SCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t C0MIE : 1; /*!< [0..0] CH0比较中断使能(CH0 Capture/Compare Interrupt Enable): */
+ __IOM uint32_t C0OIE : 1; /*!< [1..1] CH0重复捕获中断使能(CH0 OverCapture Interrupt
+ Enable): */
+ __IOM uint32_t C1MIE : 1; /*!< [2..2] CH1比较中断使能(CH1 Capture/Compare Interrupt Enable): */
+ __IOM uint32_t C1OIE : 1; /*!< [3..3] CH1重复捕获中断使能(CH1 OverCapture Interrupt
+ Enable): */
+ __IOM uint32_t C2MIE : 1; /*!< [4..4] CH2比较中断使能(CH2 Capture/Compare Interrupt Enable): */
+ __IOM uint32_t C2OIE : 1; /*!< [5..5] CH2重复捕获中断使能(CH2 OverCapture Interrupt
+ Enable): */
+ __IOM uint32_t C3MIE : 1; /*!< [6..6] CH3比较中断使能(CH3 Capture/Compare Interrupt Enable): */
+ __IOM uint32_t C3OIE : 1; /*!< [7..7] CH3重复捕获中断使能(CH3 OverCapture Interrupt
+ Enable): */
+ __IOM uint32_t UIE : 1; /*!< [8..8] 更新中断使能(Update Interrupt Enable) */
+ __IOM uint32_t OVIE : 1; /*!< [9..9] 计数上溢中断使能(Overflow Interrupt Enable) */
+ __IOM uint32_t TIE : 1; /*!< [10..10] 触发中断使能(Trigger Interrupt Enable) */
+ __IOM uint32_t BIE : 1; /*!< [11..11] 断路中断使能(Break Interrupt Enable) */
+ uint32_t : 20;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+
+ struct {
+ __IOM uint32_t CC0MIF : 1; /*!< [0..0] CC0比较成功中断标志位(CC0 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC0OIF : 1; /*!< [1..1] CC0重复捕获成功中断标志位(CC0 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC1MIF : 1; /*!< [2..2] CC1比较成功中断标志位(CC1 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC1OIF : 1; /*!< [3..3] CC1重复捕获成功中断标志位(CC1 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC2MIF : 1; /*!< [4..4] CC2比较成功中断标志位(CC2 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC2OIF : 1; /*!< [5..5] CC2重复捕获成功中断标志位(CC2 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC3MIF : 1; /*!< [6..6] CC3比较成功中断标志位(CC3 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC3OIF : 1; /*!< [7..7] CC3重复捕获成功中断标志位(CC3 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t UIF : 1; /*!< [8..8] 更新中断标志(Update Interrupt Flag) */
+ __IOM uint32_t OVIF : 1; /*!< [9..9] 计数器上溢中断标志位(Counter Overflow Interrupt
+ Flag) */
+ __IOM uint32_t TIF : 1; /*!< [10..10] 触发中断标志(Trigger Interrupt Flag) */
+ __IOM uint32_t B0IF : 1; /*!< [11..11] 断路中断标志位(Break0 Interrupt Flag) */
+ __IOM uint32_t SBIF : 1; /*!< [12..12] 系统断路中断标志位(System Fault Break Interrupt
+ Flag) */
+ __IOM uint32_t B1IF : 1; /*!< [13..13] 断路中断标志位(Break1 Interrupt Flag) */
+ uint32_t : 18;
+ } SR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+
+ struct {
+ __IOM uint32_t UG : 1; /*!< [0..0] 更新事件生成(Update Generation) */
+ __IOM uint32_t TG : 1; /*!< [1..1] 触发事件生成(Trigger Generation) */
+ __IOM uint32_t B0G : 1; /*!< [2..2] 断路0事件生成(Break0 Generation) */
+ __IOM uint32_t B1G : 1; /*!< [3..3] 断路1事件生成(Break1 Generation) */
+ __IOM uint32_t CC0UG : 1; /*!< [4..4] CC0捕获/比较更新事件生成(CC0 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC1UG : 1; /*!< [5..5] CC1捕获/比较更新事件生成(CC1 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC2UG : 1; /*!< [6..6] CC2捕获/比较更新事件生成(CC2 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC3UG : 1; /*!< [7..7] CC3捕获/比较更新事件生成(CC3 Capture/Compare
+ Update Generation) */
+ uint32_t : 24;
+ } UGR_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+
+ struct {
+ __IOM uint32_t CC0S : 2; /*!< [1..0] CC0捕获/比较方向选择(CC0 Capture Compare Selection) */
+ __IOM uint32_t CC0PE : 2; /*!< [3..2] CC0输入捕获分频/比较自动加载使能(CC0 Compare
+ Auto-Realod Enable) */
+ __IOM uint32_t OC0M : 4; /*!< [7..4] CC0输入滤波/输出比较模式选择(CC0 Input Filter/Output
+ Compare Mode) */
+ __IOM uint32_t CC1S : 2; /*!< [9..8] CC1捕获/比较方向选择(CC1 Capture Compare Selection) */
+ __IOM uint32_t CC1PE : 2; /*!< [11..10] CC1输入捕获分频/比较自动加载使能(CC1
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC1M : 4; /*!< [15..12] CC1输入滤波/输出比较模式选择(CC1 Input
+ Filter/Output Compare Mode) */
+ __IOM uint32_t CC2S : 2; /*!< [17..16] CC2捕获/比较方向选择(CC2 Capture Compare Selection) */
+ __IOM uint32_t CC2PE : 2; /*!< [19..18] CC2输入捕获分频/比较自动加载使能(CC2
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC2M : 4; /*!< [23..20] CC2输入滤波/输出比较模式选择(CC2 Input
+ Filter/Output Compare Mode) */
+ __IOM uint32_t CC3S : 2; /*!< [25..24] CC3捕获/比较方向选择(CC3 Capture Compare Selection) */
+ __IOM uint32_t CC3PE : 2; /*!< [27..26] CC3输入捕获分频/比较自动加载使能(CC3
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC3M : 4; /*!< [31..28] CC3输入滤波/输出比较模式选择(CC3 Input
+ Filter/Output Compare Mode) */
+ } CCMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+
+ struct {
+ __IOM uint32_t CC0E : 1; /*!< [0..0] CC0捕获/比较通道使能(CC0 Capture/Compare Enable) */
+ __IOM uint32_t CC0NE : 1; /*!< [1..1] CC0N捕获/比较互补通道使能(CC0N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC0P : 2; /*!< [3..2] CC0捕获/比较极性选择(CC0 Compare/Capture Polarity) */
+ __IOM uint32_t CC1E : 1; /*!< [4..4] CC1捕获/比较通道使能(CC1 Capture/Compare Enable) */
+ __IOM uint32_t CC1NE : 1; /*!< [5..5] CC1N捕获/比较互补通道使能(CC1N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC1P : 2; /*!< [7..6] CC1捕获/比较极性选择(CC1 Compare/Capture Polarity) */
+ __IOM uint32_t CC2E : 1; /*!< [8..8] CC2捕获/比较通道使能(CC2 Capture/Compare Enable) */
+ __IOM uint32_t CC2NE : 1; /*!< [9..9] CC2N捕获/比较互补通道使能(CC2N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC2P : 2; /*!< [11..10] CC2捕获/比较极性选择(CC2 Compare/Capture Polarity) */
+ __IOM uint32_t CC3E : 1; /*!< [12..12] CC3捕获/比较通道使能(CC3 Capture/Compare Enable) */
+ __IOM uint32_t CC3NE : 1; /*!< [13..13] CC3N捕获/比较互补通道使能(CC3N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC3P : 2; /*!< [15..14] CC3捕获/比较极性选择(CC3 Compare/Capture Polarity) */
+ uint32_t : 16;
+ } CCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DCR; /*!< (@ 0x00000028) TMRx Dead-Time Contorl Register */
+
+ struct {
+ __IOM uint32_t DTG : 8; /*!< [7..0] 配置死区时间选择(Dead-Time Generator Setup) */
+ __IOM uint32_t OSSI : 1; /*!< [8..8] 空闲模式下关闭状态选择(Off-State Selection
+ for Idle-Mode) */
+ __IOM uint32_t OSSR : 1; /*!< [9..9] 运行模式下关闭状态选择(Off-State Selection
+ for Run-Mode) */
+ __IOM uint32_t AOE : 1; /*!< [10..10] 自动输出使能(Automatic Output Enable) */
+ __IOM uint32_t MOE : 1; /*!< [11..11] 主路输出使能(Main Output Enable) */
+ __IOM uint32_t BK0E : 1; /*!< [12..12] 断路控制使能(Break0 Enable) */
+ __IOM uint32_t BK0P : 1; /*!< [13..13] 断路输入极性(Break0 Polarity) */
+ __IOM uint32_t BK0F : 8; /*!< [21..14] 断路滤波器(Break0 Filter) */
+ __IOM uint32_t BK1E : 1; /*!< [22..22] 断路控制使能(Break1 Enable) */
+ __IOM uint32_t BK1P : 1; /*!< [23..23] 断路输入极性(Break1 Polarity) */
+ __IOM uint32_t BK1F : 8; /*!< [31..24] 断路滤波器(Break1 Filter) */
+ } DCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+
+ struct {
+ __IOM uint32_t TOW : 4; /*!< [3..0] TRGO脉冲宽度控制(Trigger Output Width) */
+ __IOM uint32_t TCW : 4; /*!< [7..4] TRGCC脉冲宽度控制(Trigger Compare/Caputre Width) */
+ __IOM uint32_t TC0E : 1; /*!< [8..8] TRGO CH0输出使能(Trigger CH0 Enable) */
+ __IOM uint32_t TC1E : 1; /*!< [9..9] TRGO CH1输出使能(Trigger CH1 Enable) */
+ __IOM uint32_t TC2E : 1; /*!< [10..10] TRGO CH2输出使能(Trigger CH2 Enable) */
+ __IOM uint32_t TC3E : 1; /*!< [11..11] TRGO CH3输出使能(Trigger CH3 Enable) */
+ uint32_t : 20;
+ } TTCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+
+ struct {
+ __IOM uint32_t CPV : 16; /*!< [15..0] 计数周期值(Counter Period Value) */
+ uint32_t : 16;
+ } CPR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 16; /*!< [15..0] 预分频寄存器（Prescaler Value) */
+ uint32_t : 16;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] 定时器计数值(Counter Value) */
+ uint32_t : 16;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CRR; /*!< (@ 0x00000040) TMRx Counter Repeat Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] 重复计数值(Counter Repeat Value) */
+ uint32_t : 24;
+ } CRR_b;
+ } ;
+ __IM uint32_t RESERVED2[3];
+
+ union {
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+
+ struct {
+ __IOM uint32_t CC0V : 16; /*!< [15..0] CC0捕获/比较值(CC0 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+
+ struct {
+ __IOM uint32_t CC1V : 16; /*!< [15..0] CC1捕获/比较值(CC1 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC2R; /*!< (@ 0x00000058) TMRx Capture Compare Register2 */
+
+ struct {
+ __IOM uint32_t CC2V : 16; /*!< [15..0] CC2捕获/比较值(CC2 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC3R; /*!< (@ 0x0000005C) TMRx Capture Compare Register3 */
+
+ struct {
+ __IOM uint32_t CC3V : 16; /*!< [15..0] CC3捕获/比较值(CC3 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+
+ struct {
+ __IOM uint32_t C0TIS : 4; /*!< [3..0] CH0触发输入选择(CH0 Trigger Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C1TIS : 4; /*!< [11..8] CH1触发输入选择(CH1 Capture Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C2TIS : 4; /*!< [19..16] CH2触发输入选择(CH2 Capture Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C3TIS : 4; /*!< [27..24] CH3触发输入选择(CH3 Capture Input Selection) */
+ uint32_t : 4;
+ } CIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BPR; /*!< (@ 0x00000064) TMRx Break Polarity Register */
+
+ struct {
+ __IOM uint32_t B0POL : 16; /*!< [15..0] Break0输入极性选择(Break0 Input Polarity Selection) */
+ __IOM uint32_t B1POL : 16; /*!< [31..16] Break1输入极性选择(Break1 Input Polarity Selection) */
+ } BPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BER; /*!< (@ 0x00000068) TMRx Break Enable Register */
+
+ struct {
+ __IOM uint32_t B0IEN : 16; /*!< [15..0] Break0输入使能控制(Break0 Input Enable) */
+ __IOM uint32_t B1IEN : 16; /*!< [31..16] Break1输入使能控制(Break1 Input Enable) */
+ } BER_b;
+ } ;
+} TMR9_Type; /*!< Size = 108 (0x6c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR10 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR10 (TMR10)
+ */
+
+typedef struct { /*!< (@ 0x40031000) TMR10 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 计数器使能位(Counter Enable): */
+ __IOM uint32_t UDIS : 1; /*!< [1..1] 更新禁止位(Update Disable) */
+ __IOM uint32_t URS : 1; /*!< [2..2] 更新事件源(Update Request Source) */
+ __IOM uint32_t OPM : 1; /*!< [3..3] 单脉冲模式(One Pulse Mode) */
+ __IOM uint32_t DIR : 1; /*!< [4..4] 计数方向(Counter Direction) */
+ __IOM uint32_t CMS : 2; /*!< [6..5] 中心对齐模式(Center-Aligned Mode Selection) */
+ __IOM uint32_t ARE : 1; /*!< [7..7] 自动重载使能(AutoReload Enable) */
+ __IOM uint32_t DCD : 2; /*!< [9..8] 时钟分频(Clock Division) */
+ __IOM uint32_t TI0S : 1; /*!< [10..10] TI0输入选择(TI0 Input Selection) */
+ uint32_t : 21;
+ } CR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CR1; /*!< (@ 0x00000004) TMRx Control Register1 */
+
+ struct {
+ __IOM uint32_t MMS : 3; /*!< [2..0] 主模式选择(Master Mode Selection): */
+ uint32_t : 5;
+ __IOM uint32_t OIS0 : 1; /*!< [8..8] CH0空闲状态输出电平(CH0 Output Idle-State): */
+ __IOM uint32_t OIS0N : 1; /*!< [9..9] CH0N空闲状态输出电平(CH0N Output Idle-State): */
+ __IOM uint32_t OIS1 : 1; /*!< [10..10] CH1空闲状态输出电平(CH1 Output Idle-State): */
+ __IOM uint32_t OIS1N : 1; /*!< [11..11] CH1N空闲状态输出电平(CH1N Output Idle-State): */
+ __IOM uint32_t OIS2 : 1; /*!< [12..12] CH2空闲状态输出电平(CH2 Output Idle-State): */
+ __IOM uint32_t OIS2N : 1; /*!< [13..13] CH2N空闲状态输出电平(CH2N Output Idle-State): */
+ __IOM uint32_t OIS3 : 1; /*!< [14..14] CH3空闲状态输出电平(CH3 Output Idle-State): */
+ __IOM uint32_t OIS3N : 1; /*!< [15..15] CH3N空闲状态输出电平(CH3N Output Idle-State): */
+ uint32_t : 16;
+ } CR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+
+ struct {
+ __IOM uint32_t SMS : 4; /*!< [3..0] 从模式选择(Slave Mode Selection): */
+ uint32_t : 3;
+ __IOM uint32_t FE : 1; /*!< [7..7] 主从快速同步使能(Master/Slave Fast-Sync Enable) */
+ __IOM uint32_t TS : 5; /*!< [12..8] 触发选择(Trigger Selection) */
+ uint32_t : 3;
+ __IOM uint32_t EFS : 4; /*!< [19..16] ETR滤波选择(ETR Filter Selection) */
+ __IOM uint32_t EMS : 2; /*!< [21..20] ETR边沿模式选择(ETR Edge-Mode Selection) */
+ __IOM uint32_t EE : 1; /*!< [22..22] ETR控制模式选择(ETR Mode Selection) */
+ uint32_t : 1;
+ __IOM uint32_t ETS : 4; /*!< [27..24] ETR输入源选择(ETR Input Shource Selection) */
+ uint32_t : 4;
+ } SCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t C0MIE : 1; /*!< [0..0] CH0比较中断使能(CH0 Capture/Compare Interrupt Enable): */
+ __IOM uint32_t C0OIE : 1; /*!< [1..1] CH0重复捕获中断使能(CH0 OverCapture Interrupt
+ Enable): */
+ __IOM uint32_t C1MIE : 1; /*!< [2..2] CH1比较中断使能(CH1 Capture/Compare Interrupt Enable): */
+ __IOM uint32_t C1OIE : 1; /*!< [3..3] CH1重复捕获中断使能(CH1 OverCapture Interrupt
+ Enable): */
+ __IOM uint32_t C2MIE : 1; /*!< [4..4] CH2比较中断使能(CH2 Capture/Compare Interrupt Enable): */
+ __IOM uint32_t C2OIE : 1; /*!< [5..5] CH2重复捕获中断使能(CH2 OverCapture Interrupt
+ Enable): */
+ __IOM uint32_t C3MIE : 1; /*!< [6..6] CH3比较中断使能(CH3 Capture/Compare Interrupt Enable): */
+ __IOM uint32_t C3OIE : 1; /*!< [7..7] CH3重复捕获中断使能(CH3 OverCapture Interrupt
+ Enable): */
+ __IOM uint32_t UIE : 1; /*!< [8..8] 更新中断使能(Update Interrupt Enable) */
+ __IOM uint32_t OVIE : 1; /*!< [9..9] 计数上溢中断使能(Overflow Interrupt Enable) */
+ __IOM uint32_t TIE : 1; /*!< [10..10] 触发中断使能(Trigger Interrupt Enable) */
+ __IOM uint32_t BIE : 1; /*!< [11..11] 断路中断使能(Break Interrupt Enable) */
+ uint32_t : 20;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+
+ struct {
+ __IOM uint32_t CC0MIF : 1; /*!< [0..0] CC0比较成功中断标志位(CC0 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC0OIF : 1; /*!< [1..1] CC0重复捕获成功中断标志位(CC0 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC1MIF : 1; /*!< [2..2] CC1比较成功中断标志位(CC1 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC1OIF : 1; /*!< [3..3] CC1重复捕获成功中断标志位(CC1 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC2MIF : 1; /*!< [4..4] CC2比较成功中断标志位(CC2 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC2OIF : 1; /*!< [5..5] CC2重复捕获成功中断标志位(CC2 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t CC3MIF : 1; /*!< [6..6] CC3比较成功中断标志位(CC3 Capture/Compare Interrupt
+ Flag) */
+ __IOM uint32_t CC3OIF : 1; /*!< [7..7] CC3重复捕获成功中断标志位(CC3 OverCapture
+ Interrupt Flag) */
+ __IOM uint32_t UIF : 1; /*!< [8..8] 更新中断标志(Update Interrupt Flag) */
+ __IOM uint32_t OVIF : 1; /*!< [9..9] 计数器上溢中断标志位(Counter Overflow Interrupt
+ Flag) */
+ __IOM uint32_t TIF : 1; /*!< [10..10] 触发中断标志(Trigger Interrupt Flag) */
+ __IOM uint32_t B0IF : 1; /*!< [11..11] 断路中断标志位(Break0 Interrupt Flag) */
+ __IOM uint32_t SBIF : 1; /*!< [12..12] 系统断路中断标志位(System Fault Break Interrupt
+ Flag) */
+ __IOM uint32_t B1IF : 1; /*!< [13..13] 断路中断标志位(Break1 Interrupt Flag) */
+ uint32_t : 18;
+ } SR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+
+ struct {
+ __IOM uint32_t UG : 1; /*!< [0..0] 更新事件生成(Update Generation) */
+ __IOM uint32_t TG : 1; /*!< [1..1] 触发事件生成(Trigger Generation) */
+ __IOM uint32_t B0G : 1; /*!< [2..2] 断路0事件生成(Break0 Generation) */
+ __IOM uint32_t B1G : 1; /*!< [3..3] 断路1事件生成(Break1 Generation) */
+ __IOM uint32_t CC0UG : 1; /*!< [4..4] CC0捕获/比较更新事件生成(CC0 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC1UG : 1; /*!< [5..5] CC1捕获/比较更新事件生成(CC1 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC2UG : 1; /*!< [6..6] CC2捕获/比较更新事件生成(CC2 Capture/Compare
+ Update Generation) */
+ __IOM uint32_t CC3UG : 1; /*!< [7..7] CC3捕获/比较更新事件生成(CC3 Capture/Compare
+ Update Generation) */
+ uint32_t : 24;
+ } UGR_b;
+ } ;
+ __IM uint32_t RESERVED[2];
+
+ union {
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Capture Compare Mode Register */
+
+ struct {
+ __IOM uint32_t CC0S : 2; /*!< [1..0] CC0捕获/比较方向选择(CC0 Capture Compare Selection) */
+ __IOM uint32_t CC0PE : 2; /*!< [3..2] CC0输入捕获分频/比较自动加载使能(CC0 Compare
+ Auto-Realod Enable) */
+ __IOM uint32_t OC0M : 4; /*!< [7..4] CC0输入滤波/输出比较模式选择(CC0 Input Filter/Output
+ Compare Mode) */
+ __IOM uint32_t CC1S : 2; /*!< [9..8] CC1捕获/比较方向选择(CC1 Capture Compare Selection) */
+ __IOM uint32_t CC1PE : 2; /*!< [11..10] CC1输入捕获分频/比较自动加载使能(CC1
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC1M : 4; /*!< [15..12] CC1输入滤波/输出比较模式选择(CC1 Input
+ Filter/Output Compare Mode) */
+ __IOM uint32_t CC2S : 2; /*!< [17..16] CC2捕获/比较方向选择(CC2 Capture Compare Selection) */
+ __IOM uint32_t CC2PE : 2; /*!< [19..18] CC2输入捕获分频/比较自动加载使能(CC2
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC2M : 4; /*!< [23..20] CC2输入滤波/输出比较模式选择(CC2 Input
+ Filter/Output Compare Mode) */
+ __IOM uint32_t CC3S : 2; /*!< [25..24] CC3捕获/比较方向选择(CC3 Capture Compare Selection) */
+ __IOM uint32_t CC3PE : 2; /*!< [27..26] CC3输入捕获分频/比较自动加载使能(CC3
+ Compare Auto-Realod Enable) */
+ __IOM uint32_t OC3M : 4; /*!< [31..28] CC3输入滤波/输出比较模式选择(CC3 Input
+ Filter/Output Compare Mode) */
+ } CCMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Capture Compare Enable Register */
+
+ struct {
+ __IOM uint32_t CC0E : 1; /*!< [0..0] CC0捕获/比较通道使能(CC0 Capture/Compare Enable) */
+ __IOM uint32_t CC0NE : 1; /*!< [1..1] CC0N捕获/比较互补通道使能(CC0N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC0P : 2; /*!< [3..2] CC0捕获/比较极性选择(CC0 Compare/Capture Polarity) */
+ __IOM uint32_t CC1E : 1; /*!< [4..4] CC1捕获/比较通道使能(CC1 Capture/Compare Enable) */
+ __IOM uint32_t CC1NE : 1; /*!< [5..5] CC1N捕获/比较互补通道使能(CC1N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC1P : 2; /*!< [7..6] CC1捕获/比较极性选择(CC1 Compare/Capture Polarity) */
+ __IOM uint32_t CC2E : 1; /*!< [8..8] CC2捕获/比较通道使能(CC2 Capture/Compare Enable) */
+ __IOM uint32_t CC2NE : 1; /*!< [9..9] CC2N捕获/比较互补通道使能(CC2N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC2P : 2; /*!< [11..10] CC2捕获/比较极性选择(CC2 Compare/Capture Polarity) */
+ __IOM uint32_t CC3E : 1; /*!< [12..12] CC3捕获/比较通道使能(CC3 Capture/Compare Enable) */
+ __IOM uint32_t CC3NE : 1; /*!< [13..13] CC3N捕获/比较互补通道使能(CC3N Capture/Compare
+ Enable) */
+ __IOM uint32_t CC3P : 2; /*!< [15..14] CC3捕获/比较极性选择(CC3 Compare/Capture Polarity) */
+ uint32_t : 16;
+ } CCER_b;
+ } ;
+
+ union {
+ __IOM uint32_t DCR; /*!< (@ 0x00000028) TMRx Dead-Time Contorl Register */
+
+ struct {
+ __IOM uint32_t DTG : 8; /*!< [7..0] 配置死区时间选择(Dead-Time Generator Setup) */
+ __IOM uint32_t OSSI : 1; /*!< [8..8] 空闲模式下关闭状态选择(Off-State Selection
+ for Idle-Mode) */
+ __IOM uint32_t OSSR : 1; /*!< [9..9] 运行模式下关闭状态选择(Off-State Selection
+ for Run-Mode) */
+ __IOM uint32_t AOE : 1; /*!< [10..10] 自动输出使能(Automatic Output Enable) */
+ __IOM uint32_t MOE : 1; /*!< [11..11] 主路输出使能(Main Output Enable) */
+ __IOM uint32_t BK0E : 1; /*!< [12..12] 断路控制使能(Break0 Enable) */
+ __IOM uint32_t BK0P : 1; /*!< [13..13] 断路输入极性(Break0 Polarity) */
+ __IOM uint32_t BK0F : 8; /*!< [21..14] 断路滤波器(Break0 Filter) */
+ __IOM uint32_t BK1E : 1; /*!< [22..22] 断路控制使能(Break1 Enable) */
+ __IOM uint32_t BK1P : 1; /*!< [23..23] 断路输入极性(Break1 Polarity) */
+ __IOM uint32_t BK1F : 8; /*!< [31..24] 断路滤波器(Break1 Filter) */
+ } DCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t TTCR; /*!< (@ 0x0000002C) TMRx Trigger Cycles Register */
+
+ struct {
+ __IOM uint32_t TOW : 4; /*!< [3..0] TRGO脉冲宽度控制(Trigger Output Width) */
+ __IOM uint32_t TCW : 4; /*!< [7..4] TRGCC脉冲宽度控制(Trigger Compare/Caputre Width) */
+ __IOM uint32_t TC0E : 1; /*!< [8..8] TRGO CH0输出使能(Trigger CH0 Enable) */
+ __IOM uint32_t TC1E : 1; /*!< [9..9] TRGO CH1输出使能(Trigger CH1 Enable) */
+ __IOM uint32_t TC2E : 1; /*!< [10..10] TRGO CH2输出使能(Trigger CH2 Enable) */
+ __IOM uint32_t TC3E : 1; /*!< [11..11] TRGO CH3输出使能(Trigger CH3 Enable) */
+ uint32_t : 20;
+ } TTCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+
+ struct {
+ __IOM uint32_t CPV : 16; /*!< [15..0] 计数周期值(Counter Period Value) */
+ uint32_t : 16;
+ } CPR_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 16; /*!< [15..0] 预分频寄存器（Prescaler Value) */
+ uint32_t : 16;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+
+ struct {
+ __IOM uint32_t CNT : 16; /*!< [15..0] 定时器计数值(Counter Value) */
+ uint32_t : 16;
+ } CNTR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CRR; /*!< (@ 0x00000040) TMRx Counter Repeat Register */
+
+ struct {
+ __IOM uint32_t REP : 8; /*!< [7..0] 重复计数值(Counter Repeat Value) */
+ uint32_t : 24;
+ } CRR_b;
+ } ;
+ __IM uint32_t RESERVED2[3];
+
+ union {
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Capture Compare Register0 */
+
+ struct {
+ __IOM uint32_t CC0V : 16; /*!< [15..0] CC0捕获/比较值(CC0 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC0R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC1R; /*!< (@ 0x00000054) TMRx Capture Compare Register1 */
+
+ struct {
+ __IOM uint32_t CC1V : 16; /*!< [15..0] CC1捕获/比较值(CC1 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC1R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC2R; /*!< (@ 0x00000058) TMRx Capture Compare Register2 */
+
+ struct {
+ __IOM uint32_t CC2V : 16; /*!< [15..0] CC2捕获/比较值(CC2 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC2R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CC3R; /*!< (@ 0x0000005C) TMRx Capture Compare Register3 */
+
+ struct {
+ __IOM uint32_t CC3V : 16; /*!< [15..0] CC3捕获/比较值(CC3 Capture/Compare Value) */
+ uint32_t : 16;
+ } CC3R_b;
+ } ;
+
+ union {
+ __IOM uint32_t CIR; /*!< (@ 0x00000060) TMRx Capture Input Register */
+
+ struct {
+ __IOM uint32_t C0TIS : 4; /*!< [3..0] CH0触发输入选择(CH0 Trigger Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C1TIS : 4; /*!< [11..8] CH1触发输入选择(CH1 Capture Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C2TIS : 4; /*!< [19..16] CH2触发输入选择(CH2 Capture Input Selection) */
+ uint32_t : 4;
+ __IOM uint32_t C3TIS : 4; /*!< [27..24] CH3触发输入选择(CH3 Capture Input Selection) */
+ uint32_t : 4;
+ } CIR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BPR; /*!< (@ 0x00000064) TMRx Break Polarity Register */
+
+ struct {
+ __IOM uint32_t B0POL : 16; /*!< [15..0] Break0输入极性选择(Break0 Input Polarity Selection) */
+ __IOM uint32_t B1POL : 16; /*!< [31..16] Break1输入极性选择(Break1 Input Polarity Selection) */
+ } BPR_b;
+ } ;
+
+ union {
+ __IOM uint32_t BER; /*!< (@ 0x00000068) TMRx Break Enable Register */
+
+ struct {
+ __IOM uint32_t B0IEN : 16; /*!< [15..0] Break0输入使能控制(Break0 Input Enable) */
+ __IOM uint32_t B1IEN : 16; /*!< [31..16] Break1输入使能控制(Break1 Input Enable) */
+ } BER_b;
+ } ;
+} TMR10_Type; /*!< Size = 108 (0x6c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ADC0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief ADC0 (ADC0)
+ */
+
+typedef struct { /*!< (@ 0x40038000) ADC0 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) ADC Control Register */
+
+ struct {
+ __IOM uint32_t ADEN : 1; /*!< [0..0] ADC 开始模块使能命令 */
+ __IOM uint32_t ADDIS : 1; /*!< [1..1] ADC 停止模块使能命令 */
+ __IOM uint32_t ADSTART : 1; /*!< [2..2] ADC 开始常规转换命令 */
+ __IOM uint32_t JADSTART : 1; /*!< [3..3] ADC 开始注入转换命令 */
+ __IOM uint32_t ADSTP : 1; /*!< [4..4] ADC 停止常规转换命令 */
+ __IOM uint32_t JADSTP : 1; /*!< [5..5] ADC 停止注入转换命令 */
+ __IOM uint32_t ADCAL : 1; /*!< [6..6] ADC 启动校准命令 */
+ __IOM uint32_t ADCALDIF : 1; /*!< [7..7] ADC 校准模式选择 */
+ uint32_t : 24;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFGR0; /*!< (@ 0x00000004) ADC Configuration Register0 */
+
+ struct {
+ __IOM uint32_t ROVSE : 1; /*!< [0..0] 规则序列过采样使能 */
+ __IOM uint32_t JOVSE : 1; /*!< [1..1] 注入序列过采样使能 */
+ uint32_t : 2;
+ __IOM uint32_t OVSR : 3; /*!< [6..4] 过采样数据叠加比率 */
+ __IOM uint32_t ROVSM : 1; /*!< [7..7] 常规通道的过采样模式 */
+ __IOM uint32_t OVSS : 4; /*!< [11..8] 过采样数据移位位数 */
+ __IOM uint32_t TROVS : 1; /*!< [12..12] 触发式规则序列过采样使能 */
+ uint32_t : 1;
+ __IOM uint32_t SDMAEN : 1; /*!< [14..14] 系统DMA请求使能 */
+ __IOM uint32_t OVRMOD : 1; /*!< [15..15] 数据溢出模式 */
+ __IOM uint32_t DISCEN : 1; /*!< [16..16] 常规序列的单次／不连续转换模式 */
+ __IOM uint32_t DISCNUM : 3; /*!< [19..17] 不连续采样模式通道计数 */
+ __IOM uint32_t JDISCEN : 1; /*!< [20..20] 注入序列的不连续采样模式 */
+ uint32_t : 1;
+ __IOM uint32_t JAUTO : 1; /*!< [22..22] 注入序列自动转换 */
+ __IOM uint32_t CONT : 1; /*!< [23..23] 常规序列的单次／连续转换模式 */
+ uint32_t : 4;
+ __IOM uint32_t OVSCAL : 3; /*!< [30..28] 自动校准数据叠加比率 */
+ uint32_t : 1;
+ } CFGR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFGR1; /*!< (@ 0x00000008) ADC Configuration Register1 */
+
+ struct {
+ __IOM uint32_t BIASEN : 1; /*!< [0..0] 内部偏置模块使能 */
+ __IOM uint32_t REFEN : 1; /*!< [1..1] Reference模块使能 */
+ uint32_t : 1;
+ __IOM uint32_t CHEN : 1; /*!< [3..3] 通道使能 */
+ __IOM uint32_t ISEL : 2; /*!< [5..4] 偏置电流档位 */
+ uint32_t : 2;
+ __IOM uint32_t AWD0EN : 1; /*!< [8..8] 模拟看门狗 0 监测规则序列 */
+ __IOM uint32_t AWD1EN : 1; /*!< [9..9] 模拟看门狗 1 监测规则序列 */
+ __IOM uint32_t AWD2EN : 1; /*!< [10..10] 模拟看门狗 2 监测规则序列 */
+ uint32_t : 1;
+ __IOM uint32_t JAWD0EN : 1; /*!< [12..12] 模拟看门狗 0 监测注入序列 */
+ __IOM uint32_t JAWD1EN : 1; /*!< [13..13] 模拟看门狗 1 监测注入序列 */
+ __IOM uint32_t JAWD2EN : 1; /*!< [14..14] 模拟看门狗 2 监测注入序列 */
+ uint32_t : 17;
+ } CFGR1_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) ADC Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t EOC : 1; /*!< [0..0] 常规转换结束中断标志 */
+ __IOM uint32_t EOS : 1; /*!< [1..1] 常规序列结束中断标志 */
+ __IOM uint32_t JEOC : 1; /*!< [2..2] 注入转换结束中断标志 */
+ __IOM uint32_t JEOS : 1; /*!< [3..3] 注入序列结束中断标志 */
+ __IOM uint32_t OVR : 1; /*!< [4..4] ADC 数据溢出中断标志 */
+ __IOM uint32_t AWD0 : 1; /*!< [5..5] 模拟看门狗 0 中断标志 */
+ __IOM uint32_t AWD1 : 1; /*!< [6..6] 模拟看门狗 1 中断标志 */
+ __IOM uint32_t AWD2 : 1; /*!< [7..7] 模拟看门狗 2 中断标志 */
+ __IOM uint32_t ADRDY : 1; /*!< [8..8] ADC 就绪中断标志 */
+ __IOM uint32_t EOSMP : 1; /*!< [9..9] 采样阶段结束中断标志 */
+ uint32_t : 22;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000014) ADC Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t EOCIE : 1; /*!< [0..0] 常规转换结束中断使能 */
+ __IOM uint32_t EOSIE : 1; /*!< [1..1] 常规序列结束中断使能 */
+ __IOM uint32_t JEOCIE : 1; /*!< [2..2] 注入转换结束中断使能 */
+ __IOM uint32_t JEOSIE : 1; /*!< [3..3] 注入序列结束中断使能 */
+ __IOM uint32_t OVRIE : 1; /*!< [4..4] ADC 数据溢出中断使能 */
+ __IOM uint32_t AWD0IE : 1; /*!< [5..5] 模拟看门狗 0 中断使能 */
+ __IOM uint32_t AWD1IE : 1; /*!< [6..6] 模拟看门狗 1 中断使能 */
+ __IOM uint32_t AWD2IE : 1; /*!< [7..7] 模拟看门狗 2 中断使能 */
+ __IOM uint32_t ADRDYIE : 1; /*!< [8..8] ADC 就绪中断使能 */
+ __IOM uint32_t EOSMPIE : 1; /*!< [9..9] 采样阶段结束中断使能 */
+ uint32_t : 22;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIGSEL; /*!< (@ 0x00000018) ADC Single-End Select Register */
+
+ struct {
+ __IOM uint32_t SIGSEL : 20; /*!< [19..0] ADC 通道转换模式选择 */
+ uint32_t : 12;
+ } SIGSEL_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t SMPR0; /*!< (@ 0x00000020) ADC Sample Time Register 0 */
+
+ struct {
+ __IOM uint32_t SMP0 : 3; /*!< [2..0] 通道 0 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP1 : 3; /*!< [6..4] 通道 1 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP2 : 3; /*!< [10..8] 通道 2 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP3 : 3; /*!< [14..12] 通道 3 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP4 : 3; /*!< [18..16] 通道 4 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP5 : 3; /*!< [22..20] 通道 5 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP6 : 3; /*!< [26..24] 通道 6 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP7 : 3; /*!< [30..28] 通道 7 采样时间选择位 */
+ uint32_t : 1;
+ } SMPR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t SMPR1; /*!< (@ 0x00000024) ADC Sample Time Register 1 */
+
+ struct {
+ __IOM uint32_t SMP8 : 3; /*!< [2..0] 通道 8 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP9 : 3; /*!< [6..4] 通道 9 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP10 : 3; /*!< [10..8] 通道 10 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP11 : 3; /*!< [14..12] 通道 11 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP12 : 3; /*!< [18..16] 通道 12 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP13 : 3; /*!< [22..20] 通道 13 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP14 : 3; /*!< [26..24] 通道 14 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP15 : 3; /*!< [30..28] 通道 15 采样时间选择位 */
+ uint32_t : 1;
+ } SMPR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SMPR2; /*!< (@ 0x00000028) ADC Sample Time Register 2 */
+
+ struct {
+ __IOM uint32_t SMP16 : 3; /*!< [2..0] 通道 16 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP17 : 3; /*!< [6..4] 通道 17 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP18 : 3; /*!< [10..8] 通道 18 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP19 : 3; /*!< [14..12] 通道 19 采样时间选择位 */
+ uint32_t : 17;
+ } SMPR2_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t CALR0; /*!< (@ 0x00000030) ADC Calibration Data Register 0 */
+
+ struct {
+ __IOM uint32_t CAL0 : 2; /*!< [1..0] 通道 0 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT0 : 1; /*!< [3..3] 通道 0 饱和运算选择位 */
+ __IOM uint32_t CAL1 : 2; /*!< [5..4] 通道 1 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT1 : 1; /*!< [7..7] 通道 1 饱和运算选择位 */
+ __IOM uint32_t CAL2 : 2; /*!< [9..8] 通道 2 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT2 : 1; /*!< [11..11] 通道 2 饱和运算选择位 */
+ __IOM uint32_t CAL3 : 2; /*!< [13..12] 通道 3 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT3 : 1; /*!< [15..15] 通道 3 饱和运算选择位 */
+ __IOM uint32_t CAL4 : 2; /*!< [17..16] 通道 4 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT4 : 1; /*!< [19..19] 通道 4 饱和运算选择位 */
+ __IOM uint32_t CAL5 : 2; /*!< [21..20] 通道 5 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT5 : 1; /*!< [23..23] 通道 5 饱和运算选择位 */
+ __IOM uint32_t CAL6 : 2; /*!< [25..24] 通道 6 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT6 : 1; /*!< [27..27] 通道 6 饱和运算选择位 */
+ __IOM uint32_t CAL7 : 2; /*!< [29..28] 通道 7 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT7 : 1; /*!< [31..31] 通道 7 饱和运算选择位 */
+ } CALR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CALR1; /*!< (@ 0x00000034) ADC Calibration Data Register 1 */
+
+ struct {
+ __IOM uint32_t CAL8 : 2; /*!< [1..0] 通道 8 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT8 : 1; /*!< [3..3] 通道 8 饱和运算选择位 */
+ __IOM uint32_t CAL9 : 2; /*!< [5..4] 通道 9 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT9 : 1; /*!< [7..7] 通道 9 饱和运算选择位 */
+ __IOM uint32_t CAL10 : 2; /*!< [9..8] 通道 10 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT10 : 1; /*!< [11..11] 通道 10 饱和运算选择位 */
+ __IOM uint32_t CAL11 : 2; /*!< [13..12] 通道 11 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT11 : 1; /*!< [15..15] 通道 11 饱和运算选择位 */
+ __IOM uint32_t CAL12 : 2; /*!< [17..16] 通道 12 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT12 : 1; /*!< [19..19] 通道 12 饱和运算选择位 */
+ __IOM uint32_t CAL13 : 2; /*!< [21..20] 通道 13 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT13 : 1; /*!< [23..23] 通道 13 饱和运算选择位 */
+ __IOM uint32_t CAL14 : 2; /*!< [25..24] 通道 14 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT14 : 1; /*!< [27..27] 通道 14 饱和运算选择位 */
+ __IOM uint32_t CAL15 : 2; /*!< [29..28] 通道 15 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT15 : 1; /*!< [31..31] 通道 15 饱和运算选择位 */
+ } CALR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t CALR2; /*!< (@ 0x00000038) ADC Calibration Data Register 2 */
+
+ struct {
+ __IOM uint32_t CAL16 : 2; /*!< [1..0] 通道 16 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT16 : 1; /*!< [3..3] 通道 16 饱和运算选择位 */
+ __IOM uint32_t CAL17 : 2; /*!< [5..4] 通道 17 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT17 : 1; /*!< [7..7] 通道 17 饱和运算选择位 */
+ __IOM uint32_t CAL18 : 2; /*!< [9..8] 通道 18 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT18 : 1; /*!< [11..11] 通道 18 饱和运算选择位 */
+ __IOM uint32_t CAL19 : 2; /*!< [13..12] 通道 19 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT19 : 1; /*!< [15..15] 通道 19 饱和运算选择位 */
+ uint32_t : 16;
+ } CALR2_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t SQR0; /*!< (@ 0x00000040) ADC Regular Sequence Register0 */
+
+ struct {
+ __IOM uint32_t SQ1 : 5; /*!< [4..0] 常规序列中的第 1 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ2 : 5; /*!< [10..6] 常规序列中的第 2 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ3 : 5; /*!< [16..12] 常规序列中的第 3 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ4 : 5; /*!< [22..18] 常规序列中的第 4 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ5 : 5; /*!< [28..24] 常规序列中的第 5 次转换 */
+ uint32_t : 3;
+ } SQR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR1; /*!< (@ 0x00000044) ADC Regular Sequence Register1 */
+
+ struct {
+ __IOM uint32_t SQ6 : 5; /*!< [4..0] 常规序列中的第 6 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ7 : 5; /*!< [10..6] 常规序列中的第 7 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ8 : 5; /*!< [16..12] 常规序列中的第 8 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ9 : 5; /*!< [22..18] 常规序列中的第 9 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ10 : 5; /*!< [28..24] 常规序列中的第 10 次转换 */
+ uint32_t : 3;
+ } SQR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR2; /*!< (@ 0x00000048) ADC Regular Sequence Register2 */
+
+ struct {
+ __IOM uint32_t SQ11 : 5; /*!< [4..0] 常规序列中的第 11 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ12 : 5; /*!< [10..6] 常规序列中的第 12 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ13 : 5; /*!< [16..12] 常规序列中的第 13 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ14 : 5; /*!< [22..18] 常规序列中的第 14 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ15 : 5; /*!< [28..24] 常规序列中的第 15 次转换 */
+ uint32_t : 3;
+ } SQR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR3; /*!< (@ 0x0000004C) ADC Regular Sequence Register3 */
+
+ struct {
+ __IOM uint32_t SQ16 : 5; /*!< [4..0] 常规序列中的第 16 次转换 */
+ uint32_t : 27;
+ } SQR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t LR; /*!< (@ 0x00000050) ADC Regular Length Register */
+
+ struct {
+ __IOM uint32_t EXTSEL : 5; /*!< [4..0] 常规序列的硬件触发选择 */
+ uint32_t : 1;
+ __IOM uint32_t EXTEN : 2; /*!< [7..6] 常规序列的硬件触发使能和极性选择 */
+ __IOM uint32_t LEN : 4; /*!< [11..8] 常规序列的长度 */
+ uint32_t : 20;
+ } LR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DR; /*!< (@ 0x00000054) ADC Regular Data Register */
+
+ struct {
+ __IOM uint32_t RDATA : 16; /*!< [15..0] 常规序列已转换的数据 */
+ uint32_t : 16;
+ } DR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MAXDR; /*!< (@ 0x00000058) ADC Maximum Regular Data Register */
+
+ struct {
+ __IOM uint32_t MAXDATA : 16; /*!< [15..0] 常规序列数据饱和运算最大值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MAXDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MINDR; /*!< (@ 0x0000005C) ADC Minimum Regular Data Register */
+
+ struct {
+ __IOM uint32_t MINDATA : 16; /*!< [15..0] 常规序列数据饱和运算最小值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MINDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JSQR; /*!< (@ 0x00000060) ADC Injected Sequence Register */
+
+ struct {
+ __IOM uint32_t JSQ1 : 5; /*!< [4..0] 注入序列中的第 1 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ2 : 5; /*!< [10..6] 注入序列中的第 2 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ3 : 5; /*!< [16..12] 注入序列中的第 3 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ4 : 5; /*!< [22..18] 注入序列中的第 4 次转换 */
+ uint32_t : 9;
+ } JSQR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JLR; /*!< (@ 0x00000064) ADC Injected Length Register */
+
+ struct {
+ __IOM uint32_t JEXTSEL : 5; /*!< [4..0] 注入序列的硬件触发选择 */
+ uint32_t : 1;
+ __IOM uint32_t JEXTEN : 2; /*!< [7..6] 注入序列的硬件触发使能和极性选择 */
+ __IOM uint32_t JLEN : 2; /*!< [9..8] 注入序列的长度 */
+ uint32_t : 22;
+ } JLR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MAXJDR; /*!< (@ 0x00000068) ADC Maximum Injected Data Register */
+
+ struct {
+ __IOM uint32_t MAXDATA : 16; /*!< [15..0] 注入序列数据饱和运算最大值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MAXJDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MINJDR; /*!< (@ 0x0000006C) ADC Minimum Injected Data Register */
+
+ struct {
+ __IOM uint32_t MINDATA : 16; /*!< [15..0] 注入序列数据饱和运算最小值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MINJDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR0; /*!< (@ 0x00000070) ADC Injected Data Register0 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 0 个已转换数据 */
+ uint32_t : 16;
+ } JDR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR1; /*!< (@ 0x00000074) ADC Injected Data Register1 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 1 个已转换数据 */
+ uint32_t : 16;
+ } JDR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR2; /*!< (@ 0x00000078) ADC Injected Data Register2 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 2 个已转换数据 */
+ uint32_t : 16;
+ } JDR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR3; /*!< (@ 0x0000007C) ADC Injected Data Register3 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 3 个已转换数据 */
+ uint32_t : 16;
+ } JDR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR0; /*!< (@ 0x00000080) ADC Watchdog0 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT0 : 16; /*!< [15..0] 模拟看门狗 0 阈值下限 */
+ __IOM uint32_t HT0 : 16; /*!< [31..16] 模拟看门狗 0 阈值上限 */
+ } TR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR1; /*!< (@ 0x00000084) ADC Watchdog1 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT1 : 16; /*!< [15..0] 模拟看门狗 1 阈值下限 */
+ __IOM uint32_t HT1 : 16; /*!< [31..16] 模拟看门狗 1 阈值上限 */
+ } TR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR2; /*!< (@ 0x00000088) ADC Watchdog2 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT2 : 16; /*!< [15..0] 模拟看门狗 2 阈值下限 */
+ __IOM uint32_t HT2 : 16; /*!< [31..16] 模拟看门狗 2 阈值上限 */
+ } TR2_b;
+ } ;
+ __IM uint32_t RESERVED4;
+
+ union {
+ __IOM uint32_t AWD0CR; /*!< (@ 0x00000090) ADC Watchdog0 Control Register */
+
+ struct {
+ __IOM uint32_t AW0CH : 20; /*!< [19..0] 模拟看门狗 0 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 0 滤波点数 */
+ uint32_t : 4;
+ } AWD0CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AWD1CR; /*!< (@ 0x00000094) ADC Watchdog1 Control Register */
+
+ struct {
+ __IOM uint32_t AW1CH : 20; /*!< [19..0] 模拟看门狗 1 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 1 滤波点数 */
+ uint32_t : 4;
+ } AWD1CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AWD2CR; /*!< (@ 0x00000098) ADC Watchdog 2 Control Register */
+
+ struct {
+ __IOM uint32_t AW2CH : 20; /*!< [19..0] 模拟看门狗 2 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 2 滤波点数 */
+ uint32_t : 4;
+ } AWD2CR_b;
+ } ;
+ __IM uint32_t RESERVED5;
+
+ union {
+ __IOM uint32_t OFR0; /*!< (@ 0x000000A0) ADC Offset Register0 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 0 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR1; /*!< (@ 0x000000A4) ADC Offset Register1 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 1 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR2; /*!< (@ 0x000000A8) ADC Offset Register2 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 2 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR3; /*!< (@ 0x000000AC) ADC Offset Register3 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 3 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR3_b;
+ } ;
+ __IM uint32_t RESERVED6[4];
+
+ union {
+ __IOM uint32_t GCR0; /*!< (@ 0x000000C0) ADC Gain Coeff Register0 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 0 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR1; /*!< (@ 0x000000C4) ADC Gain Coeff Register1 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 1 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR2; /*!< (@ 0x000000C8) ADC Gain Coeff Register2 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 2 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR3; /*!< (@ 0x000000CC) ADC Gain Coeff Register3 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 3 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR3_b;
+ } ;
+ __IM uint32_t RESERVED7[12];
+
+ union {
+ __IOM uint32_t DISR; /*!< (@ 0x00000100) ADC Data Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t DON0 : 1; /*!< [0..0] 通道 0 转换完成中断标志 */
+ __IOM uint32_t DON1 : 1; /*!< [1..1] 通道 1 转换完成中断标志 */
+ __IOM uint32_t DON2 : 1; /*!< [2..2] 通道 2 转换完成中断标志 */
+ __IOM uint32_t DON3 : 1; /*!< [3..3] 通道 3 转换完成中断标志 */
+ __IOM uint32_t DON4 : 1; /*!< [4..4] 通道 4 转换完成中断标志 */
+ __IOM uint32_t DON5 : 1; /*!< [5..5] 通道 5 转换完成中断标志 */
+ __IOM uint32_t DON6 : 1; /*!< [6..6] 通道 6 转换完成中断标志 */
+ __IOM uint32_t DON7 : 1; /*!< [7..7] 通道 7 转换完成中断标志 */
+ __IOM uint32_t DON8 : 1; /*!< [8..8] 通道 8 转换完成中断标志 */
+ __IOM uint32_t DON9 : 1; /*!< [9..9] 通道 9 转换完成中断标志 */
+ __IOM uint32_t DON10 : 1; /*!< [10..10] 通道 10 转换完成中断标志 */
+ __IOM uint32_t DON11 : 1; /*!< [11..11] 通道 11 转换完成中断标志 */
+ __IOM uint32_t DON12 : 1; /*!< [12..12] 通道 12 转换完成中断标志 */
+ __IOM uint32_t DON13 : 1; /*!< [13..13] 通道 13 转换完成中断标志 */
+ __IOM uint32_t DON14 : 1; /*!< [14..14] 通道 14 转换完成中断标志 */
+ __IOM uint32_t DON15 : 1; /*!< [15..15] 通道 15 转换完成中断标志 */
+ __IOM uint32_t DON16 : 1; /*!< [16..16] 通道 16 转换完成中断标志 */
+ __IOM uint32_t DON17 : 1; /*!< [17..17] 通道 17 转换完成中断标志 */
+ __IOM uint32_t DON18 : 1; /*!< [18..18] 通道 18 转换完成中断标志 */
+ __IOM uint32_t DON19 : 1; /*!< [19..19] 通道 19 转换完成中断标志 */
+ uint32_t : 12;
+ } DISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DIER; /*!< (@ 0x00000104) ADC Data Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t DONIE0 : 1; /*!< [0..0] 通道 0 转换完成中断使能 */
+ __IOM uint32_t DONIE1 : 1; /*!< [1..1] 通道 1 转换完成中断使能 */
+ __IOM uint32_t DONIE2 : 1; /*!< [2..2] 通道 2 转换完成中断使能 */
+ __IOM uint32_t DONIE3 : 1; /*!< [3..3] 通道 3 转换完成中断使能 */
+ __IOM uint32_t DONIE4 : 1; /*!< [4..4] 通道 4 转换完成中断使能 */
+ __IOM uint32_t DONIE5 : 1; /*!< [5..5] 通道 5 转换完成中断使能 */
+ __IOM uint32_t DONIE6 : 1; /*!< [6..6] 通道 6 转换完成中断使能 */
+ __IOM uint32_t DONIE7 : 1; /*!< [7..7] 通道 7 转换完成中断使能 */
+ __IOM uint32_t DONIE8 : 1; /*!< [8..8] 通道 8 转换完成中断使能 */
+ __IOM uint32_t DONIE9 : 1; /*!< [9..9] 通道 9 转换完成中断使能 */
+ __IOM uint32_t DONIE10 : 1; /*!< [10..10] 通道 10 转换完成中断使能 */
+ __IOM uint32_t DONIE11 : 1; /*!< [11..11] 通道 11 转换完成中断使能 */
+ __IOM uint32_t DONIE12 : 1; /*!< [12..12] 通道 12 转换完成中断使能 */
+ __IOM uint32_t DONIE13 : 1; /*!< [13..13] 通道 13 转换完成中断使能 */
+ __IOM uint32_t DONIE14 : 1; /*!< [14..14] 通道 14 转换完成中断使能 */
+ __IOM uint32_t DONIE15 : 1; /*!< [15..15] 通道 15 转换完成中断使能 */
+ __IOM uint32_t DONIE16 : 1; /*!< [16..16] 通道 16 转换完成中断使能 */
+ __IOM uint32_t DONIE17 : 1; /*!< [17..17] 通道 17 转换完成中断使能 */
+ __IOM uint32_t DONIE18 : 1; /*!< [18..18] 通道 18 转换完成中断使能 */
+ __IOM uint32_t DONIE19 : 1; /*!< [19..19] 通道 19 转换完成中断使能 */
+ uint32_t : 12;
+ } DIER_b;
+ } ;
+ __IM uint32_t RESERVED8[2];
+
+ union {
+ __IOM uint32_t CDR0; /*!< (@ 0x00000110) ADC Channel Data Register0 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 0 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR1; /*!< (@ 0x00000114) ADC Channel Data Register1 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 1 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR2; /*!< (@ 0x00000118) ADC Channel Data Register2 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 2 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR3; /*!< (@ 0x0000011C) ADC Channel Data Register3 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 3 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR4; /*!< (@ 0x00000120) ADC Channel Data Register4 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 4 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR5; /*!< (@ 0x00000124) ADC Channel Data Register5 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 5 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR6; /*!< (@ 0x00000128) ADC Channel Data Register6 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 6 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR7; /*!< (@ 0x0000012C) ADC Channel Data Register7 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 7 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR8; /*!< (@ 0x00000130) ADC Channel Data Register8 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 8 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR9; /*!< (@ 0x00000134) ADC Channel Data Register9 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 9 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR10; /*!< (@ 0x00000138) ADC Channel Data Register10 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 10 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR11; /*!< (@ 0x0000013C) ADC Channel Data Register11 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 11 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR12; /*!< (@ 0x00000140) ADC Channel Data Register12 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 12 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR13; /*!< (@ 0x00000144) ADC Channel Data Register13 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 13 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR14; /*!< (@ 0x00000148) ADC Channel Data Register14 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 14 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR15; /*!< (@ 0x0000014C) ADC Channel Data Register15 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 15 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR16; /*!< (@ 0x00000150) ADC Channel Data Register16 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 16 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR17; /*!< (@ 0x00000154) ADC Channel Data Register17 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 17 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR18; /*!< (@ 0x00000158) ADC Channel Data Register18 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 18 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR19; /*!< (@ 0x0000015C) ADC Channel Data Register19 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 19 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR19_b;
+ } ;
+ __IM uint32_t RESERVED9[8];
+
+ union {
+ __IOM uint32_t HISR; /*!< (@ 0x00000180) ADC Half Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t HLF0 : 1; /*!< [0..0] 通道 0 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF1 : 1; /*!< [1..1] 通道 1 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF2 : 1; /*!< [2..2] 通道 2 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF3 : 1; /*!< [3..3] 通道 3 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF4 : 1; /*!< [4..4] 通道 4 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF5 : 1; /*!< [5..5] 通道 5 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF6 : 1; /*!< [6..6] 通道 6 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF7 : 1; /*!< [7..7] 通道 7 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF8 : 1; /*!< [8..8] 通道 8 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF9 : 1; /*!< [9..9] 通道 9 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF10 : 1; /*!< [10..10] 通道 10 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF11 : 1; /*!< [11..11] 通道 11 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF12 : 1; /*!< [12..12] 通道 12 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF13 : 1; /*!< [13..13] 通道 13 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF14 : 1; /*!< [14..14] 通道 14 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF15 : 1; /*!< [15..15] 通道 15 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF16 : 1; /*!< [16..16] 通道 16 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF17 : 1; /*!< [17..17] 通道 17 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF18 : 1; /*!< [18..18] 通道 18 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF19 : 1; /*!< [19..19] 通道 19 DMA传输半完成中断标志 */
+ uint32_t : 12;
+ } HISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t HIER; /*!< (@ 0x00000184) ADC Half Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t HLFIE0 : 1; /*!< [0..0] 通道 0 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE1 : 1; /*!< [1..1] 通道 1 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE2 : 1; /*!< [2..2] 通道 2 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE3 : 1; /*!< [3..3] 通道 3 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE4 : 1; /*!< [4..4] 通道 4 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE5 : 1; /*!< [5..5] 通道 5 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE6 : 1; /*!< [6..6] 通道 6 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE7 : 1; /*!< [7..7] 通道 7 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE8 : 1; /*!< [8..8] 通道 8 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE9 : 1; /*!< [9..9] 通道 9 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE10 : 1; /*!< [10..10] 通道 10 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE11 : 1; /*!< [11..11] 通道 11 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE12 : 1; /*!< [12..12] 通道 12 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE13 : 1; /*!< [13..13] 通道 13 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE14 : 1; /*!< [14..14] 通道 14 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE15 : 1; /*!< [15..15] 通道 15 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE16 : 1; /*!< [16..16] 通道 16 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE17 : 1; /*!< [17..17] 通道 17 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE18 : 1; /*!< [18..18] 通道 18 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE19 : 1; /*!< [19..19] 通道 19 DMA 传输半完成中断使能 */
+ uint32_t : 12;
+ } HIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t FISR; /*!< (@ 0x00000188) ADC Full Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t FUL0 : 1; /*!< [0..0] 通道 0 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL1 : 1; /*!< [1..1] 通道 1 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL2 : 1; /*!< [2..2] 通道 2 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL3 : 1; /*!< [3..3] 通道 3 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL4 : 1; /*!< [4..4] 通道 4 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL5 : 1; /*!< [5..5] 通道 5 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL6 : 1; /*!< [6..6] 通道 6 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL7 : 1; /*!< [7..7] 通道 7 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL8 : 1; /*!< [8..8] 通道 8 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL9 : 1; /*!< [9..9] 通道 9 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL10 : 1; /*!< [10..10] 通道 10 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL11 : 1; /*!< [11..11] 通道 11 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL12 : 1; /*!< [12..12] 通道 12 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL13 : 1; /*!< [13..13] 通道 13 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL14 : 1; /*!< [14..14] 通道 14 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL15 : 1; /*!< [15..15] 通道 15 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL16 : 1; /*!< [16..16] 通道 16 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL17 : 1; /*!< [17..17] 通道 17 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL18 : 1; /*!< [18..18] 通道 18 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL19 : 1; /*!< [19..19] 通道 19 DMA 传输完成中断标志 */
+ uint32_t : 12;
+ } FISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIER; /*!< (@ 0x0000018C) ADC Full Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t FULIE0 : 1; /*!< [0..0] 通道 0 传输完成中断使能 */
+ __IOM uint32_t FULIE1 : 1; /*!< [1..1] 通道 1 传输完成中断使能 */
+ __IOM uint32_t FULIE2 : 1; /*!< [2..2] 通道 2 传输完成中断使能 */
+ __IOM uint32_t FULIE3 : 1; /*!< [3..3] 通道 3 传输完成中断使能 */
+ __IOM uint32_t FULIE4 : 1; /*!< [4..4] 通道 4 传输完成中断使能 */
+ __IOM uint32_t FULIE5 : 1; /*!< [5..5] 通道 5 传输完成中断使能 */
+ __IOM uint32_t FULIE6 : 1; /*!< [6..6] 通道 6 传输完成中断使能 */
+ __IOM uint32_t FULIE7 : 1; /*!< [7..7] 通道 7 传输完成中断使能 */
+ __IOM uint32_t FULIE8 : 1; /*!< [8..8] 通道 8 传输完成中断使能 */
+ __IOM uint32_t FULIE9 : 1; /*!< [9..9] 通道 9 传输完成中断使能 */
+ __IOM uint32_t FULIE10 : 1; /*!< [10..10] 通道 10 传输完成中断使能 */
+ __IOM uint32_t FULIE11 : 1; /*!< [11..11] 通道 11 传输完成中断使能 */
+ __IOM uint32_t FULIE12 : 1; /*!< [12..12] 通道 12 传输完成中断使能 */
+ __IOM uint32_t FULIE13 : 1; /*!< [13..13] 通道 13 传输完成中断使能 */
+ __IOM uint32_t FULIE14 : 1; /*!< [14..14] 通道 14 传输完成中断使能 */
+ __IOM uint32_t FULIE15 : 1; /*!< [15..15] 通道 15 传输完成中断使能 */
+ __IOM uint32_t FULIE16 : 1; /*!< [16..16] 通道 16 传输完成中断使能 */
+ __IOM uint32_t FULIE17 : 1; /*!< [17..17] 通道 17 传输完成中断使能 */
+ __IOM uint32_t FULIE18 : 1; /*!< [18..18] 通道 18 传输完成中断使能 */
+ __IOM uint32_t FULIE19 : 1; /*!< [19..19] 通道 19 传输完成中断使能 */
+ uint32_t : 12;
+ } FIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t TCR0; /*!< (@ 0x00000190) ADC Transfer Control Register0 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR0; /*!< (@ 0x00000194) ADC Transfer Address Register0 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 0 DMA 传输的首地址 */
+ } TAR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR0; /*!< (@ 0x00000198) ADC Transfer Length Register0 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 0 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR0_b;
+ } ;
+ __IM uint32_t RESERVED10;
+
+ union {
+ __IOM uint32_t TCR1; /*!< (@ 0x000001A0) ADC Transfer Control Register1 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR1; /*!< (@ 0x000001A4) ADC Transfer Address Register1 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 1 DMA 传输的首地址 */
+ } TAR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR1; /*!< (@ 0x000001A8) ADC Transfer Length Register1 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 1 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR1_b;
+ } ;
+ __IM uint32_t RESERVED11;
+
+ union {
+ __IOM uint32_t TCR2; /*!< (@ 0x000001B0) ADC Transfer Control Register2 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR2; /*!< (@ 0x000001B4) ADC Transfer Address Register2 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 2 DMA 传输的首地址 */
+ } TAR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR2; /*!< (@ 0x000001B8) ADC Transfer Length Register2 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 2 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR2_b;
+ } ;
+ __IM uint32_t RESERVED12;
+
+ union {
+ __IOM uint32_t TCR3; /*!< (@ 0x000001C0) ADC Transfer Control Register3 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR3; /*!< (@ 0x000001C4) ADC Transfer Address Register3 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 3 DMA 传输的首地址 */
+ } TAR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR3; /*!< (@ 0x000001C8) ADC Transfer Length Register3 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 3 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR3_b;
+ } ;
+ __IM uint32_t RESERVED13;
+
+ union {
+ __IOM uint32_t TCR4; /*!< (@ 0x000001D0) ADC Transfer Control Register4 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR4; /*!< (@ 0x000001D4) ADC Transfer Address Register4 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 4 DMA 传输的首地址 */
+ } TAR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR4; /*!< (@ 0x000001D8) ADC Transfer Length Register4 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 4 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR4_b;
+ } ;
+ __IM uint32_t RESERVED14;
+
+ union {
+ __IOM uint32_t TCR5; /*!< (@ 0x000001E0) ADC Transfer Control Register5 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR5; /*!< (@ 0x000001E4) ADC Transfer Address Register5 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 5 DMA 传输的首地址 */
+ } TAR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR5; /*!< (@ 0x000001E8) ADC Transfer Length Register5 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 5 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR5_b;
+ } ;
+ __IM uint32_t RESERVED15;
+
+ union {
+ __IOM uint32_t TCR6; /*!< (@ 0x000001F0) ADC Transfer Control Register6 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR6; /*!< (@ 0x000001F4) ADC Transfer Address Register6 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 6 DMA 传输的首地址 */
+ } TAR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR6; /*!< (@ 0x000001F8) ADC Transfer Length Register6 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 6 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR6_b;
+ } ;
+ __IM uint32_t RESERVED16;
+
+ union {
+ __IOM uint32_t TCR7; /*!< (@ 0x00000200) ADC Transfer Control Register7 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR7; /*!< (@ 0x00000204) ADC Transfer Address Register7 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 7 DMA 传输的首地址 */
+ } TAR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR7; /*!< (@ 0x00000208) ADC Transfer Length Register7 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 7 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR7_b;
+ } ;
+ __IM uint32_t RESERVED17;
+
+ union {
+ __IOM uint32_t TCR8; /*!< (@ 0x00000210) ADC Transfer Control Register8 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR8; /*!< (@ 0x00000214) ADC Transfer Address Register8 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 8 DMA 传输的首地址 */
+ } TAR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR8; /*!< (@ 0x00000218) ADC Transfer Length Register8 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 8 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR8_b;
+ } ;
+ __IM uint32_t RESERVED18;
+
+ union {
+ __IOM uint32_t TCR9; /*!< (@ 0x00000220) ADC Transfer Control Register9 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR9; /*!< (@ 0x00000224) ADC Transfer Address Register9 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 9 DMA 传输的首地址 */
+ } TAR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR9; /*!< (@ 0x00000228) ADC Transfer Length Register9 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 9 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR9_b;
+ } ;
+ __IM uint32_t RESERVED19;
+
+ union {
+ __IOM uint32_t TCR10; /*!< (@ 0x00000230) ADC Transfer Control Register10 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR10; /*!< (@ 0x00000234) ADC Transfer Address Register10 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 10 DMA 传输的首地址 */
+ } TAR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR10; /*!< (@ 0x00000238) ADC Transfer Length Register10 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 10 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR10_b;
+ } ;
+ __IM uint32_t RESERVED20;
+
+ union {
+ __IOM uint32_t TCR11; /*!< (@ 0x00000240) ADC Transfer Control Register11 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR11; /*!< (@ 0x00000244) ADC Transfer Address Register11 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 11 DMA 传输的首地址 */
+ } TAR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR11; /*!< (@ 0x00000248) ADC Transfer Length Register11 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 11 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR11_b;
+ } ;
+ __IM uint32_t RESERVED21;
+
+ union {
+ __IOM uint32_t TCR12; /*!< (@ 0x00000250) ADC Transfer Control Register12 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR12; /*!< (@ 0x00000254) ADC Transfer Address Register12 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 12 DMA 传输的首地址 */
+ } TAR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR12; /*!< (@ 0x00000258) ADC Transfer Length Register12 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 12 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR12_b;
+ } ;
+ __IM uint32_t RESERVED22;
+
+ union {
+ __IOM uint32_t TCR13; /*!< (@ 0x00000260) ADC Transfer Control Register13 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR13; /*!< (@ 0x00000264) ADC Transfer Address Register13 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 13 DMA 传输的首地址 */
+ } TAR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR13; /*!< (@ 0x00000268) ADC Transfer Length Register13 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 13 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR13_b;
+ } ;
+ __IM uint32_t RESERVED23;
+
+ union {
+ __IOM uint32_t TCR14; /*!< (@ 0x00000270) ADC Transfer Control Register14 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR14; /*!< (@ 0x00000274) ADC Transfer Address Register14 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 14 DMA 传输的首地址 */
+ } TAR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR14; /*!< (@ 0x00000278) ADC Transfer Length Register14 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 14 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR14_b;
+ } ;
+ __IM uint32_t RESERVED24;
+
+ union {
+ __IOM uint32_t TCR15; /*!< (@ 0x00000280) ADC Transfer Control Register15 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR15; /*!< (@ 0x00000284) ADC Transfer Address Register15 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 15 DMA 传输的首地址 */
+ } TAR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR15; /*!< (@ 0x00000288) ADC Transfer Length Register15 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 15 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR15_b;
+ } ;
+ __IM uint32_t RESERVED25;
+
+ union {
+ __IOM uint32_t TCR16; /*!< (@ 0x00000290) ADC Transfer Control Register16 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR16; /*!< (@ 0x00000294) ADC Transfer Address Register16 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 16 DMA 传输的首地址 */
+ } TAR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR16; /*!< (@ 0x00000298) ADC Transfer Length Register16 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 16 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR16_b;
+ } ;
+ __IM uint32_t RESERVED26;
+
+ union {
+ __IOM uint32_t TCR17; /*!< (@ 0x000002A0) ADC Transfer Control Register17 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR17; /*!< (@ 0x000002A4) ADC Transfer Address Register17 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 17 DMA 传输的首地址 */
+ } TAR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR17; /*!< (@ 0x000002A8) ADC Transfer Length Register17 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 17 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR17_b;
+ } ;
+ __IM uint32_t RESERVED27;
+
+ union {
+ __IOM uint32_t TCR18; /*!< (@ 0x000002B0) ADC Transfer Control Register18 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR18; /*!< (@ 0x000002B4) ADC Transfer Address Register18 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 18 DMA 传输的首地址 */
+ } TAR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR18; /*!< (@ 0x000002B8) ADC Transfer Length Register18 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 18 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR18_b;
+ } ;
+ __IM uint32_t RESERVED28;
+
+ union {
+ __IOM uint32_t TCR19; /*!< (@ 0x000002C0) ADC Transfer Control Register19 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR19_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR19; /*!< (@ 0x000002C4) ADC Transfer Address Register19 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 19 DMA 传输的首地址 */
+ } TAR19_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR19; /*!< (@ 0x000002C8) ADC Transfer Length Register19 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 19 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR19_b;
+ } ;
+ __IM uint32_t RESERVED29[13];
+
+ union {
+ __IOM uint32_t CCR; /*!< (@ 0x00000300) ADC Common Control Registe */
+
+ struct {
+ __IOM uint32_t DUAL : 4; /*!< [3..0] ADC DUAL模式选择（仅Master ADC配置有效） */
+ uint32_t : 4;
+ __IOM uint32_t DELAY : 10; /*!< [17..8] ADC DUAL采样相位延迟（仅Master ADC配置有效） */
+ uint32_t : 14;
+ } CCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CSR; /*!< (@ 0x00000304) ADC Common Status Register */
+
+ struct {
+ __IM uint32_t EOC_MST : 1; /*!< [0..0] 常规转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOS_MST : 1; /*!< [1..1] 常规序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOC_MST : 1; /*!< [2..2] 注入转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOS_MST : 1; /*!< [3..3] 注入序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t OVR_MST : 1; /*!< [4..4] ADC 数据溢出中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD0_MST : 1; /*!< [5..5] 模拟看门狗 0 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD1_MST : 1; /*!< [6..6] 模拟看门狗 1 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD2_MST : 1; /*!< [7..7] 模拟看门狗 2 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t ADRDY_MST : 1; /*!< [8..8] ADC 就绪中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOSMP_MST : 1; /*!< [9..9] 采样阶段结束中断标志（仅Master ADC读取有效） */
+ uint32_t : 6;
+ __IM uint32_t EOC_SLV : 1; /*!< [16..16] 常规转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOS_SLV : 1; /*!< [17..17] 常规序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOC_SLV : 1; /*!< [18..18] 注入转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOS_SLV : 1; /*!< [19..19] 注入序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t OVR_SLV : 1; /*!< [20..20] ADC 数据溢出中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD0_SLV : 1; /*!< [21..21] 模拟看门狗 0 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD1_SLV : 1; /*!< [22..22] 模拟看门狗 1 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD2_SLV : 1; /*!< [23..23] 模拟看门狗 2 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t ADRDY_SLV : 1; /*!< [24..24] ADC 就绪中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOSMP_SLV : 1; /*!< [25..25] 采样阶段结束中断标志（仅Master ADC读取有效） */
+ uint32_t : 6;
+ } CSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR; /*!< (@ 0x00000308) ADC Common Regular Data Register */
+
+ struct {
+ __IM uint32_t RDATA_MST : 16; /*!< [15..0] Master ADC 常规序列已转换的数据（仅Master
+ ADC读取有效） */
+ __IM uint32_t RDATA_SLV : 16; /*!< [31..16] Slave ADC 常规序列已转换的数据（仅Master
+ ADC读取有效） */
+ } CDR_b;
+ } ;
+} ADC0_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ADC1 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief ADC1 (ADC1)
+ */
+
+typedef struct { /*!< (@ 0x40038400) ADC1 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) ADC Control Register */
+
+ struct {
+ __IOM uint32_t ADEN : 1; /*!< [0..0] ADC 开始模块使能命令 */
+ __IOM uint32_t ADDIS : 1; /*!< [1..1] ADC 停止模块使能命令 */
+ __IOM uint32_t ADSTART : 1; /*!< [2..2] ADC 开始常规转换命令 */
+ __IOM uint32_t JADSTART : 1; /*!< [3..3] ADC 开始注入转换命令 */
+ __IOM uint32_t ADSTP : 1; /*!< [4..4] ADC 停止常规转换命令 */
+ __IOM uint32_t JADSTP : 1; /*!< [5..5] ADC 停止注入转换命令 */
+ __IOM uint32_t ADCAL : 1; /*!< [6..6] ADC 启动校准命令 */
+ __IOM uint32_t ADCALDIF : 1; /*!< [7..7] ADC 校准模式选择 */
+ uint32_t : 24;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFGR0; /*!< (@ 0x00000004) ADC Configuration Register0 */
+
+ struct {
+ __IOM uint32_t ROVSE : 1; /*!< [0..0] 规则序列过采样使能 */
+ __IOM uint32_t JOVSE : 1; /*!< [1..1] 注入序列过采样使能 */
+ uint32_t : 2;
+ __IOM uint32_t OVSR : 3; /*!< [6..4] 过采样数据叠加比率 */
+ __IOM uint32_t ROVSM : 1; /*!< [7..7] 常规通道的过采样模式 */
+ __IOM uint32_t OVSS : 4; /*!< [11..8] 过采样数据移位位数 */
+ __IOM uint32_t TROVS : 1; /*!< [12..12] 触发式规则序列过采样使能 */
+ uint32_t : 1;
+ __IOM uint32_t SDMAEN : 1; /*!< [14..14] 系统DMA请求使能 */
+ __IOM uint32_t OVRMOD : 1; /*!< [15..15] 数据溢出模式 */
+ __IOM uint32_t DISCEN : 1; /*!< [16..16] 常规序列的单次／不连续转换模式 */
+ __IOM uint32_t DISCNUM : 3; /*!< [19..17] 不连续采样模式通道计数 */
+ __IOM uint32_t JDISCEN : 1; /*!< [20..20] 注入序列的不连续采样模式 */
+ uint32_t : 1;
+ __IOM uint32_t JAUTO : 1; /*!< [22..22] 注入序列自动转换 */
+ __IOM uint32_t CONT : 1; /*!< [23..23] 常规序列的单次／连续转换模式 */
+ uint32_t : 4;
+ __IOM uint32_t OVSCAL : 3; /*!< [30..28] 自动校准数据叠加比率 */
+ uint32_t : 1;
+ } CFGR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFGR1; /*!< (@ 0x00000008) ADC Configuration Register1 */
+
+ struct {
+ __IOM uint32_t BIASEN : 1; /*!< [0..0] 内部偏置模块使能 */
+ __IOM uint32_t REFEN : 1; /*!< [1..1] Reference模块使能 */
+ uint32_t : 1;
+ __IOM uint32_t CHEN : 1; /*!< [3..3] 通道使能 */
+ __IOM uint32_t ISEL : 2; /*!< [5..4] 偏置电流档位 */
+ uint32_t : 2;
+ __IOM uint32_t AWD0EN : 1; /*!< [8..8] 模拟看门狗 0 监测规则序列 */
+ __IOM uint32_t AWD1EN : 1; /*!< [9..9] 模拟看门狗 1 监测规则序列 */
+ __IOM uint32_t AWD2EN : 1; /*!< [10..10] 模拟看门狗 2 监测规则序列 */
+ uint32_t : 1;
+ __IOM uint32_t JAWD0EN : 1; /*!< [12..12] 模拟看门狗 0 监测注入序列 */
+ __IOM uint32_t JAWD1EN : 1; /*!< [13..13] 模拟看门狗 1 监测注入序列 */
+ __IOM uint32_t JAWD2EN : 1; /*!< [14..14] 模拟看门狗 2 监测注入序列 */
+ uint32_t : 17;
+ } CFGR1_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) ADC Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t EOC : 1; /*!< [0..0] 常规转换结束中断标志 */
+ __IOM uint32_t EOS : 1; /*!< [1..1] 常规序列结束中断标志 */
+ __IOM uint32_t JEOC : 1; /*!< [2..2] 注入转换结束中断标志 */
+ __IOM uint32_t JEOS : 1; /*!< [3..3] 注入序列结束中断标志 */
+ __IOM uint32_t OVR : 1; /*!< [4..4] ADC 数据溢出中断标志 */
+ __IOM uint32_t AWD0 : 1; /*!< [5..5] 模拟看门狗 0 中断标志 */
+ __IOM uint32_t AWD1 : 1; /*!< [6..6] 模拟看门狗 1 中断标志 */
+ __IOM uint32_t AWD2 : 1; /*!< [7..7] 模拟看门狗 2 中断标志 */
+ __IOM uint32_t ADRDY : 1; /*!< [8..8] ADC 就绪中断标志 */
+ __IOM uint32_t EOSMP : 1; /*!< [9..9] 采样阶段结束中断标志 */
+ uint32_t : 22;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000014) ADC Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t EOCIE : 1; /*!< [0..0] 常规转换结束中断使能 */
+ __IOM uint32_t EOSIE : 1; /*!< [1..1] 常规序列结束中断使能 */
+ __IOM uint32_t JEOCIE : 1; /*!< [2..2] 注入转换结束中断使能 */
+ __IOM uint32_t JEOSIE : 1; /*!< [3..3] 注入序列结束中断使能 */
+ __IOM uint32_t OVRIE : 1; /*!< [4..4] ADC 数据溢出中断使能 */
+ __IOM uint32_t AWD0IE : 1; /*!< [5..5] 模拟看门狗 0 中断使能 */
+ __IOM uint32_t AWD1IE : 1; /*!< [6..6] 模拟看门狗 1 中断使能 */
+ __IOM uint32_t AWD2IE : 1; /*!< [7..7] 模拟看门狗 2 中断使能 */
+ __IOM uint32_t ADRDYIE : 1; /*!< [8..8] ADC 就绪中断使能 */
+ __IOM uint32_t EOSMPIE : 1; /*!< [9..9] 采样阶段结束中断使能 */
+ uint32_t : 22;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIGSEL; /*!< (@ 0x00000018) ADC Single-End Select Register */
+
+ struct {
+ __IOM uint32_t SIGSEL : 20; /*!< [19..0] ADC 通道转换模式选择 */
+ uint32_t : 12;
+ } SIGSEL_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t SMPR0; /*!< (@ 0x00000020) ADC Sample Time Register 0 */
+
+ struct {
+ __IOM uint32_t SMP0 : 3; /*!< [2..0] 通道 0 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP1 : 3; /*!< [6..4] 通道 1 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP2 : 3; /*!< [10..8] 通道 2 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP3 : 3; /*!< [14..12] 通道 3 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP4 : 3; /*!< [18..16] 通道 4 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP5 : 3; /*!< [22..20] 通道 5 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP6 : 3; /*!< [26..24] 通道 6 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP7 : 3; /*!< [30..28] 通道 7 采样时间选择位 */
+ uint32_t : 1;
+ } SMPR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t SMPR1; /*!< (@ 0x00000024) ADC Sample Time Register 1 */
+
+ struct {
+ __IOM uint32_t SMP8 : 3; /*!< [2..0] 通道 8 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP9 : 3; /*!< [6..4] 通道 9 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP10 : 3; /*!< [10..8] 通道 10 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP11 : 3; /*!< [14..12] 通道 11 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP12 : 3; /*!< [18..16] 通道 12 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP13 : 3; /*!< [22..20] 通道 13 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP14 : 3; /*!< [26..24] 通道 14 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP15 : 3; /*!< [30..28] 通道 15 采样时间选择位 */
+ uint32_t : 1;
+ } SMPR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SMPR2; /*!< (@ 0x00000028) ADC Sample Time Register 2 */
+
+ struct {
+ __IOM uint32_t SMP16 : 3; /*!< [2..0] 通道 16 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP17 : 3; /*!< [6..4] 通道 17 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP18 : 3; /*!< [10..8] 通道 18 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP19 : 3; /*!< [14..12] 通道 19 采样时间选择位 */
+ uint32_t : 17;
+ } SMPR2_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t CALR0; /*!< (@ 0x00000030) ADC Calibration Data Register 0 */
+
+ struct {
+ __IOM uint32_t CAL0 : 2; /*!< [1..0] 通道 0 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT0 : 1; /*!< [3..3] 通道 0 饱和运算选择位 */
+ __IOM uint32_t CAL1 : 2; /*!< [5..4] 通道 1 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT1 : 1; /*!< [7..7] 通道 1 饱和运算选择位 */
+ __IOM uint32_t CAL2 : 2; /*!< [9..8] 通道 2 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT2 : 1; /*!< [11..11] 通道 2 饱和运算选择位 */
+ __IOM uint32_t CAL3 : 2; /*!< [13..12] 通道 3 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT3 : 1; /*!< [15..15] 通道 3 饱和运算选择位 */
+ __IOM uint32_t CAL4 : 2; /*!< [17..16] 通道 4 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT4 : 1; /*!< [19..19] 通道 4 饱和运算选择位 */
+ __IOM uint32_t CAL5 : 2; /*!< [21..20] 通道 5 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT5 : 1; /*!< [23..23] 通道 5 饱和运算选择位 */
+ __IOM uint32_t CAL6 : 2; /*!< [25..24] 通道 6 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT6 : 1; /*!< [27..27] 通道 6 饱和运算选择位 */
+ __IOM uint32_t CAL7 : 2; /*!< [29..28] 通道 7 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT7 : 1; /*!< [31..31] 通道 7 饱和运算选择位 */
+ } CALR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CALR1; /*!< (@ 0x00000034) ADC Calibration Data Register 1 */
+
+ struct {
+ __IOM uint32_t CAL8 : 2; /*!< [1..0] 通道 8 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT8 : 1; /*!< [3..3] 通道 8 饱和运算选择位 */
+ __IOM uint32_t CAL9 : 2; /*!< [5..4] 通道 9 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT9 : 1; /*!< [7..7] 通道 9 饱和运算选择位 */
+ __IOM uint32_t CAL10 : 2; /*!< [9..8] 通道 10 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT10 : 1; /*!< [11..11] 通道 10 饱和运算选择位 */
+ __IOM uint32_t CAL11 : 2; /*!< [13..12] 通道 11 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT11 : 1; /*!< [15..15] 通道 11 饱和运算选择位 */
+ __IOM uint32_t CAL12 : 2; /*!< [17..16] 通道 12 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT12 : 1; /*!< [19..19] 通道 12 饱和运算选择位 */
+ __IOM uint32_t CAL13 : 2; /*!< [21..20] 通道 13 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT13 : 1; /*!< [23..23] 通道 13 饱和运算选择位 */
+ __IOM uint32_t CAL14 : 2; /*!< [25..24] 通道 14 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT14 : 1; /*!< [27..27] 通道 14 饱和运算选择位 */
+ __IOM uint32_t CAL15 : 2; /*!< [29..28] 通道 15 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT15 : 1; /*!< [31..31] 通道 15 饱和运算选择位 */
+ } CALR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t CALR2; /*!< (@ 0x00000038) ADC Calibration Data Register 2 */
+
+ struct {
+ __IOM uint32_t CAL16 : 2; /*!< [1..0] 通道 16 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT16 : 1; /*!< [3..3] 通道 16 饱和运算选择位 */
+ __IOM uint32_t CAL17 : 2; /*!< [5..4] 通道 17 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT17 : 1; /*!< [7..7] 通道 17 饱和运算选择位 */
+ __IOM uint32_t CAL18 : 2; /*!< [9..8] 通道 18 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT18 : 1; /*!< [11..11] 通道 18 饱和运算选择位 */
+ __IOM uint32_t CAL19 : 2; /*!< [13..12] 通道 19 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT19 : 1; /*!< [15..15] 通道 19 饱和运算选择位 */
+ uint32_t : 16;
+ } CALR2_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t SQR0; /*!< (@ 0x00000040) ADC Regular Sequence Register0 */
+
+ struct {
+ __IOM uint32_t SQ1 : 5; /*!< [4..0] 常规序列中的第 1 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ2 : 5; /*!< [10..6] 常规序列中的第 2 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ3 : 5; /*!< [16..12] 常规序列中的第 3 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ4 : 5; /*!< [22..18] 常规序列中的第 4 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ5 : 5; /*!< [28..24] 常规序列中的第 5 次转换 */
+ uint32_t : 3;
+ } SQR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR1; /*!< (@ 0x00000044) ADC Regular Sequence Register1 */
+
+ struct {
+ __IOM uint32_t SQ6 : 5; /*!< [4..0] 常规序列中的第 6 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ7 : 5; /*!< [10..6] 常规序列中的第 7 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ8 : 5; /*!< [16..12] 常规序列中的第 8 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ9 : 5; /*!< [22..18] 常规序列中的第 9 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ10 : 5; /*!< [28..24] 常规序列中的第 10 次转换 */
+ uint32_t : 3;
+ } SQR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR2; /*!< (@ 0x00000048) ADC Regular Sequence Register2 */
+
+ struct {
+ __IOM uint32_t SQ11 : 5; /*!< [4..0] 常规序列中的第 11 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ12 : 5; /*!< [10..6] 常规序列中的第 12 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ13 : 5; /*!< [16..12] 常规序列中的第 13 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ14 : 5; /*!< [22..18] 常规序列中的第 14 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ15 : 5; /*!< [28..24] 常规序列中的第 15 次转换 */
+ uint32_t : 3;
+ } SQR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR3; /*!< (@ 0x0000004C) ADC Regular Sequence Register3 */
+
+ struct {
+ __IOM uint32_t SQ16 : 5; /*!< [4..0] 常规序列中的第 16 次转换 */
+ uint32_t : 27;
+ } SQR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t LR; /*!< (@ 0x00000050) ADC Regular Length Register */
+
+ struct {
+ __IOM uint32_t EXTSEL : 5; /*!< [4..0] 常规序列的硬件触发选择 */
+ uint32_t : 1;
+ __IOM uint32_t EXTEN : 2; /*!< [7..6] 常规序列的硬件触发使能和极性选择 */
+ __IOM uint32_t LEN : 4; /*!< [11..8] 常规序列的长度 */
+ uint32_t : 20;
+ } LR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DR; /*!< (@ 0x00000054) ADC Regular Data Register */
+
+ struct {
+ __IOM uint32_t RDATA : 16; /*!< [15..0] 常规序列已转换的数据 */
+ uint32_t : 16;
+ } DR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MAXDR; /*!< (@ 0x00000058) ADC Maximum Regular Data Register */
+
+ struct {
+ __IOM uint32_t MAXDATA : 16; /*!< [15..0] 常规序列数据饱和运算最大值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MAXDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MINDR; /*!< (@ 0x0000005C) ADC Minimum Regular Data Register */
+
+ struct {
+ __IOM uint32_t MINDATA : 16; /*!< [15..0] 常规序列数据饱和运算最小值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MINDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JSQR; /*!< (@ 0x00000060) ADC Injected Sequence Register */
+
+ struct {
+ __IOM uint32_t JSQ1 : 5; /*!< [4..0] 注入序列中的第 1 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ2 : 5; /*!< [10..6] 注入序列中的第 2 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ3 : 5; /*!< [16..12] 注入序列中的第 3 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ4 : 5; /*!< [22..18] 注入序列中的第 4 次转换 */
+ uint32_t : 9;
+ } JSQR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JLR; /*!< (@ 0x00000064) ADC Injected Length Register */
+
+ struct {
+ __IOM uint32_t JEXTSEL : 5; /*!< [4..0] 注入序列的硬件触发选择 */
+ uint32_t : 1;
+ __IOM uint32_t JEXTEN : 2; /*!< [7..6] 注入序列的硬件触发使能和极性选择 */
+ __IOM uint32_t JLEN : 2; /*!< [9..8] 注入序列的长度 */
+ uint32_t : 22;
+ } JLR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MAXJDR; /*!< (@ 0x00000068) ADC Maximum Injected Data Register */
+
+ struct {
+ __IOM uint32_t MAXDATA : 16; /*!< [15..0] 注入序列数据饱和运算最大值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MAXJDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MINJDR; /*!< (@ 0x0000006C) ADC Minimum Injected Data Register */
+
+ struct {
+ __IOM uint32_t MINDATA : 16; /*!< [15..0] 注入序列数据饱和运算最小值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MINJDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR0; /*!< (@ 0x00000070) ADC Injected Data Register0 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 0 个已转换数据 */
+ uint32_t : 16;
+ } JDR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR1; /*!< (@ 0x00000074) ADC Injected Data Register1 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 1 个已转换数据 */
+ uint32_t : 16;
+ } JDR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR2; /*!< (@ 0x00000078) ADC Injected Data Register2 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 2 个已转换数据 */
+ uint32_t : 16;
+ } JDR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR3; /*!< (@ 0x0000007C) ADC Injected Data Register3 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 3 个已转换数据 */
+ uint32_t : 16;
+ } JDR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR0; /*!< (@ 0x00000080) ADC Watchdog0 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT0 : 16; /*!< [15..0] 模拟看门狗 0 阈值下限 */
+ __IOM uint32_t HT0 : 16; /*!< [31..16] 模拟看门狗 0 阈值上限 */
+ } TR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR1; /*!< (@ 0x00000084) ADC Watchdog1 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT1 : 16; /*!< [15..0] 模拟看门狗 1 阈值下限 */
+ __IOM uint32_t HT1 : 16; /*!< [31..16] 模拟看门狗 1 阈值上限 */
+ } TR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR2; /*!< (@ 0x00000088) ADC Watchdog2 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT2 : 16; /*!< [15..0] 模拟看门狗 2 阈值下限 */
+ __IOM uint32_t HT2 : 16; /*!< [31..16] 模拟看门狗 2 阈值上限 */
+ } TR2_b;
+ } ;
+ __IM uint32_t RESERVED4;
+
+ union {
+ __IOM uint32_t AWD0CR; /*!< (@ 0x00000090) ADC Watchdog0 Control Register */
+
+ struct {
+ __IOM uint32_t AW0CH : 20; /*!< [19..0] 模拟看门狗 0 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 0 滤波点数 */
+ uint32_t : 4;
+ } AWD0CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AWD1CR; /*!< (@ 0x00000094) ADC Watchdog1 Control Register */
+
+ struct {
+ __IOM uint32_t AW1CH : 20; /*!< [19..0] 模拟看门狗 1 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 1 滤波点数 */
+ uint32_t : 4;
+ } AWD1CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AWD2CR; /*!< (@ 0x00000098) ADC Watchdog 2 Control Register */
+
+ struct {
+ __IOM uint32_t AW2CH : 20; /*!< [19..0] 模拟看门狗 2 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 2 滤波点数 */
+ uint32_t : 4;
+ } AWD2CR_b;
+ } ;
+ __IM uint32_t RESERVED5;
+
+ union {
+ __IOM uint32_t OFR0; /*!< (@ 0x000000A0) ADC Offset Register0 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 0 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR1; /*!< (@ 0x000000A4) ADC Offset Register1 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 1 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR2; /*!< (@ 0x000000A8) ADC Offset Register2 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 2 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR3; /*!< (@ 0x000000AC) ADC Offset Register3 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 3 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR3_b;
+ } ;
+ __IM uint32_t RESERVED6[4];
+
+ union {
+ __IOM uint32_t GCR0; /*!< (@ 0x000000C0) ADC Gain Coeff Register0 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 0 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR1; /*!< (@ 0x000000C4) ADC Gain Coeff Register1 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 1 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR2; /*!< (@ 0x000000C8) ADC Gain Coeff Register2 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 2 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR3; /*!< (@ 0x000000CC) ADC Gain Coeff Register3 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 3 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR3_b;
+ } ;
+ __IM uint32_t RESERVED7[12];
+
+ union {
+ __IOM uint32_t DISR; /*!< (@ 0x00000100) ADC Data Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t DON0 : 1; /*!< [0..0] 通道 0 转换完成中断标志 */
+ __IOM uint32_t DON1 : 1; /*!< [1..1] 通道 1 转换完成中断标志 */
+ __IOM uint32_t DON2 : 1; /*!< [2..2] 通道 2 转换完成中断标志 */
+ __IOM uint32_t DON3 : 1; /*!< [3..3] 通道 3 转换完成中断标志 */
+ __IOM uint32_t DON4 : 1; /*!< [4..4] 通道 4 转换完成中断标志 */
+ __IOM uint32_t DON5 : 1; /*!< [5..5] 通道 5 转换完成中断标志 */
+ __IOM uint32_t DON6 : 1; /*!< [6..6] 通道 6 转换完成中断标志 */
+ __IOM uint32_t DON7 : 1; /*!< [7..7] 通道 7 转换完成中断标志 */
+ __IOM uint32_t DON8 : 1; /*!< [8..8] 通道 8 转换完成中断标志 */
+ __IOM uint32_t DON9 : 1; /*!< [9..9] 通道 9 转换完成中断标志 */
+ __IOM uint32_t DON10 : 1; /*!< [10..10] 通道 10 转换完成中断标志 */
+ __IOM uint32_t DON11 : 1; /*!< [11..11] 通道 11 转换完成中断标志 */
+ __IOM uint32_t DON12 : 1; /*!< [12..12] 通道 12 转换完成中断标志 */
+ __IOM uint32_t DON13 : 1; /*!< [13..13] 通道 13 转换完成中断标志 */
+ __IOM uint32_t DON14 : 1; /*!< [14..14] 通道 14 转换完成中断标志 */
+ __IOM uint32_t DON15 : 1; /*!< [15..15] 通道 15 转换完成中断标志 */
+ __IOM uint32_t DON16 : 1; /*!< [16..16] 通道 16 转换完成中断标志 */
+ __IOM uint32_t DON17 : 1; /*!< [17..17] 通道 17 转换完成中断标志 */
+ __IOM uint32_t DON18 : 1; /*!< [18..18] 通道 18 转换完成中断标志 */
+ __IOM uint32_t DON19 : 1; /*!< [19..19] 通道 19 转换完成中断标志 */
+ uint32_t : 12;
+ } DISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DIER; /*!< (@ 0x00000104) ADC Data Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t DONIE0 : 1; /*!< [0..0] 通道 0 转换完成中断使能 */
+ __IOM uint32_t DONIE1 : 1; /*!< [1..1] 通道 1 转换完成中断使能 */
+ __IOM uint32_t DONIE2 : 1; /*!< [2..2] 通道 2 转换完成中断使能 */
+ __IOM uint32_t DONIE3 : 1; /*!< [3..3] 通道 3 转换完成中断使能 */
+ __IOM uint32_t DONIE4 : 1; /*!< [4..4] 通道 4 转换完成中断使能 */
+ __IOM uint32_t DONIE5 : 1; /*!< [5..5] 通道 5 转换完成中断使能 */
+ __IOM uint32_t DONIE6 : 1; /*!< [6..6] 通道 6 转换完成中断使能 */
+ __IOM uint32_t DONIE7 : 1; /*!< [7..7] 通道 7 转换完成中断使能 */
+ __IOM uint32_t DONIE8 : 1; /*!< [8..8] 通道 8 转换完成中断使能 */
+ __IOM uint32_t DONIE9 : 1; /*!< [9..9] 通道 9 转换完成中断使能 */
+ __IOM uint32_t DONIE10 : 1; /*!< [10..10] 通道 10 转换完成中断使能 */
+ __IOM uint32_t DONIE11 : 1; /*!< [11..11] 通道 11 转换完成中断使能 */
+ __IOM uint32_t DONIE12 : 1; /*!< [12..12] 通道 12 转换完成中断使能 */
+ __IOM uint32_t DONIE13 : 1; /*!< [13..13] 通道 13 转换完成中断使能 */
+ __IOM uint32_t DONIE14 : 1; /*!< [14..14] 通道 14 转换完成中断使能 */
+ __IOM uint32_t DONIE15 : 1; /*!< [15..15] 通道 15 转换完成中断使能 */
+ __IOM uint32_t DONIE16 : 1; /*!< [16..16] 通道 16 转换完成中断使能 */
+ __IOM uint32_t DONIE17 : 1; /*!< [17..17] 通道 17 转换完成中断使能 */
+ __IOM uint32_t DONIE18 : 1; /*!< [18..18] 通道 18 转换完成中断使能 */
+ __IOM uint32_t DONIE19 : 1; /*!< [19..19] 通道 19 转换完成中断使能 */
+ uint32_t : 12;
+ } DIER_b;
+ } ;
+ __IM uint32_t RESERVED8[2];
+
+ union {
+ __IOM uint32_t CDR0; /*!< (@ 0x00000110) ADC Channel Data Register0 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 0 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR1; /*!< (@ 0x00000114) ADC Channel Data Register1 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 1 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR2; /*!< (@ 0x00000118) ADC Channel Data Register2 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 2 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR3; /*!< (@ 0x0000011C) ADC Channel Data Register3 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 3 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR4; /*!< (@ 0x00000120) ADC Channel Data Register4 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 4 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR5; /*!< (@ 0x00000124) ADC Channel Data Register5 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 5 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR6; /*!< (@ 0x00000128) ADC Channel Data Register6 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 6 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR7; /*!< (@ 0x0000012C) ADC Channel Data Register7 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 7 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR8; /*!< (@ 0x00000130) ADC Channel Data Register8 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 8 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR9; /*!< (@ 0x00000134) ADC Channel Data Register9 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 9 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR10; /*!< (@ 0x00000138) ADC Channel Data Register10 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 10 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR11; /*!< (@ 0x0000013C) ADC Channel Data Register11 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 11 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR12; /*!< (@ 0x00000140) ADC Channel Data Register12 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 12 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR13; /*!< (@ 0x00000144) ADC Channel Data Register13 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 13 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR14; /*!< (@ 0x00000148) ADC Channel Data Register14 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 14 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR15; /*!< (@ 0x0000014C) ADC Channel Data Register15 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 15 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR16; /*!< (@ 0x00000150) ADC Channel Data Register16 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 16 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR17; /*!< (@ 0x00000154) ADC Channel Data Register17 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 17 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR18; /*!< (@ 0x00000158) ADC Channel Data Register18 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 18 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR19; /*!< (@ 0x0000015C) ADC Channel Data Register19 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 19 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR19_b;
+ } ;
+ __IM uint32_t RESERVED9[8];
+
+ union {
+ __IOM uint32_t HISR; /*!< (@ 0x00000180) ADC Half Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t HLF0 : 1; /*!< [0..0] 通道 0 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF1 : 1; /*!< [1..1] 通道 1 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF2 : 1; /*!< [2..2] 通道 2 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF3 : 1; /*!< [3..3] 通道 3 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF4 : 1; /*!< [4..4] 通道 4 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF5 : 1; /*!< [5..5] 通道 5 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF6 : 1; /*!< [6..6] 通道 6 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF7 : 1; /*!< [7..7] 通道 7 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF8 : 1; /*!< [8..8] 通道 8 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF9 : 1; /*!< [9..9] 通道 9 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF10 : 1; /*!< [10..10] 通道 10 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF11 : 1; /*!< [11..11] 通道 11 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF12 : 1; /*!< [12..12] 通道 12 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF13 : 1; /*!< [13..13] 通道 13 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF14 : 1; /*!< [14..14] 通道 14 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF15 : 1; /*!< [15..15] 通道 15 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF16 : 1; /*!< [16..16] 通道 16 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF17 : 1; /*!< [17..17] 通道 17 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF18 : 1; /*!< [18..18] 通道 18 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF19 : 1; /*!< [19..19] 通道 19 DMA传输半完成中断标志 */
+ uint32_t : 12;
+ } HISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t HIER; /*!< (@ 0x00000184) ADC Half Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t HLFIE0 : 1; /*!< [0..0] 通道 0 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE1 : 1; /*!< [1..1] 通道 1 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE2 : 1; /*!< [2..2] 通道 2 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE3 : 1; /*!< [3..3] 通道 3 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE4 : 1; /*!< [4..4] 通道 4 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE5 : 1; /*!< [5..5] 通道 5 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE6 : 1; /*!< [6..6] 通道 6 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE7 : 1; /*!< [7..7] 通道 7 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE8 : 1; /*!< [8..8] 通道 8 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE9 : 1; /*!< [9..9] 通道 9 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE10 : 1; /*!< [10..10] 通道 10 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE11 : 1; /*!< [11..11] 通道 11 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE12 : 1; /*!< [12..12] 通道 12 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE13 : 1; /*!< [13..13] 通道 13 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE14 : 1; /*!< [14..14] 通道 14 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE15 : 1; /*!< [15..15] 通道 15 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE16 : 1; /*!< [16..16] 通道 16 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE17 : 1; /*!< [17..17] 通道 17 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE18 : 1; /*!< [18..18] 通道 18 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE19 : 1; /*!< [19..19] 通道 19 DMA 传输半完成中断使能 */
+ uint32_t : 12;
+ } HIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t FISR; /*!< (@ 0x00000188) ADC Full Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t FUL0 : 1; /*!< [0..0] 通道 0 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL1 : 1; /*!< [1..1] 通道 1 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL2 : 1; /*!< [2..2] 通道 2 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL3 : 1; /*!< [3..3] 通道 3 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL4 : 1; /*!< [4..4] 通道 4 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL5 : 1; /*!< [5..5] 通道 5 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL6 : 1; /*!< [6..6] 通道 6 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL7 : 1; /*!< [7..7] 通道 7 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL8 : 1; /*!< [8..8] 通道 8 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL9 : 1; /*!< [9..9] 通道 9 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL10 : 1; /*!< [10..10] 通道 10 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL11 : 1; /*!< [11..11] 通道 11 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL12 : 1; /*!< [12..12] 通道 12 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL13 : 1; /*!< [13..13] 通道 13 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL14 : 1; /*!< [14..14] 通道 14 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL15 : 1; /*!< [15..15] 通道 15 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL16 : 1; /*!< [16..16] 通道 16 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL17 : 1; /*!< [17..17] 通道 17 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL18 : 1; /*!< [18..18] 通道 18 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL19 : 1; /*!< [19..19] 通道 19 DMA 传输完成中断标志 */
+ uint32_t : 12;
+ } FISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIER; /*!< (@ 0x0000018C) ADC Full Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t FULIE0 : 1; /*!< [0..0] 通道 0 传输完成中断使能 */
+ __IOM uint32_t FULIE1 : 1; /*!< [1..1] 通道 1 传输完成中断使能 */
+ __IOM uint32_t FULIE2 : 1; /*!< [2..2] 通道 2 传输完成中断使能 */
+ __IOM uint32_t FULIE3 : 1; /*!< [3..3] 通道 3 传输完成中断使能 */
+ __IOM uint32_t FULIE4 : 1; /*!< [4..4] 通道 4 传输完成中断使能 */
+ __IOM uint32_t FULIE5 : 1; /*!< [5..5] 通道 5 传输完成中断使能 */
+ __IOM uint32_t FULIE6 : 1; /*!< [6..6] 通道 6 传输完成中断使能 */
+ __IOM uint32_t FULIE7 : 1; /*!< [7..7] 通道 7 传输完成中断使能 */
+ __IOM uint32_t FULIE8 : 1; /*!< [8..8] 通道 8 传输完成中断使能 */
+ __IOM uint32_t FULIE9 : 1; /*!< [9..9] 通道 9 传输完成中断使能 */
+ __IOM uint32_t FULIE10 : 1; /*!< [10..10] 通道 10 传输完成中断使能 */
+ __IOM uint32_t FULIE11 : 1; /*!< [11..11] 通道 11 传输完成中断使能 */
+ __IOM uint32_t FULIE12 : 1; /*!< [12..12] 通道 12 传输完成中断使能 */
+ __IOM uint32_t FULIE13 : 1; /*!< [13..13] 通道 13 传输完成中断使能 */
+ __IOM uint32_t FULIE14 : 1; /*!< [14..14] 通道 14 传输完成中断使能 */
+ __IOM uint32_t FULIE15 : 1; /*!< [15..15] 通道 15 传输完成中断使能 */
+ __IOM uint32_t FULIE16 : 1; /*!< [16..16] 通道 16 传输完成中断使能 */
+ __IOM uint32_t FULIE17 : 1; /*!< [17..17] 通道 17 传输完成中断使能 */
+ __IOM uint32_t FULIE18 : 1; /*!< [18..18] 通道 18 传输完成中断使能 */
+ __IOM uint32_t FULIE19 : 1; /*!< [19..19] 通道 19 传输完成中断使能 */
+ uint32_t : 12;
+ } FIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t TCR0; /*!< (@ 0x00000190) ADC Transfer Control Register0 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR0; /*!< (@ 0x00000194) ADC Transfer Address Register0 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 0 DMA 传输的首地址 */
+ } TAR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR0; /*!< (@ 0x00000198) ADC Transfer Length Register0 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 0 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR0_b;
+ } ;
+ __IM uint32_t RESERVED10;
+
+ union {
+ __IOM uint32_t TCR1; /*!< (@ 0x000001A0) ADC Transfer Control Register1 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR1; /*!< (@ 0x000001A4) ADC Transfer Address Register1 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 1 DMA 传输的首地址 */
+ } TAR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR1; /*!< (@ 0x000001A8) ADC Transfer Length Register1 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 1 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR1_b;
+ } ;
+ __IM uint32_t RESERVED11;
+
+ union {
+ __IOM uint32_t TCR2; /*!< (@ 0x000001B0) ADC Transfer Control Register2 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR2; /*!< (@ 0x000001B4) ADC Transfer Address Register2 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 2 DMA 传输的首地址 */
+ } TAR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR2; /*!< (@ 0x000001B8) ADC Transfer Length Register2 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 2 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR2_b;
+ } ;
+ __IM uint32_t RESERVED12;
+
+ union {
+ __IOM uint32_t TCR3; /*!< (@ 0x000001C0) ADC Transfer Control Register3 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR3; /*!< (@ 0x000001C4) ADC Transfer Address Register3 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 3 DMA 传输的首地址 */
+ } TAR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR3; /*!< (@ 0x000001C8) ADC Transfer Length Register3 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 3 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR3_b;
+ } ;
+ __IM uint32_t RESERVED13;
+
+ union {
+ __IOM uint32_t TCR4; /*!< (@ 0x000001D0) ADC Transfer Control Register4 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR4; /*!< (@ 0x000001D4) ADC Transfer Address Register4 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 4 DMA 传输的首地址 */
+ } TAR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR4; /*!< (@ 0x000001D8) ADC Transfer Length Register4 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 4 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR4_b;
+ } ;
+ __IM uint32_t RESERVED14;
+
+ union {
+ __IOM uint32_t TCR5; /*!< (@ 0x000001E0) ADC Transfer Control Register5 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR5; /*!< (@ 0x000001E4) ADC Transfer Address Register5 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 5 DMA 传输的首地址 */
+ } TAR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR5; /*!< (@ 0x000001E8) ADC Transfer Length Register5 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 5 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR5_b;
+ } ;
+ __IM uint32_t RESERVED15;
+
+ union {
+ __IOM uint32_t TCR6; /*!< (@ 0x000001F0) ADC Transfer Control Register6 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR6; /*!< (@ 0x000001F4) ADC Transfer Address Register6 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 6 DMA 传输的首地址 */
+ } TAR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR6; /*!< (@ 0x000001F8) ADC Transfer Length Register6 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 6 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR6_b;
+ } ;
+ __IM uint32_t RESERVED16;
+
+ union {
+ __IOM uint32_t TCR7; /*!< (@ 0x00000200) ADC Transfer Control Register7 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR7; /*!< (@ 0x00000204) ADC Transfer Address Register7 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 7 DMA 传输的首地址 */
+ } TAR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR7; /*!< (@ 0x00000208) ADC Transfer Length Register7 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 7 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR7_b;
+ } ;
+ __IM uint32_t RESERVED17;
+
+ union {
+ __IOM uint32_t TCR8; /*!< (@ 0x00000210) ADC Transfer Control Register8 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR8; /*!< (@ 0x00000214) ADC Transfer Address Register8 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 8 DMA 传输的首地址 */
+ } TAR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR8; /*!< (@ 0x00000218) ADC Transfer Length Register8 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 8 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR8_b;
+ } ;
+ __IM uint32_t RESERVED18;
+
+ union {
+ __IOM uint32_t TCR9; /*!< (@ 0x00000220) ADC Transfer Control Register9 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR9; /*!< (@ 0x00000224) ADC Transfer Address Register9 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 9 DMA 传输的首地址 */
+ } TAR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR9; /*!< (@ 0x00000228) ADC Transfer Length Register9 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 9 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR9_b;
+ } ;
+ __IM uint32_t RESERVED19;
+
+ union {
+ __IOM uint32_t TCR10; /*!< (@ 0x00000230) ADC Transfer Control Register10 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR10; /*!< (@ 0x00000234) ADC Transfer Address Register10 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 10 DMA 传输的首地址 */
+ } TAR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR10; /*!< (@ 0x00000238) ADC Transfer Length Register10 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 10 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR10_b;
+ } ;
+ __IM uint32_t RESERVED20;
+
+ union {
+ __IOM uint32_t TCR11; /*!< (@ 0x00000240) ADC Transfer Control Register11 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR11; /*!< (@ 0x00000244) ADC Transfer Address Register11 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 11 DMA 传输的首地址 */
+ } TAR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR11; /*!< (@ 0x00000248) ADC Transfer Length Register11 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 11 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR11_b;
+ } ;
+ __IM uint32_t RESERVED21;
+
+ union {
+ __IOM uint32_t TCR12; /*!< (@ 0x00000250) ADC Transfer Control Register12 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR12; /*!< (@ 0x00000254) ADC Transfer Address Register12 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 12 DMA 传输的首地址 */
+ } TAR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR12; /*!< (@ 0x00000258) ADC Transfer Length Register12 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 12 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR12_b;
+ } ;
+ __IM uint32_t RESERVED22;
+
+ union {
+ __IOM uint32_t TCR13; /*!< (@ 0x00000260) ADC Transfer Control Register13 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR13; /*!< (@ 0x00000264) ADC Transfer Address Register13 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 13 DMA 传输的首地址 */
+ } TAR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR13; /*!< (@ 0x00000268) ADC Transfer Length Register13 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 13 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR13_b;
+ } ;
+ __IM uint32_t RESERVED23;
+
+ union {
+ __IOM uint32_t TCR14; /*!< (@ 0x00000270) ADC Transfer Control Register14 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR14; /*!< (@ 0x00000274) ADC Transfer Address Register14 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 14 DMA 传输的首地址 */
+ } TAR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR14; /*!< (@ 0x00000278) ADC Transfer Length Register14 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 14 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR14_b;
+ } ;
+ __IM uint32_t RESERVED24;
+
+ union {
+ __IOM uint32_t TCR15; /*!< (@ 0x00000280) ADC Transfer Control Register15 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR15; /*!< (@ 0x00000284) ADC Transfer Address Register15 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 15 DMA 传输的首地址 */
+ } TAR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR15; /*!< (@ 0x00000288) ADC Transfer Length Register15 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 15 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR15_b;
+ } ;
+ __IM uint32_t RESERVED25;
+
+ union {
+ __IOM uint32_t TCR16; /*!< (@ 0x00000290) ADC Transfer Control Register16 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR16; /*!< (@ 0x00000294) ADC Transfer Address Register16 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 16 DMA 传输的首地址 */
+ } TAR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR16; /*!< (@ 0x00000298) ADC Transfer Length Register16 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 16 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR16_b;
+ } ;
+ __IM uint32_t RESERVED26;
+
+ union {
+ __IOM uint32_t TCR17; /*!< (@ 0x000002A0) ADC Transfer Control Register17 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR17; /*!< (@ 0x000002A4) ADC Transfer Address Register17 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 17 DMA 传输的首地址 */
+ } TAR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR17; /*!< (@ 0x000002A8) ADC Transfer Length Register17 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 17 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR17_b;
+ } ;
+ __IM uint32_t RESERVED27;
+
+ union {
+ __IOM uint32_t TCR18; /*!< (@ 0x000002B0) ADC Transfer Control Register18 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR18; /*!< (@ 0x000002B4) ADC Transfer Address Register18 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 18 DMA 传输的首地址 */
+ } TAR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR18; /*!< (@ 0x000002B8) ADC Transfer Length Register18 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 18 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR18_b;
+ } ;
+ __IM uint32_t RESERVED28;
+
+ union {
+ __IOM uint32_t TCR19; /*!< (@ 0x000002C0) ADC Transfer Control Register19 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR19_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR19; /*!< (@ 0x000002C4) ADC Transfer Address Register19 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 19 DMA 传输的首地址 */
+ } TAR19_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR19; /*!< (@ 0x000002C8) ADC Transfer Length Register19 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 19 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR19_b;
+ } ;
+ __IM uint32_t RESERVED29[13];
+
+ union {
+ __IOM uint32_t CCR; /*!< (@ 0x00000300) ADC Common Control Registe */
+
+ struct {
+ __IOM uint32_t DUAL : 4; /*!< [3..0] ADC DUAL模式选择（仅Master ADC配置有效） */
+ uint32_t : 4;
+ __IOM uint32_t DELAY : 10; /*!< [17..8] ADC DUAL采样相位延迟（仅Master ADC配置有效） */
+ uint32_t : 14;
+ } CCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CSR; /*!< (@ 0x00000304) ADC Common Status Register */
+
+ struct {
+ __IM uint32_t EOC_MST : 1; /*!< [0..0] 常规转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOS_MST : 1; /*!< [1..1] 常规序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOC_MST : 1; /*!< [2..2] 注入转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOS_MST : 1; /*!< [3..3] 注入序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t OVR_MST : 1; /*!< [4..4] ADC 数据溢出中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD0_MST : 1; /*!< [5..5] 模拟看门狗 0 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD1_MST : 1; /*!< [6..6] 模拟看门狗 1 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD2_MST : 1; /*!< [7..7] 模拟看门狗 2 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t ADRDY_MST : 1; /*!< [8..8] ADC 就绪中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOSMP_MST : 1; /*!< [9..9] 采样阶段结束中断标志（仅Master ADC读取有效） */
+ uint32_t : 6;
+ __IM uint32_t EOC_SLV : 1; /*!< [16..16] 常规转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOS_SLV : 1; /*!< [17..17] 常规序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOC_SLV : 1; /*!< [18..18] 注入转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOS_SLV : 1; /*!< [19..19] 注入序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t OVR_SLV : 1; /*!< [20..20] ADC 数据溢出中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD0_SLV : 1; /*!< [21..21] 模拟看门狗 0 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD1_SLV : 1; /*!< [22..22] 模拟看门狗 1 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD2_SLV : 1; /*!< [23..23] 模拟看门狗 2 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t ADRDY_SLV : 1; /*!< [24..24] ADC 就绪中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOSMP_SLV : 1; /*!< [25..25] 采样阶段结束中断标志（仅Master ADC读取有效） */
+ uint32_t : 6;
+ } CSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR; /*!< (@ 0x00000308) ADC Common Regular Data Register */
+
+ struct {
+ __IM uint32_t RDATA_MST : 16; /*!< [15..0] Master ADC 常规序列已转换的数据（仅Master
+ ADC读取有效） */
+ __IM uint32_t RDATA_SLV : 16; /*!< [31..16] Slave ADC 常规序列已转换的数据（仅Master
+ ADC读取有效） */
+ } CDR_b;
+ } ;
+} ADC1_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ADC2 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief ADC2 (ADC2)
+ */
+
+typedef struct { /*!< (@ 0x40038800) ADC2 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) ADC Control Register */
+
+ struct {
+ __IOM uint32_t ADEN : 1; /*!< [0..0] ADC 开始模块使能命令 */
+ __IOM uint32_t ADDIS : 1; /*!< [1..1] ADC 停止模块使能命令 */
+ __IOM uint32_t ADSTART : 1; /*!< [2..2] ADC 开始常规转换命令 */
+ __IOM uint32_t JADSTART : 1; /*!< [3..3] ADC 开始注入转换命令 */
+ __IOM uint32_t ADSTP : 1; /*!< [4..4] ADC 停止常规转换命令 */
+ __IOM uint32_t JADSTP : 1; /*!< [5..5] ADC 停止注入转换命令 */
+ __IOM uint32_t ADCAL : 1; /*!< [6..6] ADC 启动校准命令 */
+ __IOM uint32_t ADCALDIF : 1; /*!< [7..7] ADC 校准模式选择 */
+ uint32_t : 24;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFGR0; /*!< (@ 0x00000004) ADC Configuration Register0 */
+
+ struct {
+ __IOM uint32_t ROVSE : 1; /*!< [0..0] 规则序列过采样使能 */
+ __IOM uint32_t JOVSE : 1; /*!< [1..1] 注入序列过采样使能 */
+ uint32_t : 2;
+ __IOM uint32_t OVSR : 3; /*!< [6..4] 过采样数据叠加比率 */
+ __IOM uint32_t ROVSM : 1; /*!< [7..7] 常规通道的过采样模式 */
+ __IOM uint32_t OVSS : 4; /*!< [11..8] 过采样数据移位位数 */
+ __IOM uint32_t TROVS : 1; /*!< [12..12] 触发式规则序列过采样使能 */
+ uint32_t : 1;
+ __IOM uint32_t SDMAEN : 1; /*!< [14..14] 系统DMA请求使能 */
+ __IOM uint32_t OVRMOD : 1; /*!< [15..15] 数据溢出模式 */
+ __IOM uint32_t DISCEN : 1; /*!< [16..16] 常规序列的单次／不连续转换模式 */
+ __IOM uint32_t DISCNUM : 3; /*!< [19..17] 不连续采样模式通道计数 */
+ __IOM uint32_t JDISCEN : 1; /*!< [20..20] 注入序列的不连续采样模式 */
+ uint32_t : 1;
+ __IOM uint32_t JAUTO : 1; /*!< [22..22] 注入序列自动转换 */
+ __IOM uint32_t CONT : 1; /*!< [23..23] 常规序列的单次／连续转换模式 */
+ uint32_t : 4;
+ __IOM uint32_t OVSCAL : 3; /*!< [30..28] 自动校准数据叠加比率 */
+ uint32_t : 1;
+ } CFGR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFGR1; /*!< (@ 0x00000008) ADC Configuration Register1 */
+
+ struct {
+ __IOM uint32_t BIASEN : 1; /*!< [0..0] 内部偏置模块使能 */
+ __IOM uint32_t REFEN : 1; /*!< [1..1] Reference模块使能 */
+ uint32_t : 1;
+ __IOM uint32_t CHEN : 1; /*!< [3..3] 通道使能 */
+ __IOM uint32_t ISEL : 2; /*!< [5..4] 偏置电流档位 */
+ uint32_t : 2;
+ __IOM uint32_t AWD0EN : 1; /*!< [8..8] 模拟看门狗 0 监测规则序列 */
+ __IOM uint32_t AWD1EN : 1; /*!< [9..9] 模拟看门狗 1 监测规则序列 */
+ __IOM uint32_t AWD2EN : 1; /*!< [10..10] 模拟看门狗 2 监测规则序列 */
+ uint32_t : 1;
+ __IOM uint32_t JAWD0EN : 1; /*!< [12..12] 模拟看门狗 0 监测注入序列 */
+ __IOM uint32_t JAWD1EN : 1; /*!< [13..13] 模拟看门狗 1 监测注入序列 */
+ __IOM uint32_t JAWD2EN : 1; /*!< [14..14] 模拟看门狗 2 监测注入序列 */
+ uint32_t : 17;
+ } CFGR1_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) ADC Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t EOC : 1; /*!< [0..0] 常规转换结束中断标志 */
+ __IOM uint32_t EOS : 1; /*!< [1..1] 常规序列结束中断标志 */
+ __IOM uint32_t JEOC : 1; /*!< [2..2] 注入转换结束中断标志 */
+ __IOM uint32_t JEOS : 1; /*!< [3..3] 注入序列结束中断标志 */
+ __IOM uint32_t OVR : 1; /*!< [4..4] ADC 数据溢出中断标志 */
+ __IOM uint32_t AWD0 : 1; /*!< [5..5] 模拟看门狗 0 中断标志 */
+ __IOM uint32_t AWD1 : 1; /*!< [6..6] 模拟看门狗 1 中断标志 */
+ __IOM uint32_t AWD2 : 1; /*!< [7..7] 模拟看门狗 2 中断标志 */
+ __IOM uint32_t ADRDY : 1; /*!< [8..8] ADC 就绪中断标志 */
+ __IOM uint32_t EOSMP : 1; /*!< [9..9] 采样阶段结束中断标志 */
+ uint32_t : 22;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000014) ADC Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t EOCIE : 1; /*!< [0..0] 常规转换结束中断使能 */
+ __IOM uint32_t EOSIE : 1; /*!< [1..1] 常规序列结束中断使能 */
+ __IOM uint32_t JEOCIE : 1; /*!< [2..2] 注入转换结束中断使能 */
+ __IOM uint32_t JEOSIE : 1; /*!< [3..3] 注入序列结束中断使能 */
+ __IOM uint32_t OVRIE : 1; /*!< [4..4] ADC 数据溢出中断使能 */
+ __IOM uint32_t AWD0IE : 1; /*!< [5..5] 模拟看门狗 0 中断使能 */
+ __IOM uint32_t AWD1IE : 1; /*!< [6..6] 模拟看门狗 1 中断使能 */
+ __IOM uint32_t AWD2IE : 1; /*!< [7..7] 模拟看门狗 2 中断使能 */
+ __IOM uint32_t ADRDYIE : 1; /*!< [8..8] ADC 就绪中断使能 */
+ __IOM uint32_t EOSMPIE : 1; /*!< [9..9] 采样阶段结束中断使能 */
+ uint32_t : 22;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIGSEL; /*!< (@ 0x00000018) ADC Single-End Select Register */
+
+ struct {
+ __IOM uint32_t SIGSEL : 20; /*!< [19..0] ADC 通道转换模式选择 */
+ uint32_t : 12;
+ } SIGSEL_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t SMPR0; /*!< (@ 0x00000020) ADC Sample Time Register 0 */
+
+ struct {
+ __IOM uint32_t SMP0 : 3; /*!< [2..0] 通道 0 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP1 : 3; /*!< [6..4] 通道 1 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP2 : 3; /*!< [10..8] 通道 2 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP3 : 3; /*!< [14..12] 通道 3 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP4 : 3; /*!< [18..16] 通道 4 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP5 : 3; /*!< [22..20] 通道 5 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP6 : 3; /*!< [26..24] 通道 6 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP7 : 3; /*!< [30..28] 通道 7 采样时间选择位 */
+ uint32_t : 1;
+ } SMPR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t SMPR1; /*!< (@ 0x00000024) ADC Sample Time Register 1 */
+
+ struct {
+ __IOM uint32_t SMP8 : 3; /*!< [2..0] 通道 8 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP9 : 3; /*!< [6..4] 通道 9 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP10 : 3; /*!< [10..8] 通道 10 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP11 : 3; /*!< [14..12] 通道 11 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP12 : 3; /*!< [18..16] 通道 12 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP13 : 3; /*!< [22..20] 通道 13 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP14 : 3; /*!< [26..24] 通道 14 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP15 : 3; /*!< [30..28] 通道 15 采样时间选择位 */
+ uint32_t : 1;
+ } SMPR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SMPR2; /*!< (@ 0x00000028) ADC Sample Time Register 2 */
+
+ struct {
+ __IOM uint32_t SMP16 : 3; /*!< [2..0] 通道 16 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP17 : 3; /*!< [6..4] 通道 17 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP18 : 3; /*!< [10..8] 通道 18 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP19 : 3; /*!< [14..12] 通道 19 采样时间选择位 */
+ uint32_t : 17;
+ } SMPR2_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t CALR0; /*!< (@ 0x00000030) ADC Calibration Data Register 0 */
+
+ struct {
+ __IOM uint32_t CAL0 : 2; /*!< [1..0] 通道 0 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT0 : 1; /*!< [3..3] 通道 0 饱和运算选择位 */
+ __IOM uint32_t CAL1 : 2; /*!< [5..4] 通道 1 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT1 : 1; /*!< [7..7] 通道 1 饱和运算选择位 */
+ __IOM uint32_t CAL2 : 2; /*!< [9..8] 通道 2 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT2 : 1; /*!< [11..11] 通道 2 饱和运算选择位 */
+ __IOM uint32_t CAL3 : 2; /*!< [13..12] 通道 3 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT3 : 1; /*!< [15..15] 通道 3 饱和运算选择位 */
+ __IOM uint32_t CAL4 : 2; /*!< [17..16] 通道 4 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT4 : 1; /*!< [19..19] 通道 4 饱和运算选择位 */
+ __IOM uint32_t CAL5 : 2; /*!< [21..20] 通道 5 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT5 : 1; /*!< [23..23] 通道 5 饱和运算选择位 */
+ __IOM uint32_t CAL6 : 2; /*!< [25..24] 通道 6 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT6 : 1; /*!< [27..27] 通道 6 饱和运算选择位 */
+ __IOM uint32_t CAL7 : 2; /*!< [29..28] 通道 7 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT7 : 1; /*!< [31..31] 通道 7 饱和运算选择位 */
+ } CALR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CALR1; /*!< (@ 0x00000034) ADC Calibration Data Register 1 */
+
+ struct {
+ __IOM uint32_t CAL8 : 2; /*!< [1..0] 通道 8 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT8 : 1; /*!< [3..3] 通道 8 饱和运算选择位 */
+ __IOM uint32_t CAL9 : 2; /*!< [5..4] 通道 9 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT9 : 1; /*!< [7..7] 通道 9 饱和运算选择位 */
+ __IOM uint32_t CAL10 : 2; /*!< [9..8] 通道 10 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT10 : 1; /*!< [11..11] 通道 10 饱和运算选择位 */
+ __IOM uint32_t CAL11 : 2; /*!< [13..12] 通道 11 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT11 : 1; /*!< [15..15] 通道 11 饱和运算选择位 */
+ __IOM uint32_t CAL12 : 2; /*!< [17..16] 通道 12 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT12 : 1; /*!< [19..19] 通道 12 饱和运算选择位 */
+ __IOM uint32_t CAL13 : 2; /*!< [21..20] 通道 13 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT13 : 1; /*!< [23..23] 通道 13 饱和运算选择位 */
+ __IOM uint32_t CAL14 : 2; /*!< [25..24] 通道 14 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT14 : 1; /*!< [27..27] 通道 14 饱和运算选择位 */
+ __IOM uint32_t CAL15 : 2; /*!< [29..28] 通道 15 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT15 : 1; /*!< [31..31] 通道 15 饱和运算选择位 */
+ } CALR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t CALR2; /*!< (@ 0x00000038) ADC Calibration Data Register 2 */
+
+ struct {
+ __IOM uint32_t CAL16 : 2; /*!< [1..0] 通道 16 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT16 : 1; /*!< [3..3] 通道 16 饱和运算选择位 */
+ __IOM uint32_t CAL17 : 2; /*!< [5..4] 通道 17 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT17 : 1; /*!< [7..7] 通道 17 饱和运算选择位 */
+ __IOM uint32_t CAL18 : 2; /*!< [9..8] 通道 18 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT18 : 1; /*!< [11..11] 通道 18 饱和运算选择位 */
+ __IOM uint32_t CAL19 : 2; /*!< [13..12] 通道 19 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT19 : 1; /*!< [15..15] 通道 19 饱和运算选择位 */
+ uint32_t : 16;
+ } CALR2_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t SQR0; /*!< (@ 0x00000040) ADC Regular Sequence Register0 */
+
+ struct {
+ __IOM uint32_t SQ1 : 5; /*!< [4..0] 常规序列中的第 1 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ2 : 5; /*!< [10..6] 常规序列中的第 2 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ3 : 5; /*!< [16..12] 常规序列中的第 3 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ4 : 5; /*!< [22..18] 常规序列中的第 4 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ5 : 5; /*!< [28..24] 常规序列中的第 5 次转换 */
+ uint32_t : 3;
+ } SQR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR1; /*!< (@ 0x00000044) ADC Regular Sequence Register1 */
+
+ struct {
+ __IOM uint32_t SQ6 : 5; /*!< [4..0] 常规序列中的第 6 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ7 : 5; /*!< [10..6] 常规序列中的第 7 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ8 : 5; /*!< [16..12] 常规序列中的第 8 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ9 : 5; /*!< [22..18] 常规序列中的第 9 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ10 : 5; /*!< [28..24] 常规序列中的第 10 次转换 */
+ uint32_t : 3;
+ } SQR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR2; /*!< (@ 0x00000048) ADC Regular Sequence Register2 */
+
+ struct {
+ __IOM uint32_t SQ11 : 5; /*!< [4..0] 常规序列中的第 11 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ12 : 5; /*!< [10..6] 常规序列中的第 12 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ13 : 5; /*!< [16..12] 常规序列中的第 13 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ14 : 5; /*!< [22..18] 常规序列中的第 14 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ15 : 5; /*!< [28..24] 常规序列中的第 15 次转换 */
+ uint32_t : 3;
+ } SQR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR3; /*!< (@ 0x0000004C) ADC Regular Sequence Register3 */
+
+ struct {
+ __IOM uint32_t SQ16 : 5; /*!< [4..0] 常规序列中的第 16 次转换 */
+ uint32_t : 27;
+ } SQR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t LR; /*!< (@ 0x00000050) ADC Regular Length Register */
+
+ struct {
+ __IOM uint32_t EXTSEL : 5; /*!< [4..0] 常规序列的硬件触发选择 */
+ uint32_t : 1;
+ __IOM uint32_t EXTEN : 2; /*!< [7..6] 常规序列的硬件触发使能和极性选择 */
+ __IOM uint32_t LEN : 4; /*!< [11..8] 常规序列的长度 */
+ uint32_t : 20;
+ } LR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DR; /*!< (@ 0x00000054) ADC Regular Data Register */
+
+ struct {
+ __IOM uint32_t RDATA : 16; /*!< [15..0] 常规序列已转换的数据 */
+ uint32_t : 16;
+ } DR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MAXDR; /*!< (@ 0x00000058) ADC Maximum Regular Data Register */
+
+ struct {
+ __IOM uint32_t MAXDATA : 16; /*!< [15..0] 常规序列数据饱和运算最大值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MAXDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MINDR; /*!< (@ 0x0000005C) ADC Minimum Regular Data Register */
+
+ struct {
+ __IOM uint32_t MINDATA : 16; /*!< [15..0] 常规序列数据饱和运算最小值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MINDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JSQR; /*!< (@ 0x00000060) ADC Injected Sequence Register */
+
+ struct {
+ __IOM uint32_t JSQ1 : 5; /*!< [4..0] 注入序列中的第 1 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ2 : 5; /*!< [10..6] 注入序列中的第 2 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ3 : 5; /*!< [16..12] 注入序列中的第 3 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ4 : 5; /*!< [22..18] 注入序列中的第 4 次转换 */
+ uint32_t : 9;
+ } JSQR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JLR; /*!< (@ 0x00000064) ADC Injected Length Register */
+
+ struct {
+ __IOM uint32_t JEXTSEL : 5; /*!< [4..0] 注入序列的硬件触发选择 */
+ uint32_t : 1;
+ __IOM uint32_t JEXTEN : 2; /*!< [7..6] 注入序列的硬件触发使能和极性选择 */
+ __IOM uint32_t JLEN : 2; /*!< [9..8] 注入序列的长度 */
+ uint32_t : 22;
+ } JLR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MAXJDR; /*!< (@ 0x00000068) ADC Maximum Injected Data Register */
+
+ struct {
+ __IOM uint32_t MAXDATA : 16; /*!< [15..0] 注入序列数据饱和运算最大值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MAXJDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MINJDR; /*!< (@ 0x0000006C) ADC Minimum Injected Data Register */
+
+ struct {
+ __IOM uint32_t MINDATA : 16; /*!< [15..0] 注入序列数据饱和运算最小值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MINJDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR0; /*!< (@ 0x00000070) ADC Injected Data Register0 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 0 个已转换数据 */
+ uint32_t : 16;
+ } JDR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR1; /*!< (@ 0x00000074) ADC Injected Data Register1 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 1 个已转换数据 */
+ uint32_t : 16;
+ } JDR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR2; /*!< (@ 0x00000078) ADC Injected Data Register2 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 2 个已转换数据 */
+ uint32_t : 16;
+ } JDR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR3; /*!< (@ 0x0000007C) ADC Injected Data Register3 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 3 个已转换数据 */
+ uint32_t : 16;
+ } JDR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR0; /*!< (@ 0x00000080) ADC Watchdog0 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT0 : 16; /*!< [15..0] 模拟看门狗 0 阈值下限 */
+ __IOM uint32_t HT0 : 16; /*!< [31..16] 模拟看门狗 0 阈值上限 */
+ } TR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR1; /*!< (@ 0x00000084) ADC Watchdog1 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT1 : 16; /*!< [15..0] 模拟看门狗 1 阈值下限 */
+ __IOM uint32_t HT1 : 16; /*!< [31..16] 模拟看门狗 1 阈值上限 */
+ } TR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR2; /*!< (@ 0x00000088) ADC Watchdog2 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT2 : 16; /*!< [15..0] 模拟看门狗 2 阈值下限 */
+ __IOM uint32_t HT2 : 16; /*!< [31..16] 模拟看门狗 2 阈值上限 */
+ } TR2_b;
+ } ;
+ __IM uint32_t RESERVED4;
+
+ union {
+ __IOM uint32_t AWD0CR; /*!< (@ 0x00000090) ADC Watchdog0 Control Register */
+
+ struct {
+ __IOM uint32_t AW0CH : 20; /*!< [19..0] 模拟看门狗 0 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 0 滤波点数 */
+ uint32_t : 4;
+ } AWD0CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AWD1CR; /*!< (@ 0x00000094) ADC Watchdog1 Control Register */
+
+ struct {
+ __IOM uint32_t AW1CH : 20; /*!< [19..0] 模拟看门狗 1 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 1 滤波点数 */
+ uint32_t : 4;
+ } AWD1CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AWD2CR; /*!< (@ 0x00000098) ADC Watchdog 2 Control Register */
+
+ struct {
+ __IOM uint32_t AW2CH : 20; /*!< [19..0] 模拟看门狗 2 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 2 滤波点数 */
+ uint32_t : 4;
+ } AWD2CR_b;
+ } ;
+ __IM uint32_t RESERVED5;
+
+ union {
+ __IOM uint32_t OFR0; /*!< (@ 0x000000A0) ADC Offset Register0 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 0 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR1; /*!< (@ 0x000000A4) ADC Offset Register1 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 1 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR2; /*!< (@ 0x000000A8) ADC Offset Register2 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 2 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR3; /*!< (@ 0x000000AC) ADC Offset Register3 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 3 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR3_b;
+ } ;
+ __IM uint32_t RESERVED6[4];
+
+ union {
+ __IOM uint32_t GCR0; /*!< (@ 0x000000C0) ADC Gain Coeff Register0 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 0 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR1; /*!< (@ 0x000000C4) ADC Gain Coeff Register1 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 1 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR2; /*!< (@ 0x000000C8) ADC Gain Coeff Register2 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 2 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR3; /*!< (@ 0x000000CC) ADC Gain Coeff Register3 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 3 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR3_b;
+ } ;
+ __IM uint32_t RESERVED7[12];
+
+ union {
+ __IOM uint32_t DISR; /*!< (@ 0x00000100) ADC Data Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t DON0 : 1; /*!< [0..0] 通道 0 转换完成中断标志 */
+ __IOM uint32_t DON1 : 1; /*!< [1..1] 通道 1 转换完成中断标志 */
+ __IOM uint32_t DON2 : 1; /*!< [2..2] 通道 2 转换完成中断标志 */
+ __IOM uint32_t DON3 : 1; /*!< [3..3] 通道 3 转换完成中断标志 */
+ __IOM uint32_t DON4 : 1; /*!< [4..4] 通道 4 转换完成中断标志 */
+ __IOM uint32_t DON5 : 1; /*!< [5..5] 通道 5 转换完成中断标志 */
+ __IOM uint32_t DON6 : 1; /*!< [6..6] 通道 6 转换完成中断标志 */
+ __IOM uint32_t DON7 : 1; /*!< [7..7] 通道 7 转换完成中断标志 */
+ __IOM uint32_t DON8 : 1; /*!< [8..8] 通道 8 转换完成中断标志 */
+ __IOM uint32_t DON9 : 1; /*!< [9..9] 通道 9 转换完成中断标志 */
+ __IOM uint32_t DON10 : 1; /*!< [10..10] 通道 10 转换完成中断标志 */
+ __IOM uint32_t DON11 : 1; /*!< [11..11] 通道 11 转换完成中断标志 */
+ __IOM uint32_t DON12 : 1; /*!< [12..12] 通道 12 转换完成中断标志 */
+ __IOM uint32_t DON13 : 1; /*!< [13..13] 通道 13 转换完成中断标志 */
+ __IOM uint32_t DON14 : 1; /*!< [14..14] 通道 14 转换完成中断标志 */
+ __IOM uint32_t DON15 : 1; /*!< [15..15] 通道 15 转换完成中断标志 */
+ __IOM uint32_t DON16 : 1; /*!< [16..16] 通道 16 转换完成中断标志 */
+ __IOM uint32_t DON17 : 1; /*!< [17..17] 通道 17 转换完成中断标志 */
+ __IOM uint32_t DON18 : 1; /*!< [18..18] 通道 18 转换完成中断标志 */
+ __IOM uint32_t DON19 : 1; /*!< [19..19] 通道 19 转换完成中断标志 */
+ uint32_t : 12;
+ } DISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DIER; /*!< (@ 0x00000104) ADC Data Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t DONIE0 : 1; /*!< [0..0] 通道 0 转换完成中断使能 */
+ __IOM uint32_t DONIE1 : 1; /*!< [1..1] 通道 1 转换完成中断使能 */
+ __IOM uint32_t DONIE2 : 1; /*!< [2..2] 通道 2 转换完成中断使能 */
+ __IOM uint32_t DONIE3 : 1; /*!< [3..3] 通道 3 转换完成中断使能 */
+ __IOM uint32_t DONIE4 : 1; /*!< [4..4] 通道 4 转换完成中断使能 */
+ __IOM uint32_t DONIE5 : 1; /*!< [5..5] 通道 5 转换完成中断使能 */
+ __IOM uint32_t DONIE6 : 1; /*!< [6..6] 通道 6 转换完成中断使能 */
+ __IOM uint32_t DONIE7 : 1; /*!< [7..7] 通道 7 转换完成中断使能 */
+ __IOM uint32_t DONIE8 : 1; /*!< [8..8] 通道 8 转换完成中断使能 */
+ __IOM uint32_t DONIE9 : 1; /*!< [9..9] 通道 9 转换完成中断使能 */
+ __IOM uint32_t DONIE10 : 1; /*!< [10..10] 通道 10 转换完成中断使能 */
+ __IOM uint32_t DONIE11 : 1; /*!< [11..11] 通道 11 转换完成中断使能 */
+ __IOM uint32_t DONIE12 : 1; /*!< [12..12] 通道 12 转换完成中断使能 */
+ __IOM uint32_t DONIE13 : 1; /*!< [13..13] 通道 13 转换完成中断使能 */
+ __IOM uint32_t DONIE14 : 1; /*!< [14..14] 通道 14 转换完成中断使能 */
+ __IOM uint32_t DONIE15 : 1; /*!< [15..15] 通道 15 转换完成中断使能 */
+ __IOM uint32_t DONIE16 : 1; /*!< [16..16] 通道 16 转换完成中断使能 */
+ __IOM uint32_t DONIE17 : 1; /*!< [17..17] 通道 17 转换完成中断使能 */
+ __IOM uint32_t DONIE18 : 1; /*!< [18..18] 通道 18 转换完成中断使能 */
+ __IOM uint32_t DONIE19 : 1; /*!< [19..19] 通道 19 转换完成中断使能 */
+ uint32_t : 12;
+ } DIER_b;
+ } ;
+ __IM uint32_t RESERVED8[2];
+
+ union {
+ __IOM uint32_t CDR0; /*!< (@ 0x00000110) ADC Channel Data Register0 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 0 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR1; /*!< (@ 0x00000114) ADC Channel Data Register1 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 1 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR2; /*!< (@ 0x00000118) ADC Channel Data Register2 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 2 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR3; /*!< (@ 0x0000011C) ADC Channel Data Register3 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 3 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR4; /*!< (@ 0x00000120) ADC Channel Data Register4 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 4 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR5; /*!< (@ 0x00000124) ADC Channel Data Register5 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 5 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR6; /*!< (@ 0x00000128) ADC Channel Data Register6 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 6 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR7; /*!< (@ 0x0000012C) ADC Channel Data Register7 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 7 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR8; /*!< (@ 0x00000130) ADC Channel Data Register8 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 8 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR9; /*!< (@ 0x00000134) ADC Channel Data Register9 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 9 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR10; /*!< (@ 0x00000138) ADC Channel Data Register10 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 10 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR11; /*!< (@ 0x0000013C) ADC Channel Data Register11 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 11 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR12; /*!< (@ 0x00000140) ADC Channel Data Register12 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 12 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR13; /*!< (@ 0x00000144) ADC Channel Data Register13 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 13 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR14; /*!< (@ 0x00000148) ADC Channel Data Register14 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 14 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR15; /*!< (@ 0x0000014C) ADC Channel Data Register15 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 15 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR16; /*!< (@ 0x00000150) ADC Channel Data Register16 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 16 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR17; /*!< (@ 0x00000154) ADC Channel Data Register17 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 17 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR18; /*!< (@ 0x00000158) ADC Channel Data Register18 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 18 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR19; /*!< (@ 0x0000015C) ADC Channel Data Register19 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 19 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR19_b;
+ } ;
+ __IM uint32_t RESERVED9[8];
+
+ union {
+ __IOM uint32_t HISR; /*!< (@ 0x00000180) ADC Half Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t HLF0 : 1; /*!< [0..0] 通道 0 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF1 : 1; /*!< [1..1] 通道 1 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF2 : 1; /*!< [2..2] 通道 2 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF3 : 1; /*!< [3..3] 通道 3 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF4 : 1; /*!< [4..4] 通道 4 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF5 : 1; /*!< [5..5] 通道 5 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF6 : 1; /*!< [6..6] 通道 6 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF7 : 1; /*!< [7..7] 通道 7 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF8 : 1; /*!< [8..8] 通道 8 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF9 : 1; /*!< [9..9] 通道 9 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF10 : 1; /*!< [10..10] 通道 10 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF11 : 1; /*!< [11..11] 通道 11 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF12 : 1; /*!< [12..12] 通道 12 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF13 : 1; /*!< [13..13] 通道 13 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF14 : 1; /*!< [14..14] 通道 14 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF15 : 1; /*!< [15..15] 通道 15 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF16 : 1; /*!< [16..16] 通道 16 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF17 : 1; /*!< [17..17] 通道 17 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF18 : 1; /*!< [18..18] 通道 18 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF19 : 1; /*!< [19..19] 通道 19 DMA传输半完成中断标志 */
+ uint32_t : 12;
+ } HISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t HIER; /*!< (@ 0x00000184) ADC Half Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t HLFIE0 : 1; /*!< [0..0] 通道 0 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE1 : 1; /*!< [1..1] 通道 1 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE2 : 1; /*!< [2..2] 通道 2 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE3 : 1; /*!< [3..3] 通道 3 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE4 : 1; /*!< [4..4] 通道 4 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE5 : 1; /*!< [5..5] 通道 5 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE6 : 1; /*!< [6..6] 通道 6 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE7 : 1; /*!< [7..7] 通道 7 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE8 : 1; /*!< [8..8] 通道 8 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE9 : 1; /*!< [9..9] 通道 9 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE10 : 1; /*!< [10..10] 通道 10 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE11 : 1; /*!< [11..11] 通道 11 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE12 : 1; /*!< [12..12] 通道 12 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE13 : 1; /*!< [13..13] 通道 13 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE14 : 1; /*!< [14..14] 通道 14 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE15 : 1; /*!< [15..15] 通道 15 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE16 : 1; /*!< [16..16] 通道 16 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE17 : 1; /*!< [17..17] 通道 17 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE18 : 1; /*!< [18..18] 通道 18 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE19 : 1; /*!< [19..19] 通道 19 DMA 传输半完成中断使能 */
+ uint32_t : 12;
+ } HIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t FISR; /*!< (@ 0x00000188) ADC Full Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t FUL0 : 1; /*!< [0..0] 通道 0 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL1 : 1; /*!< [1..1] 通道 1 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL2 : 1; /*!< [2..2] 通道 2 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL3 : 1; /*!< [3..3] 通道 3 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL4 : 1; /*!< [4..4] 通道 4 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL5 : 1; /*!< [5..5] 通道 5 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL6 : 1; /*!< [6..6] 通道 6 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL7 : 1; /*!< [7..7] 通道 7 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL8 : 1; /*!< [8..8] 通道 8 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL9 : 1; /*!< [9..9] 通道 9 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL10 : 1; /*!< [10..10] 通道 10 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL11 : 1; /*!< [11..11] 通道 11 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL12 : 1; /*!< [12..12] 通道 12 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL13 : 1; /*!< [13..13] 通道 13 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL14 : 1; /*!< [14..14] 通道 14 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL15 : 1; /*!< [15..15] 通道 15 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL16 : 1; /*!< [16..16] 通道 16 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL17 : 1; /*!< [17..17] 通道 17 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL18 : 1; /*!< [18..18] 通道 18 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL19 : 1; /*!< [19..19] 通道 19 DMA 传输完成中断标志 */
+ uint32_t : 12;
+ } FISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIER; /*!< (@ 0x0000018C) ADC Full Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t FULIE0 : 1; /*!< [0..0] 通道 0 传输完成中断使能 */
+ __IOM uint32_t FULIE1 : 1; /*!< [1..1] 通道 1 传输完成中断使能 */
+ __IOM uint32_t FULIE2 : 1; /*!< [2..2] 通道 2 传输完成中断使能 */
+ __IOM uint32_t FULIE3 : 1; /*!< [3..3] 通道 3 传输完成中断使能 */
+ __IOM uint32_t FULIE4 : 1; /*!< [4..4] 通道 4 传输完成中断使能 */
+ __IOM uint32_t FULIE5 : 1; /*!< [5..5] 通道 5 传输完成中断使能 */
+ __IOM uint32_t FULIE6 : 1; /*!< [6..6] 通道 6 传输完成中断使能 */
+ __IOM uint32_t FULIE7 : 1; /*!< [7..7] 通道 7 传输完成中断使能 */
+ __IOM uint32_t FULIE8 : 1; /*!< [8..8] 通道 8 传输完成中断使能 */
+ __IOM uint32_t FULIE9 : 1; /*!< [9..9] 通道 9 传输完成中断使能 */
+ __IOM uint32_t FULIE10 : 1; /*!< [10..10] 通道 10 传输完成中断使能 */
+ __IOM uint32_t FULIE11 : 1; /*!< [11..11] 通道 11 传输完成中断使能 */
+ __IOM uint32_t FULIE12 : 1; /*!< [12..12] 通道 12 传输完成中断使能 */
+ __IOM uint32_t FULIE13 : 1; /*!< [13..13] 通道 13 传输完成中断使能 */
+ __IOM uint32_t FULIE14 : 1; /*!< [14..14] 通道 14 传输完成中断使能 */
+ __IOM uint32_t FULIE15 : 1; /*!< [15..15] 通道 15 传输完成中断使能 */
+ __IOM uint32_t FULIE16 : 1; /*!< [16..16] 通道 16 传输完成中断使能 */
+ __IOM uint32_t FULIE17 : 1; /*!< [17..17] 通道 17 传输完成中断使能 */
+ __IOM uint32_t FULIE18 : 1; /*!< [18..18] 通道 18 传输完成中断使能 */
+ __IOM uint32_t FULIE19 : 1; /*!< [19..19] 通道 19 传输完成中断使能 */
+ uint32_t : 12;
+ } FIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t TCR0; /*!< (@ 0x00000190) ADC Transfer Control Register0 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR0; /*!< (@ 0x00000194) ADC Transfer Address Register0 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 0 DMA 传输的首地址 */
+ } TAR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR0; /*!< (@ 0x00000198) ADC Transfer Length Register0 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 0 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR0_b;
+ } ;
+ __IM uint32_t RESERVED10;
+
+ union {
+ __IOM uint32_t TCR1; /*!< (@ 0x000001A0) ADC Transfer Control Register1 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR1; /*!< (@ 0x000001A4) ADC Transfer Address Register1 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 1 DMA 传输的首地址 */
+ } TAR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR1; /*!< (@ 0x000001A8) ADC Transfer Length Register1 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 1 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR1_b;
+ } ;
+ __IM uint32_t RESERVED11;
+
+ union {
+ __IOM uint32_t TCR2; /*!< (@ 0x000001B0) ADC Transfer Control Register2 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR2; /*!< (@ 0x000001B4) ADC Transfer Address Register2 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 2 DMA 传输的首地址 */
+ } TAR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR2; /*!< (@ 0x000001B8) ADC Transfer Length Register2 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 2 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR2_b;
+ } ;
+ __IM uint32_t RESERVED12;
+
+ union {
+ __IOM uint32_t TCR3; /*!< (@ 0x000001C0) ADC Transfer Control Register3 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR3; /*!< (@ 0x000001C4) ADC Transfer Address Register3 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 3 DMA 传输的首地址 */
+ } TAR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR3; /*!< (@ 0x000001C8) ADC Transfer Length Register3 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 3 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR3_b;
+ } ;
+ __IM uint32_t RESERVED13;
+
+ union {
+ __IOM uint32_t TCR4; /*!< (@ 0x000001D0) ADC Transfer Control Register4 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR4; /*!< (@ 0x000001D4) ADC Transfer Address Register4 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 4 DMA 传输的首地址 */
+ } TAR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR4; /*!< (@ 0x000001D8) ADC Transfer Length Register4 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 4 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR4_b;
+ } ;
+ __IM uint32_t RESERVED14;
+
+ union {
+ __IOM uint32_t TCR5; /*!< (@ 0x000001E0) ADC Transfer Control Register5 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR5; /*!< (@ 0x000001E4) ADC Transfer Address Register5 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 5 DMA 传输的首地址 */
+ } TAR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR5; /*!< (@ 0x000001E8) ADC Transfer Length Register5 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 5 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR5_b;
+ } ;
+ __IM uint32_t RESERVED15;
+
+ union {
+ __IOM uint32_t TCR6; /*!< (@ 0x000001F0) ADC Transfer Control Register6 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR6; /*!< (@ 0x000001F4) ADC Transfer Address Register6 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 6 DMA 传输的首地址 */
+ } TAR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR6; /*!< (@ 0x000001F8) ADC Transfer Length Register6 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 6 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR6_b;
+ } ;
+ __IM uint32_t RESERVED16;
+
+ union {
+ __IOM uint32_t TCR7; /*!< (@ 0x00000200) ADC Transfer Control Register7 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR7; /*!< (@ 0x00000204) ADC Transfer Address Register7 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 7 DMA 传输的首地址 */
+ } TAR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR7; /*!< (@ 0x00000208) ADC Transfer Length Register7 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 7 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR7_b;
+ } ;
+ __IM uint32_t RESERVED17;
+
+ union {
+ __IOM uint32_t TCR8; /*!< (@ 0x00000210) ADC Transfer Control Register8 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR8; /*!< (@ 0x00000214) ADC Transfer Address Register8 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 8 DMA 传输的首地址 */
+ } TAR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR8; /*!< (@ 0x00000218) ADC Transfer Length Register8 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 8 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR8_b;
+ } ;
+ __IM uint32_t RESERVED18;
+
+ union {
+ __IOM uint32_t TCR9; /*!< (@ 0x00000220) ADC Transfer Control Register9 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR9; /*!< (@ 0x00000224) ADC Transfer Address Register9 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 9 DMA 传输的首地址 */
+ } TAR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR9; /*!< (@ 0x00000228) ADC Transfer Length Register9 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 9 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR9_b;
+ } ;
+ __IM uint32_t RESERVED19;
+
+ union {
+ __IOM uint32_t TCR10; /*!< (@ 0x00000230) ADC Transfer Control Register10 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR10; /*!< (@ 0x00000234) ADC Transfer Address Register10 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 10 DMA 传输的首地址 */
+ } TAR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR10; /*!< (@ 0x00000238) ADC Transfer Length Register10 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 10 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR10_b;
+ } ;
+ __IM uint32_t RESERVED20;
+
+ union {
+ __IOM uint32_t TCR11; /*!< (@ 0x00000240) ADC Transfer Control Register11 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR11; /*!< (@ 0x00000244) ADC Transfer Address Register11 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 11 DMA 传输的首地址 */
+ } TAR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR11; /*!< (@ 0x00000248) ADC Transfer Length Register11 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 11 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR11_b;
+ } ;
+ __IM uint32_t RESERVED21;
+
+ union {
+ __IOM uint32_t TCR12; /*!< (@ 0x00000250) ADC Transfer Control Register12 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR12; /*!< (@ 0x00000254) ADC Transfer Address Register12 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 12 DMA 传输的首地址 */
+ } TAR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR12; /*!< (@ 0x00000258) ADC Transfer Length Register12 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 12 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR12_b;
+ } ;
+ __IM uint32_t RESERVED22;
+
+ union {
+ __IOM uint32_t TCR13; /*!< (@ 0x00000260) ADC Transfer Control Register13 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR13; /*!< (@ 0x00000264) ADC Transfer Address Register13 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 13 DMA 传输的首地址 */
+ } TAR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR13; /*!< (@ 0x00000268) ADC Transfer Length Register13 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 13 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR13_b;
+ } ;
+ __IM uint32_t RESERVED23;
+
+ union {
+ __IOM uint32_t TCR14; /*!< (@ 0x00000270) ADC Transfer Control Register14 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR14; /*!< (@ 0x00000274) ADC Transfer Address Register14 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 14 DMA 传输的首地址 */
+ } TAR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR14; /*!< (@ 0x00000278) ADC Transfer Length Register14 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 14 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR14_b;
+ } ;
+ __IM uint32_t RESERVED24;
+
+ union {
+ __IOM uint32_t TCR15; /*!< (@ 0x00000280) ADC Transfer Control Register15 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR15; /*!< (@ 0x00000284) ADC Transfer Address Register15 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 15 DMA 传输的首地址 */
+ } TAR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR15; /*!< (@ 0x00000288) ADC Transfer Length Register15 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 15 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR15_b;
+ } ;
+ __IM uint32_t RESERVED25;
+
+ union {
+ __IOM uint32_t TCR16; /*!< (@ 0x00000290) ADC Transfer Control Register16 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR16; /*!< (@ 0x00000294) ADC Transfer Address Register16 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 16 DMA 传输的首地址 */
+ } TAR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR16; /*!< (@ 0x00000298) ADC Transfer Length Register16 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 16 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR16_b;
+ } ;
+ __IM uint32_t RESERVED26;
+
+ union {
+ __IOM uint32_t TCR17; /*!< (@ 0x000002A0) ADC Transfer Control Register17 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR17; /*!< (@ 0x000002A4) ADC Transfer Address Register17 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 17 DMA 传输的首地址 */
+ } TAR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR17; /*!< (@ 0x000002A8) ADC Transfer Length Register17 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 17 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR17_b;
+ } ;
+ __IM uint32_t RESERVED27;
+
+ union {
+ __IOM uint32_t TCR18; /*!< (@ 0x000002B0) ADC Transfer Control Register18 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR18; /*!< (@ 0x000002B4) ADC Transfer Address Register18 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 18 DMA 传输的首地址 */
+ } TAR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR18; /*!< (@ 0x000002B8) ADC Transfer Length Register18 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 18 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR18_b;
+ } ;
+ __IM uint32_t RESERVED28;
+
+ union {
+ __IOM uint32_t TCR19; /*!< (@ 0x000002C0) ADC Transfer Control Register19 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR19_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR19; /*!< (@ 0x000002C4) ADC Transfer Address Register19 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 19 DMA 传输的首地址 */
+ } TAR19_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR19; /*!< (@ 0x000002C8) ADC Transfer Length Register19 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 19 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR19_b;
+ } ;
+ __IM uint32_t RESERVED29[13];
+
+ union {
+ __IOM uint32_t CCR; /*!< (@ 0x00000300) ADC Common Control Registe */
+
+ struct {
+ __IOM uint32_t DUAL : 4; /*!< [3..0] ADC DUAL模式选择（仅Master ADC配置有效） */
+ uint32_t : 4;
+ __IOM uint32_t DELAY : 10; /*!< [17..8] ADC DUAL采样相位延迟（仅Master ADC配置有效） */
+ uint32_t : 14;
+ } CCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CSR; /*!< (@ 0x00000304) ADC Common Status Register */
+
+ struct {
+ __IM uint32_t EOC_MST : 1; /*!< [0..0] 常规转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOS_MST : 1; /*!< [1..1] 常规序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOC_MST : 1; /*!< [2..2] 注入转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOS_MST : 1; /*!< [3..3] 注入序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t OVR_MST : 1; /*!< [4..4] ADC 数据溢出中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD0_MST : 1; /*!< [5..5] 模拟看门狗 0 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD1_MST : 1; /*!< [6..6] 模拟看门狗 1 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD2_MST : 1; /*!< [7..7] 模拟看门狗 2 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t ADRDY_MST : 1; /*!< [8..8] ADC 就绪中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOSMP_MST : 1; /*!< [9..9] 采样阶段结束中断标志（仅Master ADC读取有效） */
+ uint32_t : 6;
+ __IM uint32_t EOC_SLV : 1; /*!< [16..16] 常规转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOS_SLV : 1; /*!< [17..17] 常规序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOC_SLV : 1; /*!< [18..18] 注入转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOS_SLV : 1; /*!< [19..19] 注入序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t OVR_SLV : 1; /*!< [20..20] ADC 数据溢出中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD0_SLV : 1; /*!< [21..21] 模拟看门狗 0 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD1_SLV : 1; /*!< [22..22] 模拟看门狗 1 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD2_SLV : 1; /*!< [23..23] 模拟看门狗 2 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t ADRDY_SLV : 1; /*!< [24..24] ADC 就绪中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOSMP_SLV : 1; /*!< [25..25] 采样阶段结束中断标志（仅Master ADC读取有效） */
+ uint32_t : 6;
+ } CSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR; /*!< (@ 0x00000308) ADC Common Regular Data Register */
+
+ struct {
+ __IM uint32_t RDATA_MST : 16; /*!< [15..0] Master ADC 常规序列已转换的数据（仅Master
+ ADC读取有效） */
+ __IM uint32_t RDATA_SLV : 16; /*!< [31..16] Slave ADC 常规序列已转换的数据（仅Master
+ ADC读取有效） */
+ } CDR_b;
+ } ;
+} ADC2_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ADC3 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief ADC3 (ADC3)
+ */
+
+typedef struct { /*!< (@ 0x40038C00) ADC3 Structure */
+
+ union {
+ __IOM uint32_t CR; /*!< (@ 0x00000000) ADC Control Register */
+
+ struct {
+ __IOM uint32_t ADEN : 1; /*!< [0..0] ADC 开始模块使能命令 */
+ __IOM uint32_t ADDIS : 1; /*!< [1..1] ADC 停止模块使能命令 */
+ __IOM uint32_t ADSTART : 1; /*!< [2..2] ADC 开始常规转换命令 */
+ __IOM uint32_t JADSTART : 1; /*!< [3..3] ADC 开始注入转换命令 */
+ __IOM uint32_t ADSTP : 1; /*!< [4..4] ADC 停止常规转换命令 */
+ __IOM uint32_t JADSTP : 1; /*!< [5..5] ADC 停止注入转换命令 */
+ __IOM uint32_t ADCAL : 1; /*!< [6..6] ADC 启动校准命令 */
+ __IOM uint32_t ADCALDIF : 1; /*!< [7..7] ADC 校准模式选择 */
+ uint32_t : 24;
+ } CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFGR0; /*!< (@ 0x00000004) ADC Configuration Register0 */
+
+ struct {
+ __IOM uint32_t ROVSE : 1; /*!< [0..0] 规则序列过采样使能 */
+ __IOM uint32_t JOVSE : 1; /*!< [1..1] 注入序列过采样使能 */
+ uint32_t : 2;
+ __IOM uint32_t OVSR : 3; /*!< [6..4] 过采样数据叠加比率 */
+ __IOM uint32_t ROVSM : 1; /*!< [7..7] 常规通道的过采样模式 */
+ __IOM uint32_t OVSS : 4; /*!< [11..8] 过采样数据移位位数 */
+ __IOM uint32_t TROVS : 1; /*!< [12..12] 触发式规则序列过采样使能 */
+ uint32_t : 1;
+ __IOM uint32_t SDMAEN : 1; /*!< [14..14] 系统DMA请求使能 */
+ __IOM uint32_t OVRMOD : 1; /*!< [15..15] 数据溢出模式 */
+ __IOM uint32_t DISCEN : 1; /*!< [16..16] 常规序列的单次／不连续转换模式 */
+ __IOM uint32_t DISCNUM : 3; /*!< [19..17] 不连续采样模式通道计数 */
+ __IOM uint32_t JDISCEN : 1; /*!< [20..20] 注入序列的不连续采样模式 */
+ uint32_t : 1;
+ __IOM uint32_t JAUTO : 1; /*!< [22..22] 注入序列自动转换 */
+ __IOM uint32_t CONT : 1; /*!< [23..23] 常规序列的单次／连续转换模式 */
+ uint32_t : 4;
+ __IOM uint32_t OVSCAL : 3; /*!< [30..28] 自动校准数据叠加比率 */
+ uint32_t : 1;
+ } CFGR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CFGR1; /*!< (@ 0x00000008) ADC Configuration Register1 */
+
+ struct {
+ __IOM uint32_t BIASEN : 1; /*!< [0..0] 内部偏置模块使能 */
+ __IOM uint32_t REFEN : 1; /*!< [1..1] Reference模块使能 */
+ uint32_t : 1;
+ __IOM uint32_t CHEN : 1; /*!< [3..3] 通道使能 */
+ __IOM uint32_t ISEL : 2; /*!< [5..4] 偏置电流档位 */
+ uint32_t : 2;
+ __IOM uint32_t AWD0EN : 1; /*!< [8..8] 模拟看门狗 0 监测规则序列 */
+ __IOM uint32_t AWD1EN : 1; /*!< [9..9] 模拟看门狗 1 监测规则序列 */
+ __IOM uint32_t AWD2EN : 1; /*!< [10..10] 模拟看门狗 2 监测规则序列 */
+ uint32_t : 1;
+ __IOM uint32_t JAWD0EN : 1; /*!< [12..12] 模拟看门狗 0 监测注入序列 */
+ __IOM uint32_t JAWD1EN : 1; /*!< [13..13] 模拟看门狗 1 监测注入序列 */
+ __IOM uint32_t JAWD2EN : 1; /*!< [14..14] 模拟看门狗 2 监测注入序列 */
+ uint32_t : 17;
+ } CFGR1_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t ISR; /*!< (@ 0x00000010) ADC Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t EOC : 1; /*!< [0..0] 常规转换结束中断标志 */
+ __IOM uint32_t EOS : 1; /*!< [1..1] 常规序列结束中断标志 */
+ __IOM uint32_t JEOC : 1; /*!< [2..2] 注入转换结束中断标志 */
+ __IOM uint32_t JEOS : 1; /*!< [3..3] 注入序列结束中断标志 */
+ __IOM uint32_t OVR : 1; /*!< [4..4] ADC 数据溢出中断标志 */
+ __IOM uint32_t AWD0 : 1; /*!< [5..5] 模拟看门狗 0 中断标志 */
+ __IOM uint32_t AWD1 : 1; /*!< [6..6] 模拟看门狗 1 中断标志 */
+ __IOM uint32_t AWD2 : 1; /*!< [7..7] 模拟看门狗 2 中断标志 */
+ __IOM uint32_t ADRDY : 1; /*!< [8..8] ADC 就绪中断标志 */
+ __IOM uint32_t EOSMP : 1; /*!< [9..9] 采样阶段结束中断标志 */
+ uint32_t : 22;
+ } ISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x00000014) ADC Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t EOCIE : 1; /*!< [0..0] 常规转换结束中断使能 */
+ __IOM uint32_t EOSIE : 1; /*!< [1..1] 常规序列结束中断使能 */
+ __IOM uint32_t JEOCIE : 1; /*!< [2..2] 注入转换结束中断使能 */
+ __IOM uint32_t JEOSIE : 1; /*!< [3..3] 注入序列结束中断使能 */
+ __IOM uint32_t OVRIE : 1; /*!< [4..4] ADC 数据溢出中断使能 */
+ __IOM uint32_t AWD0IE : 1; /*!< [5..5] 模拟看门狗 0 中断使能 */
+ __IOM uint32_t AWD1IE : 1; /*!< [6..6] 模拟看门狗 1 中断使能 */
+ __IOM uint32_t AWD2IE : 1; /*!< [7..7] 模拟看门狗 2 中断使能 */
+ __IOM uint32_t ADRDYIE : 1; /*!< [8..8] ADC 就绪中断使能 */
+ __IOM uint32_t EOSMPIE : 1; /*!< [9..9] 采样阶段结束中断使能 */
+ uint32_t : 22;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SIGSEL; /*!< (@ 0x00000018) ADC Single-End Select Register */
+
+ struct {
+ __IOM uint32_t SIGSEL : 20; /*!< [19..0] ADC 通道转换模式选择 */
+ uint32_t : 12;
+ } SIGSEL_b;
+ } ;
+ __IM uint32_t RESERVED1;
+
+ union {
+ __IOM uint32_t SMPR0; /*!< (@ 0x00000020) ADC Sample Time Register 0 */
+
+ struct {
+ __IOM uint32_t SMP0 : 3; /*!< [2..0] 通道 0 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP1 : 3; /*!< [6..4] 通道 1 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP2 : 3; /*!< [10..8] 通道 2 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP3 : 3; /*!< [14..12] 通道 3 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP4 : 3; /*!< [18..16] 通道 4 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP5 : 3; /*!< [22..20] 通道 5 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP6 : 3; /*!< [26..24] 通道 6 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP7 : 3; /*!< [30..28] 通道 7 采样时间选择位 */
+ uint32_t : 1;
+ } SMPR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t SMPR1; /*!< (@ 0x00000024) ADC Sample Time Register 1 */
+
+ struct {
+ __IOM uint32_t SMP8 : 3; /*!< [2..0] 通道 8 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP9 : 3; /*!< [6..4] 通道 9 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP10 : 3; /*!< [10..8] 通道 10 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP11 : 3; /*!< [14..12] 通道 11 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP12 : 3; /*!< [18..16] 通道 12 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP13 : 3; /*!< [22..20] 通道 13 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP14 : 3; /*!< [26..24] 通道 14 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP15 : 3; /*!< [30..28] 通道 15 采样时间选择位 */
+ uint32_t : 1;
+ } SMPR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SMPR2; /*!< (@ 0x00000028) ADC Sample Time Register 2 */
+
+ struct {
+ __IOM uint32_t SMP16 : 3; /*!< [2..0] 通道 16 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP17 : 3; /*!< [6..4] 通道 17 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP18 : 3; /*!< [10..8] 通道 18 采样时间选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SMP19 : 3; /*!< [14..12] 通道 19 采样时间选择位 */
+ uint32_t : 17;
+ } SMPR2_b;
+ } ;
+ __IM uint32_t RESERVED2;
+
+ union {
+ __IOM uint32_t CALR0; /*!< (@ 0x00000030) ADC Calibration Data Register 0 */
+
+ struct {
+ __IOM uint32_t CAL0 : 2; /*!< [1..0] 通道 0 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT0 : 1; /*!< [3..3] 通道 0 饱和运算选择位 */
+ __IOM uint32_t CAL1 : 2; /*!< [5..4] 通道 1 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT1 : 1; /*!< [7..7] 通道 1 饱和运算选择位 */
+ __IOM uint32_t CAL2 : 2; /*!< [9..8] 通道 2 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT2 : 1; /*!< [11..11] 通道 2 饱和运算选择位 */
+ __IOM uint32_t CAL3 : 2; /*!< [13..12] 通道 3 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT3 : 1; /*!< [15..15] 通道 3 饱和运算选择位 */
+ __IOM uint32_t CAL4 : 2; /*!< [17..16] 通道 4 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT4 : 1; /*!< [19..19] 通道 4 饱和运算选择位 */
+ __IOM uint32_t CAL5 : 2; /*!< [21..20] 通道 5 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT5 : 1; /*!< [23..23] 通道 5 饱和运算选择位 */
+ __IOM uint32_t CAL6 : 2; /*!< [25..24] 通道 6 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT6 : 1; /*!< [27..27] 通道 6 饱和运算选择位 */
+ __IOM uint32_t CAL7 : 2; /*!< [29..28] 通道 7 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT7 : 1; /*!< [31..31] 通道 7 饱和运算选择位 */
+ } CALR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CALR1; /*!< (@ 0x00000034) ADC Calibration Data Register 1 */
+
+ struct {
+ __IOM uint32_t CAL8 : 2; /*!< [1..0] 通道 8 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT8 : 1; /*!< [3..3] 通道 8 饱和运算选择位 */
+ __IOM uint32_t CAL9 : 2; /*!< [5..4] 通道 9 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT9 : 1; /*!< [7..7] 通道 9 饱和运算选择位 */
+ __IOM uint32_t CAL10 : 2; /*!< [9..8] 通道 10 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT10 : 1; /*!< [11..11] 通道 10 饱和运算选择位 */
+ __IOM uint32_t CAL11 : 2; /*!< [13..12] 通道 11 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT11 : 1; /*!< [15..15] 通道 11 饱和运算选择位 */
+ __IOM uint32_t CAL12 : 2; /*!< [17..16] 通道 12 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT12 : 1; /*!< [19..19] 通道 12 饱和运算选择位 */
+ __IOM uint32_t CAL13 : 2; /*!< [21..20] 通道 13 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT13 : 1; /*!< [23..23] 通道 13 饱和运算选择位 */
+ __IOM uint32_t CAL14 : 2; /*!< [25..24] 通道 14 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT14 : 1; /*!< [27..27] 通道 14 饱和运算选择位 */
+ __IOM uint32_t CAL15 : 2; /*!< [29..28] 通道 15 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT15 : 1; /*!< [31..31] 通道 15 饱和运算选择位 */
+ } CALR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t CALR2; /*!< (@ 0x00000038) ADC Calibration Data Register 2 */
+
+ struct {
+ __IOM uint32_t CAL16 : 2; /*!< [1..0] 通道 16 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT16 : 1; /*!< [3..3] 通道 16 饱和运算选择位 */
+ __IOM uint32_t CAL17 : 2; /*!< [5..4] 通道 17 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT17 : 1; /*!< [7..7] 通道 17 饱和运算选择位 */
+ __IOM uint32_t CAL18 : 2; /*!< [9..8] 通道 18 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT18 : 1; /*!< [11..11] 通道 18 饱和运算选择位 */
+ __IOM uint32_t CAL19 : 2; /*!< [13..12] 通道 19 校准系数选择位 */
+ uint32_t : 1;
+ __IOM uint32_t SAT19 : 1; /*!< [15..15] 通道 19 饱和运算选择位 */
+ uint32_t : 16;
+ } CALR2_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t SQR0; /*!< (@ 0x00000040) ADC Regular Sequence Register0 */
+
+ struct {
+ __IOM uint32_t SQ1 : 5; /*!< [4..0] 常规序列中的第 1 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ2 : 5; /*!< [10..6] 常规序列中的第 2 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ3 : 5; /*!< [16..12] 常规序列中的第 3 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ4 : 5; /*!< [22..18] 常规序列中的第 4 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ5 : 5; /*!< [28..24] 常规序列中的第 5 次转换 */
+ uint32_t : 3;
+ } SQR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR1; /*!< (@ 0x00000044) ADC Regular Sequence Register1 */
+
+ struct {
+ __IOM uint32_t SQ6 : 5; /*!< [4..0] 常规序列中的第 6 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ7 : 5; /*!< [10..6] 常规序列中的第 7 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ8 : 5; /*!< [16..12] 常规序列中的第 8 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ9 : 5; /*!< [22..18] 常规序列中的第 9 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ10 : 5; /*!< [28..24] 常规序列中的第 10 次转换 */
+ uint32_t : 3;
+ } SQR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR2; /*!< (@ 0x00000048) ADC Regular Sequence Register2 */
+
+ struct {
+ __IOM uint32_t SQ11 : 5; /*!< [4..0] 常规序列中的第 11 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ12 : 5; /*!< [10..6] 常规序列中的第 12 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ13 : 5; /*!< [16..12] 常规序列中的第 13 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ14 : 5; /*!< [22..18] 常规序列中的第 14 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t SQ15 : 5; /*!< [28..24] 常规序列中的第 15 次转换 */
+ uint32_t : 3;
+ } SQR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t SQR3; /*!< (@ 0x0000004C) ADC Regular Sequence Register3 */
+
+ struct {
+ __IOM uint32_t SQ16 : 5; /*!< [4..0] 常规序列中的第 16 次转换 */
+ uint32_t : 27;
+ } SQR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t LR; /*!< (@ 0x00000050) ADC Regular Length Register */
+
+ struct {
+ __IOM uint32_t EXTSEL : 5; /*!< [4..0] 常规序列的硬件触发选择 */
+ uint32_t : 1;
+ __IOM uint32_t EXTEN : 2; /*!< [7..6] 常规序列的硬件触发使能和极性选择 */
+ __IOM uint32_t LEN : 4; /*!< [11..8] 常规序列的长度 */
+ uint32_t : 20;
+ } LR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DR; /*!< (@ 0x00000054) ADC Regular Data Register */
+
+ struct {
+ __IOM uint32_t RDATA : 16; /*!< [15..0] 常规序列已转换的数据 */
+ uint32_t : 16;
+ } DR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MAXDR; /*!< (@ 0x00000058) ADC Maximum Regular Data Register */
+
+ struct {
+ __IOM uint32_t MAXDATA : 16; /*!< [15..0] 常规序列数据饱和运算最大值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MAXDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MINDR; /*!< (@ 0x0000005C) ADC Minimum Regular Data Register */
+
+ struct {
+ __IOM uint32_t MINDATA : 16; /*!< [15..0] 常规序列数据饱和运算最小值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MINDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JSQR; /*!< (@ 0x00000060) ADC Injected Sequence Register */
+
+ struct {
+ __IOM uint32_t JSQ1 : 5; /*!< [4..0] 注入序列中的第 1 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ2 : 5; /*!< [10..6] 注入序列中的第 2 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ3 : 5; /*!< [16..12] 注入序列中的第 3 次转换 */
+ uint32_t : 1;
+ __IOM uint32_t JSQ4 : 5; /*!< [22..18] 注入序列中的第 4 次转换 */
+ uint32_t : 9;
+ } JSQR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JLR; /*!< (@ 0x00000064) ADC Injected Length Register */
+
+ struct {
+ __IOM uint32_t JEXTSEL : 5; /*!< [4..0] 注入序列的硬件触发选择 */
+ uint32_t : 1;
+ __IOM uint32_t JEXTEN : 2; /*!< [7..6] 注入序列的硬件触发使能和极性选择 */
+ __IOM uint32_t JLEN : 2; /*!< [9..8] 注入序列的长度 */
+ uint32_t : 22;
+ } JLR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MAXJDR; /*!< (@ 0x00000068) ADC Maximum Injected Data Register */
+
+ struct {
+ __IOM uint32_t MAXDATA : 16; /*!< [15..0] 注入序列数据饱和运算最大值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MAXJDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t MINJDR; /*!< (@ 0x0000006C) ADC Minimum Injected Data Register */
+
+ struct {
+ __IOM uint32_t MINDATA : 16; /*!< [15..0] 注入序列数据饱和运算最小值（在通道配置为支持饱�
+ �运算时有效） */
+ uint32_t : 16;
+ } MINJDR_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR0; /*!< (@ 0x00000070) ADC Injected Data Register0 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 0 个已转换数据 */
+ uint32_t : 16;
+ } JDR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR1; /*!< (@ 0x00000074) ADC Injected Data Register1 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 1 个已转换数据 */
+ uint32_t : 16;
+ } JDR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR2; /*!< (@ 0x00000078) ADC Injected Data Register2 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 2 个已转换数据 */
+ uint32_t : 16;
+ } JDR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t JDR3; /*!< (@ 0x0000007C) ADC Injected Data Register3 */
+
+ struct {
+ __IOM uint32_t JDATA : 16; /*!< [15..0] 注入序列的第 3 个已转换数据 */
+ uint32_t : 16;
+ } JDR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR0; /*!< (@ 0x00000080) ADC Watchdog0 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT0 : 16; /*!< [15..0] 模拟看门狗 0 阈值下限 */
+ __IOM uint32_t HT0 : 16; /*!< [31..16] 模拟看门狗 0 阈值上限 */
+ } TR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR1; /*!< (@ 0x00000084) ADC Watchdog1 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT1 : 16; /*!< [15..0] 模拟看门狗 1 阈值下限 */
+ __IOM uint32_t HT1 : 16; /*!< [31..16] 模拟看门狗 1 阈值上限 */
+ } TR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TR2; /*!< (@ 0x00000088) ADC Watchdog2 Threshold Register */
+
+ struct {
+ __IOM uint32_t LT2 : 16; /*!< [15..0] 模拟看门狗 2 阈值下限 */
+ __IOM uint32_t HT2 : 16; /*!< [31..16] 模拟看门狗 2 阈值上限 */
+ } TR2_b;
+ } ;
+ __IM uint32_t RESERVED4;
+
+ union {
+ __IOM uint32_t AWD0CR; /*!< (@ 0x00000090) ADC Watchdog0 Control Register */
+
+ struct {
+ __IOM uint32_t AW0CH : 20; /*!< [19..0] 模拟看门狗 0 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 0 滤波点数 */
+ uint32_t : 4;
+ } AWD0CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AWD1CR; /*!< (@ 0x00000094) ADC Watchdog1 Control Register */
+
+ struct {
+ __IOM uint32_t AW1CH : 20; /*!< [19..0] 模拟看门狗 1 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 1 滤波点数 */
+ uint32_t : 4;
+ } AWD1CR_b;
+ } ;
+
+ union {
+ __IOM uint32_t AWD2CR; /*!< (@ 0x00000098) ADC Watchdog 2 Control Register */
+
+ struct {
+ __IOM uint32_t AW2CH : 20; /*!< [19..0] 模拟看门狗 2 通道选择 */
+ uint32_t : 4;
+ __IOM uint32_t AWDFILT : 4; /*!< [27..24] 模拟看门狗 2 滤波点数 */
+ uint32_t : 4;
+ } AWD2CR_b;
+ } ;
+ __IM uint32_t RESERVED5;
+
+ union {
+ __IOM uint32_t OFR0; /*!< (@ 0x000000A0) ADC Offset Register0 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 0 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR1; /*!< (@ 0x000000A4) ADC Offset Register1 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 1 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR2; /*!< (@ 0x000000A8) ADC Offset Register2 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 2 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t OFR3; /*!< (@ 0x000000AC) ADC Offset Register3 */
+
+ struct {
+ __IOM uint32_t OFFSET : 16; /*!< [15..0] 第 3 组 ADC 偏置补偿系数 */
+ uint32_t : 16;
+ } OFR3_b;
+ } ;
+ __IM uint32_t RESERVED6[4];
+
+ union {
+ __IOM uint32_t GCR0; /*!< (@ 0x000000C0) ADC Gain Coeff Register0 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 0 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR1; /*!< (@ 0x000000C4) ADC Gain Coeff Register1 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 1 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR2; /*!< (@ 0x000000C8) ADC Gain Coeff Register2 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 2 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t GCR3; /*!< (@ 0x000000CC) ADC Gain Coeff Register3 */
+
+ struct {
+ __IOM uint32_t COEFF : 15; /*!< [14..0] 第 3 组 ADC 增益补偿系数 */
+ uint32_t : 17;
+ } GCR3_b;
+ } ;
+ __IM uint32_t RESERVED7[12];
+
+ union {
+ __IOM uint32_t DISR; /*!< (@ 0x00000100) ADC Data Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t DON0 : 1; /*!< [0..0] 通道 0 转换完成中断标志 */
+ __IOM uint32_t DON1 : 1; /*!< [1..1] 通道 1 转换完成中断标志 */
+ __IOM uint32_t DON2 : 1; /*!< [2..2] 通道 2 转换完成中断标志 */
+ __IOM uint32_t DON3 : 1; /*!< [3..3] 通道 3 转换完成中断标志 */
+ __IOM uint32_t DON4 : 1; /*!< [4..4] 通道 4 转换完成中断标志 */
+ __IOM uint32_t DON5 : 1; /*!< [5..5] 通道 5 转换完成中断标志 */
+ __IOM uint32_t DON6 : 1; /*!< [6..6] 通道 6 转换完成中断标志 */
+ __IOM uint32_t DON7 : 1; /*!< [7..7] 通道 7 转换完成中断标志 */
+ __IOM uint32_t DON8 : 1; /*!< [8..8] 通道 8 转换完成中断标志 */
+ __IOM uint32_t DON9 : 1; /*!< [9..9] 通道 9 转换完成中断标志 */
+ __IOM uint32_t DON10 : 1; /*!< [10..10] 通道 10 转换完成中断标志 */
+ __IOM uint32_t DON11 : 1; /*!< [11..11] 通道 11 转换完成中断标志 */
+ __IOM uint32_t DON12 : 1; /*!< [12..12] 通道 12 转换完成中断标志 */
+ __IOM uint32_t DON13 : 1; /*!< [13..13] 通道 13 转换完成中断标志 */
+ __IOM uint32_t DON14 : 1; /*!< [14..14] 通道 14 转换完成中断标志 */
+ __IOM uint32_t DON15 : 1; /*!< [15..15] 通道 15 转换完成中断标志 */
+ __IOM uint32_t DON16 : 1; /*!< [16..16] 通道 16 转换完成中断标志 */
+ __IOM uint32_t DON17 : 1; /*!< [17..17] 通道 17 转换完成中断标志 */
+ __IOM uint32_t DON18 : 1; /*!< [18..18] 通道 18 转换完成中断标志 */
+ __IOM uint32_t DON19 : 1; /*!< [19..19] 通道 19 转换完成中断标志 */
+ uint32_t : 12;
+ } DISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t DIER; /*!< (@ 0x00000104) ADC Data Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t DONIE0 : 1; /*!< [0..0] 通道 0 转换完成中断使能 */
+ __IOM uint32_t DONIE1 : 1; /*!< [1..1] 通道 1 转换完成中断使能 */
+ __IOM uint32_t DONIE2 : 1; /*!< [2..2] 通道 2 转换完成中断使能 */
+ __IOM uint32_t DONIE3 : 1; /*!< [3..3] 通道 3 转换完成中断使能 */
+ __IOM uint32_t DONIE4 : 1; /*!< [4..4] 通道 4 转换完成中断使能 */
+ __IOM uint32_t DONIE5 : 1; /*!< [5..5] 通道 5 转换完成中断使能 */
+ __IOM uint32_t DONIE6 : 1; /*!< [6..6] 通道 6 转换完成中断使能 */
+ __IOM uint32_t DONIE7 : 1; /*!< [7..7] 通道 7 转换完成中断使能 */
+ __IOM uint32_t DONIE8 : 1; /*!< [8..8] 通道 8 转换完成中断使能 */
+ __IOM uint32_t DONIE9 : 1; /*!< [9..9] 通道 9 转换完成中断使能 */
+ __IOM uint32_t DONIE10 : 1; /*!< [10..10] 通道 10 转换完成中断使能 */
+ __IOM uint32_t DONIE11 : 1; /*!< [11..11] 通道 11 转换完成中断使能 */
+ __IOM uint32_t DONIE12 : 1; /*!< [12..12] 通道 12 转换完成中断使能 */
+ __IOM uint32_t DONIE13 : 1; /*!< [13..13] 通道 13 转换完成中断使能 */
+ __IOM uint32_t DONIE14 : 1; /*!< [14..14] 通道 14 转换完成中断使能 */
+ __IOM uint32_t DONIE15 : 1; /*!< [15..15] 通道 15 转换完成中断使能 */
+ __IOM uint32_t DONIE16 : 1; /*!< [16..16] 通道 16 转换完成中断使能 */
+ __IOM uint32_t DONIE17 : 1; /*!< [17..17] 通道 17 转换完成中断使能 */
+ __IOM uint32_t DONIE18 : 1; /*!< [18..18] 通道 18 转换完成中断使能 */
+ __IOM uint32_t DONIE19 : 1; /*!< [19..19] 通道 19 转换完成中断使能 */
+ uint32_t : 12;
+ } DIER_b;
+ } ;
+ __IM uint32_t RESERVED8[2];
+
+ union {
+ __IOM uint32_t CDR0; /*!< (@ 0x00000110) ADC Channel Data Register0 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 0 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR1; /*!< (@ 0x00000114) ADC Channel Data Register1 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 1 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR2; /*!< (@ 0x00000118) ADC Channel Data Register2 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 2 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR3; /*!< (@ 0x0000011C) ADC Channel Data Register3 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 3 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR4; /*!< (@ 0x00000120) ADC Channel Data Register4 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 4 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR5; /*!< (@ 0x00000124) ADC Channel Data Register5 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 5 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR6; /*!< (@ 0x00000128) ADC Channel Data Register6 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 6 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR7; /*!< (@ 0x0000012C) ADC Channel Data Register7 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 7 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR8; /*!< (@ 0x00000130) ADC Channel Data Register8 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 8 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR9; /*!< (@ 0x00000134) ADC Channel Data Register9 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 9 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR10; /*!< (@ 0x00000138) ADC Channel Data Register10 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 10 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR11; /*!< (@ 0x0000013C) ADC Channel Data Register11 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 11 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR12; /*!< (@ 0x00000140) ADC Channel Data Register12 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 12 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR13; /*!< (@ 0x00000144) ADC Channel Data Register13 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 13 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR14; /*!< (@ 0x00000148) ADC Channel Data Register14 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 14 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR15; /*!< (@ 0x0000014C) ADC Channel Data Register15 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 15 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR16; /*!< (@ 0x00000150) ADC Channel Data Register16 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 16 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR17; /*!< (@ 0x00000154) ADC Channel Data Register17 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 17 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR18; /*!< (@ 0x00000158) ADC Channel Data Register18 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 18 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR19; /*!< (@ 0x0000015C) ADC Channel Data Register19 */
+
+ struct {
+ __IM uint32_t CDATA : 16; /*!< [15..0] 通道 19 ADC 转换数据结果 */
+ uint32_t : 16;
+ } CDR19_b;
+ } ;
+ __IM uint32_t RESERVED9[8];
+
+ union {
+ __IOM uint32_t HISR; /*!< (@ 0x00000180) ADC Half Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t HLF0 : 1; /*!< [0..0] 通道 0 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF1 : 1; /*!< [1..1] 通道 1 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF2 : 1; /*!< [2..2] 通道 2 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF3 : 1; /*!< [3..3] 通道 3 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF4 : 1; /*!< [4..4] 通道 4 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF5 : 1; /*!< [5..5] 通道 5 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF6 : 1; /*!< [6..6] 通道 6 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF7 : 1; /*!< [7..7] 通道 7 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF8 : 1; /*!< [8..8] 通道 8 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF9 : 1; /*!< [9..9] 通道 9 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF10 : 1; /*!< [10..10] 通道 10 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF11 : 1; /*!< [11..11] 通道 11 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF12 : 1; /*!< [12..12] 通道 12 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF13 : 1; /*!< [13..13] 通道 13 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF14 : 1; /*!< [14..14] 通道 14 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF15 : 1; /*!< [15..15] 通道 15 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF16 : 1; /*!< [16..16] 通道 16 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF17 : 1; /*!< [17..17] 通道 17 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF18 : 1; /*!< [18..18] 通道 18 DMA传输半完成中断标志 */
+ __IOM uint32_t HLF19 : 1; /*!< [19..19] 通道 19 DMA传输半完成中断标志 */
+ uint32_t : 12;
+ } HISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t HIER; /*!< (@ 0x00000184) ADC Half Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t HLFIE0 : 1; /*!< [0..0] 通道 0 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE1 : 1; /*!< [1..1] 通道 1 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE2 : 1; /*!< [2..2] 通道 2 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE3 : 1; /*!< [3..3] 通道 3 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE4 : 1; /*!< [4..4] 通道 4 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE5 : 1; /*!< [5..5] 通道 5 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE6 : 1; /*!< [6..6] 通道 6 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE7 : 1; /*!< [7..7] 通道 7 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE8 : 1; /*!< [8..8] 通道 8 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE9 : 1; /*!< [9..9] 通道 9 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE10 : 1; /*!< [10..10] 通道 10 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE11 : 1; /*!< [11..11] 通道 11 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE12 : 1; /*!< [12..12] 通道 12 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE13 : 1; /*!< [13..13] 通道 13 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE14 : 1; /*!< [14..14] 通道 14 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE15 : 1; /*!< [15..15] 通道 15 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE16 : 1; /*!< [16..16] 通道 16 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE17 : 1; /*!< [17..17] 通道 17 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE18 : 1; /*!< [18..18] 通道 18 DMA 传输半完成中断使能 */
+ __IOM uint32_t HLFIE19 : 1; /*!< [19..19] 通道 19 DMA 传输半完成中断使能 */
+ uint32_t : 12;
+ } HIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t FISR; /*!< (@ 0x00000188) ADC Full Interrupt Status Register */
+
+ struct {
+ __IOM uint32_t FUL0 : 1; /*!< [0..0] 通道 0 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL1 : 1; /*!< [1..1] 通道 1 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL2 : 1; /*!< [2..2] 通道 2 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL3 : 1; /*!< [3..3] 通道 3 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL4 : 1; /*!< [4..4] 通道 4 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL5 : 1; /*!< [5..5] 通道 5 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL6 : 1; /*!< [6..6] 通道 6 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL7 : 1; /*!< [7..7] 通道 7 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL8 : 1; /*!< [8..8] 通道 8 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL9 : 1; /*!< [9..9] 通道 9 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL10 : 1; /*!< [10..10] 通道 10 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL11 : 1; /*!< [11..11] 通道 11 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL12 : 1; /*!< [12..12] 通道 12 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL13 : 1; /*!< [13..13] 通道 13 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL14 : 1; /*!< [14..14] 通道 14 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL15 : 1; /*!< [15..15] 通道 15 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL16 : 1; /*!< [16..16] 通道 16 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL17 : 1; /*!< [17..17] 通道 17 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL18 : 1; /*!< [18..18] 通道 18 DMA 传输完成中断标志 */
+ __IOM uint32_t FUL19 : 1; /*!< [19..19] 通道 19 DMA 传输完成中断标志 */
+ uint32_t : 12;
+ } FISR_b;
+ } ;
+
+ union {
+ __IOM uint32_t FIER; /*!< (@ 0x0000018C) ADC Full Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t FULIE0 : 1; /*!< [0..0] 通道 0 传输完成中断使能 */
+ __IOM uint32_t FULIE1 : 1; /*!< [1..1] 通道 1 传输完成中断使能 */
+ __IOM uint32_t FULIE2 : 1; /*!< [2..2] 通道 2 传输完成中断使能 */
+ __IOM uint32_t FULIE3 : 1; /*!< [3..3] 通道 3 传输完成中断使能 */
+ __IOM uint32_t FULIE4 : 1; /*!< [4..4] 通道 4 传输完成中断使能 */
+ __IOM uint32_t FULIE5 : 1; /*!< [5..5] 通道 5 传输完成中断使能 */
+ __IOM uint32_t FULIE6 : 1; /*!< [6..6] 通道 6 传输完成中断使能 */
+ __IOM uint32_t FULIE7 : 1; /*!< [7..7] 通道 7 传输完成中断使能 */
+ __IOM uint32_t FULIE8 : 1; /*!< [8..8] 通道 8 传输完成中断使能 */
+ __IOM uint32_t FULIE9 : 1; /*!< [9..9] 通道 9 传输完成中断使能 */
+ __IOM uint32_t FULIE10 : 1; /*!< [10..10] 通道 10 传输完成中断使能 */
+ __IOM uint32_t FULIE11 : 1; /*!< [11..11] 通道 11 传输完成中断使能 */
+ __IOM uint32_t FULIE12 : 1; /*!< [12..12] 通道 12 传输完成中断使能 */
+ __IOM uint32_t FULIE13 : 1; /*!< [13..13] 通道 13 传输完成中断使能 */
+ __IOM uint32_t FULIE14 : 1; /*!< [14..14] 通道 14 传输完成中断使能 */
+ __IOM uint32_t FULIE15 : 1; /*!< [15..15] 通道 15 传输完成中断使能 */
+ __IOM uint32_t FULIE16 : 1; /*!< [16..16] 通道 16 传输完成中断使能 */
+ __IOM uint32_t FULIE17 : 1; /*!< [17..17] 通道 17 传输完成中断使能 */
+ __IOM uint32_t FULIE18 : 1; /*!< [18..18] 通道 18 传输完成中断使能 */
+ __IOM uint32_t FULIE19 : 1; /*!< [19..19] 通道 19 传输完成中断使能 */
+ uint32_t : 12;
+ } FIER_b;
+ } ;
+
+ union {
+ __IOM uint32_t TCR0; /*!< (@ 0x00000190) ADC Transfer Control Register0 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR0; /*!< (@ 0x00000194) ADC Transfer Address Register0 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 0 DMA 传输的首地址 */
+ } TAR0_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR0; /*!< (@ 0x00000198) ADC Transfer Length Register0 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 0 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR0_b;
+ } ;
+ __IM uint32_t RESERVED10;
+
+ union {
+ __IOM uint32_t TCR1; /*!< (@ 0x000001A0) ADC Transfer Control Register1 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR1; /*!< (@ 0x000001A4) ADC Transfer Address Register1 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 1 DMA 传输的首地址 */
+ } TAR1_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR1; /*!< (@ 0x000001A8) ADC Transfer Length Register1 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 1 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR1_b;
+ } ;
+ __IM uint32_t RESERVED11;
+
+ union {
+ __IOM uint32_t TCR2; /*!< (@ 0x000001B0) ADC Transfer Control Register2 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR2; /*!< (@ 0x000001B4) ADC Transfer Address Register2 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 2 DMA 传输的首地址 */
+ } TAR2_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR2; /*!< (@ 0x000001B8) ADC Transfer Length Register2 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 2 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR2_b;
+ } ;
+ __IM uint32_t RESERVED12;
+
+ union {
+ __IOM uint32_t TCR3; /*!< (@ 0x000001C0) ADC Transfer Control Register3 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR3; /*!< (@ 0x000001C4) ADC Transfer Address Register3 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 3 DMA 传输的首地址 */
+ } TAR3_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR3; /*!< (@ 0x000001C8) ADC Transfer Length Register3 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 3 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR3_b;
+ } ;
+ __IM uint32_t RESERVED13;
+
+ union {
+ __IOM uint32_t TCR4; /*!< (@ 0x000001D0) ADC Transfer Control Register4 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR4; /*!< (@ 0x000001D4) ADC Transfer Address Register4 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 4 DMA 传输的首地址 */
+ } TAR4_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR4; /*!< (@ 0x000001D8) ADC Transfer Length Register4 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 4 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR4_b;
+ } ;
+ __IM uint32_t RESERVED14;
+
+ union {
+ __IOM uint32_t TCR5; /*!< (@ 0x000001E0) ADC Transfer Control Register5 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR5; /*!< (@ 0x000001E4) ADC Transfer Address Register5 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 5 DMA 传输的首地址 */
+ } TAR5_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR5; /*!< (@ 0x000001E8) ADC Transfer Length Register5 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 5 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR5_b;
+ } ;
+ __IM uint32_t RESERVED15;
+
+ union {
+ __IOM uint32_t TCR6; /*!< (@ 0x000001F0) ADC Transfer Control Register6 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR6; /*!< (@ 0x000001F4) ADC Transfer Address Register6 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 6 DMA 传输的首地址 */
+ } TAR6_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR6; /*!< (@ 0x000001F8) ADC Transfer Length Register6 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 6 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR6_b;
+ } ;
+ __IM uint32_t RESERVED16;
+
+ union {
+ __IOM uint32_t TCR7; /*!< (@ 0x00000200) ADC Transfer Control Register7 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR7; /*!< (@ 0x00000204) ADC Transfer Address Register7 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 7 DMA 传输的首地址 */
+ } TAR7_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR7; /*!< (@ 0x00000208) ADC Transfer Length Register7 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 7 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR7_b;
+ } ;
+ __IM uint32_t RESERVED17;
+
+ union {
+ __IOM uint32_t TCR8; /*!< (@ 0x00000210) ADC Transfer Control Register8 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR8; /*!< (@ 0x00000214) ADC Transfer Address Register8 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 8 DMA 传输的首地址 */
+ } TAR8_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR8; /*!< (@ 0x00000218) ADC Transfer Length Register8 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 8 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR8_b;
+ } ;
+ __IM uint32_t RESERVED18;
+
+ union {
+ __IOM uint32_t TCR9; /*!< (@ 0x00000220) ADC Transfer Control Register9 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR9; /*!< (@ 0x00000224) ADC Transfer Address Register9 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 9 DMA 传输的首地址 */
+ } TAR9_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR9; /*!< (@ 0x00000228) ADC Transfer Length Register9 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 9 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR9_b;
+ } ;
+ __IM uint32_t RESERVED19;
+
+ union {
+ __IOM uint32_t TCR10; /*!< (@ 0x00000230) ADC Transfer Control Register10 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR10; /*!< (@ 0x00000234) ADC Transfer Address Register10 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 10 DMA 传输的首地址 */
+ } TAR10_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR10; /*!< (@ 0x00000238) ADC Transfer Length Register10 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 10 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR10_b;
+ } ;
+ __IM uint32_t RESERVED20;
+
+ union {
+ __IOM uint32_t TCR11; /*!< (@ 0x00000240) ADC Transfer Control Register11 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR11; /*!< (@ 0x00000244) ADC Transfer Address Register11 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 11 DMA 传输的首地址 */
+ } TAR11_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR11; /*!< (@ 0x00000248) ADC Transfer Length Register11 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 11 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR11_b;
+ } ;
+ __IM uint32_t RESERVED21;
+
+ union {
+ __IOM uint32_t TCR12; /*!< (@ 0x00000250) ADC Transfer Control Register12 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR12; /*!< (@ 0x00000254) ADC Transfer Address Register12 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 12 DMA 传输的首地址 */
+ } TAR12_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR12; /*!< (@ 0x00000258) ADC Transfer Length Register12 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 12 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR12_b;
+ } ;
+ __IM uint32_t RESERVED22;
+
+ union {
+ __IOM uint32_t TCR13; /*!< (@ 0x00000260) ADC Transfer Control Register13 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR13; /*!< (@ 0x00000264) ADC Transfer Address Register13 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 13 DMA 传输的首地址 */
+ } TAR13_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR13; /*!< (@ 0x00000268) ADC Transfer Length Register13 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 13 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR13_b;
+ } ;
+ __IM uint32_t RESERVED23;
+
+ union {
+ __IOM uint32_t TCR14; /*!< (@ 0x00000270) ADC Transfer Control Register14 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR14; /*!< (@ 0x00000274) ADC Transfer Address Register14 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 14 DMA 传输的首地址 */
+ } TAR14_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR14; /*!< (@ 0x00000278) ADC Transfer Length Register14 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 14 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR14_b;
+ } ;
+ __IM uint32_t RESERVED24;
+
+ union {
+ __IOM uint32_t TCR15; /*!< (@ 0x00000280) ADC Transfer Control Register15 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR15; /*!< (@ 0x00000284) ADC Transfer Address Register15 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 15 DMA 传输的首地址 */
+ } TAR15_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR15; /*!< (@ 0x00000288) ADC Transfer Length Register15 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 15 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR15_b;
+ } ;
+ __IM uint32_t RESERVED25;
+
+ union {
+ __IOM uint32_t TCR16; /*!< (@ 0x00000290) ADC Transfer Control Register16 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR16; /*!< (@ 0x00000294) ADC Transfer Address Register16 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 16 DMA 传输的首地址 */
+ } TAR16_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR16; /*!< (@ 0x00000298) ADC Transfer Length Register16 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 16 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR16_b;
+ } ;
+ __IM uint32_t RESERVED26;
+
+ union {
+ __IOM uint32_t TCR17; /*!< (@ 0x000002A0) ADC Transfer Control Register17 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR17; /*!< (@ 0x000002A4) ADC Transfer Address Register17 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 17 DMA 传输的首地址 */
+ } TAR17_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR17; /*!< (@ 0x000002A8) ADC Transfer Length Register17 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 17 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR17_b;
+ } ;
+ __IM uint32_t RESERVED27;
+
+ union {
+ __IOM uint32_t TCR18; /*!< (@ 0x000002B0) ADC Transfer Control Register18 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR18; /*!< (@ 0x000002B4) ADC Transfer Address Register18 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 18 DMA 传输的首地址 */
+ } TAR18_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR18; /*!< (@ 0x000002B8) ADC Transfer Length Register18 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 18 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR18_b;
+ } ;
+ __IM uint32_t RESERVED28;
+
+ union {
+ __IOM uint32_t TCR19; /*!< (@ 0x000002C0) ADC Transfer Control Register19 */
+
+ struct {
+ __IOM uint32_t START : 1; /*!< [0..0] DMA模式启动位 */
+ __IOM uint32_t STP : 1; /*!< [1..1] DMA模式停止位 */
+ __IOM uint32_t CIRC : 1; /*!< [2..2] DMA循环模式选择位 */
+ __IOM uint32_t FIX : 1; /*!< [3..3] DMA固定地址选择位 */
+ uint32_t : 28;
+ } TCR19_b;
+ } ;
+
+ union {
+ __IOM uint32_t TAR19; /*!< (@ 0x000002C4) ADC Transfer Address Register19 */
+
+ struct {
+ __IOM uint32_t ADDR : 32; /*!< [31..0] 通道 19 DMA 传输的首地址 */
+ } TAR19_b;
+ } ;
+
+ union {
+ __IOM uint32_t TLR19; /*!< (@ 0x000002C8) ADC Transfer Length Register19 */
+
+ struct {
+ __IOM uint32_t LENG : 16; /*!< [15..0] 通道 19 DMA 传输的长度（单位为 byte） */
+ uint32_t : 16;
+ } TLR19_b;
+ } ;
+ __IM uint32_t RESERVED29[13];
+
+ union {
+ __IOM uint32_t CCR; /*!< (@ 0x00000300) ADC Common Control Registe */
+
+ struct {
+ __IOM uint32_t DUAL : 4; /*!< [3..0] ADC DUAL模式选择（仅Master ADC配置有效） */
+ uint32_t : 4;
+ __IOM uint32_t DELAY : 10; /*!< [17..8] ADC DUAL采样相位延迟（仅Master ADC配置有效） */
+ uint32_t : 14;
+ } CCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CSR; /*!< (@ 0x00000304) ADC Common Status Register */
+
+ struct {
+ __IM uint32_t EOC_MST : 1; /*!< [0..0] 常规转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOS_MST : 1; /*!< [1..1] 常规序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOC_MST : 1; /*!< [2..2] 注入转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOS_MST : 1; /*!< [3..3] 注入序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t OVR_MST : 1; /*!< [4..4] ADC 数据溢出中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD0_MST : 1; /*!< [5..5] 模拟看门狗 0 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD1_MST : 1; /*!< [6..6] 模拟看门狗 1 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD2_MST : 1; /*!< [7..7] 模拟看门狗 2 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t ADRDY_MST : 1; /*!< [8..8] ADC 就绪中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOSMP_MST : 1; /*!< [9..9] 采样阶段结束中断标志（仅Master ADC读取有效） */
+ uint32_t : 6;
+ __IM uint32_t EOC_SLV : 1; /*!< [16..16] 常规转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOS_SLV : 1; /*!< [17..17] 常规序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOC_SLV : 1; /*!< [18..18] 注入转换结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t JEOS_SLV : 1; /*!< [19..19] 注入序列结束中断标志（仅Master ADC读取有效） */
+ __IM uint32_t OVR_SLV : 1; /*!< [20..20] ADC 数据溢出中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD0_SLV : 1; /*!< [21..21] 模拟看门狗 0 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD1_SLV : 1; /*!< [22..22] 模拟看门狗 1 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t AWD2_SLV : 1; /*!< [23..23] 模拟看门狗 2 中断标志（仅Master ADC读取有效） */
+ __IM uint32_t ADRDY_SLV : 1; /*!< [24..24] ADC 就绪中断标志（仅Master ADC读取有效） */
+ __IM uint32_t EOSMP_SLV : 1; /*!< [25..25] 采样阶段结束中断标志（仅Master ADC读取有效） */
+ uint32_t : 6;
+ } CSR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CDR; /*!< (@ 0x00000308) ADC Common Regular Data Register */
+
+ struct {
+ __IM uint32_t RDATA_MST : 16; /*!< [15..0] Master ADC 常规序列已转换的数据（仅Master
+ ADC读取有效） */
+ __IM uint32_t RDATA_SLV : 16; /*!< [31..16] Slave ADC 常规序列已转换的数据（仅Master
+ ADC读取有效） */
+ } CDR_b;
+ } ;
+} ADC3_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TMR6 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief TMR6 (TMR6)
+ */
+
+typedef struct { /*!< (@ 0x4000E000) TMR6 Structure */
+
+ union {
+ __IOM uint32_t CR0; /*!< (@ 0x00000000) TMRx Control Register0 */
+
+ struct {
+ __IOM uint32_t CEN : 1; /*!< [0..0] 定时器使能位(Timer Enable) */
+ uint32_t : 2;
+ __IOM uint32_t OPM : 1; /*!< [3..3] 单脉冲模式(One Pulse Mode) */
+ uint32_t : 3;
+ __IOM uint32_t ARE : 1; /*!< [7..7] 自动重载使能(AutoReload Enable) */
+ uint32_t : 24;
+ } CR0_b;
+ } ;
+ __IM uint32_t RESERVED;
+
+ union {
+ __IOM uint32_t SCR; /*!< (@ 0x00000008) TMRx Slave Control Register */
+
+ struct {
+ __IOM uint32_t SMS : 4; /*!< [3..0] 从模式选择(Slave Mode Selection) */
+ uint32_t : 4;
+ __IOM uint32_t TS : 5; /*!< [12..8] 触发选择(Trigger Selection) */
+ uint32_t : 3;
+ __IOM uint32_t EFS : 4; /*!< [19..16] ETR滤波选择(ETR Filter Selection) */
+ __IOM uint32_t EMS : 2; /*!< [21..20] ETR模式选择(ETR Mode Selection) */
+ __IOM uint32_t EE : 1; /*!< [22..22] ETR模式选择(ETR Mode Selection) */
+ uint32_t : 9;
+ } SCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t IER; /*!< (@ 0x0000000C) TMRx Interrupt Enable Register */
+
+ struct {
+ __IOM uint32_t CIE : 1; /*!< [0..0] 比较中断使能(Compare Interrupt Enable) */
+ uint32_t : 7;
+ __IOM uint32_t UIE : 1; /*!< [8..8] 更新中断使能(Update Interrupt Enable) */
+ uint32_t : 1;
+ __IOM uint32_t TIE : 1; /*!< [10..10] 触发中断使能(Trigger Interrupt Enable) */
+ uint32_t : 21;
+ } IER_b;
+ } ;
+
+ union {
+ __IOM uint32_t SR; /*!< (@ 0x00000010) TMRx Status Register */
+
+ struct {
+ __IOM uint32_t CIF : 1; /*!< [0..0] 比较成功中断标志位(Compare Interrupt Flag) */
+ uint32_t : 7;
+ __IOM uint32_t UIF : 1; /*!< [8..8] 更新中断标志(Update Interrupt Flag) */
+ uint32_t : 1;
+ __IOM uint32_t TIF : 1; /*!< [10..10] 触发中断标志(Trigger Interrupt Flag) */
+ uint32_t : 5;
+ __IM uint32_t PUS : 1; /*!< [16..16] 周期值更新标志（Period Update Status） */
+ __IM uint32_t CUS : 1; /*!< [17..17] 比较值更新标志（Compare Update Status） */
+ __IM uint32_t STS : 1; /*!< [18..18] 计数器状态标志（Counter Running Status） */
+ uint32_t : 13;
+ } SR_b;
+ } ;
+
+ union {
+ __IOM uint32_t UGR; /*!< (@ 0x00000014) TMRx Update Generation Register */
+
+ struct {
+ __IOM uint32_t UG : 1; /*!< [0..0] 更新事件生成(Update Generation) */
+ __IOM uint32_t TG : 1; /*!< [1..1] 触发事件生成(Trigger Generation) */
+ uint32_t : 2;
+ __IOM uint32_t CG : 1; /*!< [4..4] 比较更新事件生成(Compare Update Generation) */
+ uint32_t : 7;
+ __IOM uint32_t SG : 1; /*!< [12..12] 计数器启动事件生成(Counter Start Generation) */
+ uint32_t : 19;
+ } UGR_b;
+ } ;
+ __IM uint32_t RESERVED1[2];
+
+ union {
+ __IOM uint32_t CCMR; /*!< (@ 0x00000020) TMRx Compare Mode Register */
+
+ struct {
+ uint32_t : 2;
+ __IOM uint32_t RLD : 1; /*!< [2..2] 比较自动加载使能(Compare Auto-Realod Enable) */
+ uint32_t : 29;
+ } CCMR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CCER; /*!< (@ 0x00000024) TMRx Compare Enable Register */
+
+ struct {
+ __IOM uint32_t CCE : 1; /*!< [0..0] 比较通道使能(Compare Enable) */
+ uint32_t : 1;
+ __IOM uint32_t CCP : 1; /*!< [2..2] 比较极性选择(Compare Polarity) */
+ uint32_t : 29;
+ } CCER_b;
+ } ;
+ __IM uint32_t RESERVED2[2];
+
+ union {
+ __IOM uint32_t CPR; /*!< (@ 0x00000030) TMRx Counter Period Register */
+
+ struct {
+ __IOM uint32_t CPV : 16; /*!< [15..0] 计数周期值(Counter Period Value) */
+ uint32_t : 16;
+ } CPR_b;
+ } ;
+ __IM uint32_t RESERVED3;
+
+ union {
+ __IOM uint32_t PSCR; /*!< (@ 0x00000038) TMRx Prescaler Register */
+
+ struct {
+ __IOM uint32_t PSC : 8; /*!< [7..0] 预分频寄存器（Prescaler Value) */
+ uint32_t : 24;
+ } PSCR_b;
+ } ;
+
+ union {
+ __IOM uint32_t CNTR; /*!< (@ 0x0000003C) TMRx Counter Register */
+
+ struct {
+ __IM uint32_t CNT : 16; /*!< [15..0] 定时器计数值(Counter Value) */
+ uint32_t : 16;
+ } CNTR_b;
+ } ;
+ __IM uint32_t RESERVED4[4];
+
+ union {
+ __IOM uint32_t CC0R; /*!< (@ 0x00000050) TMRx Compare Register */
+
+ struct {
+ __IOM uint32_t CMP : 16; /*!< [15..0] 输出比较值(Compare Value) */
+ uint32_t : 16;
+ } CC0R_b;
+ } ;
+} TMR6_Type; /*!< Size = 84 (0x54) */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+#define XIF_BASE 0x40016000UL
+#define WWDG_BASE 0x4000D000UL
+#define USB_BASE 0x40035000UL
+#define UART0_BASE 0x40003000UL
+#define UART1_BASE 0x40004000UL
+#define UART2_BASE 0x40005000UL
+#define UART3_BASE 0x40010000UL
+#define UART4_BASE 0x40011000UL
+#define SYSCTRL_BASE 0x40021000UL
+#define SPI0_BASE 0x40012000UL
+#define SPI1_BASE 0x40013000UL
+#define RCU_BASE 0x40020000UL
+#define QEI0_BASE 0x4002D000UL
+#define QEI1_BASE 0x4002E000UL
+#define QEI2_BASE 0x4002F000UL
+#define PDM0_BASE 0x40017000UL
+#define PDM1_BASE 0x40017100UL
+#define PDM2_BASE 0x40017200UL
+#define PDM3_BASE 0x40017300UL
+#define IWDG_BASE 0x4000C000UL
+#define IIR0_BASE 0x4003E000UL
+#define IIR1_BASE 0x4003E100UL
+#define IIR2_BASE 0x4003E200UL
+#define IIR3_BASE 0x4003E300UL
+#define IIR4_BASE 0x4003E400UL
+#define IIR5_BASE 0x4003E500UL
+#define I2C0_BASE 0x40000000UL
+#define I2C1_BASE 0x40001000UL
+#define I2C2_BASE 0x40002000UL
+#define HRPWM_SLV0_BASE 0x4003B100UL
+#define HRPWM_SLV1_BASE 0x4003B200UL
+#define HRPWM_SLV2_BASE 0x4003B300UL
+#define HRPWM_SLV3_BASE 0x4003B400UL
+#define HRPWM_SLV4_BASE 0x4003B500UL
+#define HRPWM_SLV5_BASE 0x4003B600UL
+#define HRPWM_SLV6_BASE 0x4003B700UL
+#define HRPWM_SLV7_BASE 0x4003B800UL
+#define HRPWM_COM_BASE 0x4003BF00UL
+#define HRPWM_MST_BASE 0x4003B000UL
+#define TMR3_BASE 0x4002A000UL
+#define TMR4_BASE 0x4002B000UL
+#define TMR0_BASE 0x40018000UL
+#define TMR1_BASE 0x40019000UL
+#define TMR2_BASE 0x4001A000UL
+#define GPIOA_BASE 0x40024000UL
+#define GPIOB_BASE 0x40025000UL
+#define GPIOC_BASE 0x40026000UL
+#define GPIOD_BASE 0x40027000UL
+#define GPIOE_BASE 0x40028000UL
+#define GPIOF_BASE 0x40029000UL
+#define FLASH_BASE 0x40023000UL
+#define DMA0_BASE 0x40022000UL
+#define DMA1_BASE 0x40022020UL
+#define DMA2_BASE 0x40022040UL
+#define DMA3_BASE 0x40022060UL
+#define DMA4_BASE 0x40022080UL
+#define DMA5_BASE 0x400220A0UL
+#define DAC0_BASE 0x40039000UL
+#define DAC1_BASE 0x40039100UL
+#define DAC2_BASE 0x40039200UL
+#define DAC3_BASE 0x40039300UL
+#define DAC4_BASE 0x40039400UL
+#define DAC5_BASE 0x40039500UL
+#define DAC6_BASE 0x40039600UL
+#define DAC7_BASE 0x40039700UL
+#define DAC8_BASE 0x40039800UL
+#define CORDIC_BASE 0x4003F000UL
+#define CMP0_BASE 0x4003A000UL
+#define CMP1_BASE 0x4003A100UL
+#define CMP2_BASE 0x4003A200UL
+#define CMP3_BASE 0x4003A300UL
+#define CMP4_BASE 0x4003A400UL
+#define CMP5_BASE 0x4003A500UL
+#define CMP6_BASE 0x4003A600UL
+#define CMP7_BASE 0x4003A700UL
+#define CMP8_BASE 0x4003A800UL
+#define CAN0_BASE 0x40014000UL
+#define CAN1_BASE 0x40015000UL
+#define TMR7_BASE 0x40008000UL
+#define TMR8_BASE 0x40009000UL
+#define TMR9_BASE 0x40030000UL
+#define TMR10_BASE 0x40031000UL
+#define ADC0_BASE 0x40038000UL
+#define ADC1_BASE 0x40038400UL
+#define ADC2_BASE 0x40038800UL
+#define ADC3_BASE 0x40038C00UL
+#define TMR6_BASE 0x4000E000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+#define XIF ((XIF_Type*) XIF_BASE)
+#define WWDG ((WWDG_Type*) WWDG_BASE)
+#define USB ((USB_Type*) USB_BASE)
+#define UART0 ((UART0_Type*) UART0_BASE)
+#define UART1 ((UART1_Type*) UART1_BASE)
+#define UART2 ((UART2_Type*) UART2_BASE)
+#define UART3 ((UART3_Type*) UART3_BASE)
+#define UART4 ((UART4_Type*) UART4_BASE)
+#define SYSCTRL ((SYSCTRL_Type*) SYSCTRL_BASE)
+#define SPI0 ((SPI0_Type*) SPI0_BASE)
+#define SPI1 ((SPI1_Type*) SPI1_BASE)
+#define RCU ((RCU_Type*) RCU_BASE)
+#define QEI0 ((QEI0_Type*) QEI0_BASE)
+#define QEI1 ((QEI1_Type*) QEI1_BASE)
+#define QEI2 ((QEI2_Type*) QEI2_BASE)
+#define PDM0 ((PDM0_Type*) PDM0_BASE)
+#define PDM1 ((PDM1_Type*) PDM1_BASE)
+#define PDM2 ((PDM2_Type*) PDM2_BASE)
+#define PDM3 ((PDM3_Type*) PDM3_BASE)
+#define IWDG ((IWDG_Type*) IWDG_BASE)
+#define IIR0 ((IIR0_Type*) IIR0_BASE)
+#define IIR1 ((IIR1_Type*) IIR1_BASE)
+#define IIR2 ((IIR2_Type*) IIR2_BASE)
+#define IIR3 ((IIR3_Type*) IIR3_BASE)
+#define IIR4 ((IIR4_Type*) IIR4_BASE)
+#define IIR5 ((IIR5_Type*) IIR5_BASE)
+#define I2C0 ((I2C0_Type*) I2C0_BASE)
+#define I2C1 ((I2C1_Type*) I2C1_BASE)
+#define I2C2 ((I2C2_Type*) I2C2_BASE)
+#define HRPWM_SLV0 ((HRPWM_SLV0_Type*) HRPWM_SLV0_BASE)
+#define HRPWM_SLV1 ((HRPWM_SLV1_Type*) HRPWM_SLV1_BASE)
+#define HRPWM_SLV2 ((HRPWM_SLV2_Type*) HRPWM_SLV2_BASE)
+#define HRPWM_SLV3 ((HRPWM_SLV3_Type*) HRPWM_SLV3_BASE)
+#define HRPWM_SLV4 ((HRPWM_SLV4_Type*) HRPWM_SLV4_BASE)
+#define HRPWM_SLV5 ((HRPWM_SLV5_Type*) HRPWM_SLV5_BASE)
+#define HRPWM_SLV6 ((HRPWM_SLV6_Type*) HRPWM_SLV6_BASE)
+#define HRPWM_SLV7 ((HRPWM_SLV7_Type*) HRPWM_SLV7_BASE)
+#define HRPWM_COM ((HRPWM_COM_Type*) HRPWM_COM_BASE)
+#define HRPWM_MST ((HRPWM_MST_Type*) HRPWM_MST_BASE)
+#define TMR3 ((TMR3_Type*) TMR3_BASE)
+#define TMR4 ((TMR4_Type*) TMR4_BASE)
+#define TMR0 ((TMR0_Type*) TMR0_BASE)
+#define TMR1 ((TMR1_Type*) TMR1_BASE)
+#define TMR2 ((TMR2_Type*) TMR2_BASE)
+#define GPIOA ((GPIOA_Type*) GPIOA_BASE)
+#define GPIOB ((GPIOB_Type*) GPIOB_BASE)
+#define GPIOC ((GPIOC_Type*) GPIOC_BASE)
+#define GPIOD ((GPIOD_Type*) GPIOD_BASE)
+#define GPIOE ((GPIOE_Type*) GPIOE_BASE)
+#define GPIOF ((GPIOF_Type*) GPIOF_BASE)
+#define FLASH ((FLASH_Type*) FLASH_BASE)
+#define DMA0 ((DMA0_Type*) DMA0_BASE)
+#define DMA1 ((DMA1_Type*) DMA1_BASE)
+#define DMA2 ((DMA2_Type*) DMA2_BASE)
+#define DMA3 ((DMA3_Type*) DMA3_BASE)
+#define DMA4 ((DMA4_Type*) DMA4_BASE)
+#define DMA5 ((DMA5_Type*) DMA5_BASE)
+#define DAC0 ((DAC0_Type*) DAC0_BASE)
+#define DAC1 ((DAC1_Type*) DAC1_BASE)
+#define DAC2 ((DAC2_Type*) DAC2_BASE)
+#define DAC3 ((DAC3_Type*) DAC3_BASE)
+#define DAC4 ((DAC4_Type*) DAC4_BASE)
+#define DAC5 ((DAC5_Type*) DAC5_BASE)
+#define DAC6 ((DAC6_Type*) DAC6_BASE)
+#define DAC7 ((DAC7_Type*) DAC7_BASE)
+#define DAC8 ((DAC8_Type*) DAC8_BASE)
+#define CORDIC ((CORDIC_Type*) CORDIC_BASE)
+#define CMP0 ((CMP0_Type*) CMP0_BASE)
+#define CMP1 ((CMP1_Type*) CMP1_BASE)
+#define CMP2 ((CMP2_Type*) CMP2_BASE)
+#define CMP3 ((CMP3_Type*) CMP3_BASE)
+#define CMP4 ((CMP4_Type*) CMP4_BASE)
+#define CMP5 ((CMP5_Type*) CMP5_BASE)
+#define CMP6 ((CMP6_Type*) CMP6_BASE)
+#define CMP7 ((CMP7_Type*) CMP7_BASE)
+#define CMP8 ((CMP8_Type*) CMP8_BASE)
+#define CAN0 ((CAN0_Type*) CAN0_BASE)
+#define CAN1 ((CAN1_Type*) CAN1_BASE)
+#define TMR7 ((TMR7_Type*) TMR7_BASE)
+#define TMR8 ((TMR8_Type*) TMR8_BASE)
+#define TMR9 ((TMR9_Type*) TMR9_BASE)
+#define TMR10 ((TMR10_Type*) TMR10_BASE)
+#define ADC0 ((ADC0_Type*) ADC0_BASE)
+#define ADC1 ((ADC1_Type*) ADC1_BASE)
+#define ADC2 ((ADC2_Type*) ADC2_BASE)
+#define ADC3 ((ADC3_Type*) ADC3_BASE)
+#define TMR6 ((TMR6_Type*) TMR6_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+
+/* ========================================= End of section using anonymous unions ========================================= */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================ Pos/Mask Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup PosMask_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ XIF ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define XIF_ENABLE_DIR_Pos (5UL) /*!< DIR (Bit 5) */
+#define XIF_ENABLE_DIR_Msk (0x20UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define XIF_ENABLE_TXDEN_Pos (4UL) /*!< TXDEN (Bit 4) */
+#define XIF_ENABLE_TXDEN_Msk (0x10UL) /*!< TXDEN (Bitfield-Mask: 0x01) */
+#define XIF_ENABLE_RELOAD_Pos (3UL) /*!< RELOAD (Bit 3) */
+#define XIF_ENABLE_RELOAD_Msk (0x8UL) /*!< RELOAD (Bitfield-Mask: 0x01) */
+#define XIF_ENABLE_SRST_Pos (2UL) /*!< SRST (Bit 2) */
+#define XIF_ENABLE_SRST_Msk (0x4UL) /*!< SRST (Bitfield-Mask: 0x01) */
+#define XIF_ENABLE_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */
+#define XIF_ENABLE_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+#define XIF_ENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
+#define XIF_ENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define XIF_CTRL_TXDIE_Pos (26UL) /*!< TXDIE (Bit 26) */
+#define XIF_CTRL_TXDIE_Msk (0x4000000UL) /*!< TXDIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_TXEIE_Pos (24UL) /*!< TXEIE (Bit 24) */
+#define XIF_CTRL_TXEIE_Msk (0x1000000UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_TXFTLR_Pos (20UL) /*!< TXFTLR (Bit 20) */
+#define XIF_CTRL_TXFTLR_Msk (0x700000UL) /*!< TXFTLR (Bitfield-Mask: 0x07) */
+#define XIF_CTRL_DCS_Pos (16UL) /*!< DCS (Bit 16) */
+#define XIF_CTRL_DCS_Msk (0x70000UL) /*!< DCS (Bitfield-Mask: 0x07) */
+#define XIF_CTRL_BTOIE_Pos (15UL) /*!< BTOIE (Bit 15) */
+#define XIF_CTRL_BTOIE_Msk (0x8000UL) /*!< BTOIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_RXDIE_Pos (14UL) /*!< RXDIE (Bit 14) */
+#define XIF_CTRL_RXDIE_Msk (0x4000UL) /*!< RXDIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_RXOFIE_Pos (13UL) /*!< RXOFIE (Bit 13) */
+#define XIF_CTRL_RXOFIE_Msk (0x2000UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_RXFIE_Pos (12UL) /*!< RXFIE (Bit 12) */
+#define XIF_CTRL_RXFIE_Msk (0x1000UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+#define XIF_CTRL_RXFTLR_Pos (8UL) /*!< RXFTLR (Bit 8) */
+#define XIF_CTRL_RXFTLR_Msk (0x700UL) /*!< RXFTLR (Bitfield-Mask: 0x07) */
+#define XIF_CTRL_DCNT_Pos (0UL) /*!< DCNT (Bit 0) */
+#define XIF_CTRL_DCNT_Msk (0xffUL) /*!< DCNT (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMING ========================================================= */
+#define XIF_TIMING_RDHTIME_Pos (24UL) /*!< RDHTIME (Bit 24) */
+#define XIF_TIMING_RDHTIME_Msk (0xff000000UL) /*!< RDHTIME (Bitfield-Mask: 0xff) */
+#define XIF_TIMING_RDLTIME_Pos (16UL) /*!< RDLTIME (Bit 16) */
+#define XIF_TIMING_RDLTIME_Msk (0xff0000UL) /*!< RDLTIME (Bitfield-Mask: 0xff) */
+#define XIF_TIMING_CONLTIME_Pos (8UL) /*!< CONLTIME (Bit 8) */
+#define XIF_TIMING_CONLTIME_Msk (0xff00UL) /*!< CONLTIME (Bitfield-Mask: 0xff) */
+#define XIF_TIMING_RSTTIME_Pos (0UL) /*!< RSTTIME (Bit 0) */
+#define XIF_TIMING_RSTTIME_Msk (0xffUL) /*!< RSTTIME (Bitfield-Mask: 0xff) */
+/* ========================================================== TO =========================================================== */
+#define XIF_TO_PTOT_Pos (0UL) /*!< PTOT (Bit 0) */
+#define XIF_TO_PTOT_Msk (0xffffUL) /*!< PTOT (Bitfield-Mask: 0xffff) */
+/* ========================================================= DATA ========================================================== */
+#define XIF_DATA_DATA_Pos (0UL) /*!< DATA (Bit 0) */
+#define XIF_DATA_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
+/* ========================================================== ISR ========================================================== */
+#define XIF_ISR_TFF_Pos (21UL) /*!< TFF (Bit 21) */
+#define XIF_ISR_TFF_Msk (0x200000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define XIF_ISR_TFE_Pos (20UL) /*!< TFE (Bit 20) */
+#define XIF_ISR_TFE_Msk (0x100000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define XIF_ISR_TXDI_Pos (18UL) /*!< TXDI (Bit 18) */
+#define XIF_ISR_TXDI_Msk (0x40000UL) /*!< TXDI (Bitfield-Mask: 0x01) */
+#define XIF_ISR_TXEI_Pos (16UL) /*!< TXEI (Bit 16) */
+#define XIF_ISR_TXEI_Msk (0x10000UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define XIF_ISR_TXFLR_Pos (12UL) /*!< TXFLR (Bit 12) */
+#define XIF_ISR_TXFLR_Msk (0xf000UL) /*!< TXFLR (Bitfield-Mask: 0x0f) */
+#define XIF_ISR_RXFLR_Pos (8UL) /*!< RXFLR (Bit 8) */
+#define XIF_ISR_RXFLR_Msk (0xf00UL) /*!< RXFLR (Bitfield-Mask: 0x0f) */
+#define XIF_ISR_FF_Pos (5UL) /*!< FF (Bit 5) */
+#define XIF_ISR_FF_Msk (0x20UL) /*!< FF (Bitfield-Mask: 0x01) */
+#define XIF_ISR_FE_Pos (4UL) /*!< FE (Bit 4) */
+#define XIF_ISR_FE_Msk (0x10UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define XIF_ISR_BTOI_Pos (3UL) /*!< BTOI (Bit 3) */
+#define XIF_ISR_BTOI_Msk (0x8UL) /*!< BTOI (Bitfield-Mask: 0x01) */
+#define XIF_ISR_RXDI_Pos (2UL) /*!< RXDI (Bit 2) */
+#define XIF_ISR_RXDI_Msk (0x4UL) /*!< RXDI (Bitfield-Mask: 0x01) */
+#define XIF_ISR_RXOFI_Pos (1UL) /*!< RXOFI (Bit 1) */
+#define XIF_ISR_RXOFI_Msk (0x2UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define XIF_ISR_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define XIF_ISR_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ========================================================= WDATA ========================================================= */
+#define XIF_WDATA_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */
+#define XIF_WDATA_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ WWDG ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define WWDG_CR_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */
+#define WWDG_CR_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */
+#define WWDG_CR_WEN_Pos (0UL) /*!< WEN (Bit 0) */
+#define WWDG_CR_WEN_Msk (0x1UL) /*!< WEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WVR ========================================================== */
+#define WWDG_WVR_WV_Pos (0UL) /*!< WV (Bit 0) */
+#define WWDG_WVR_WV_Msk (0xffffUL) /*!< WV (Bitfield-Mask: 0xffff) */
+/* ========================================================== CVR ========================================================== */
+#define WWDG_CVR_CV_Pos (0UL) /*!< CV (Bit 0) */
+#define WWDG_CVR_CV_Msk (0xffffUL) /*!< CV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define WWDG_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define WWDG_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================== ISR ========================================================== */
+#define WWDG_ISR_EWIF_Pos (0UL) /*!< EWIF (Bit 0) */
+#define WWDG_ISR_EWIF_Msk (0x1UL) /*!< EWIF (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ USB ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CTRL ========================================================== */
+#define USB_CTRL_ISOUP_Pos (15UL) /*!< ISOUP (Bit 15) */
+#define USB_CTRL_ISOUP_Msk (0x8000UL) /*!< ISOUP (Bitfield-Mask: 0x01) */
+#define USB_CTRL_SCONN_Pos (14UL) /*!< SCONN (Bit 14) */
+#define USB_CTRL_SCONN_Msk (0x4000UL) /*!< SCONN (Bitfield-Mask: 0x01) */
+#define USB_CTRL_RESET_Pos (11UL) /*!< RESET (Bit 11) */
+#define USB_CTRL_RESET_Msk (0x800UL) /*!< RESET (Bitfield-Mask: 0x01) */
+#define USB_CTRL_RESUME_Pos (10UL) /*!< RESUME (Bit 10) */
+#define USB_CTRL_RESUME_Msk (0x400UL) /*!< RESUME (Bitfield-Mask: 0x01) */
+#define USB_CTRL_SUSMOD_Pos (9UL) /*!< SUSMOD (Bit 9) */
+#define USB_CTRL_SUSMOD_Msk (0x200UL) /*!< SUSMOD (Bitfield-Mask: 0x01) */
+#define USB_CTRL_FADDR_Pos (0UL) /*!< FADDR (Bit 0) */
+#define USB_CTRL_FADDR_Msk (0xffUL) /*!< FADDR (Bitfield-Mask: 0xff) */
+/* ========================================================= INDEX ========================================================= */
+#define USB_INDEX_INDEX_Pos (16UL) /*!< INDEX (Bit 16) */
+#define USB_INDEX_INDEX_Msk (0xf0000UL) /*!< INDEX (Bitfield-Mask: 0x0f) */
+#define USB_INDEX_FNUM_Pos (0UL) /*!< FNUM (Bit 0) */
+#define USB_INDEX_FNUM_Msk (0xffffUL) /*!< FNUM (Bitfield-Mask: 0xffff) */
+/* ======================================================== TX0CTRL ======================================================== */
+#define USB_TX0CTRL_FLFIFO_Pos (24UL) /*!< FLFIFO (Bit 24) */
+#define USB_TX0CTRL_FLFIFO_Msk (0x1000000UL) /*!< FLFIFO (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_SSECLR_Pos (23UL) /*!< SSECLR (Bit 23) */
+#define USB_TX0CTRL_SSECLR_Msk (0x800000UL) /*!< SSECLR (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_SRPCLR_Pos (22UL) /*!< SRPCLR (Bit 22) */
+#define USB_TX0CTRL_SRPCLR_Msk (0x400000UL) /*!< SRPCLR (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_SENDSTA_Pos (21UL) /*!< SENDSTA (Bit 21) */
+#define USB_TX0CTRL_SENDSTA_Msk (0x200000UL) /*!< SENDSTA (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_SETUPEND_Pos (20UL) /*!< SETUPEND (Bit 20) */
+#define USB_TX0CTRL_SETUPEND_Msk (0x100000UL) /*!< SETUPEND (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_DATAEND_Pos (19UL) /*!< DATAEND (Bit 19) */
+#define USB_TX0CTRL_DATAEND_Msk (0x80000UL) /*!< DATAEND (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_SENTSTA_Pos (18UL) /*!< SENTSTA (Bit 18) */
+#define USB_TX0CTRL_SENTSTA_Msk (0x40000UL) /*!< SENTSTA (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_TXPR_Pos (17UL) /*!< TXPR (Bit 17) */
+#define USB_TX0CTRL_TXPR_Msk (0x20000UL) /*!< TXPR (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_RXPR_Pos (16UL) /*!< RXPR (Bit 16) */
+#define USB_TX0CTRL_RXPR_Msk (0x10000UL) /*!< RXPR (Bitfield-Mask: 0x01) */
+#define USB_TX0CTRL_TXMAXP_Pos (0UL) /*!< TXMAXP (Bit 0) */
+#define USB_TX0CTRL_TXMAXP_Msk (0xffffUL) /*!< TXMAXP (Bitfield-Mask: 0xffff) */
+/* ======================================================== TXnCTRL ======================================================== */
+#define USB_TXnCTRL_AUTOSET_Pos (31UL) /*!< AUTOSET (Bit 31) */
+#define USB_TXnCTRL_AUTOSET_Msk (0x80000000UL) /*!< AUTOSET (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_ISO_Pos (30UL) /*!< ISO (Bit 30) */
+#define USB_TXnCTRL_ISO_Msk (0x40000000UL) /*!< ISO (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_MODE_Pos (29UL) /*!< MODE (Bit 29) */
+#define USB_TXnCTRL_MODE_Msk (0x20000000UL) /*!< MODE (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_FRCDATTOG_Pos (27UL) /*!< FRCDATTOG (Bit 27) */
+#define USB_TXnCTRL_FRCDATTOG_Msk (0x8000000UL) /*!< FRCDATTOG (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_CLRDT_Pos (22UL) /*!< CLRDT (Bit 22) */
+#define USB_TXnCTRL_CLRDT_Msk (0x400000UL) /*!< CLRDT (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_SENTSTA_Pos (21UL) /*!< SENTSTA (Bit 21) */
+#define USB_TXnCTRL_SENTSTA_Msk (0x200000UL) /*!< SENTSTA (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_SENDSTA_Pos (20UL) /*!< SENDSTA (Bit 20) */
+#define USB_TXnCTRL_SENDSTA_Msk (0x100000UL) /*!< SENDSTA (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_FLFIFO_Pos (19UL) /*!< FLFIFO (Bit 19) */
+#define USB_TXnCTRL_FLFIFO_Msk (0x80000UL) /*!< FLFIFO (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_UNRUN_Pos (18UL) /*!< UNRUN (Bit 18) */
+#define USB_TXnCTRL_UNRUN_Msk (0x40000UL) /*!< UNRUN (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_FIFONE_Pos (17UL) /*!< FIFONE (Bit 17) */
+#define USB_TXnCTRL_FIFONE_Msk (0x20000UL) /*!< FIFONE (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_TXPR_Pos (16UL) /*!< TXPR (Bit 16) */
+#define USB_TXnCTRL_TXPR_Msk (0x10000UL) /*!< TXPR (Bitfield-Mask: 0x01) */
+#define USB_TXnCTRL_TXMAXP_Pos (0UL) /*!< TXMAXP (Bit 0) */
+#define USB_TXnCTRL_TXMAXP_Msk (0xffffUL) /*!< TXMAXP (Bitfield-Mask: 0xffff) */
+/* ======================================================== RXCTRL ========================================================= */
+#define USB_RXCTRL_AUTOCLR_Pos (31UL) /*!< AUTOCLR (Bit 31) */
+#define USB_RXCTRL_AUTOCLR_Msk (0x80000000UL) /*!< AUTOCLR (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_ISO_Pos (30UL) /*!< ISO (Bit 30) */
+#define USB_RXCTRL_ISO_Msk (0x40000000UL) /*!< ISO (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_INCRX_Pos (24UL) /*!< INCRX (Bit 24) */
+#define USB_RXCTRL_INCRX_Msk (0x1000000UL) /*!< INCRX (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_CDATTOG_Pos (23UL) /*!< CDATTOG (Bit 23) */
+#define USB_RXCTRL_CDATTOG_Msk (0x800000UL) /*!< CDATTOG (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_SENTSTA_Pos (22UL) /*!< SENTSTA (Bit 22) */
+#define USB_RXCTRL_SENTSTA_Msk (0x400000UL) /*!< SENTSTA (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_SENDSTA_Pos (21UL) /*!< SENDSTA (Bit 21) */
+#define USB_RXCTRL_SENDSTA_Msk (0x200000UL) /*!< SENDSTA (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_FLFIFO_Pos (20UL) /*!< FLFIFO (Bit 20) */
+#define USB_RXCTRL_FLFIFO_Msk (0x100000UL) /*!< FLFIFO (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_DATAERR_Pos (19UL) /*!< DATAERR (Bit 19) */
+#define USB_RXCTRL_DATAERR_Msk (0x80000UL) /*!< DATAERR (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_OVERRUN_Pos (18UL) /*!< OVERRUN (Bit 18) */
+#define USB_RXCTRL_OVERRUN_Msk (0x40000UL) /*!< OVERRUN (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_FIFOFULL_Pos (17UL) /*!< FIFOFULL (Bit 17) */
+#define USB_RXCTRL_FIFOFULL_Msk (0x20000UL) /*!< FIFOFULL (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_RXPR_Pos (16UL) /*!< RXPR (Bit 16) */
+#define USB_RXCTRL_RXPR_Msk (0x10000UL) /*!< RXPR (Bitfield-Mask: 0x01) */
+#define USB_RXCTRL_RXMAXP_Pos (0UL) /*!< RXMAXP (Bit 0) */
+#define USB_RXCTRL_RXMAXP_Msk (0xffffUL) /*!< RXMAXP (Bitfield-Mask: 0xffff) */
+/* ======================================================== RXCOUNT ======================================================== */
+#define USB_RXCOUNT_RXCOUNT_Pos (0UL) /*!< RXCOUNT (Bit 0) */
+#define USB_RXCOUNT_RXCOUNT_Msk (0x3fffUL) /*!< RXCOUNT (Bitfield-Mask: 0x3fff) */
+/* ======================================================= FIFOSIZE ======================================================== */
+#define USB_FIFOSIZE_RXFIFOSIZE_Pos (28UL) /*!< RXFIFOSIZE (Bit 28) */
+#define USB_FIFOSIZE_RXFIFOSIZE_Msk (0xf0000000UL) /*!< RXFIFOSIZE (Bitfield-Mask: 0x0f) */
+#define USB_FIFOSIZE_TXFIFOSIZE_Pos (24UL) /*!< TXFIFOSIZE (Bit 24) */
+#define USB_FIFOSIZE_TXFIFOSIZE_Msk (0xf000000UL) /*!< TXFIFOSIZE (Bitfield-Mask: 0x0f) */
+/* ======================================================== FIFOSZ ========================================================= */
+#define USB_FIFOSZ_RXDPB_Pos (28UL) /*!< RXDPB (Bit 28) */
+#define USB_FIFOSZ_RXDPB_Msk (0x10000000UL) /*!< RXDPB (Bitfield-Mask: 0x01) */
+#define USB_FIFOSZ_RXSZ_Pos (24UL) /*!< RXSZ (Bit 24) */
+#define USB_FIFOSZ_RXSZ_Msk (0xf000000UL) /*!< RXSZ (Bitfield-Mask: 0x0f) */
+#define USB_FIFOSZ_TXDPB_Pos (20UL) /*!< TXDPB (Bit 20) */
+#define USB_FIFOSZ_TXDPB_Msk (0x100000UL) /*!< TXDPB (Bitfield-Mask: 0x01) */
+#define USB_FIFOSZ_TXSZ_Pos (16UL) /*!< TXSZ (Bit 16) */
+#define USB_FIFOSZ_TXSZ_Msk (0xf0000UL) /*!< TXSZ (Bitfield-Mask: 0x0f) */
+/* ======================================================== FIFOAD ========================================================= */
+#define USB_FIFOAD_RXAD_Pos (16UL) /*!< RXAD (Bit 16) */
+#define USB_FIFOAD_RXAD_Msk (0x1fff0000UL) /*!< RXAD (Bitfield-Mask: 0x1fff) */
+#define USB_FIFOAD_TXAD_Pos (0UL) /*!< TXAD (Bit 0) */
+#define USB_FIFOAD_TXAD_Msk (0x1fffUL) /*!< TXAD (Bitfield-Mask: 0x1fff) */
+/* ======================================================== PINCTRL ======================================================== */
+#define USB_PINCTRL_DMOE_Pos (31UL) /*!< DMOE (Bit 31) */
+#define USB_PINCTRL_DMOE_Msk (0x80000000UL) /*!< DMOE (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMOE_EN_Pos (30UL) /*!< DMOE_EN (Bit 30) */
+#define USB_PINCTRL_DMOE_EN_Msk (0x40000000UL) /*!< DMOE_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPOE_Pos (29UL) /*!< DPOE (Bit 29) */
+#define USB_PINCTRL_DPOE_Msk (0x20000000UL) /*!< DPOE (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPOE_EN_Pos (28UL) /*!< DPOE_EN (Bit 28) */
+#define USB_PINCTRL_DPOE_EN_Msk (0x10000000UL) /*!< DPOE_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMIE_Pos (27UL) /*!< DMIE (Bit 27) */
+#define USB_PINCTRL_DMIE_Msk (0x8000000UL) /*!< DMIE (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMIE_EN_Pos (26UL) /*!< DMIE_EN (Bit 26) */
+#define USB_PINCTRL_DMIE_EN_Msk (0x4000000UL) /*!< DMIE_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPIE_Pos (25UL) /*!< DPIE (Bit 25) */
+#define USB_PINCTRL_DPIE_Msk (0x2000000UL) /*!< DPIE (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPIE_EN_Pos (24UL) /*!< DPIE_EN (Bit 24) */
+#define USB_PINCTRL_DPIE_EN_Msk (0x1000000UL) /*!< DPIE_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMSR_Pos (23UL) /*!< DMSR (Bit 23) */
+#define USB_PINCTRL_DMSR_Msk (0x800000UL) /*!< DMSR (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMTRIM_Pos (20UL) /*!< DMTRIM (Bit 20) */
+#define USB_PINCTRL_DMTRIM_Msk (0x700000UL) /*!< DMTRIM (Bitfield-Mask: 0x07) */
+#define USB_PINCTRL_DPSR_Pos (19UL) /*!< DPSR (Bit 19) */
+#define USB_PINCTRL_DPSR_Msk (0x80000UL) /*!< DPSR (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPTRIM_Pos (16UL) /*!< DPTRIM (Bit 16) */
+#define USB_PINCTRL_DPTRIM_Msk (0x70000UL) /*!< DPTRIM (Bitfield-Mask: 0x07) */
+#define USB_PINCTRL_DMPD_Pos (15UL) /*!< DMPD (Bit 15) */
+#define USB_PINCTRL_DMPD_Msk (0x8000UL) /*!< DMPD (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMPD_EN_Pos (14UL) /*!< DMPD_EN (Bit 14) */
+#define USB_PINCTRL_DMPD_EN_Msk (0x4000UL) /*!< DMPD_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMPU_Pos (13UL) /*!< DMPU (Bit 13) */
+#define USB_PINCTRL_DMPU_Msk (0x2000UL) /*!< DMPU (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DMPU_EN_Pos (12UL) /*!< DMPU_EN (Bit 12) */
+#define USB_PINCTRL_DMPU_EN_Msk (0x1000UL) /*!< DMPU_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPPD_Pos (11UL) /*!< DPPD (Bit 11) */
+#define USB_PINCTRL_DPPD_Msk (0x800UL) /*!< DPPD (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPPD_EN_Pos (10UL) /*!< DPPD_EN (Bit 10) */
+#define USB_PINCTRL_DPPD_EN_Msk (0x400UL) /*!< DPPD_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPPU_Pos (9UL) /*!< DPPU (Bit 9) */
+#define USB_PINCTRL_DPPU_Msk (0x200UL) /*!< DPPU (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_DPPU_EN_Pos (8UL) /*!< DPPU_EN (Bit 8) */
+#define USB_PINCTRL_DPPU_EN_Msk (0x100UL) /*!< DPPU_EN (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_Test_En_Pos (6UL) /*!< Test_En (Bit 6) */
+#define USB_PINCTRL_Test_En_Msk (0x40UL) /*!< Test_En (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_VBUSVALID_Pos (5UL) /*!< VBUSVALID (Bit 5) */
+#define USB_PINCTRL_VBUSVALID_Msk (0x20UL) /*!< VBUSVALID (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_AVALID_Pos (4UL) /*!< AVALID (Bit 4) */
+#define USB_PINCTRL_AVALID_Msk (0x10UL) /*!< AVALID (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_VBUSLO_Pos (3UL) /*!< VBUSLO (Bit 3) */
+#define USB_PINCTRL_VBUSLO_Msk (0x8UL) /*!< VBUSLO (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_CID_Pos (2UL) /*!< CID (Bit 2) */
+#define USB_PINCTRL_CID_Msk (0x4UL) /*!< CID (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_TM1_Pos (1UL) /*!< TM1 (Bit 1) */
+#define USB_PINCTRL_TM1_Msk (0x2UL) /*!< TM1 (Bitfield-Mask: 0x01) */
+#define USB_PINCTRL_PHY_EN_Pos (0UL) /*!< PHY_EN (Bit 0) */
+#define USB_PINCTRL_PHY_EN_Msk (0x1UL) /*!< PHY_EN (Bitfield-Mask: 0x01) */
+/* ======================================================= IUINTREN ======================================================== */
+#define USB_IUINTREN_DETDB_Pos (4UL) /*!< DETDB (Bit 4) */
+#define USB_IUINTREN_DETDB_Msk (0xfff0UL) /*!< DETDB (Bitfield-Mask: 0xfff) */
+#define USB_IUINTREN_UPDETIEN_Pos (1UL) /*!< UPDETIEN (Bit 1) */
+#define USB_IUINTREN_UPDETIEN_Msk (0x2UL) /*!< UPDETIEN (Bitfield-Mask: 0x01) */
+#define USB_IUINTREN_ISDETIEN_Pos (0UL) /*!< ISDETIEN (Bit 0) */
+#define USB_IUINTREN_ISDETIEN_Msk (0x1UL) /*!< ISDETIEN (Bitfield-Mask: 0x01) */
+/* ======================================================= EPINTREN ======================================================== */
+#define USB_EPINTREN_EP2RXINTEN_Pos (18UL) /*!< EP2RXINTEN (Bit 18) */
+#define USB_EPINTREN_EP2RXINTEN_Msk (0x40000UL) /*!< EP2RXINTEN (Bitfield-Mask: 0x01) */
+#define USB_EPINTREN_EP1RXINTEN_Pos (17UL) /*!< EP1RXINTEN (Bit 17) */
+#define USB_EPINTREN_EP1RXINTEN_Msk (0x20000UL) /*!< EP1RXINTEN (Bitfield-Mask: 0x01) */
+#define USB_EPINTREN_EP2TXINTEN_Pos (2UL) /*!< EP2TXINTEN (Bit 2) */
+#define USB_EPINTREN_EP2TXINTEN_Msk (0x4UL) /*!< EP2TXINTEN (Bitfield-Mask: 0x01) */
+#define USB_EPINTREN_EP1TXINTEN_Pos (1UL) /*!< EP1TXINTEN (Bit 1) */
+#define USB_EPINTREN_EP1TXINTEN_Msk (0x2UL) /*!< EP1TXINTEN (Bitfield-Mask: 0x01) */
+#define USB_EPINTREN_EP0INTEN_Pos (0UL) /*!< EP0INTEN (Bit 0) */
+#define USB_EPINTREN_EP0INTEN_Msk (0x1UL) /*!< EP0INTEN (Bitfield-Mask: 0x01) */
+/* ======================================================= USBINTREN ======================================================= */
+#define USB_USBINTREN_DISCONINTEN_Pos (5UL) /*!< DISCONINTEN (Bit 5) */
+#define USB_USBINTREN_DISCONINTEN_Msk (0x20UL) /*!< DISCONINTEN (Bitfield-Mask: 0x01) */
+#define USB_USBINTREN_SOFINTEN_Pos (3UL) /*!< SOFINTEN (Bit 3) */
+#define USB_USBINTREN_SOFINTEN_Msk (0x8UL) /*!< SOFINTEN (Bitfield-Mask: 0x01) */
+#define USB_USBINTREN_RESETINTEN_Pos (2UL) /*!< RESETINTEN (Bit 2) */
+#define USB_USBINTREN_RESETINTEN_Msk (0x4UL) /*!< RESETINTEN (Bitfield-Mask: 0x01) */
+#define USB_USBINTREN_RESUMEINTEN_Pos (1UL) /*!< RESUMEINTEN (Bit 1) */
+#define USB_USBINTREN_RESUMEINTEN_Msk (0x2UL) /*!< RESUMEINTEN (Bitfield-Mask: 0x01) */
+#define USB_USBINTREN_SUSPENDINTEN_Pos (0UL) /*!< SUSPENDINTEN (Bit 0) */
+#define USB_USBINTREN_SUSPENDINTEN_Msk (0x1UL) /*!< SUSPENDINTEN (Bitfield-Mask: 0x01) */
+/* ======================================================== IUINTR ========================================================= */
+#define USB_IUINTR_UPDETI_Pos (1UL) /*!< UPDETI (Bit 1) */
+#define USB_IUINTR_UPDETI_Msk (0x2UL) /*!< UPDETI (Bitfield-Mask: 0x01) */
+#define USB_IUINTR_ISDETI_Pos (0UL) /*!< ISDETI (Bit 0) */
+#define USB_IUINTR_ISDETI_Msk (0x1UL) /*!< ISDETI (Bitfield-Mask: 0x01) */
+/* ======================================================== EPINTR ========================================================= */
+#define USB_EPINTR_EP2RXINT_Pos (18UL) /*!< EP2RXINT (Bit 18) */
+#define USB_EPINTR_EP2RXINT_Msk (0x40000UL) /*!< EP2RXINT (Bitfield-Mask: 0x01) */
+#define USB_EPINTR_EP1RXINT_Pos (17UL) /*!< EP1RXINT (Bit 17) */
+#define USB_EPINTR_EP1RXINT_Msk (0x20000UL) /*!< EP1RXINT (Bitfield-Mask: 0x01) */
+#define USB_EPINTR_EP2TXINT_Pos (2UL) /*!< EP2TXINT (Bit 2) */
+#define USB_EPINTR_EP2TXINT_Msk (0x4UL) /*!< EP2TXINT (Bitfield-Mask: 0x01) */
+#define USB_EPINTR_EP1TXINT_Pos (1UL) /*!< EP1TXINT (Bit 1) */
+#define USB_EPINTR_EP1TXINT_Msk (0x2UL) /*!< EP1TXINT (Bitfield-Mask: 0x01) */
+#define USB_EPINTR_EP0INT_Pos (0UL) /*!< EP0INT (Bit 0) */
+#define USB_EPINTR_EP0INT_Msk (0x1UL) /*!< EP0INT (Bitfield-Mask: 0x01) */
+/* ======================================================== USBINTR ======================================================== */
+#define USB_USBINTR_DISCON_Pos (5UL) /*!< DISCON (Bit 5) */
+#define USB_USBINTR_DISCON_Msk (0x20UL) /*!< DISCON (Bitfield-Mask: 0x01) */
+#define USB_USBINTR_SOF_Pos (3UL) /*!< SOF (Bit 3) */
+#define USB_USBINTR_SOF_Msk (0x8UL) /*!< SOF (Bitfield-Mask: 0x01) */
+#define USB_USBINTR_RESET_Pos (2UL) /*!< RESET (Bit 2) */
+#define USB_USBINTR_RESET_Msk (0x4UL) /*!< RESET (Bitfield-Mask: 0x01) */
+#define USB_USBINTR_RESUME_Pos (1UL) /*!< RESUME (Bit 1) */
+#define USB_USBINTR_RESUME_Msk (0x2UL) /*!< RESUME (Bitfield-Mask: 0x01) */
+#define USB_USBINTR_SUSPEND_Pos (0UL) /*!< SUSPEND (Bit 0) */
+#define USB_USBINTR_SUSPEND_Msk (0x1UL) /*!< SUSPEND (Bitfield-Mask: 0x01) */
+/* ========================================================= FIFO0 ========================================================= */
+#define USB_FIFO0_FIFO0_Pos (0UL) /*!< FIFO0 (Bit 0) */
+#define USB_FIFO0_FIFO0_Msk (0xffffffffUL) /*!< FIFO0 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= FIFO1 ========================================================= */
+#define USB_FIFO1_FIFO1_Pos (0UL) /*!< FIFO1 (Bit 0) */
+#define USB_FIFO1_FIFO1_Msk (0xffffffffUL) /*!< FIFO1 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= FIFO2 ========================================================= */
+#define USB_FIFO2_FIFO2_Pos (0UL) /*!< FIFO2 (Bit 0) */
+#define USB_FIFO2_FIFO2_Msk (0xffffffffUL) /*!< FIFO2 (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define UART0_CR0_ABRM_Pos (20UL) /*!< ABRM (Bit 20) */
+#define UART0_CR0_ABRM_Msk (0x300000UL) /*!< ABRM (Bitfield-Mask: 0x03) */
+#define UART0_CR0_OVDIS_Pos (17UL) /*!< OVDIS (Bit 17) */
+#define UART0_CR0_OVDIS_Msk (0x20000UL) /*!< OVDIS (Bitfield-Mask: 0x01) */
+#define UART0_CR0_LOOP_Pos (16UL) /*!< LOOP (Bit 16) */
+#define UART0_CR0_LOOP_Msk (0x10000UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define UART0_CR0_ONEBIT_Pos (15UL) /*!< ONEBIT (Bit 15) */
+#define UART0_CR0_ONEBIT_Msk (0x8000UL) /*!< ONEBIT (Bitfield-Mask: 0x01) */
+#define UART0_CR0_RTOM_Pos (14UL) /*!< RTOM (Bit 14) */
+#define UART0_CR0_RTOM_Msk (0x4000UL) /*!< RTOM (Bitfield-Mask: 0x01) */
+#define UART0_CR0_NFE_Pos (13UL) /*!< NFE (Bit 13) */
+#define UART0_CR0_NFE_Msk (0x2000UL) /*!< NFE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_OVER8_Pos (12UL) /*!< OVER8 (Bit 12) */
+#define UART0_CR0_OVER8_Msk (0x1000UL) /*!< OVER8 (Bitfield-Mask: 0x01) */
+#define UART0_CR0_RTOE_Pos (11UL) /*!< RTOE (Bit 11) */
+#define UART0_CR0_RTOE_Msk (0x800UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_TPOL_Pos (10UL) /*!< TPOL (Bit 10) */
+#define UART0_CR0_TPOL_Msk (0x400UL) /*!< TPOL (Bitfield-Mask: 0x01) */
+#define UART0_CR0_RPOL_Pos (9UL) /*!< RPOL (Bit 9) */
+#define UART0_CR0_RPOL_Msk (0x200UL) /*!< RPOL (Bitfield-Mask: 0x01) */
+#define UART0_CR0_SWAP_Pos (8UL) /*!< SWAP (Bit 8) */
+#define UART0_CR0_SWAP_Msk (0x100UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define UART0_CR0_OWE_Pos (7UL) /*!< OWE (Bit 7) */
+#define UART0_CR0_OWE_Msk (0x80UL) /*!< OWE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_DTE_Pos (6UL) /*!< DTE (Bit 6) */
+#define UART0_CR0_DTE_Msk (0x40UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_DRE_Pos (5UL) /*!< DRE (Bit 5) */
+#define UART0_CR0_DRE_Msk (0x20UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_TFR_Pos (4UL) /*!< TFR (Bit 4) */
+#define UART0_CR0_TFR_Msk (0x10UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define UART0_CR0_RFR_Pos (3UL) /*!< RFR (Bit 3) */
+#define UART0_CR0_RFR_Msk (0x8UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define UART0_CR0_TE_Pos (2UL) /*!< TE (Bit 2) */
+#define UART0_CR0_TE_Msk (0x4UL) /*!< TE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_RE_Pos (1UL) /*!< RE (Bit 1) */
+#define UART0_CR0_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
+#define UART0_CR0_UE_Pos (0UL) /*!< UE (Bit 0) */
+#define UART0_CR0_UE_Msk (0x1UL) /*!< UE (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define UART0_CR1_ABR_Pos (21UL) /*!< ABR (Bit 21) */
+#define UART0_CR1_ABR_Msk (0x200000UL) /*!< ABR (Bitfield-Mask: 0x01) */
+#define UART0_CR1_IDR_Pos (20UL) /*!< IDR (Bit 20) */
+#define UART0_CR1_IDR_Msk (0x100000UL) /*!< IDR (Bitfield-Mask: 0x01) */
+#define UART0_CR1_BKR_Pos (19UL) /*!< BKR (Bit 19) */
+#define UART0_CR1_BKR_Msk (0x80000UL) /*!< BKR (Bitfield-Mask: 0x01) */
+#define UART0_CR1_TEM_Pos (18UL) /*!< TEM (Bit 18) */
+#define UART0_CR1_TEM_Msk (0x40000UL) /*!< TEM (Bitfield-Mask: 0x01) */
+#define UART0_CR1_REM_Pos (17UL) /*!< REM (Bit 17) */
+#define UART0_CR1_REM_Msk (0x20000UL) /*!< REM (Bitfield-Mask: 0x01) */
+#define UART0_CR1_EBE_Pos (16UL) /*!< EBE (Bit 16) */
+#define UART0_CR1_EBE_Msk (0x10000UL) /*!< EBE (Bitfield-Mask: 0x01) */
+#define UART0_CR1_DEP_Pos (10UL) /*!< DEP (Bit 10) */
+#define UART0_CR1_DEP_Msk (0x400UL) /*!< DEP (Bitfield-Mask: 0x01) */
+#define UART0_CR1_REP_Pos (9UL) /*!< REP (Bit 9) */
+#define UART0_CR1_REP_Msk (0x200UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define UART0_CR1_RS485E_Pos (8UL) /*!< RS485E (Bit 8) */
+#define UART0_CR1_RS485E_Msk (0x100UL) /*!< RS485E (Bitfield-Mask: 0x01) */
+#define UART0_CR1_MSB_Pos (7UL) /*!< MSB (Bit 7) */
+#define UART0_CR1_MSB_Msk (0x80UL) /*!< MSB (Bitfield-Mask: 0x01) */
+#define UART0_CR1_SPE_Pos (5UL) /*!< SPE (Bit 5) */
+#define UART0_CR1_SPE_Msk (0x20UL) /*!< SPE (Bitfield-Mask: 0x01) */
+#define UART0_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
+#define UART0_CR1_PSEL_Msk (0x10UL) /*!< PSEL (Bitfield-Mask: 0x01) */
+#define UART0_CR1_PEN_Pos (3UL) /*!< PEN (Bit 3) */
+#define UART0_CR1_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
+#define UART0_CR1_STP_Pos (2UL) /*!< STP (Bit 2) */
+#define UART0_CR1_STP_Msk (0x4UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define UART0_CR1_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+#define UART0_CR1_LEN_Msk (0x3UL) /*!< LEN (Bitfield-Mask: 0x03) */
+/* ========================================================= BAUD ========================================================== */
+#define UART0_BAUD_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define UART0_BAUD_BAUD_Msk (0xffffUL) /*!< BAUD (Bitfield-Mask: 0xffff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define UART0_FIFOCTRL_TXFT_Pos (4UL) /*!< TXFT (Bit 4) */
+#define UART0_FIFOCTRL_TXFT_Msk (0xf0UL) /*!< TXFT (Bitfield-Mask: 0x0f) */
+#define UART0_FIFOCTRL_RXFT_Pos (0UL) /*!< RXFT (Bit 0) */
+#define UART0_FIFOCTRL_RXFT_Msk (0xfUL) /*!< RXFT (Bitfield-Mask: 0x0f) */
+/* ======================================================== TIMING0 ======================================================== */
+#define UART0_TIMING0_DEDT_Pos (16UL) /*!< DEDT (Bit 16) */
+#define UART0_TIMING0_DEDT_Msk (0xffff0000UL) /*!< DEDT (Bitfield-Mask: 0xffff) */
+#define UART0_TIMING0_DEAT_Pos (0UL) /*!< DEAT (Bit 0) */
+#define UART0_TIMING0_DEAT_Msk (0xffffUL) /*!< DEAT (Bitfield-Mask: 0xffff) */
+/* ======================================================== TIMING1 ======================================================== */
+#define UART0_TIMING1_DRET_Pos (16UL) /*!< DRET (Bit 16) */
+#define UART0_TIMING1_DRET_Msk (0xffff0000UL) /*!< DRET (Bitfield-Mask: 0xffff) */
+#define UART0_TIMING1_RDET_Pos (0UL) /*!< RDET (Bit 0) */
+#define UART0_TIMING1_RDET_Msk (0xffffUL) /*!< RDET (Bitfield-Mask: 0xffff) */
+/* ========================================================== TDR ========================================================== */
+#define UART0_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define UART0_TDR_TD_Msk (0x1ffUL) /*!< TD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== RDR ========================================================== */
+#define UART0_RDR_OVDA_Pos (16UL) /*!< OVDA (Bit 16) */
+#define UART0_RDR_OVDA_Msk (0x7ff0000UL) /*!< OVDA (Bitfield-Mask: 0x7ff) */
+#define UART0_RDR_FMST_Pos (10UL) /*!< FMST (Bit 10) */
+#define UART0_RDR_FMST_Msk (0x400UL) /*!< FMST (Bitfield-Mask: 0x01) */
+#define UART0_RDR_PRST_Pos (9UL) /*!< PRST (Bit 9) */
+#define UART0_RDR_PRST_Msk (0x200UL) /*!< PRST (Bitfield-Mask: 0x01) */
+#define UART0_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define UART0_RDR_RD_Msk (0x1ffUL) /*!< RD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== TAR ========================================================== */
+#define UART0_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define UART0_TAR_TAR_Msk (0xffUL) /*!< TAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RAR ========================================================== */
+#define UART0_RAR_RAR_Pos (0UL) /*!< RAR (Bit 0) */
+#define UART0_RAR_RAR_Msk (0xffUL) /*!< RAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RTO ========================================================== */
+#define UART0_RTO_RTO_Pos (0UL) /*!< RTO (Bit 0) */
+#define UART0_RTO_RTO_Msk (0xffffUL) /*!< RTO (Bitfield-Mask: 0xffff) */
+/* ========================================================= INTEN ========================================================= */
+#define UART0_INTEN_ABRE_Pos (16UL) /*!< ABRE (Bit 16) */
+#define UART0_INTEN_ABRE_Msk (0x10000UL) /*!< ABRE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_AMIE_Pos (15UL) /*!< AMIE (Bit 15) */
+#define UART0_INTEN_AMIE_Msk (0x8000UL) /*!< AMIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_IDLE_Pos (14UL) /*!< IDLE (Bit 14) */
+#define UART0_INTEN_IDLE_Msk (0x4000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_TBIE_Pos (13UL) /*!< TBIE (Bit 13) */
+#define UART0_INTEN_TBIE_Msk (0x2000UL) /*!< TBIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_TDIE_Pos (12UL) /*!< TDIE (Bit 12) */
+#define UART0_INTEN_TDIE_Msk (0x1000UL) /*!< TDIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_RTIE_Pos (11UL) /*!< RTIE (Bit 11) */
+#define UART0_INTEN_RTIE_Msk (0x800UL) /*!< RTIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_BKIE_Pos (10UL) /*!< BKIE (Bit 10) */
+#define UART0_INTEN_BKIE_Msk (0x400UL) /*!< BKIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_FEIE_Pos (9UL) /*!< FEIE (Bit 9) */
+#define UART0_INTEN_FEIE_Msk (0x200UL) /*!< FEIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_PEIE_Pos (8UL) /*!< PEIE (Bit 8) */
+#define UART0_INTEN_PEIE_Msk (0x100UL) /*!< PEIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_NOIE_Pos (7UL) /*!< NOIE (Bit 7) */
+#define UART0_INTEN_NOIE_Msk (0x80UL) /*!< NOIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_IDIE_Pos (6UL) /*!< IDIE (Bit 6) */
+#define UART0_INTEN_IDIE_Msk (0x40UL) /*!< IDIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_TOIE_Pos (4UL) /*!< TOIE (Bit 4) */
+#define UART0_INTEN_TOIE_Msk (0x10UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_RUIE_Pos (3UL) /*!< RUIE (Bit 3) */
+#define UART0_INTEN_RUIE_Msk (0x8UL) /*!< RUIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_ROIE_Pos (2UL) /*!< ROIE (Bit 2) */
+#define UART0_INTEN_ROIE_Msk (0x4UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_TEIE_Pos (1UL) /*!< TEIE (Bit 1) */
+#define UART0_INTEN_TEIE_Msk (0x2UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define UART0_INTEN_RFIE_Pos (0UL) /*!< RFIE (Bit 0) */
+#define UART0_INTEN_RFIE_Msk (0x1UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define UART0_INT_ABRF_Pos (16UL) /*!< ABRF (Bit 16) */
+#define UART0_INT_ABRF_Msk (0x10000UL) /*!< ABRF (Bitfield-Mask: 0x01) */
+#define UART0_INT_AMIF_Pos (15UL) /*!< AMIF (Bit 15) */
+#define UART0_INT_AMIF_Msk (0x8000UL) /*!< AMIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_IDLF_Pos (14UL) /*!< IDLF (Bit 14) */
+#define UART0_INT_IDLF_Msk (0x4000UL) /*!< IDLF (Bitfield-Mask: 0x01) */
+#define UART0_INT_TBIF_Pos (13UL) /*!< TBIF (Bit 13) */
+#define UART0_INT_TBIF_Msk (0x2000UL) /*!< TBIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_TDIF_Pos (12UL) /*!< TDIF (Bit 12) */
+#define UART0_INT_TDIF_Msk (0x1000UL) /*!< TDIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_RTOI_Pos (11UL) /*!< RTOI (Bit 11) */
+#define UART0_INT_RTOI_Msk (0x800UL) /*!< RTOI (Bitfield-Mask: 0x01) */
+#define UART0_INT_BKIF_Pos (10UL) /*!< BKIF (Bit 10) */
+#define UART0_INT_BKIF_Msk (0x400UL) /*!< BKIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_FEIF_Pos (9UL) /*!< FEIF (Bit 9) */
+#define UART0_INT_FEIF_Msk (0x200UL) /*!< FEIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_PEIF_Pos (8UL) /*!< PEIF (Bit 8) */
+#define UART0_INT_PEIF_Msk (0x100UL) /*!< PEIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_NOIF_Pos (7UL) /*!< NOIF (Bit 7) */
+#define UART0_INT_NOIF_Msk (0x80UL) /*!< NOIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_IDIF_Pos (6UL) /*!< IDIF (Bit 6) */
+#define UART0_INT_IDIF_Msk (0x40UL) /*!< IDIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_TOIF_Pos (4UL) /*!< TOIF (Bit 4) */
+#define UART0_INT_TOIF_Msk (0x10UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_RUIF_Pos (3UL) /*!< RUIF (Bit 3) */
+#define UART0_INT_RUIF_Msk (0x8UL) /*!< RUIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_ROIF_Pos (2UL) /*!< ROIF (Bit 2) */
+#define UART0_INT_ROIF_Msk (0x4UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define UART0_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define UART0_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define UART0_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define UART0_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define UART0_STATUS_RSE_Pos (16UL) /*!< RSE (Bit 16) */
+#define UART0_STATUS_RSE_Msk (0x10000UL) /*!< RSE (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_RFL_Pos (11UL) /*!< RFL (Bit 11) */
+#define UART0_STATUS_RFL_Msk (0xf800UL) /*!< RFL (Bitfield-Mask: 0x1f) */
+#define UART0_STATUS_RFF_Pos (10UL) /*!< RFF (Bit 10) */
+#define UART0_STATUS_RFF_Msk (0x400UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_RFE_Pos (9UL) /*!< RFE (Bit 9) */
+#define UART0_STATUS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_RBSY_Pos (8UL) /*!< RBSY (Bit 8) */
+#define UART0_STATUS_RBSY_Msk (0x100UL) /*!< RBSY (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_TFL_Pos (3UL) /*!< TFL (Bit 3) */
+#define UART0_STATUS_TFL_Msk (0xf8UL) /*!< TFL (Bitfield-Mask: 0x1f) */
+#define UART0_STATUS_TFF_Pos (2UL) /*!< TFF (Bit 2) */
+#define UART0_STATUS_TFF_Msk (0x4UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_TFE_Pos (1UL) /*!< TFE (Bit 1) */
+#define UART0_STATUS_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define UART0_STATUS_TBSY_Pos (0UL) /*!< TBSY (Bit 0) */
+#define UART0_STATUS_TBSY_Msk (0x1UL) /*!< TBSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define UART1_CR0_ABRM_Pos (20UL) /*!< ABRM (Bit 20) */
+#define UART1_CR0_ABRM_Msk (0x300000UL) /*!< ABRM (Bitfield-Mask: 0x03) */
+#define UART1_CR0_OVDIS_Pos (17UL) /*!< OVDIS (Bit 17) */
+#define UART1_CR0_OVDIS_Msk (0x20000UL) /*!< OVDIS (Bitfield-Mask: 0x01) */
+#define UART1_CR0_LOOP_Pos (16UL) /*!< LOOP (Bit 16) */
+#define UART1_CR0_LOOP_Msk (0x10000UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define UART1_CR0_ONEBIT_Pos (15UL) /*!< ONEBIT (Bit 15) */
+#define UART1_CR0_ONEBIT_Msk (0x8000UL) /*!< ONEBIT (Bitfield-Mask: 0x01) */
+#define UART1_CR0_RTOM_Pos (14UL) /*!< RTOM (Bit 14) */
+#define UART1_CR0_RTOM_Msk (0x4000UL) /*!< RTOM (Bitfield-Mask: 0x01) */
+#define UART1_CR0_NFE_Pos (13UL) /*!< NFE (Bit 13) */
+#define UART1_CR0_NFE_Msk (0x2000UL) /*!< NFE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_OVER8_Pos (12UL) /*!< OVER8 (Bit 12) */
+#define UART1_CR0_OVER8_Msk (0x1000UL) /*!< OVER8 (Bitfield-Mask: 0x01) */
+#define UART1_CR0_RTOE_Pos (11UL) /*!< RTOE (Bit 11) */
+#define UART1_CR0_RTOE_Msk (0x800UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_TPOL_Pos (10UL) /*!< TPOL (Bit 10) */
+#define UART1_CR0_TPOL_Msk (0x400UL) /*!< TPOL (Bitfield-Mask: 0x01) */
+#define UART1_CR0_RPOL_Pos (9UL) /*!< RPOL (Bit 9) */
+#define UART1_CR0_RPOL_Msk (0x200UL) /*!< RPOL (Bitfield-Mask: 0x01) */
+#define UART1_CR0_SWAP_Pos (8UL) /*!< SWAP (Bit 8) */
+#define UART1_CR0_SWAP_Msk (0x100UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define UART1_CR0_OWE_Pos (7UL) /*!< OWE (Bit 7) */
+#define UART1_CR0_OWE_Msk (0x80UL) /*!< OWE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_DTE_Pos (6UL) /*!< DTE (Bit 6) */
+#define UART1_CR0_DTE_Msk (0x40UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_DRE_Pos (5UL) /*!< DRE (Bit 5) */
+#define UART1_CR0_DRE_Msk (0x20UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_TFR_Pos (4UL) /*!< TFR (Bit 4) */
+#define UART1_CR0_TFR_Msk (0x10UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define UART1_CR0_RFR_Pos (3UL) /*!< RFR (Bit 3) */
+#define UART1_CR0_RFR_Msk (0x8UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define UART1_CR0_TE_Pos (2UL) /*!< TE (Bit 2) */
+#define UART1_CR0_TE_Msk (0x4UL) /*!< TE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_RE_Pos (1UL) /*!< RE (Bit 1) */
+#define UART1_CR0_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
+#define UART1_CR0_UE_Pos (0UL) /*!< UE (Bit 0) */
+#define UART1_CR0_UE_Msk (0x1UL) /*!< UE (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define UART1_CR1_ABR_Pos (21UL) /*!< ABR (Bit 21) */
+#define UART1_CR1_ABR_Msk (0x200000UL) /*!< ABR (Bitfield-Mask: 0x01) */
+#define UART1_CR1_IDR_Pos (20UL) /*!< IDR (Bit 20) */
+#define UART1_CR1_IDR_Msk (0x100000UL) /*!< IDR (Bitfield-Mask: 0x01) */
+#define UART1_CR1_BKR_Pos (19UL) /*!< BKR (Bit 19) */
+#define UART1_CR1_BKR_Msk (0x80000UL) /*!< BKR (Bitfield-Mask: 0x01) */
+#define UART1_CR1_TEM_Pos (18UL) /*!< TEM (Bit 18) */
+#define UART1_CR1_TEM_Msk (0x40000UL) /*!< TEM (Bitfield-Mask: 0x01) */
+#define UART1_CR1_REM_Pos (17UL) /*!< REM (Bit 17) */
+#define UART1_CR1_REM_Msk (0x20000UL) /*!< REM (Bitfield-Mask: 0x01) */
+#define UART1_CR1_EBE_Pos (16UL) /*!< EBE (Bit 16) */
+#define UART1_CR1_EBE_Msk (0x10000UL) /*!< EBE (Bitfield-Mask: 0x01) */
+#define UART1_CR1_DEP_Pos (10UL) /*!< DEP (Bit 10) */
+#define UART1_CR1_DEP_Msk (0x400UL) /*!< DEP (Bitfield-Mask: 0x01) */
+#define UART1_CR1_REP_Pos (9UL) /*!< REP (Bit 9) */
+#define UART1_CR1_REP_Msk (0x200UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define UART1_CR1_RS485E_Pos (8UL) /*!< RS485E (Bit 8) */
+#define UART1_CR1_RS485E_Msk (0x100UL) /*!< RS485E (Bitfield-Mask: 0x01) */
+#define UART1_CR1_MSB_Pos (7UL) /*!< MSB (Bit 7) */
+#define UART1_CR1_MSB_Msk (0x80UL) /*!< MSB (Bitfield-Mask: 0x01) */
+#define UART1_CR1_SPE_Pos (5UL) /*!< SPE (Bit 5) */
+#define UART1_CR1_SPE_Msk (0x20UL) /*!< SPE (Bitfield-Mask: 0x01) */
+#define UART1_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
+#define UART1_CR1_PSEL_Msk (0x10UL) /*!< PSEL (Bitfield-Mask: 0x01) */
+#define UART1_CR1_PEN_Pos (3UL) /*!< PEN (Bit 3) */
+#define UART1_CR1_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
+#define UART1_CR1_STP_Pos (2UL) /*!< STP (Bit 2) */
+#define UART1_CR1_STP_Msk (0x4UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define UART1_CR1_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+#define UART1_CR1_LEN_Msk (0x3UL) /*!< LEN (Bitfield-Mask: 0x03) */
+/* ========================================================= BAUD ========================================================== */
+#define UART1_BAUD_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define UART1_BAUD_BAUD_Msk (0xffffUL) /*!< BAUD (Bitfield-Mask: 0xffff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define UART1_FIFOCTRL_TXFT_Pos (4UL) /*!< TXFT (Bit 4) */
+#define UART1_FIFOCTRL_TXFT_Msk (0xf0UL) /*!< TXFT (Bitfield-Mask: 0x0f) */
+#define UART1_FIFOCTRL_RXFT_Pos (0UL) /*!< RXFT (Bit 0) */
+#define UART1_FIFOCTRL_RXFT_Msk (0xfUL) /*!< RXFT (Bitfield-Mask: 0x0f) */
+/* ======================================================== TIMING0 ======================================================== */
+#define UART1_TIMING0_DEDT_Pos (16UL) /*!< DEDT (Bit 16) */
+#define UART1_TIMING0_DEDT_Msk (0xffff0000UL) /*!< DEDT (Bitfield-Mask: 0xffff) */
+#define UART1_TIMING0_DEAT_Pos (0UL) /*!< DEAT (Bit 0) */
+#define UART1_TIMING0_DEAT_Msk (0xffffUL) /*!< DEAT (Bitfield-Mask: 0xffff) */
+/* ======================================================== TIMING1 ======================================================== */
+#define UART1_TIMING1_DRET_Pos (16UL) /*!< DRET (Bit 16) */
+#define UART1_TIMING1_DRET_Msk (0xffff0000UL) /*!< DRET (Bitfield-Mask: 0xffff) */
+#define UART1_TIMING1_RDET_Pos (0UL) /*!< RDET (Bit 0) */
+#define UART1_TIMING1_RDET_Msk (0xffffUL) /*!< RDET (Bitfield-Mask: 0xffff) */
+/* ========================================================== TDR ========================================================== */
+#define UART1_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define UART1_TDR_TD_Msk (0x1ffUL) /*!< TD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== RDR ========================================================== */
+#define UART1_RDR_OVDA_Pos (16UL) /*!< OVDA (Bit 16) */
+#define UART1_RDR_OVDA_Msk (0x7ff0000UL) /*!< OVDA (Bitfield-Mask: 0x7ff) */
+#define UART1_RDR_FMST_Pos (10UL) /*!< FMST (Bit 10) */
+#define UART1_RDR_FMST_Msk (0x400UL) /*!< FMST (Bitfield-Mask: 0x01) */
+#define UART1_RDR_PRST_Pos (9UL) /*!< PRST (Bit 9) */
+#define UART1_RDR_PRST_Msk (0x200UL) /*!< PRST (Bitfield-Mask: 0x01) */
+#define UART1_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define UART1_RDR_RD_Msk (0x1ffUL) /*!< RD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== TAR ========================================================== */
+#define UART1_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define UART1_TAR_TAR_Msk (0xffUL) /*!< TAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RAR ========================================================== */
+#define UART1_RAR_RAR_Pos (0UL) /*!< RAR (Bit 0) */
+#define UART1_RAR_RAR_Msk (0xffUL) /*!< RAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RTO ========================================================== */
+#define UART1_RTO_RTO_Pos (0UL) /*!< RTO (Bit 0) */
+#define UART1_RTO_RTO_Msk (0xffffUL) /*!< RTO (Bitfield-Mask: 0xffff) */
+/* ========================================================= INTEN ========================================================= */
+#define UART1_INTEN_ABRE_Pos (16UL) /*!< ABRE (Bit 16) */
+#define UART1_INTEN_ABRE_Msk (0x10000UL) /*!< ABRE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_AMIE_Pos (15UL) /*!< AMIE (Bit 15) */
+#define UART1_INTEN_AMIE_Msk (0x8000UL) /*!< AMIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_IDLE_Pos (14UL) /*!< IDLE (Bit 14) */
+#define UART1_INTEN_IDLE_Msk (0x4000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_TBIE_Pos (13UL) /*!< TBIE (Bit 13) */
+#define UART1_INTEN_TBIE_Msk (0x2000UL) /*!< TBIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_TDIE_Pos (12UL) /*!< TDIE (Bit 12) */
+#define UART1_INTEN_TDIE_Msk (0x1000UL) /*!< TDIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_RTIE_Pos (11UL) /*!< RTIE (Bit 11) */
+#define UART1_INTEN_RTIE_Msk (0x800UL) /*!< RTIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_BKIE_Pos (10UL) /*!< BKIE (Bit 10) */
+#define UART1_INTEN_BKIE_Msk (0x400UL) /*!< BKIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_FEIE_Pos (9UL) /*!< FEIE (Bit 9) */
+#define UART1_INTEN_FEIE_Msk (0x200UL) /*!< FEIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_PEIE_Pos (8UL) /*!< PEIE (Bit 8) */
+#define UART1_INTEN_PEIE_Msk (0x100UL) /*!< PEIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_NOIE_Pos (7UL) /*!< NOIE (Bit 7) */
+#define UART1_INTEN_NOIE_Msk (0x80UL) /*!< NOIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_IDIE_Pos (6UL) /*!< IDIE (Bit 6) */
+#define UART1_INTEN_IDIE_Msk (0x40UL) /*!< IDIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_TOIE_Pos (4UL) /*!< TOIE (Bit 4) */
+#define UART1_INTEN_TOIE_Msk (0x10UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_RUIE_Pos (3UL) /*!< RUIE (Bit 3) */
+#define UART1_INTEN_RUIE_Msk (0x8UL) /*!< RUIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_ROIE_Pos (2UL) /*!< ROIE (Bit 2) */
+#define UART1_INTEN_ROIE_Msk (0x4UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_TEIE_Pos (1UL) /*!< TEIE (Bit 1) */
+#define UART1_INTEN_TEIE_Msk (0x2UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define UART1_INTEN_RFIE_Pos (0UL) /*!< RFIE (Bit 0) */
+#define UART1_INTEN_RFIE_Msk (0x1UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define UART1_INT_ABRF_Pos (16UL) /*!< ABRF (Bit 16) */
+#define UART1_INT_ABRF_Msk (0x10000UL) /*!< ABRF (Bitfield-Mask: 0x01) */
+#define UART1_INT_AMIF_Pos (15UL) /*!< AMIF (Bit 15) */
+#define UART1_INT_AMIF_Msk (0x8000UL) /*!< AMIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_IDLF_Pos (14UL) /*!< IDLF (Bit 14) */
+#define UART1_INT_IDLF_Msk (0x4000UL) /*!< IDLF (Bitfield-Mask: 0x01) */
+#define UART1_INT_TBIF_Pos (13UL) /*!< TBIF (Bit 13) */
+#define UART1_INT_TBIF_Msk (0x2000UL) /*!< TBIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_TDIF_Pos (12UL) /*!< TDIF (Bit 12) */
+#define UART1_INT_TDIF_Msk (0x1000UL) /*!< TDIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_RTOI_Pos (11UL) /*!< RTOI (Bit 11) */
+#define UART1_INT_RTOI_Msk (0x800UL) /*!< RTOI (Bitfield-Mask: 0x01) */
+#define UART1_INT_BKIF_Pos (10UL) /*!< BKIF (Bit 10) */
+#define UART1_INT_BKIF_Msk (0x400UL) /*!< BKIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_FEIF_Pos (9UL) /*!< FEIF (Bit 9) */
+#define UART1_INT_FEIF_Msk (0x200UL) /*!< FEIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_PEIF_Pos (8UL) /*!< PEIF (Bit 8) */
+#define UART1_INT_PEIF_Msk (0x100UL) /*!< PEIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_NOIF_Pos (7UL) /*!< NOIF (Bit 7) */
+#define UART1_INT_NOIF_Msk (0x80UL) /*!< NOIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_IDIF_Pos (6UL) /*!< IDIF (Bit 6) */
+#define UART1_INT_IDIF_Msk (0x40UL) /*!< IDIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_TOIF_Pos (4UL) /*!< TOIF (Bit 4) */
+#define UART1_INT_TOIF_Msk (0x10UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_RUIF_Pos (3UL) /*!< RUIF (Bit 3) */
+#define UART1_INT_RUIF_Msk (0x8UL) /*!< RUIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_ROIF_Pos (2UL) /*!< ROIF (Bit 2) */
+#define UART1_INT_ROIF_Msk (0x4UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define UART1_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define UART1_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define UART1_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define UART1_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define UART1_STATUS_RSE_Pos (16UL) /*!< RSE (Bit 16) */
+#define UART1_STATUS_RSE_Msk (0x10000UL) /*!< RSE (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_RFL_Pos (11UL) /*!< RFL (Bit 11) */
+#define UART1_STATUS_RFL_Msk (0xf800UL) /*!< RFL (Bitfield-Mask: 0x1f) */
+#define UART1_STATUS_RFF_Pos (10UL) /*!< RFF (Bit 10) */
+#define UART1_STATUS_RFF_Msk (0x400UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_RFE_Pos (9UL) /*!< RFE (Bit 9) */
+#define UART1_STATUS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_RBSY_Pos (8UL) /*!< RBSY (Bit 8) */
+#define UART1_STATUS_RBSY_Msk (0x100UL) /*!< RBSY (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_TFL_Pos (3UL) /*!< TFL (Bit 3) */
+#define UART1_STATUS_TFL_Msk (0xf8UL) /*!< TFL (Bitfield-Mask: 0x1f) */
+#define UART1_STATUS_TFF_Pos (2UL) /*!< TFF (Bit 2) */
+#define UART1_STATUS_TFF_Msk (0x4UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_TFE_Pos (1UL) /*!< TFE (Bit 1) */
+#define UART1_STATUS_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define UART1_STATUS_TBSY_Pos (0UL) /*!< TBSY (Bit 0) */
+#define UART1_STATUS_TBSY_Msk (0x1UL) /*!< TBSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define UART2_CR0_ABRM_Pos (20UL) /*!< ABRM (Bit 20) */
+#define UART2_CR0_ABRM_Msk (0x300000UL) /*!< ABRM (Bitfield-Mask: 0x03) */
+#define UART2_CR0_OVDIS_Pos (17UL) /*!< OVDIS (Bit 17) */
+#define UART2_CR0_OVDIS_Msk (0x20000UL) /*!< OVDIS (Bitfield-Mask: 0x01) */
+#define UART2_CR0_LOOP_Pos (16UL) /*!< LOOP (Bit 16) */
+#define UART2_CR0_LOOP_Msk (0x10000UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define UART2_CR0_ONEBIT_Pos (15UL) /*!< ONEBIT (Bit 15) */
+#define UART2_CR0_ONEBIT_Msk (0x8000UL) /*!< ONEBIT (Bitfield-Mask: 0x01) */
+#define UART2_CR0_RTOM_Pos (14UL) /*!< RTOM (Bit 14) */
+#define UART2_CR0_RTOM_Msk (0x4000UL) /*!< RTOM (Bitfield-Mask: 0x01) */
+#define UART2_CR0_NFE_Pos (13UL) /*!< NFE (Bit 13) */
+#define UART2_CR0_NFE_Msk (0x2000UL) /*!< NFE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_OVER8_Pos (12UL) /*!< OVER8 (Bit 12) */
+#define UART2_CR0_OVER8_Msk (0x1000UL) /*!< OVER8 (Bitfield-Mask: 0x01) */
+#define UART2_CR0_RTOE_Pos (11UL) /*!< RTOE (Bit 11) */
+#define UART2_CR0_RTOE_Msk (0x800UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_TPOL_Pos (10UL) /*!< TPOL (Bit 10) */
+#define UART2_CR0_TPOL_Msk (0x400UL) /*!< TPOL (Bitfield-Mask: 0x01) */
+#define UART2_CR0_RPOL_Pos (9UL) /*!< RPOL (Bit 9) */
+#define UART2_CR0_RPOL_Msk (0x200UL) /*!< RPOL (Bitfield-Mask: 0x01) */
+#define UART2_CR0_SWAP_Pos (8UL) /*!< SWAP (Bit 8) */
+#define UART2_CR0_SWAP_Msk (0x100UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define UART2_CR0_OWE_Pos (7UL) /*!< OWE (Bit 7) */
+#define UART2_CR0_OWE_Msk (0x80UL) /*!< OWE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_DTE_Pos (6UL) /*!< DTE (Bit 6) */
+#define UART2_CR0_DTE_Msk (0x40UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_DRE_Pos (5UL) /*!< DRE (Bit 5) */
+#define UART2_CR0_DRE_Msk (0x20UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_TFR_Pos (4UL) /*!< TFR (Bit 4) */
+#define UART2_CR0_TFR_Msk (0x10UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define UART2_CR0_RFR_Pos (3UL) /*!< RFR (Bit 3) */
+#define UART2_CR0_RFR_Msk (0x8UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define UART2_CR0_TE_Pos (2UL) /*!< TE (Bit 2) */
+#define UART2_CR0_TE_Msk (0x4UL) /*!< TE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_RE_Pos (1UL) /*!< RE (Bit 1) */
+#define UART2_CR0_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
+#define UART2_CR0_UE_Pos (0UL) /*!< UE (Bit 0) */
+#define UART2_CR0_UE_Msk (0x1UL) /*!< UE (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define UART2_CR1_ABR_Pos (21UL) /*!< ABR (Bit 21) */
+#define UART2_CR1_ABR_Msk (0x200000UL) /*!< ABR (Bitfield-Mask: 0x01) */
+#define UART2_CR1_IDR_Pos (20UL) /*!< IDR (Bit 20) */
+#define UART2_CR1_IDR_Msk (0x100000UL) /*!< IDR (Bitfield-Mask: 0x01) */
+#define UART2_CR1_BKR_Pos (19UL) /*!< BKR (Bit 19) */
+#define UART2_CR1_BKR_Msk (0x80000UL) /*!< BKR (Bitfield-Mask: 0x01) */
+#define UART2_CR1_TEM_Pos (18UL) /*!< TEM (Bit 18) */
+#define UART2_CR1_TEM_Msk (0x40000UL) /*!< TEM (Bitfield-Mask: 0x01) */
+#define UART2_CR1_REM_Pos (17UL) /*!< REM (Bit 17) */
+#define UART2_CR1_REM_Msk (0x20000UL) /*!< REM (Bitfield-Mask: 0x01) */
+#define UART2_CR1_EBE_Pos (16UL) /*!< EBE (Bit 16) */
+#define UART2_CR1_EBE_Msk (0x10000UL) /*!< EBE (Bitfield-Mask: 0x01) */
+#define UART2_CR1_DEP_Pos (10UL) /*!< DEP (Bit 10) */
+#define UART2_CR1_DEP_Msk (0x400UL) /*!< DEP (Bitfield-Mask: 0x01) */
+#define UART2_CR1_REP_Pos (9UL) /*!< REP (Bit 9) */
+#define UART2_CR1_REP_Msk (0x200UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define UART2_CR1_RS485E_Pos (8UL) /*!< RS485E (Bit 8) */
+#define UART2_CR1_RS485E_Msk (0x100UL) /*!< RS485E (Bitfield-Mask: 0x01) */
+#define UART2_CR1_MSB_Pos (7UL) /*!< MSB (Bit 7) */
+#define UART2_CR1_MSB_Msk (0x80UL) /*!< MSB (Bitfield-Mask: 0x01) */
+#define UART2_CR1_SPE_Pos (5UL) /*!< SPE (Bit 5) */
+#define UART2_CR1_SPE_Msk (0x20UL) /*!< SPE (Bitfield-Mask: 0x01) */
+#define UART2_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
+#define UART2_CR1_PSEL_Msk (0x10UL) /*!< PSEL (Bitfield-Mask: 0x01) */
+#define UART2_CR1_PEN_Pos (3UL) /*!< PEN (Bit 3) */
+#define UART2_CR1_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
+#define UART2_CR1_STP_Pos (2UL) /*!< STP (Bit 2) */
+#define UART2_CR1_STP_Msk (0x4UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define UART2_CR1_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+#define UART2_CR1_LEN_Msk (0x3UL) /*!< LEN (Bitfield-Mask: 0x03) */
+/* ========================================================= BAUD ========================================================== */
+#define UART2_BAUD_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define UART2_BAUD_BAUD_Msk (0xffffUL) /*!< BAUD (Bitfield-Mask: 0xffff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define UART2_FIFOCTRL_TXFT_Pos (4UL) /*!< TXFT (Bit 4) */
+#define UART2_FIFOCTRL_TXFT_Msk (0xf0UL) /*!< TXFT (Bitfield-Mask: 0x0f) */
+#define UART2_FIFOCTRL_RXFT_Pos (0UL) /*!< RXFT (Bit 0) */
+#define UART2_FIFOCTRL_RXFT_Msk (0xfUL) /*!< RXFT (Bitfield-Mask: 0x0f) */
+/* ======================================================== TIMING0 ======================================================== */
+#define UART2_TIMING0_DEDT_Pos (16UL) /*!< DEDT (Bit 16) */
+#define UART2_TIMING0_DEDT_Msk (0xffff0000UL) /*!< DEDT (Bitfield-Mask: 0xffff) */
+#define UART2_TIMING0_DEAT_Pos (0UL) /*!< DEAT (Bit 0) */
+#define UART2_TIMING0_DEAT_Msk (0xffffUL) /*!< DEAT (Bitfield-Mask: 0xffff) */
+/* ======================================================== TIMING1 ======================================================== */
+#define UART2_TIMING1_DRET_Pos (16UL) /*!< DRET (Bit 16) */
+#define UART2_TIMING1_DRET_Msk (0xffff0000UL) /*!< DRET (Bitfield-Mask: 0xffff) */
+#define UART2_TIMING1_RDET_Pos (0UL) /*!< RDET (Bit 0) */
+#define UART2_TIMING1_RDET_Msk (0xffffUL) /*!< RDET (Bitfield-Mask: 0xffff) */
+/* ========================================================== TDR ========================================================== */
+#define UART2_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define UART2_TDR_TD_Msk (0x1ffUL) /*!< TD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== RDR ========================================================== */
+#define UART2_RDR_OVDA_Pos (16UL) /*!< OVDA (Bit 16) */
+#define UART2_RDR_OVDA_Msk (0x7ff0000UL) /*!< OVDA (Bitfield-Mask: 0x7ff) */
+#define UART2_RDR_FMST_Pos (10UL) /*!< FMST (Bit 10) */
+#define UART2_RDR_FMST_Msk (0x400UL) /*!< FMST (Bitfield-Mask: 0x01) */
+#define UART2_RDR_PRST_Pos (9UL) /*!< PRST (Bit 9) */
+#define UART2_RDR_PRST_Msk (0x200UL) /*!< PRST (Bitfield-Mask: 0x01) */
+#define UART2_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define UART2_RDR_RD_Msk (0x1ffUL) /*!< RD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== TAR ========================================================== */
+#define UART2_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define UART2_TAR_TAR_Msk (0xffUL) /*!< TAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RAR ========================================================== */
+#define UART2_RAR_RAR_Pos (0UL) /*!< RAR (Bit 0) */
+#define UART2_RAR_RAR_Msk (0xffUL) /*!< RAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RTO ========================================================== */
+#define UART2_RTO_RTO_Pos (0UL) /*!< RTO (Bit 0) */
+#define UART2_RTO_RTO_Msk (0xffffUL) /*!< RTO (Bitfield-Mask: 0xffff) */
+/* ========================================================= INTEN ========================================================= */
+#define UART2_INTEN_ABRE_Pos (16UL) /*!< ABRE (Bit 16) */
+#define UART2_INTEN_ABRE_Msk (0x10000UL) /*!< ABRE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_AMIE_Pos (15UL) /*!< AMIE (Bit 15) */
+#define UART2_INTEN_AMIE_Msk (0x8000UL) /*!< AMIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_IDLE_Pos (14UL) /*!< IDLE (Bit 14) */
+#define UART2_INTEN_IDLE_Msk (0x4000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_TBIE_Pos (13UL) /*!< TBIE (Bit 13) */
+#define UART2_INTEN_TBIE_Msk (0x2000UL) /*!< TBIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_TDIE_Pos (12UL) /*!< TDIE (Bit 12) */
+#define UART2_INTEN_TDIE_Msk (0x1000UL) /*!< TDIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_RTIE_Pos (11UL) /*!< RTIE (Bit 11) */
+#define UART2_INTEN_RTIE_Msk (0x800UL) /*!< RTIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_BKIE_Pos (10UL) /*!< BKIE (Bit 10) */
+#define UART2_INTEN_BKIE_Msk (0x400UL) /*!< BKIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_FEIE_Pos (9UL) /*!< FEIE (Bit 9) */
+#define UART2_INTEN_FEIE_Msk (0x200UL) /*!< FEIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_PEIE_Pos (8UL) /*!< PEIE (Bit 8) */
+#define UART2_INTEN_PEIE_Msk (0x100UL) /*!< PEIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_NOIE_Pos (7UL) /*!< NOIE (Bit 7) */
+#define UART2_INTEN_NOIE_Msk (0x80UL) /*!< NOIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_IDIE_Pos (6UL) /*!< IDIE (Bit 6) */
+#define UART2_INTEN_IDIE_Msk (0x40UL) /*!< IDIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_TOIE_Pos (4UL) /*!< TOIE (Bit 4) */
+#define UART2_INTEN_TOIE_Msk (0x10UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_RUIE_Pos (3UL) /*!< RUIE (Bit 3) */
+#define UART2_INTEN_RUIE_Msk (0x8UL) /*!< RUIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_ROIE_Pos (2UL) /*!< ROIE (Bit 2) */
+#define UART2_INTEN_ROIE_Msk (0x4UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_TEIE_Pos (1UL) /*!< TEIE (Bit 1) */
+#define UART2_INTEN_TEIE_Msk (0x2UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define UART2_INTEN_RFIE_Pos (0UL) /*!< RFIE (Bit 0) */
+#define UART2_INTEN_RFIE_Msk (0x1UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define UART2_INT_ABRF_Pos (16UL) /*!< ABRF (Bit 16) */
+#define UART2_INT_ABRF_Msk (0x10000UL) /*!< ABRF (Bitfield-Mask: 0x01) */
+#define UART2_INT_AMIF_Pos (15UL) /*!< AMIF (Bit 15) */
+#define UART2_INT_AMIF_Msk (0x8000UL) /*!< AMIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_IDLF_Pos (14UL) /*!< IDLF (Bit 14) */
+#define UART2_INT_IDLF_Msk (0x4000UL) /*!< IDLF (Bitfield-Mask: 0x01) */
+#define UART2_INT_TBIF_Pos (13UL) /*!< TBIF (Bit 13) */
+#define UART2_INT_TBIF_Msk (0x2000UL) /*!< TBIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_TDIF_Pos (12UL) /*!< TDIF (Bit 12) */
+#define UART2_INT_TDIF_Msk (0x1000UL) /*!< TDIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_RTOI_Pos (11UL) /*!< RTOI (Bit 11) */
+#define UART2_INT_RTOI_Msk (0x800UL) /*!< RTOI (Bitfield-Mask: 0x01) */
+#define UART2_INT_BKIF_Pos (10UL) /*!< BKIF (Bit 10) */
+#define UART2_INT_BKIF_Msk (0x400UL) /*!< BKIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_FEIF_Pos (9UL) /*!< FEIF (Bit 9) */
+#define UART2_INT_FEIF_Msk (0x200UL) /*!< FEIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_PEIF_Pos (8UL) /*!< PEIF (Bit 8) */
+#define UART2_INT_PEIF_Msk (0x100UL) /*!< PEIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_NOIF_Pos (7UL) /*!< NOIF (Bit 7) */
+#define UART2_INT_NOIF_Msk (0x80UL) /*!< NOIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_IDIF_Pos (6UL) /*!< IDIF (Bit 6) */
+#define UART2_INT_IDIF_Msk (0x40UL) /*!< IDIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_TOIF_Pos (4UL) /*!< TOIF (Bit 4) */
+#define UART2_INT_TOIF_Msk (0x10UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_RUIF_Pos (3UL) /*!< RUIF (Bit 3) */
+#define UART2_INT_RUIF_Msk (0x8UL) /*!< RUIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_ROIF_Pos (2UL) /*!< ROIF (Bit 2) */
+#define UART2_INT_ROIF_Msk (0x4UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define UART2_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define UART2_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define UART2_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define UART2_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define UART2_STATUS_RSE_Pos (16UL) /*!< RSE (Bit 16) */
+#define UART2_STATUS_RSE_Msk (0x10000UL) /*!< RSE (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_RFL_Pos (11UL) /*!< RFL (Bit 11) */
+#define UART2_STATUS_RFL_Msk (0xf800UL) /*!< RFL (Bitfield-Mask: 0x1f) */
+#define UART2_STATUS_RFF_Pos (10UL) /*!< RFF (Bit 10) */
+#define UART2_STATUS_RFF_Msk (0x400UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_RFE_Pos (9UL) /*!< RFE (Bit 9) */
+#define UART2_STATUS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_RBSY_Pos (8UL) /*!< RBSY (Bit 8) */
+#define UART2_STATUS_RBSY_Msk (0x100UL) /*!< RBSY (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_TFL_Pos (3UL) /*!< TFL (Bit 3) */
+#define UART2_STATUS_TFL_Msk (0xf8UL) /*!< TFL (Bitfield-Mask: 0x1f) */
+#define UART2_STATUS_TFF_Pos (2UL) /*!< TFF (Bit 2) */
+#define UART2_STATUS_TFF_Msk (0x4UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_TFE_Pos (1UL) /*!< TFE (Bit 1) */
+#define UART2_STATUS_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define UART2_STATUS_TBSY_Pos (0UL) /*!< TBSY (Bit 0) */
+#define UART2_STATUS_TBSY_Msk (0x1UL) /*!< TBSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define UART3_CR0_ABRM_Pos (20UL) /*!< ABRM (Bit 20) */
+#define UART3_CR0_ABRM_Msk (0x300000UL) /*!< ABRM (Bitfield-Mask: 0x03) */
+#define UART3_CR0_OVDIS_Pos (17UL) /*!< OVDIS (Bit 17) */
+#define UART3_CR0_OVDIS_Msk (0x20000UL) /*!< OVDIS (Bitfield-Mask: 0x01) */
+#define UART3_CR0_LOOP_Pos (16UL) /*!< LOOP (Bit 16) */
+#define UART3_CR0_LOOP_Msk (0x10000UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define UART3_CR0_ONEBIT_Pos (15UL) /*!< ONEBIT (Bit 15) */
+#define UART3_CR0_ONEBIT_Msk (0x8000UL) /*!< ONEBIT (Bitfield-Mask: 0x01) */
+#define UART3_CR0_RTOM_Pos (14UL) /*!< RTOM (Bit 14) */
+#define UART3_CR0_RTOM_Msk (0x4000UL) /*!< RTOM (Bitfield-Mask: 0x01) */
+#define UART3_CR0_NFE_Pos (13UL) /*!< NFE (Bit 13) */
+#define UART3_CR0_NFE_Msk (0x2000UL) /*!< NFE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_OVER8_Pos (12UL) /*!< OVER8 (Bit 12) */
+#define UART3_CR0_OVER8_Msk (0x1000UL) /*!< OVER8 (Bitfield-Mask: 0x01) */
+#define UART3_CR0_RTOE_Pos (11UL) /*!< RTOE (Bit 11) */
+#define UART3_CR0_RTOE_Msk (0x800UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_TPOL_Pos (10UL) /*!< TPOL (Bit 10) */
+#define UART3_CR0_TPOL_Msk (0x400UL) /*!< TPOL (Bitfield-Mask: 0x01) */
+#define UART3_CR0_RPOL_Pos (9UL) /*!< RPOL (Bit 9) */
+#define UART3_CR0_RPOL_Msk (0x200UL) /*!< RPOL (Bitfield-Mask: 0x01) */
+#define UART3_CR0_SWAP_Pos (8UL) /*!< SWAP (Bit 8) */
+#define UART3_CR0_SWAP_Msk (0x100UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define UART3_CR0_OWE_Pos (7UL) /*!< OWE (Bit 7) */
+#define UART3_CR0_OWE_Msk (0x80UL) /*!< OWE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_DTE_Pos (6UL) /*!< DTE (Bit 6) */
+#define UART3_CR0_DTE_Msk (0x40UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_DRE_Pos (5UL) /*!< DRE (Bit 5) */
+#define UART3_CR0_DRE_Msk (0x20UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_TFR_Pos (4UL) /*!< TFR (Bit 4) */
+#define UART3_CR0_TFR_Msk (0x10UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define UART3_CR0_RFR_Pos (3UL) /*!< RFR (Bit 3) */
+#define UART3_CR0_RFR_Msk (0x8UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define UART3_CR0_TE_Pos (2UL) /*!< TE (Bit 2) */
+#define UART3_CR0_TE_Msk (0x4UL) /*!< TE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_RE_Pos (1UL) /*!< RE (Bit 1) */
+#define UART3_CR0_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
+#define UART3_CR0_UE_Pos (0UL) /*!< UE (Bit 0) */
+#define UART3_CR0_UE_Msk (0x1UL) /*!< UE (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define UART3_CR1_ABR_Pos (21UL) /*!< ABR (Bit 21) */
+#define UART3_CR1_ABR_Msk (0x200000UL) /*!< ABR (Bitfield-Mask: 0x01) */
+#define UART3_CR1_IDR_Pos (20UL) /*!< IDR (Bit 20) */
+#define UART3_CR1_IDR_Msk (0x100000UL) /*!< IDR (Bitfield-Mask: 0x01) */
+#define UART3_CR1_BKR_Pos (19UL) /*!< BKR (Bit 19) */
+#define UART3_CR1_BKR_Msk (0x80000UL) /*!< BKR (Bitfield-Mask: 0x01) */
+#define UART3_CR1_TEM_Pos (18UL) /*!< TEM (Bit 18) */
+#define UART3_CR1_TEM_Msk (0x40000UL) /*!< TEM (Bitfield-Mask: 0x01) */
+#define UART3_CR1_REM_Pos (17UL) /*!< REM (Bit 17) */
+#define UART3_CR1_REM_Msk (0x20000UL) /*!< REM (Bitfield-Mask: 0x01) */
+#define UART3_CR1_EBE_Pos (16UL) /*!< EBE (Bit 16) */
+#define UART3_CR1_EBE_Msk (0x10000UL) /*!< EBE (Bitfield-Mask: 0x01) */
+#define UART3_CR1_DEP_Pos (10UL) /*!< DEP (Bit 10) */
+#define UART3_CR1_DEP_Msk (0x400UL) /*!< DEP (Bitfield-Mask: 0x01) */
+#define UART3_CR1_REP_Pos (9UL) /*!< REP (Bit 9) */
+#define UART3_CR1_REP_Msk (0x200UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define UART3_CR1_RS485E_Pos (8UL) /*!< RS485E (Bit 8) */
+#define UART3_CR1_RS485E_Msk (0x100UL) /*!< RS485E (Bitfield-Mask: 0x01) */
+#define UART3_CR1_MSB_Pos (7UL) /*!< MSB (Bit 7) */
+#define UART3_CR1_MSB_Msk (0x80UL) /*!< MSB (Bitfield-Mask: 0x01) */
+#define UART3_CR1_SPE_Pos (5UL) /*!< SPE (Bit 5) */
+#define UART3_CR1_SPE_Msk (0x20UL) /*!< SPE (Bitfield-Mask: 0x01) */
+#define UART3_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
+#define UART3_CR1_PSEL_Msk (0x10UL) /*!< PSEL (Bitfield-Mask: 0x01) */
+#define UART3_CR1_PEN_Pos (3UL) /*!< PEN (Bit 3) */
+#define UART3_CR1_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
+#define UART3_CR1_STP_Pos (2UL) /*!< STP (Bit 2) */
+#define UART3_CR1_STP_Msk (0x4UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define UART3_CR1_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+#define UART3_CR1_LEN_Msk (0x3UL) /*!< LEN (Bitfield-Mask: 0x03) */
+/* ========================================================= BAUD ========================================================== */
+#define UART3_BAUD_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define UART3_BAUD_BAUD_Msk (0xffffUL) /*!< BAUD (Bitfield-Mask: 0xffff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define UART3_FIFOCTRL_TXFT_Pos (4UL) /*!< TXFT (Bit 4) */
+#define UART3_FIFOCTRL_TXFT_Msk (0xf0UL) /*!< TXFT (Bitfield-Mask: 0x0f) */
+#define UART3_FIFOCTRL_RXFT_Pos (0UL) /*!< RXFT (Bit 0) */
+#define UART3_FIFOCTRL_RXFT_Msk (0xfUL) /*!< RXFT (Bitfield-Mask: 0x0f) */
+/* ======================================================== TIMING0 ======================================================== */
+#define UART3_TIMING0_DEDT_Pos (16UL) /*!< DEDT (Bit 16) */
+#define UART3_TIMING0_DEDT_Msk (0xffff0000UL) /*!< DEDT (Bitfield-Mask: 0xffff) */
+#define UART3_TIMING0_DEAT_Pos (0UL) /*!< DEAT (Bit 0) */
+#define UART3_TIMING0_DEAT_Msk (0xffffUL) /*!< DEAT (Bitfield-Mask: 0xffff) */
+/* ======================================================== TIMING1 ======================================================== */
+#define UART3_TIMING1_DRET_Pos (16UL) /*!< DRET (Bit 16) */
+#define UART3_TIMING1_DRET_Msk (0xffff0000UL) /*!< DRET (Bitfield-Mask: 0xffff) */
+#define UART3_TIMING1_RDET_Pos (0UL) /*!< RDET (Bit 0) */
+#define UART3_TIMING1_RDET_Msk (0xffffUL) /*!< RDET (Bitfield-Mask: 0xffff) */
+/* ========================================================== TDR ========================================================== */
+#define UART3_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define UART3_TDR_TD_Msk (0x1ffUL) /*!< TD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== RDR ========================================================== */
+#define UART3_RDR_OVDA_Pos (16UL) /*!< OVDA (Bit 16) */
+#define UART3_RDR_OVDA_Msk (0x7ff0000UL) /*!< OVDA (Bitfield-Mask: 0x7ff) */
+#define UART3_RDR_FMST_Pos (10UL) /*!< FMST (Bit 10) */
+#define UART3_RDR_FMST_Msk (0x400UL) /*!< FMST (Bitfield-Mask: 0x01) */
+#define UART3_RDR_PRST_Pos (9UL) /*!< PRST (Bit 9) */
+#define UART3_RDR_PRST_Msk (0x200UL) /*!< PRST (Bitfield-Mask: 0x01) */
+#define UART3_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define UART3_RDR_RD_Msk (0x1ffUL) /*!< RD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== TAR ========================================================== */
+#define UART3_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define UART3_TAR_TAR_Msk (0xffUL) /*!< TAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RAR ========================================================== */
+#define UART3_RAR_RAR_Pos (0UL) /*!< RAR (Bit 0) */
+#define UART3_RAR_RAR_Msk (0xffUL) /*!< RAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RTO ========================================================== */
+#define UART3_RTO_RTO_Pos (0UL) /*!< RTO (Bit 0) */
+#define UART3_RTO_RTO_Msk (0xffffUL) /*!< RTO (Bitfield-Mask: 0xffff) */
+/* ========================================================= INTEN ========================================================= */
+#define UART3_INTEN_ABRE_Pos (16UL) /*!< ABRE (Bit 16) */
+#define UART3_INTEN_ABRE_Msk (0x10000UL) /*!< ABRE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_AMIE_Pos (15UL) /*!< AMIE (Bit 15) */
+#define UART3_INTEN_AMIE_Msk (0x8000UL) /*!< AMIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_IDLE_Pos (14UL) /*!< IDLE (Bit 14) */
+#define UART3_INTEN_IDLE_Msk (0x4000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_TBIE_Pos (13UL) /*!< TBIE (Bit 13) */
+#define UART3_INTEN_TBIE_Msk (0x2000UL) /*!< TBIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_TDIE_Pos (12UL) /*!< TDIE (Bit 12) */
+#define UART3_INTEN_TDIE_Msk (0x1000UL) /*!< TDIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_RTIE_Pos (11UL) /*!< RTIE (Bit 11) */
+#define UART3_INTEN_RTIE_Msk (0x800UL) /*!< RTIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_BKIE_Pos (10UL) /*!< BKIE (Bit 10) */
+#define UART3_INTEN_BKIE_Msk (0x400UL) /*!< BKIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_FEIE_Pos (9UL) /*!< FEIE (Bit 9) */
+#define UART3_INTEN_FEIE_Msk (0x200UL) /*!< FEIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_PEIE_Pos (8UL) /*!< PEIE (Bit 8) */
+#define UART3_INTEN_PEIE_Msk (0x100UL) /*!< PEIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_NOIE_Pos (7UL) /*!< NOIE (Bit 7) */
+#define UART3_INTEN_NOIE_Msk (0x80UL) /*!< NOIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_IDIE_Pos (6UL) /*!< IDIE (Bit 6) */
+#define UART3_INTEN_IDIE_Msk (0x40UL) /*!< IDIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_TOIE_Pos (4UL) /*!< TOIE (Bit 4) */
+#define UART3_INTEN_TOIE_Msk (0x10UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_RUIE_Pos (3UL) /*!< RUIE (Bit 3) */
+#define UART3_INTEN_RUIE_Msk (0x8UL) /*!< RUIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_ROIE_Pos (2UL) /*!< ROIE (Bit 2) */
+#define UART3_INTEN_ROIE_Msk (0x4UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_TEIE_Pos (1UL) /*!< TEIE (Bit 1) */
+#define UART3_INTEN_TEIE_Msk (0x2UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define UART3_INTEN_RFIE_Pos (0UL) /*!< RFIE (Bit 0) */
+#define UART3_INTEN_RFIE_Msk (0x1UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define UART3_INT_ABRF_Pos (16UL) /*!< ABRF (Bit 16) */
+#define UART3_INT_ABRF_Msk (0x10000UL) /*!< ABRF (Bitfield-Mask: 0x01) */
+#define UART3_INT_AMIF_Pos (15UL) /*!< AMIF (Bit 15) */
+#define UART3_INT_AMIF_Msk (0x8000UL) /*!< AMIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_IDLF_Pos (14UL) /*!< IDLF (Bit 14) */
+#define UART3_INT_IDLF_Msk (0x4000UL) /*!< IDLF (Bitfield-Mask: 0x01) */
+#define UART3_INT_TBIF_Pos (13UL) /*!< TBIF (Bit 13) */
+#define UART3_INT_TBIF_Msk (0x2000UL) /*!< TBIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_TDIF_Pos (12UL) /*!< TDIF (Bit 12) */
+#define UART3_INT_TDIF_Msk (0x1000UL) /*!< TDIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_RTOI_Pos (11UL) /*!< RTOI (Bit 11) */
+#define UART3_INT_RTOI_Msk (0x800UL) /*!< RTOI (Bitfield-Mask: 0x01) */
+#define UART3_INT_BKIF_Pos (10UL) /*!< BKIF (Bit 10) */
+#define UART3_INT_BKIF_Msk (0x400UL) /*!< BKIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_FEIF_Pos (9UL) /*!< FEIF (Bit 9) */
+#define UART3_INT_FEIF_Msk (0x200UL) /*!< FEIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_PEIF_Pos (8UL) /*!< PEIF (Bit 8) */
+#define UART3_INT_PEIF_Msk (0x100UL) /*!< PEIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_NOIF_Pos (7UL) /*!< NOIF (Bit 7) */
+#define UART3_INT_NOIF_Msk (0x80UL) /*!< NOIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_IDIF_Pos (6UL) /*!< IDIF (Bit 6) */
+#define UART3_INT_IDIF_Msk (0x40UL) /*!< IDIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_TOIF_Pos (4UL) /*!< TOIF (Bit 4) */
+#define UART3_INT_TOIF_Msk (0x10UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_RUIF_Pos (3UL) /*!< RUIF (Bit 3) */
+#define UART3_INT_RUIF_Msk (0x8UL) /*!< RUIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_ROIF_Pos (2UL) /*!< ROIF (Bit 2) */
+#define UART3_INT_ROIF_Msk (0x4UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define UART3_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define UART3_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define UART3_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define UART3_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define UART3_STATUS_RSE_Pos (16UL) /*!< RSE (Bit 16) */
+#define UART3_STATUS_RSE_Msk (0x10000UL) /*!< RSE (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_RFL_Pos (11UL) /*!< RFL (Bit 11) */
+#define UART3_STATUS_RFL_Msk (0xf800UL) /*!< RFL (Bitfield-Mask: 0x1f) */
+#define UART3_STATUS_RFF_Pos (10UL) /*!< RFF (Bit 10) */
+#define UART3_STATUS_RFF_Msk (0x400UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_RFE_Pos (9UL) /*!< RFE (Bit 9) */
+#define UART3_STATUS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_RBSY_Pos (8UL) /*!< RBSY (Bit 8) */
+#define UART3_STATUS_RBSY_Msk (0x100UL) /*!< RBSY (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_TFL_Pos (3UL) /*!< TFL (Bit 3) */
+#define UART3_STATUS_TFL_Msk (0xf8UL) /*!< TFL (Bitfield-Mask: 0x1f) */
+#define UART3_STATUS_TFF_Pos (2UL) /*!< TFF (Bit 2) */
+#define UART3_STATUS_TFF_Msk (0x4UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_TFE_Pos (1UL) /*!< TFE (Bit 1) */
+#define UART3_STATUS_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define UART3_STATUS_TBSY_Pos (0UL) /*!< TBSY (Bit 0) */
+#define UART3_STATUS_TBSY_Msk (0x1UL) /*!< TBSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ UART4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define UART4_CR0_ABRM_Pos (20UL) /*!< ABRM (Bit 20) */
+#define UART4_CR0_ABRM_Msk (0x300000UL) /*!< ABRM (Bitfield-Mask: 0x03) */
+#define UART4_CR0_OVDIS_Pos (17UL) /*!< OVDIS (Bit 17) */
+#define UART4_CR0_OVDIS_Msk (0x20000UL) /*!< OVDIS (Bitfield-Mask: 0x01) */
+#define UART4_CR0_LOOP_Pos (16UL) /*!< LOOP (Bit 16) */
+#define UART4_CR0_LOOP_Msk (0x10000UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define UART4_CR0_ONEBIT_Pos (15UL) /*!< ONEBIT (Bit 15) */
+#define UART4_CR0_ONEBIT_Msk (0x8000UL) /*!< ONEBIT (Bitfield-Mask: 0x01) */
+#define UART4_CR0_RTOM_Pos (14UL) /*!< RTOM (Bit 14) */
+#define UART4_CR0_RTOM_Msk (0x4000UL) /*!< RTOM (Bitfield-Mask: 0x01) */
+#define UART4_CR0_NFE_Pos (13UL) /*!< NFE (Bit 13) */
+#define UART4_CR0_NFE_Msk (0x2000UL) /*!< NFE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_OVER8_Pos (12UL) /*!< OVER8 (Bit 12) */
+#define UART4_CR0_OVER8_Msk (0x1000UL) /*!< OVER8 (Bitfield-Mask: 0x01) */
+#define UART4_CR0_RTOE_Pos (11UL) /*!< RTOE (Bit 11) */
+#define UART4_CR0_RTOE_Msk (0x800UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_TPOL_Pos (10UL) /*!< TPOL (Bit 10) */
+#define UART4_CR0_TPOL_Msk (0x400UL) /*!< TPOL (Bitfield-Mask: 0x01) */
+#define UART4_CR0_RPOL_Pos (9UL) /*!< RPOL (Bit 9) */
+#define UART4_CR0_RPOL_Msk (0x200UL) /*!< RPOL (Bitfield-Mask: 0x01) */
+#define UART4_CR0_SWAP_Pos (8UL) /*!< SWAP (Bit 8) */
+#define UART4_CR0_SWAP_Msk (0x100UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define UART4_CR0_OWE_Pos (7UL) /*!< OWE (Bit 7) */
+#define UART4_CR0_OWE_Msk (0x80UL) /*!< OWE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_DTE_Pos (6UL) /*!< DTE (Bit 6) */
+#define UART4_CR0_DTE_Msk (0x40UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_DRE_Pos (5UL) /*!< DRE (Bit 5) */
+#define UART4_CR0_DRE_Msk (0x20UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_TFR_Pos (4UL) /*!< TFR (Bit 4) */
+#define UART4_CR0_TFR_Msk (0x10UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define UART4_CR0_RFR_Pos (3UL) /*!< RFR (Bit 3) */
+#define UART4_CR0_RFR_Msk (0x8UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define UART4_CR0_TE_Pos (2UL) /*!< TE (Bit 2) */
+#define UART4_CR0_TE_Msk (0x4UL) /*!< TE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_RE_Pos (1UL) /*!< RE (Bit 1) */
+#define UART4_CR0_RE_Msk (0x2UL) /*!< RE (Bitfield-Mask: 0x01) */
+#define UART4_CR0_UE_Pos (0UL) /*!< UE (Bit 0) */
+#define UART4_CR0_UE_Msk (0x1UL) /*!< UE (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define UART4_CR1_ABR_Pos (21UL) /*!< ABR (Bit 21) */
+#define UART4_CR1_ABR_Msk (0x200000UL) /*!< ABR (Bitfield-Mask: 0x01) */
+#define UART4_CR1_IDR_Pos (20UL) /*!< IDR (Bit 20) */
+#define UART4_CR1_IDR_Msk (0x100000UL) /*!< IDR (Bitfield-Mask: 0x01) */
+#define UART4_CR1_BKR_Pos (19UL) /*!< BKR (Bit 19) */
+#define UART4_CR1_BKR_Msk (0x80000UL) /*!< BKR (Bitfield-Mask: 0x01) */
+#define UART4_CR1_TEM_Pos (18UL) /*!< TEM (Bit 18) */
+#define UART4_CR1_TEM_Msk (0x40000UL) /*!< TEM (Bitfield-Mask: 0x01) */
+#define UART4_CR1_REM_Pos (17UL) /*!< REM (Bit 17) */
+#define UART4_CR1_REM_Msk (0x20000UL) /*!< REM (Bitfield-Mask: 0x01) */
+#define UART4_CR1_EBE_Pos (16UL) /*!< EBE (Bit 16) */
+#define UART4_CR1_EBE_Msk (0x10000UL) /*!< EBE (Bitfield-Mask: 0x01) */
+#define UART4_CR1_DEP_Pos (10UL) /*!< DEP (Bit 10) */
+#define UART4_CR1_DEP_Msk (0x400UL) /*!< DEP (Bitfield-Mask: 0x01) */
+#define UART4_CR1_REP_Pos (9UL) /*!< REP (Bit 9) */
+#define UART4_CR1_REP_Msk (0x200UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define UART4_CR1_RS485E_Pos (8UL) /*!< RS485E (Bit 8) */
+#define UART4_CR1_RS485E_Msk (0x100UL) /*!< RS485E (Bitfield-Mask: 0x01) */
+#define UART4_CR1_MSB_Pos (7UL) /*!< MSB (Bit 7) */
+#define UART4_CR1_MSB_Msk (0x80UL) /*!< MSB (Bitfield-Mask: 0x01) */
+#define UART4_CR1_SPE_Pos (5UL) /*!< SPE (Bit 5) */
+#define UART4_CR1_SPE_Msk (0x20UL) /*!< SPE (Bitfield-Mask: 0x01) */
+#define UART4_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
+#define UART4_CR1_PSEL_Msk (0x10UL) /*!< PSEL (Bitfield-Mask: 0x01) */
+#define UART4_CR1_PEN_Pos (3UL) /*!< PEN (Bit 3) */
+#define UART4_CR1_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
+#define UART4_CR1_STP_Pos (2UL) /*!< STP (Bit 2) */
+#define UART4_CR1_STP_Msk (0x4UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define UART4_CR1_LEN_Pos (0UL) /*!< LEN (Bit 0) */
+#define UART4_CR1_LEN_Msk (0x3UL) /*!< LEN (Bitfield-Mask: 0x03) */
+/* ========================================================= BAUD ========================================================== */
+#define UART4_BAUD_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define UART4_BAUD_BAUD_Msk (0xffffUL) /*!< BAUD (Bitfield-Mask: 0xffff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define UART4_FIFOCTRL_TXFT_Pos (4UL) /*!< TXFT (Bit 4) */
+#define UART4_FIFOCTRL_TXFT_Msk (0xf0UL) /*!< TXFT (Bitfield-Mask: 0x0f) */
+#define UART4_FIFOCTRL_RXFT_Pos (0UL) /*!< RXFT (Bit 0) */
+#define UART4_FIFOCTRL_RXFT_Msk (0xfUL) /*!< RXFT (Bitfield-Mask: 0x0f) */
+/* ======================================================== TIMING0 ======================================================== */
+#define UART4_TIMING0_DEDT_Pos (16UL) /*!< DEDT (Bit 16) */
+#define UART4_TIMING0_DEDT_Msk (0xffff0000UL) /*!< DEDT (Bitfield-Mask: 0xffff) */
+#define UART4_TIMING0_DEAT_Pos (0UL) /*!< DEAT (Bit 0) */
+#define UART4_TIMING0_DEAT_Msk (0xffffUL) /*!< DEAT (Bitfield-Mask: 0xffff) */
+/* ======================================================== TIMING1 ======================================================== */
+#define UART4_TIMING1_DRET_Pos (16UL) /*!< DRET (Bit 16) */
+#define UART4_TIMING1_DRET_Msk (0xffff0000UL) /*!< DRET (Bitfield-Mask: 0xffff) */
+#define UART4_TIMING1_RDET_Pos (0UL) /*!< RDET (Bit 0) */
+#define UART4_TIMING1_RDET_Msk (0xffffUL) /*!< RDET (Bitfield-Mask: 0xffff) */
+/* ========================================================== TDR ========================================================== */
+#define UART4_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define UART4_TDR_TD_Msk (0x1ffUL) /*!< TD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== RDR ========================================================== */
+#define UART4_RDR_OVDA_Pos (16UL) /*!< OVDA (Bit 16) */
+#define UART4_RDR_OVDA_Msk (0x7ff0000UL) /*!< OVDA (Bitfield-Mask: 0x7ff) */
+#define UART4_RDR_FMST_Pos (10UL) /*!< FMST (Bit 10) */
+#define UART4_RDR_FMST_Msk (0x400UL) /*!< FMST (Bitfield-Mask: 0x01) */
+#define UART4_RDR_PRST_Pos (9UL) /*!< PRST (Bit 9) */
+#define UART4_RDR_PRST_Msk (0x200UL) /*!< PRST (Bitfield-Mask: 0x01) */
+#define UART4_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define UART4_RDR_RD_Msk (0x1ffUL) /*!< RD (Bitfield-Mask: 0x1ff) */
+/* ========================================================== TAR ========================================================== */
+#define UART4_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define UART4_TAR_TAR_Msk (0xffUL) /*!< TAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RAR ========================================================== */
+#define UART4_RAR_RAR_Pos (0UL) /*!< RAR (Bit 0) */
+#define UART4_RAR_RAR_Msk (0xffUL) /*!< RAR (Bitfield-Mask: 0xff) */
+/* ========================================================== RTO ========================================================== */
+#define UART4_RTO_RTO_Pos (0UL) /*!< RTO (Bit 0) */
+#define UART4_RTO_RTO_Msk (0xffffUL) /*!< RTO (Bitfield-Mask: 0xffff) */
+/* ========================================================= INTEN ========================================================= */
+#define UART4_INTEN_ABRE_Pos (16UL) /*!< ABRE (Bit 16) */
+#define UART4_INTEN_ABRE_Msk (0x10000UL) /*!< ABRE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_AMIE_Pos (15UL) /*!< AMIE (Bit 15) */
+#define UART4_INTEN_AMIE_Msk (0x8000UL) /*!< AMIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_IDLE_Pos (14UL) /*!< IDLE (Bit 14) */
+#define UART4_INTEN_IDLE_Msk (0x4000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_TBIE_Pos (13UL) /*!< TBIE (Bit 13) */
+#define UART4_INTEN_TBIE_Msk (0x2000UL) /*!< TBIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_TDIE_Pos (12UL) /*!< TDIE (Bit 12) */
+#define UART4_INTEN_TDIE_Msk (0x1000UL) /*!< TDIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_RTIE_Pos (11UL) /*!< RTIE (Bit 11) */
+#define UART4_INTEN_RTIE_Msk (0x800UL) /*!< RTIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_BKIE_Pos (10UL) /*!< BKIE (Bit 10) */
+#define UART4_INTEN_BKIE_Msk (0x400UL) /*!< BKIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_FEIE_Pos (9UL) /*!< FEIE (Bit 9) */
+#define UART4_INTEN_FEIE_Msk (0x200UL) /*!< FEIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_PEIE_Pos (8UL) /*!< PEIE (Bit 8) */
+#define UART4_INTEN_PEIE_Msk (0x100UL) /*!< PEIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_NOIE_Pos (7UL) /*!< NOIE (Bit 7) */
+#define UART4_INTEN_NOIE_Msk (0x80UL) /*!< NOIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_IDIE_Pos (6UL) /*!< IDIE (Bit 6) */
+#define UART4_INTEN_IDIE_Msk (0x40UL) /*!< IDIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_TOIE_Pos (4UL) /*!< TOIE (Bit 4) */
+#define UART4_INTEN_TOIE_Msk (0x10UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_RUIE_Pos (3UL) /*!< RUIE (Bit 3) */
+#define UART4_INTEN_RUIE_Msk (0x8UL) /*!< RUIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_ROIE_Pos (2UL) /*!< ROIE (Bit 2) */
+#define UART4_INTEN_ROIE_Msk (0x4UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_TEIE_Pos (1UL) /*!< TEIE (Bit 1) */
+#define UART4_INTEN_TEIE_Msk (0x2UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define UART4_INTEN_RFIE_Pos (0UL) /*!< RFIE (Bit 0) */
+#define UART4_INTEN_RFIE_Msk (0x1UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define UART4_INT_ABRF_Pos (16UL) /*!< ABRF (Bit 16) */
+#define UART4_INT_ABRF_Msk (0x10000UL) /*!< ABRF (Bitfield-Mask: 0x01) */
+#define UART4_INT_AMIF_Pos (15UL) /*!< AMIF (Bit 15) */
+#define UART4_INT_AMIF_Msk (0x8000UL) /*!< AMIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_IDLF_Pos (14UL) /*!< IDLF (Bit 14) */
+#define UART4_INT_IDLF_Msk (0x4000UL) /*!< IDLF (Bitfield-Mask: 0x01) */
+#define UART4_INT_TBIF_Pos (13UL) /*!< TBIF (Bit 13) */
+#define UART4_INT_TBIF_Msk (0x2000UL) /*!< TBIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_TDIF_Pos (12UL) /*!< TDIF (Bit 12) */
+#define UART4_INT_TDIF_Msk (0x1000UL) /*!< TDIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_RTOI_Pos (11UL) /*!< RTOI (Bit 11) */
+#define UART4_INT_RTOI_Msk (0x800UL) /*!< RTOI (Bitfield-Mask: 0x01) */
+#define UART4_INT_BKIF_Pos (10UL) /*!< BKIF (Bit 10) */
+#define UART4_INT_BKIF_Msk (0x400UL) /*!< BKIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_FEIF_Pos (9UL) /*!< FEIF (Bit 9) */
+#define UART4_INT_FEIF_Msk (0x200UL) /*!< FEIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_PEIF_Pos (8UL) /*!< PEIF (Bit 8) */
+#define UART4_INT_PEIF_Msk (0x100UL) /*!< PEIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_NOIF_Pos (7UL) /*!< NOIF (Bit 7) */
+#define UART4_INT_NOIF_Msk (0x80UL) /*!< NOIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_IDIF_Pos (6UL) /*!< IDIF (Bit 6) */
+#define UART4_INT_IDIF_Msk (0x40UL) /*!< IDIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_TOIF_Pos (4UL) /*!< TOIF (Bit 4) */
+#define UART4_INT_TOIF_Msk (0x10UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_RUIF_Pos (3UL) /*!< RUIF (Bit 3) */
+#define UART4_INT_RUIF_Msk (0x8UL) /*!< RUIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_ROIF_Pos (2UL) /*!< ROIF (Bit 2) */
+#define UART4_INT_ROIF_Msk (0x4UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define UART4_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define UART4_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define UART4_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define UART4_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define UART4_STATUS_RSE_Pos (16UL) /*!< RSE (Bit 16) */
+#define UART4_STATUS_RSE_Msk (0x10000UL) /*!< RSE (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_RFL_Pos (11UL) /*!< RFL (Bit 11) */
+#define UART4_STATUS_RFL_Msk (0xf800UL) /*!< RFL (Bitfield-Mask: 0x1f) */
+#define UART4_STATUS_RFF_Pos (10UL) /*!< RFF (Bit 10) */
+#define UART4_STATUS_RFF_Msk (0x400UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_RFE_Pos (9UL) /*!< RFE (Bit 9) */
+#define UART4_STATUS_RFE_Msk (0x200UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_RBSY_Pos (8UL) /*!< RBSY (Bit 8) */
+#define UART4_STATUS_RBSY_Msk (0x100UL) /*!< RBSY (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_TFL_Pos (3UL) /*!< TFL (Bit 3) */
+#define UART4_STATUS_TFL_Msk (0xf8UL) /*!< TFL (Bitfield-Mask: 0x1f) */
+#define UART4_STATUS_TFF_Pos (2UL) /*!< TFF (Bit 2) */
+#define UART4_STATUS_TFF_Msk (0x4UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_TFE_Pos (1UL) /*!< TFE (Bit 1) */
+#define UART4_STATUS_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define UART4_STATUS_TBSY_Pos (0UL) /*!< TBSY (Bit 0) */
+#define UART4_STATUS_TBSY_Msk (0x1UL) /*!< TBSY (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ SYSCTRL ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== SYSDCR ========================================================= */
+#define SYSCTRL_SYSDCR_TMR10DEN_Pos (11UL) /*!< TMR10DEN (Bit 11) */
+#define SYSCTRL_SYSDCR_TMR10DEN_Msk (0x800UL) /*!< TMR10DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR9DEN_Pos (10UL) /*!< TMR9DEN (Bit 10) */
+#define SYSCTRL_SYSDCR_TMR9DEN_Msk (0x400UL) /*!< TMR9DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR4DEN_Pos (9UL) /*!< TMR4DEN (Bit 9) */
+#define SYSCTRL_SYSDCR_TMR4DEN_Msk (0x200UL) /*!< TMR4DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR3DEN_Pos (8UL) /*!< TMR3DEN (Bit 8) */
+#define SYSCTRL_SYSDCR_TMR3DEN_Msk (0x100UL) /*!< TMR3DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR2DEN_Pos (7UL) /*!< TMR2DEN (Bit 7) */
+#define SYSCTRL_SYSDCR_TMR2DEN_Msk (0x80UL) /*!< TMR2DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR1DEN_Pos (6UL) /*!< TMR1DEN (Bit 6) */
+#define SYSCTRL_SYSDCR_TMR1DEN_Msk (0x40UL) /*!< TMR1DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR0DEN_Pos (5UL) /*!< TMR0DEN (Bit 5) */
+#define SYSCTRL_SYSDCR_TMR0DEN_Msk (0x20UL) /*!< TMR0DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR8DEN_Pos (4UL) /*!< TMR8DEN (Bit 4) */
+#define SYSCTRL_SYSDCR_TMR8DEN_Msk (0x10UL) /*!< TMR8DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_TMR7DEN_Pos (3UL) /*!< TMR7DEN (Bit 3) */
+#define SYSCTRL_SYSDCR_TMR7DEN_Msk (0x8UL) /*!< TMR7DEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_PWMDEN_Pos (2UL) /*!< PWMDEN (Bit 2) */
+#define SYSCTRL_SYSDCR_PWMDEN_Msk (0x4UL) /*!< PWMDEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_WWDGDEN_Pos (1UL) /*!< WWDGDEN (Bit 1) */
+#define SYSCTRL_SYSDCR_WWDGDEN_Msk (0x2UL) /*!< WWDGDEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSDCR_IWDGDEN_Pos (0UL) /*!< IWDGDEN (Bit 0) */
+#define SYSCTRL_SYSDCR_IWDGDEN_Msk (0x1UL) /*!< IWDGDEN (Bitfield-Mask: 0x01) */
+/* ========================================================= SYSCR ========================================================= */
+#define SYSCTRL_SYSCR_FBM_Pos (8UL) /*!< FBM (Bit 8) */
+#define SYSCTRL_SYSCR_FBM_Msk (0x100UL) /*!< FBM (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_QEI2FE_Pos (6UL) /*!< QEI2FE (Bit 6) */
+#define SYSCTRL_SYSCR_QEI2FE_Msk (0x40UL) /*!< QEI2FE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_QEI1FE_Pos (5UL) /*!< QEI1FE (Bit 5) */
+#define SYSCTRL_SYSCR_QEI1FE_Msk (0x20UL) /*!< QEI1FE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_QEI0FE_Pos (4UL) /*!< QEI0FE (Bit 4) */
+#define SYSCTRL_SYSCR_QEI0FE_Msk (0x10UL) /*!< QEI0FE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_PLLFE_Pos (3UL) /*!< PLLFE (Bit 3) */
+#define SYSCTRL_SYSCR_PLLFE_Msk (0x8UL) /*!< PLLFE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_OSCFE_Pos (2UL) /*!< OSCFE (Bit 2) */
+#define SYSCTRL_SYSCR_OSCFE_Msk (0x4UL) /*!< OSCFE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_LKFE_Pos (1UL) /*!< LKFE (Bit 1) */
+#define SYSCTRL_SYSCR_LKFE_Msk (0x2UL) /*!< LKFE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSCR_ECCFE_Pos (0UL) /*!< ECCFE (Bit 0) */
+#define SYSCTRL_SYSCR_ECCFE_Msk (0x1UL) /*!< ECCFE (Bitfield-Mask: 0x01) */
+/* ======================================================== DMARCR ========================================================= */
+#define SYSCTRL_DMARCR_DRCR_Pos (19UL) /*!< DRCR (Bit 19) */
+#define SYSCTRL_DMARCR_DRCR_Msk (0xfff80000UL) /*!< DRCR (Bitfield-Mask: 0x1fff) */
+/* ======================================================== SYSATR ========================================================= */
+#define SYSCTRL_SYSATR_ABFSRC_Pos (10UL) /*!< ABFSRC (Bit 10) */
+#define SYSCTRL_SYSATR_ABFSRC_Msk (0x7c00UL) /*!< ABFSRC (Bitfield-Mask: 0x1f) */
+#define SYSCTRL_SYSATR_ABFBYP_Pos (9UL) /*!< ABFBYP (Bit 9) */
+#define SYSCTRL_SYSATR_ABFBYP_Msk (0x200UL) /*!< ABFBYP (Bitfield-Mask: 0x01) */
+#define SYSCTRL_SYSATR_ABFEN_Pos (8UL) /*!< ABFEN (Bit 8) */
+#define SYSCTRL_SYSATR_ABFEN_Msk (0x100UL) /*!< ABFEN (Bitfield-Mask: 0x01) */
+/* ========================================================= PWRCR ========================================================= */
+#define SYSCTRL_PWRCR_AVDDDRD_Pos (8UL) /*!< AVDDDRD (Bit 8) */
+#define SYSCTRL_PWRCR_AVDDDRD_Msk (0x100UL) /*!< AVDDDRD (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PWRCR_VDDSET_Pos (4UL) /*!< VDDSET (Bit 4) */
+#define SYSCTRL_PWRCR_VDDSET_Msk (0xf0UL) /*!< VDDSET (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_PWRCR_AVDDSET_Pos (2UL) /*!< AVDDSET (Bit 2) */
+#define SYSCTRL_PWRCR_AVDDSET_Msk (0xcUL) /*!< AVDDSET (Bitfield-Mask: 0x03) */
+#define SYSCTRL_PWRCR_AVDDEN_Pos (1UL) /*!< AVDDEN (Bit 1) */
+#define SYSCTRL_PWRCR_AVDDEN_Msk (0x2UL) /*!< AVDDEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PWRCR_TSE_Pos (0UL) /*!< TSE (Bit 0) */
+#define SYSCTRL_PWRCR_TSE_Msk (0x1UL) /*!< TSE (Bitfield-Mask: 0x01) */
+/* ========================================================= PLCR ========================================================== */
+#define SYSCTRL_PLCR_VDDOCL_Pos (12UL) /*!< VDDOCL (Bit 12) */
+#define SYSCTRL_PLCR_VDDOCL_Msk (0x3000UL) /*!< VDDOCL (Bitfield-Mask: 0x03) */
+#define SYSCTRL_PLCR_AVCCLVL_Pos (10UL) /*!< AVCCLVL (Bit 10) */
+#define SYSCTRL_PLCR_AVCCLVL_Msk (0xc00UL) /*!< AVCCLVL (Bitfield-Mask: 0x03) */
+#define SYSCTRL_PLCR_VDDLVS_Pos (4UL) /*!< VDDLVS (Bit 4) */
+#define SYSCTRL_PLCR_VDDLVS_Msk (0x70UL) /*!< VDDLVS (Bitfield-Mask: 0x07) */
+#define SYSCTRL_PLCR_VDDOCE_Pos (3UL) /*!< VDDOCE (Bit 3) */
+#define SYSCTRL_PLCR_VDDOCE_Msk (0x8UL) /*!< VDDOCE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PLCR_AVCCLVE_Pos (2UL) /*!< AVCCLVE (Bit 2) */
+#define SYSCTRL_PLCR_AVCCLVE_Msk (0x4UL) /*!< AVCCLVE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PLCR_VCCLVE_Pos (1UL) /*!< VCCLVE (Bit 1) */
+#define SYSCTRL_PLCR_VCCLVE_Msk (0x2UL) /*!< VCCLVE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PLCR_VDDLVE_Pos (0UL) /*!< VDDLVE (Bit 0) */
+#define SYSCTRL_PLCR_VDDLVE_Msk (0x1UL) /*!< VDDLVE (Bitfield-Mask: 0x01) */
+/* ========================================================= PECR ========================================================== */
+#define SYSCTRL_PECR_VDDOCBE_Pos (11UL) /*!< VDDOCBE (Bit 11) */
+#define SYSCTRL_PECR_VDDOCBE_Msk (0x800UL) /*!< VDDOCBE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_AVCCLVBE_Pos (10UL) /*!< AVCCLVBE (Bit 10) */
+#define SYSCTRL_PECR_AVCCLVBE_Msk (0x400UL) /*!< AVCCLVBE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VCCLVBE_Pos (9UL) /*!< VCCLVBE (Bit 9) */
+#define SYSCTRL_PECR_VCCLVBE_Msk (0x200UL) /*!< VCCLVBE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VDDLVBE_Pos (8UL) /*!< VDDLVBE (Bit 8) */
+#define SYSCTRL_PECR_VDDLVBE_Msk (0x100UL) /*!< VDDLVBE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VDDOCRE_Pos (7UL) /*!< VDDOCRE (Bit 7) */
+#define SYSCTRL_PECR_VDDOCRE_Msk (0x80UL) /*!< VDDOCRE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_AVCCLVRE_Pos (6UL) /*!< AVCCLVRE (Bit 6) */
+#define SYSCTRL_PECR_AVCCLVRE_Msk (0x40UL) /*!< AVCCLVRE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VCCLVRE_Pos (5UL) /*!< VCCLVRE (Bit 5) */
+#define SYSCTRL_PECR_VCCLVRE_Msk (0x20UL) /*!< VCCLVRE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VDDLVRE_Pos (4UL) /*!< VDDLVRE (Bit 4) */
+#define SYSCTRL_PECR_VDDLVRE_Msk (0x10UL) /*!< VDDLVRE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VDDOCIE_Pos (3UL) /*!< VDDOCIE (Bit 3) */
+#define SYSCTRL_PECR_VDDOCIE_Msk (0x8UL) /*!< VDDOCIE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_AVCCLVIE_Pos (2UL) /*!< AVCCLVIE (Bit 2) */
+#define SYSCTRL_PECR_AVCCLVIE_Msk (0x4UL) /*!< AVCCLVIE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VCCLVIE_Pos (1UL) /*!< VCCLVIE (Bit 1) */
+#define SYSCTRL_PECR_VCCLVIE_Msk (0x2UL) /*!< VCCLVIE (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PECR_VDDLVIE_Pos (0UL) /*!< VDDLVIE (Bit 0) */
+#define SYSCTRL_PECR_VDDLVIE_Msk (0x1UL) /*!< VDDLVIE (Bitfield-Mask: 0x01) */
+/* ========================================================== PSR ========================================================== */
+#define SYSCTRL_PSR_VDDOCS_Pos (3UL) /*!< VDDOCS (Bit 3) */
+#define SYSCTRL_PSR_VDDOCS_Msk (0x8UL) /*!< VDDOCS (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PSR_AVCCLVS_Pos (2UL) /*!< AVCCLVS (Bit 2) */
+#define SYSCTRL_PSR_AVCCLVS_Msk (0x4UL) /*!< AVCCLVS (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PSR_VCCLVS_Pos (1UL) /*!< VCCLVS (Bit 1) */
+#define SYSCTRL_PSR_VCCLVS_Msk (0x2UL) /*!< VCCLVS (Bitfield-Mask: 0x01) */
+#define SYSCTRL_PSR_VDDLVS_Pos (0UL) /*!< VDDLVS (Bit 0) */
+#define SYSCTRL_PSR_VDDLVS_Msk (0x1UL) /*!< VDDLVS (Bitfield-Mask: 0x01) */
+/* ========================================================= PWRDR ========================================================= */
+#define SYSCTRL_PWRDR_VDDOCF_Pos (12UL) /*!< VDDOCF (Bit 12) */
+#define SYSCTRL_PWRDR_VDDOCF_Msk (0xf000UL) /*!< VDDOCF (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_PWRDR_AVCCLVF_Pos (8UL) /*!< AVCCLVF (Bit 8) */
+#define SYSCTRL_PWRDR_AVCCLVF_Msk (0xf00UL) /*!< AVCCLVF (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_PWRDR_VCCLVF_Pos (4UL) /*!< VCCLVF (Bit 4) */
+#define SYSCTRL_PWRDR_VCCLVF_Msk (0xf0UL) /*!< VCCLVF (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_PWRDR_VDDLVF_Pos (0UL) /*!< VDDLVF (Bit 0) */
+#define SYSCTRL_PWRDR_VDDLVF_Msk (0xfUL) /*!< VDDLVF (Bitfield-Mask: 0x0f) */
+/* ========================================================= CIDR ========================================================== */
+#define SYSCTRL_CIDR_DCN_Pos (16UL) /*!< DCN (Bit 16) */
+#define SYSCTRL_CIDR_DCN_Msk (0xff0000UL) /*!< DCN (Bitfield-Mask: 0xff) */
+#define SYSCTRL_CIDR_CID_Pos (0UL) /*!< CID (Bit 0) */
+#define SYSCTRL_CIDR_CID_Msk (0xffffUL) /*!< CID (Bitfield-Mask: 0xffff) */
+/* ========================================================= KEYR ========================================================== */
+#define SYSCTRL_KEYR_KST1_Pos (17UL) /*!< KST1 (Bit 17) */
+#define SYSCTRL_KEYR_KST1_Msk (0x20000UL) /*!< KST1 (Bitfield-Mask: 0x01) */
+#define SYSCTRL_KEYR_KST0_Pos (16UL) /*!< KST0 (Bit 16) */
+#define SYSCTRL_KEYR_KST0_Msk (0x10000UL) /*!< KST0 (Bitfield-Mask: 0x01) */
+#define SYSCTRL_KEYR_KEY_Pos (0UL) /*!< KEY (Bit 0) */
+#define SYSCTRL_KEYR_KEY_Msk (0xffffUL) /*!< KEY (Bitfield-Mask: 0xffff) */
+/* ========================================================= UID0 ========================================================== */
+#define SYSCTRL_UID0_UID0_Pos (0UL) /*!< UID0 (Bit 0) */
+#define SYSCTRL_UID0_UID0_Msk (0xffffffffUL) /*!< UID0 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UID1 ========================================================== */
+#define SYSCTRL_UID1_UID1_Pos (0UL) /*!< UID1 (Bit 0) */
+#define SYSCTRL_UID1_UID1_Msk (0xffffffffUL) /*!< UID1 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UID2 ========================================================== */
+#define SYSCTRL_UID2_UID2_Pos (0UL) /*!< UID2 (Bit 0) */
+#define SYSCTRL_UID2_UID2_Msk (0xffffffffUL) /*!< UID2 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UID3 ========================================================== */
+#define SYSCTRL_UID3_UID3_Pos (0UL) /*!< UID3 (Bit 0) */
+#define SYSCTRL_UID3_UID3_Msk (0xffffffffUL) /*!< UID3 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ATCR ========================================================== */
+#define SYSCTRL_ATCR_VBFRDY_Pos (31UL) /*!< VBFRDY (Bit 31) */
+#define SYSCTRL_ATCR_VBFRDY_Msk (0x80000000UL) /*!< VBFRDY (Bitfield-Mask: 0x01) */
+#define SYSCTRL_ATCR_BGV_Pos (20UL) /*!< BGV (Bit 20) */
+#define SYSCTRL_ATCR_BGV_Msk (0x7ff00000UL) /*!< BGV (Bitfield-Mask: 0x7ff) */
+#define SYSCTRL_ATCR_VBFCL_Pos (19UL) /*!< VBFCL (Bit 19) */
+#define SYSCTRL_ATCR_VBFCL_Msk (0x80000UL) /*!< VBFCL (Bitfield-Mask: 0x01) */
+#define SYSCTRL_ATCR_VBFTRIM_Pos (14UL) /*!< VBFTRIM (Bit 14) */
+#define SYSCTRL_ATCR_VBFTRIM_Msk (0x7c000UL) /*!< VBFTRIM (Bitfield-Mask: 0x1f) */
+#define SYSCTRL_ATCR_VBFSEL_Pos (13UL) /*!< VBFSEL (Bit 13) */
+#define SYSCTRL_ATCR_VBFSEL_Msk (0x2000UL) /*!< VBFSEL (Bitfield-Mask: 0x01) */
+#define SYSCTRL_ATCR_VBFEN_Pos (12UL) /*!< VBFEN (Bit 12) */
+#define SYSCTRL_ATCR_VBFEN_Msk (0x1000UL) /*!< VBFEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_ATCR_REFITRIM_Pos (6UL) /*!< REFITRIM (Bit 6) */
+#define SYSCTRL_ATCR_REFITRIM_Msk (0xfc0UL) /*!< REFITRIM (Bitfield-Mask: 0x3f) */
+#define SYSCTRL_ATCR_REFVTRIM_Pos (1UL) /*!< REFVTRIM (Bit 1) */
+#define SYSCTRL_ATCR_REFVTRIM_Msk (0x3eUL) /*!< REFVTRIM (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCR0 ========================================================== */
+#define SYSCTRL_FCR0_ADC3TRIM_Pos (24UL) /*!< ADC3TRIM (Bit 24) */
+#define SYSCTRL_FCR0_ADC3TRIM_Msk (0x1f000000UL) /*!< ADC3TRIM (Bitfield-Mask: 0x1f) */
+#define SYSCTRL_FCR0_ADC2TRIM_Pos (16UL) /*!< ADC2TRIM (Bit 16) */
+#define SYSCTRL_FCR0_ADC2TRIM_Msk (0x1f0000UL) /*!< ADC2TRIM (Bitfield-Mask: 0x1f) */
+#define SYSCTRL_FCR0_ADC1TRIM_Pos (8UL) /*!< ADC1TRIM (Bit 8) */
+#define SYSCTRL_FCR0_ADC1TRIM_Msk (0x1f00UL) /*!< ADC1TRIM (Bitfield-Mask: 0x1f) */
+#define SYSCTRL_FCR0_ADC0TRIM_Pos (0UL) /*!< ADC0TRIM (Bit 0) */
+#define SYSCTRL_FCR0_ADC0TRIM_Msk (0x1fUL) /*!< ADC0TRIM (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCR1 ========================================================== */
+#define SYSCTRL_FCR1_DAC2TRIM_Pos (28UL) /*!< DAC2TRIM (Bit 28) */
+#define SYSCTRL_FCR1_DAC2TRIM_Msk (0xf0000000UL) /*!< DAC2TRIM (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_FCR1_DAC1TRIM_Pos (24UL) /*!< DAC1TRIM (Bit 24) */
+#define SYSCTRL_FCR1_DAC1TRIM_Msk (0xf000000UL) /*!< DAC1TRIM (Bitfield-Mask: 0x0f) */
+#define SYSCTRL_FCR1_DAC0TRIM_Pos (20UL) /*!< DAC0TRIM (Bit 20) */
+#define SYSCTRL_FCR1_DAC0TRIM_Msk (0xf00000UL) /*!< DAC0TRIM (Bitfield-Mask: 0x0f) */
+/* ========================================================= FCR2 ========================================================== */
+#define SYSCTRL_FCR2_RC8M_Pos (8UL) /*!< RC8M (Bit 8) */
+#define SYSCTRL_FCR2_RC8M_Msk (0xffffff00UL) /*!< RC8M (Bitfield-Mask: 0xffffff) */
+#define SYSCTRL_FCR2_ADCPVEN_Pos (4UL) /*!< ADCPVEN (Bit 4) */
+#define SYSCTRL_FCR2_ADCPVEN_Msk (0x10UL) /*!< ADCPVEN (Bitfield-Mask: 0x01) */
+#define SYSCTRL_FCR2_PLL0BANDx_Pos (2UL) /*!< PLL0BANDx (Bit 2) */
+#define SYSCTRL_FCR2_PLL0BANDx_Msk (0xcUL) /*!< PLL0BANDx (Bitfield-Mask: 0x03) */
+#define SYSCTRL_FCR2_PLL0BANDy_Pos (0UL) /*!< PLL0BANDy (Bit 0) */
+#define SYSCTRL_FCR2_PLL0BANDy_Msk (0x3UL) /*!< PLL0BANDy (Bitfield-Mask: 0x03) */
+/* ========================================================= FCR3 ========================================================== */
+#define SYSCTRL_FCR3_PLL0INTy_Pos (16UL) /*!< PLL0INTy (Bit 16) */
+#define SYSCTRL_FCR3_PLL0INTy_Msk (0x3fff0000UL) /*!< PLL0INTy (Bitfield-Mask: 0x3fff) */
+#define SYSCTRL_FCR3_PLL0FRACy_Pos (0UL) /*!< PLL0FRACy (Bit 0) */
+#define SYSCTRL_FCR3_PLL0FRACy_Msk (0xffffUL) /*!< PLL0FRACy (Bitfield-Mask: 0xffff) */
+/* ========================================================= FCR4 ========================================================== */
+#define SYSCTRL_FCR4_PLL0INTx_Pos (16UL) /*!< PLL0INTx (Bit 16) */
+#define SYSCTRL_FCR4_PLL0INTx_Msk (0x3fff0000UL) /*!< PLL0INTx (Bitfield-Mask: 0x3fff) */
+#define SYSCTRL_FCR4_PLL0FRACx_Pos (0UL) /*!< PLL0FRACx (Bit 0) */
+#define SYSCTRL_FCR4_PLL0FRACx_Msk (0xffffUL) /*!< PLL0FRACx (Bitfield-Mask: 0xffff) */
+/* ========================================================= FCR5 ========================================================== */
+#define SYSCTRL_FCR5_RC32K_Pos (16UL) /*!< RC32K (Bit 16) */
+#define SYSCTRL_FCR5_RC32K_Msk (0xffff0000UL) /*!< RC32K (Bitfield-Mask: 0xffff) */
+#define SYSCTRL_FCR5_Tsensor_Pos (0UL) /*!< Tsensor (Bit 0) */
+#define SYSCTRL_FCR5_Tsensor_Msk (0xffffUL) /*!< Tsensor (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ SPI0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define SPI0_ENABLE_CSI_Pos (15UL) /*!< CSI (Bit 15) */
+#define SPI0_ENABLE_CSI_Msk (0x8000UL) /*!< CSI (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_CSIS_Pos (14UL) /*!< CSIS (Bit 14) */
+#define SPI0_ENABLE_CSIS_Msk (0x4000UL) /*!< CSIS (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_CSO_Pos (13UL) /*!< CSO (Bit 13) */
+#define SPI0_ENABLE_CSO_Msk (0x2000UL) /*!< CSO (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_CSOS_Pos (12UL) /*!< CSOS (Bit 12) */
+#define SPI0_ENABLE_CSOS_Msk (0x1000UL) /*!< CSOS (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_DTE_Pos (9UL) /*!< DTE (Bit 9) */
+#define SPI0_ENABLE_DTE_Msk (0x200UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_DRE_Pos (8UL) /*!< DRE (Bit 8) */
+#define SPI0_ENABLE_DRE_Msk (0x100UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_LOOP_Pos (7UL) /*!< LOOP (Bit 7) */
+#define SPI0_ENABLE_LOOP_Msk (0x80UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_SWAP_Pos (6UL) /*!< SWAP (Bit 6) */
+#define SPI0_ENABLE_SWAP_Msk (0x40UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_CSPOL_Pos (5UL) /*!< CSPOL (Bit 5) */
+#define SPI0_ENABLE_CSPOL_Msk (0x20UL) /*!< CSPOL (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_CSSEL_Pos (4UL) /*!< CSSEL (Bit 4) */
+#define SPI0_ENABLE_CSSEL_Msk (0x10UL) /*!< CSSEL (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_TWE_Pos (3UL) /*!< TWE (Bit 3) */
+#define SPI0_ENABLE_TWE_Msk (0x8UL) /*!< TWE (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_TFR_Pos (2UL) /*!< TFR (Bit 2) */
+#define SPI0_ENABLE_TFR_Msk (0x4UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_RFR_Pos (1UL) /*!< RFR (Bit 1) */
+#define SPI0_ENABLE_RFR_Msk (0x2UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define SPI0_ENABLE_SPIEN_Pos (0UL) /*!< SPIEN (Bit 0) */
+#define SPI0_ENABLE_SPIEN_Msk (0x1UL) /*!< SPIEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define SPI0_CTRL_RXDLY_Pos (16UL) /*!< RXDLY (Bit 16) */
+#define SPI0_CTRL_RXDLY_Msk (0x70000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define SPI0_CTRL_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define SPI0_CTRL_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define SPI0_CTRL_UDRCFG_Pos (7UL) /*!< UDRCFG (Bit 7) */
+#define SPI0_CTRL_UDRCFG_Msk (0x80UL) /*!< UDRCFG (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_LSB_Pos (6UL) /*!< LSB (Bit 6) */
+#define SPI0_CTRL_LSB_Msk (0x40UL) /*!< LSB (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_RXEN_Pos (5UL) /*!< RXEN (Bit 5) */
+#define SPI0_CTRL_RXEN_Msk (0x20UL) /*!< RXEN (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_TXEN_Pos (4UL) /*!< TXEN (Bit 4) */
+#define SPI0_CTRL_TXEN_Msk (0x10UL) /*!< TXEN (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_SHZOE_Pos (3UL) /*!< SHZOE (Bit 3) */
+#define SPI0_CTRL_SHZOE_Msk (0x8UL) /*!< SHZOE (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_CPOL_Pos (2UL) /*!< CPOL (Bit 2) */
+#define SPI0_CTRL_CPOL_Msk (0x4UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_CPHA_Pos (1UL) /*!< CPHA (Bit 1) */
+#define SPI0_CTRL_CPHA_Msk (0x2UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+#define SPI0_CTRL_MSTEN_Pos (0UL) /*!< MSTEN (Bit 0) */
+#define SPI0_CTRL_MSTEN_Msk (0x1UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+/* ========================================================= BAUD ========================================================== */
+#define SPI0_BAUD_BAUD_Pos (1UL) /*!< BAUD (Bit 1) */
+#define SPI0_BAUD_BAUD_Msk (0xffeUL) /*!< BAUD (Bitfield-Mask: 0x7ff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define SPI0_FIFOCTRL_RXFTLR_Pos (4UL) /*!< RXFTLR (Bit 4) */
+#define SPI0_FIFOCTRL_RXFTLR_Msk (0xf0UL) /*!< RXFTLR (Bitfield-Mask: 0x0f) */
+#define SPI0_FIFOCTRL_TXFTLR_Pos (0UL) /*!< TXFTLR (Bit 0) */
+#define SPI0_FIFOCTRL_TXFTLR_Msk (0xfUL) /*!< TXFTLR (Bitfield-Mask: 0x0f) */
+/* ========================================================== CNT ========================================================== */
+#define SPI0_CNT_DCNT_Pos (0UL) /*!< DCNT (Bit 0) */
+#define SPI0_CNT_DCNT_Msk (0xffffUL) /*!< DCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= RCNT ========================================================== */
+#define SPI0_RCNT_RCNT_Pos (0UL) /*!< RCNT (Bit 0) */
+#define SPI0_RCNT_RCNT_Msk (0xffffUL) /*!< RCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= START ========================================================= */
+#define SPI0_START_STOP_Pos (1UL) /*!< STOP (Bit 1) */
+#define SPI0_START_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */
+#define SPI0_START_START_Pos (0UL) /*!< START (Bit 0) */
+#define SPI0_START_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ======================================================== TIMING ========================================================= */
+#define SPI0_TIMING_MCSI_Pos (16UL) /*!< MCSI (Bit 16) */
+#define SPI0_TIMING_MCSI_Msk (0x1f0000UL) /*!< MCSI (Bitfield-Mask: 0x1f) */
+#define SPI0_TIMING_MIDI_Pos (0UL) /*!< MIDI (Bit 0) */
+#define SPI0_TIMING_MIDI_Msk (0x1fUL) /*!< MIDI (Bitfield-Mask: 0x1f) */
+/* ========================================================= INTEN ========================================================= */
+#define SPI0_INTEN_RXCIE_Pos (11UL) /*!< RXCIE (Bit 11) */
+#define SPI0_INTEN_RXCIE_Msk (0x800UL) /*!< RXCIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_TXCIE_Pos (10UL) /*!< TXCIE (Bit 10) */
+#define SPI0_INTEN_TXCIE_Msk (0x400UL) /*!< TXCIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_RXDEIE_Pos (9UL) /*!< RXDEIE (Bit 9) */
+#define SPI0_INTEN_RXDEIE_Msk (0x200UL) /*!< RXDEIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_TXDEIE_Pos (8UL) /*!< TXDEIE (Bit 8) */
+#define SPI0_INTEN_TXDEIE_Msk (0x100UL) /*!< TXDEIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_MDFIE_Pos (7UL) /*!< MDFIE (Bit 7) */
+#define SPI0_INTEN_MDFIE_Msk (0x80UL) /*!< MDFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_OPFIE_Pos (6UL) /*!< OPFIE (Bit 6) */
+#define SPI0_INTEN_OPFIE_Msk (0x40UL) /*!< OPFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_TXUFIE_Pos (5UL) /*!< TXUFIE (Bit 5) */
+#define SPI0_INTEN_TXUFIE_Msk (0x20UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_TXOFIE_Pos (4UL) /*!< TXOFIE (Bit 4) */
+#define SPI0_INTEN_TXOFIE_Msk (0x10UL) /*!< TXOFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_RXUFIE_Pos (3UL) /*!< RXUFIE (Bit 3) */
+#define SPI0_INTEN_RXUFIE_Msk (0x8UL) /*!< RXUFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_RXOFIE_Pos (2UL) /*!< RXOFIE (Bit 2) */
+#define SPI0_INTEN_RXOFIE_Msk (0x4UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_TXEIE_Pos (1UL) /*!< TXEIE (Bit 1) */
+#define SPI0_INTEN_TXEIE_Msk (0x2UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define SPI0_INTEN_RXFIE_Pos (0UL) /*!< RXFIE (Bit 0) */
+#define SPI0_INTEN_RXFIE_Msk (0x1UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define SPI0_INT_RXCI_Pos (11UL) /*!< RXCI (Bit 11) */
+#define SPI0_INT_RXCI_Msk (0x800UL) /*!< RXCI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_TXCI_Pos (10UL) /*!< TXCI (Bit 10) */
+#define SPI0_INT_TXCI_Msk (0x400UL) /*!< TXCI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_RXDEI_Pos (9UL) /*!< RXDEI (Bit 9) */
+#define SPI0_INT_RXDEI_Msk (0x200UL) /*!< RXDEI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_TXDEI_Pos (8UL) /*!< TXDEI (Bit 8) */
+#define SPI0_INT_TXDEI_Msk (0x100UL) /*!< TXDEI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_MDFI_Pos (7UL) /*!< MDFI (Bit 7) */
+#define SPI0_INT_MDFI_Msk (0x80UL) /*!< MDFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_OPFI_Pos (6UL) /*!< OPFI (Bit 6) */
+#define SPI0_INT_OPFI_Msk (0x40UL) /*!< OPFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_TXUFI_Pos (5UL) /*!< TXUFI (Bit 5) */
+#define SPI0_INT_TXUFI_Msk (0x20UL) /*!< TXUFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_TXOFI_Pos (4UL) /*!< TXOFI (Bit 4) */
+#define SPI0_INT_TXOFI_Msk (0x10UL) /*!< TXOFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_RXUFI_Pos (3UL) /*!< RXUFI (Bit 3) */
+#define SPI0_INT_RXUFI_Msk (0x8UL) /*!< RXUFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_RXOFI_Pos (2UL) /*!< RXOFI (Bit 2) */
+#define SPI0_INT_RXOFI_Msk (0x4UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define SPI0_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define SPI0_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define SPI0_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define SPI0_STATUS_RFF_Pos (30UL) /*!< RFF (Bit 30) */
+#define SPI0_STATUS_RFF_Msk (0x40000000UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define SPI0_STATUS_RFE_Pos (29UL) /*!< RFE (Bit 29) */
+#define SPI0_STATUS_RFE_Msk (0x20000000UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define SPI0_STATUS_RXFLR_Pos (24UL) /*!< RXFLR (Bit 24) */
+#define SPI0_STATUS_RXFLR_Msk (0x1f000000UL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
+#define SPI0_STATUS_TFF_Pos (22UL) /*!< TFF (Bit 22) */
+#define SPI0_STATUS_TFF_Msk (0x400000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define SPI0_STATUS_TFE_Pos (21UL) /*!< TFE (Bit 21) */
+#define SPI0_STATUS_TFE_Msk (0x200000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define SPI0_STATUS_TXFLR_Pos (16UL) /*!< TXFLR (Bit 16) */
+#define SPI0_STATUS_TXFLR_Msk (0x1f0000UL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
+#define SPI0_STATUS_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */
+#define SPI0_STATUS_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+/* ========================================================== TDR ========================================================== */
+#define SPI0_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define SPI0_TDR_TD_Msk (0xffffUL) /*!< TD (Bitfield-Mask: 0xffff) */
+/* ========================================================== RDR ========================================================== */
+#define SPI0_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define SPI0_RDR_RD_Msk (0xffffUL) /*!< RD (Bitfield-Mask: 0xffff) */
+/* ========================================================= UDRDR ========================================================= */
+#define SPI0_UDRDR_UDRDR_Pos (0UL) /*!< UDRDR (Bit 0) */
+#define SPI0_UDRDR_UDRDR_Msk (0xffffUL) /*!< UDRDR (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ SPI1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define SPI1_ENABLE_CSI_Pos (15UL) /*!< CSI (Bit 15) */
+#define SPI1_ENABLE_CSI_Msk (0x8000UL) /*!< CSI (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_CSIS_Pos (14UL) /*!< CSIS (Bit 14) */
+#define SPI1_ENABLE_CSIS_Msk (0x4000UL) /*!< CSIS (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_CSO_Pos (13UL) /*!< CSO (Bit 13) */
+#define SPI1_ENABLE_CSO_Msk (0x2000UL) /*!< CSO (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_CSOS_Pos (12UL) /*!< CSOS (Bit 12) */
+#define SPI1_ENABLE_CSOS_Msk (0x1000UL) /*!< CSOS (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_DTE_Pos (9UL) /*!< DTE (Bit 9) */
+#define SPI1_ENABLE_DTE_Msk (0x200UL) /*!< DTE (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_DRE_Pos (8UL) /*!< DRE (Bit 8) */
+#define SPI1_ENABLE_DRE_Msk (0x100UL) /*!< DRE (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_LOOP_Pos (7UL) /*!< LOOP (Bit 7) */
+#define SPI1_ENABLE_LOOP_Msk (0x80UL) /*!< LOOP (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_SWAP_Pos (6UL) /*!< SWAP (Bit 6) */
+#define SPI1_ENABLE_SWAP_Msk (0x40UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_CSPOL_Pos (5UL) /*!< CSPOL (Bit 5) */
+#define SPI1_ENABLE_CSPOL_Msk (0x20UL) /*!< CSPOL (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_CSSEL_Pos (4UL) /*!< CSSEL (Bit 4) */
+#define SPI1_ENABLE_CSSEL_Msk (0x10UL) /*!< CSSEL (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_TWE_Pos (3UL) /*!< TWE (Bit 3) */
+#define SPI1_ENABLE_TWE_Msk (0x8UL) /*!< TWE (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_TFR_Pos (2UL) /*!< TFR (Bit 2) */
+#define SPI1_ENABLE_TFR_Msk (0x4UL) /*!< TFR (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_RFR_Pos (1UL) /*!< RFR (Bit 1) */
+#define SPI1_ENABLE_RFR_Msk (0x2UL) /*!< RFR (Bitfield-Mask: 0x01) */
+#define SPI1_ENABLE_SPIEN_Pos (0UL) /*!< SPIEN (Bit 0) */
+#define SPI1_ENABLE_SPIEN_Msk (0x1UL) /*!< SPIEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define SPI1_CTRL_RXDLY_Pos (16UL) /*!< RXDLY (Bit 16) */
+#define SPI1_CTRL_RXDLY_Msk (0x70000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define SPI1_CTRL_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define SPI1_CTRL_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define SPI1_CTRL_UDRCFG_Pos (7UL) /*!< UDRCFG (Bit 7) */
+#define SPI1_CTRL_UDRCFG_Msk (0x80UL) /*!< UDRCFG (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_LSB_Pos (6UL) /*!< LSB (Bit 6) */
+#define SPI1_CTRL_LSB_Msk (0x40UL) /*!< LSB (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_RXEN_Pos (5UL) /*!< RXEN (Bit 5) */
+#define SPI1_CTRL_RXEN_Msk (0x20UL) /*!< RXEN (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_TXEN_Pos (4UL) /*!< TXEN (Bit 4) */
+#define SPI1_CTRL_TXEN_Msk (0x10UL) /*!< TXEN (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_SHZOE_Pos (3UL) /*!< SHZOE (Bit 3) */
+#define SPI1_CTRL_SHZOE_Msk (0x8UL) /*!< SHZOE (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_CPOL_Pos (2UL) /*!< CPOL (Bit 2) */
+#define SPI1_CTRL_CPOL_Msk (0x4UL) /*!< CPOL (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_CPHA_Pos (1UL) /*!< CPHA (Bit 1) */
+#define SPI1_CTRL_CPHA_Msk (0x2UL) /*!< CPHA (Bitfield-Mask: 0x01) */
+#define SPI1_CTRL_MSTEN_Pos (0UL) /*!< MSTEN (Bit 0) */
+#define SPI1_CTRL_MSTEN_Msk (0x1UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+/* ========================================================= BAUD ========================================================== */
+#define SPI1_BAUD_BAUD_Pos (1UL) /*!< BAUD (Bit 1) */
+#define SPI1_BAUD_BAUD_Msk (0xffeUL) /*!< BAUD (Bitfield-Mask: 0x7ff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define SPI1_FIFOCTRL_RXFTLR_Pos (4UL) /*!< RXFTLR (Bit 4) */
+#define SPI1_FIFOCTRL_RXFTLR_Msk (0xf0UL) /*!< RXFTLR (Bitfield-Mask: 0x0f) */
+#define SPI1_FIFOCTRL_TXFTLR_Pos (0UL) /*!< TXFTLR (Bit 0) */
+#define SPI1_FIFOCTRL_TXFTLR_Msk (0xfUL) /*!< TXFTLR (Bitfield-Mask: 0x0f) */
+/* ========================================================== CNT ========================================================== */
+#define SPI1_CNT_DCNT_Pos (0UL) /*!< DCNT (Bit 0) */
+#define SPI1_CNT_DCNT_Msk (0xffffUL) /*!< DCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= RCNT ========================================================== */
+#define SPI1_RCNT_RCNT_Pos (0UL) /*!< RCNT (Bit 0) */
+#define SPI1_RCNT_RCNT_Msk (0xffffUL) /*!< RCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= START ========================================================= */
+#define SPI1_START_STOP_Pos (1UL) /*!< STOP (Bit 1) */
+#define SPI1_START_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */
+#define SPI1_START_START_Pos (0UL) /*!< START (Bit 0) */
+#define SPI1_START_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ======================================================== TIMING ========================================================= */
+#define SPI1_TIMING_MCSI_Pos (16UL) /*!< MCSI (Bit 16) */
+#define SPI1_TIMING_MCSI_Msk (0x1f0000UL) /*!< MCSI (Bitfield-Mask: 0x1f) */
+#define SPI1_TIMING_MIDI_Pos (0UL) /*!< MIDI (Bit 0) */
+#define SPI1_TIMING_MIDI_Msk (0x1fUL) /*!< MIDI (Bitfield-Mask: 0x1f) */
+/* ========================================================= INTEN ========================================================= */
+#define SPI1_INTEN_RXCIE_Pos (11UL) /*!< RXCIE (Bit 11) */
+#define SPI1_INTEN_RXCIE_Msk (0x800UL) /*!< RXCIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_TXCIE_Pos (10UL) /*!< TXCIE (Bit 10) */
+#define SPI1_INTEN_TXCIE_Msk (0x400UL) /*!< TXCIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_RXDEIE_Pos (9UL) /*!< RXDEIE (Bit 9) */
+#define SPI1_INTEN_RXDEIE_Msk (0x200UL) /*!< RXDEIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_TXDEIE_Pos (8UL) /*!< TXDEIE (Bit 8) */
+#define SPI1_INTEN_TXDEIE_Msk (0x100UL) /*!< TXDEIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_MDFIE_Pos (7UL) /*!< MDFIE (Bit 7) */
+#define SPI1_INTEN_MDFIE_Msk (0x80UL) /*!< MDFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_OPFIE_Pos (6UL) /*!< OPFIE (Bit 6) */
+#define SPI1_INTEN_OPFIE_Msk (0x40UL) /*!< OPFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_TXUFIE_Pos (5UL) /*!< TXUFIE (Bit 5) */
+#define SPI1_INTEN_TXUFIE_Msk (0x20UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_TXOFIE_Pos (4UL) /*!< TXOFIE (Bit 4) */
+#define SPI1_INTEN_TXOFIE_Msk (0x10UL) /*!< TXOFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_RXUFIE_Pos (3UL) /*!< RXUFIE (Bit 3) */
+#define SPI1_INTEN_RXUFIE_Msk (0x8UL) /*!< RXUFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_RXOFIE_Pos (2UL) /*!< RXOFIE (Bit 2) */
+#define SPI1_INTEN_RXOFIE_Msk (0x4UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_TXEIE_Pos (1UL) /*!< TXEIE (Bit 1) */
+#define SPI1_INTEN_TXEIE_Msk (0x2UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define SPI1_INTEN_RXFIE_Pos (0UL) /*!< RXFIE (Bit 0) */
+#define SPI1_INTEN_RXFIE_Msk (0x1UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+/* ========================================================== INT ========================================================== */
+#define SPI1_INT_RXCI_Pos (11UL) /*!< RXCI (Bit 11) */
+#define SPI1_INT_RXCI_Msk (0x800UL) /*!< RXCI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_TXCI_Pos (10UL) /*!< TXCI (Bit 10) */
+#define SPI1_INT_TXCI_Msk (0x400UL) /*!< TXCI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_RXDEI_Pos (9UL) /*!< RXDEI (Bit 9) */
+#define SPI1_INT_RXDEI_Msk (0x200UL) /*!< RXDEI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_TXDEI_Pos (8UL) /*!< TXDEI (Bit 8) */
+#define SPI1_INT_TXDEI_Msk (0x100UL) /*!< TXDEI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_MDFI_Pos (7UL) /*!< MDFI (Bit 7) */
+#define SPI1_INT_MDFI_Msk (0x80UL) /*!< MDFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_OPFI_Pos (6UL) /*!< OPFI (Bit 6) */
+#define SPI1_INT_OPFI_Msk (0x40UL) /*!< OPFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_TXUFI_Pos (5UL) /*!< TXUFI (Bit 5) */
+#define SPI1_INT_TXUFI_Msk (0x20UL) /*!< TXUFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_TXOFI_Pos (4UL) /*!< TXOFI (Bit 4) */
+#define SPI1_INT_TXOFI_Msk (0x10UL) /*!< TXOFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_RXUFI_Pos (3UL) /*!< RXUFI (Bit 3) */
+#define SPI1_INT_RXUFI_Msk (0x8UL) /*!< RXUFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_RXOFI_Pos (2UL) /*!< RXOFI (Bit 2) */
+#define SPI1_INT_RXOFI_Msk (0x4UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define SPI1_INT_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define SPI1_INT_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define SPI1_INT_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define SPI1_STATUS_RFF_Pos (30UL) /*!< RFF (Bit 30) */
+#define SPI1_STATUS_RFF_Msk (0x40000000UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define SPI1_STATUS_RFE_Pos (29UL) /*!< RFE (Bit 29) */
+#define SPI1_STATUS_RFE_Msk (0x20000000UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define SPI1_STATUS_RXFLR_Pos (24UL) /*!< RXFLR (Bit 24) */
+#define SPI1_STATUS_RXFLR_Msk (0x1f000000UL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
+#define SPI1_STATUS_TFF_Pos (22UL) /*!< TFF (Bit 22) */
+#define SPI1_STATUS_TFF_Msk (0x400000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define SPI1_STATUS_TFE_Pos (21UL) /*!< TFE (Bit 21) */
+#define SPI1_STATUS_TFE_Msk (0x200000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define SPI1_STATUS_TXFLR_Pos (16UL) /*!< TXFLR (Bit 16) */
+#define SPI1_STATUS_TXFLR_Msk (0x1f0000UL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
+#define SPI1_STATUS_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */
+#define SPI1_STATUS_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+/* ========================================================== TDR ========================================================== */
+#define SPI1_TDR_TD_Pos (0UL) /*!< TD (Bit 0) */
+#define SPI1_TDR_TD_Msk (0xffffUL) /*!< TD (Bitfield-Mask: 0xffff) */
+/* ========================================================== RDR ========================================================== */
+#define SPI1_RDR_RD_Pos (0UL) /*!< RD (Bit 0) */
+#define SPI1_RDR_RD_Msk (0xffffUL) /*!< RD (Bitfield-Mask: 0xffff) */
+/* ========================================================= UDRDR ========================================================= */
+#define SPI1_UDRDR_UDRDR_Pos (0UL) /*!< UDRDR (Bit 0) */
+#define SPI1_UDRDR_UDRDR_Msk (0xffffUL) /*!< UDRDR (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ RCU ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PLL0CR ========================================================= */
+#define RCU_PLL0CR_EN_Pos (31UL) /*!< EN (Bit 31) */
+#define RCU_PLL0CR_EN_Msk (0x80000000UL) /*!< EN (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_LKF_Pos (30UL) /*!< LKF (Bit 30) */
+#define RCU_PLL0CR_LKF_Msk (0x40000000UL) /*!< LKF (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_RFD_Pos (11UL) /*!< RFD (Bit 11) */
+#define RCU_PLL0CR_RFD_Msk (0x800UL) /*!< RFD (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_LPF_Pos (10UL) /*!< LPF (Bit 10) */
+#define RCU_PLL0CR_LPF_Msk (0x400UL) /*!< LPF (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_BDS_Pos (8UL) /*!< BDS (Bit 8) */
+#define RCU_PLL0CR_BDS_Msk (0x300UL) /*!< BDS (Bitfield-Mask: 0x03) */
+#define RCU_PLL0CR_UG_Pos (3UL) /*!< UG (Bit 3) */
+#define RCU_PLL0CR_UG_Msk (0x8UL) /*!< UG (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_ARE_Pos (2UL) /*!< ARE (Bit 2) */
+#define RCU_PLL0CR_ARE_Msk (0x4UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define RCU_PLL0CR_RCS_Pos (0UL) /*!< RCS (Bit 0) */
+#define RCU_PLL0CR_RCS_Msk (0x3UL) /*!< RCS (Bitfield-Mask: 0x03) */
+/* ======================================================== PLL0FR ========================================================= */
+#define RCU_PLL0FR_INT_Pos (16UL) /*!< INT (Bit 16) */
+#define RCU_PLL0FR_INT_Msk (0x3fff0000UL) /*!< INT (Bitfield-Mask: 0x3fff) */
+#define RCU_PLL0FR_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
+#define RCU_PLL0FR_FRAC_Msk (0xffffUL) /*!< FRAC (Bitfield-Mask: 0xffff) */
+/* ========================================================== CCR ========================================================== */
+#define RCU_CCR_P1PSC_Pos (12UL) /*!< P1PSC (Bit 12) */
+#define RCU_CCR_P1PSC_Msk (0xf000UL) /*!< P1PSC (Bitfield-Mask: 0x0f) */
+#define RCU_CCR_P0PSC_Pos (8UL) /*!< P0PSC (Bit 8) */
+#define RCU_CCR_P0PSC_Msk (0xf00UL) /*!< P0PSC (Bitfield-Mask: 0x0f) */
+#define RCU_CCR_HPSC_Pos (2UL) /*!< HPSC (Bit 2) */
+#define RCU_CCR_HPSC_Msk (0xfcUL) /*!< HPSC (Bitfield-Mask: 0x3f) */
+#define RCU_CCR_SCS_Pos (0UL) /*!< SCS (Bit 0) */
+#define RCU_CCR_SCS_Msk (0x3UL) /*!< SCS (Bitfield-Mask: 0x03) */
+/* ========================================================= PCSR ========================================================== */
+#define RCU_PCSR_TMR6CS_Pos (8UL) /*!< TMR6CS (Bit 8) */
+#define RCU_PCSR_TMR6CS_Msk (0x300UL) /*!< TMR6CS (Bitfield-Mask: 0x03) */
+#define RCU_PCSR_CANCS_Pos (6UL) /*!< CANCS (Bit 6) */
+#define RCU_PCSR_CANCS_Msk (0xc0UL) /*!< CANCS (Bitfield-Mask: 0x03) */
+#define RCU_PCSR_USBCS_Pos (4UL) /*!< USBCS (Bit 4) */
+#define RCU_PCSR_USBCS_Msk (0x30UL) /*!< USBCS (Bitfield-Mask: 0x03) */
+#define RCU_PCSR_ADCCS_Pos (2UL) /*!< ADCCS (Bit 2) */
+#define RCU_PCSR_ADCCS_Msk (0xcUL) /*!< ADCCS (Bitfield-Mask: 0x03) */
+#define RCU_PCSR_PWMCS_Pos (0UL) /*!< PWMCS (Bit 0) */
+#define RCU_PCSR_PWMCS_Msk (0x3UL) /*!< PWMCS (Bitfield-Mask: 0x03) */
+/* ========================================================= PCDR0 ========================================================= */
+#define RCU_PCDR0_PDDIV_Pos (24UL) /*!< PDDIV (Bit 24) */
+#define RCU_PCDR0_PDDIV_Msk (0xff000000UL) /*!< PDDIV (Bitfield-Mask: 0xff) */
+#define RCU_PCDR0_PCDIV_Pos (16UL) /*!< PCDIV (Bit 16) */
+#define RCU_PCDR0_PCDIV_Msk (0xff0000UL) /*!< PCDIV (Bitfield-Mask: 0xff) */
+#define RCU_PCDR0_PBDIV_Pos (8UL) /*!< PBDIV (Bit 8) */
+#define RCU_PCDR0_PBDIV_Msk (0xff00UL) /*!< PBDIV (Bitfield-Mask: 0xff) */
+#define RCU_PCDR0_PADIV_Pos (0UL) /*!< PADIV (Bit 0) */
+#define RCU_PCDR0_PADIV_Msk (0xffUL) /*!< PADIV (Bitfield-Mask: 0xff) */
+/* ========================================================= PCDR1 ========================================================= */
+#define RCU_PCDR1_PFDIV_Pos (8UL) /*!< PFDIV (Bit 8) */
+#define RCU_PCDR1_PFDIV_Msk (0xff00UL) /*!< PFDIV (Bitfield-Mask: 0xff) */
+#define RCU_PCDR1_PEDIV_Pos (0UL) /*!< PEDIV (Bit 0) */
+#define RCU_PCDR1_PEDIV_Msk (0xffUL) /*!< PEDIV (Bitfield-Mask: 0xff) */
+/* ========================================================= PCDR2 ========================================================= */
+#define RCU_PCDR2_CANDIV_Pos (12UL) /*!< CANDIV (Bit 12) */
+#define RCU_PCDR2_CANDIV_Msk (0xf000UL) /*!< CANDIV (Bitfield-Mask: 0x0f) */
+#define RCU_PCDR2_USBDIV_Pos (8UL) /*!< USBDIV (Bit 8) */
+#define RCU_PCDR2_USBDIV_Msk (0xf00UL) /*!< USBDIV (Bitfield-Mask: 0x0f) */
+#define RCU_PCDR2_ADCDIV_Pos (4UL) /*!< ADCDIV (Bit 4) */
+#define RCU_PCDR2_ADCDIV_Msk (0xf0UL) /*!< ADCDIV (Bitfield-Mask: 0x0f) */
+#define RCU_PCDR2_PWMDIV_Pos (0UL) /*!< PWMDIV (Bit 0) */
+#define RCU_PCDR2_PWMDIV_Msk (0xfUL) /*!< PWMDIV (Bitfield-Mask: 0x0f) */
+/* ========================================================= PCENR ========================================================= */
+#define RCU_PCENR_TMR6FEN_Pos (15UL) /*!< TMR6FEN (Bit 15) */
+#define RCU_PCENR_TMR6FEN_Msk (0x8000UL) /*!< TMR6FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_CAN1FEN_Pos (14UL) /*!< CAN1FEN (Bit 14) */
+#define RCU_PCENR_CAN1FEN_Msk (0x4000UL) /*!< CAN1FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_CAN0FEN_Pos (13UL) /*!< CAN0FEN (Bit 13) */
+#define RCU_PCENR_CAN0FEN_Msk (0x2000UL) /*!< CAN0FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_USBFEN_Pos (12UL) /*!< USBFEN (Bit 12) */
+#define RCU_PCENR_USBFEN_Msk (0x1000UL) /*!< USBFEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM7FEN_Pos (11UL) /*!< PWM7FEN (Bit 11) */
+#define RCU_PCENR_PWM7FEN_Msk (0x800UL) /*!< PWM7FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM6FEN_Pos (10UL) /*!< PWM6FEN (Bit 10) */
+#define RCU_PCENR_PWM6FEN_Msk (0x400UL) /*!< PWM6FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM5FEN_Pos (9UL) /*!< PWM5FEN (Bit 9) */
+#define RCU_PCENR_PWM5FEN_Msk (0x200UL) /*!< PWM5FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM4FEN_Pos (8UL) /*!< PWM4FEN (Bit 8) */
+#define RCU_PCENR_PWM4FEN_Msk (0x100UL) /*!< PWM4FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM3FEN_Pos (7UL) /*!< PWM3FEN (Bit 7) */
+#define RCU_PCENR_PWM3FEN_Msk (0x80UL) /*!< PWM3FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM2FEN_Pos (6UL) /*!< PWM2FEN (Bit 6) */
+#define RCU_PCENR_PWM2FEN_Msk (0x40UL) /*!< PWM2FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM1FEN_Pos (5UL) /*!< PWM1FEN (Bit 5) */
+#define RCU_PCENR_PWM1FEN_Msk (0x20UL) /*!< PWM1FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_PWM0FEN_Pos (4UL) /*!< PWM0FEN (Bit 4) */
+#define RCU_PCENR_PWM0FEN_Msk (0x10UL) /*!< PWM0FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_ADC3FEN_Pos (3UL) /*!< ADC3FEN (Bit 3) */
+#define RCU_PCENR_ADC3FEN_Msk (0x8UL) /*!< ADC3FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_ADC2FEN_Pos (2UL) /*!< ADC2FEN (Bit 2) */
+#define RCU_PCENR_ADC2FEN_Msk (0x4UL) /*!< ADC2FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_ADC1FEN_Pos (1UL) /*!< ADC1FEN (Bit 1) */
+#define RCU_PCENR_ADC1FEN_Msk (0x2UL) /*!< ADC1FEN (Bitfield-Mask: 0x01) */
+#define RCU_PCENR_ADC0FEN_Pos (0UL) /*!< ADC0FEN (Bit 0) */
+#define RCU_PCENR_ADC0FEN_Msk (0x1UL) /*!< ADC0FEN (Bitfield-Mask: 0x01) */
+/* ======================================================== APB0ENR ======================================================== */
+#define RCU_APB0ENR_TMR6EN_Pos (8UL) /*!< TMR6EN (Bit 8) */
+#define RCU_APB0ENR_TMR6EN_Msk (0x100UL) /*!< TMR6EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_TMR8EN_Pos (7UL) /*!< TMR8EN (Bit 7) */
+#define RCU_APB0ENR_TMR8EN_Msk (0x80UL) /*!< TMR8EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_TMR7EN_Pos (6UL) /*!< TMR7EN (Bit 6) */
+#define RCU_APB0ENR_TMR7EN_Msk (0x40UL) /*!< TMR7EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_UART2EN_Pos (5UL) /*!< UART2EN (Bit 5) */
+#define RCU_APB0ENR_UART2EN_Msk (0x20UL) /*!< UART2EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_UART1EN_Pos (4UL) /*!< UART1EN (Bit 4) */
+#define RCU_APB0ENR_UART1EN_Msk (0x10UL) /*!< UART1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_UART0EN_Pos (3UL) /*!< UART0EN (Bit 3) */
+#define RCU_APB0ENR_UART0EN_Msk (0x8UL) /*!< UART0EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_I2C2EN_Pos (2UL) /*!< I2C2EN (Bit 2) */
+#define RCU_APB0ENR_I2C2EN_Msk (0x4UL) /*!< I2C2EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_I2C1EN_Pos (1UL) /*!< I2C1EN (Bit 1) */
+#define RCU_APB0ENR_I2C1EN_Msk (0x2UL) /*!< I2C1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB0ENR_I2C0EN_Pos (0UL) /*!< I2C0EN (Bit 0) */
+#define RCU_APB0ENR_I2C0EN_Msk (0x1UL) /*!< I2C0EN (Bitfield-Mask: 0x01) */
+/* ======================================================== APB1ENR ======================================================== */
+#define RCU_APB1ENR_TMR2EN_Pos (13UL) /*!< TMR2EN (Bit 13) */
+#define RCU_APB1ENR_TMR2EN_Msk (0x2000UL) /*!< TMR2EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_TMR1EN_Pos (12UL) /*!< TMR1EN (Bit 12) */
+#define RCU_APB1ENR_TMR1EN_Msk (0x1000UL) /*!< TMR1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_TMR0EN_Pos (11UL) /*!< TMR0EN (Bit 11) */
+#define RCU_APB1ENR_TMR0EN_Msk (0x800UL) /*!< TMR0EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_PDM3EN_Pos (10UL) /*!< PDM3EN (Bit 10) */
+#define RCU_APB1ENR_PDM3EN_Msk (0x400UL) /*!< PDM3EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_PDM2EN_Pos (9UL) /*!< PDM2EN (Bit 9) */
+#define RCU_APB1ENR_PDM2EN_Msk (0x200UL) /*!< PDM2EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_PDM1EN_Pos (8UL) /*!< PDM1EN (Bit 8) */
+#define RCU_APB1ENR_PDM1EN_Msk (0x100UL) /*!< PDM1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_PDM0EN_Pos (7UL) /*!< PDM0EN (Bit 7) */
+#define RCU_APB1ENR_PDM0EN_Msk (0x80UL) /*!< PDM0EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_XIFEN_Pos (6UL) /*!< XIFEN (Bit 6) */
+#define RCU_APB1ENR_XIFEN_Msk (0x40UL) /*!< XIFEN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_CAN1EN_Pos (5UL) /*!< CAN1EN (Bit 5) */
+#define RCU_APB1ENR_CAN1EN_Msk (0x20UL) /*!< CAN1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_CAN0EN_Pos (4UL) /*!< CAN0EN (Bit 4) */
+#define RCU_APB1ENR_CAN0EN_Msk (0x10UL) /*!< CAN0EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_SPI1EN_Pos (3UL) /*!< SPI1EN (Bit 3) */
+#define RCU_APB1ENR_SPI1EN_Msk (0x8UL) /*!< SPI1EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_SPI0EN_Pos (2UL) /*!< SPI0EN (Bit 2) */
+#define RCU_APB1ENR_SPI0EN_Msk (0x4UL) /*!< SPI0EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_UART4EN_Pos (1UL) /*!< UART4EN (Bit 1) */
+#define RCU_APB1ENR_UART4EN_Msk (0x2UL) /*!< UART4EN (Bitfield-Mask: 0x01) */
+#define RCU_APB1ENR_UART3EN_Pos (0UL) /*!< UART3EN (Bit 0) */
+#define RCU_APB1ENR_UART3EN_Msk (0x1UL) /*!< UART3EN (Bitfield-Mask: 0x01) */
+/* ======================================================== AHB0ENR ======================================================== */
+#define RCU_AHB0ENR_QEI2EN_Pos (12UL) /*!< QEI2EN (Bit 12) */
+#define RCU_AHB0ENR_QEI2EN_Msk (0x1000UL) /*!< QEI2EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_QEI1EN_Pos (11UL) /*!< QEI1EN (Bit 11) */
+#define RCU_AHB0ENR_QEI1EN_Msk (0x800UL) /*!< QEI1EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_QEI0EN_Pos (10UL) /*!< QEI0EN (Bit 10) */
+#define RCU_AHB0ENR_QEI0EN_Msk (0x400UL) /*!< QEI0EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_TMR4EN_Pos (9UL) /*!< TMR4EN (Bit 9) */
+#define RCU_AHB0ENR_TMR4EN_Msk (0x200UL) /*!< TMR4EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_TMR3EN_Pos (8UL) /*!< TMR3EN (Bit 8) */
+#define RCU_AHB0ENR_TMR3EN_Msk (0x100UL) /*!< TMR3EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PFEN_Pos (7UL) /*!< PFEN (Bit 7) */
+#define RCU_AHB0ENR_PFEN_Msk (0x80UL) /*!< PFEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PEEN_Pos (6UL) /*!< PEEN (Bit 6) */
+#define RCU_AHB0ENR_PEEN_Msk (0x40UL) /*!< PEEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PDEN_Pos (5UL) /*!< PDEN (Bit 5) */
+#define RCU_AHB0ENR_PDEN_Msk (0x20UL) /*!< PDEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PCEN_Pos (4UL) /*!< PCEN (Bit 4) */
+#define RCU_AHB0ENR_PCEN_Msk (0x10UL) /*!< PCEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PBEN_Pos (3UL) /*!< PBEN (Bit 3) */
+#define RCU_AHB0ENR_PBEN_Msk (0x8UL) /*!< PBEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_PAEN_Pos (2UL) /*!< PAEN (Bit 2) */
+#define RCU_AHB0ENR_PAEN_Msk (0x4UL) /*!< PAEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_FLSEN_Pos (1UL) /*!< FLSEN (Bit 1) */
+#define RCU_AHB0ENR_FLSEN_Msk (0x2UL) /*!< FLSEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB0ENR_DMAEN_Pos (0UL) /*!< DMAEN (Bit 0) */
+#define RCU_AHB0ENR_DMAEN_Msk (0x1UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+/* ======================================================== AHB1ENR ======================================================== */
+#define RCU_AHB1ENR_CORDICEN_Pos (23UL) /*!< CORDICEN (Bit 23) */
+#define RCU_AHB1ENR_CORDICEN_Msk (0x800000UL) /*!< CORDICEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR5EN_Pos (22UL) /*!< IIR5EN (Bit 22) */
+#define RCU_AHB1ENR_IIR5EN_Msk (0x400000UL) /*!< IIR5EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR4EN_Pos (21UL) /*!< IIR4EN (Bit 21) */
+#define RCU_AHB1ENR_IIR4EN_Msk (0x200000UL) /*!< IIR4EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR3EN_Pos (20UL) /*!< IIR3EN (Bit 20) */
+#define RCU_AHB1ENR_IIR3EN_Msk (0x100000UL) /*!< IIR3EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR2EN_Pos (19UL) /*!< IIR2EN (Bit 19) */
+#define RCU_AHB1ENR_IIR2EN_Msk (0x80000UL) /*!< IIR2EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR1EN_Pos (18UL) /*!< IIR1EN (Bit 18) */
+#define RCU_AHB1ENR_IIR1EN_Msk (0x40000UL) /*!< IIR1EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_IIR0EN_Pos (17UL) /*!< IIR0EN (Bit 17) */
+#define RCU_AHB1ENR_IIR0EN_Msk (0x20000UL) /*!< IIR0EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM7EN_Pos (16UL) /*!< PWM7EN (Bit 16) */
+#define RCU_AHB1ENR_PWM7EN_Msk (0x10000UL) /*!< PWM7EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM6EN_Pos (15UL) /*!< PWM6EN (Bit 15) */
+#define RCU_AHB1ENR_PWM6EN_Msk (0x8000UL) /*!< PWM6EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM5EN_Pos (14UL) /*!< PWM5EN (Bit 14) */
+#define RCU_AHB1ENR_PWM5EN_Msk (0x4000UL) /*!< PWM5EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM4EN_Pos (13UL) /*!< PWM4EN (Bit 13) */
+#define RCU_AHB1ENR_PWM4EN_Msk (0x2000UL) /*!< PWM4EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM3EN_Pos (12UL) /*!< PWM3EN (Bit 12) */
+#define RCU_AHB1ENR_PWM3EN_Msk (0x1000UL) /*!< PWM3EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM2EN_Pos (11UL) /*!< PWM2EN (Bit 11) */
+#define RCU_AHB1ENR_PWM2EN_Msk (0x800UL) /*!< PWM2EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM1EN_Pos (10UL) /*!< PWM1EN (Bit 10) */
+#define RCU_AHB1ENR_PWM1EN_Msk (0x400UL) /*!< PWM1EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_PWM0EN_Pos (9UL) /*!< PWM0EN (Bit 9) */
+#define RCU_AHB1ENR_PWM0EN_Msk (0x200UL) /*!< PWM0EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_CMPxEN_Pos (8UL) /*!< CMPxEN (Bit 8) */
+#define RCU_AHB1ENR_CMPxEN_Msk (0x100UL) /*!< CMPxEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_DACxEN_Pos (7UL) /*!< DACxEN (Bit 7) */
+#define RCU_AHB1ENR_DACxEN_Msk (0x80UL) /*!< DACxEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_ADC3EN_Pos (6UL) /*!< ADC3EN (Bit 6) */
+#define RCU_AHB1ENR_ADC3EN_Msk (0x40UL) /*!< ADC3EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_ADC2EN_Pos (5UL) /*!< ADC2EN (Bit 5) */
+#define RCU_AHB1ENR_ADC2EN_Msk (0x20UL) /*!< ADC2EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_ADC1EN_Pos (4UL) /*!< ADC1EN (Bit 4) */
+#define RCU_AHB1ENR_ADC1EN_Msk (0x10UL) /*!< ADC1EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_ADC0EN_Pos (3UL) /*!< ADC0EN (Bit 3) */
+#define RCU_AHB1ENR_ADC0EN_Msk (0x8UL) /*!< ADC0EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_USBEN_Pos (2UL) /*!< USBEN (Bit 2) */
+#define RCU_AHB1ENR_USBEN_Msk (0x4UL) /*!< USBEN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_TMR10EN_Pos (1UL) /*!< TMR10EN (Bit 1) */
+#define RCU_AHB1ENR_TMR10EN_Msk (0x2UL) /*!< TMR10EN (Bitfield-Mask: 0x01) */
+#define RCU_AHB1ENR_TMR9EN_Pos (0UL) /*!< TMR9EN (Bit 0) */
+#define RCU_AHB1ENR_TMR9EN_Msk (0x1UL) /*!< TMR9EN (Bitfield-Mask: 0x01) */
+/* ======================================================= APB0RSTR ======================================================== */
+#define RCU_APB0RSTR_TMR6RST_Pos (8UL) /*!< TMR6RST (Bit 8) */
+#define RCU_APB0RSTR_TMR6RST_Msk (0x100UL) /*!< TMR6RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_TMR8RST_Pos (7UL) /*!< TMR8RST (Bit 7) */
+#define RCU_APB0RSTR_TMR8RST_Msk (0x80UL) /*!< TMR8RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_TMR7RST_Pos (6UL) /*!< TMR7RST (Bit 6) */
+#define RCU_APB0RSTR_TMR7RST_Msk (0x40UL) /*!< TMR7RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_UART2RST_Pos (5UL) /*!< UART2RST (Bit 5) */
+#define RCU_APB0RSTR_UART2RST_Msk (0x20UL) /*!< UART2RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_UART1RST_Pos (4UL) /*!< UART1RST (Bit 4) */
+#define RCU_APB0RSTR_UART1RST_Msk (0x10UL) /*!< UART1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_UART0RST_Pos (3UL) /*!< UART0RST (Bit 3) */
+#define RCU_APB0RSTR_UART0RST_Msk (0x8UL) /*!< UART0RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_I2C2RST_Pos (2UL) /*!< I2C2RST (Bit 2) */
+#define RCU_APB0RSTR_I2C2RST_Msk (0x4UL) /*!< I2C2RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_I2C1RST_Pos (1UL) /*!< I2C1RST (Bit 1) */
+#define RCU_APB0RSTR_I2C1RST_Msk (0x2UL) /*!< I2C1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB0RSTR_I2C0RST_Pos (0UL) /*!< I2C0RST (Bit 0) */
+#define RCU_APB0RSTR_I2C0RST_Msk (0x1UL) /*!< I2C0RST (Bitfield-Mask: 0x01) */
+/* ======================================================= APB1RSTR ======================================================== */
+#define RCU_APB1RSTR_TMR2RST_Pos (13UL) /*!< TMR2RST (Bit 13) */
+#define RCU_APB1RSTR_TMR2RST_Msk (0x2000UL) /*!< TMR2RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_TMR1RST_Pos (12UL) /*!< TMR1RST (Bit 12) */
+#define RCU_APB1RSTR_TMR1RST_Msk (0x1000UL) /*!< TMR1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_TMR0RST_Pos (11UL) /*!< TMR0RST (Bit 11) */
+#define RCU_APB1RSTR_TMR0RST_Msk (0x800UL) /*!< TMR0RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_PDM3RST_Pos (10UL) /*!< PDM3RST (Bit 10) */
+#define RCU_APB1RSTR_PDM3RST_Msk (0x400UL) /*!< PDM3RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_PDM2RST_Pos (9UL) /*!< PDM2RST (Bit 9) */
+#define RCU_APB1RSTR_PDM2RST_Msk (0x200UL) /*!< PDM2RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_PDM1RST_Pos (8UL) /*!< PDM1RST (Bit 8) */
+#define RCU_APB1RSTR_PDM1RST_Msk (0x100UL) /*!< PDM1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_PDM0RST_Pos (7UL) /*!< PDM0RST (Bit 7) */
+#define RCU_APB1RSTR_PDM0RST_Msk (0x80UL) /*!< PDM0RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_XIFRST_Pos (6UL) /*!< XIFRST (Bit 6) */
+#define RCU_APB1RSTR_XIFRST_Msk (0x40UL) /*!< XIFRST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_CAN1RST_Pos (5UL) /*!< CAN1RST (Bit 5) */
+#define RCU_APB1RSTR_CAN1RST_Msk (0x20UL) /*!< CAN1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_CAN0RST_Pos (4UL) /*!< CAN0RST (Bit 4) */
+#define RCU_APB1RSTR_CAN0RST_Msk (0x10UL) /*!< CAN0RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_SPI1RST_Pos (3UL) /*!< SPI1RST (Bit 3) */
+#define RCU_APB1RSTR_SPI1RST_Msk (0x8UL) /*!< SPI1RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_SPI0RST_Pos (2UL) /*!< SPI0RST (Bit 2) */
+#define RCU_APB1RSTR_SPI0RST_Msk (0x4UL) /*!< SPI0RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_UART4RST_Pos (1UL) /*!< UART4RST (Bit 1) */
+#define RCU_APB1RSTR_UART4RST_Msk (0x2UL) /*!< UART4RST (Bitfield-Mask: 0x01) */
+#define RCU_APB1RSTR_UART3RST_Pos (0UL) /*!< UART3RST (Bit 0) */
+#define RCU_APB1RSTR_UART3RST_Msk (0x1UL) /*!< UART3RST (Bitfield-Mask: 0x01) */
+/* ======================================================= AHB0RSTR ======================================================== */
+#define RCU_AHB0RSTR_QEI2RST_Pos (12UL) /*!< QEI2RST (Bit 12) */
+#define RCU_AHB0RSTR_QEI2RST_Msk (0x1000UL) /*!< QEI2RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_QEI1RST_Pos (11UL) /*!< QEI1RST (Bit 11) */
+#define RCU_AHB0RSTR_QEI1RST_Msk (0x800UL) /*!< QEI1RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_QEI0RST_Pos (10UL) /*!< QEI0RST (Bit 10) */
+#define RCU_AHB0RSTR_QEI0RST_Msk (0x400UL) /*!< QEI0RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_TMR4RST_Pos (9UL) /*!< TMR4RST (Bit 9) */
+#define RCU_AHB0RSTR_TMR4RST_Msk (0x200UL) /*!< TMR4RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_TMR3RST_Pos (8UL) /*!< TMR3RST (Bit 8) */
+#define RCU_AHB0RSTR_TMR3RST_Msk (0x100UL) /*!< TMR3RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PFRST_Pos (7UL) /*!< PFRST (Bit 7) */
+#define RCU_AHB0RSTR_PFRST_Msk (0x80UL) /*!< PFRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PERST_Pos (6UL) /*!< PERST (Bit 6) */
+#define RCU_AHB0RSTR_PERST_Msk (0x40UL) /*!< PERST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PDRST_Pos (5UL) /*!< PDRST (Bit 5) */
+#define RCU_AHB0RSTR_PDRST_Msk (0x20UL) /*!< PDRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PCRST_Pos (4UL) /*!< PCRST (Bit 4) */
+#define RCU_AHB0RSTR_PCRST_Msk (0x10UL) /*!< PCRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PBRST_Pos (3UL) /*!< PBRST (Bit 3) */
+#define RCU_AHB0RSTR_PBRST_Msk (0x8UL) /*!< PBRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_PARST_Pos (2UL) /*!< PARST (Bit 2) */
+#define RCU_AHB0RSTR_PARST_Msk (0x4UL) /*!< PARST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_FLSRST_Pos (1UL) /*!< FLSRST (Bit 1) */
+#define RCU_AHB0RSTR_FLSRST_Msk (0x2UL) /*!< FLSRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB0RSTR_DMARST_Pos (0UL) /*!< DMARST (Bit 0) */
+#define RCU_AHB0RSTR_DMARST_Msk (0x1UL) /*!< DMARST (Bitfield-Mask: 0x01) */
+/* ======================================================= AHB1RSTR ======================================================== */
+#define RCU_AHB1RSTR_CORDICRST_Pos (13UL) /*!< CORDICRST (Bit 13) */
+#define RCU_AHB1RSTR_CORDICRST_Msk (0x2000UL) /*!< CORDICRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR5RST_Pos (12UL) /*!< IIR5RST (Bit 12) */
+#define RCU_AHB1RSTR_IIR5RST_Msk (0x1000UL) /*!< IIR5RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR4RST_Pos (11UL) /*!< IIR4RST (Bit 11) */
+#define RCU_AHB1RSTR_IIR4RST_Msk (0x800UL) /*!< IIR4RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR3RST_Pos (10UL) /*!< IIR3RST (Bit 10) */
+#define RCU_AHB1RSTR_IIR3RST_Msk (0x400UL) /*!< IIR3RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR2RST_Pos (9UL) /*!< IIR2RST (Bit 9) */
+#define RCU_AHB1RSTR_IIR2RST_Msk (0x200UL) /*!< IIR2RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR1RST_Pos (8UL) /*!< IIR1RST (Bit 8) */
+#define RCU_AHB1RSTR_IIR1RST_Msk (0x100UL) /*!< IIR1RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_IIR0RST_Pos (7UL) /*!< IIR0RST (Bit 7) */
+#define RCU_AHB1RSTR_IIR0RST_Msk (0x80UL) /*!< IIR0RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_PWMRST_Pos (6UL) /*!< PWMRST (Bit 6) */
+#define RCU_AHB1RSTR_PWMRST_Msk (0x40UL) /*!< PWMRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_CMPRST_Pos (5UL) /*!< CMPRST (Bit 5) */
+#define RCU_AHB1RSTR_CMPRST_Msk (0x20UL) /*!< CMPRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_DACRST_Pos (4UL) /*!< DACRST (Bit 4) */
+#define RCU_AHB1RSTR_DACRST_Msk (0x10UL) /*!< DACRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_ADCRST_Pos (3UL) /*!< ADCRST (Bit 3) */
+#define RCU_AHB1RSTR_ADCRST_Msk (0x8UL) /*!< ADCRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_USBRST_Pos (2UL) /*!< USBRST (Bit 2) */
+#define RCU_AHB1RSTR_USBRST_Msk (0x4UL) /*!< USBRST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_TMR10RST_Pos (1UL) /*!< TMR10RST (Bit 1) */
+#define RCU_AHB1RSTR_TMR10RST_Msk (0x2UL) /*!< TMR10RST (Bitfield-Mask: 0x01) */
+#define RCU_AHB1RSTR_TMR9RST_Pos (0UL) /*!< TMR9RST (Bit 0) */
+#define RCU_AHB1RSTR_TMR9RST_Msk (0x1UL) /*!< TMR9RST (Bitfield-Mask: 0x01) */
+/* ======================================================== XOSCCR ========================================================= */
+#define RCU_XOSCCR_HEN_Pos (4UL) /*!< HEN (Bit 4) */
+#define RCU_XOSCCR_HEN_Msk (0x10UL) /*!< HEN (Bitfield-Mask: 0x01) */
+#define RCU_XOSCCR_XDR_Pos (1UL) /*!< XDR (Bit 1) */
+#define RCU_XOSCCR_XDR_Msk (0xeUL) /*!< XDR (Bitfield-Mask: 0x07) */
+#define RCU_XOSCCR_XEN_Pos (0UL) /*!< XEN (Bit 0) */
+#define RCU_XOSCCR_XEN_Msk (0x1UL) /*!< XEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CSSCR ========================================================= */
+#define RCU_CSSCR_LMT_Pos (6UL) /*!< LMT (Bit 6) */
+#define RCU_CSSCR_LMT_Msk (0xc0UL) /*!< LMT (Bitfield-Mask: 0x03) */
+#define RCU_CSSCR_WIN_Pos (4UL) /*!< WIN (Bit 4) */
+#define RCU_CSSCR_WIN_Msk (0x30UL) /*!< WIN (Bitfield-Mask: 0x03) */
+#define RCU_CSSCR_LPD_Pos (3UL) /*!< LPD (Bit 3) */
+#define RCU_CSSCR_LPD_Msk (0x8UL) /*!< LPD (Bitfield-Mask: 0x01) */
+#define RCU_CSSCR_LPE_Pos (2UL) /*!< LPE (Bit 2) */
+#define RCU_CSSCR_LPE_Msk (0x4UL) /*!< LPE (Bitfield-Mask: 0x01) */
+#define RCU_CSSCR_SSE_Pos (1UL) /*!< SSE (Bit 1) */
+#define RCU_CSSCR_SSE_Msk (0x2UL) /*!< SSE (Bitfield-Mask: 0x01) */
+#define RCU_CSSCR_SWE_Pos (0UL) /*!< SWE (Bit 0) */
+#define RCU_CSSCR_SWE_Msk (0x1UL) /*!< SWE (Bitfield-Mask: 0x01) */
+/* ========================================================= DBGCR ========================================================= */
+#define RCU_DBGCR_ECIE_Pos (5UL) /*!< ECIE (Bit 5) */
+#define RCU_DBGCR_ECIE_Msk (0x20UL) /*!< ECIE (Bitfield-Mask: 0x01) */
+#define RCU_DBGCR_MCOEN_Pos (4UL) /*!< MCOEN (Bit 4) */
+#define RCU_DBGCR_MCOEN_Msk (0x10UL) /*!< MCOEN (Bitfield-Mask: 0x01) */
+#define RCU_DBGCR_MCO_Pos (0UL) /*!< MCO (Bit 0) */
+#define RCU_DBGCR_MCO_Msk (0x7UL) /*!< MCO (Bitfield-Mask: 0x07) */
+/* ======================================================== SRSTSR ========================================================= */
+#define RCU_SRSTSR_IWRSTE_Pos (11UL) /*!< IWRSTE (Bit 11) */
+#define RCU_SRSTSR_IWRSTE_Msk (0x800UL) /*!< IWRSTE (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_WWRSTE_Pos (10UL) /*!< WWRSTE (Bit 10) */
+#define RCU_SRSTSR_WWRSTE_Msk (0x400UL) /*!< WWRSTE (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_LKRSTE_Pos (9UL) /*!< LKRSTE (Bit 9) */
+#define RCU_SRSTSR_LKRSTE_Msk (0x200UL) /*!< LKRSTE (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_SQRSTE_Pos (8UL) /*!< SQRSTE (Bit 8) */
+#define RCU_SRSTSR_SQRSTE_Msk (0x100UL) /*!< SQRSTE (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_WWR_Pos (5UL) /*!< WWR (Bit 5) */
+#define RCU_SRSTSR_WWR_Msk (0x20UL) /*!< WWR (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_IWR_Pos (4UL) /*!< IWR (Bit 4) */
+#define RCU_SRSTSR_IWR_Msk (0x10UL) /*!< IWR (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_LKR_Pos (3UL) /*!< LKR (Bit 3) */
+#define RCU_SRSTSR_LKR_Msk (0x8UL) /*!< LKR (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_SQR_Pos (2UL) /*!< SQR (Bit 2) */
+#define RCU_SRSTSR_SQR_Msk (0x4UL) /*!< SQR (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_LPR_Pos (1UL) /*!< LPR (Bit 1) */
+#define RCU_SRSTSR_LPR_Msk (0x2UL) /*!< LPR (Bitfield-Mask: 0x01) */
+#define RCU_SRSTSR_MCR_Pos (0UL) /*!< MCR (Bit 0) */
+#define RCU_SRSTSR_MCR_Msk (0x1UL) /*!< MCR (Bitfield-Mask: 0x01) */
+/* ========================================================= KEYR ========================================================== */
+#define RCU_KEYR_KEY_Pos (0UL) /*!< KEY (Bit 0) */
+#define RCU_KEYR_KEY_Msk (0x1UL) /*!< KEY (Bitfield-Mask: 0x01) */
+/* ========================================================= SRSR ========================================================== */
+#define RCU_SRSR_WWR_Pos (5UL) /*!< WWR (Bit 5) */
+#define RCU_SRSR_WWR_Msk (0x20UL) /*!< WWR (Bitfield-Mask: 0x01) */
+#define RCU_SRSR_IWR_Pos (4UL) /*!< IWR (Bit 4) */
+#define RCU_SRSR_IWR_Msk (0x10UL) /*!< IWR (Bitfield-Mask: 0x01) */
+#define RCU_SRSR_LKR_Pos (3UL) /*!< LKR (Bit 3) */
+#define RCU_SRSR_LKR_Msk (0x8UL) /*!< LKR (Bitfield-Mask: 0x01) */
+#define RCU_SRSR_SQR_Pos (2UL) /*!< SQR (Bit 2) */
+#define RCU_SRSR_SQR_Msk (0x4UL) /*!< SQR (Bitfield-Mask: 0x01) */
+#define RCU_SRSR_LPR_Pos (1UL) /*!< LPR (Bit 1) */
+#define RCU_SRSR_LPR_Msk (0x2UL) /*!< LPR (Bitfield-Mask: 0x01) */
+#define RCU_SRSR_MCR_Pos (0UL) /*!< MCR (Bit 0) */
+#define RCU_SRSR_MCR_Msk (0x1UL) /*!< MCR (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ QEI0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== POSCNT ========================================================= */
+#define QEI0_POSCNT_POSCNT_Pos (0UL) /*!< POSCNT (Bit 0) */
+#define QEI0_POSCNT_POSCNT_Msk (0xffffffffUL) /*!< POSCNT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSINIT ======================================================== */
+#define QEI0_POSINIT_POSINIT_Pos (0UL) /*!< POSINIT (Bit 0) */
+#define QEI0_POSINIT_POSINIT_Msk (0xffffffffUL) /*!< POSINIT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSMAX ========================================================= */
+#define QEI0_POSMAX_POSMAX_Pos (0UL) /*!< POSMAX (Bit 0) */
+#define QEI0_POSMAX_POSMAX_Msk (0xffffffffUL) /*!< POSMAX (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSCMP ========================================================= */
+#define QEI0_POSCMP_POSCMP_Pos (0UL) /*!< POSCMP (Bit 0) */
+#define QEI0_POSCMP_POSCMP_Msk (0xffffffffUL) /*!< POSCMP (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSILAT ======================================================== */
+#define QEI0_POSILAT_POSILAT_Pos (0UL) /*!< POSILAT (Bit 0) */
+#define QEI0_POSILAT_POSILAT_Msk (0xffffffffUL) /*!< POSILAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSLAT ========================================================= */
+#define QEI0_POSLAT_POSLAT_Pos (0UL) /*!< POSLAT (Bit 0) */
+#define QEI0_POSLAT_POSLAT_Msk (0xffffffffUL) /*!< POSLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UTMR ========================================================== */
+#define QEI0_UTMR_UTMR_Pos (0UL) /*!< UTMR (Bit 0) */
+#define QEI0_UTMR_UTMR_Msk (0xffffffffUL) /*!< UTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UPRD ========================================================== */
+#define QEI0_UPRD_UPRD_Pos (0UL) /*!< UPRD (Bit 0) */
+#define QEI0_UPRD_UPRD_Msk (0xffffffffUL) /*!< UPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== DECCTL ========================================================= */
+#define QEI0_DECCTL_DBC_Pos (16UL) /*!< DBC (Bit 16) */
+#define QEI0_DECCTL_DBC_Msk (0xff0000UL) /*!< DBC (Bitfield-Mask: 0xff) */
+#define QEI0_DECCTL_DCM_Pos (14UL) /*!< DCM (Bit 14) */
+#define QEI0_DECCTL_DCM_Msk (0x4000UL) /*!< DCM (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_QSRC_Pos (12UL) /*!< QSRC (Bit 12) */
+#define QEI0_DECCTL_QSRC_Msk (0x3000UL) /*!< QSRC (Bitfield-Mask: 0x03) */
+#define QEI0_DECCTL_XCR_Pos (6UL) /*!< XCR (Bit 6) */
+#define QEI0_DECCTL_XCR_Msk (0x40UL) /*!< XCR (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_IGATE_Pos (5UL) /*!< IGATE (Bit 5) */
+#define QEI0_DECCTL_IGATE_Msk (0x20UL) /*!< IGATE (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_SWAP_Pos (4UL) /*!< SWAP (Bit 4) */
+#define QEI0_DECCTL_SWAP_Msk (0x10UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_QBP_Pos (3UL) /*!< QBP (Bit 3) */
+#define QEI0_DECCTL_QBP_Msk (0x8UL) /*!< QBP (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_QAP_Pos (2UL) /*!< QAP (Bit 2) */
+#define QEI0_DECCTL_QAP_Msk (0x4UL) /*!< QAP (Bitfield-Mask: 0x01) */
+#define QEI0_DECCTL_QIP_Pos (0UL) /*!< QIP (Bit 0) */
+#define QEI0_DECCTL_QIP_Msk (0x1UL) /*!< QIP (Bitfield-Mask: 0x01) */
+/* ======================================================== QEPCTL ========================================================= */
+#define QEI0_QEPCTL_PCRM_Pos (12UL) /*!< PCRM (Bit 12) */
+#define QEI0_QEPCTL_PCRM_Msk (0x3000UL) /*!< PCRM (Bitfield-Mask: 0x03) */
+#define QEI0_QEPCTL_SWI_Pos (8UL) /*!< SWI (Bit 8) */
+#define QEI0_QEPCTL_SWI_Msk (0x100UL) /*!< SWI (Bitfield-Mask: 0x01) */
+#define QEI0_QEPCTL_IEI_Pos (6UL) /*!< IEI (Bit 6) */
+#define QEI0_QEPCTL_IEI_Msk (0xc0UL) /*!< IEI (Bitfield-Mask: 0x03) */
+#define QEI0_QEPCTL_IEL_Pos (4UL) /*!< IEL (Bit 4) */
+#define QEI0_QEPCTL_IEL_Msk (0x30UL) /*!< IEL (Bitfield-Mask: 0x03) */
+#define QEI0_QEPCTL_UTE_Pos (1UL) /*!< UTE (Bit 1) */
+#define QEI0_QEPCTL_UTE_Msk (0x2UL) /*!< UTE (Bitfield-Mask: 0x01) */
+#define QEI0_QEPCTL_QPE_Pos (0UL) /*!< QPE (Bit 0) */
+#define QEI0_QEPCTL_QPE_Msk (0x1UL) /*!< QPE (Bitfield-Mask: 0x01) */
+/* ======================================================== POSCTL ========================================================= */
+#define QEI0_POSCTL_PSE_Pos (1UL) /*!< PSE (Bit 1) */
+#define QEI0_POSCTL_PSE_Msk (0x2UL) /*!< PSE (Bitfield-Mask: 0x01) */
+#define QEI0_POSCTL_CCE_Pos (0UL) /*!< CCE (Bit 0) */
+#define QEI0_POSCTL_CCE_Msk (0x1UL) /*!< CCE (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPCTL ========================================================= */
+#define QEI0_CAPCTL_UPPS_Pos (8UL) /*!< UPPS (Bit 8) */
+#define QEI0_CAPCTL_UPPS_Msk (0xf00UL) /*!< UPPS (Bitfield-Mask: 0x0f) */
+#define QEI0_CAPCTL_CCPS_Pos (4UL) /*!< CCPS (Bit 4) */
+#define QEI0_CAPCTL_CCPS_Msk (0x70UL) /*!< CCPS (Bitfield-Mask: 0x07) */
+#define QEI0_CAPCTL_CMD_Pos (1UL) /*!< CMD (Bit 1) */
+#define QEI0_CAPCTL_CMD_Msk (0x2UL) /*!< CMD (Bitfield-Mask: 0x01) */
+#define QEI0_CAPCTL_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define QEI0_CAPCTL_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= QCTMR ========================================================= */
+#define QEI0_QCTMR_CTMR_Pos (0UL) /*!< CTMR (Bit 0) */
+#define QEI0_QCTMR_CTMR_Msk (0xffffffffUL) /*!< CTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= QCPRD ========================================================= */
+#define QEI0_QCPRD_CPRD_Pos (0UL) /*!< CPRD (Bit 0) */
+#define QEI0_QCPRD_CPRD_Msk (0xffffffffUL) /*!< CPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CTMRLAT ======================================================== */
+#define QEI0_CTMRLAT_CTMRLAT_Pos (0UL) /*!< CTMRLAT (Bit 0) */
+#define QEI0_CTMRLAT_CTMRLAT_Msk (0xffffffffUL) /*!< CTMRLAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CPRDLAT ======================================================== */
+#define QEI0_CPRDLAT_CPRDLAT_Pos (0UL) /*!< CPRDLAT (Bit 0) */
+#define QEI0_CPRDLAT_CPRDLAT_Msk (0xffffffffUL) /*!< CPRDLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= IENR ========================================================== */
+#define QEI0_IENR_CDE_Pos (10UL) /*!< CDE (Bit 10) */
+#define QEI0_IENR_CDE_Msk (0x400UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PRE_Pos (9UL) /*!< PRE (Bit 9) */
+#define QEI0_IENR_PRE_Msk (0x200UL) /*!< PRE (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PIE_Pos (8UL) /*!< PIE (Bit 8) */
+#define QEI0_IENR_PIE_Msk (0x100UL) /*!< PIE (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI0_IENR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI0_IENR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI0_IENR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI0_IENR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI0_IENR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI0_IENR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_QPE_Pos (1UL) /*!< QPE (Bit 1) */
+#define QEI0_IENR_QPE_Msk (0x2UL) /*!< QPE (Bitfield-Mask: 0x01) */
+#define QEI0_IENR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI0_IENR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+/* ========================================================= STSR ========================================================== */
+#define QEI0_STSR_QDF_Pos (16UL) /*!< QDF (Bit 16) */
+#define QEI0_STSR_QDF_Msk (0x10000UL) /*!< QDF (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_QDI_Pos (15UL) /*!< QDI (Bit 15) */
+#define QEI0_STSR_QDI_Msk (0x8000UL) /*!< QDI (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_QDS_Pos (14UL) /*!< QDS (Bit 14) */
+#define QEI0_STSR_QDS_Msk (0x4000UL) /*!< QDS (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_COE_Pos (13UL) /*!< COE (Bit 13) */
+#define QEI0_STSR_COE_Msk (0x2000UL) /*!< COE (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_CDE_Pos (12UL) /*!< CDE (Bit 12) */
+#define QEI0_STSR_CDE_Msk (0x1000UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_FIS_Pos (11UL) /*!< FIS (Bit 11) */
+#define QEI0_STSR_FIS_Msk (0x800UL) /*!< FIS (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_CDS_Pos (10UL) /*!< CDS (Bit 10) */
+#define QEI0_STSR_CDS_Msk (0x400UL) /*!< CDS (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PRS_Pos (9UL) /*!< PRS (Bit 9) */
+#define QEI0_STSR_PRS_Msk (0x200UL) /*!< PRS (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PIS_Pos (8UL) /*!< PIS (Bit 8) */
+#define QEI0_STSR_PIS_Msk (0x100UL) /*!< PIS (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI0_STSR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI0_STSR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI0_STSR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI0_STSR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI0_STSR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI0_STSR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PHE_Pos (1UL) /*!< PHE (Bit 1) */
+#define QEI0_STSR_PHE_Msk (0x2UL) /*!< PHE (Bitfield-Mask: 0x01) */
+#define QEI0_STSR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI0_STSR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ QEI1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== POSCNT ========================================================= */
+#define QEI1_POSCNT_POSCNT_Pos (0UL) /*!< POSCNT (Bit 0) */
+#define QEI1_POSCNT_POSCNT_Msk (0xffffffffUL) /*!< POSCNT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSINIT ======================================================== */
+#define QEI1_POSINIT_POSINIT_Pos (0UL) /*!< POSINIT (Bit 0) */
+#define QEI1_POSINIT_POSINIT_Msk (0xffffffffUL) /*!< POSINIT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSMAX ========================================================= */
+#define QEI1_POSMAX_POSMAX_Pos (0UL) /*!< POSMAX (Bit 0) */
+#define QEI1_POSMAX_POSMAX_Msk (0xffffffffUL) /*!< POSMAX (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSCMP ========================================================= */
+#define QEI1_POSCMP_POSCMP_Pos (0UL) /*!< POSCMP (Bit 0) */
+#define QEI1_POSCMP_POSCMP_Msk (0xffffffffUL) /*!< POSCMP (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSILAT ======================================================== */
+#define QEI1_POSILAT_POSILAT_Pos (0UL) /*!< POSILAT (Bit 0) */
+#define QEI1_POSILAT_POSILAT_Msk (0xffffffffUL) /*!< POSILAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSLAT ========================================================= */
+#define QEI1_POSLAT_POSLAT_Pos (0UL) /*!< POSLAT (Bit 0) */
+#define QEI1_POSLAT_POSLAT_Msk (0xffffffffUL) /*!< POSLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UTMR ========================================================== */
+#define QEI1_UTMR_UTMR_Pos (0UL) /*!< UTMR (Bit 0) */
+#define QEI1_UTMR_UTMR_Msk (0xffffffffUL) /*!< UTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UPRD ========================================================== */
+#define QEI1_UPRD_UPRD_Pos (0UL) /*!< UPRD (Bit 0) */
+#define QEI1_UPRD_UPRD_Msk (0xffffffffUL) /*!< UPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== DECCTL ========================================================= */
+#define QEI1_DECCTL_DBC_Pos (16UL) /*!< DBC (Bit 16) */
+#define QEI1_DECCTL_DBC_Msk (0xff0000UL) /*!< DBC (Bitfield-Mask: 0xff) */
+#define QEI1_DECCTL_DCM_Pos (14UL) /*!< DCM (Bit 14) */
+#define QEI1_DECCTL_DCM_Msk (0x4000UL) /*!< DCM (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_QSRC_Pos (12UL) /*!< QSRC (Bit 12) */
+#define QEI1_DECCTL_QSRC_Msk (0x3000UL) /*!< QSRC (Bitfield-Mask: 0x03) */
+#define QEI1_DECCTL_XCR_Pos (6UL) /*!< XCR (Bit 6) */
+#define QEI1_DECCTL_XCR_Msk (0x40UL) /*!< XCR (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_IGATE_Pos (5UL) /*!< IGATE (Bit 5) */
+#define QEI1_DECCTL_IGATE_Msk (0x20UL) /*!< IGATE (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_SWAP_Pos (4UL) /*!< SWAP (Bit 4) */
+#define QEI1_DECCTL_SWAP_Msk (0x10UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_QBP_Pos (3UL) /*!< QBP (Bit 3) */
+#define QEI1_DECCTL_QBP_Msk (0x8UL) /*!< QBP (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_QAP_Pos (2UL) /*!< QAP (Bit 2) */
+#define QEI1_DECCTL_QAP_Msk (0x4UL) /*!< QAP (Bitfield-Mask: 0x01) */
+#define QEI1_DECCTL_QIP_Pos (0UL) /*!< QIP (Bit 0) */
+#define QEI1_DECCTL_QIP_Msk (0x1UL) /*!< QIP (Bitfield-Mask: 0x01) */
+/* ======================================================== QEPCTL ========================================================= */
+#define QEI1_QEPCTL_PCRM_Pos (12UL) /*!< PCRM (Bit 12) */
+#define QEI1_QEPCTL_PCRM_Msk (0x3000UL) /*!< PCRM (Bitfield-Mask: 0x03) */
+#define QEI1_QEPCTL_SWI_Pos (8UL) /*!< SWI (Bit 8) */
+#define QEI1_QEPCTL_SWI_Msk (0x100UL) /*!< SWI (Bitfield-Mask: 0x01) */
+#define QEI1_QEPCTL_IEI_Pos (6UL) /*!< IEI (Bit 6) */
+#define QEI1_QEPCTL_IEI_Msk (0xc0UL) /*!< IEI (Bitfield-Mask: 0x03) */
+#define QEI1_QEPCTL_IEL_Pos (4UL) /*!< IEL (Bit 4) */
+#define QEI1_QEPCTL_IEL_Msk (0x30UL) /*!< IEL (Bitfield-Mask: 0x03) */
+#define QEI1_QEPCTL_UTE_Pos (1UL) /*!< UTE (Bit 1) */
+#define QEI1_QEPCTL_UTE_Msk (0x2UL) /*!< UTE (Bitfield-Mask: 0x01) */
+#define QEI1_QEPCTL_QPE_Pos (0UL) /*!< QPE (Bit 0) */
+#define QEI1_QEPCTL_QPE_Msk (0x1UL) /*!< QPE (Bitfield-Mask: 0x01) */
+/* ======================================================== POSCTL ========================================================= */
+#define QEI1_POSCTL_PSE_Pos (1UL) /*!< PSE (Bit 1) */
+#define QEI1_POSCTL_PSE_Msk (0x2UL) /*!< PSE (Bitfield-Mask: 0x01) */
+#define QEI1_POSCTL_CCE_Pos (0UL) /*!< CCE (Bit 0) */
+#define QEI1_POSCTL_CCE_Msk (0x1UL) /*!< CCE (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPCTL ========================================================= */
+#define QEI1_CAPCTL_UPPS_Pos (8UL) /*!< UPPS (Bit 8) */
+#define QEI1_CAPCTL_UPPS_Msk (0xf00UL) /*!< UPPS (Bitfield-Mask: 0x0f) */
+#define QEI1_CAPCTL_CCPS_Pos (4UL) /*!< CCPS (Bit 4) */
+#define QEI1_CAPCTL_CCPS_Msk (0x70UL) /*!< CCPS (Bitfield-Mask: 0x07) */
+#define QEI1_CAPCTL_CMD_Pos (1UL) /*!< CMD (Bit 1) */
+#define QEI1_CAPCTL_CMD_Msk (0x2UL) /*!< CMD (Bitfield-Mask: 0x01) */
+#define QEI1_CAPCTL_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define QEI1_CAPCTL_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= QCTMR ========================================================= */
+#define QEI1_QCTMR_CTMR_Pos (0UL) /*!< CTMR (Bit 0) */
+#define QEI1_QCTMR_CTMR_Msk (0xffffffffUL) /*!< CTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= QCPRD ========================================================= */
+#define QEI1_QCPRD_CPRD_Pos (0UL) /*!< CPRD (Bit 0) */
+#define QEI1_QCPRD_CPRD_Msk (0xffffffffUL) /*!< CPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CTMRLAT ======================================================== */
+#define QEI1_CTMRLAT_CTMRLAT_Pos (0UL) /*!< CTMRLAT (Bit 0) */
+#define QEI1_CTMRLAT_CTMRLAT_Msk (0xffffffffUL) /*!< CTMRLAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CPRDLAT ======================================================== */
+#define QEI1_CPRDLAT_CPRDLAT_Pos (0UL) /*!< CPRDLAT (Bit 0) */
+#define QEI1_CPRDLAT_CPRDLAT_Msk (0xffffffffUL) /*!< CPRDLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= IENR ========================================================== */
+#define QEI1_IENR_CDE_Pos (10UL) /*!< CDE (Bit 10) */
+#define QEI1_IENR_CDE_Msk (0x400UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PRE_Pos (9UL) /*!< PRE (Bit 9) */
+#define QEI1_IENR_PRE_Msk (0x200UL) /*!< PRE (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PIE_Pos (8UL) /*!< PIE (Bit 8) */
+#define QEI1_IENR_PIE_Msk (0x100UL) /*!< PIE (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI1_IENR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI1_IENR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI1_IENR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI1_IENR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI1_IENR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI1_IENR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_QPE_Pos (1UL) /*!< QPE (Bit 1) */
+#define QEI1_IENR_QPE_Msk (0x2UL) /*!< QPE (Bitfield-Mask: 0x01) */
+#define QEI1_IENR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI1_IENR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+/* ========================================================= STSR ========================================================== */
+#define QEI1_STSR_QDF_Pos (16UL) /*!< QDF (Bit 16) */
+#define QEI1_STSR_QDF_Msk (0x10000UL) /*!< QDF (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_QDI_Pos (15UL) /*!< QDI (Bit 15) */
+#define QEI1_STSR_QDI_Msk (0x8000UL) /*!< QDI (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_QDS_Pos (14UL) /*!< QDS (Bit 14) */
+#define QEI1_STSR_QDS_Msk (0x4000UL) /*!< QDS (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_COE_Pos (13UL) /*!< COE (Bit 13) */
+#define QEI1_STSR_COE_Msk (0x2000UL) /*!< COE (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_CDE_Pos (12UL) /*!< CDE (Bit 12) */
+#define QEI1_STSR_CDE_Msk (0x1000UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_FIS_Pos (11UL) /*!< FIS (Bit 11) */
+#define QEI1_STSR_FIS_Msk (0x800UL) /*!< FIS (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_CDS_Pos (10UL) /*!< CDS (Bit 10) */
+#define QEI1_STSR_CDS_Msk (0x400UL) /*!< CDS (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PRS_Pos (9UL) /*!< PRS (Bit 9) */
+#define QEI1_STSR_PRS_Msk (0x200UL) /*!< PRS (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PIS_Pos (8UL) /*!< PIS (Bit 8) */
+#define QEI1_STSR_PIS_Msk (0x100UL) /*!< PIS (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI1_STSR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI1_STSR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI1_STSR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI1_STSR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI1_STSR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI1_STSR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PHE_Pos (1UL) /*!< PHE (Bit 1) */
+#define QEI1_STSR_PHE_Msk (0x2UL) /*!< PHE (Bitfield-Mask: 0x01) */
+#define QEI1_STSR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI1_STSR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ QEI2 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== POSCNT ========================================================= */
+#define QEI2_POSCNT_POSCNT_Pos (0UL) /*!< POSCNT (Bit 0) */
+#define QEI2_POSCNT_POSCNT_Msk (0xffffffffUL) /*!< POSCNT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSINIT ======================================================== */
+#define QEI2_POSINIT_POSINIT_Pos (0UL) /*!< POSINIT (Bit 0) */
+#define QEI2_POSINIT_POSINIT_Msk (0xffffffffUL) /*!< POSINIT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSMAX ========================================================= */
+#define QEI2_POSMAX_POSMAX_Pos (0UL) /*!< POSMAX (Bit 0) */
+#define QEI2_POSMAX_POSMAX_Msk (0xffffffffUL) /*!< POSMAX (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSCMP ========================================================= */
+#define QEI2_POSCMP_POSCMP_Pos (0UL) /*!< POSCMP (Bit 0) */
+#define QEI2_POSCMP_POSCMP_Msk (0xffffffffUL) /*!< POSCMP (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSILAT ======================================================== */
+#define QEI2_POSILAT_POSILAT_Pos (0UL) /*!< POSILAT (Bit 0) */
+#define QEI2_POSILAT_POSILAT_Msk (0xffffffffUL) /*!< POSILAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== POSLAT ========================================================= */
+#define QEI2_POSLAT_POSLAT_Pos (0UL) /*!< POSLAT (Bit 0) */
+#define QEI2_POSLAT_POSLAT_Msk (0xffffffffUL) /*!< POSLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UTMR ========================================================== */
+#define QEI2_UTMR_UTMR_Pos (0UL) /*!< UTMR (Bit 0) */
+#define QEI2_UTMR_UTMR_Msk (0xffffffffUL) /*!< UTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= UPRD ========================================================== */
+#define QEI2_UPRD_UPRD_Pos (0UL) /*!< UPRD (Bit 0) */
+#define QEI2_UPRD_UPRD_Msk (0xffffffffUL) /*!< UPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== DECCTL ========================================================= */
+#define QEI2_DECCTL_DBC_Pos (16UL) /*!< DBC (Bit 16) */
+#define QEI2_DECCTL_DBC_Msk (0xff0000UL) /*!< DBC (Bitfield-Mask: 0xff) */
+#define QEI2_DECCTL_DCM_Pos (14UL) /*!< DCM (Bit 14) */
+#define QEI2_DECCTL_DCM_Msk (0x4000UL) /*!< DCM (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_QSRC_Pos (12UL) /*!< QSRC (Bit 12) */
+#define QEI2_DECCTL_QSRC_Msk (0x3000UL) /*!< QSRC (Bitfield-Mask: 0x03) */
+#define QEI2_DECCTL_XCR_Pos (6UL) /*!< XCR (Bit 6) */
+#define QEI2_DECCTL_XCR_Msk (0x40UL) /*!< XCR (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_IGATE_Pos (5UL) /*!< IGATE (Bit 5) */
+#define QEI2_DECCTL_IGATE_Msk (0x20UL) /*!< IGATE (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_SWAP_Pos (4UL) /*!< SWAP (Bit 4) */
+#define QEI2_DECCTL_SWAP_Msk (0x10UL) /*!< SWAP (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_QBP_Pos (3UL) /*!< QBP (Bit 3) */
+#define QEI2_DECCTL_QBP_Msk (0x8UL) /*!< QBP (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_QAP_Pos (2UL) /*!< QAP (Bit 2) */
+#define QEI2_DECCTL_QAP_Msk (0x4UL) /*!< QAP (Bitfield-Mask: 0x01) */
+#define QEI2_DECCTL_QIP_Pos (0UL) /*!< QIP (Bit 0) */
+#define QEI2_DECCTL_QIP_Msk (0x1UL) /*!< QIP (Bitfield-Mask: 0x01) */
+/* ======================================================== QEPCTL ========================================================= */
+#define QEI2_QEPCTL_PCRM_Pos (12UL) /*!< PCRM (Bit 12) */
+#define QEI2_QEPCTL_PCRM_Msk (0x3000UL) /*!< PCRM (Bitfield-Mask: 0x03) */
+#define QEI2_QEPCTL_SWI_Pos (8UL) /*!< SWI (Bit 8) */
+#define QEI2_QEPCTL_SWI_Msk (0x100UL) /*!< SWI (Bitfield-Mask: 0x01) */
+#define QEI2_QEPCTL_IEI_Pos (6UL) /*!< IEI (Bit 6) */
+#define QEI2_QEPCTL_IEI_Msk (0xc0UL) /*!< IEI (Bitfield-Mask: 0x03) */
+#define QEI2_QEPCTL_IEL_Pos (4UL) /*!< IEL (Bit 4) */
+#define QEI2_QEPCTL_IEL_Msk (0x30UL) /*!< IEL (Bitfield-Mask: 0x03) */
+#define QEI2_QEPCTL_UTE_Pos (1UL) /*!< UTE (Bit 1) */
+#define QEI2_QEPCTL_UTE_Msk (0x2UL) /*!< UTE (Bitfield-Mask: 0x01) */
+#define QEI2_QEPCTL_QPE_Pos (0UL) /*!< QPE (Bit 0) */
+#define QEI2_QEPCTL_QPE_Msk (0x1UL) /*!< QPE (Bitfield-Mask: 0x01) */
+/* ======================================================== POSCTL ========================================================= */
+#define QEI2_POSCTL_PSE_Pos (1UL) /*!< PSE (Bit 1) */
+#define QEI2_POSCTL_PSE_Msk (0x2UL) /*!< PSE (Bitfield-Mask: 0x01) */
+#define QEI2_POSCTL_CCE_Pos (0UL) /*!< CCE (Bit 0) */
+#define QEI2_POSCTL_CCE_Msk (0x1UL) /*!< CCE (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPCTL ========================================================= */
+#define QEI2_CAPCTL_UPPS_Pos (8UL) /*!< UPPS (Bit 8) */
+#define QEI2_CAPCTL_UPPS_Msk (0xf00UL) /*!< UPPS (Bitfield-Mask: 0x0f) */
+#define QEI2_CAPCTL_CCPS_Pos (4UL) /*!< CCPS (Bit 4) */
+#define QEI2_CAPCTL_CCPS_Msk (0x70UL) /*!< CCPS (Bitfield-Mask: 0x07) */
+#define QEI2_CAPCTL_CMD_Pos (1UL) /*!< CMD (Bit 1) */
+#define QEI2_CAPCTL_CMD_Msk (0x2UL) /*!< CMD (Bitfield-Mask: 0x01) */
+#define QEI2_CAPCTL_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define QEI2_CAPCTL_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= QCTMR ========================================================= */
+#define QEI2_QCTMR_CTMR_Pos (0UL) /*!< CTMR (Bit 0) */
+#define QEI2_QCTMR_CTMR_Msk (0xffffffffUL) /*!< CTMR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= QCPRD ========================================================= */
+#define QEI2_QCPRD_CPRD_Pos (0UL) /*!< CPRD (Bit 0) */
+#define QEI2_QCPRD_CPRD_Msk (0xffffffffUL) /*!< CPRD (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CTMRLAT ======================================================== */
+#define QEI2_CTMRLAT_CTMRLAT_Pos (0UL) /*!< CTMRLAT (Bit 0) */
+#define QEI2_CTMRLAT_CTMRLAT_Msk (0xffffffffUL) /*!< CTMRLAT (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== CPRDLAT ======================================================== */
+#define QEI2_CPRDLAT_CPRDLAT_Pos (0UL) /*!< CPRDLAT (Bit 0) */
+#define QEI2_CPRDLAT_CPRDLAT_Msk (0xffffffffUL) /*!< CPRDLAT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= IENR ========================================================== */
+#define QEI2_IENR_CDE_Pos (10UL) /*!< CDE (Bit 10) */
+#define QEI2_IENR_CDE_Msk (0x400UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PRE_Pos (9UL) /*!< PRE (Bit 9) */
+#define QEI2_IENR_PRE_Msk (0x200UL) /*!< PRE (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PIE_Pos (8UL) /*!< PIE (Bit 8) */
+#define QEI2_IENR_PIE_Msk (0x100UL) /*!< PIE (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI2_IENR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI2_IENR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI2_IENR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI2_IENR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI2_IENR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI2_IENR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_QPE_Pos (1UL) /*!< QPE (Bit 1) */
+#define QEI2_IENR_QPE_Msk (0x2UL) /*!< QPE (Bitfield-Mask: 0x01) */
+#define QEI2_IENR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI2_IENR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+/* ========================================================= STSR ========================================================== */
+#define QEI2_STSR_QDF_Pos (16UL) /*!< QDF (Bit 16) */
+#define QEI2_STSR_QDF_Msk (0x10000UL) /*!< QDF (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_QDI_Pos (15UL) /*!< QDI (Bit 15) */
+#define QEI2_STSR_QDI_Msk (0x8000UL) /*!< QDI (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_QDS_Pos (14UL) /*!< QDS (Bit 14) */
+#define QEI2_STSR_QDS_Msk (0x4000UL) /*!< QDS (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_COE_Pos (13UL) /*!< COE (Bit 13) */
+#define QEI2_STSR_COE_Msk (0x2000UL) /*!< COE (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_CDE_Pos (12UL) /*!< CDE (Bit 12) */
+#define QEI2_STSR_CDE_Msk (0x1000UL) /*!< CDE (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_FIS_Pos (11UL) /*!< FIS (Bit 11) */
+#define QEI2_STSR_FIS_Msk (0x800UL) /*!< FIS (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_CDS_Pos (10UL) /*!< CDS (Bit 10) */
+#define QEI2_STSR_CDS_Msk (0x400UL) /*!< CDS (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PRS_Pos (9UL) /*!< PRS (Bit 9) */
+#define QEI2_STSR_PRS_Msk (0x200UL) /*!< PRS (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PIS_Pos (8UL) /*!< PIS (Bit 8) */
+#define QEI2_STSR_PIS_Msk (0x100UL) /*!< PIS (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_UTO_Pos (7UL) /*!< UTO (Bit 7) */
+#define QEI2_STSR_UTO_Msk (0x80UL) /*!< UTO (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_IEL_Pos (6UL) /*!< IEL (Bit 6) */
+#define QEI2_STSR_IEL_Msk (0x40UL) /*!< IEL (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PCM_Pos (5UL) /*!< PCM (Bit 5) */
+#define QEI2_STSR_PCM_Msk (0x20UL) /*!< PCM (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PCO_Pos (4UL) /*!< PCO (Bit 4) */
+#define QEI2_STSR_PCO_Msk (0x10UL) /*!< PCO (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PCU_Pos (3UL) /*!< PCU (Bit 3) */
+#define QEI2_STSR_PCU_Msk (0x8UL) /*!< PCU (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_QDC_Pos (2UL) /*!< QDC (Bit 2) */
+#define QEI2_STSR_QDC_Msk (0x4UL) /*!< QDC (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PHE_Pos (1UL) /*!< PHE (Bit 1) */
+#define QEI2_STSR_PHE_Msk (0x2UL) /*!< PHE (Bitfield-Mask: 0x01) */
+#define QEI2_STSR_PCE_Pos (0UL) /*!< PCE (Bit 0) */
+#define QEI2_STSR_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ PDM0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define PDM0_ENABLE_INMOD_Pos (1UL) /*!< INMOD (Bit 1) */
+#define PDM0_ENABLE_INMOD_Msk (0x2UL) /*!< INMOD (Bitfield-Mask: 0x01) */
+#define PDM0_ENABLE_PDMEN_Pos (0UL) /*!< PDMEN (Bit 0) */
+#define PDM0_ENABLE_PDMEN_Msk (0x1UL) /*!< PDMEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define PDM0_CTRL_RXDLY_Pos (28UL) /*!< RXDLY (Bit 28) */
+#define PDM0_CTRL_RXDLY_Msk (0x70000000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define PDM0_CTRL_DMAEN_Pos (19UL) /*!< DMAEN (Bit 19) */
+#define PDM0_CTRL_DMAEN_Msk (0x80000UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+#define PDM0_CTRL_SAMPMODE_Pos (18UL) /*!< SAMPMODE (Bit 18) */
+#define PDM0_CTRL_SAMPMODE_Msk (0x40000UL) /*!< SAMPMODE (Bitfield-Mask: 0x01) */
+#define PDM0_CTRL_SCPOL_Pos (17UL) /*!< SCPOL (Bit 17) */
+#define PDM0_CTRL_SCPOL_Msk (0x20000UL) /*!< SCPOL (Bitfield-Mask: 0x01) */
+#define PDM0_CTRL_MSTEN_Pos (16UL) /*!< MSTEN (Bit 16) */
+#define PDM0_CTRL_MSTEN_Msk (0x10000UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define PDM0_CTRL_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define PDM0_CTRL_BAUD_Msk (0xfffUL) /*!< BAUD (Bitfield-Mask: 0xfff) */
+/* ========================================================= DFCR ========================================================== */
+#define PDM0_DFCR_SHIFT_Pos (16UL) /*!< SHIFT (Bit 16) */
+#define PDM0_DFCR_SHIFT_Msk (0xf0000UL) /*!< SHIFT (Bitfield-Mask: 0x0f) */
+#define PDM0_DFCR_SDSYNCEN_Pos (14UL) /*!< SDSYNCEN (Bit 14) */
+#define PDM0_DFCR_SDSYNCEN_Msk (0x4000UL) /*!< SDSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM0_DFCR_DFDR_Pos (13UL) /*!< DFDR (Bit 13) */
+#define PDM0_DFCR_DFDR_Msk (0x2000UL) /*!< DFDR (Bitfield-Mask: 0x01) */
+#define PDM0_DFCR_DFBYPASS_Pos (12UL) /*!< DFBYPASS (Bit 12) */
+#define PDM0_DFCR_DFBYPASS_Msk (0x1000UL) /*!< DFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM0_DFCR_DFSST_Pos (9UL) /*!< DFSST (Bit 9) */
+#define PDM0_DFCR_DFSST_Msk (0xe00UL) /*!< DFSST (Bitfield-Mask: 0x07) */
+#define PDM0_DFCR_DFEN_Pos (8UL) /*!< DFEN (Bit 8) */
+#define PDM0_DFCR_DFEN_Msk (0x100UL) /*!< DFEN (Bitfield-Mask: 0x01) */
+#define PDM0_DFCR_DOSR_Pos (0UL) /*!< DOSR (Bit 0) */
+#define PDM0_DFCR_DOSR_Msk (0xffUL) /*!< DOSR (Bitfield-Mask: 0xff) */
+/* ========================================================= CFCR ========================================================== */
+#define PDM0_CFCR_COMPSEL_Pos (10UL) /*!< COMPSEL (Bit 10) */
+#define PDM0_CFCR_COMPSEL_Msk (0x400UL) /*!< COMPSEL (Bitfield-Mask: 0x01) */
+#define PDM0_CFCR_CFBYPASS_Pos (9UL) /*!< CFBYPASS (Bit 9) */
+#define PDM0_CFCR_CFBYPASS_Msk (0x200UL) /*!< CFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM0_CFCR_CFSST_Pos (6UL) /*!< CFSST (Bit 6) */
+#define PDM0_CFCR_CFSST_Msk (0x1c0UL) /*!< CFSST (Bitfield-Mask: 0x07) */
+#define PDM0_CFCR_CFEN_Pos (5UL) /*!< CFEN (Bit 5) */
+#define PDM0_CFCR_CFEN_Msk (0x20UL) /*!< CFEN (Bitfield-Mask: 0x01) */
+#define PDM0_CFCR_COSR_Pos (0UL) /*!< COSR (Bit 0) */
+#define PDM0_CFCR_COSR_Msk (0x1fUL) /*!< COSR (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCSR ========================================================== */
+#define PDM0_FCSR_FIFORST_Pos (18UL) /*!< FIFORST (Bit 18) */
+#define PDM0_FCSR_FIFORST_Msk (0x40000UL) /*!< FIFORST (Bitfield-Mask: 0x01) */
+#define PDM0_FCSR_FIFOFULL_Pos (17UL) /*!< FIFOFULL (Bit 17) */
+#define PDM0_FCSR_FIFOFULL_Msk (0x20000UL) /*!< FIFOFULL (Bitfield-Mask: 0x01) */
+#define PDM0_FCSR_FIFOEMPTY_Pos (16UL) /*!< FIFOEMPTY (Bit 16) */
+#define PDM0_FCSR_FIFOEMPTY_Msk (0x10000UL) /*!< FIFOEMPTY (Bitfield-Mask: 0x01) */
+#define PDM0_FCSR_PDMFST_Pos (8UL) /*!< PDMFST (Bit 8) */
+#define PDM0_FCSR_PDMFST_Msk (0xf00UL) /*!< PDMFST (Bitfield-Mask: 0x0f) */
+#define PDM0_FCSR_PDMFIL_Pos (0UL) /*!< PDMFIL (Bit 0) */
+#define PDM0_FCSR_PDMFIL_Msk (0x7UL) /*!< PDMFIL (Bitfield-Mask: 0x07) */
+/* ========================================================== IER ========================================================== */
+#define PDM0_IER_FIUIE_Pos (7UL) /*!< FIUIE (Bit 7) */
+#define PDM0_IER_FIUIE_Msk (0x80UL) /*!< FIUIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_CTIE_Pos (6UL) /*!< CTIE (Bit 6) */
+#define PDM0_IER_CTIE_Msk (0x40UL) /*!< CTIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_FFIE_Pos (5UL) /*!< FFIE (Bit 5) */
+#define PDM0_IER_FFIE_Msk (0x20UL) /*!< FFIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_FIOIE_Pos (4UL) /*!< FIOIE (Bit 4) */
+#define PDM0_IER_FIOIE_Msk (0x10UL) /*!< FIOIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_DOFIE_Pos (3UL) /*!< DOFIE (Bit 3) */
+#define PDM0_IER_DOFIE_Msk (0x8UL) /*!< DOFIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_DFIE_Pos (2UL) /*!< DFIE (Bit 2) */
+#define PDM0_IER_DFIE_Msk (0x4UL) /*!< DFIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_LLIE_Pos (1UL) /*!< LLIE (Bit 1) */
+#define PDM0_IER_LLIE_Msk (0x2UL) /*!< LLIE (Bitfield-Mask: 0x01) */
+#define PDM0_IER_HLIE_Pos (0UL) /*!< HLIE (Bit 0) */
+#define PDM0_IER_HLIE_Msk (0x1UL) /*!< HLIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define PDM0_ISR_FIUINTR_Pos (7UL) /*!< FIUINTR (Bit 7) */
+#define PDM0_ISR_FIUINTR_Msk (0x80UL) /*!< FIUINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_CTOINTR_Pos (6UL) /*!< CTOINTR (Bit 6) */
+#define PDM0_ISR_CTOINTR_Msk (0x40UL) /*!< CTOINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_FIFINTR_Pos (5UL) /*!< FIFINTR (Bit 5) */
+#define PDM0_ISR_FIFINTR_Msk (0x20UL) /*!< FIFINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_FIOINTR_Pos (4UL) /*!< FIOINTR (Bit 4) */
+#define PDM0_ISR_FIOINTR_Msk (0x10UL) /*!< FIOINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_DOINTR_Pos (3UL) /*!< DOINTR (Bit 3) */
+#define PDM0_ISR_DOINTR_Msk (0x8UL) /*!< DOINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_DFINTR_Pos (2UL) /*!< DFINTR (Bit 2) */
+#define PDM0_ISR_DFINTR_Msk (0x4UL) /*!< DFINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_LLINTR_Pos (1UL) /*!< LLINTR (Bit 1) */
+#define PDM0_ISR_LLINTR_Msk (0x2UL) /*!< LLINTR (Bitfield-Mask: 0x01) */
+#define PDM0_ISR_HLINTR_Pos (0UL) /*!< HLINTR (Bit 0) */
+#define PDM0_ISR_HLINTR_Msk (0x1UL) /*!< HLINTR (Bitfield-Mask: 0x01) */
+/* ========================================================= DDAT ========================================================== */
+#define PDM0_DDAT_DDAT_Pos (0UL) /*!< DDAT (Bit 0) */
+#define PDM0_DDAT_DDAT_Msk (0xffffffUL) /*!< DDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CDAT ========================================================== */
+#define PDM0_CDAT_CDAT_Pos (0UL) /*!< CDAT (Bit 0) */
+#define PDM0_CDAT_CDAT_Msk (0xffffUL) /*!< CDAT (Bitfield-Mask: 0xffff) */
+/* ========================================================= FDAT ========================================================== */
+#define PDM0_FDAT_FDAT_Pos (0UL) /*!< FDAT (Bit 0) */
+#define PDM0_FDAT_FDAT_Msk (0xffffffUL) /*!< FDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CMPH ========================================================== */
+#define PDM0_CMPH_HLT_Pos (0UL) /*!< HLT (Bit 0) */
+#define PDM0_CMPH_HLT_Msk (0xffffUL) /*!< HLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPL ========================================================== */
+#define PDM0_CMPL_LLT_Pos (0UL) /*!< LLT (Bit 0) */
+#define PDM0_CMPL_LLT_Msk (0xffffUL) /*!< LLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CLKTO ========================================================= */
+#define PDM0_CLKTO_CLKTOT_Pos (0UL) /*!< CLKTOT (Bit 0) */
+#define PDM0_CLKTO_CLKTOT_Msk (0x3ffffUL) /*!< CLKTOT (Bitfield-Mask: 0x3ffff) */
+/* ======================================================== SDSYNC ========================================================= */
+#define PDM0_SDSYNC_WTSCLREN_Pos (10UL) /*!< WTSCLREN (Bit 10) */
+#define PDM0_SDSYNC_WTSCLREN_Msk (0x400UL) /*!< WTSCLREN (Bitfield-Mask: 0x01) */
+#define PDM0_SDSYNC_FFSYNCCLREN_Pos (9UL) /*!< FFSYNCCLREN (Bit 9) */
+#define PDM0_SDSYNC_FFSYNCCLREN_Msk (0x200UL) /*!< FFSYNCCLREN (Bitfield-Mask: 0x01) */
+#define PDM0_SDSYNC_WTSYNCLR_Pos (8UL) /*!< WTSYNCLR (Bit 8) */
+#define PDM0_SDSYNC_WTSYNCLR_Msk (0x100UL) /*!< WTSYNCLR (Bitfield-Mask: 0x01) */
+#define PDM0_SDSYNC_WTSYNFLG_Pos (7UL) /*!< WTSYNFLG (Bit 7) */
+#define PDM0_SDSYNC_WTSYNFLG_Msk (0x80UL) /*!< WTSYNFLG (Bitfield-Mask: 0x01) */
+#define PDM0_SDSYNC_WTSYNCEN_Pos (6UL) /*!< WTSYNCEN (Bit 6) */
+#define PDM0_SDSYNC_WTSYNCEN_Msk (0x40UL) /*!< WTSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM0_SDSYNC_SYNCSEL_Pos (0UL) /*!< SYNCSEL (Bit 0) */
+#define PDM0_SDSYNC_SYNCSEL_Msk (0x3fUL) /*!< SYNCSEL (Bitfield-Mask: 0x3f) */
+/* ========================================================= IDAT ========================================================== */
+#define PDM0_IDAT_IDAT_Pos (0UL) /*!< IDAT (Bit 0) */
+#define PDM0_IDAT_IDAT_Msk (0xffffUL) /*!< IDAT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ PDM1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define PDM1_ENABLE_INMOD_Pos (1UL) /*!< INMOD (Bit 1) */
+#define PDM1_ENABLE_INMOD_Msk (0x2UL) /*!< INMOD (Bitfield-Mask: 0x01) */
+#define PDM1_ENABLE_PDMEN_Pos (0UL) /*!< PDMEN (Bit 0) */
+#define PDM1_ENABLE_PDMEN_Msk (0x1UL) /*!< PDMEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define PDM1_CTRL_RXDLY_Pos (28UL) /*!< RXDLY (Bit 28) */
+#define PDM1_CTRL_RXDLY_Msk (0x70000000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define PDM1_CTRL_DMAEN_Pos (19UL) /*!< DMAEN (Bit 19) */
+#define PDM1_CTRL_DMAEN_Msk (0x80000UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+#define PDM1_CTRL_SAMPMODE_Pos (18UL) /*!< SAMPMODE (Bit 18) */
+#define PDM1_CTRL_SAMPMODE_Msk (0x40000UL) /*!< SAMPMODE (Bitfield-Mask: 0x01) */
+#define PDM1_CTRL_SCPOL_Pos (17UL) /*!< SCPOL (Bit 17) */
+#define PDM1_CTRL_SCPOL_Msk (0x20000UL) /*!< SCPOL (Bitfield-Mask: 0x01) */
+#define PDM1_CTRL_MSTEN_Pos (16UL) /*!< MSTEN (Bit 16) */
+#define PDM1_CTRL_MSTEN_Msk (0x10000UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define PDM1_CTRL_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define PDM1_CTRL_BAUD_Msk (0xfffUL) /*!< BAUD (Bitfield-Mask: 0xfff) */
+/* ========================================================= DFCR ========================================================== */
+#define PDM1_DFCR_SHIFT_Pos (16UL) /*!< SHIFT (Bit 16) */
+#define PDM1_DFCR_SHIFT_Msk (0xf0000UL) /*!< SHIFT (Bitfield-Mask: 0x0f) */
+#define PDM1_DFCR_SDSYNCEN_Pos (14UL) /*!< SDSYNCEN (Bit 14) */
+#define PDM1_DFCR_SDSYNCEN_Msk (0x4000UL) /*!< SDSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM1_DFCR_DFDR_Pos (13UL) /*!< DFDR (Bit 13) */
+#define PDM1_DFCR_DFDR_Msk (0x2000UL) /*!< DFDR (Bitfield-Mask: 0x01) */
+#define PDM1_DFCR_DFBYPASS_Pos (12UL) /*!< DFBYPASS (Bit 12) */
+#define PDM1_DFCR_DFBYPASS_Msk (0x1000UL) /*!< DFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM1_DFCR_DFSST_Pos (9UL) /*!< DFSST (Bit 9) */
+#define PDM1_DFCR_DFSST_Msk (0xe00UL) /*!< DFSST (Bitfield-Mask: 0x07) */
+#define PDM1_DFCR_DFEN_Pos (8UL) /*!< DFEN (Bit 8) */
+#define PDM1_DFCR_DFEN_Msk (0x100UL) /*!< DFEN (Bitfield-Mask: 0x01) */
+#define PDM1_DFCR_DOSR_Pos (0UL) /*!< DOSR (Bit 0) */
+#define PDM1_DFCR_DOSR_Msk (0xffUL) /*!< DOSR (Bitfield-Mask: 0xff) */
+/* ========================================================= CFCR ========================================================== */
+#define PDM1_CFCR_COMPSEL_Pos (10UL) /*!< COMPSEL (Bit 10) */
+#define PDM1_CFCR_COMPSEL_Msk (0x400UL) /*!< COMPSEL (Bitfield-Mask: 0x01) */
+#define PDM1_CFCR_CFBYPASS_Pos (9UL) /*!< CFBYPASS (Bit 9) */
+#define PDM1_CFCR_CFBYPASS_Msk (0x200UL) /*!< CFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM1_CFCR_CFSST_Pos (6UL) /*!< CFSST (Bit 6) */
+#define PDM1_CFCR_CFSST_Msk (0x1c0UL) /*!< CFSST (Bitfield-Mask: 0x07) */
+#define PDM1_CFCR_CFEN_Pos (5UL) /*!< CFEN (Bit 5) */
+#define PDM1_CFCR_CFEN_Msk (0x20UL) /*!< CFEN (Bitfield-Mask: 0x01) */
+#define PDM1_CFCR_COSR_Pos (0UL) /*!< COSR (Bit 0) */
+#define PDM1_CFCR_COSR_Msk (0x1fUL) /*!< COSR (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCSR ========================================================== */
+#define PDM1_FCSR_FIFORST_Pos (18UL) /*!< FIFORST (Bit 18) */
+#define PDM1_FCSR_FIFORST_Msk (0x40000UL) /*!< FIFORST (Bitfield-Mask: 0x01) */
+#define PDM1_FCSR_FIFOFULL_Pos (17UL) /*!< FIFOFULL (Bit 17) */
+#define PDM1_FCSR_FIFOFULL_Msk (0x20000UL) /*!< FIFOFULL (Bitfield-Mask: 0x01) */
+#define PDM1_FCSR_FIFOEMPTY_Pos (16UL) /*!< FIFOEMPTY (Bit 16) */
+#define PDM1_FCSR_FIFOEMPTY_Msk (0x10000UL) /*!< FIFOEMPTY (Bitfield-Mask: 0x01) */
+#define PDM1_FCSR_PDMFST_Pos (8UL) /*!< PDMFST (Bit 8) */
+#define PDM1_FCSR_PDMFST_Msk (0xf00UL) /*!< PDMFST (Bitfield-Mask: 0x0f) */
+#define PDM1_FCSR_PDMFIL_Pos (0UL) /*!< PDMFIL (Bit 0) */
+#define PDM1_FCSR_PDMFIL_Msk (0x7UL) /*!< PDMFIL (Bitfield-Mask: 0x07) */
+/* ========================================================== IER ========================================================== */
+#define PDM1_IER_FIUIE_Pos (7UL) /*!< FIUIE (Bit 7) */
+#define PDM1_IER_FIUIE_Msk (0x80UL) /*!< FIUIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_CTIE_Pos (6UL) /*!< CTIE (Bit 6) */
+#define PDM1_IER_CTIE_Msk (0x40UL) /*!< CTIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_FFIE_Pos (5UL) /*!< FFIE (Bit 5) */
+#define PDM1_IER_FFIE_Msk (0x20UL) /*!< FFIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_FIOIE_Pos (4UL) /*!< FIOIE (Bit 4) */
+#define PDM1_IER_FIOIE_Msk (0x10UL) /*!< FIOIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_DOFIE_Pos (3UL) /*!< DOFIE (Bit 3) */
+#define PDM1_IER_DOFIE_Msk (0x8UL) /*!< DOFIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_DFIE_Pos (2UL) /*!< DFIE (Bit 2) */
+#define PDM1_IER_DFIE_Msk (0x4UL) /*!< DFIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_LLIE_Pos (1UL) /*!< LLIE (Bit 1) */
+#define PDM1_IER_LLIE_Msk (0x2UL) /*!< LLIE (Bitfield-Mask: 0x01) */
+#define PDM1_IER_HLIE_Pos (0UL) /*!< HLIE (Bit 0) */
+#define PDM1_IER_HLIE_Msk (0x1UL) /*!< HLIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define PDM1_ISR_FIUINTR_Pos (7UL) /*!< FIUINTR (Bit 7) */
+#define PDM1_ISR_FIUINTR_Msk (0x80UL) /*!< FIUINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_CTOINTR_Pos (6UL) /*!< CTOINTR (Bit 6) */
+#define PDM1_ISR_CTOINTR_Msk (0x40UL) /*!< CTOINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_FIFINTR_Pos (5UL) /*!< FIFINTR (Bit 5) */
+#define PDM1_ISR_FIFINTR_Msk (0x20UL) /*!< FIFINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_FIOINTR_Pos (4UL) /*!< FIOINTR (Bit 4) */
+#define PDM1_ISR_FIOINTR_Msk (0x10UL) /*!< FIOINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_DOINTR_Pos (3UL) /*!< DOINTR (Bit 3) */
+#define PDM1_ISR_DOINTR_Msk (0x8UL) /*!< DOINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_DFINTR_Pos (2UL) /*!< DFINTR (Bit 2) */
+#define PDM1_ISR_DFINTR_Msk (0x4UL) /*!< DFINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_LLINTR_Pos (1UL) /*!< LLINTR (Bit 1) */
+#define PDM1_ISR_LLINTR_Msk (0x2UL) /*!< LLINTR (Bitfield-Mask: 0x01) */
+#define PDM1_ISR_HLINTR_Pos (0UL) /*!< HLINTR (Bit 0) */
+#define PDM1_ISR_HLINTR_Msk (0x1UL) /*!< HLINTR (Bitfield-Mask: 0x01) */
+/* ========================================================= DDAT ========================================================== */
+#define PDM1_DDAT_DDAT_Pos (0UL) /*!< DDAT (Bit 0) */
+#define PDM1_DDAT_DDAT_Msk (0xffffffUL) /*!< DDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CDAT ========================================================== */
+#define PDM1_CDAT_CDAT_Pos (0UL) /*!< CDAT (Bit 0) */
+#define PDM1_CDAT_CDAT_Msk (0xffffUL) /*!< CDAT (Bitfield-Mask: 0xffff) */
+/* ========================================================= FDAT ========================================================== */
+#define PDM1_FDAT_FDAT_Pos (0UL) /*!< FDAT (Bit 0) */
+#define PDM1_FDAT_FDAT_Msk (0xffffffUL) /*!< FDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CMPH ========================================================== */
+#define PDM1_CMPH_HLT_Pos (0UL) /*!< HLT (Bit 0) */
+#define PDM1_CMPH_HLT_Msk (0xffffUL) /*!< HLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPL ========================================================== */
+#define PDM1_CMPL_LLT_Pos (0UL) /*!< LLT (Bit 0) */
+#define PDM1_CMPL_LLT_Msk (0xffffUL) /*!< LLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CLKTO ========================================================= */
+#define PDM1_CLKTO_CLKTOT_Pos (0UL) /*!< CLKTOT (Bit 0) */
+#define PDM1_CLKTO_CLKTOT_Msk (0x3ffffUL) /*!< CLKTOT (Bitfield-Mask: 0x3ffff) */
+/* ======================================================== SDSYNC ========================================================= */
+#define PDM1_SDSYNC_WTSCLREN_Pos (10UL) /*!< WTSCLREN (Bit 10) */
+#define PDM1_SDSYNC_WTSCLREN_Msk (0x400UL) /*!< WTSCLREN (Bitfield-Mask: 0x01) */
+#define PDM1_SDSYNC_FFSYNCCLREN_Pos (9UL) /*!< FFSYNCCLREN (Bit 9) */
+#define PDM1_SDSYNC_FFSYNCCLREN_Msk (0x200UL) /*!< FFSYNCCLREN (Bitfield-Mask: 0x01) */
+#define PDM1_SDSYNC_WTSYNCLR_Pos (8UL) /*!< WTSYNCLR (Bit 8) */
+#define PDM1_SDSYNC_WTSYNCLR_Msk (0x100UL) /*!< WTSYNCLR (Bitfield-Mask: 0x01) */
+#define PDM1_SDSYNC_WTSYNFLG_Pos (7UL) /*!< WTSYNFLG (Bit 7) */
+#define PDM1_SDSYNC_WTSYNFLG_Msk (0x80UL) /*!< WTSYNFLG (Bitfield-Mask: 0x01) */
+#define PDM1_SDSYNC_WTSYNCEN_Pos (6UL) /*!< WTSYNCEN (Bit 6) */
+#define PDM1_SDSYNC_WTSYNCEN_Msk (0x40UL) /*!< WTSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM1_SDSYNC_SYNCSEL_Pos (0UL) /*!< SYNCSEL (Bit 0) */
+#define PDM1_SDSYNC_SYNCSEL_Msk (0x3fUL) /*!< SYNCSEL (Bitfield-Mask: 0x3f) */
+/* ========================================================= IDAT ========================================================== */
+#define PDM1_IDAT_IDAT_Pos (0UL) /*!< IDAT (Bit 0) */
+#define PDM1_IDAT_IDAT_Msk (0xffffUL) /*!< IDAT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ PDM2 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define PDM2_ENABLE_INMOD_Pos (1UL) /*!< INMOD (Bit 1) */
+#define PDM2_ENABLE_INMOD_Msk (0x2UL) /*!< INMOD (Bitfield-Mask: 0x01) */
+#define PDM2_ENABLE_PDMEN_Pos (0UL) /*!< PDMEN (Bit 0) */
+#define PDM2_ENABLE_PDMEN_Msk (0x1UL) /*!< PDMEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define PDM2_CTRL_RXDLY_Pos (28UL) /*!< RXDLY (Bit 28) */
+#define PDM2_CTRL_RXDLY_Msk (0x70000000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define PDM2_CTRL_DMAEN_Pos (19UL) /*!< DMAEN (Bit 19) */
+#define PDM2_CTRL_DMAEN_Msk (0x80000UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+#define PDM2_CTRL_SAMPMODE_Pos (18UL) /*!< SAMPMODE (Bit 18) */
+#define PDM2_CTRL_SAMPMODE_Msk (0x40000UL) /*!< SAMPMODE (Bitfield-Mask: 0x01) */
+#define PDM2_CTRL_SCPOL_Pos (17UL) /*!< SCPOL (Bit 17) */
+#define PDM2_CTRL_SCPOL_Msk (0x20000UL) /*!< SCPOL (Bitfield-Mask: 0x01) */
+#define PDM2_CTRL_MSTEN_Pos (16UL) /*!< MSTEN (Bit 16) */
+#define PDM2_CTRL_MSTEN_Msk (0x10000UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define PDM2_CTRL_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define PDM2_CTRL_BAUD_Msk (0xfffUL) /*!< BAUD (Bitfield-Mask: 0xfff) */
+/* ========================================================= DFCR ========================================================== */
+#define PDM2_DFCR_SHIFT_Pos (16UL) /*!< SHIFT (Bit 16) */
+#define PDM2_DFCR_SHIFT_Msk (0xf0000UL) /*!< SHIFT (Bitfield-Mask: 0x0f) */
+#define PDM2_DFCR_SDSYNCEN_Pos (14UL) /*!< SDSYNCEN (Bit 14) */
+#define PDM2_DFCR_SDSYNCEN_Msk (0x4000UL) /*!< SDSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM2_DFCR_DFDR_Pos (13UL) /*!< DFDR (Bit 13) */
+#define PDM2_DFCR_DFDR_Msk (0x2000UL) /*!< DFDR (Bitfield-Mask: 0x01) */
+#define PDM2_DFCR_DFBYPASS_Pos (12UL) /*!< DFBYPASS (Bit 12) */
+#define PDM2_DFCR_DFBYPASS_Msk (0x1000UL) /*!< DFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM2_DFCR_DFSST_Pos (9UL) /*!< DFSST (Bit 9) */
+#define PDM2_DFCR_DFSST_Msk (0xe00UL) /*!< DFSST (Bitfield-Mask: 0x07) */
+#define PDM2_DFCR_DFEN_Pos (8UL) /*!< DFEN (Bit 8) */
+#define PDM2_DFCR_DFEN_Msk (0x100UL) /*!< DFEN (Bitfield-Mask: 0x01) */
+#define PDM2_DFCR_DOSR_Pos (0UL) /*!< DOSR (Bit 0) */
+#define PDM2_DFCR_DOSR_Msk (0xffUL) /*!< DOSR (Bitfield-Mask: 0xff) */
+/* ========================================================= CFCR ========================================================== */
+#define PDM2_CFCR_COMPSEL_Pos (10UL) /*!< COMPSEL (Bit 10) */
+#define PDM2_CFCR_COMPSEL_Msk (0x400UL) /*!< COMPSEL (Bitfield-Mask: 0x01) */
+#define PDM2_CFCR_CFBYPASS_Pos (9UL) /*!< CFBYPASS (Bit 9) */
+#define PDM2_CFCR_CFBYPASS_Msk (0x200UL) /*!< CFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM2_CFCR_CFSST_Pos (6UL) /*!< CFSST (Bit 6) */
+#define PDM2_CFCR_CFSST_Msk (0x1c0UL) /*!< CFSST (Bitfield-Mask: 0x07) */
+#define PDM2_CFCR_CFEN_Pos (5UL) /*!< CFEN (Bit 5) */
+#define PDM2_CFCR_CFEN_Msk (0x20UL) /*!< CFEN (Bitfield-Mask: 0x01) */
+#define PDM2_CFCR_COSR_Pos (0UL) /*!< COSR (Bit 0) */
+#define PDM2_CFCR_COSR_Msk (0x1fUL) /*!< COSR (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCSR ========================================================== */
+#define PDM2_FCSR_FIFORST_Pos (18UL) /*!< FIFORST (Bit 18) */
+#define PDM2_FCSR_FIFORST_Msk (0x40000UL) /*!< FIFORST (Bitfield-Mask: 0x01) */
+#define PDM2_FCSR_FIFOFULL_Pos (17UL) /*!< FIFOFULL (Bit 17) */
+#define PDM2_FCSR_FIFOFULL_Msk (0x20000UL) /*!< FIFOFULL (Bitfield-Mask: 0x01) */
+#define PDM2_FCSR_FIFOEMPTY_Pos (16UL) /*!< FIFOEMPTY (Bit 16) */
+#define PDM2_FCSR_FIFOEMPTY_Msk (0x10000UL) /*!< FIFOEMPTY (Bitfield-Mask: 0x01) */
+#define PDM2_FCSR_PDMFST_Pos (8UL) /*!< PDMFST (Bit 8) */
+#define PDM2_FCSR_PDMFST_Msk (0xf00UL) /*!< PDMFST (Bitfield-Mask: 0x0f) */
+#define PDM2_FCSR_PDMFIL_Pos (0UL) /*!< PDMFIL (Bit 0) */
+#define PDM2_FCSR_PDMFIL_Msk (0x7UL) /*!< PDMFIL (Bitfield-Mask: 0x07) */
+/* ========================================================== IER ========================================================== */
+#define PDM2_IER_FIUIE_Pos (7UL) /*!< FIUIE (Bit 7) */
+#define PDM2_IER_FIUIE_Msk (0x80UL) /*!< FIUIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_CTIE_Pos (6UL) /*!< CTIE (Bit 6) */
+#define PDM2_IER_CTIE_Msk (0x40UL) /*!< CTIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_FFIE_Pos (5UL) /*!< FFIE (Bit 5) */
+#define PDM2_IER_FFIE_Msk (0x20UL) /*!< FFIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_FIOIE_Pos (4UL) /*!< FIOIE (Bit 4) */
+#define PDM2_IER_FIOIE_Msk (0x10UL) /*!< FIOIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_DOFIE_Pos (3UL) /*!< DOFIE (Bit 3) */
+#define PDM2_IER_DOFIE_Msk (0x8UL) /*!< DOFIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_DFIE_Pos (2UL) /*!< DFIE (Bit 2) */
+#define PDM2_IER_DFIE_Msk (0x4UL) /*!< DFIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_LLIE_Pos (1UL) /*!< LLIE (Bit 1) */
+#define PDM2_IER_LLIE_Msk (0x2UL) /*!< LLIE (Bitfield-Mask: 0x01) */
+#define PDM2_IER_HLIE_Pos (0UL) /*!< HLIE (Bit 0) */
+#define PDM2_IER_HLIE_Msk (0x1UL) /*!< HLIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define PDM2_ISR_FIUINTR_Pos (7UL) /*!< FIUINTR (Bit 7) */
+#define PDM2_ISR_FIUINTR_Msk (0x80UL) /*!< FIUINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_CTOINTR_Pos (6UL) /*!< CTOINTR (Bit 6) */
+#define PDM2_ISR_CTOINTR_Msk (0x40UL) /*!< CTOINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_FIFINTR_Pos (5UL) /*!< FIFINTR (Bit 5) */
+#define PDM2_ISR_FIFINTR_Msk (0x20UL) /*!< FIFINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_FIOINTR_Pos (4UL) /*!< FIOINTR (Bit 4) */
+#define PDM2_ISR_FIOINTR_Msk (0x10UL) /*!< FIOINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_DOINTR_Pos (3UL) /*!< DOINTR (Bit 3) */
+#define PDM2_ISR_DOINTR_Msk (0x8UL) /*!< DOINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_DFINTR_Pos (2UL) /*!< DFINTR (Bit 2) */
+#define PDM2_ISR_DFINTR_Msk (0x4UL) /*!< DFINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_LLINTR_Pos (1UL) /*!< LLINTR (Bit 1) */
+#define PDM2_ISR_LLINTR_Msk (0x2UL) /*!< LLINTR (Bitfield-Mask: 0x01) */
+#define PDM2_ISR_HLINTR_Pos (0UL) /*!< HLINTR (Bit 0) */
+#define PDM2_ISR_HLINTR_Msk (0x1UL) /*!< HLINTR (Bitfield-Mask: 0x01) */
+/* ========================================================= DDAT ========================================================== */
+#define PDM2_DDAT_DDAT_Pos (0UL) /*!< DDAT (Bit 0) */
+#define PDM2_DDAT_DDAT_Msk (0xffffffUL) /*!< DDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CDAT ========================================================== */
+#define PDM2_CDAT_CDAT_Pos (0UL) /*!< CDAT (Bit 0) */
+#define PDM2_CDAT_CDAT_Msk (0xffffUL) /*!< CDAT (Bitfield-Mask: 0xffff) */
+/* ========================================================= FDAT ========================================================== */
+#define PDM2_FDAT_FDAT_Pos (0UL) /*!< FDAT (Bit 0) */
+#define PDM2_FDAT_FDAT_Msk (0xffffffUL) /*!< FDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CMPH ========================================================== */
+#define PDM2_CMPH_HLT_Pos (0UL) /*!< HLT (Bit 0) */
+#define PDM2_CMPH_HLT_Msk (0xffffUL) /*!< HLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPL ========================================================== */
+#define PDM2_CMPL_LLT_Pos (0UL) /*!< LLT (Bit 0) */
+#define PDM2_CMPL_LLT_Msk (0xffffUL) /*!< LLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CLKTO ========================================================= */
+#define PDM2_CLKTO_CLKTOT_Pos (0UL) /*!< CLKTOT (Bit 0) */
+#define PDM2_CLKTO_CLKTOT_Msk (0x3ffffUL) /*!< CLKTOT (Bitfield-Mask: 0x3ffff) */
+/* ======================================================== SDSYNC ========================================================= */
+#define PDM2_SDSYNC_WTSCLREN_Pos (10UL) /*!< WTSCLREN (Bit 10) */
+#define PDM2_SDSYNC_WTSCLREN_Msk (0x400UL) /*!< WTSCLREN (Bitfield-Mask: 0x01) */
+#define PDM2_SDSYNC_FFSYNCCLREN_Pos (9UL) /*!< FFSYNCCLREN (Bit 9) */
+#define PDM2_SDSYNC_FFSYNCCLREN_Msk (0x200UL) /*!< FFSYNCCLREN (Bitfield-Mask: 0x01) */
+#define PDM2_SDSYNC_WTSYNCLR_Pos (8UL) /*!< WTSYNCLR (Bit 8) */
+#define PDM2_SDSYNC_WTSYNCLR_Msk (0x100UL) /*!< WTSYNCLR (Bitfield-Mask: 0x01) */
+#define PDM2_SDSYNC_WTSYNFLG_Pos (7UL) /*!< WTSYNFLG (Bit 7) */
+#define PDM2_SDSYNC_WTSYNFLG_Msk (0x80UL) /*!< WTSYNFLG (Bitfield-Mask: 0x01) */
+#define PDM2_SDSYNC_WTSYNCEN_Pos (6UL) /*!< WTSYNCEN (Bit 6) */
+#define PDM2_SDSYNC_WTSYNCEN_Msk (0x40UL) /*!< WTSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM2_SDSYNC_SYNCSEL_Pos (0UL) /*!< SYNCSEL (Bit 0) */
+#define PDM2_SDSYNC_SYNCSEL_Msk (0x3fUL) /*!< SYNCSEL (Bitfield-Mask: 0x3f) */
+/* ========================================================= IDAT ========================================================== */
+#define PDM2_IDAT_IDAT_Pos (0UL) /*!< IDAT (Bit 0) */
+#define PDM2_IDAT_IDAT_Msk (0xffffUL) /*!< IDAT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ PDM3 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define PDM3_ENABLE_INMOD_Pos (1UL) /*!< INMOD (Bit 1) */
+#define PDM3_ENABLE_INMOD_Msk (0x2UL) /*!< INMOD (Bitfield-Mask: 0x01) */
+#define PDM3_ENABLE_PDMEN_Pos (0UL) /*!< PDMEN (Bit 0) */
+#define PDM3_ENABLE_PDMEN_Msk (0x1UL) /*!< PDMEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define PDM3_CTRL_RXDLY_Pos (28UL) /*!< RXDLY (Bit 28) */
+#define PDM3_CTRL_RXDLY_Msk (0x70000000UL) /*!< RXDLY (Bitfield-Mask: 0x07) */
+#define PDM3_CTRL_DMAEN_Pos (19UL) /*!< DMAEN (Bit 19) */
+#define PDM3_CTRL_DMAEN_Msk (0x80000UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
+#define PDM3_CTRL_SAMPMODE_Pos (18UL) /*!< SAMPMODE (Bit 18) */
+#define PDM3_CTRL_SAMPMODE_Msk (0x40000UL) /*!< SAMPMODE (Bitfield-Mask: 0x01) */
+#define PDM3_CTRL_SCPOL_Pos (17UL) /*!< SCPOL (Bit 17) */
+#define PDM3_CTRL_SCPOL_Msk (0x20000UL) /*!< SCPOL (Bitfield-Mask: 0x01) */
+#define PDM3_CTRL_MSTEN_Pos (16UL) /*!< MSTEN (Bit 16) */
+#define PDM3_CTRL_MSTEN_Msk (0x10000UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define PDM3_CTRL_BAUD_Pos (0UL) /*!< BAUD (Bit 0) */
+#define PDM3_CTRL_BAUD_Msk (0xfffUL) /*!< BAUD (Bitfield-Mask: 0xfff) */
+/* ========================================================= DFCR ========================================================== */
+#define PDM3_DFCR_SHIFT_Pos (16UL) /*!< SHIFT (Bit 16) */
+#define PDM3_DFCR_SHIFT_Msk (0xf0000UL) /*!< SHIFT (Bitfield-Mask: 0x0f) */
+#define PDM3_DFCR_SDSYNCEN_Pos (14UL) /*!< SDSYNCEN (Bit 14) */
+#define PDM3_DFCR_SDSYNCEN_Msk (0x4000UL) /*!< SDSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM3_DFCR_DFDR_Pos (13UL) /*!< DFDR (Bit 13) */
+#define PDM3_DFCR_DFDR_Msk (0x2000UL) /*!< DFDR (Bitfield-Mask: 0x01) */
+#define PDM3_DFCR_DFBYPASS_Pos (12UL) /*!< DFBYPASS (Bit 12) */
+#define PDM3_DFCR_DFBYPASS_Msk (0x1000UL) /*!< DFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM3_DFCR_DFSST_Pos (9UL) /*!< DFSST (Bit 9) */
+#define PDM3_DFCR_DFSST_Msk (0xe00UL) /*!< DFSST (Bitfield-Mask: 0x07) */
+#define PDM3_DFCR_DFEN_Pos (8UL) /*!< DFEN (Bit 8) */
+#define PDM3_DFCR_DFEN_Msk (0x100UL) /*!< DFEN (Bitfield-Mask: 0x01) */
+#define PDM3_DFCR_DOSR_Pos (0UL) /*!< DOSR (Bit 0) */
+#define PDM3_DFCR_DOSR_Msk (0xffUL) /*!< DOSR (Bitfield-Mask: 0xff) */
+/* ========================================================= CFCR ========================================================== */
+#define PDM3_CFCR_COMPSEL_Pos (10UL) /*!< COMPSEL (Bit 10) */
+#define PDM3_CFCR_COMPSEL_Msk (0x400UL) /*!< COMPSEL (Bitfield-Mask: 0x01) */
+#define PDM3_CFCR_CFBYPASS_Pos (9UL) /*!< CFBYPASS (Bit 9) */
+#define PDM3_CFCR_CFBYPASS_Msk (0x200UL) /*!< CFBYPASS (Bitfield-Mask: 0x01) */
+#define PDM3_CFCR_CFSST_Pos (6UL) /*!< CFSST (Bit 6) */
+#define PDM3_CFCR_CFSST_Msk (0x1c0UL) /*!< CFSST (Bitfield-Mask: 0x07) */
+#define PDM3_CFCR_CFEN_Pos (5UL) /*!< CFEN (Bit 5) */
+#define PDM3_CFCR_CFEN_Msk (0x20UL) /*!< CFEN (Bitfield-Mask: 0x01) */
+#define PDM3_CFCR_COSR_Pos (0UL) /*!< COSR (Bit 0) */
+#define PDM3_CFCR_COSR_Msk (0x1fUL) /*!< COSR (Bitfield-Mask: 0x1f) */
+/* ========================================================= FCSR ========================================================== */
+#define PDM3_FCSR_FIFORST_Pos (18UL) /*!< FIFORST (Bit 18) */
+#define PDM3_FCSR_FIFORST_Msk (0x40000UL) /*!< FIFORST (Bitfield-Mask: 0x01) */
+#define PDM3_FCSR_FIFOFULL_Pos (17UL) /*!< FIFOFULL (Bit 17) */
+#define PDM3_FCSR_FIFOFULL_Msk (0x20000UL) /*!< FIFOFULL (Bitfield-Mask: 0x01) */
+#define PDM3_FCSR_FIFOEMPTY_Pos (16UL) /*!< FIFOEMPTY (Bit 16) */
+#define PDM3_FCSR_FIFOEMPTY_Msk (0x10000UL) /*!< FIFOEMPTY (Bitfield-Mask: 0x01) */
+#define PDM3_FCSR_PDMFST_Pos (8UL) /*!< PDMFST (Bit 8) */
+#define PDM3_FCSR_PDMFST_Msk (0xf00UL) /*!< PDMFST (Bitfield-Mask: 0x0f) */
+#define PDM3_FCSR_PDMFIL_Pos (0UL) /*!< PDMFIL (Bit 0) */
+#define PDM3_FCSR_PDMFIL_Msk (0x7UL) /*!< PDMFIL (Bitfield-Mask: 0x07) */
+/* ========================================================== IER ========================================================== */
+#define PDM3_IER_FIUIE_Pos (7UL) /*!< FIUIE (Bit 7) */
+#define PDM3_IER_FIUIE_Msk (0x80UL) /*!< FIUIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_CTIE_Pos (6UL) /*!< CTIE (Bit 6) */
+#define PDM3_IER_CTIE_Msk (0x40UL) /*!< CTIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_FFIE_Pos (5UL) /*!< FFIE (Bit 5) */
+#define PDM3_IER_FFIE_Msk (0x20UL) /*!< FFIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_FIOIE_Pos (4UL) /*!< FIOIE (Bit 4) */
+#define PDM3_IER_FIOIE_Msk (0x10UL) /*!< FIOIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_DOFIE_Pos (3UL) /*!< DOFIE (Bit 3) */
+#define PDM3_IER_DOFIE_Msk (0x8UL) /*!< DOFIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_DFIE_Pos (2UL) /*!< DFIE (Bit 2) */
+#define PDM3_IER_DFIE_Msk (0x4UL) /*!< DFIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_LLIE_Pos (1UL) /*!< LLIE (Bit 1) */
+#define PDM3_IER_LLIE_Msk (0x2UL) /*!< LLIE (Bitfield-Mask: 0x01) */
+#define PDM3_IER_HLIE_Pos (0UL) /*!< HLIE (Bit 0) */
+#define PDM3_IER_HLIE_Msk (0x1UL) /*!< HLIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define PDM3_ISR_FIUINTR_Pos (7UL) /*!< FIUINTR (Bit 7) */
+#define PDM3_ISR_FIUINTR_Msk (0x80UL) /*!< FIUINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_CTOINTR_Pos (6UL) /*!< CTOINTR (Bit 6) */
+#define PDM3_ISR_CTOINTR_Msk (0x40UL) /*!< CTOINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_FIFINTR_Pos (5UL) /*!< FIFINTR (Bit 5) */
+#define PDM3_ISR_FIFINTR_Msk (0x20UL) /*!< FIFINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_FIOINTR_Pos (4UL) /*!< FIOINTR (Bit 4) */
+#define PDM3_ISR_FIOINTR_Msk (0x10UL) /*!< FIOINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_DOINTR_Pos (3UL) /*!< DOINTR (Bit 3) */
+#define PDM3_ISR_DOINTR_Msk (0x8UL) /*!< DOINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_DFINTR_Pos (2UL) /*!< DFINTR (Bit 2) */
+#define PDM3_ISR_DFINTR_Msk (0x4UL) /*!< DFINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_LLINTR_Pos (1UL) /*!< LLINTR (Bit 1) */
+#define PDM3_ISR_LLINTR_Msk (0x2UL) /*!< LLINTR (Bitfield-Mask: 0x01) */
+#define PDM3_ISR_HLINTR_Pos (0UL) /*!< HLINTR (Bit 0) */
+#define PDM3_ISR_HLINTR_Msk (0x1UL) /*!< HLINTR (Bitfield-Mask: 0x01) */
+/* ========================================================= DDAT ========================================================== */
+#define PDM3_DDAT_DDAT_Pos (0UL) /*!< DDAT (Bit 0) */
+#define PDM3_DDAT_DDAT_Msk (0xffffffUL) /*!< DDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CDAT ========================================================== */
+#define PDM3_CDAT_CDAT_Pos (0UL) /*!< CDAT (Bit 0) */
+#define PDM3_CDAT_CDAT_Msk (0xffffUL) /*!< CDAT (Bitfield-Mask: 0xffff) */
+/* ========================================================= FDAT ========================================================== */
+#define PDM3_FDAT_FDAT_Pos (0UL) /*!< FDAT (Bit 0) */
+#define PDM3_FDAT_FDAT_Msk (0xffffffUL) /*!< FDAT (Bitfield-Mask: 0xffffff) */
+/* ========================================================= CMPH ========================================================== */
+#define PDM3_CMPH_HLT_Pos (0UL) /*!< HLT (Bit 0) */
+#define PDM3_CMPH_HLT_Msk (0xffffUL) /*!< HLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPL ========================================================== */
+#define PDM3_CMPL_LLT_Pos (0UL) /*!< LLT (Bit 0) */
+#define PDM3_CMPL_LLT_Msk (0xffffUL) /*!< LLT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CLKTO ========================================================= */
+#define PDM3_CLKTO_CLKTOT_Pos (0UL) /*!< CLKTOT (Bit 0) */
+#define PDM3_CLKTO_CLKTOT_Msk (0x3ffffUL) /*!< CLKTOT (Bitfield-Mask: 0x3ffff) */
+/* ======================================================== SDSYNC ========================================================= */
+#define PDM3_SDSYNC_WTSCLREN_Pos (10UL) /*!< WTSCLREN (Bit 10) */
+#define PDM3_SDSYNC_WTSCLREN_Msk (0x400UL) /*!< WTSCLREN (Bitfield-Mask: 0x01) */
+#define PDM3_SDSYNC_FFSYNCCLREN_Pos (9UL) /*!< FFSYNCCLREN (Bit 9) */
+#define PDM3_SDSYNC_FFSYNCCLREN_Msk (0x200UL) /*!< FFSYNCCLREN (Bitfield-Mask: 0x01) */
+#define PDM3_SDSYNC_WTSYNCLR_Pos (8UL) /*!< WTSYNCLR (Bit 8) */
+#define PDM3_SDSYNC_WTSYNCLR_Msk (0x100UL) /*!< WTSYNCLR (Bitfield-Mask: 0x01) */
+#define PDM3_SDSYNC_WTSYNFLG_Pos (7UL) /*!< WTSYNFLG (Bit 7) */
+#define PDM3_SDSYNC_WTSYNFLG_Msk (0x80UL) /*!< WTSYNFLG (Bitfield-Mask: 0x01) */
+#define PDM3_SDSYNC_WTSYNCEN_Pos (6UL) /*!< WTSYNCEN (Bit 6) */
+#define PDM3_SDSYNC_WTSYNCEN_Msk (0x40UL) /*!< WTSYNCEN (Bitfield-Mask: 0x01) */
+#define PDM3_SDSYNC_SYNCSEL_Pos (0UL) /*!< SYNCSEL (Bit 0) */
+#define PDM3_SDSYNC_SYNCSEL_Msk (0x3fUL) /*!< SYNCSEL (Bitfield-Mask: 0x3f) */
+/* ========================================================= IDAT ========================================================== */
+#define PDM3_IDAT_IDAT_Pos (0UL) /*!< IDAT (Bit 0) */
+#define PDM3_IDAT_IDAT_Msk (0xffffUL) /*!< IDAT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IWDG ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= KEYR ========================================================== */
+#define IWDG_KEYR_KEY_Pos (0UL) /*!< KEY (Bit 0) */
+#define IWDG_KEYR_KEY_Msk (0xffffUL) /*!< KEY (Bitfield-Mask: 0xffff) */
+/* ========================================================== CR =========================================================== */
+#define IWDG_CR_TOIE_Pos (1UL) /*!< TOIE (Bit 1) */
+#define IWDG_CR_TOIE_Msk (0x2UL) /*!< TOIE (Bitfield-Mask: 0x01) */
+#define IWDG_CR_MODE_Pos (0UL) /*!< MODE (Bit 0) */
+#define IWDG_CR_MODE_Msk (0x1UL) /*!< MODE (Bitfield-Mask: 0x01) */
+/* ========================================================== RLR ========================================================== */
+#define IWDG_RLR_RLV_Pos (0UL) /*!< RLV (Bit 0) */
+#define IWDG_RLR_RLV_Msk (0xffffUL) /*!< RLV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define IWDG_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define IWDG_PSCR_PSC_Msk (0x7UL) /*!< PSC (Bitfield-Mask: 0x07) */
+/* ========================================================== SR =========================================================== */
+#define IWDG_SR_TOIF_Pos (2UL) /*!< TOIF (Bit 2) */
+#define IWDG_SR_TOIF_Msk (0x4UL) /*!< TOIF (Bitfield-Mask: 0x01) */
+#define IWDG_SR_RLVUPD_Pos (1UL) /*!< RLVUPD (Bit 1) */
+#define IWDG_SR_RLVUPD_Msk (0x2UL) /*!< RLVUPD (Bitfield-Mask: 0x01) */
+#define IWDG_SR_PSCUPD_Pos (0UL) /*!< PSCUPD (Bit 0) */
+#define IWDG_SR_PSCUPD_Msk (0x1UL) /*!< PSCUPD (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR0_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR0_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR0_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR0_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR0_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR0_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR0_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR0_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR0_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR0_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR0_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR0_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR0_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR0_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR0_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR0_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR0_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR0_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR0_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR0_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR0_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR0_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR0_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR0_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR0_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR0_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR0_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR0_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR0_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR0_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR0_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR0_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR0_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR0_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR0_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR0_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR0_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR0_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR0_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR0_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR0_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR0_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR0_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR0_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR1_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR1_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR1_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR1_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR1_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR1_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR1_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR1_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR1_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR1_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR1_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR1_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR1_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR1_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR1_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR1_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR1_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR1_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR1_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR1_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR1_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR1_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR1_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR1_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR1_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR1_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR1_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR1_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR1_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR1_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR1_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR1_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR1_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR1_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR1_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR1_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR1_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR1_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR1_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR1_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR1_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR1_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR1_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR1_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR2_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR2_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR2_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR2_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR2_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR2_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR2_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR2_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR2_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR2_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR2_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR2_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR2_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR2_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR2_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR2_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR2_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR2_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR2_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR2_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR2_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR2_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR2_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR2_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR2_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR2_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR2_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR2_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR2_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR2_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR2_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR2_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR2_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR2_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR2_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR2_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR2_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR2_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR2_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR2_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR2_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR2_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR2_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR2_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR3_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR3_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR3_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR3_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR3_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR3_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR3_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR3_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR3_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR3_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR3_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR3_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR3_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR3_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR3_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR3_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR3_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR3_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR3_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR3_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR3_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR3_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR3_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR3_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR3_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR3_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR3_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR3_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR3_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR3_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR3_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR3_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR3_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR3_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR3_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR3_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR3_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR3_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR3_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR3_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR3_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR3_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR3_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR3_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR4_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR4_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR4_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR4_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR4_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR4_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR4_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR4_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR4_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR4_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR4_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR4_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR4_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR4_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR4_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR4_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR4_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR4_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR4_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR4_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR4_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR4_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR4_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR4_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR4_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR4_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR4_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR4_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR4_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR4_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR4_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR4_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR4_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR4_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR4_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR4_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR4_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR4_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR4_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR4_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR4_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR4_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR4_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR4_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ IIR5 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define IIR5_CR_RST_Pos (8UL) /*!< RST (Bit 8) */
+#define IIR5_CR_RST_Msk (0x100UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define IIR5_CR_IEE_Pos (7UL) /*!< IEE (Bit 7) */
+#define IIR5_CR_IEE_Msk (0x80UL) /*!< IEE (Bitfield-Mask: 0x01) */
+#define IIR5_CR_ORD_Pos (2UL) /*!< ORD (Bit 2) */
+#define IIR5_CR_ORD_Msk (0xcUL) /*!< ORD (Bitfield-Mask: 0x03) */
+#define IIR5_CR_IEN_Pos (0UL) /*!< IEN (Bit 0) */
+#define IIR5_CR_IEN_Msk (0x1UL) /*!< IEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define IIR5_ISR_BSY_Pos (1UL) /*!< BSY (Bit 1) */
+#define IIR5_ISR_BSY_Msk (0x2UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define IIR5_ISR_ERR_Pos (0UL) /*!< ERR (Bit 0) */
+#define IIR5_ISR_ERR_Msk (0x1UL) /*!< ERR (Bitfield-Mask: 0x01) */
+/* ========================================================== IDR ========================================================== */
+#define IIR5_IDR_ID_Pos (0UL) /*!< ID (Bit 0) */
+#define IIR5_IDR_ID_Msk (0xffffUL) /*!< ID (Bitfield-Mask: 0xffff) */
+/* ========================================================== ODR ========================================================== */
+#define IIR5_ODR_OD_Pos (0UL) /*!< OD (Bit 0) */
+#define IIR5_ODR_OD_Msk (0xffffUL) /*!< OD (Bitfield-Mask: 0xffff) */
+/* ========================================================== SCL ========================================================== */
+#define IIR5_SCL_OSCL1_Pos (24UL) /*!< OSCL1 (Bit 24) */
+#define IIR5_SCL_OSCL1_Msk (0x1f000000UL) /*!< OSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR5_SCL_FSCL1_Pos (16UL) /*!< FSCL1 (Bit 16) */
+#define IIR5_SCL_FSCL1_Msk (0x1f0000UL) /*!< FSCL1 (Bitfield-Mask: 0x1f) */
+#define IIR5_SCL_OSCL0_Pos (8UL) /*!< OSCL0 (Bit 8) */
+#define IIR5_SCL_OSCL0_Msk (0x1f00UL) /*!< OSCL0 (Bitfield-Mask: 0x1f) */
+#define IIR5_SCL_FSCL0_Pos (0UL) /*!< FSCL0 (Bit 0) */
+#define IIR5_SCL_FSCL0_Msk (0x1fUL) /*!< FSCL0 (Bitfield-Mask: 0x1f) */
+/* ========================================================= G0B0R ========================================================= */
+#define IIR5_G0B0R_G0B0COEF_Pos (0UL) /*!< G0B0COEF (Bit 0) */
+#define IIR5_G0B0R_G0B0COEF_Msk (0x7ffffffUL) /*!< G0B0COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B1R ========================================================= */
+#define IIR5_G0B1R_G0B1COEF_Pos (0UL) /*!< G0B1COEF (Bit 0) */
+#define IIR5_G0B1R_G0B1COEF_Msk (0x7ffffffUL) /*!< G0B1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B2R ========================================================= */
+#define IIR5_G0B2R_G0B2COEF_Pos (0UL) /*!< G0B2COEF (Bit 0) */
+#define IIR5_G0B2R_G0B2COEF_Msk (0x7ffffffUL) /*!< G0B2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B3R ========================================================= */
+#define IIR5_G0B3R_G0B3COEF_Pos (0UL) /*!< G0B3COEF (Bit 0) */
+#define IIR5_G0B3R_G0B3COEF_Msk (0x7ffffffUL) /*!< G0B3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B4R ========================================================= */
+#define IIR5_G0B4R_G0B4COEF_Pos (0UL) /*!< G0B4COEF (Bit 0) */
+#define IIR5_G0B4R_G0B4COEF_Msk (0x7ffffffUL) /*!< G0B4COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0B5R ========================================================= */
+#define IIR5_G0B5R_G0B5COEF_Pos (0UL) /*!< G0B5COEF (Bit 0) */
+#define IIR5_G0B5R_G0B5COEF_Msk (0x7ffffffUL) /*!< G0B5COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A1R ========================================================= */
+#define IIR5_G0A1R_G0A1COEF_Pos (0UL) /*!< G0A1COEF (Bit 0) */
+#define IIR5_G0A1R_G0A1COEF_Msk (0x7ffffffUL) /*!< G0A1COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A2R ========================================================= */
+#define IIR5_G0A2R_G0A2COEF_Pos (0UL) /*!< G0A2COEF (Bit 0) */
+#define IIR5_G0A2R_G0A2COEF_Msk (0x7ffffffUL) /*!< G0A2COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A3R ========================================================= */
+#define IIR5_G0A3R_G0A3COEF_Pos (0UL) /*!< G0A3COEF (Bit 0) */
+#define IIR5_G0A3R_G0A3COEF_Msk (0x7ffffffUL) /*!< G0A3COEF (Bitfield-Mask: 0x7ffffff) */
+/* ========================================================= G0A4R ========================================================= */
+#define IIR5_G0A4R_G0A4COEF_Pos (0UL) /*!< G0A4COEF (Bit 0) */
+#define IIR5_G0A4R_G0A4COEF_Msk (0x7ffffffUL) /*!< G0A4COEF (Bitfield-Mask: 0x7ffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ I2C0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define I2C0_ENABLE_HDRX_Pos (18UL) /*!< HDRX (Bit 18) */
+#define I2C0_ENABLE_HDRX_Msk (0xc0000UL) /*!< HDRX (Bitfield-Mask: 0x03) */
+#define I2C0_ENABLE_NSTCH_Pos (17UL) /*!< NSTCH (Bit 17) */
+#define I2C0_ENABLE_NSTCH_Msk (0x20000UL) /*!< NSTCH (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_MSTCH_Pos (16UL) /*!< MSTCH (Bit 16) */
+#define I2C0_ENABLE_MSTCH_Msk (0x10000UL) /*!< MSTCH (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_SMTOEN_Pos (15UL) /*!< SMTOEN (Bit 15) */
+#define I2C0_ENABLE_SMTOEN_Msk (0x8000UL) /*!< SMTOEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_SMHEN_Pos (14UL) /*!< SMHEN (Bit 14) */
+#define I2C0_ENABLE_SMHEN_Msk (0x4000UL) /*!< SMHEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_SMARPEN_Pos (13UL) /*!< SMARPEN (Bit 13) */
+#define I2C0_ENABLE_SMARPEN_Msk (0x2000UL) /*!< SMARPEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_SMALEN_Pos (12UL) /*!< SMALEN (Bit 12) */
+#define I2C0_ENABLE_SMALEN_Msk (0x1000UL) /*!< SMALEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_OSAEN_Pos (11UL) /*!< OSAEN (Bit 11) */
+#define I2C0_ENABLE_OSAEN_Msk (0x800UL) /*!< OSAEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_GCEN_Pos (10UL) /*!< GCEN (Bit 10) */
+#define I2C0_ENABLE_GCEN_Msk (0x400UL) /*!< GCEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_A10BEN_Pos (9UL) /*!< A10BEN (Bit 9) */
+#define I2C0_ENABLE_A10BEN_Msk (0x200UL) /*!< A10BEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_MSTEN_Pos (8UL) /*!< MSTEN (Bit 8) */
+#define I2C0_ENABLE_MSTEN_Msk (0x100UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_RFHSEN_Pos (7UL) /*!< RFHSEN (Bit 7) */
+#define I2C0_ENABLE_RFHSEN_Msk (0x80UL) /*!< RFHSEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_DMATXEN_Pos (6UL) /*!< DMATXEN (Bit 6) */
+#define I2C0_ENABLE_DMATXEN_Msk (0x40UL) /*!< DMATXEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_DMARXEN_Pos (5UL) /*!< DMARXEN (Bit 5) */
+#define I2C0_ENABLE_DMARXEN_Msk (0x20UL) /*!< DMARXEN (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_RLSCMD_Pos (4UL) /*!< RLSCMD (Bit 4) */
+#define I2C0_ENABLE_RLSCMD_Msk (0x10UL) /*!< RLSCMD (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_TFRST_Pos (3UL) /*!< TFRST (Bit 3) */
+#define I2C0_ENABLE_TFRST_Msk (0x8UL) /*!< TFRST (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_RFRST_Pos (2UL) /*!< RFRST (Bit 2) */
+#define I2C0_ENABLE_RFRST_Msk (0x4UL) /*!< RFRST (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_UDRCFG_Pos (1UL) /*!< UDRCFG (Bit 1) */
+#define I2C0_ENABLE_UDRCFG_Msk (0x2UL) /*!< UDRCFG (Bitfield-Mask: 0x01) */
+#define I2C0_ENABLE_I2CEN_Pos (0UL) /*!< I2CEN (Bit 0) */
+#define I2C0_ENABLE_I2CEN_Msk (0x1UL) /*!< I2CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define I2C0_CTRL_AUTOEND_Pos (14UL) /*!< AUTOEND (Bit 14) */
+#define I2C0_CTRL_AUTOEND_Msk (0x4000UL) /*!< AUTOEND (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_MODE10B_Pos (13UL) /*!< MODE10B (Bit 13) */
+#define I2C0_CTRL_MODE10B_Msk (0x2000UL) /*!< MODE10B (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_PECBYTE_Pos (12UL) /*!< PECBYTE (Bit 12) */
+#define I2C0_CTRL_PECBYTE_Msk (0x1000UL) /*!< PECBYTE (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_NACK_Pos (11UL) /*!< NACK (Bit 11) */
+#define I2C0_CTRL_NACK_Msk (0x800UL) /*!< NACK (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_START_Pos (10UL) /*!< START (Bit 10) */
+#define I2C0_CTRL_START_Msk (0x400UL) /*!< START (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_STOP_Pos (9UL) /*!< STOP (Bit 9) */
+#define I2C0_CTRL_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_DIRECT_Pos (8UL) /*!< DIRECT (Bit 8) */
+#define I2C0_CTRL_DIRECT_Msk (0x100UL) /*!< DIRECT (Bitfield-Mask: 0x01) */
+#define I2C0_CTRL_I2CCNT_Pos (0UL) /*!< I2CCNT (Bit 0) */
+#define I2C0_CTRL_I2CCNT_Msk (0xffUL) /*!< I2CCNT (Bitfield-Mask: 0xff) */
+/* ========================================================= BAUD ========================================================== */
+#define I2C0_BAUD_SCLHCNT_Pos (16UL) /*!< SCLHCNT (Bit 16) */
+#define I2C0_BAUD_SCLHCNT_Msk (0x3ff0000UL) /*!< SCLHCNT (Bitfield-Mask: 0x3ff) */
+#define I2C0_BAUD_SCLLCNT_Pos (0UL) /*!< SCLLCNT (Bit 0) */
+#define I2C0_BAUD_SCLLCNT_Msk (0x3ffUL) /*!< SCLLCNT (Bitfield-Mask: 0x3ff) */
+/* ========================================================= UDRDR ========================================================= */
+#define I2C0_UDRDR_UDRDR_Pos (0UL) /*!< UDRDR (Bit 0) */
+#define I2C0_UDRDR_UDRDR_Msk (0xffUL) /*!< UDRDR (Bitfield-Mask: 0xff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define I2C0_FIFOCTRL_RXFTLR_Pos (4UL) /*!< RXFTLR (Bit 4) */
+#define I2C0_FIFOCTRL_RXFTLR_Msk (0xf0UL) /*!< RXFTLR (Bitfield-Mask: 0x0f) */
+#define I2C0_FIFOCTRL_TXFTLR_Pos (0UL) /*!< TXFTLR (Bit 0) */
+#define I2C0_FIFOCTRL_TXFTLR_Msk (0xfUL) /*!< TXFTLR (Bitfield-Mask: 0x0f) */
+/* ========================================================== TAR ========================================================== */
+#define I2C0_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define I2C0_TAR_TAR_Msk (0x3ffUL) /*!< TAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== SAR ========================================================== */
+#define I2C0_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define I2C0_SAR_SAR_Msk (0x3ffUL) /*!< SAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================= OSAR ========================================================== */
+#define I2C0_OSAR_OSAM_Pos (16UL) /*!< OSAM (Bit 16) */
+#define I2C0_OSAR_OSAM_Msk (0x3ff0000UL) /*!< OSAM (Bitfield-Mask: 0x3ff) */
+#define I2C0_OSAR_OSAR_Pos (0UL) /*!< OSAR (Bit 0) */
+#define I2C0_OSAR_OSAR_Msk (0x3ffUL) /*!< OSAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== PEC ========================================================== */
+#define I2C0_PEC_IDPEC_Pos (8UL) /*!< IDPEC (Bit 8) */
+#define I2C0_PEC_IDPEC_Msk (0xff00UL) /*!< IDPEC (Bitfield-Mask: 0xff) */
+#define I2C0_PEC_RXPEC_Pos (0UL) /*!< RXPEC (Bit 0) */
+#define I2C0_PEC_RXPEC_Msk (0xffUL) /*!< RXPEC (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMING ========================================================= */
+#define I2C0_TIMING_SPKLEN_Pos (24UL) /*!< SPKLEN (Bit 24) */
+#define I2C0_TIMING_SPKLEN_Msk (0xff000000UL) /*!< SPKLEN (Bitfield-Mask: 0xff) */
+#define I2C0_TIMING_SLVSUDAT_Pos (16UL) /*!< SLVSUDAT (Bit 16) */
+#define I2C0_TIMING_SLVSUDAT_Msk (0xff0000UL) /*!< SLVSUDAT (Bitfield-Mask: 0xff) */
+#define I2C0_TIMING_SUDAT_Pos (8UL) /*!< SUDAT (Bit 8) */
+#define I2C0_TIMING_SUDAT_Msk (0xff00UL) /*!< SUDAT (Bitfield-Mask: 0xff) */
+#define I2C0_TIMING_HDDAT_Pos (0UL) /*!< HDDAT (Bit 0) */
+#define I2C0_TIMING_HDDAT_Msk (0xffUL) /*!< HDDAT (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMEOUT ======================================================== */
+#define I2C0_TIMEOUT_SEXTTO_Pos (16UL) /*!< SEXTTO (Bit 16) */
+#define I2C0_TIMEOUT_SEXTTO_Msk (0xffff0000UL) /*!< SEXTTO (Bitfield-Mask: 0xffff) */
+#define I2C0_TIMEOUT_MEXTTO_Pos (0UL) /*!< MEXTTO (Bit 0) */
+#define I2C0_TIMEOUT_MEXTTO_Msk (0xffffUL) /*!< MEXTTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== BUSTOUT ======================================================== */
+#define I2C0_BUSTOUT_TOSEL_Pos (31UL) /*!< TOSEL (Bit 31) */
+#define I2C0_BUSTOUT_TOSEL_Msk (0x80000000UL) /*!< TOSEL (Bitfield-Mask: 0x01) */
+#define I2C0_BUSTOUT_BTO_Pos (0UL) /*!< BTO (Bit 0) */
+#define I2C0_BUSTOUT_BTO_Msk (0xffffUL) /*!< BTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== INTREN ========================================================= */
+#define I2C0_INTREN_BTOIE_Pos (23UL) /*!< BTOIE (Bit 23) */
+#define I2C0_INTREN_BTOIE_Msk (0x800000UL) /*!< BTOIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_MOHIE_Pos (22UL) /*!< MOHIE (Bit 22) */
+#define I2C0_INTREN_MOHIE_Msk (0x400000UL) /*!< MOHIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_SWTXIE_Pos (21UL) /*!< SWTXIE (Bit 21) */
+#define I2C0_INTREN_SWTXIE_Msk (0x200000UL) /*!< SWTXIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_MTXAIE_Pos (20UL) /*!< MTXAIE (Bit 20) */
+#define I2C0_INTREN_MTXAIE_Msk (0x100000UL) /*!< MTXAIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RXGCIE_Pos (19UL) /*!< RXGCIE (Bit 19) */
+#define I2C0_INTREN_RXGCIE_Msk (0x80000UL) /*!< RXGCIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_PECRXIE_Pos (18UL) /*!< PECRXIE (Bit 18) */
+#define I2C0_INTREN_PECRXIE_Msk (0x40000UL) /*!< PECRXIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_SEXTOIE_Pos (17UL) /*!< SEXTOIE (Bit 17) */
+#define I2C0_INTREN_SEXTOIE_Msk (0x20000UL) /*!< SEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_MEXTOIE_Pos (16UL) /*!< MEXTOIE (Bit 16) */
+#define I2C0_INTREN_MEXTOIE_Msk (0x10000UL) /*!< MEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_ALDETIE_Pos (15UL) /*!< ALDETIE (Bit 15) */
+#define I2C0_INTREN_ALDETIE_Msk (0x8000UL) /*!< ALDETIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_NACKIE_Pos (14UL) /*!< NACKIE (Bit 14) */
+#define I2C0_INTREN_NACKIE_Msk (0x4000UL) /*!< NACKIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RSDETIE_Pos (13UL) /*!< RSDETIE (Bit 13) */
+#define I2C0_INTREN_RSDETIE_Msk (0x2000UL) /*!< RSDETIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_SPDETIE_Pos (12UL) /*!< SPDETIE (Bit 12) */
+#define I2C0_INTREN_SPDETIE_Msk (0x1000UL) /*!< SPDETIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_STDETIE_Pos (11UL) /*!< STDETIE (Bit 11) */
+#define I2C0_INTREN_STDETIE_Msk (0x800UL) /*!< STDETIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RXADIE_Pos (10UL) /*!< RXADIE (Bit 10) */
+#define I2C0_INTREN_RXADIE_Msk (0x400UL) /*!< RXADIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_TXADIE_Pos (9UL) /*!< TXADIE (Bit 9) */
+#define I2C0_INTREN_TXADIE_Msk (0x200UL) /*!< TXADIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_MDEIE_Pos (8UL) /*!< MDEIE (Bit 8) */
+#define I2C0_INTREN_MDEIE_Msk (0x100UL) /*!< MDEIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_BUSEIE_Pos (7UL) /*!< BUSEIE (Bit 7) */
+#define I2C0_INTREN_BUSEIE_Msk (0x80UL) /*!< BUSEIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_ARBFIE_Pos (6UL) /*!< ARBFIE (Bit 6) */
+#define I2C0_INTREN_ARBFIE_Msk (0x40UL) /*!< ARBFIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_TXUFIE_Pos (5UL) /*!< TXUFIE (Bit 5) */
+#define I2C0_INTREN_TXUFIE_Msk (0x20UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_TXOFIE_Pos (4UL) /*!< TXOFIE (Bit 4) */
+#define I2C0_INTREN_TXOFIE_Msk (0x10UL) /*!< TXOFIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RXUFIE_Pos (3UL) /*!< RXUFIE (Bit 3) */
+#define I2C0_INTREN_RXUFIE_Msk (0x8UL) /*!< RXUFIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RXOFIE_Pos (2UL) /*!< RXOFIE (Bit 2) */
+#define I2C0_INTREN_RXOFIE_Msk (0x4UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_TXEIE_Pos (1UL) /*!< TXEIE (Bit 1) */
+#define I2C0_INTREN_TXEIE_Msk (0x2UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define I2C0_INTREN_RXFIE_Pos (0UL) /*!< RXFIE (Bit 0) */
+#define I2C0_INTREN_RXFIE_Msk (0x1UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+/* ========================================================= INTR ========================================================== */
+#define I2C0_INTR_RCNT_Pos (24UL) /*!< RCNT (Bit 24) */
+#define I2C0_INTR_RCNT_Msk (0xff000000UL) /*!< RCNT (Bitfield-Mask: 0xff) */
+#define I2C0_INTR_BTOI_Pos (23UL) /*!< BTOI (Bit 23) */
+#define I2C0_INTR_BTOI_Msk (0x800000UL) /*!< BTOI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_MOHI_Pos (22UL) /*!< MOHI (Bit 22) */
+#define I2C0_INTR_MOHI_Msk (0x400000UL) /*!< MOHI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_SWTXI_Pos (21UL) /*!< SWTXI (Bit 21) */
+#define I2C0_INTR_SWTXI_Msk (0x200000UL) /*!< SWTXI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_MTXAI_Pos (20UL) /*!< MTXAI (Bit 20) */
+#define I2C0_INTR_MTXAI_Msk (0x100000UL) /*!< MTXAI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RXGCI_Pos (19UL) /*!< RXGCI (Bit 19) */
+#define I2C0_INTR_RXGCI_Msk (0x80000UL) /*!< RXGCI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_PECRXI_Pos (18UL) /*!< PECRXI (Bit 18) */
+#define I2C0_INTR_PECRXI_Msk (0x40000UL) /*!< PECRXI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_SEXTOI_Pos (17UL) /*!< SEXTOI (Bit 17) */
+#define I2C0_INTR_SEXTOI_Msk (0x20000UL) /*!< SEXTOI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_MEXTOI_Pos (16UL) /*!< MEXTOI (Bit 16) */
+#define I2C0_INTR_MEXTOI_Msk (0x10000UL) /*!< MEXTOI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_ALDETI_Pos (15UL) /*!< ALDETI (Bit 15) */
+#define I2C0_INTR_ALDETI_Msk (0x8000UL) /*!< ALDETI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_NACKI_Pos (14UL) /*!< NACKI (Bit 14) */
+#define I2C0_INTR_NACKI_Msk (0x4000UL) /*!< NACKI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RSDETI_Pos (13UL) /*!< RSDETI (Bit 13) */
+#define I2C0_INTR_RSDETI_Msk (0x2000UL) /*!< RSDETI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_SPETI_Pos (12UL) /*!< SPETI (Bit 12) */
+#define I2C0_INTR_SPETI_Msk (0x1000UL) /*!< SPETI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_STDETI_Pos (11UL) /*!< STDETI (Bit 11) */
+#define I2C0_INTR_STDETI_Msk (0x800UL) /*!< STDETI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RXADI_Pos (10UL) /*!< RXADI (Bit 10) */
+#define I2C0_INTR_RXADI_Msk (0x400UL) /*!< RXADI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_TXADI_Pos (9UL) /*!< TXADI (Bit 9) */
+#define I2C0_INTR_TXADI_Msk (0x200UL) /*!< TXADI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_MDEI_Pos (8UL) /*!< MDEI (Bit 8) */
+#define I2C0_INTR_MDEI_Msk (0x100UL) /*!< MDEI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_BUSEI_Pos (7UL) /*!< BUSEI (Bit 7) */
+#define I2C0_INTR_BUSEI_Msk (0x80UL) /*!< BUSEI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_ARBFI_Pos (6UL) /*!< ARBFI (Bit 6) */
+#define I2C0_INTR_ARBFI_Msk (0x40UL) /*!< ARBFI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_TXUFI_Pos (5UL) /*!< TXUFI (Bit 5) */
+#define I2C0_INTR_TXUFI_Msk (0x20UL) /*!< TXUFI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_TXOFI_Pos (4UL) /*!< TXOFI (Bit 4) */
+#define I2C0_INTR_TXOFI_Msk (0x10UL) /*!< TXOFI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RXUFI_Pos (3UL) /*!< RXUFI (Bit 3) */
+#define I2C0_INTR_RXUFI_Msk (0x8UL) /*!< RXUFI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RXOFI_Pos (2UL) /*!< RXOFI (Bit 2) */
+#define I2C0_INTR_RXOFI_Msk (0x4UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define I2C0_INTR_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define I2C0_INTR_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define I2C0_INTR_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define I2C0_STATUS_RFF_Pos (30UL) /*!< RFF (Bit 30) */
+#define I2C0_STATUS_RFF_Msk (0x40000000UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define I2C0_STATUS_RFE_Pos (29UL) /*!< RFE (Bit 29) */
+#define I2C0_STATUS_RFE_Msk (0x20000000UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define I2C0_STATUS_RXFLR_Pos (24UL) /*!< RXFLR (Bit 24) */
+#define I2C0_STATUS_RXFLR_Msk (0x1f000000UL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
+#define I2C0_STATUS_TFF_Pos (22UL) /*!< TFF (Bit 22) */
+#define I2C0_STATUS_TFF_Msk (0x400000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define I2C0_STATUS_TFE_Pos (21UL) /*!< TFE (Bit 21) */
+#define I2C0_STATUS_TFE_Msk (0x200000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define I2C0_STATUS_TXFLR_Pos (16UL) /*!< TXFLR (Bit 16) */
+#define I2C0_STATUS_TXFLR_Msk (0x1f0000UL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
+#define I2C0_STATUS_ARBSTA_Pos (2UL) /*!< ARBSTA (Bit 2) */
+#define I2C0_STATUS_ARBSTA_Msk (0xcUL) /*!< ARBSTA (Bitfield-Mask: 0x03) */
+#define I2C0_STATUS_BUSBSY_Pos (1UL) /*!< BUSBSY (Bit 1) */
+#define I2C0_STATUS_BUSBSY_Msk (0x2UL) /*!< BUSBSY (Bitfield-Mask: 0x01) */
+#define I2C0_STATUS_FSMBSY_Pos (0UL) /*!< FSMBSY (Bit 0) */
+#define I2C0_STATUS_FSMBSY_Msk (0x1UL) /*!< FSMBSY (Bitfield-Mask: 0x01) */
+/* ======================================================== TXDATA ========================================================= */
+#define I2C0_TXDATA_TXDATA_Pos (0UL) /*!< TXDATA (Bit 0) */
+#define I2C0_TXDATA_TXDATA_Msk (0xffUL) /*!< TXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXDATA ========================================================= */
+#define I2C0_RXDATA_RXDATA_Pos (0UL) /*!< RXDATA (Bit 0) */
+#define I2C0_RXDATA_RXDATA_Msk (0xffUL) /*!< RXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXADDR ========================================================= */
+#define I2C0_RXADDR_ADDR_Pos (1UL) /*!< ADDR (Bit 1) */
+#define I2C0_RXADDR_ADDR_Msk (0xfeUL) /*!< ADDR (Bitfield-Mask: 0x7f) */
+#define I2C0_RXADDR_DIR_Pos (0UL) /*!< DIR (Bit 0) */
+#define I2C0_RXADDR_DIR_Msk (0x1UL) /*!< DIR (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ I2C1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define I2C1_ENABLE_HDRX_Pos (18UL) /*!< HDRX (Bit 18) */
+#define I2C1_ENABLE_HDRX_Msk (0xc0000UL) /*!< HDRX (Bitfield-Mask: 0x03) */
+#define I2C1_ENABLE_NSTCH_Pos (17UL) /*!< NSTCH (Bit 17) */
+#define I2C1_ENABLE_NSTCH_Msk (0x20000UL) /*!< NSTCH (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_MSTCH_Pos (16UL) /*!< MSTCH (Bit 16) */
+#define I2C1_ENABLE_MSTCH_Msk (0x10000UL) /*!< MSTCH (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_SMTOEN_Pos (15UL) /*!< SMTOEN (Bit 15) */
+#define I2C1_ENABLE_SMTOEN_Msk (0x8000UL) /*!< SMTOEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_SMHEN_Pos (14UL) /*!< SMHEN (Bit 14) */
+#define I2C1_ENABLE_SMHEN_Msk (0x4000UL) /*!< SMHEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_SMARPEN_Pos (13UL) /*!< SMARPEN (Bit 13) */
+#define I2C1_ENABLE_SMARPEN_Msk (0x2000UL) /*!< SMARPEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_SMALEN_Pos (12UL) /*!< SMALEN (Bit 12) */
+#define I2C1_ENABLE_SMALEN_Msk (0x1000UL) /*!< SMALEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_OSAEN_Pos (11UL) /*!< OSAEN (Bit 11) */
+#define I2C1_ENABLE_OSAEN_Msk (0x800UL) /*!< OSAEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_GCEN_Pos (10UL) /*!< GCEN (Bit 10) */
+#define I2C1_ENABLE_GCEN_Msk (0x400UL) /*!< GCEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_A10BEN_Pos (9UL) /*!< A10BEN (Bit 9) */
+#define I2C1_ENABLE_A10BEN_Msk (0x200UL) /*!< A10BEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_MSTEN_Pos (8UL) /*!< MSTEN (Bit 8) */
+#define I2C1_ENABLE_MSTEN_Msk (0x100UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_RFHSEN_Pos (7UL) /*!< RFHSEN (Bit 7) */
+#define I2C1_ENABLE_RFHSEN_Msk (0x80UL) /*!< RFHSEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_DMATXEN_Pos (6UL) /*!< DMATXEN (Bit 6) */
+#define I2C1_ENABLE_DMATXEN_Msk (0x40UL) /*!< DMATXEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_DMARXEN_Pos (5UL) /*!< DMARXEN (Bit 5) */
+#define I2C1_ENABLE_DMARXEN_Msk (0x20UL) /*!< DMARXEN (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_RLSCMD_Pos (4UL) /*!< RLSCMD (Bit 4) */
+#define I2C1_ENABLE_RLSCMD_Msk (0x10UL) /*!< RLSCMD (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_TFRST_Pos (3UL) /*!< TFRST (Bit 3) */
+#define I2C1_ENABLE_TFRST_Msk (0x8UL) /*!< TFRST (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_RFRST_Pos (2UL) /*!< RFRST (Bit 2) */
+#define I2C1_ENABLE_RFRST_Msk (0x4UL) /*!< RFRST (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_UDRCFG_Pos (1UL) /*!< UDRCFG (Bit 1) */
+#define I2C1_ENABLE_UDRCFG_Msk (0x2UL) /*!< UDRCFG (Bitfield-Mask: 0x01) */
+#define I2C1_ENABLE_I2CEN_Pos (0UL) /*!< I2CEN (Bit 0) */
+#define I2C1_ENABLE_I2CEN_Msk (0x1UL) /*!< I2CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define I2C1_CTRL_AUTOEND_Pos (14UL) /*!< AUTOEND (Bit 14) */
+#define I2C1_CTRL_AUTOEND_Msk (0x4000UL) /*!< AUTOEND (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_MODE10B_Pos (13UL) /*!< MODE10B (Bit 13) */
+#define I2C1_CTRL_MODE10B_Msk (0x2000UL) /*!< MODE10B (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_PECBYTE_Pos (12UL) /*!< PECBYTE (Bit 12) */
+#define I2C1_CTRL_PECBYTE_Msk (0x1000UL) /*!< PECBYTE (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_NACK_Pos (11UL) /*!< NACK (Bit 11) */
+#define I2C1_CTRL_NACK_Msk (0x800UL) /*!< NACK (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_START_Pos (10UL) /*!< START (Bit 10) */
+#define I2C1_CTRL_START_Msk (0x400UL) /*!< START (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_STOP_Pos (9UL) /*!< STOP (Bit 9) */
+#define I2C1_CTRL_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_DIRECT_Pos (8UL) /*!< DIRECT (Bit 8) */
+#define I2C1_CTRL_DIRECT_Msk (0x100UL) /*!< DIRECT (Bitfield-Mask: 0x01) */
+#define I2C1_CTRL_I2CCNT_Pos (0UL) /*!< I2CCNT (Bit 0) */
+#define I2C1_CTRL_I2CCNT_Msk (0xffUL) /*!< I2CCNT (Bitfield-Mask: 0xff) */
+/* ========================================================= BAUD ========================================================== */
+#define I2C1_BAUD_SCLHCNT_Pos (16UL) /*!< SCLHCNT (Bit 16) */
+#define I2C1_BAUD_SCLHCNT_Msk (0x3ff0000UL) /*!< SCLHCNT (Bitfield-Mask: 0x3ff) */
+#define I2C1_BAUD_SCLLCNT_Pos (0UL) /*!< SCLLCNT (Bit 0) */
+#define I2C1_BAUD_SCLLCNT_Msk (0x3ffUL) /*!< SCLLCNT (Bitfield-Mask: 0x3ff) */
+/* ========================================================= UDRDR ========================================================= */
+#define I2C1_UDRDR_UDRDR_Pos (0UL) /*!< UDRDR (Bit 0) */
+#define I2C1_UDRDR_UDRDR_Msk (0xffUL) /*!< UDRDR (Bitfield-Mask: 0xff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define I2C1_FIFOCTRL_RXFTLR_Pos (4UL) /*!< RXFTLR (Bit 4) */
+#define I2C1_FIFOCTRL_RXFTLR_Msk (0xf0UL) /*!< RXFTLR (Bitfield-Mask: 0x0f) */
+#define I2C1_FIFOCTRL_TXFTLR_Pos (0UL) /*!< TXFTLR (Bit 0) */
+#define I2C1_FIFOCTRL_TXFTLR_Msk (0xfUL) /*!< TXFTLR (Bitfield-Mask: 0x0f) */
+/* ========================================================== TAR ========================================================== */
+#define I2C1_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define I2C1_TAR_TAR_Msk (0x3ffUL) /*!< TAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== SAR ========================================================== */
+#define I2C1_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define I2C1_SAR_SAR_Msk (0x3ffUL) /*!< SAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================= OSAR ========================================================== */
+#define I2C1_OSAR_OSAM_Pos (16UL) /*!< OSAM (Bit 16) */
+#define I2C1_OSAR_OSAM_Msk (0x3ff0000UL) /*!< OSAM (Bitfield-Mask: 0x3ff) */
+#define I2C1_OSAR_OSAR_Pos (0UL) /*!< OSAR (Bit 0) */
+#define I2C1_OSAR_OSAR_Msk (0x3ffUL) /*!< OSAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== PEC ========================================================== */
+#define I2C1_PEC_IDPEC_Pos (8UL) /*!< IDPEC (Bit 8) */
+#define I2C1_PEC_IDPEC_Msk (0xff00UL) /*!< IDPEC (Bitfield-Mask: 0xff) */
+#define I2C1_PEC_RXPEC_Pos (0UL) /*!< RXPEC (Bit 0) */
+#define I2C1_PEC_RXPEC_Msk (0xffUL) /*!< RXPEC (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMING ========================================================= */
+#define I2C1_TIMING_SPKLEN_Pos (24UL) /*!< SPKLEN (Bit 24) */
+#define I2C1_TIMING_SPKLEN_Msk (0xff000000UL) /*!< SPKLEN (Bitfield-Mask: 0xff) */
+#define I2C1_TIMING_SLVSUDAT_Pos (16UL) /*!< SLVSUDAT (Bit 16) */
+#define I2C1_TIMING_SLVSUDAT_Msk (0xff0000UL) /*!< SLVSUDAT (Bitfield-Mask: 0xff) */
+#define I2C1_TIMING_SUDAT_Pos (8UL) /*!< SUDAT (Bit 8) */
+#define I2C1_TIMING_SUDAT_Msk (0xff00UL) /*!< SUDAT (Bitfield-Mask: 0xff) */
+#define I2C1_TIMING_HDDAT_Pos (0UL) /*!< HDDAT (Bit 0) */
+#define I2C1_TIMING_HDDAT_Msk (0xffUL) /*!< HDDAT (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMEOUT ======================================================== */
+#define I2C1_TIMEOUT_SEXTTO_Pos (16UL) /*!< SEXTTO (Bit 16) */
+#define I2C1_TIMEOUT_SEXTTO_Msk (0xffff0000UL) /*!< SEXTTO (Bitfield-Mask: 0xffff) */
+#define I2C1_TIMEOUT_MEXTTO_Pos (0UL) /*!< MEXTTO (Bit 0) */
+#define I2C1_TIMEOUT_MEXTTO_Msk (0xffffUL) /*!< MEXTTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== BUSTOUT ======================================================== */
+#define I2C1_BUSTOUT_TOSEL_Pos (31UL) /*!< TOSEL (Bit 31) */
+#define I2C1_BUSTOUT_TOSEL_Msk (0x80000000UL) /*!< TOSEL (Bitfield-Mask: 0x01) */
+#define I2C1_BUSTOUT_BTO_Pos (0UL) /*!< BTO (Bit 0) */
+#define I2C1_BUSTOUT_BTO_Msk (0xffffUL) /*!< BTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== INTREN ========================================================= */
+#define I2C1_INTREN_BTOIE_Pos (23UL) /*!< BTOIE (Bit 23) */
+#define I2C1_INTREN_BTOIE_Msk (0x800000UL) /*!< BTOIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_MOHIE_Pos (22UL) /*!< MOHIE (Bit 22) */
+#define I2C1_INTREN_MOHIE_Msk (0x400000UL) /*!< MOHIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_SWTXIE_Pos (21UL) /*!< SWTXIE (Bit 21) */
+#define I2C1_INTREN_SWTXIE_Msk (0x200000UL) /*!< SWTXIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_MTXAIE_Pos (20UL) /*!< MTXAIE (Bit 20) */
+#define I2C1_INTREN_MTXAIE_Msk (0x100000UL) /*!< MTXAIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RXGCIE_Pos (19UL) /*!< RXGCIE (Bit 19) */
+#define I2C1_INTREN_RXGCIE_Msk (0x80000UL) /*!< RXGCIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_PECRXIE_Pos (18UL) /*!< PECRXIE (Bit 18) */
+#define I2C1_INTREN_PECRXIE_Msk (0x40000UL) /*!< PECRXIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_SEXTOIE_Pos (17UL) /*!< SEXTOIE (Bit 17) */
+#define I2C1_INTREN_SEXTOIE_Msk (0x20000UL) /*!< SEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_MEXTOIE_Pos (16UL) /*!< MEXTOIE (Bit 16) */
+#define I2C1_INTREN_MEXTOIE_Msk (0x10000UL) /*!< MEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_ALDETIE_Pos (15UL) /*!< ALDETIE (Bit 15) */
+#define I2C1_INTREN_ALDETIE_Msk (0x8000UL) /*!< ALDETIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_NACKIE_Pos (14UL) /*!< NACKIE (Bit 14) */
+#define I2C1_INTREN_NACKIE_Msk (0x4000UL) /*!< NACKIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RSDETIE_Pos (13UL) /*!< RSDETIE (Bit 13) */
+#define I2C1_INTREN_RSDETIE_Msk (0x2000UL) /*!< RSDETIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_SPDETIE_Pos (12UL) /*!< SPDETIE (Bit 12) */
+#define I2C1_INTREN_SPDETIE_Msk (0x1000UL) /*!< SPDETIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_STDETIE_Pos (11UL) /*!< STDETIE (Bit 11) */
+#define I2C1_INTREN_STDETIE_Msk (0x800UL) /*!< STDETIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RXADIE_Pos (10UL) /*!< RXADIE (Bit 10) */
+#define I2C1_INTREN_RXADIE_Msk (0x400UL) /*!< RXADIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_TXADIE_Pos (9UL) /*!< TXADIE (Bit 9) */
+#define I2C1_INTREN_TXADIE_Msk (0x200UL) /*!< TXADIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_MDEIE_Pos (8UL) /*!< MDEIE (Bit 8) */
+#define I2C1_INTREN_MDEIE_Msk (0x100UL) /*!< MDEIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_BUSEIE_Pos (7UL) /*!< BUSEIE (Bit 7) */
+#define I2C1_INTREN_BUSEIE_Msk (0x80UL) /*!< BUSEIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_ARBFIE_Pos (6UL) /*!< ARBFIE (Bit 6) */
+#define I2C1_INTREN_ARBFIE_Msk (0x40UL) /*!< ARBFIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_TXUFIE_Pos (5UL) /*!< TXUFIE (Bit 5) */
+#define I2C1_INTREN_TXUFIE_Msk (0x20UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_TXOFIE_Pos (4UL) /*!< TXOFIE (Bit 4) */
+#define I2C1_INTREN_TXOFIE_Msk (0x10UL) /*!< TXOFIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RXUFIE_Pos (3UL) /*!< RXUFIE (Bit 3) */
+#define I2C1_INTREN_RXUFIE_Msk (0x8UL) /*!< RXUFIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RXOFIE_Pos (2UL) /*!< RXOFIE (Bit 2) */
+#define I2C1_INTREN_RXOFIE_Msk (0x4UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_TXEIE_Pos (1UL) /*!< TXEIE (Bit 1) */
+#define I2C1_INTREN_TXEIE_Msk (0x2UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define I2C1_INTREN_RXFIE_Pos (0UL) /*!< RXFIE (Bit 0) */
+#define I2C1_INTREN_RXFIE_Msk (0x1UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+/* ========================================================= INTR ========================================================== */
+#define I2C1_INTR_RCNT_Pos (24UL) /*!< RCNT (Bit 24) */
+#define I2C1_INTR_RCNT_Msk (0xff000000UL) /*!< RCNT (Bitfield-Mask: 0xff) */
+#define I2C1_INTR_BTOI_Pos (23UL) /*!< BTOI (Bit 23) */
+#define I2C1_INTR_BTOI_Msk (0x800000UL) /*!< BTOI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_MOHI_Pos (22UL) /*!< MOHI (Bit 22) */
+#define I2C1_INTR_MOHI_Msk (0x400000UL) /*!< MOHI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_SWTXI_Pos (21UL) /*!< SWTXI (Bit 21) */
+#define I2C1_INTR_SWTXI_Msk (0x200000UL) /*!< SWTXI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_MTXAI_Pos (20UL) /*!< MTXAI (Bit 20) */
+#define I2C1_INTR_MTXAI_Msk (0x100000UL) /*!< MTXAI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RXGCI_Pos (19UL) /*!< RXGCI (Bit 19) */
+#define I2C1_INTR_RXGCI_Msk (0x80000UL) /*!< RXGCI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_PECRXI_Pos (18UL) /*!< PECRXI (Bit 18) */
+#define I2C1_INTR_PECRXI_Msk (0x40000UL) /*!< PECRXI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_SEXTOI_Pos (17UL) /*!< SEXTOI (Bit 17) */
+#define I2C1_INTR_SEXTOI_Msk (0x20000UL) /*!< SEXTOI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_MEXTOI_Pos (16UL) /*!< MEXTOI (Bit 16) */
+#define I2C1_INTR_MEXTOI_Msk (0x10000UL) /*!< MEXTOI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_ALDETI_Pos (15UL) /*!< ALDETI (Bit 15) */
+#define I2C1_INTR_ALDETI_Msk (0x8000UL) /*!< ALDETI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_NACKI_Pos (14UL) /*!< NACKI (Bit 14) */
+#define I2C1_INTR_NACKI_Msk (0x4000UL) /*!< NACKI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RSDETI_Pos (13UL) /*!< RSDETI (Bit 13) */
+#define I2C1_INTR_RSDETI_Msk (0x2000UL) /*!< RSDETI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_SPETI_Pos (12UL) /*!< SPETI (Bit 12) */
+#define I2C1_INTR_SPETI_Msk (0x1000UL) /*!< SPETI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_STDETI_Pos (11UL) /*!< STDETI (Bit 11) */
+#define I2C1_INTR_STDETI_Msk (0x800UL) /*!< STDETI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RXADI_Pos (10UL) /*!< RXADI (Bit 10) */
+#define I2C1_INTR_RXADI_Msk (0x400UL) /*!< RXADI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_TXADI_Pos (9UL) /*!< TXADI (Bit 9) */
+#define I2C1_INTR_TXADI_Msk (0x200UL) /*!< TXADI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_MDEI_Pos (8UL) /*!< MDEI (Bit 8) */
+#define I2C1_INTR_MDEI_Msk (0x100UL) /*!< MDEI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_BUSEI_Pos (7UL) /*!< BUSEI (Bit 7) */
+#define I2C1_INTR_BUSEI_Msk (0x80UL) /*!< BUSEI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_ARBFI_Pos (6UL) /*!< ARBFI (Bit 6) */
+#define I2C1_INTR_ARBFI_Msk (0x40UL) /*!< ARBFI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_TXUFI_Pos (5UL) /*!< TXUFI (Bit 5) */
+#define I2C1_INTR_TXUFI_Msk (0x20UL) /*!< TXUFI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_TXOFI_Pos (4UL) /*!< TXOFI (Bit 4) */
+#define I2C1_INTR_TXOFI_Msk (0x10UL) /*!< TXOFI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RXUFI_Pos (3UL) /*!< RXUFI (Bit 3) */
+#define I2C1_INTR_RXUFI_Msk (0x8UL) /*!< RXUFI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RXOFI_Pos (2UL) /*!< RXOFI (Bit 2) */
+#define I2C1_INTR_RXOFI_Msk (0x4UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define I2C1_INTR_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define I2C1_INTR_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define I2C1_INTR_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define I2C1_STATUS_RFF_Pos (30UL) /*!< RFF (Bit 30) */
+#define I2C1_STATUS_RFF_Msk (0x40000000UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define I2C1_STATUS_RFE_Pos (29UL) /*!< RFE (Bit 29) */
+#define I2C1_STATUS_RFE_Msk (0x20000000UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define I2C1_STATUS_RXFLR_Pos (24UL) /*!< RXFLR (Bit 24) */
+#define I2C1_STATUS_RXFLR_Msk (0x1f000000UL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
+#define I2C1_STATUS_TFF_Pos (22UL) /*!< TFF (Bit 22) */
+#define I2C1_STATUS_TFF_Msk (0x400000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define I2C1_STATUS_TFE_Pos (21UL) /*!< TFE (Bit 21) */
+#define I2C1_STATUS_TFE_Msk (0x200000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define I2C1_STATUS_TXFLR_Pos (16UL) /*!< TXFLR (Bit 16) */
+#define I2C1_STATUS_TXFLR_Msk (0x1f0000UL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
+#define I2C1_STATUS_ARBSTA_Pos (2UL) /*!< ARBSTA (Bit 2) */
+#define I2C1_STATUS_ARBSTA_Msk (0xcUL) /*!< ARBSTA (Bitfield-Mask: 0x03) */
+#define I2C1_STATUS_BUSBSY_Pos (1UL) /*!< BUSBSY (Bit 1) */
+#define I2C1_STATUS_BUSBSY_Msk (0x2UL) /*!< BUSBSY (Bitfield-Mask: 0x01) */
+#define I2C1_STATUS_FSMBSY_Pos (0UL) /*!< FSMBSY (Bit 0) */
+#define I2C1_STATUS_FSMBSY_Msk (0x1UL) /*!< FSMBSY (Bitfield-Mask: 0x01) */
+/* ======================================================== TXDATA ========================================================= */
+#define I2C1_TXDATA_TXDATA_Pos (0UL) /*!< TXDATA (Bit 0) */
+#define I2C1_TXDATA_TXDATA_Msk (0xffUL) /*!< TXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXDATA ========================================================= */
+#define I2C1_RXDATA_RXDATA_Pos (0UL) /*!< RXDATA (Bit 0) */
+#define I2C1_RXDATA_RXDATA_Msk (0xffUL) /*!< RXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXADDR ========================================================= */
+#define I2C1_RXADDR_ADDR_Pos (1UL) /*!< ADDR (Bit 1) */
+#define I2C1_RXADDR_ADDR_Msk (0xfeUL) /*!< ADDR (Bitfield-Mask: 0x7f) */
+#define I2C1_RXADDR_DIR_Pos (0UL) /*!< DIR (Bit 0) */
+#define I2C1_RXADDR_DIR_Msk (0x1UL) /*!< DIR (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ I2C2 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== ENABLE ========================================================= */
+#define I2C2_ENABLE_HDRX_Pos (18UL) /*!< HDRX (Bit 18) */
+#define I2C2_ENABLE_HDRX_Msk (0xc0000UL) /*!< HDRX (Bitfield-Mask: 0x03) */
+#define I2C2_ENABLE_NSTCH_Pos (17UL) /*!< NSTCH (Bit 17) */
+#define I2C2_ENABLE_NSTCH_Msk (0x20000UL) /*!< NSTCH (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_MSTCH_Pos (16UL) /*!< MSTCH (Bit 16) */
+#define I2C2_ENABLE_MSTCH_Msk (0x10000UL) /*!< MSTCH (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_SMTOEN_Pos (15UL) /*!< SMTOEN (Bit 15) */
+#define I2C2_ENABLE_SMTOEN_Msk (0x8000UL) /*!< SMTOEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_SMHEN_Pos (14UL) /*!< SMHEN (Bit 14) */
+#define I2C2_ENABLE_SMHEN_Msk (0x4000UL) /*!< SMHEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_SMARPEN_Pos (13UL) /*!< SMARPEN (Bit 13) */
+#define I2C2_ENABLE_SMARPEN_Msk (0x2000UL) /*!< SMARPEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_SMALEN_Pos (12UL) /*!< SMALEN (Bit 12) */
+#define I2C2_ENABLE_SMALEN_Msk (0x1000UL) /*!< SMALEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_OSAEN_Pos (11UL) /*!< OSAEN (Bit 11) */
+#define I2C2_ENABLE_OSAEN_Msk (0x800UL) /*!< OSAEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_GCEN_Pos (10UL) /*!< GCEN (Bit 10) */
+#define I2C2_ENABLE_GCEN_Msk (0x400UL) /*!< GCEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_A10BEN_Pos (9UL) /*!< A10BEN (Bit 9) */
+#define I2C2_ENABLE_A10BEN_Msk (0x200UL) /*!< A10BEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_MSTEN_Pos (8UL) /*!< MSTEN (Bit 8) */
+#define I2C2_ENABLE_MSTEN_Msk (0x100UL) /*!< MSTEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_RFHSEN_Pos (7UL) /*!< RFHSEN (Bit 7) */
+#define I2C2_ENABLE_RFHSEN_Msk (0x80UL) /*!< RFHSEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_DMATXEN_Pos (6UL) /*!< DMATXEN (Bit 6) */
+#define I2C2_ENABLE_DMATXEN_Msk (0x40UL) /*!< DMATXEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_DMARXEN_Pos (5UL) /*!< DMARXEN (Bit 5) */
+#define I2C2_ENABLE_DMARXEN_Msk (0x20UL) /*!< DMARXEN (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_RLSCMD_Pos (4UL) /*!< RLSCMD (Bit 4) */
+#define I2C2_ENABLE_RLSCMD_Msk (0x10UL) /*!< RLSCMD (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_TFRST_Pos (3UL) /*!< TFRST (Bit 3) */
+#define I2C2_ENABLE_TFRST_Msk (0x8UL) /*!< TFRST (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_RFRST_Pos (2UL) /*!< RFRST (Bit 2) */
+#define I2C2_ENABLE_RFRST_Msk (0x4UL) /*!< RFRST (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_UDRCFG_Pos (1UL) /*!< UDRCFG (Bit 1) */
+#define I2C2_ENABLE_UDRCFG_Msk (0x2UL) /*!< UDRCFG (Bitfield-Mask: 0x01) */
+#define I2C2_ENABLE_I2CEN_Pos (0UL) /*!< I2CEN (Bit 0) */
+#define I2C2_ENABLE_I2CEN_Msk (0x1UL) /*!< I2CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CTRL ========================================================== */
+#define I2C2_CTRL_AUTOEND_Pos (14UL) /*!< AUTOEND (Bit 14) */
+#define I2C2_CTRL_AUTOEND_Msk (0x4000UL) /*!< AUTOEND (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_MODE10B_Pos (13UL) /*!< MODE10B (Bit 13) */
+#define I2C2_CTRL_MODE10B_Msk (0x2000UL) /*!< MODE10B (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_PECBYTE_Pos (12UL) /*!< PECBYTE (Bit 12) */
+#define I2C2_CTRL_PECBYTE_Msk (0x1000UL) /*!< PECBYTE (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_NACK_Pos (11UL) /*!< NACK (Bit 11) */
+#define I2C2_CTRL_NACK_Msk (0x800UL) /*!< NACK (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_START_Pos (10UL) /*!< START (Bit 10) */
+#define I2C2_CTRL_START_Msk (0x400UL) /*!< START (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_STOP_Pos (9UL) /*!< STOP (Bit 9) */
+#define I2C2_CTRL_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_DIRECT_Pos (8UL) /*!< DIRECT (Bit 8) */
+#define I2C2_CTRL_DIRECT_Msk (0x100UL) /*!< DIRECT (Bitfield-Mask: 0x01) */
+#define I2C2_CTRL_I2CCNT_Pos (0UL) /*!< I2CCNT (Bit 0) */
+#define I2C2_CTRL_I2CCNT_Msk (0xffUL) /*!< I2CCNT (Bitfield-Mask: 0xff) */
+/* ========================================================= BAUD ========================================================== */
+#define I2C2_BAUD_SCLHCNT_Pos (16UL) /*!< SCLHCNT (Bit 16) */
+#define I2C2_BAUD_SCLHCNT_Msk (0x3ff0000UL) /*!< SCLHCNT (Bitfield-Mask: 0x3ff) */
+#define I2C2_BAUD_SCLLCNT_Pos (0UL) /*!< SCLLCNT (Bit 0) */
+#define I2C2_BAUD_SCLLCNT_Msk (0x3ffUL) /*!< SCLLCNT (Bitfield-Mask: 0x3ff) */
+/* ========================================================= UDRDR ========================================================= */
+#define I2C2_UDRDR_UDRDR_Pos (0UL) /*!< UDRDR (Bit 0) */
+#define I2C2_UDRDR_UDRDR_Msk (0xffUL) /*!< UDRDR (Bitfield-Mask: 0xff) */
+/* ======================================================= FIFOCTRL ======================================================== */
+#define I2C2_FIFOCTRL_RXFTLR_Pos (4UL) /*!< RXFTLR (Bit 4) */
+#define I2C2_FIFOCTRL_RXFTLR_Msk (0xf0UL) /*!< RXFTLR (Bitfield-Mask: 0x0f) */
+#define I2C2_FIFOCTRL_TXFTLR_Pos (0UL) /*!< TXFTLR (Bit 0) */
+#define I2C2_FIFOCTRL_TXFTLR_Msk (0xfUL) /*!< TXFTLR (Bitfield-Mask: 0x0f) */
+/* ========================================================== TAR ========================================================== */
+#define I2C2_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
+#define I2C2_TAR_TAR_Msk (0x3ffUL) /*!< TAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== SAR ========================================================== */
+#define I2C2_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define I2C2_SAR_SAR_Msk (0x3ffUL) /*!< SAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================= OSAR ========================================================== */
+#define I2C2_OSAR_OSAM_Pos (16UL) /*!< OSAM (Bit 16) */
+#define I2C2_OSAR_OSAM_Msk (0x3ff0000UL) /*!< OSAM (Bitfield-Mask: 0x3ff) */
+#define I2C2_OSAR_OSAR_Pos (0UL) /*!< OSAR (Bit 0) */
+#define I2C2_OSAR_OSAR_Msk (0x3ffUL) /*!< OSAR (Bitfield-Mask: 0x3ff) */
+/* ========================================================== PEC ========================================================== */
+#define I2C2_PEC_IDPEC_Pos (8UL) /*!< IDPEC (Bit 8) */
+#define I2C2_PEC_IDPEC_Msk (0xff00UL) /*!< IDPEC (Bitfield-Mask: 0xff) */
+#define I2C2_PEC_RXPEC_Pos (0UL) /*!< RXPEC (Bit 0) */
+#define I2C2_PEC_RXPEC_Msk (0xffUL) /*!< RXPEC (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMING ========================================================= */
+#define I2C2_TIMING_SPKLEN_Pos (24UL) /*!< SPKLEN (Bit 24) */
+#define I2C2_TIMING_SPKLEN_Msk (0xff000000UL) /*!< SPKLEN (Bitfield-Mask: 0xff) */
+#define I2C2_TIMING_SLVSUDAT_Pos (16UL) /*!< SLVSUDAT (Bit 16) */
+#define I2C2_TIMING_SLVSUDAT_Msk (0xff0000UL) /*!< SLVSUDAT (Bitfield-Mask: 0xff) */
+#define I2C2_TIMING_SUDAT_Pos (8UL) /*!< SUDAT (Bit 8) */
+#define I2C2_TIMING_SUDAT_Msk (0xff00UL) /*!< SUDAT (Bitfield-Mask: 0xff) */
+#define I2C2_TIMING_HDDAT_Pos (0UL) /*!< HDDAT (Bit 0) */
+#define I2C2_TIMING_HDDAT_Msk (0xffUL) /*!< HDDAT (Bitfield-Mask: 0xff) */
+/* ======================================================== TIMEOUT ======================================================== */
+#define I2C2_TIMEOUT_SEXTTO_Pos (16UL) /*!< SEXTTO (Bit 16) */
+#define I2C2_TIMEOUT_SEXTTO_Msk (0xffff0000UL) /*!< SEXTTO (Bitfield-Mask: 0xffff) */
+#define I2C2_TIMEOUT_MEXTTO_Pos (0UL) /*!< MEXTTO (Bit 0) */
+#define I2C2_TIMEOUT_MEXTTO_Msk (0xffffUL) /*!< MEXTTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== BUSTOUT ======================================================== */
+#define I2C2_BUSTOUT_TOSEL_Pos (31UL) /*!< TOSEL (Bit 31) */
+#define I2C2_BUSTOUT_TOSEL_Msk (0x80000000UL) /*!< TOSEL (Bitfield-Mask: 0x01) */
+#define I2C2_BUSTOUT_BTO_Pos (0UL) /*!< BTO (Bit 0) */
+#define I2C2_BUSTOUT_BTO_Msk (0xffffUL) /*!< BTO (Bitfield-Mask: 0xffff) */
+/* ======================================================== INTREN ========================================================= */
+#define I2C2_INTREN_BTOIE_Pos (23UL) /*!< BTOIE (Bit 23) */
+#define I2C2_INTREN_BTOIE_Msk (0x800000UL) /*!< BTOIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_MOHIE_Pos (22UL) /*!< MOHIE (Bit 22) */
+#define I2C2_INTREN_MOHIE_Msk (0x400000UL) /*!< MOHIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_SWTXIE_Pos (21UL) /*!< SWTXIE (Bit 21) */
+#define I2C2_INTREN_SWTXIE_Msk (0x200000UL) /*!< SWTXIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_MTXAIE_Pos (20UL) /*!< MTXAIE (Bit 20) */
+#define I2C2_INTREN_MTXAIE_Msk (0x100000UL) /*!< MTXAIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RXGCIE_Pos (19UL) /*!< RXGCIE (Bit 19) */
+#define I2C2_INTREN_RXGCIE_Msk (0x80000UL) /*!< RXGCIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_PECRXIE_Pos (18UL) /*!< PECRXIE (Bit 18) */
+#define I2C2_INTREN_PECRXIE_Msk (0x40000UL) /*!< PECRXIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_SEXTOIE_Pos (17UL) /*!< SEXTOIE (Bit 17) */
+#define I2C2_INTREN_SEXTOIE_Msk (0x20000UL) /*!< SEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_MEXTOIE_Pos (16UL) /*!< MEXTOIE (Bit 16) */
+#define I2C2_INTREN_MEXTOIE_Msk (0x10000UL) /*!< MEXTOIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_ALDETIE_Pos (15UL) /*!< ALDETIE (Bit 15) */
+#define I2C2_INTREN_ALDETIE_Msk (0x8000UL) /*!< ALDETIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_NACKIE_Pos (14UL) /*!< NACKIE (Bit 14) */
+#define I2C2_INTREN_NACKIE_Msk (0x4000UL) /*!< NACKIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RSDETIE_Pos (13UL) /*!< RSDETIE (Bit 13) */
+#define I2C2_INTREN_RSDETIE_Msk (0x2000UL) /*!< RSDETIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_SPDETIE_Pos (12UL) /*!< SPDETIE (Bit 12) */
+#define I2C2_INTREN_SPDETIE_Msk (0x1000UL) /*!< SPDETIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_STDETIE_Pos (11UL) /*!< STDETIE (Bit 11) */
+#define I2C2_INTREN_STDETIE_Msk (0x800UL) /*!< STDETIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RXADIE_Pos (10UL) /*!< RXADIE (Bit 10) */
+#define I2C2_INTREN_RXADIE_Msk (0x400UL) /*!< RXADIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_TXADIE_Pos (9UL) /*!< TXADIE (Bit 9) */
+#define I2C2_INTREN_TXADIE_Msk (0x200UL) /*!< TXADIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_MDEIE_Pos (8UL) /*!< MDEIE (Bit 8) */
+#define I2C2_INTREN_MDEIE_Msk (0x100UL) /*!< MDEIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_BUSEIE_Pos (7UL) /*!< BUSEIE (Bit 7) */
+#define I2C2_INTREN_BUSEIE_Msk (0x80UL) /*!< BUSEIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_ARBFIE_Pos (6UL) /*!< ARBFIE (Bit 6) */
+#define I2C2_INTREN_ARBFIE_Msk (0x40UL) /*!< ARBFIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_TXUFIE_Pos (5UL) /*!< TXUFIE (Bit 5) */
+#define I2C2_INTREN_TXUFIE_Msk (0x20UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_TXOFIE_Pos (4UL) /*!< TXOFIE (Bit 4) */
+#define I2C2_INTREN_TXOFIE_Msk (0x10UL) /*!< TXOFIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RXUFIE_Pos (3UL) /*!< RXUFIE (Bit 3) */
+#define I2C2_INTREN_RXUFIE_Msk (0x8UL) /*!< RXUFIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RXOFIE_Pos (2UL) /*!< RXOFIE (Bit 2) */
+#define I2C2_INTREN_RXOFIE_Msk (0x4UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_TXEIE_Pos (1UL) /*!< TXEIE (Bit 1) */
+#define I2C2_INTREN_TXEIE_Msk (0x2UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
+#define I2C2_INTREN_RXFIE_Pos (0UL) /*!< RXFIE (Bit 0) */
+#define I2C2_INTREN_RXFIE_Msk (0x1UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
+/* ========================================================= INTR ========================================================== */
+#define I2C2_INTR_RCNT_Pos (24UL) /*!< RCNT (Bit 24) */
+#define I2C2_INTR_RCNT_Msk (0xff000000UL) /*!< RCNT (Bitfield-Mask: 0xff) */
+#define I2C2_INTR_BTOI_Pos (23UL) /*!< BTOI (Bit 23) */
+#define I2C2_INTR_BTOI_Msk (0x800000UL) /*!< BTOI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_MOHI_Pos (22UL) /*!< MOHI (Bit 22) */
+#define I2C2_INTR_MOHI_Msk (0x400000UL) /*!< MOHI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_SWTXI_Pos (21UL) /*!< SWTXI (Bit 21) */
+#define I2C2_INTR_SWTXI_Msk (0x200000UL) /*!< SWTXI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_MTXAI_Pos (20UL) /*!< MTXAI (Bit 20) */
+#define I2C2_INTR_MTXAI_Msk (0x100000UL) /*!< MTXAI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RXGCI_Pos (19UL) /*!< RXGCI (Bit 19) */
+#define I2C2_INTR_RXGCI_Msk (0x80000UL) /*!< RXGCI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_PECRXI_Pos (18UL) /*!< PECRXI (Bit 18) */
+#define I2C2_INTR_PECRXI_Msk (0x40000UL) /*!< PECRXI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_SEXTOI_Pos (17UL) /*!< SEXTOI (Bit 17) */
+#define I2C2_INTR_SEXTOI_Msk (0x20000UL) /*!< SEXTOI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_MEXTOI_Pos (16UL) /*!< MEXTOI (Bit 16) */
+#define I2C2_INTR_MEXTOI_Msk (0x10000UL) /*!< MEXTOI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_ALDETI_Pos (15UL) /*!< ALDETI (Bit 15) */
+#define I2C2_INTR_ALDETI_Msk (0x8000UL) /*!< ALDETI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_NACKI_Pos (14UL) /*!< NACKI (Bit 14) */
+#define I2C2_INTR_NACKI_Msk (0x4000UL) /*!< NACKI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RSDETI_Pos (13UL) /*!< RSDETI (Bit 13) */
+#define I2C2_INTR_RSDETI_Msk (0x2000UL) /*!< RSDETI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_SPETI_Pos (12UL) /*!< SPETI (Bit 12) */
+#define I2C2_INTR_SPETI_Msk (0x1000UL) /*!< SPETI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_STDETI_Pos (11UL) /*!< STDETI (Bit 11) */
+#define I2C2_INTR_STDETI_Msk (0x800UL) /*!< STDETI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RXADI_Pos (10UL) /*!< RXADI (Bit 10) */
+#define I2C2_INTR_RXADI_Msk (0x400UL) /*!< RXADI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_TXADI_Pos (9UL) /*!< TXADI (Bit 9) */
+#define I2C2_INTR_TXADI_Msk (0x200UL) /*!< TXADI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_MDEI_Pos (8UL) /*!< MDEI (Bit 8) */
+#define I2C2_INTR_MDEI_Msk (0x100UL) /*!< MDEI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_BUSEI_Pos (7UL) /*!< BUSEI (Bit 7) */
+#define I2C2_INTR_BUSEI_Msk (0x80UL) /*!< BUSEI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_ARBFI_Pos (6UL) /*!< ARBFI (Bit 6) */
+#define I2C2_INTR_ARBFI_Msk (0x40UL) /*!< ARBFI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_TXUFI_Pos (5UL) /*!< TXUFI (Bit 5) */
+#define I2C2_INTR_TXUFI_Msk (0x20UL) /*!< TXUFI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_TXOFI_Pos (4UL) /*!< TXOFI (Bit 4) */
+#define I2C2_INTR_TXOFI_Msk (0x10UL) /*!< TXOFI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RXUFI_Pos (3UL) /*!< RXUFI (Bit 3) */
+#define I2C2_INTR_RXUFI_Msk (0x8UL) /*!< RXUFI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RXOFI_Pos (2UL) /*!< RXOFI (Bit 2) */
+#define I2C2_INTR_RXOFI_Msk (0x4UL) /*!< RXOFI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_TXEI_Pos (1UL) /*!< TXEI (Bit 1) */
+#define I2C2_INTR_TXEI_Msk (0x2UL) /*!< TXEI (Bitfield-Mask: 0x01) */
+#define I2C2_INTR_RXFI_Pos (0UL) /*!< RXFI (Bit 0) */
+#define I2C2_INTR_RXFI_Msk (0x1UL) /*!< RXFI (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define I2C2_STATUS_RFF_Pos (30UL) /*!< RFF (Bit 30) */
+#define I2C2_STATUS_RFF_Msk (0x40000000UL) /*!< RFF (Bitfield-Mask: 0x01) */
+#define I2C2_STATUS_RFE_Pos (29UL) /*!< RFE (Bit 29) */
+#define I2C2_STATUS_RFE_Msk (0x20000000UL) /*!< RFE (Bitfield-Mask: 0x01) */
+#define I2C2_STATUS_RXFLR_Pos (24UL) /*!< RXFLR (Bit 24) */
+#define I2C2_STATUS_RXFLR_Msk (0x1f000000UL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
+#define I2C2_STATUS_TFF_Pos (22UL) /*!< TFF (Bit 22) */
+#define I2C2_STATUS_TFF_Msk (0x400000UL) /*!< TFF (Bitfield-Mask: 0x01) */
+#define I2C2_STATUS_TFE_Pos (21UL) /*!< TFE (Bit 21) */
+#define I2C2_STATUS_TFE_Msk (0x200000UL) /*!< TFE (Bitfield-Mask: 0x01) */
+#define I2C2_STATUS_TXFLR_Pos (16UL) /*!< TXFLR (Bit 16) */
+#define I2C2_STATUS_TXFLR_Msk (0x1f0000UL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
+#define I2C2_STATUS_ARBSTA_Pos (2UL) /*!< ARBSTA (Bit 2) */
+#define I2C2_STATUS_ARBSTA_Msk (0xcUL) /*!< ARBSTA (Bitfield-Mask: 0x03) */
+#define I2C2_STATUS_BUSBSY_Pos (1UL) /*!< BUSBSY (Bit 1) */
+#define I2C2_STATUS_BUSBSY_Msk (0x2UL) /*!< BUSBSY (Bitfield-Mask: 0x01) */
+#define I2C2_STATUS_FSMBSY_Pos (0UL) /*!< FSMBSY (Bit 0) */
+#define I2C2_STATUS_FSMBSY_Msk (0x1UL) /*!< FSMBSY (Bitfield-Mask: 0x01) */
+/* ======================================================== TXDATA ========================================================= */
+#define I2C2_TXDATA_TXDATA_Pos (0UL) /*!< TXDATA (Bit 0) */
+#define I2C2_TXDATA_TXDATA_Msk (0xffUL) /*!< TXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXDATA ========================================================= */
+#define I2C2_RXDATA_RXDATA_Pos (0UL) /*!< RXDATA (Bit 0) */
+#define I2C2_RXDATA_RXDATA_Msk (0xffUL) /*!< RXDATA (Bitfield-Mask: 0xff) */
+/* ======================================================== RXADDR ========================================================= */
+#define I2C2_RXADDR_ADDR_Pos (1UL) /*!< ADDR (Bit 1) */
+#define I2C2_RXADDR_ADDR_Msk (0xfeUL) /*!< ADDR (Bitfield-Mask: 0x7f) */
+#define I2C2_RXADDR_DIR_Pos (0UL) /*!< DIR (Bit 0) */
+#define I2C2_RXADDR_DIR_Msk (0x1UL) /*!< DIR (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV0 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV0_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV0_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV0_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV0_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV0_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV0_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV0_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV0_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV0_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV0_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV0_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV0_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV0_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV0_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV0_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV0_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV0_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV0_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV0_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV0_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV0_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV0_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV0_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV0_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV0_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV0_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV0_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV0_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV0_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV0_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV0_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV0_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV0_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV0_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV0_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV0_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV0_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV0_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV0_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV0_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV0_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV0_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV0_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV0_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV0_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV0_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV0_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV0_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV0_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV0_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV0_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV0_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV0_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV0_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV0_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV0_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV0_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV0_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV0_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV0_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV0_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV0_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV0_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV0_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV0_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV0_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV0_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV0_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV0_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV0_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV0_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV0_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV0_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV0_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV0_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV0_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV0_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV0_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV0_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV0_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV0_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV0_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV0_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV0_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV0_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV0_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV0_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV0_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV0_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV0_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV0_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV0_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV0_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV0_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV0_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV0_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV0_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV0_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV0_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV0_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV0_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV0_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV0_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV0_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV0_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV0_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV0_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV0_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV0_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV0_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV0_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV0_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV0_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV0_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV0_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV0_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV0_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV0_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV0_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV0_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV0_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV0_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV0_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV0_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV0_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV0_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV0_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV0_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV0_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV0_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV0_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV0_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV0_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV0_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV0_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV0_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV0_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV0_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV0_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV0_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV0_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV0_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV0_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV0_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV0_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV0_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV0_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV0_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV0_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV0_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV0_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV0_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV0_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV0_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV0_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV0_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV0_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV0_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV0_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV0_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV0_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV0_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV0_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV0_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV0_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV0_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV0_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV0_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV0_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV0_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV0_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV0_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV0_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV0_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV0_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV0_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV0_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV0_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV0_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV0_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV0_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV0_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV0_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV0_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV0_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV0_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV0_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV0_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV0_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV0_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV0_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV0_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV0_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV0_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV0_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV0_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV0_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV0_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV0_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV0_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV0_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV0_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV0_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV0_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV0_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV0_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV0_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV0_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV0_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV0_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV0_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV0_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV0_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV0_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV0_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV0_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV0_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV0_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV0_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV0_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV0_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV0_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV0_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV0_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV0_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV0_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV0_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV0_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV0_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV0_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV0_RSTR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV0_RSTR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV4CMPD_Pos (30UL) /*!< SLV4CMPD (Bit 30) */
+#define HRPWM_SLV0_RSTR_SLV4CMPD_Msk (0x40000000UL) /*!< SLV4CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV4CMPB_Pos (29UL) /*!< SLV4CMPB (Bit 29) */
+#define HRPWM_SLV0_RSTR_SLV4CMPB_Msk (0x20000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV4CMPA_Pos (28UL) /*!< SLV4CMPA (Bit 28) */
+#define HRPWM_SLV0_RSTR_SLV4CMPA_Msk (0x10000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV3CMPD_Pos (27UL) /*!< SLV3CMPD (Bit 27) */
+#define HRPWM_SLV0_RSTR_SLV3CMPD_Msk (0x8000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV3CMPB_Pos (26UL) /*!< SLV3CMPB (Bit 26) */
+#define HRPWM_SLV0_RSTR_SLV3CMPB_Msk (0x4000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV3CMPA_Pos (25UL) /*!< SLV3CMPA (Bit 25) */
+#define HRPWM_SLV0_RSTR_SLV3CMPA_Msk (0x2000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV2CMPD_Pos (24UL) /*!< SLV2CMPD (Bit 24) */
+#define HRPWM_SLV0_RSTR_SLV2CMPD_Msk (0x1000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV0_RSTR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV0_RSTR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV1CMPD_Pos (21UL) /*!< SLV1CMPD (Bit 21) */
+#define HRPWM_SLV0_RSTR_SLV1CMPD_Msk (0x200000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV1CMPB_Pos (20UL) /*!< SLV1CMPB (Bit 20) */
+#define HRPWM_SLV0_RSTR_SLV1CMPB_Msk (0x100000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV1CMPA_Pos (19UL) /*!< SLV1CMPA (Bit 19) */
+#define HRPWM_SLV0_RSTR_SLV1CMPA_Msk (0x80000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV0_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV0_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV0_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV0_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV0_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV0_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV0_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV0_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV0_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV0_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV0_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV0_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV0_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV0_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV0_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV0_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV0_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV0_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTR_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV0_RSTR_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV0_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV0_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV0_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV0_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV0_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV0_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV0_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV0_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV0_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV0_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV0_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV0_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV0_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV0_CAPACR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV0_CAPACR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV0_CAPACR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV0_CAPACR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV0_CAPACR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV0_CAPACR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV0_CAPACR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV0_CAPACR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV0_CAPACR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV0_CAPACR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV0_CAPACR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV0_CAPACR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV0_CAPACR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV2CMPB_Pos (19UL) /*!< SLV2CMPB (Bit 19) */
+#define HRPWM_SLV0_CAPACR_SLV2CMPB_Msk (0x80000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV2CMPA_Pos (18UL) /*!< SLV2CMPA (Bit 18) */
+#define HRPWM_SLV0_CAPACR_SLV2CMPA_Msk (0x40000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV2CLRA_Pos (17UL) /*!< SLV2CLRA (Bit 17) */
+#define HRPWM_SLV0_CAPACR_SLV2CLRA_Msk (0x20000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV2SETA_Pos (16UL) /*!< SLV2SETA (Bit 16) */
+#define HRPWM_SLV0_CAPACR_SLV2SETA_Msk (0x10000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV1CMPB_Pos (15UL) /*!< SLV1CMPB (Bit 15) */
+#define HRPWM_SLV0_CAPACR_SLV1CMPB_Msk (0x8000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV1CMPA_Pos (14UL) /*!< SLV1CMPA (Bit 14) */
+#define HRPWM_SLV0_CAPACR_SLV1CMPA_Msk (0x4000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV1CLRA_Pos (13UL) /*!< SLV1CLRA (Bit 13) */
+#define HRPWM_SLV0_CAPACR_SLV1CLRA_Msk (0x2000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SLV1SETA_Pos (12UL) /*!< SLV1SETA (Bit 12) */
+#define HRPWM_SLV0_CAPACR_SLV1SETA_Msk (0x1000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV0_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV0_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV0_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV0_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV0_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV0_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV0_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV0_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV0_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV0_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV0_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV0_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV0_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV0_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV0_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV0_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV0_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV0_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV0_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV0_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV0_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV0_CAPBCR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV0_CAPBCR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV0_CAPBCR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV0_CAPBCR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV0_CAPBCR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV0_CAPBCR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV0_CAPBCR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV0_CAPBCR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV0_CAPBCR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV0_CAPBCR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV0_CAPBCR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV0_CAPBCR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV0_CAPBCR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV2CMPB_Pos (19UL) /*!< SLV2CMPB (Bit 19) */
+#define HRPWM_SLV0_CAPBCR_SLV2CMPB_Msk (0x80000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV2CMPA_Pos (18UL) /*!< SLV2CMPA (Bit 18) */
+#define HRPWM_SLV0_CAPBCR_SLV2CMPA_Msk (0x40000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV2CLRA_Pos (17UL) /*!< SLV2CLRA (Bit 17) */
+#define HRPWM_SLV0_CAPBCR_SLV2CLRA_Msk (0x20000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV2SETA_Pos (16UL) /*!< SLV2SETA (Bit 16) */
+#define HRPWM_SLV0_CAPBCR_SLV2SETA_Msk (0x10000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV1CMPB_Pos (15UL) /*!< SLV1CMPB (Bit 15) */
+#define HRPWM_SLV0_CAPBCR_SLV1CMPB_Msk (0x8000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV1CMPA_Pos (14UL) /*!< SLV1CMPA (Bit 14) */
+#define HRPWM_SLV0_CAPBCR_SLV1CMPA_Msk (0x4000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV1CLRA_Pos (13UL) /*!< SLV1CLRA (Bit 13) */
+#define HRPWM_SLV0_CAPBCR_SLV1CLRA_Msk (0x2000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SLV1SETA_Pos (12UL) /*!< SLV1SETA (Bit 12) */
+#define HRPWM_SLV0_CAPBCR_SLV1SETA_Msk (0x1000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV0_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV0_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV0_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV0_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV0_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV0_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV0_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV0_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV0_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV0_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV0_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV0_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV0_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV0_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV0_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV0_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV0_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV0_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV0_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV0_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV0_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV0_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV0_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV0_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV0_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV0_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV0_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV0_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV0_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV0_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV0_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV0_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV0_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV0_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV0_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV0_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV0_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV0_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV0_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV0_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV0_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV0_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV0_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV0_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV0_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV0_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV0_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV0_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV0_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV0_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV0_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV0_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV0_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV0_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV0_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV0_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV0_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV0_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV0_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV0_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV0_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV0_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV0_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV0_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV0_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV0_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV0_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV0_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV0_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV0_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV0_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV0_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV0_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV0_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV1 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV1_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV1_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV1_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV1_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV1_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV1_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV1_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV1_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV1_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV1_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV1_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV1_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV1_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV1_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV1_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV1_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV1_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV1_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV1_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV1_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV1_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV1_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV1_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV1_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV1_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV1_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV1_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV1_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV1_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV1_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV1_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV1_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV1_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV1_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV1_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV1_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV1_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV1_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV1_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV1_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV1_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV1_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV1_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV1_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV1_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV1_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV1_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV1_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV1_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV1_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV1_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV1_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV1_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV1_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV1_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV1_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV1_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV1_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV1_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV1_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV1_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV1_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV1_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV1_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV1_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV1_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV1_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV1_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV1_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV1_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV1_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV1_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV1_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV1_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV1_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV1_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV1_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV1_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV1_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV1_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV1_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV1_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV1_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV1_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV1_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV1_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV1_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV1_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV1_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV1_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV1_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV1_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV1_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV1_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV1_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV1_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV1_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV1_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV1_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV1_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV1_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV1_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV1_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV1_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV1_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV1_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV1_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV1_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV1_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV1_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV1_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV1_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV1_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV1_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV1_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV1_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV1_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV1_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV1_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV1_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV1_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV1_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV1_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV1_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV1_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV1_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV1_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV1_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV1_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV1_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV1_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV1_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV1_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV1_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV1_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV1_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV1_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV1_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV1_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV1_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV1_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV1_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV1_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV1_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV1_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV1_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV1_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV1_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV1_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV1_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV1_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV1_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV1_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV1_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV1_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV1_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV1_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV1_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV1_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV1_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV1_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV1_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV1_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV1_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV1_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV1_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV1_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV1_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV1_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV1_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV1_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV1_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV1_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV1_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV1_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV1_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV1_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV1_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV1_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV1_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV1_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV1_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV1_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV1_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV1_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV1_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV1_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV1_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV1_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV1_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV1_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV1_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV1_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV1_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV1_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV1_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV1_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV1_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV1_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV1_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV1_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV1_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV1_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV1_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV1_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV1_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV1_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV1_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV1_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV1_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV1_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV1_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV1_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV1_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV1_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV1_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV1_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV1_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV1_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV1_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV1_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV1_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV1_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV1_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV1_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV1_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV1_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV1_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV1_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV1_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV1_RSTR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV1_RSTR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV4CMPD_Pos (30UL) /*!< SLV4CMPD (Bit 30) */
+#define HRPWM_SLV1_RSTR_SLV4CMPD_Msk (0x40000000UL) /*!< SLV4CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV4CMPB_Pos (29UL) /*!< SLV4CMPB (Bit 29) */
+#define HRPWM_SLV1_RSTR_SLV4CMPB_Msk (0x20000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV4CMPA_Pos (28UL) /*!< SLV4CMPA (Bit 28) */
+#define HRPWM_SLV1_RSTR_SLV4CMPA_Msk (0x10000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV3CMPD_Pos (27UL) /*!< SLV3CMPD (Bit 27) */
+#define HRPWM_SLV1_RSTR_SLV3CMPD_Msk (0x8000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV3CMPB_Pos (26UL) /*!< SLV3CMPB (Bit 26) */
+#define HRPWM_SLV1_RSTR_SLV3CMPB_Msk (0x4000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV3CMPA_Pos (25UL) /*!< SLV3CMPA (Bit 25) */
+#define HRPWM_SLV1_RSTR_SLV3CMPA_Msk (0x2000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV2CMPD_Pos (24UL) /*!< SLV2CMPD (Bit 24) */
+#define HRPWM_SLV1_RSTR_SLV2CMPD_Msk (0x1000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV1_RSTR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV1_RSTR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV1_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV1_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV1_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV1_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV1_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV1_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV1_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV1_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV1_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV1_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV1_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV1_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV1_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV1_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV1_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV1_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV1_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV1_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV1_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV1_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV1_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTR_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV1_RSTR_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV1_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV1_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV1_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV1_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV1_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV1_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV1_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV1_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV1_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV1_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV1_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV1_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV1_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV1_CAPACR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV1_CAPACR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV1_CAPACR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV1_CAPACR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV1_CAPACR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV1_CAPACR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV1_CAPACR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV1_CAPACR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV1_CAPACR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV1_CAPACR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV1_CAPACR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV1_CAPACR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV1_CAPACR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV2CMPB_Pos (19UL) /*!< SLV2CMPB (Bit 19) */
+#define HRPWM_SLV1_CAPACR_SLV2CMPB_Msk (0x80000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV2CMPA_Pos (18UL) /*!< SLV2CMPA (Bit 18) */
+#define HRPWM_SLV1_CAPACR_SLV2CMPA_Msk (0x40000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV2CLRA_Pos (17UL) /*!< SLV2CLRA (Bit 17) */
+#define HRPWM_SLV1_CAPACR_SLV2CLRA_Msk (0x20000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV2SETA_Pos (16UL) /*!< SLV2SETA (Bit 16) */
+#define HRPWM_SLV1_CAPACR_SLV2SETA_Msk (0x10000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV1_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV1_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV1_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV1_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV1_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV1_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV1_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV1_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV1_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV1_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV1_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV1_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV1_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV1_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV1_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV1_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV1_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV1_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV1_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV1_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV1_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV1_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV1_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV1_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV1_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV1_CAPBCR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV1_CAPBCR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV1_CAPBCR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV1_CAPBCR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV1_CAPBCR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV1_CAPBCR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV1_CAPBCR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV1_CAPBCR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV1_CAPBCR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV1_CAPBCR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV1_CAPBCR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV1_CAPBCR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV1_CAPBCR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV2CMPB_Pos (19UL) /*!< SLV2CMPB (Bit 19) */
+#define HRPWM_SLV1_CAPBCR_SLV2CMPB_Msk (0x80000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV2CMPA_Pos (18UL) /*!< SLV2CMPA (Bit 18) */
+#define HRPWM_SLV1_CAPBCR_SLV2CMPA_Msk (0x40000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV2CLRA_Pos (17UL) /*!< SLV2CLRA (Bit 17) */
+#define HRPWM_SLV1_CAPBCR_SLV2CLRA_Msk (0x20000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV2SETA_Pos (16UL) /*!< SLV2SETA (Bit 16) */
+#define HRPWM_SLV1_CAPBCR_SLV2SETA_Msk (0x10000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV1_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV1_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV1_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV1_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV1_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV1_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV1_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV1_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV1_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV1_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV1_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV1_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV1_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV1_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV1_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV1_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV1_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV1_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV1_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV1_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV1_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV1_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV1_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV1_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV1_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV1_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV1_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV1_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV1_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV1_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV1_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV1_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV1_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV1_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV1_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV1_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV1_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV1_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV1_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV1_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV1_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV1_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV1_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV1_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV1_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV1_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV1_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV1_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV1_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV1_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV1_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV1_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV1_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV1_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV1_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV1_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV1_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV1_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV1_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV1_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV1_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV1_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV1_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV1_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV1_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV1_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV1_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV1_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV1_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV1_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV1_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV1_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV1_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV1_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV1_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV1_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV1_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV1_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV2 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV2_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV2_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV2_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV2_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV2_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV2_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV2_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV2_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV2_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV2_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV2_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV2_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV2_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV2_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV2_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV2_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV2_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV2_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV2_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV2_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV2_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV2_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV2_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV2_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV2_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV2_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV2_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV2_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV2_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV2_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV2_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV2_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV2_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV2_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV2_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV2_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV2_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV2_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV2_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV2_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV2_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV2_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV2_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV2_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV2_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV2_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV2_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV2_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV2_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV2_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV2_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV2_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV2_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV2_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV2_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV2_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV2_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV2_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV2_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV2_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV2_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV2_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV2_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV2_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV2_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV2_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV2_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV2_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV2_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV2_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV2_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV2_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV2_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV2_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV2_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV2_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV2_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV2_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV2_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV2_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV2_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV2_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV2_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV2_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV2_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV2_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV2_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV2_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV2_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV2_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV2_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV2_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV2_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV2_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV2_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV2_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV2_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV2_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV2_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV2_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV2_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV2_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV2_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV2_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV2_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV2_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV2_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV2_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV2_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV2_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV2_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV2_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV2_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV2_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV2_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV2_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV2_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV2_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV2_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV2_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV2_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV2_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV2_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV2_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV2_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV2_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV2_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV2_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV2_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV2_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV2_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV2_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV2_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV2_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV2_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV2_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV2_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV2_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV2_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV2_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV2_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV2_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV2_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV2_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV2_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV2_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV2_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV2_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV2_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV2_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV2_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV2_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV2_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV2_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV2_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV2_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV2_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV2_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV2_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV2_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV2_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV2_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV2_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV2_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV2_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV2_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV2_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV2_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV2_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV2_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV2_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV2_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV2_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV2_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV2_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV2_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV2_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV2_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV2_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV2_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV2_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV2_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV2_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV2_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV2_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV2_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV2_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV2_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV2_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV2_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV2_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV2_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV2_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV2_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV2_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV2_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV2_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV2_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV2_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV2_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV2_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV2_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV2_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV2_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV2_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV2_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV2_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV2_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV2_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV2_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV2_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV2_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV2_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV2_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV2_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV2_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV2_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV2_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV2_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV2_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV2_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV2_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV2_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV2_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV2_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV2_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV2_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV2_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV2_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV2_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV2_RSTR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV2_RSTR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV4CMPD_Pos (30UL) /*!< SLV4CMPD (Bit 30) */
+#define HRPWM_SLV2_RSTR_SLV4CMPD_Msk (0x40000000UL) /*!< SLV4CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV4CMPB_Pos (29UL) /*!< SLV4CMPB (Bit 29) */
+#define HRPWM_SLV2_RSTR_SLV4CMPB_Msk (0x20000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV4CMPA_Pos (28UL) /*!< SLV4CMPA (Bit 28) */
+#define HRPWM_SLV2_RSTR_SLV4CMPA_Msk (0x10000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV3CMPD_Pos (27UL) /*!< SLV3CMPD (Bit 27) */
+#define HRPWM_SLV2_RSTR_SLV3CMPD_Msk (0x8000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV3CMPB_Pos (26UL) /*!< SLV3CMPB (Bit 26) */
+#define HRPWM_SLV2_RSTR_SLV3CMPB_Msk (0x4000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV3CMPA_Pos (25UL) /*!< SLV3CMPA (Bit 25) */
+#define HRPWM_SLV2_RSTR_SLV3CMPA_Msk (0x2000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV2_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV2_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV2_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV2_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV2_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV2_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV2_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV2_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV2_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV2_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV2_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV2_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV2_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV2_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV2_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV2_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV2_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV2_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV2_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV2_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV2_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV2_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV2_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV2_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTR_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV2_RSTR_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV2_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV2_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV2_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV2_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV2_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV2_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV2_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV2_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV2_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV2_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV2_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV2_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV2_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV2_CAPACR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV2_CAPACR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV2_CAPACR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV2_CAPACR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV2_CAPACR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV2_CAPACR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV2_CAPACR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV2_CAPACR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV2_CAPACR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV2_CAPACR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV2_CAPACR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV2_CAPACR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV2_CAPACR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV2_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV2_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV2_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV2_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV2_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV2_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV2_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV2_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV2_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV2_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV2_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV2_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV2_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV2_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV2_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV2_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV2_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV2_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV2_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV2_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV2_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV2_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV2_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV2_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV2_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV2_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV2_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV2_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV2_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV2_CAPBCR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV2_CAPBCR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV2_CAPBCR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV2_CAPBCR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV2_CAPBCR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV2_CAPBCR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV2_CAPBCR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV2_CAPBCR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV2_CAPBCR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV3CMPB_Pos (23UL) /*!< SLV3CMPB (Bit 23) */
+#define HRPWM_SLV2_CAPBCR_SLV3CMPB_Msk (0x800000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV3CMPA_Pos (22UL) /*!< SLV3CMPA (Bit 22) */
+#define HRPWM_SLV2_CAPBCR_SLV3CMPA_Msk (0x400000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV3CLRA_Pos (21UL) /*!< SLV3CLRA (Bit 21) */
+#define HRPWM_SLV2_CAPBCR_SLV3CLRA_Msk (0x200000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV3SETA_Pos (20UL) /*!< SLV3SETA (Bit 20) */
+#define HRPWM_SLV2_CAPBCR_SLV3SETA_Msk (0x100000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV2_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV2_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV2_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV2_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV2_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV2_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV2_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV2_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV2_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV2_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV2_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV2_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV2_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV2_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV2_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV2_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV2_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV2_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV2_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV2_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV2_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV2_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV2_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV2_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV2_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV2_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV2_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV2_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV2_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV2_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV2_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV2_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV2_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV2_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV2_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV2_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV2_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV2_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV2_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV2_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV2_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV2_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV2_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV2_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV2_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV2_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV2_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV2_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV2_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV2_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV2_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV2_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV2_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV2_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV2_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV2_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV2_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV2_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV2_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV2_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV2_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV2_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV2_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV2_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV2_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV2_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV2_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV2_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV2_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV2_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV2_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV2_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV2_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV2_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV2_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV2_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV2_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV2_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV2_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV2_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV2_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV2_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV3 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV3_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV3_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV3_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV3_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV3_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV3_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV3_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV3_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV3_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV3_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV3_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV3_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV3_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV3_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV3_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV3_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV3_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV3_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV3_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV3_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV3_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV3_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV3_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV3_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV3_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV3_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV3_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV3_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV3_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV3_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV3_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV3_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV3_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV3_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV3_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV3_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV3_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV3_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV3_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV3_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV3_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV3_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV3_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV3_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV3_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV3_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV3_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV3_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV3_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV3_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV3_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV3_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV3_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV3_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV3_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV3_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV3_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV3_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV3_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV3_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV3_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV3_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV3_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV3_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV3_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV3_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV3_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV3_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV3_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV3_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV3_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV3_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV3_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV3_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV3_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV3_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV3_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV3_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV3_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV3_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV3_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV3_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV3_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV3_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV3_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV3_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV3_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV3_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV3_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV3_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV3_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV3_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV3_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV3_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV3_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV3_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV3_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV3_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV3_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV3_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV3_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV3_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV3_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV3_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV3_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV3_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV3_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV3_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV3_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV3_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV3_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV3_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV3_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV3_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV3_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV3_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV3_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV3_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV3_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV3_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV3_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV3_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV3_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV3_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV3_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV3_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV3_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV3_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV3_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV3_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV3_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV3_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV3_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV3_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV3_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV3_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV3_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV3_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV3_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV3_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV3_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV3_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV3_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV3_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV3_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV3_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV3_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV3_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV3_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV3_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV3_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV3_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV3_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV3_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV3_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV3_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV3_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV3_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV3_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV3_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV3_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV3_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV3_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV3_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV3_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV3_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV3_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV3_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV3_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV3_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV3_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV3_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV3_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV3_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV3_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV3_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV3_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV3_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV3_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV3_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV3_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV3_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV3_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV3_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV3_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV3_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV3_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV3_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV3_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV3_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV3_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV3_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV3_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV3_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV3_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV3_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV3_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV3_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV3_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV3_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV3_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV3_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV3_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV3_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV3_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV3_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV3_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV3_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV3_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV3_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV3_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV3_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV3_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV3_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV3_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV3_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV3_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV3_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV3_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV3_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV3_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV3_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV3_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV3_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV3_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV3_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV3_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV3_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV3_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV3_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV3_RSTR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV3_RSTR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV4CMPD_Pos (30UL) /*!< SLV4CMPD (Bit 30) */
+#define HRPWM_SLV3_RSTR_SLV4CMPD_Msk (0x40000000UL) /*!< SLV4CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV4CMPB_Pos (29UL) /*!< SLV4CMPB (Bit 29) */
+#define HRPWM_SLV3_RSTR_SLV4CMPB_Msk (0x20000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV4CMPA_Pos (28UL) /*!< SLV4CMPA (Bit 28) */
+#define HRPWM_SLV3_RSTR_SLV4CMPA_Msk (0x10000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV2CMPD_Pos (27UL) /*!< SLV2CMPD (Bit 27) */
+#define HRPWM_SLV3_RSTR_SLV2CMPD_Msk (0x8000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV2CMPB_Pos (26UL) /*!< SLV2CMPB (Bit 26) */
+#define HRPWM_SLV3_RSTR_SLV2CMPB_Msk (0x4000000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV2CMPA_Pos (25UL) /*!< SLV2CMPA (Bit 25) */
+#define HRPWM_SLV3_RSTR_SLV2CMPA_Msk (0x2000000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV3_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV3_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV3_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV3_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV3_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV3_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV3_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV3_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV3_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV3_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV3_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV3_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV3_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV3_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV3_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV3_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV3_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV3_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV3_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV3_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV3_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV3_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV3_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV3_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTR_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV3_RSTR_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV3_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV3_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV3_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV3_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV3_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV3_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV3_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV3_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV3_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV3_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV3_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV3_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV3_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV3_CAPACR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV3_CAPACR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV3_CAPACR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV3_CAPACR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV3_CAPACR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV3_CAPACR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV3_CAPACR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV3_CAPACR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV3_CAPACR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV3_CAPACR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV3_CAPACR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV3_CAPACR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV3_CAPACR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV3_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV3_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV3_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV3_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV3_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV3_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV3_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV3_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV3_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV3_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV3_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV3_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV3_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV3_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV3_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV3_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV3_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV3_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV3_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV3_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV3_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV3_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV3_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV3_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV3_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV3_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV3_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV3_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV3_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV3_CAPBCR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV3_CAPBCR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV3_CAPBCR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV3_CAPBCR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV3_CAPBCR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV4CMPB_Pos (27UL) /*!< SLV4CMPB (Bit 27) */
+#define HRPWM_SLV3_CAPBCR_SLV4CMPB_Msk (0x8000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV4CMPA_Pos (26UL) /*!< SLV4CMPA (Bit 26) */
+#define HRPWM_SLV3_CAPBCR_SLV4CMPA_Msk (0x4000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV4CLRA_Pos (25UL) /*!< SLV4CLRA (Bit 25) */
+#define HRPWM_SLV3_CAPBCR_SLV4CLRA_Msk (0x2000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV4SETA_Pos (24UL) /*!< SLV4SETA (Bit 24) */
+#define HRPWM_SLV3_CAPBCR_SLV4SETA_Msk (0x1000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV3_CAPBCR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV3_CAPBCR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV3_CAPBCR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV3_CAPBCR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV3_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV3_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV3_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV3_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV3_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV3_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV3_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV3_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV3_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV3_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV3_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV3_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV3_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV3_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV3_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV3_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV3_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV3_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV3_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV3_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV3_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV3_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV3_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV3_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV3_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV3_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV3_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV3_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV3_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV3_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV3_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV3_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV3_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV3_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV3_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV3_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV3_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV3_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV3_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV3_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV3_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV3_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV3_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV3_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV3_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV3_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV3_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV3_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV3_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV3_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV3_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV3_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV3_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV3_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV3_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV3_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV3_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV3_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV3_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV3_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV3_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV3_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV3_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV3_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV3_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV3_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV3_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV3_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV3_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV3_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV3_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV3_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV3_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV3_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV3_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV3_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV3_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV3_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV3_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV3_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV3_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV3_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV4 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV4_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV4_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV4_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV4_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV4_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV4_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV4_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV4_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV4_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV4_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV4_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV4_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV4_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV4_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV4_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV4_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV4_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV4_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV4_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV4_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV4_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV4_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV4_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV4_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV4_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV4_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV4_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV4_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV4_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV4_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV4_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV4_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV4_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV4_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV4_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV4_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV4_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV4_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV4_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV4_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV4_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV4_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV4_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV4_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV4_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV4_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV4_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV4_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV4_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV4_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV4_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV4_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV4_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV4_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV4_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV4_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV4_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV4_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV4_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV4_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV4_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV4_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV4_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV4_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV4_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV4_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV4_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV4_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV4_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV4_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV4_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV4_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV4_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV4_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV4_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV4_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV4_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV4_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV4_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV4_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV4_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV4_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV4_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV4_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV4_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV4_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV4_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV4_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV4_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV4_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV4_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV4_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV4_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV4_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV4_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV4_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV4_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV4_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV4_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV4_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV4_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV4_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV4_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV4_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV4_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV4_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV4_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV4_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV4_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV4_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV4_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV4_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV4_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV4_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV4_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV4_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV4_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV4_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV4_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV4_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV4_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV4_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV4_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV4_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV4_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV4_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV4_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV4_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV4_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV4_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV4_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV4_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV4_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV4_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV4_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV4_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV4_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV4_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV4_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV4_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV4_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV4_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV4_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV4_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV4_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV4_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV4_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV4_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV4_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV4_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV4_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV4_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV4_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV4_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV4_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV4_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV4_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV4_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV4_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV4_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV4_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV4_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV4_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV4_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV4_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV4_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV4_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV4_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV4_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV4_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV4_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV4_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV4_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV4_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV4_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV4_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV4_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV4_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV4_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV4_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV4_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV4_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV4_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV4_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV4_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV4_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV4_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV4_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV4_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV4_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV4_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV4_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV4_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV4_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV4_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV4_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV4_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV4_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV4_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV4_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV4_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV4_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV4_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV4_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV4_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV4_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV4_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV4_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV4_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV4_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV4_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV4_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV4_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV4_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV4_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV4_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV4_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV4_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV4_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV4_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV4_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV4_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV4_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV4_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV4_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV4_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV4_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV4_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV4_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV4_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV4_RSTR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV4_RSTR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV3CMPD_Pos (30UL) /*!< SLV3CMPD (Bit 30) */
+#define HRPWM_SLV4_RSTR_SLV3CMPD_Msk (0x40000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV3CMPB_Pos (29UL) /*!< SLV3CMPB (Bit 29) */
+#define HRPWM_SLV4_RSTR_SLV3CMPB_Msk (0x20000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV3CMPA_Pos (28UL) /*!< SLV3CMPA (Bit 28) */
+#define HRPWM_SLV4_RSTR_SLV3CMPA_Msk (0x10000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV2CMPD_Pos (27UL) /*!< SLV2CMPD (Bit 27) */
+#define HRPWM_SLV4_RSTR_SLV2CMPD_Msk (0x8000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV2CMPB_Pos (26UL) /*!< SLV2CMPB (Bit 26) */
+#define HRPWM_SLV4_RSTR_SLV2CMPB_Msk (0x4000000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV2CMPA_Pos (25UL) /*!< SLV2CMPA (Bit 25) */
+#define HRPWM_SLV4_RSTR_SLV2CMPA_Msk (0x2000000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV4_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV4_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV4_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV4_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV4_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV4_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV4_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV4_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV4_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV4_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV4_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV4_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV4_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV4_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV4_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV4_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV4_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV4_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV4_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV4_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV4_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV4_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV4_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV4_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTR_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV4_RSTR_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV4_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV4_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV4_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV4_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV4_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV4_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV4_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV4_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV4_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV4_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV4_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV4_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV4_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV4_CAPACR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV4_CAPACR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV4_CAPACR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV4_CAPACR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV4_CAPACR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV4_CAPACR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV4_CAPACR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV4_CAPACR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV4_CAPACR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV4_CAPACR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV4_CAPACR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV4_CAPACR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV4_CAPACR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV4_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV4_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV4_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV4_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV4_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV4_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV4_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV4_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV4_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV4_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV4_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV4_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV4_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV4_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV4_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV4_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV4_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV4_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV4_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV4_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV4_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV4_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV4_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV4_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV4_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV4_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV4_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV4_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV4_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV4_CAPBCR_SLV5CMPB_Pos (31UL) /*!< SLV5CMPB (Bit 31) */
+#define HRPWM_SLV4_CAPBCR_SLV5CMPB_Msk (0x80000000UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV5CMPA_Pos (30UL) /*!< SLV5CMPA (Bit 30) */
+#define HRPWM_SLV4_CAPBCR_SLV5CMPA_Msk (0x40000000UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV5CLRA_Pos (29UL) /*!< SLV5CLRA (Bit 29) */
+#define HRPWM_SLV4_CAPBCR_SLV5CLRA_Msk (0x20000000UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV5SETA_Pos (28UL) /*!< SLV5SETA (Bit 28) */
+#define HRPWM_SLV4_CAPBCR_SLV5SETA_Msk (0x10000000UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV4_CAPBCR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV4_CAPBCR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV4_CAPBCR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV4_CAPBCR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV4_CAPBCR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV4_CAPBCR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV4_CAPBCR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV4_CAPBCR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV4_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV4_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV4_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV4_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV4_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV4_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV4_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV4_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV4_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV4_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV4_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV4_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV4_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV4_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV4_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV4_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV4_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV4_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV4_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV4_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV4_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV4_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV4_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV4_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV4_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV4_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV4_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV4_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV4_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV4_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV4_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV4_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV4_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV4_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV4_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV4_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV4_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV4_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV4_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV4_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV4_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV4_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV4_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV4_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV4_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV4_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV4_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV4_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV4_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV4_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV4_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV4_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV4_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV4_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV4_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV4_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV4_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV4_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV4_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV4_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV4_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV4_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV4_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV4_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV4_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV4_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV4_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV4_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV4_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV4_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV4_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV4_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV4_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV4_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV4_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV4_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV4_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV4_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV4_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV4_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV4_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV4_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV5 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV5_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV5_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV5_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV5_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV5_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV5_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV5_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV5_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV5_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV5_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV5_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV5_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV5_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV5_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV5_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV5_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV5_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV5_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV5_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV5_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV5_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV5_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV5_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV5_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV5_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV5_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV5_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV5_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV5_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV5_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV5_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV5_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV5_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV5_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV5_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV5_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV5_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV5_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV5_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV5_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV5_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV5_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV5_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV5_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV5_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV5_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV5_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV5_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV5_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV5_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV5_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV5_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV5_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV5_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV5_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV5_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV5_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV5_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV5_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV5_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV5_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV5_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV5_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV5_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV5_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV5_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV5_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV5_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV5_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV5_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV5_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV5_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV5_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV5_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV5_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV5_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV5_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV5_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV5_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV5_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV5_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV5_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV5_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV5_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV5_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV5_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV5_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV5_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV5_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV5_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV5_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV5_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV5_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV5_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV5_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV5_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV5_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV5_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV5_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV5_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV5_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV5_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV5_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV5_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV5_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV5_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV5_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV5_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV5_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV5_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV5_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV5_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV5_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV5_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV5_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV5_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV5_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV5_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV5_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV5_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV5_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV5_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV5_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV5_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV5_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV5_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV5_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV5_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV5_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV5_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV5_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV5_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV5_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV5_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV5_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV5_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV5_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV5_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV5_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV5_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV5_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV5_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV5_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV5_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV5_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV5_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV5_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV5_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV5_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV5_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV5_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV5_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV5_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV5_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV5_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV5_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV5_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV5_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV5_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV5_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV5_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV5_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV5_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV5_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV5_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV5_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV5_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV5_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV5_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV5_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV5_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV5_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV5_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV5_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV5_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV5_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV5_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV5_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV5_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV5_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV5_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV5_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV5_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV5_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV5_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV5_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV5_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV5_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV5_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV5_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV5_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV5_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV5_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV5_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV5_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV5_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV5_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV5_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV5_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV5_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV5_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV5_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV5_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV5_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV5_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV5_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV5_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV5_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV5_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV5_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV5_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV5_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV5_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV5_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV5_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV5_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV5_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV5_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV5_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV5_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV5_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV5_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV5_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV5_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV5_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV5_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV5_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV5_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV5_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV5_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV5_RSTR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV5_RSTR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV3CMPD_Pos (30UL) /*!< SLV3CMPD (Bit 30) */
+#define HRPWM_SLV5_RSTR_SLV3CMPD_Msk (0x40000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV3CMPB_Pos (29UL) /*!< SLV3CMPB (Bit 29) */
+#define HRPWM_SLV5_RSTR_SLV3CMPB_Msk (0x20000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV3CMPA_Pos (28UL) /*!< SLV3CMPA (Bit 28) */
+#define HRPWM_SLV5_RSTR_SLV3CMPA_Msk (0x10000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV2CMPD_Pos (27UL) /*!< SLV2CMPD (Bit 27) */
+#define HRPWM_SLV5_RSTR_SLV2CMPD_Msk (0x8000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV2CMPB_Pos (26UL) /*!< SLV2CMPB (Bit 26) */
+#define HRPWM_SLV5_RSTR_SLV2CMPB_Msk (0x4000000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV2CMPA_Pos (25UL) /*!< SLV2CMPA (Bit 25) */
+#define HRPWM_SLV5_RSTR_SLV2CMPA_Msk (0x2000000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV5_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV5_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV5_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV5_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV5_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV5_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV5_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV5_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV5_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV5_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV5_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV5_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV5_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV5_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV5_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV5_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV5_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV5_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV5_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV5_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV5_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV5_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV5_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV5_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTR_SLV4CMPA_Pos (0UL) /*!< SLV4CMPA (Bit 0) */
+#define HRPWM_SLV5_RSTR_SLV4CMPA_Msk (0x1UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV5_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV5_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV5_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV5_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTER_SLV6CMPD_Pos (2UL) /*!< SLV6CMPD (Bit 2) */
+#define HRPWM_SLV5_RSTER_SLV6CMPD_Msk (0x4UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTER_SLV6CMPB_Pos (1UL) /*!< SLV6CMPB (Bit 1) */
+#define HRPWM_SLV5_RSTER_SLV6CMPB_Msk (0x2UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_RSTER_SLV6CMPA_Pos (0UL) /*!< SLV6CMPA (Bit 0) */
+#define HRPWM_SLV5_RSTER_SLV6CMPA_Msk (0x1UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV5_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV5_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV5_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV5_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV5_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV5_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV5_CAPACR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV5_CAPACR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV5_CAPACR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV5_CAPACR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV5_CAPACR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV5_CAPACR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV5_CAPACR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV5_CAPACR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV5_CAPACR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV5_CAPACR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV5_CAPACR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV5_CAPACR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV5_CAPACR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV5_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV5_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV5_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV5_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV5_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV5_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV5_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV5_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV5_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV5_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV5_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV5_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV5_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV5_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV5_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV5_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV5_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV5_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV5_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV5_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV5_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV5_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV5_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV5_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV5_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV5_CAPACER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV5_CAPACER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV5_CAPACER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPACER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV5_CAPACER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV5_CAPBCR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV5_CAPBCR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV5_CAPBCR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV5_CAPBCR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV5_CAPBCR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV5_CAPBCR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV5_CAPBCR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV5_CAPBCR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV5_CAPBCR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV5_CAPBCR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV5_CAPBCR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV5_CAPBCR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV5_CAPBCR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV5_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV5_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV5_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV5_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV5_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV5_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV5_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV5_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV5_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV5_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV5_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV5_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV5_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV5_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV5_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV5_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV6CMPB_Pos (3UL) /*!< SLV6CMPB (Bit 3) */
+#define HRPWM_SLV5_CAPBCER_SLV6CMPB_Msk (0x8UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV6CMPA_Pos (2UL) /*!< SLV6CMPA (Bit 2) */
+#define HRPWM_SLV5_CAPBCER_SLV6CMPA_Msk (0x4UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV6CLRA_Pos (1UL) /*!< SLV6CLRA (Bit 1) */
+#define HRPWM_SLV5_CAPBCER_SLV6CLRA_Msk (0x2UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_CAPBCER_SLV6SETA_Pos (0UL) /*!< SLV6SETA (Bit 0) */
+#define HRPWM_SLV5_CAPBCER_SLV6SETA_Msk (0x1UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV5_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV5_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV5_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV5_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV5_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV5_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV5_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV5_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV5_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV5_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV5_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV5_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV5_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV5_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV5_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV5_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV5_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV5_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV5_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV5_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV5_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV5_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV5_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV5_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV5_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV5_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV5_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV5_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV5_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV5_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV5_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV5_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV5_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV5_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV5_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV5_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV5_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV5_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV5_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV5_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV5_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV5_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV5_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV5_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV5_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV5_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV5_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV5_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV5_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV5_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV5_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV5_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV5_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV5_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV5_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV5_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV5_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV5_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV5_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV5_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV5_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV5_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV6 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV6_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV6_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV6_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV6_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV6_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV6_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV6_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV6_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV6_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV6_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV6_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV6_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV6_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV6_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV6_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV6_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV6_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV6_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV6_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV6_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV6_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV6_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV6_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV6_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV6_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV6_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV6_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV6_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV6_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV6_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV6_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV6_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV6_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV6_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV6_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV6_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV6_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV6_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV6_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV6_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV6_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV6_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV6_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV6_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV6_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV6_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV6_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV6_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV6_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV6_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV6_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV6_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV6_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV6_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV6_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV6_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV6_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV6_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV6_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV6_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV6_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV6_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV6_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV6_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV6_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV6_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV6_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV6_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV6_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV6_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV6_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV6_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV6_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV6_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV6_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV6_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV6_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV6_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV6_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV6_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV6_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV6_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV6_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV6_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV6_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV6_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV6_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV6_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV6_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV6_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV6_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV6_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV6_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV6_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV6_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV6_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV6_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV6_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV6_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV6_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV6_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV6_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV6_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV6_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV6_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV6_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV6_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV6_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV6_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV6_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV6_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV6_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV6_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV6_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV6_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV6_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV6_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV6_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV6_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV6_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV6_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV6_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV6_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV6_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV6_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV6_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV6_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV6_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV6_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV6_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV6_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV6_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV6_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV6_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV6_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV6_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV6_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV6_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV6_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV6_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV6_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV6_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV6_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV6_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV6_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV6_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV6_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV6_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV6_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV6_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV6_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV6_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV6_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV6_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV6_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV6_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV6_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV6_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV6_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV6_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV6_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV6_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV6_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV6_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV6_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV6_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV6_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV6_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV6_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV6_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV6_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV6_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV6_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV6_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV6_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV6_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV6_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV6_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV6_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV6_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV6_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV6_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV6_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV6_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV6_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV6_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV6_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV6_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV6_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV6_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV6_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV6_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV6_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV6_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV6_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV6_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV6_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV6_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV6_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV6_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV6_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV6_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV6_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV6_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV6_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV6_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV6_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV6_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV6_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV6_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV6_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV6_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV6_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV6_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV6_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV6_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV6_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV6_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV6_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV6_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV6_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV6_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV6_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV6_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV6_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV6_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV6_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV6_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV6_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV6_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV6_RSTR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV6_RSTR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV3CMPD_Pos (30UL) /*!< SLV3CMPD (Bit 30) */
+#define HRPWM_SLV6_RSTR_SLV3CMPD_Msk (0x40000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV3CMPB_Pos (29UL) /*!< SLV3CMPB (Bit 29) */
+#define HRPWM_SLV6_RSTR_SLV3CMPB_Msk (0x20000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV3CMPA_Pos (28UL) /*!< SLV3CMPA (Bit 28) */
+#define HRPWM_SLV6_RSTR_SLV3CMPA_Msk (0x10000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV2CMPD_Pos (27UL) /*!< SLV2CMPD (Bit 27) */
+#define HRPWM_SLV6_RSTR_SLV2CMPD_Msk (0x8000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV2CMPB_Pos (26UL) /*!< SLV2CMPB (Bit 26) */
+#define HRPWM_SLV6_RSTR_SLV2CMPB_Msk (0x4000000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV2CMPA_Pos (25UL) /*!< SLV2CMPA (Bit 25) */
+#define HRPWM_SLV6_RSTR_SLV2CMPA_Msk (0x2000000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV6_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV6_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV6_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV6_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV6_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV6_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV6_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV6_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV6_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV6_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV6_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV6_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV6_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV6_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV6_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV6_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV6_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV6_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV6_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV6_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV6_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV6_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV6_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV6_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTR_SLV4CMPA_Pos (0UL) /*!< SLV4CMPA (Bit 0) */
+#define HRPWM_SLV6_RSTR_SLV4CMPA_Msk (0x1UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV6_RSTER_SLV7CMPD_Pos (5UL) /*!< SLV7CMPD (Bit 5) */
+#define HRPWM_SLV6_RSTER_SLV7CMPD_Msk (0x20UL) /*!< SLV7CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTER_SLV7CMPB_Pos (4UL) /*!< SLV7CMPB (Bit 4) */
+#define HRPWM_SLV6_RSTER_SLV7CMPB_Msk (0x10UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTER_SLV7CMPA_Pos (3UL) /*!< SLV7CMPA (Bit 3) */
+#define HRPWM_SLV6_RSTER_SLV7CMPA_Msk (0x8UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTER_SLV5CMPD_Pos (2UL) /*!< SLV5CMPD (Bit 2) */
+#define HRPWM_SLV6_RSTER_SLV5CMPD_Msk (0x4UL) /*!< SLV5CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTER_SLV5CMPB_Pos (1UL) /*!< SLV5CMPB (Bit 1) */
+#define HRPWM_SLV6_RSTER_SLV5CMPB_Msk (0x2UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_RSTER_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV6_RSTER_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV6_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV6_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV6_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV6_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV6_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV6_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV6_CAPACR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV6_CAPACR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV6_CAPACR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV6_CAPACR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV6_CAPACR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV6_CAPACR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV6_CAPACR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV6_CAPACR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV6_CAPACR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV6_CAPACR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV6_CAPACR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV6_CAPACR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV6_CAPACR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV6_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV6_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV6_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV6_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV6_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV6_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV6_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV6_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV6_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV6_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV6_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV6_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV6_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV6_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV6_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV6_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV6_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV6_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV6_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV6_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV6_CAPACER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV6_CAPACER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV6_CAPACER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV6_CAPACER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV6_CAPACER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV5CMPB_Pos (3UL) /*!< SLV5CMPB (Bit 3) */
+#define HRPWM_SLV6_CAPACER_SLV5CMPB_Msk (0x8UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV5CMPA_Pos (2UL) /*!< SLV5CMPA (Bit 2) */
+#define HRPWM_SLV6_CAPACER_SLV5CMPA_Msk (0x4UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV5CLRA_Pos (1UL) /*!< SLV5CLRA (Bit 1) */
+#define HRPWM_SLV6_CAPACER_SLV5CLRA_Msk (0x2UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPACER_SLV5SETA_Pos (0UL) /*!< SLV5SETA (Bit 0) */
+#define HRPWM_SLV6_CAPACER_SLV5SETA_Msk (0x1UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV6_CAPBCR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV6_CAPBCR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV6_CAPBCR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV6_CAPBCR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV6_CAPBCR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV6_CAPBCR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV6_CAPBCR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV6_CAPBCR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV6_CAPBCR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV6_CAPBCR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV6_CAPBCR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV6_CAPBCR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV6_CAPBCR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV6_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV6_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV6_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV6_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV6_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV6_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV6_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV6_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV6_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV6_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV6_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV6_CAPBCER_SLV7CMPB_Pos (7UL) /*!< SLV7CMPB (Bit 7) */
+#define HRPWM_SLV6_CAPBCER_SLV7CMPB_Msk (0x80UL) /*!< SLV7CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV7CMPA_Pos (6UL) /*!< SLV7CMPA (Bit 6) */
+#define HRPWM_SLV6_CAPBCER_SLV7CMPA_Msk (0x40UL) /*!< SLV7CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV7CLRA_Pos (5UL) /*!< SLV7CLRA (Bit 5) */
+#define HRPWM_SLV6_CAPBCER_SLV7CLRA_Msk (0x20UL) /*!< SLV7CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV7SETA_Pos (4UL) /*!< SLV7SETA (Bit 4) */
+#define HRPWM_SLV6_CAPBCER_SLV7SETA_Msk (0x10UL) /*!< SLV7SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV5CMPB_Pos (3UL) /*!< SLV5CMPB (Bit 3) */
+#define HRPWM_SLV6_CAPBCER_SLV5CMPB_Msk (0x8UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV5CMPA_Pos (2UL) /*!< SLV5CMPA (Bit 2) */
+#define HRPWM_SLV6_CAPBCER_SLV5CMPA_Msk (0x4UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV5CLRA_Pos (1UL) /*!< SLV5CLRA (Bit 1) */
+#define HRPWM_SLV6_CAPBCER_SLV5CLRA_Msk (0x2UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_CAPBCER_SLV5SETA_Pos (0UL) /*!< SLV5SETA (Bit 0) */
+#define HRPWM_SLV6_CAPBCER_SLV5SETA_Msk (0x1UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV6_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV6_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV6_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV6_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV6_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV6_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV6_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV6_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV6_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV6_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV6_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV6_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV6_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV6_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV6_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV6_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV6_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV6_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV6_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV6_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV6_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV6_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV6_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV6_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV6_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV6_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV6_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV6_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV6_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV6_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV6_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV6_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV6_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV6_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV6_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV6_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV6_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV6_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV6_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV6_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV6_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV6_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV6_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV6_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV6_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV6_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV6_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV6_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV6_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV6_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV6_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV6_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV6_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV6_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV6_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV6_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV6_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV6_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV6_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV6_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV6_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV6_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_SLV7 ================ */
+/* =========================================================================================================================== */
+
+/* ======================================================== PWMCR0 ========================================================= */
+#define HRPWM_SLV7_PWMCR0_UPDGAT_Pos (28UL) /*!< UPDGAT (Bit 28) */
+#define HRPWM_SLV7_PWMCR0_UPDGAT_Msk (0xf0000000UL) /*!< UPDGAT (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_PWMCR0_UPDREP_Pos (27UL) /*!< UPDREP (Bit 27) */
+#define HRPWM_SLV7_PWMCR0_UPDREP_Msk (0x8000000UL) /*!< UPDREP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_UPDRST_Pos (26UL) /*!< UPDRST (Bit 26) */
+#define HRPWM_SLV7_PWMCR0_UPDRST_Msk (0x4000000UL) /*!< UPDRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_SLV7_PWMCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_SLV7_PWMCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR0_GTCMPC_Pos (22UL) /*!< GTCMPC (Bit 22) */
+#define HRPWM_SLV7_PWMCR0_GTCMPC_Msk (0x400000UL) /*!< GTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_GTCMPA_Pos (21UL) /*!< GTCMPA (Bit 21) */
+#define HRPWM_SLV7_PWMCR0_GTCMPA_Msk (0x200000UL) /*!< GTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_TRGHLF_Pos (20UL) /*!< TRGHLF (Bit 20) */
+#define HRPWM_SLV7_PWMCR0_TRGHLF_Msk (0x100000UL) /*!< TRGHLF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_DELCMPD_Pos (18UL) /*!< DELCMPD (Bit 18) */
+#define HRPWM_SLV7_PWMCR0_DELCMPD_Msk (0xc0000UL) /*!< DELCMPD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR0_DELCMPB_Pos (16UL) /*!< DELCMPB (Bit 16) */
+#define HRPWM_SLV7_PWMCR0_DELCMPB_Msk (0x30000UL) /*!< DELCMPB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR0_SYNCSTRT_Pos (11UL) /*!< SYNCSTRT (Bit 11) */
+#define HRPWM_SLV7_PWMCR0_SYNCSTRT_Msk (0x800UL) /*!< SYNCSTRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_SYNCRST_Pos (10UL) /*!< SYNCRST (Bit 10) */
+#define HRPWM_SLV7_PWMCR0_SYNCRST_Msk (0x400UL) /*!< SYNCRST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_RSYNCU_Pos (9UL) /*!< RSYNCU (Bit 9) */
+#define HRPWM_SLV7_PWMCR0_RSYNCU_Msk (0x200UL) /*!< RSYNCU (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_PSHPLL_Pos (8UL) /*!< PSHPLL (Bit 8) */
+#define HRPWM_SLV7_PWMCR0_PSHPLL_Msk (0x100UL) /*!< PSHPLL (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_SLV7_PWMCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_SLV7_PWMCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_SLV7_PWMCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_SLV7_PWMCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_SLV7_PWMCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ======================================================== PWMCR1 ========================================================= */
+#define HRPWM_SLV7_PWMCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_SLV7_PWMCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD7_Pos (24UL) /*!< UPD7 (Bit 24) */
+#define HRPWM_SLV7_PWMCR1_UPD7_Msk (0x1000000UL) /*!< UPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD6_Pos (23UL) /*!< UPD6 (Bit 23) */
+#define HRPWM_SLV7_PWMCR1_UPD6_Msk (0x800000UL) /*!< UPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD5_Pos (22UL) /*!< UPD5 (Bit 22) */
+#define HRPWM_SLV7_PWMCR1_UPD5_Msk (0x400000UL) /*!< UPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD4_Pos (21UL) /*!< UPD4 (Bit 21) */
+#define HRPWM_SLV7_PWMCR1_UPD4_Msk (0x200000UL) /*!< UPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD3_Pos (20UL) /*!< UPD3 (Bit 20) */
+#define HRPWM_SLV7_PWMCR1_UPD3_Msk (0x100000UL) /*!< UPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD2_Pos (19UL) /*!< UPD2 (Bit 19) */
+#define HRPWM_SLV7_PWMCR1_UPD2_Msk (0x80000UL) /*!< UPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD1_Pos (18UL) /*!< UPD1 (Bit 18) */
+#define HRPWM_SLV7_PWMCR1_UPD1_Msk (0x40000UL) /*!< UPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UPD0_Pos (17UL) /*!< UPD0 (Bit 17) */
+#define HRPWM_SLV7_PWMCR1_UPD0_Msk (0x20000UL) /*!< UPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_MUPD_Pos (16UL) /*!< MUPD (Bit 16) */
+#define HRPWM_SLV7_PWMCR1_MUPD_Msk (0x10000UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_FLTROM_Pos (14UL) /*!< FLTROM (Bit 14) */
+#define HRPWM_SLV7_PWMCR1_FLTROM_Msk (0xc000UL) /*!< FLTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR1_EEVROM_Pos (12UL) /*!< EEVROM (Bit 12) */
+#define HRPWM_SLV7_PWMCR1_EEVROM_Msk (0x3000UL) /*!< EEVROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR1_ADROM_Pos (10UL) /*!< ADROM (Bit 10) */
+#define HRPWM_SLV7_PWMCR1_ADROM_Msk (0xc00UL) /*!< ADROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR1_OUTROM_Pos (8UL) /*!< OUTROM (Bit 8) */
+#define HRPWM_SLV7_PWMCR1_OUTROM_Msk (0x300UL) /*!< OUTROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR1_ROM_Pos (6UL) /*!< ROM (Bit 6) */
+#define HRPWM_SLV7_PWMCR1_ROM_Msk (0xc0UL) /*!< ROM (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_PWMCR1_CAPBM_Pos (5UL) /*!< CAPBM (Bit 5) */
+#define HRPWM_SLV7_PWMCR1_CAPBM_Msk (0x20UL) /*!< CAPBM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_UDM_Pos (4UL) /*!< UDM (Bit 4) */
+#define HRPWM_SLV7_PWMCR1_UDM_Msk (0x10UL) /*!< UDM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_CAPAM_Pos (3UL) /*!< CAPAM (Bit 3) */
+#define HRPWM_SLV7_PWMCR1_CAPAM_Msk (0x8UL) /*!< CAPAM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_DCDR_Pos (2UL) /*!< DCDR (Bit 2) */
+#define HRPWM_SLV7_PWMCR1_DCDR_Msk (0x4UL) /*!< DCDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_DCDS_Pos (1UL) /*!< DCDS (Bit 1) */
+#define HRPWM_SLV7_PWMCR1_DCDS_Msk (0x2UL) /*!< DCDS (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMCR1_DCDE_Pos (0UL) /*!< DCDE (Bit 0) */
+#define HRPWM_SLV7_PWMCR1_DCDE_Msk (0x1UL) /*!< DCDE (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMISR ========================================================= */
+#define HRPWM_SLV7_PWMISR_OUTB_Pos (21UL) /*!< OUTB (Bit 21) */
+#define HRPWM_SLV7_PWMISR_OUTB_Msk (0x200000UL) /*!< OUTB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_OUTA_Pos (20UL) /*!< OUTA (Bit 20) */
+#define HRPWM_SLV7_PWMISR_OUTA_Msk (0x100000UL) /*!< OUTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_OUTBSTA_Pos (19UL) /*!< OUTBSTA (Bit 19) */
+#define HRPWM_SLV7_PWMISR_OUTBSTA_Msk (0x80000UL) /*!< OUTBSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_OUTASTA_Pos (18UL) /*!< OUTASTA (Bit 18) */
+#define HRPWM_SLV7_PWMISR_OUTASTA_Msk (0x40000UL) /*!< OUTASTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_IPPSTA_Pos (17UL) /*!< IPPSTA (Bit 17) */
+#define HRPWM_SLV7_PWMISR_IPPSTA_Msk (0x20000UL) /*!< IPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CPPSTA_Pos (16UL) /*!< CPPSTA (Bit 16) */
+#define HRPWM_SLV7_PWMISR_CPPSTA_Msk (0x10000UL) /*!< CPPSTA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_DLYPRT_Pos (14UL) /*!< DLYPRT (Bit 14) */
+#define HRPWM_SLV7_PWMISR_DLYPRT_Msk (0x4000UL) /*!< DLYPRT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CAPB_Pos (13UL) /*!< CAPB (Bit 13) */
+#define HRPWM_SLV7_PWMISR_CAPB_Msk (0x2000UL) /*!< CAPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CAPA_Pos (12UL) /*!< CAPA (Bit 12) */
+#define HRPWM_SLV7_PWMISR_CAPA_Msk (0x1000UL) /*!< CAPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_REP_Pos (11UL) /*!< REP (Bit 11) */
+#define HRPWM_SLV7_PWMISR_REP_Msk (0x800UL) /*!< REP (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_RST_Pos (10UL) /*!< RST (Bit 10) */
+#define HRPWM_SLV7_PWMISR_RST_Msk (0x400UL) /*!< RST (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CLRB_Pos (9UL) /*!< CLRB (Bit 9) */
+#define HRPWM_SLV7_PWMISR_CLRB_Msk (0x200UL) /*!< CLRB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_SETB_Pos (8UL) /*!< SETB (Bit 8) */
+#define HRPWM_SLV7_PWMISR_SETB_Msk (0x100UL) /*!< SETB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CLRA_Pos (7UL) /*!< CLRA (Bit 7) */
+#define HRPWM_SLV7_PWMISR_CLRA_Msk (0x80UL) /*!< CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_SETA_Pos (6UL) /*!< SETA (Bit 6) */
+#define HRPWM_SLV7_PWMISR_SETA_Msk (0x40UL) /*!< SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_UPD_Pos (5UL) /*!< UPD (Bit 5) */
+#define HRPWM_SLV7_PWMISR_UPD_Msk (0x20UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_PER_Pos (4UL) /*!< PER (Bit 4) */
+#define HRPWM_SLV7_PWMISR_PER_Msk (0x10UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CMPD_Pos (3UL) /*!< CMPD (Bit 3) */
+#define HRPWM_SLV7_PWMISR_CMPD_Msk (0x8UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CMPC_Pos (2UL) /*!< CMPC (Bit 2) */
+#define HRPWM_SLV7_PWMISR_CMPC_Msk (0x4UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CMPB_Pos (1UL) /*!< CMPB (Bit 1) */
+#define HRPWM_SLV7_PWMISR_CMPB_Msk (0x2UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMISR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV7_PWMISR_CMPA_Msk (0x1UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== PWMDIER ======================================================== */
+#define HRPWM_SLV7_PWMDIER_DLYPRTDE_Pos (30UL) /*!< DLYPRTDE (Bit 30) */
+#define HRPWM_SLV7_PWMDIER_DLYPRTDE_Msk (0x40000000UL) /*!< DLYPRTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CAPBDE_Pos (29UL) /*!< CAPBDE (Bit 29) */
+#define HRPWM_SLV7_PWMDIER_CAPBDE_Msk (0x20000000UL) /*!< CAPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CAPADE_Pos (28UL) /*!< CAPADE (Bit 28) */
+#define HRPWM_SLV7_PWMDIER_CAPADE_Msk (0x10000000UL) /*!< CAPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_REPDE_Pos (27UL) /*!< REPDE (Bit 27) */
+#define HRPWM_SLV7_PWMDIER_REPDE_Msk (0x8000000UL) /*!< REPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_RSTDE_Pos (26UL) /*!< RSTDE (Bit 26) */
+#define HRPWM_SLV7_PWMDIER_RSTDE_Msk (0x4000000UL) /*!< RSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CLRBDE_Pos (25UL) /*!< CLRBDE (Bit 25) */
+#define HRPWM_SLV7_PWMDIER_CLRBDE_Msk (0x2000000UL) /*!< CLRBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_SETBDE_Pos (24UL) /*!< SETBDE (Bit 24) */
+#define HRPWM_SLV7_PWMDIER_SETBDE_Msk (0x1000000UL) /*!< SETBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CLRADE_Pos (23UL) /*!< CLRADE (Bit 23) */
+#define HRPWM_SLV7_PWMDIER_CLRADE_Msk (0x800000UL) /*!< CLRADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_SETADE_Pos (22UL) /*!< SETADE (Bit 22) */
+#define HRPWM_SLV7_PWMDIER_SETADE_Msk (0x400000UL) /*!< SETADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_UPDDE_Pos (21UL) /*!< UPDDE (Bit 21) */
+#define HRPWM_SLV7_PWMDIER_UPDDE_Msk (0x200000UL) /*!< UPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_PERDE_Pos (20UL) /*!< PERDE (Bit 20) */
+#define HRPWM_SLV7_PWMDIER_PERDE_Msk (0x100000UL) /*!< PERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPDDE_Pos (19UL) /*!< CMPDDE (Bit 19) */
+#define HRPWM_SLV7_PWMDIER_CMPDDE_Msk (0x80000UL) /*!< CMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPCDE_Pos (18UL) /*!< CMPCDE (Bit 18) */
+#define HRPWM_SLV7_PWMDIER_CMPCDE_Msk (0x40000UL) /*!< CMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPBDE_Pos (17UL) /*!< CMPBDE (Bit 17) */
+#define HRPWM_SLV7_PWMDIER_CMPBDE_Msk (0x20000UL) /*!< CMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPADE_Pos (16UL) /*!< CMPADE (Bit 16) */
+#define HRPWM_SLV7_PWMDIER_CMPADE_Msk (0x10000UL) /*!< CMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_DLYPRTIE_Pos (14UL) /*!< DLYPRTIE (Bit 14) */
+#define HRPWM_SLV7_PWMDIER_DLYPRTIE_Msk (0x4000UL) /*!< DLYPRTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CAPBIE_Pos (13UL) /*!< CAPBIE (Bit 13) */
+#define HRPWM_SLV7_PWMDIER_CAPBIE_Msk (0x2000UL) /*!< CAPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CAPAIE_Pos (12UL) /*!< CAPAIE (Bit 12) */
+#define HRPWM_SLV7_PWMDIER_CAPAIE_Msk (0x1000UL) /*!< CAPAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_REPIE_Pos (11UL) /*!< REPIE (Bit 11) */
+#define HRPWM_SLV7_PWMDIER_REPIE_Msk (0x800UL) /*!< REPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_RSTIE_Pos (10UL) /*!< RSTIE (Bit 10) */
+#define HRPWM_SLV7_PWMDIER_RSTIE_Msk (0x400UL) /*!< RSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CLRBIE_Pos (9UL) /*!< CLRBIE (Bit 9) */
+#define HRPWM_SLV7_PWMDIER_CLRBIE_Msk (0x200UL) /*!< CLRBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_SETBIE_Pos (8UL) /*!< SETBIE (Bit 8) */
+#define HRPWM_SLV7_PWMDIER_SETBIE_Msk (0x100UL) /*!< SETBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CLRAIE_Pos (7UL) /*!< CLRAIE (Bit 7) */
+#define HRPWM_SLV7_PWMDIER_CLRAIE_Msk (0x80UL) /*!< CLRAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_SETAIE_Pos (6UL) /*!< SETAIE (Bit 6) */
+#define HRPWM_SLV7_PWMDIER_SETAIE_Msk (0x40UL) /*!< SETAIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_UPDIE_Pos (5UL) /*!< UPDIE (Bit 5) */
+#define HRPWM_SLV7_PWMDIER_UPDIE_Msk (0x20UL) /*!< UPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_PERIE_Pos (4UL) /*!< PERIE (Bit 4) */
+#define HRPWM_SLV7_PWMDIER_PERIE_Msk (0x10UL) /*!< PERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPDIE_Pos (3UL) /*!< CMPDIE (Bit 3) */
+#define HRPWM_SLV7_PWMDIER_CMPDIE_Msk (0x8UL) /*!< CMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPCIE_Pos (2UL) /*!< CMPCIE (Bit 2) */
+#define HRPWM_SLV7_PWMDIER_CMPCIE_Msk (0x4UL) /*!< CMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPBIE_Pos (1UL) /*!< CMPBIE (Bit 1) */
+#define HRPWM_SLV7_PWMDIER_CMPBIE_Msk (0x2UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_PWMDIER_CMPAIE_Pos (0UL) /*!< CMPAIE (Bit 0) */
+#define HRPWM_SLV7_PWMDIER_CMPAIE_Msk (0x1UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= CNTR ========================================================== */
+#define HRPWM_SLV7_CNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_SLV7_CNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_SLV7_CNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define HRPWM_SLV7_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= PERR ========================================================== */
+#define HRPWM_SLV7_PERR_PER_Pos (0UL) /*!< PER (Bit 0) */
+#define HRPWM_SLV7_PERR_PER_Msk (0xffffUL) /*!< PER (Bitfield-Mask: 0xffff) */
+/* ========================================================= REPR ========================================================== */
+#define HRPWM_SLV7_REPR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define HRPWM_SLV7_REPR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CMPAR ========================================================= */
+#define HRPWM_SLV7_CMPAR_CMPA_Pos (0UL) /*!< CMPA (Bit 0) */
+#define HRPWM_SLV7_CMPAR_CMPA_Msk (0xffffUL) /*!< CMPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPBR ========================================================= */
+#define HRPWM_SLV7_CMPBR_CMPB_Pos (0UL) /*!< CMPB (Bit 0) */
+#define HRPWM_SLV7_CMPBR_CMPB_Msk (0xffffUL) /*!< CMPB (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPCR ========================================================= */
+#define HRPWM_SLV7_CMPCR_CMPC_Pos (0UL) /*!< CMPC (Bit 0) */
+#define HRPWM_SLV7_CMPCR_CMPC_Msk (0xffffUL) /*!< CMPC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CMPDR ========================================================= */
+#define HRPWM_SLV7_CMPDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
+#define HRPWM_SLV7_CMPDR_CMPD_Msk (0xffffUL) /*!< CMPD (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPAR ========================================================= */
+#define HRPWM_SLV7_CAPAR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV7_CAPAR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPAR_CAPA_Pos (0UL) /*!< CAPA (Bit 0) */
+#define HRPWM_SLV7_CAPAR_CAPA_Msk (0xffffUL) /*!< CAPA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CAPBR ========================================================= */
+#define HRPWM_SLV7_CAPBR_DIR_Pos (16UL) /*!< DIR (Bit 16) */
+#define HRPWM_SLV7_CAPBR_DIR_Msk (0x10000UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBR_CAPB_Pos (0UL) /*!< CAPB (Bit 0) */
+#define HRPWM_SLV7_CAPBR_CAPB_Msk (0xffffUL) /*!< CAPB (Bitfield-Mask: 0xffff) */
+/* ========================================================== DTR ========================================================== */
+#define HRPWM_SLV7_DTR_SDTF_Pos (28UL) /*!< SDTF (Bit 28) */
+#define HRPWM_SLV7_DTR_SDTF_Msk (0x10000000UL) /*!< SDTF (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DTR_DTF_Pos (16UL) /*!< DTF (Bit 16) */
+#define HRPWM_SLV7_DTR_DTF_Msk (0xfff0000UL) /*!< DTF (Bitfield-Mask: 0xfff) */
+#define HRPWM_SLV7_DTR_SDTR_Pos (12UL) /*!< SDTR (Bit 12) */
+#define HRPWM_SLV7_DTR_SDTR_Msk (0x1000UL) /*!< SDTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DTR_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define HRPWM_SLV7_DTR_DTR_Msk (0xfffUL) /*!< DTR (Bitfield-Mask: 0xfff) */
+/* ========================================================= SETAR ========================================================= */
+#define HRPWM_SLV7_SETAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV7_SETAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV7_SETAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV7_SETAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV7_SETAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV7_SETAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV7_SETAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV7_SETAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV7_SETAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV7_SETAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV7_SETAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV7_SETAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV7_SETAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV7_SETAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV7_SETAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV7_SETAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV7_SETAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV7_SETAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV7_SETAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV7_SETAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV7_SETAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV7_SETAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV7_SETAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV7_SETAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRAR ========================================================= */
+#define HRPWM_SLV7_CLRAR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV7_CLRAR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV7_CLRAR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV7_CLRAR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV7_CLRAR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV7_CLRAR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV7_CLRAR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV7_CLRAR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV7_CLRAR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV7_CLRAR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV7_CLRAR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV7_CLRAR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV7_CLRAR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV7_CLRAR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRAR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV7_CLRAR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= SETBR ========================================================= */
+#define HRPWM_SLV7_SETBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV7_SETBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV7_SETBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV7_SETBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV7_SETBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV7_SETBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV7_SETBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV7_SETBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV7_SETBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV7_SETBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV7_SETBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV7_SETBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV7_SETBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV7_SETBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV7_SETBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV7_SETBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV7_SETBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV7_SETBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV7_SETBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV7_SETBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV7_SETBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV7_SETBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV7_SETBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_SETBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV7_SETBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= CLRBR ========================================================= */
+#define HRPWM_SLV7_CLRBR_UPD_Pos (22UL) /*!< UPD (Bit 22) */
+#define HRPWM_SLV7_CLRBR_UPD_Msk (0x400000UL) /*!< UPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_RESYNC_Pos (21UL) /*!< RESYNC (Bit 21) */
+#define HRPWM_SLV7_CLRBR_RESYNC_Msk (0x200000UL) /*!< RESYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT9_Pos (20UL) /*!< EXTEVNT9 (Bit 20) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT9_Msk (0x100000UL) /*!< EXTEVNT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT8_Pos (19UL) /*!< EXTEVNT8 (Bit 19) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT8_Msk (0x80000UL) /*!< EXTEVNT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT7_Pos (18UL) /*!< EXTEVNT7 (Bit 18) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT7_Msk (0x40000UL) /*!< EXTEVNT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT6_Pos (17UL) /*!< EXTEVNT6 (Bit 17) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT6_Msk (0x20000UL) /*!< EXTEVNT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT5_Pos (16UL) /*!< EXTEVNT5 (Bit 16) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT5_Msk (0x10000UL) /*!< EXTEVNT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT4_Pos (15UL) /*!< EXTEVNT4 (Bit 15) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT4_Msk (0x8000UL) /*!< EXTEVNT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT3_Pos (14UL) /*!< EXTEVNT3 (Bit 14) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT3_Msk (0x4000UL) /*!< EXTEVNT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT2_Pos (13UL) /*!< EXTEVNT2 (Bit 13) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT2_Msk (0x2000UL) /*!< EXTEVNT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT1_Pos (12UL) /*!< EXTEVNT1 (Bit 12) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT1_Msk (0x1000UL) /*!< EXTEVNT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT0_Pos (11UL) /*!< EXTEVNT0 (Bit 11) */
+#define HRPWM_SLV7_CLRBR_EXTEVNT0_Msk (0x800UL) /*!< EXTEVNT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_MSTPER_Pos (10UL) /*!< MSTPER (Bit 10) */
+#define HRPWM_SLV7_CLRBR_MSTPER_Msk (0x400UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_MSTCMPD_Pos (9UL) /*!< MSTCMPD (Bit 9) */
+#define HRPWM_SLV7_CLRBR_MSTCMPD_Msk (0x200UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_MSTCMPC_Pos (8UL) /*!< MSTCMPC (Bit 8) */
+#define HRPWM_SLV7_CLRBR_MSTCMPC_Msk (0x100UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_MSTCMPB_Pos (7UL) /*!< MSTCMPB (Bit 7) */
+#define HRPWM_SLV7_CLRBR_MSTCMPB_Msk (0x80UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_MSTCMPA_Pos (6UL) /*!< MSTCMPA (Bit 6) */
+#define HRPWM_SLV7_CLRBR_MSTCMPA_Msk (0x40UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_PER_Pos (5UL) /*!< PER (Bit 5) */
+#define HRPWM_SLV7_CLRBR_PER_Msk (0x20UL) /*!< PER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_CMPD_Pos (4UL) /*!< CMPD (Bit 4) */
+#define HRPWM_SLV7_CLRBR_CMPD_Msk (0x10UL) /*!< CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_CMPC_Pos (3UL) /*!< CMPC (Bit 3) */
+#define HRPWM_SLV7_CLRBR_CMPC_Msk (0x8UL) /*!< CMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_CMPB_Pos (2UL) /*!< CMPB (Bit 2) */
+#define HRPWM_SLV7_CLRBR_CMPB_Msk (0x4UL) /*!< CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_CMPA_Pos (1UL) /*!< CMPA (Bit 1) */
+#define HRPWM_SLV7_CLRBR_CMPA_Msk (0x2UL) /*!< CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CLRBR_SST_Pos (0UL) /*!< SST (Bit 0) */
+#define HRPWM_SLV7_CLRBR_SST_Msk (0x1UL) /*!< SST (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR0 ========================================================= */
+#define HRPWM_SLV7_EEFR0_EE4FLTR_Pos (21UL) /*!< EE4FLTR (Bit 21) */
+#define HRPWM_SLV7_EEFR0_EE4FLTR_Msk (0x1e00000UL) /*!< EE4FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR0_EE4LTCH_Pos (20UL) /*!< EE4LTCH (Bit 20) */
+#define HRPWM_SLV7_EEFR0_EE4LTCH_Msk (0x100000UL) /*!< EE4LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR0_EE3FLTR_Pos (16UL) /*!< EE3FLTR (Bit 16) */
+#define HRPWM_SLV7_EEFR0_EE3FLTR_Msk (0xf0000UL) /*!< EE3FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR0_EE3LTCH_Pos (15UL) /*!< EE3LTCH (Bit 15) */
+#define HRPWM_SLV7_EEFR0_EE3LTCH_Msk (0x8000UL) /*!< EE3LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR0_EE2FLTR_Pos (11UL) /*!< EE2FLTR (Bit 11) */
+#define HRPWM_SLV7_EEFR0_EE2FLTR_Msk (0x7800UL) /*!< EE2FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR0_EE2LTCH_Pos (10UL) /*!< EE2LTCH (Bit 10) */
+#define HRPWM_SLV7_EEFR0_EE2LTCH_Msk (0x400UL) /*!< EE2LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR0_EE1FLTR_Pos (6UL) /*!< EE1FLTR (Bit 6) */
+#define HRPWM_SLV7_EEFR0_EE1FLTR_Msk (0x3c0UL) /*!< EE1FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR0_EE1LTCH_Pos (5UL) /*!< EE1LTCH (Bit 5) */
+#define HRPWM_SLV7_EEFR0_EE1LTCH_Msk (0x20UL) /*!< EE1LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR0_EE0FLTR_Pos (1UL) /*!< EE0FLTR (Bit 1) */
+#define HRPWM_SLV7_EEFR0_EE0FLTR_Msk (0x1eUL) /*!< EE0FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR0_EE0LTCH_Pos (0UL) /*!< EE0LTCH (Bit 0) */
+#define HRPWM_SLV7_EEFR0_EE0LTCH_Msk (0x1UL) /*!< EE0LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR1 ========================================================= */
+#define HRPWM_SLV7_EEFR1_EE9FLTR_Pos (21UL) /*!< EE9FLTR (Bit 21) */
+#define HRPWM_SLV7_EEFR1_EE9FLTR_Msk (0x1e00000UL) /*!< EE9FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR1_EE9LTCH_Pos (20UL) /*!< EE9LTCH (Bit 20) */
+#define HRPWM_SLV7_EEFR1_EE9LTCH_Msk (0x100000UL) /*!< EE9LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR1_EE8FLTR_Pos (16UL) /*!< EE8FLTR (Bit 16) */
+#define HRPWM_SLV7_EEFR1_EE8FLTR_Msk (0xf0000UL) /*!< EE8FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR1_EE8LTCH_Pos (15UL) /*!< EE8LTCH (Bit 15) */
+#define HRPWM_SLV7_EEFR1_EE8LTCH_Msk (0x8000UL) /*!< EE8LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR1_EE7FLTR_Pos (11UL) /*!< EE7FLTR (Bit 11) */
+#define HRPWM_SLV7_EEFR1_EE7FLTR_Msk (0x7800UL) /*!< EE7FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR1_EE7LTCH_Pos (10UL) /*!< EE7LTCH (Bit 10) */
+#define HRPWM_SLV7_EEFR1_EE7LTCH_Msk (0x400UL) /*!< EE7LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR1_EE6FLTR_Pos (6UL) /*!< EE6FLTR (Bit 6) */
+#define HRPWM_SLV7_EEFR1_EE6FLTR_Msk (0x3c0UL) /*!< EE6FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR1_EE6LTCH_Pos (5UL) /*!< EE6LTCH (Bit 5) */
+#define HRPWM_SLV7_EEFR1_EE6LTCH_Msk (0x20UL) /*!< EE6LTCH (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR1_EE5FLTR_Pos (1UL) /*!< EE5FLTR (Bit 1) */
+#define HRPWM_SLV7_EEFR1_EE5FLTR_Msk (0x1eUL) /*!< EE5FLTR (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR1_EE5LTCH_Pos (0UL) /*!< EE5LTCH (Bit 0) */
+#define HRPWM_SLV7_EEFR1_EE5LTCH_Msk (0x1UL) /*!< EE5LTCH (Bitfield-Mask: 0x01) */
+/* ========================================================= EEFR2 ========================================================= */
+#define HRPWM_SLV7_EEFR2_EEVACNT_Pos (8UL) /*!< EEVACNT (Bit 8) */
+#define HRPWM_SLV7_EEFR2_EEVACNT_Msk (0x3f00UL) /*!< EEVACNT (Bitfield-Mask: 0x3f) */
+#define HRPWM_SLV7_EEFR2_EEVASEL_Pos (4UL) /*!< EEVASEL (Bit 4) */
+#define HRPWM_SLV7_EEFR2_EEVASEL_Msk (0xf0UL) /*!< EEVASEL (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_EEFR2_EEVARSTM_Pos (2UL) /*!< EEVARSTM (Bit 2) */
+#define HRPWM_SLV7_EEFR2_EEVARSTM_Msk (0x4UL) /*!< EEVARSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR2_EEVACRES_Pos (1UL) /*!< EEVACRES (Bit 1) */
+#define HRPWM_SLV7_EEFR2_EEVACRES_Msk (0x2UL) /*!< EEVACRES (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_EEFR2_EEVACE_Pos (0UL) /*!< EEVACE (Bit 0) */
+#define HRPWM_SLV7_EEFR2_EEVACE_Msk (0x1UL) /*!< EEVACE (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTR ========================================================== */
+#define HRPWM_SLV7_RSTR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV7_RSTR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV3CMPD_Pos (30UL) /*!< SLV3CMPD (Bit 30) */
+#define HRPWM_SLV7_RSTR_SLV3CMPD_Msk (0x40000000UL) /*!< SLV3CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV3CMPB_Pos (29UL) /*!< SLV3CMPB (Bit 29) */
+#define HRPWM_SLV7_RSTR_SLV3CMPB_Msk (0x20000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV3CMPA_Pos (28UL) /*!< SLV3CMPA (Bit 28) */
+#define HRPWM_SLV7_RSTR_SLV3CMPA_Msk (0x10000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV2CMPD_Pos (27UL) /*!< SLV2CMPD (Bit 27) */
+#define HRPWM_SLV7_RSTR_SLV2CMPD_Msk (0x8000000UL) /*!< SLV2CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV2CMPB_Pos (26UL) /*!< SLV2CMPB (Bit 26) */
+#define HRPWM_SLV7_RSTR_SLV2CMPB_Msk (0x4000000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV2CMPA_Pos (25UL) /*!< SLV2CMPA (Bit 25) */
+#define HRPWM_SLV7_RSTR_SLV2CMPA_Msk (0x2000000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV1CMPD_Pos (24UL) /*!< SLV1CMPD (Bit 24) */
+#define HRPWM_SLV7_RSTR_SLV1CMPD_Msk (0x1000000UL) /*!< SLV1CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV1CMPB_Pos (23UL) /*!< SLV1CMPB (Bit 23) */
+#define HRPWM_SLV7_RSTR_SLV1CMPB_Msk (0x800000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV1CMPA_Pos (22UL) /*!< SLV1CMPA (Bit 22) */
+#define HRPWM_SLV7_RSTR_SLV1CMPA_Msk (0x400000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV0CMPD_Pos (21UL) /*!< SLV0CMPD (Bit 21) */
+#define HRPWM_SLV7_RSTR_SLV0CMPD_Msk (0x200000UL) /*!< SLV0CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV0CMPB_Pos (20UL) /*!< SLV0CMPB (Bit 20) */
+#define HRPWM_SLV7_RSTR_SLV0CMPB_Msk (0x100000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV0CMPA_Pos (19UL) /*!< SLV0CMPA (Bit 19) */
+#define HRPWM_SLV7_RSTR_SLV0CMPA_Msk (0x80000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLVCMPD_Pos (18UL) /*!< SLVCMPD (Bit 18) */
+#define HRPWM_SLV7_RSTR_SLVCMPD_Msk (0x40000UL) /*!< SLVCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLVCMPB_Pos (17UL) /*!< SLVCMPB (Bit 17) */
+#define HRPWM_SLV7_RSTR_SLVCMPB_Msk (0x20000UL) /*!< SLVCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLVUPD_Pos (16UL) /*!< SLVUPD (Bit 16) */
+#define HRPWM_SLV7_RSTR_SLVUPD_Msk (0x10000UL) /*!< SLVUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT9_Pos (15UL) /*!< EXTEVT9 (Bit 15) */
+#define HRPWM_SLV7_RSTR_EXTEVT9_Msk (0x8000UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT8_Pos (14UL) /*!< EXTEVT8 (Bit 14) */
+#define HRPWM_SLV7_RSTR_EXTEVT8_Msk (0x4000UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT7_Pos (13UL) /*!< EXTEVT7 (Bit 13) */
+#define HRPWM_SLV7_RSTR_EXTEVT7_Msk (0x2000UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT6_Pos (12UL) /*!< EXTEVT6 (Bit 12) */
+#define HRPWM_SLV7_RSTR_EXTEVT6_Msk (0x1000UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT5_Pos (11UL) /*!< EXTEVT5 (Bit 11) */
+#define HRPWM_SLV7_RSTR_EXTEVT5_Msk (0x800UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT4_Pos (10UL) /*!< EXTEVT4 (Bit 10) */
+#define HRPWM_SLV7_RSTR_EXTEVT4_Msk (0x400UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT3_Pos (9UL) /*!< EXTEVT3 (Bit 9) */
+#define HRPWM_SLV7_RSTR_EXTEVT3_Msk (0x200UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT2_Pos (8UL) /*!< EXTEVT2 (Bit 8) */
+#define HRPWM_SLV7_RSTR_EXTEVT2_Msk (0x100UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT1_Pos (7UL) /*!< EXTEVT1 (Bit 7) */
+#define HRPWM_SLV7_RSTR_EXTEVT1_Msk (0x80UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_EXTEVT0_Pos (6UL) /*!< EXTEVT0 (Bit 6) */
+#define HRPWM_SLV7_RSTR_EXTEVT0_Msk (0x40UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_MSTPER_Pos (5UL) /*!< MSTPER (Bit 5) */
+#define HRPWM_SLV7_RSTR_MSTPER_Msk (0x20UL) /*!< MSTPER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_MSTCMPD_Pos (4UL) /*!< MSTCMPD (Bit 4) */
+#define HRPWM_SLV7_RSTR_MSTCMPD_Msk (0x10UL) /*!< MSTCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_MSTCMPC_Pos (3UL) /*!< MSTCMPC (Bit 3) */
+#define HRPWM_SLV7_RSTR_MSTCMPC_Msk (0x8UL) /*!< MSTCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_MSTCMPB_Pos (2UL) /*!< MSTCMPB (Bit 2) */
+#define HRPWM_SLV7_RSTR_MSTCMPB_Msk (0x4UL) /*!< MSTCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_MSTCMPA_Pos (1UL) /*!< MSTCMPA (Bit 1) */
+#define HRPWM_SLV7_RSTR_MSTCMPA_Msk (0x2UL) /*!< MSTCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTR_SLV4CMPA_Pos (0UL) /*!< SLV4CMPA (Bit 0) */
+#define HRPWM_SLV7_RSTR_SLV4CMPA_Msk (0x1UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= RSTER ========================================================= */
+#define HRPWM_SLV7_RSTER_SLV6CMPD_Pos (5UL) /*!< SLV6CMPD (Bit 5) */
+#define HRPWM_SLV7_RSTER_SLV6CMPD_Msk (0x20UL) /*!< SLV6CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTER_SLV6CMPB_Pos (4UL) /*!< SLV6CMPB (Bit 4) */
+#define HRPWM_SLV7_RSTER_SLV6CMPB_Msk (0x10UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTER_SLV6CMPA_Pos (3UL) /*!< SLV6CMPA (Bit 3) */
+#define HRPWM_SLV7_RSTER_SLV6CMPA_Msk (0x8UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTER_SLV5CMPD_Pos (2UL) /*!< SLV5CMPD (Bit 2) */
+#define HRPWM_SLV7_RSTER_SLV5CMPD_Msk (0x4UL) /*!< SLV5CMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTER_SLV5CMPB_Pos (1UL) /*!< SLV5CMPB (Bit 1) */
+#define HRPWM_SLV7_RSTER_SLV5CMPB_Msk (0x2UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_RSTER_SLV5CMPA_Pos (0UL) /*!< SLV5CMPA (Bit 0) */
+#define HRPWM_SLV7_RSTER_SLV5CMPA_Msk (0x1UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= CHPR ========================================================== */
+#define HRPWM_SLV7_CHPR_STRPW_Pos (12UL) /*!< STRPW (Bit 12) */
+#define HRPWM_SLV7_CHPR_STRPW_Msk (0xf000UL) /*!< STRPW (Bitfield-Mask: 0x0f) */
+#define HRPWM_SLV7_CHPR_CARDTY_Pos (6UL) /*!< CARDTY (Bit 6) */
+#define HRPWM_SLV7_CHPR_CARDTY_Msk (0x1c0UL) /*!< CARDTY (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV7_CHPR_CARFRQ_Pos (0UL) /*!< CARFRQ (Bit 0) */
+#define HRPWM_SLV7_CHPR_CARFRQ_Msk (0xfUL) /*!< CARFRQ (Bitfield-Mask: 0x0f) */
+/* ======================================================== CAPACR ========================================================= */
+#define HRPWM_SLV7_CAPACR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV7_CAPACR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV7_CAPACR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV7_CAPACR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV7_CAPACR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV7_CAPACR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV7_CAPACR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV7_CAPACR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV7_CAPACR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV7_CAPACR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV7_CAPACR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV7_CAPACR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV7_CAPACR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV7_CAPACR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV7_CAPACR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV7_CAPACR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV7_CAPACR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV7_CAPACR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV7_CAPACR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV7_CAPACR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV7_CAPACR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV7_CAPACR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV7_CAPACR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV7_CAPACR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV7_CAPACR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV7_CAPACR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV7_CAPACR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV7_CAPACR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV7_CAPACR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV7_CAPACR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV7_CAPACR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV7_CAPACR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV7_CAPACR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPACER ======================================================== */
+#define HRPWM_SLV7_CAPACER_SLV6CMPB_Pos (7UL) /*!< SLV6CMPB (Bit 7) */
+#define HRPWM_SLV7_CAPACER_SLV6CMPB_Msk (0x80UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV6CMPA_Pos (6UL) /*!< SLV6CMPA (Bit 6) */
+#define HRPWM_SLV7_CAPACER_SLV6CMPA_Msk (0x40UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV6CLRA_Pos (5UL) /*!< SLV6CLRA (Bit 5) */
+#define HRPWM_SLV7_CAPACER_SLV6CLRA_Msk (0x20UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV6SETA_Pos (4UL) /*!< SLV6SETA (Bit 4) */
+#define HRPWM_SLV7_CAPACER_SLV6SETA_Msk (0x10UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV5CMPB_Pos (3UL) /*!< SLV5CMPB (Bit 3) */
+#define HRPWM_SLV7_CAPACER_SLV5CMPB_Msk (0x8UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV5CMPA_Pos (2UL) /*!< SLV5CMPA (Bit 2) */
+#define HRPWM_SLV7_CAPACER_SLV5CMPA_Msk (0x4UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV5CLRA_Pos (1UL) /*!< SLV5CLRA (Bit 1) */
+#define HRPWM_SLV7_CAPACER_SLV5CLRA_Msk (0x2UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPACER_SLV5SETA_Pos (0UL) /*!< SLV5SETA (Bit 0) */
+#define HRPWM_SLV7_CAPACER_SLV5SETA_Msk (0x1UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCR ========================================================= */
+#define HRPWM_SLV7_CAPBCR_SLV4CMPB_Pos (31UL) /*!< SLV4CMPB (Bit 31) */
+#define HRPWM_SLV7_CAPBCR_SLV4CMPB_Msk (0x80000000UL) /*!< SLV4CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV4CMPA_Pos (30UL) /*!< SLV4CMPA (Bit 30) */
+#define HRPWM_SLV7_CAPBCR_SLV4CMPA_Msk (0x40000000UL) /*!< SLV4CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV4CLRA_Pos (29UL) /*!< SLV4CLRA (Bit 29) */
+#define HRPWM_SLV7_CAPBCR_SLV4CLRA_Msk (0x20000000UL) /*!< SLV4CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV4SETA_Pos (28UL) /*!< SLV4SETA (Bit 28) */
+#define HRPWM_SLV7_CAPBCR_SLV4SETA_Msk (0x10000000UL) /*!< SLV4SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV3CMPB_Pos (27UL) /*!< SLV3CMPB (Bit 27) */
+#define HRPWM_SLV7_CAPBCR_SLV3CMPB_Msk (0x8000000UL) /*!< SLV3CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV3CMPA_Pos (26UL) /*!< SLV3CMPA (Bit 26) */
+#define HRPWM_SLV7_CAPBCR_SLV3CMPA_Msk (0x4000000UL) /*!< SLV3CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV3CLRA_Pos (25UL) /*!< SLV3CLRA (Bit 25) */
+#define HRPWM_SLV7_CAPBCR_SLV3CLRA_Msk (0x2000000UL) /*!< SLV3CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV3SETA_Pos (24UL) /*!< SLV3SETA (Bit 24) */
+#define HRPWM_SLV7_CAPBCR_SLV3SETA_Msk (0x1000000UL) /*!< SLV3SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV2CMPB_Pos (23UL) /*!< SLV2CMPB (Bit 23) */
+#define HRPWM_SLV7_CAPBCR_SLV2CMPB_Msk (0x800000UL) /*!< SLV2CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV2CMPA_Pos (22UL) /*!< SLV2CMPA (Bit 22) */
+#define HRPWM_SLV7_CAPBCR_SLV2CMPA_Msk (0x400000UL) /*!< SLV2CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV2CLRA_Pos (21UL) /*!< SLV2CLRA (Bit 21) */
+#define HRPWM_SLV7_CAPBCR_SLV2CLRA_Msk (0x200000UL) /*!< SLV2CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV2SETA_Pos (20UL) /*!< SLV2SETA (Bit 20) */
+#define HRPWM_SLV7_CAPBCR_SLV2SETA_Msk (0x100000UL) /*!< SLV2SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV1CMPB_Pos (19UL) /*!< SLV1CMPB (Bit 19) */
+#define HRPWM_SLV7_CAPBCR_SLV1CMPB_Msk (0x80000UL) /*!< SLV1CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV1CMPA_Pos (18UL) /*!< SLV1CMPA (Bit 18) */
+#define HRPWM_SLV7_CAPBCR_SLV1CMPA_Msk (0x40000UL) /*!< SLV1CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV1CLRA_Pos (17UL) /*!< SLV1CLRA (Bit 17) */
+#define HRPWM_SLV7_CAPBCR_SLV1CLRA_Msk (0x20000UL) /*!< SLV1CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV1SETA_Pos (16UL) /*!< SLV1SETA (Bit 16) */
+#define HRPWM_SLV7_CAPBCR_SLV1SETA_Msk (0x10000UL) /*!< SLV1SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV0CMPB_Pos (15UL) /*!< SLV0CMPB (Bit 15) */
+#define HRPWM_SLV7_CAPBCR_SLV0CMPB_Msk (0x8000UL) /*!< SLV0CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV0CMPA_Pos (14UL) /*!< SLV0CMPA (Bit 14) */
+#define HRPWM_SLV7_CAPBCR_SLV0CMPA_Msk (0x4000UL) /*!< SLV0CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV0CLRA_Pos (13UL) /*!< SLV0CLRA (Bit 13) */
+#define HRPWM_SLV7_CAPBCR_SLV0CLRA_Msk (0x2000UL) /*!< SLV0CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SLV0SETA_Pos (12UL) /*!< SLV0SETA (Bit 12) */
+#define HRPWM_SLV7_CAPBCR_SLV0SETA_Msk (0x1000UL) /*!< SLV0SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT9_Pos (11UL) /*!< EXTEVT9 (Bit 11) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT9_Msk (0x800UL) /*!< EXTEVT9 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT8_Pos (10UL) /*!< EXTEVT8 (Bit 10) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT8_Msk (0x400UL) /*!< EXTEVT8 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT7_Pos (9UL) /*!< EXTEVT7 (Bit 9) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT7_Msk (0x200UL) /*!< EXTEVT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT6_Pos (8UL) /*!< EXTEVT6 (Bit 8) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT6_Msk (0x100UL) /*!< EXTEVT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT5_Pos (7UL) /*!< EXTEVT5 (Bit 7) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT5_Msk (0x80UL) /*!< EXTEVT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT4_Pos (6UL) /*!< EXTEVT4 (Bit 6) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT4_Msk (0x40UL) /*!< EXTEVT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT3_Pos (5UL) /*!< EXTEVT3 (Bit 5) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT3_Msk (0x20UL) /*!< EXTEVT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT2_Pos (4UL) /*!< EXTEVT2 (Bit 4) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT2_Msk (0x10UL) /*!< EXTEVT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT1_Pos (3UL) /*!< EXTEVT1 (Bit 3) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT1_Msk (0x8UL) /*!< EXTEVT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT0_Pos (2UL) /*!< EXTEVT0 (Bit 2) */
+#define HRPWM_SLV7_CAPBCR_EXTEVT0_Msk (0x4UL) /*!< EXTEVT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_UPDCPT_Pos (1UL) /*!< UPDCPT (Bit 1) */
+#define HRPWM_SLV7_CAPBCR_UPDCPT_Msk (0x2UL) /*!< UPDCPT (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCR_SWCPT_Pos (0UL) /*!< SWCPT (Bit 0) */
+#define HRPWM_SLV7_CAPBCR_SWCPT_Msk (0x1UL) /*!< SWCPT (Bitfield-Mask: 0x01) */
+/* ======================================================== CAPBCER ======================================================== */
+#define HRPWM_SLV7_CAPBCER_SLV6CMPB_Pos (7UL) /*!< SLV6CMPB (Bit 7) */
+#define HRPWM_SLV7_CAPBCER_SLV6CMPB_Msk (0x80UL) /*!< SLV6CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV6CMPA_Pos (6UL) /*!< SLV6CMPA (Bit 6) */
+#define HRPWM_SLV7_CAPBCER_SLV6CMPA_Msk (0x40UL) /*!< SLV6CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV6CLRA_Pos (5UL) /*!< SLV6CLRA (Bit 5) */
+#define HRPWM_SLV7_CAPBCER_SLV6CLRA_Msk (0x20UL) /*!< SLV6CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV6SETA_Pos (4UL) /*!< SLV6SETA (Bit 4) */
+#define HRPWM_SLV7_CAPBCER_SLV6SETA_Msk (0x10UL) /*!< SLV6SETA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV5CMPB_Pos (3UL) /*!< SLV5CMPB (Bit 3) */
+#define HRPWM_SLV7_CAPBCER_SLV5CMPB_Msk (0x8UL) /*!< SLV5CMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV5CMPA_Pos (2UL) /*!< SLV5CMPA (Bit 2) */
+#define HRPWM_SLV7_CAPBCER_SLV5CMPA_Msk (0x4UL) /*!< SLV5CMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV5CLRA_Pos (1UL) /*!< SLV5CLRA (Bit 1) */
+#define HRPWM_SLV7_CAPBCER_SLV5CLRA_Msk (0x2UL) /*!< SLV5CLRA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_CAPBCER_SLV5SETA_Pos (0UL) /*!< SLV5SETA (Bit 0) */
+#define HRPWM_SLV7_CAPBCER_SLV5SETA_Msk (0x1UL) /*!< SLV5SETA (Bitfield-Mask: 0x01) */
+/* ========================================================= OUTR ========================================================== */
+#define HRPWM_SLV7_OUTR_DTEN_Pos (31UL) /*!< DTEN (Bit 31) */
+#define HRPWM_SLV7_OUTR_DTEN_Msk (0x80000000UL) /*!< DTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_DLYPRTEN_Pos (30UL) /*!< DLYPRTEN (Bit 30) */
+#define HRPWM_SLV7_OUTR_DLYPRTEN_Msk (0x40000000UL) /*!< DLYPRTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_DLYPRT_Pos (27UL) /*!< DLYPRT (Bit 27) */
+#define HRPWM_SLV7_OUTR_DLYPRT_Msk (0x38000000UL) /*!< DLYPRT (Bitfield-Mask: 0x07) */
+#define HRPWM_SLV7_OUTR_BIAR_Pos (25UL) /*!< BIAR (Bit 25) */
+#define HRPWM_SLV7_OUTR_BIAR_Msk (0x2000000UL) /*!< BIAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_DIDLB_Pos (22UL) /*!< DIDLB (Bit 22) */
+#define HRPWM_SLV7_OUTR_DIDLB_Msk (0x400000UL) /*!< DIDLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_IDLEMB_Pos (21UL) /*!< IDLEMB (Bit 21) */
+#define HRPWM_SLV7_OUTR_IDLEMB_Msk (0x200000UL) /*!< IDLEMB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_CHPB_Pos (20UL) /*!< CHPB (Bit 20) */
+#define HRPWM_SLV7_OUTR_CHPB_Msk (0x100000UL) /*!< CHPB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_IDLESB_Pos (19UL) /*!< IDLESB (Bit 19) */
+#define HRPWM_SLV7_OUTR_IDLESB_Msk (0x80000UL) /*!< IDLESB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_FAULTB_Pos (17UL) /*!< FAULTB (Bit 17) */
+#define HRPWM_SLV7_OUTR_FAULTB_Msk (0x60000UL) /*!< FAULTB (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_OUTR_POLB_Pos (16UL) /*!< POLB (Bit 16) */
+#define HRPWM_SLV7_OUTR_POLB_Msk (0x10000UL) /*!< POLB (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_DIDLA_Pos (6UL) /*!< DIDLA (Bit 6) */
+#define HRPWM_SLV7_OUTR_DIDLA_Msk (0x40UL) /*!< DIDLA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_IDLEMA_Pos (5UL) /*!< IDLEMA (Bit 5) */
+#define HRPWM_SLV7_OUTR_IDLEMA_Msk (0x20UL) /*!< IDLEMA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_CHPA_Pos (4UL) /*!< CHPA (Bit 4) */
+#define HRPWM_SLV7_OUTR_CHPA_Msk (0x10UL) /*!< CHPA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_IDLESA_Pos (3UL) /*!< IDLESA (Bit 3) */
+#define HRPWM_SLV7_OUTR_IDLESA_Msk (0x8UL) /*!< IDLESA (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_OUTR_FAULTA_Pos (1UL) /*!< FAULTA (Bit 1) */
+#define HRPWM_SLV7_OUTR_FAULTA_Msk (0x6UL) /*!< FAULTA (Bitfield-Mask: 0x03) */
+#define HRPWM_SLV7_OUTR_POLA_Pos (0UL) /*!< POLA (Bit 0) */
+#define HRPWM_SLV7_OUTR_POLA_Msk (0x1UL) /*!< POLA (Bitfield-Mask: 0x01) */
+/* ========================================================= FLTR ========================================================== */
+#define HRPWM_SLV7_FLTR_FLT7EN_Pos (7UL) /*!< FLT7EN (Bit 7) */
+#define HRPWM_SLV7_FLTR_FLT7EN_Msk (0x80UL) /*!< FLT7EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT6EN_Pos (6UL) /*!< FLT6EN (Bit 6) */
+#define HRPWM_SLV7_FLTR_FLT6EN_Msk (0x40UL) /*!< FLT6EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT5EN_Pos (5UL) /*!< FLT5EN (Bit 5) */
+#define HRPWM_SLV7_FLTR_FLT5EN_Msk (0x20UL) /*!< FLT5EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT4EN_Pos (4UL) /*!< FLT4EN (Bit 4) */
+#define HRPWM_SLV7_FLTR_FLT4EN_Msk (0x10UL) /*!< FLT4EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT3EN_Pos (3UL) /*!< FLT3EN (Bit 3) */
+#define HRPWM_SLV7_FLTR_FLT3EN_Msk (0x8UL) /*!< FLT3EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT2EN_Pos (2UL) /*!< FLT2EN (Bit 2) */
+#define HRPWM_SLV7_FLTR_FLT2EN_Msk (0x4UL) /*!< FLT2EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT1EN_Pos (1UL) /*!< FLT1EN (Bit 1) */
+#define HRPWM_SLV7_FLTR_FLT1EN_Msk (0x2UL) /*!< FLT1EN (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_FLTR_FLT0EN_Pos (0UL) /*!< FLT0EN (Bit 0) */
+#define HRPWM_SLV7_FLTR_FLT0EN_Msk (0x1UL) /*!< FLT0EN (Bitfield-Mask: 0x01) */
+/* ========================================================= DMAUR ========================================================= */
+#define HRPWM_SLV7_DMAUR_FLTR_Pos (29UL) /*!< FLTR (Bit 29) */
+#define HRPWM_SLV7_DMAUR_FLTR_Msk (0x20000000UL) /*!< FLTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_OUTR_Pos (28UL) /*!< OUTR (Bit 28) */
+#define HRPWM_SLV7_DMAUR_OUTR_Msk (0x10000000UL) /*!< OUTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPBCER_Pos (27UL) /*!< CAPBCER (Bit 27) */
+#define HRPWM_SLV7_DMAUR_CAPBCER_Msk (0x8000000UL) /*!< CAPBCER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPBCR_Pos (26UL) /*!< CAPBCR (Bit 26) */
+#define HRPWM_SLV7_DMAUR_CAPBCR_Msk (0x4000000UL) /*!< CAPBCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPACER_Pos (25UL) /*!< CAPACER (Bit 25) */
+#define HRPWM_SLV7_DMAUR_CAPACER_Msk (0x2000000UL) /*!< CAPACER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPACR_Pos (24UL) /*!< CAPACR (Bit 24) */
+#define HRPWM_SLV7_DMAUR_CAPACR_Msk (0x1000000UL) /*!< CAPACR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CHPR_Pos (23UL) /*!< CHPR (Bit 23) */
+#define HRPWM_SLV7_DMAUR_CHPR_Msk (0x800000UL) /*!< CHPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_RSTER_Pos (22UL) /*!< RSTER (Bit 22) */
+#define HRPWM_SLV7_DMAUR_RSTER_Msk (0x400000UL) /*!< RSTER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_RSTR_Pos (21UL) /*!< RSTR (Bit 21) */
+#define HRPWM_SLV7_DMAUR_RSTR_Msk (0x200000UL) /*!< RSTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_EEFR2_Pos (20UL) /*!< EEFR2 (Bit 20) */
+#define HRPWM_SLV7_DMAUR_EEFR2_Msk (0x100000UL) /*!< EEFR2 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_EEFR1_Pos (19UL) /*!< EEFR1 (Bit 19) */
+#define HRPWM_SLV7_DMAUR_EEFR1_Msk (0x80000UL) /*!< EEFR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_EEFR0_Pos (18UL) /*!< EEFR0 (Bit 18) */
+#define HRPWM_SLV7_DMAUR_EEFR0_Msk (0x40000UL) /*!< EEFR0 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CLRBR_Pos (17UL) /*!< CLRBR (Bit 17) */
+#define HRPWM_SLV7_DMAUR_CLRBR_Msk (0x20000UL) /*!< CLRBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_SETBR_Pos (16UL) /*!< SETBR (Bit 16) */
+#define HRPWM_SLV7_DMAUR_SETBR_Msk (0x10000UL) /*!< SETBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CLRAR_Pos (15UL) /*!< CLRAR (Bit 15) */
+#define HRPWM_SLV7_DMAUR_CLRAR_Msk (0x8000UL) /*!< CLRAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_SETAR_Pos (14UL) /*!< SETAR (Bit 14) */
+#define HRPWM_SLV7_DMAUR_SETAR_Msk (0x4000UL) /*!< SETAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_DTR_Pos (13UL) /*!< DTR (Bit 13) */
+#define HRPWM_SLV7_DMAUR_DTR_Msk (0x2000UL) /*!< DTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPBR_Pos (12UL) /*!< CAPBR (Bit 12) */
+#define HRPWM_SLV7_DMAUR_CAPBR_Msk (0x1000UL) /*!< CAPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CAPAR_Pos (11UL) /*!< CAPAR (Bit 11) */
+#define HRPWM_SLV7_DMAUR_CAPAR_Msk (0x800UL) /*!< CAPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CMPDR_Pos (10UL) /*!< CMPDR (Bit 10) */
+#define HRPWM_SLV7_DMAUR_CMPDR_Msk (0x400UL) /*!< CMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CMPCR_Pos (9UL) /*!< CMPCR (Bit 9) */
+#define HRPWM_SLV7_DMAUR_CMPCR_Msk (0x200UL) /*!< CMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CMPBR_Pos (8UL) /*!< CMPBR (Bit 8) */
+#define HRPWM_SLV7_DMAUR_CMPBR_Msk (0x100UL) /*!< CMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CMPAR_Pos (7UL) /*!< CMPAR (Bit 7) */
+#define HRPWM_SLV7_DMAUR_CMPAR_Msk (0x80UL) /*!< CMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_REPR_Pos (6UL) /*!< REPR (Bit 6) */
+#define HRPWM_SLV7_DMAUR_REPR_Msk (0x40UL) /*!< REPR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_PERR_Pos (5UL) /*!< PERR (Bit 5) */
+#define HRPWM_SLV7_DMAUR_PERR_Msk (0x20UL) /*!< PERR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_CNTR_Pos (4UL) /*!< CNTR (Bit 4) */
+#define HRPWM_SLV7_DMAUR_CNTR_Msk (0x10UL) /*!< CNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_PWMDIER_Pos (3UL) /*!< PWMDIER (Bit 3) */
+#define HRPWM_SLV7_DMAUR_PWMDIER_Msk (0x8UL) /*!< PWMDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_PWMISR_Pos (2UL) /*!< PWMISR (Bit 2) */
+#define HRPWM_SLV7_DMAUR_PWMISR_Msk (0x4UL) /*!< PWMISR (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_PWMCR1_Pos (1UL) /*!< PWMCR1 (Bit 1) */
+#define HRPWM_SLV7_DMAUR_PWMCR1_Msk (0x2UL) /*!< PWMCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_SLV7_DMAUR_PWMCR0_Pos (0UL) /*!< PWMCR0 (Bit 0) */
+#define HRPWM_SLV7_DMAUR_PWMCR0_Msk (0x1UL) /*!< PWMCR0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DMADR ========================================================= */
+#define HRPWM_SLV7_DMADR_DMADR_Pos (0UL) /*!< DMADR (Bit 0) */
+#define HRPWM_SLV7_DMADR_DMADR_Msk (0xffffffffUL) /*!< DMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_COM ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define HRPWM_COM_CR0_USRC3_Pos (28UL) /*!< USRC3 (Bit 28) */
+#define HRPWM_COM_CR0_USRC3_Msk (0xf0000000UL) /*!< USRC3 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR0_USRC2_Pos (24UL) /*!< USRC2 (Bit 24) */
+#define HRPWM_COM_CR0_USRC2_Msk (0xf000000UL) /*!< USRC2 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR0_USRC1_Pos (20UL) /*!< USRC1 (Bit 20) */
+#define HRPWM_COM_CR0_USRC1_Msk (0xf00000UL) /*!< USRC1 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR0_USRC0_Pos (16UL) /*!< USRC0 (Bit 16) */
+#define HRPWM_COM_CR0_USRC0_Msk (0xf0000UL) /*!< USRC0 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR0_BMUDIS_Pos (15UL) /*!< BMUDIS (Bit 15) */
+#define HRPWM_COM_CR0_BMUDIS_Msk (0x8000UL) /*!< BMUDIS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS7_Pos (8UL) /*!< UDIS7 (Bit 8) */
+#define HRPWM_COM_CR0_UDIS7_Msk (0x100UL) /*!< UDIS7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS6_Pos (7UL) /*!< UDIS6 (Bit 7) */
+#define HRPWM_COM_CR0_UDIS6_Msk (0x80UL) /*!< UDIS6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS5_Pos (6UL) /*!< UDIS5 (Bit 6) */
+#define HRPWM_COM_CR0_UDIS5_Msk (0x40UL) /*!< UDIS5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS4_Pos (5UL) /*!< UDIS4 (Bit 5) */
+#define HRPWM_COM_CR0_UDIS4_Msk (0x20UL) /*!< UDIS4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS3_Pos (4UL) /*!< UDIS3 (Bit 4) */
+#define HRPWM_COM_CR0_UDIS3_Msk (0x10UL) /*!< UDIS3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS2_Pos (3UL) /*!< UDIS2 (Bit 3) */
+#define HRPWM_COM_CR0_UDIS2_Msk (0x8UL) /*!< UDIS2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS1_Pos (2UL) /*!< UDIS1 (Bit 2) */
+#define HRPWM_COM_CR0_UDIS1_Msk (0x4UL) /*!< UDIS1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_UDIS0_Pos (1UL) /*!< UDIS0 (Bit 1) */
+#define HRPWM_COM_CR0_UDIS0_Msk (0x2UL) /*!< UDIS0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR0_MUDIS_Pos (0UL) /*!< MUDIS (Bit 0) */
+#define HRPWM_COM_CR0_MUDIS_Msk (0x1UL) /*!< MUDIS (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define HRPWM_COM_CR1_TLEN3_Pos (28UL) /*!< TLEN3 (Bit 28) */
+#define HRPWM_COM_CR1_TLEN3_Msk (0xf0000000UL) /*!< TLEN3 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR1_TLEN2_Pos (24UL) /*!< TLEN2 (Bit 24) */
+#define HRPWM_COM_CR1_TLEN2_Msk (0xf000000UL) /*!< TLEN2 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR1_TLEN1_Pos (20UL) /*!< TLEN1 (Bit 20) */
+#define HRPWM_COM_CR1_TLEN1_Msk (0xf00000UL) /*!< TLEN1 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR1_TLEN0_Pos (16UL) /*!< TLEN0 (Bit 16) */
+#define HRPWM_COM_CR1_TLEN0_Msk (0xf0000UL) /*!< TLEN0 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_CR1_SWP7_Pos (7UL) /*!< SWP7 (Bit 7) */
+#define HRPWM_COM_CR1_SWP7_Msk (0x80UL) /*!< SWP7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP6_Pos (6UL) /*!< SWP6 (Bit 6) */
+#define HRPWM_COM_CR1_SWP6_Msk (0x40UL) /*!< SWP6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP5_Pos (5UL) /*!< SWP5 (Bit 5) */
+#define HRPWM_COM_CR1_SWP5_Msk (0x20UL) /*!< SWP5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP4_Pos (4UL) /*!< SWP4 (Bit 4) */
+#define HRPWM_COM_CR1_SWP4_Msk (0x10UL) /*!< SWP4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP3_Pos (3UL) /*!< SWP3 (Bit 3) */
+#define HRPWM_COM_CR1_SWP3_Msk (0x8UL) /*!< SWP3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP2_Pos (2UL) /*!< SWP2 (Bit 2) */
+#define HRPWM_COM_CR1_SWP2_Msk (0x4UL) /*!< SWP2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP1_Pos (1UL) /*!< SWP1 (Bit 1) */
+#define HRPWM_COM_CR1_SWP1_Msk (0x2UL) /*!< SWP1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR1_SWP0_Pos (0UL) /*!< SWP0 (Bit 0) */
+#define HRPWM_COM_CR1_SWP0_Msk (0x1UL) /*!< SWP0 (Bitfield-Mask: 0x01) */
+/* ========================================================== CR2 ========================================================== */
+#define HRPWM_COM_CR2_RST7_Pos (24UL) /*!< RST7 (Bit 24) */
+#define HRPWM_COM_CR2_RST7_Msk (0x1000000UL) /*!< RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST6_Pos (23UL) /*!< RST6 (Bit 23) */
+#define HRPWM_COM_CR2_RST6_Msk (0x800000UL) /*!< RST6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST5_Pos (22UL) /*!< RST5 (Bit 22) */
+#define HRPWM_COM_CR2_RST5_Msk (0x400000UL) /*!< RST5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST4_Pos (21UL) /*!< RST4 (Bit 21) */
+#define HRPWM_COM_CR2_RST4_Msk (0x200000UL) /*!< RST4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST3_Pos (20UL) /*!< RST3 (Bit 20) */
+#define HRPWM_COM_CR2_RST3_Msk (0x100000UL) /*!< RST3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST2_Pos (19UL) /*!< RST2 (Bit 19) */
+#define HRPWM_COM_CR2_RST2_Msk (0x80000UL) /*!< RST2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST1_Pos (18UL) /*!< RST1 (Bit 18) */
+#define HRPWM_COM_CR2_RST1_Msk (0x40000UL) /*!< RST1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_RST0_Pos (17UL) /*!< RST0 (Bit 17) */
+#define HRPWM_COM_CR2_RST0_Msk (0x20000UL) /*!< RST0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_MRST_Pos (16UL) /*!< MRST (Bit 16) */
+#define HRPWM_COM_CR2_MRST_Msk (0x10000UL) /*!< MRST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU7_Pos (8UL) /*!< SWU7 (Bit 8) */
+#define HRPWM_COM_CR2_SWU7_Msk (0x100UL) /*!< SWU7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU6_Pos (7UL) /*!< SWU6 (Bit 7) */
+#define HRPWM_COM_CR2_SWU6_Msk (0x80UL) /*!< SWU6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU5_Pos (6UL) /*!< SWU5 (Bit 6) */
+#define HRPWM_COM_CR2_SWU5_Msk (0x40UL) /*!< SWU5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU4_Pos (5UL) /*!< SWU4 (Bit 5) */
+#define HRPWM_COM_CR2_SWU4_Msk (0x20UL) /*!< SWU4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU3_Pos (4UL) /*!< SWU3 (Bit 4) */
+#define HRPWM_COM_CR2_SWU3_Msk (0x10UL) /*!< SWU3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU2_Pos (3UL) /*!< SWU2 (Bit 3) */
+#define HRPWM_COM_CR2_SWU2_Msk (0x8UL) /*!< SWU2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU1_Pos (2UL) /*!< SWU1 (Bit 2) */
+#define HRPWM_COM_CR2_SWU1_Msk (0x4UL) /*!< SWU1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_SWU0_Pos (1UL) /*!< SWU0 (Bit 1) */
+#define HRPWM_COM_CR2_SWU0_Msk (0x2UL) /*!< SWU0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_CR2_MSWU_Pos (0UL) /*!< MSWU (Bit 0) */
+#define HRPWM_COM_CR2_MSWU_Msk (0x1UL) /*!< MSWU (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define HRPWM_COM_ISR_BMPER_Pos (15UL) /*!< BMPER (Bit 15) */
+#define HRPWM_COM_ISR_BMPER_Msk (0x8000UL) /*!< BMPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT7_Pos (8UL) /*!< FLT7 (Bit 8) */
+#define HRPWM_COM_ISR_FLT7_Msk (0x100UL) /*!< FLT7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT6_Pos (7UL) /*!< FLT6 (Bit 7) */
+#define HRPWM_COM_ISR_FLT6_Msk (0x80UL) /*!< FLT6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT5_Pos (6UL) /*!< FLT5 (Bit 6) */
+#define HRPWM_COM_ISR_FLT5_Msk (0x40UL) /*!< FLT5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT4_Pos (5UL) /*!< FLT4 (Bit 5) */
+#define HRPWM_COM_ISR_FLT4_Msk (0x20UL) /*!< FLT4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT3_Pos (4UL) /*!< FLT3 (Bit 4) */
+#define HRPWM_COM_ISR_FLT3_Msk (0x10UL) /*!< FLT3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT2_Pos (3UL) /*!< FLT2 (Bit 3) */
+#define HRPWM_COM_ISR_FLT2_Msk (0x8UL) /*!< FLT2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT1_Pos (2UL) /*!< FLT1 (Bit 2) */
+#define HRPWM_COM_ISR_FLT1_Msk (0x4UL) /*!< FLT1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_FLT0_Pos (1UL) /*!< FLT0 (Bit 1) */
+#define HRPWM_COM_ISR_FLT0_Msk (0x2UL) /*!< FLT0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ISR_SYSFLT_Pos (0UL) /*!< SYSFLT (Bit 0) */
+#define HRPWM_COM_ISR_SYSFLT_Msk (0x1UL) /*!< SYSFLT (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define HRPWM_COM_IER_BMPERIE_Pos (15UL) /*!< BMPERIE (Bit 15) */
+#define HRPWM_COM_IER_BMPERIE_Msk (0x8000UL) /*!< BMPERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT7IE_Pos (8UL) /*!< FLT7IE (Bit 8) */
+#define HRPWM_COM_IER_FLT7IE_Msk (0x100UL) /*!< FLT7IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT6IE_Pos (7UL) /*!< FLT6IE (Bit 7) */
+#define HRPWM_COM_IER_FLT6IE_Msk (0x80UL) /*!< FLT6IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT5IE_Pos (6UL) /*!< FLT5IE (Bit 6) */
+#define HRPWM_COM_IER_FLT5IE_Msk (0x40UL) /*!< FLT5IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT4IE_Pos (5UL) /*!< FLT4IE (Bit 5) */
+#define HRPWM_COM_IER_FLT4IE_Msk (0x20UL) /*!< FLT4IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT3IE_Pos (4UL) /*!< FLT3IE (Bit 4) */
+#define HRPWM_COM_IER_FLT3IE_Msk (0x10UL) /*!< FLT3IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT2IE_Pos (3UL) /*!< FLT2IE (Bit 3) */
+#define HRPWM_COM_IER_FLT2IE_Msk (0x8UL) /*!< FLT2IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT1IE_Pos (2UL) /*!< FLT1IE (Bit 2) */
+#define HRPWM_COM_IER_FLT1IE_Msk (0x4UL) /*!< FLT1IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_FLT0IE_Pos (1UL) /*!< FLT0IE (Bit 1) */
+#define HRPWM_COM_IER_FLT0IE_Msk (0x2UL) /*!< FLT0IE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_IER_SYSFLTIE_Pos (0UL) /*!< SYSFLTIE (Bit 0) */
+#define HRPWM_COM_IER_SYSFLTIE_Msk (0x1UL) /*!< SYSFLTIE (Bitfield-Mask: 0x01) */
+/* ========================================================= OENR ========================================================== */
+#define HRPWM_COM_OENR_OEN7B_Pos (15UL) /*!< OEN7B (Bit 15) */
+#define HRPWM_COM_OENR_OEN7B_Msk (0x8000UL) /*!< OEN7B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN7A_Pos (14UL) /*!< OEN7A (Bit 14) */
+#define HRPWM_COM_OENR_OEN7A_Msk (0x4000UL) /*!< OEN7A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN6B_Pos (13UL) /*!< OEN6B (Bit 13) */
+#define HRPWM_COM_OENR_OEN6B_Msk (0x2000UL) /*!< OEN6B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN6A_Pos (12UL) /*!< OEN6A (Bit 12) */
+#define HRPWM_COM_OENR_OEN6A_Msk (0x1000UL) /*!< OEN6A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN5B_Pos (11UL) /*!< OEN5B (Bit 11) */
+#define HRPWM_COM_OENR_OEN5B_Msk (0x800UL) /*!< OEN5B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN5A_Pos (10UL) /*!< OEN5A (Bit 10) */
+#define HRPWM_COM_OENR_OEN5A_Msk (0x400UL) /*!< OEN5A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN4B_Pos (9UL) /*!< OEN4B (Bit 9) */
+#define HRPWM_COM_OENR_OEN4B_Msk (0x200UL) /*!< OEN4B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN4A_Pos (8UL) /*!< OEN4A (Bit 8) */
+#define HRPWM_COM_OENR_OEN4A_Msk (0x100UL) /*!< OEN4A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN3B_Pos (7UL) /*!< OEN3B (Bit 7) */
+#define HRPWM_COM_OENR_OEN3B_Msk (0x80UL) /*!< OEN3B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN3A_Pos (6UL) /*!< OEN3A (Bit 6) */
+#define HRPWM_COM_OENR_OEN3A_Msk (0x40UL) /*!< OEN3A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN2B_Pos (5UL) /*!< OEN2B (Bit 5) */
+#define HRPWM_COM_OENR_OEN2B_Msk (0x20UL) /*!< OEN2B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN2A_Pos (4UL) /*!< OEN2A (Bit 4) */
+#define HRPWM_COM_OENR_OEN2A_Msk (0x10UL) /*!< OEN2A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN1B_Pos (3UL) /*!< OEN1B (Bit 3) */
+#define HRPWM_COM_OENR_OEN1B_Msk (0x8UL) /*!< OEN1B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN1A_Pos (2UL) /*!< OEN1A (Bit 2) */
+#define HRPWM_COM_OENR_OEN1A_Msk (0x4UL) /*!< OEN1A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN0B_Pos (1UL) /*!< OEN0B (Bit 1) */
+#define HRPWM_COM_OENR_OEN0B_Msk (0x2UL) /*!< OEN0B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_OENR_OEN0A_Pos (0UL) /*!< OEN0A (Bit 0) */
+#define HRPWM_COM_OENR_OEN0A_Msk (0x1UL) /*!< OEN0A (Bitfield-Mask: 0x01) */
+/* ========================================================= ODISR ========================================================= */
+#define HRPWM_COM_ODISR_ODIS7B_Pos (15UL) /*!< ODIS7B (Bit 15) */
+#define HRPWM_COM_ODISR_ODIS7B_Msk (0x8000UL) /*!< ODIS7B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS7A_Pos (14UL) /*!< ODIS7A (Bit 14) */
+#define HRPWM_COM_ODISR_ODIS7A_Msk (0x4000UL) /*!< ODIS7A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS6B_Pos (13UL) /*!< ODIS6B (Bit 13) */
+#define HRPWM_COM_ODISR_ODIS6B_Msk (0x2000UL) /*!< ODIS6B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS6A_Pos (12UL) /*!< ODIS6A (Bit 12) */
+#define HRPWM_COM_ODISR_ODIS6A_Msk (0x1000UL) /*!< ODIS6A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS5B_Pos (11UL) /*!< ODIS5B (Bit 11) */
+#define HRPWM_COM_ODISR_ODIS5B_Msk (0x800UL) /*!< ODIS5B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS5A_Pos (10UL) /*!< ODIS5A (Bit 10) */
+#define HRPWM_COM_ODISR_ODIS5A_Msk (0x400UL) /*!< ODIS5A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS4B_Pos (9UL) /*!< ODIS4B (Bit 9) */
+#define HRPWM_COM_ODISR_ODIS4B_Msk (0x200UL) /*!< ODIS4B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS4A_Pos (8UL) /*!< ODIS4A (Bit 8) */
+#define HRPWM_COM_ODISR_ODIS4A_Msk (0x100UL) /*!< ODIS4A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS3B_Pos (7UL) /*!< ODIS3B (Bit 7) */
+#define HRPWM_COM_ODISR_ODIS3B_Msk (0x80UL) /*!< ODIS3B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS3A_Pos (6UL) /*!< ODIS3A (Bit 6) */
+#define HRPWM_COM_ODISR_ODIS3A_Msk (0x40UL) /*!< ODIS3A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS2B_Pos (5UL) /*!< ODIS2B (Bit 5) */
+#define HRPWM_COM_ODISR_ODIS2B_Msk (0x20UL) /*!< ODIS2B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS2A_Pos (4UL) /*!< ODIS2A (Bit 4) */
+#define HRPWM_COM_ODISR_ODIS2A_Msk (0x10UL) /*!< ODIS2A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS1B_Pos (3UL) /*!< ODIS1B (Bit 3) */
+#define HRPWM_COM_ODISR_ODIS1B_Msk (0x8UL) /*!< ODIS1B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS1A_Pos (2UL) /*!< ODIS1A (Bit 2) */
+#define HRPWM_COM_ODISR_ODIS1A_Msk (0x4UL) /*!< ODIS1A (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS0B_Pos (1UL) /*!< ODIS0B (Bit 1) */
+#define HRPWM_COM_ODISR_ODIS0B_Msk (0x2UL) /*!< ODIS0B (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ODISR_ODIS0A_Pos (0UL) /*!< ODIS0A (Bit 0) */
+#define HRPWM_COM_ODISR_ODIS0A_Msk (0x1UL) /*!< ODIS0A (Bitfield-Mask: 0x01) */
+/* ========================================================= EECR0 ========================================================= */
+#define HRPWM_COM_EECR0_EE4FAST_Pos (29UL) /*!< EE4FAST (Bit 29) */
+#define HRPWM_COM_EECR0_EE4FAST_Msk (0x20000000UL) /*!< EE4FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE4SNS_Pos (27UL) /*!< EE4SNS (Bit 27) */
+#define HRPWM_COM_EECR0_EE4SNS_Msk (0x18000000UL) /*!< EE4SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE4POL_Pos (26UL) /*!< EE4POL (Bit 26) */
+#define HRPWM_COM_EECR0_EE4POL_Msk (0x4000000UL) /*!< EE4POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE4SRC_Pos (24UL) /*!< EE4SRC (Bit 24) */
+#define HRPWM_COM_EECR0_EE4SRC_Msk (0x3000000UL) /*!< EE4SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE3FAST_Pos (23UL) /*!< EE3FAST (Bit 23) */
+#define HRPWM_COM_EECR0_EE3FAST_Msk (0x800000UL) /*!< EE3FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE3SNS_Pos (21UL) /*!< EE3SNS (Bit 21) */
+#define HRPWM_COM_EECR0_EE3SNS_Msk (0x600000UL) /*!< EE3SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE3POL_Pos (20UL) /*!< EE3POL (Bit 20) */
+#define HRPWM_COM_EECR0_EE3POL_Msk (0x100000UL) /*!< EE3POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE3SRC_Pos (18UL) /*!< EE3SRC (Bit 18) */
+#define HRPWM_COM_EECR0_EE3SRC_Msk (0xc0000UL) /*!< EE3SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE2FAST_Pos (17UL) /*!< EE2FAST (Bit 17) */
+#define HRPWM_COM_EECR0_EE2FAST_Msk (0x20000UL) /*!< EE2FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE2SNS_Pos (15UL) /*!< EE2SNS (Bit 15) */
+#define HRPWM_COM_EECR0_EE2SNS_Msk (0x18000UL) /*!< EE2SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE2POL_Pos (14UL) /*!< EE2POL (Bit 14) */
+#define HRPWM_COM_EECR0_EE2POL_Msk (0x4000UL) /*!< EE2POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE2SRC_Pos (12UL) /*!< EE2SRC (Bit 12) */
+#define HRPWM_COM_EECR0_EE2SRC_Msk (0x3000UL) /*!< EE2SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE1FAST_Pos (11UL) /*!< EE1FAST (Bit 11) */
+#define HRPWM_COM_EECR0_EE1FAST_Msk (0x800UL) /*!< EE1FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE1SNS_Pos (9UL) /*!< EE1SNS (Bit 9) */
+#define HRPWM_COM_EECR0_EE1SNS_Msk (0x600UL) /*!< EE1SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE1POL_Pos (8UL) /*!< EE1POL (Bit 8) */
+#define HRPWM_COM_EECR0_EE1POL_Msk (0x100UL) /*!< EE1POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE1SRC_Pos (6UL) /*!< EE1SRC (Bit 6) */
+#define HRPWM_COM_EECR0_EE1SRC_Msk (0xc0UL) /*!< EE1SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE0FAST_Pos (5UL) /*!< EE0FAST (Bit 5) */
+#define HRPWM_COM_EECR0_EE0FAST_Msk (0x20UL) /*!< EE0FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE0SNS_Pos (3UL) /*!< EE0SNS (Bit 3) */
+#define HRPWM_COM_EECR0_EE0SNS_Msk (0x18UL) /*!< EE0SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR0_EE0POL_Pos (2UL) /*!< EE0POL (Bit 2) */
+#define HRPWM_COM_EECR0_EE0POL_Msk (0x4UL) /*!< EE0POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR0_EE0SRC_Pos (0UL) /*!< EE0SRC (Bit 0) */
+#define HRPWM_COM_EECR0_EE0SRC_Msk (0x3UL) /*!< EE0SRC (Bitfield-Mask: 0x03) */
+/* ========================================================= EECR1 ========================================================= */
+#define HRPWM_COM_EECR1_EE9FAST_Pos (29UL) /*!< EE9FAST (Bit 29) */
+#define HRPWM_COM_EECR1_EE9FAST_Msk (0x20000000UL) /*!< EE9FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE9SNS_Pos (27UL) /*!< EE9SNS (Bit 27) */
+#define HRPWM_COM_EECR1_EE9SNS_Msk (0x18000000UL) /*!< EE9SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE9POL_Pos (26UL) /*!< EE9POL (Bit 26) */
+#define HRPWM_COM_EECR1_EE9POL_Msk (0x4000000UL) /*!< EE9POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE9SRC_Pos (24UL) /*!< EE9SRC (Bit 24) */
+#define HRPWM_COM_EECR1_EE9SRC_Msk (0x3000000UL) /*!< EE9SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE8FAST_Pos (23UL) /*!< EE8FAST (Bit 23) */
+#define HRPWM_COM_EECR1_EE8FAST_Msk (0x800000UL) /*!< EE8FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE8SNS_Pos (21UL) /*!< EE8SNS (Bit 21) */
+#define HRPWM_COM_EECR1_EE8SNS_Msk (0x600000UL) /*!< EE8SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE8POL_Pos (20UL) /*!< EE8POL (Bit 20) */
+#define HRPWM_COM_EECR1_EE8POL_Msk (0x100000UL) /*!< EE8POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE8SRC_Pos (18UL) /*!< EE8SRC (Bit 18) */
+#define HRPWM_COM_EECR1_EE8SRC_Msk (0xc0000UL) /*!< EE8SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE7FAST_Pos (17UL) /*!< EE7FAST (Bit 17) */
+#define HRPWM_COM_EECR1_EE7FAST_Msk (0x20000UL) /*!< EE7FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE7SNS_Pos (15UL) /*!< EE7SNS (Bit 15) */
+#define HRPWM_COM_EECR1_EE7SNS_Msk (0x18000UL) /*!< EE7SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE7POL_Pos (14UL) /*!< EE7POL (Bit 14) */
+#define HRPWM_COM_EECR1_EE7POL_Msk (0x4000UL) /*!< EE7POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE7SRC_Pos (12UL) /*!< EE7SRC (Bit 12) */
+#define HRPWM_COM_EECR1_EE7SRC_Msk (0x3000UL) /*!< EE7SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE6FAST_Pos (11UL) /*!< EE6FAST (Bit 11) */
+#define HRPWM_COM_EECR1_EE6FAST_Msk (0x800UL) /*!< EE6FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE6SNS_Pos (9UL) /*!< EE6SNS (Bit 9) */
+#define HRPWM_COM_EECR1_EE6SNS_Msk (0x600UL) /*!< EE6SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE6POL_Pos (8UL) /*!< EE6POL (Bit 8) */
+#define HRPWM_COM_EECR1_EE6POL_Msk (0x100UL) /*!< EE6POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE6SRC_Pos (6UL) /*!< EE6SRC (Bit 6) */
+#define HRPWM_COM_EECR1_EE6SRC_Msk (0xc0UL) /*!< EE6SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE5FAST_Pos (5UL) /*!< EE5FAST (Bit 5) */
+#define HRPWM_COM_EECR1_EE5FAST_Msk (0x20UL) /*!< EE5FAST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE5SNS_Pos (3UL) /*!< EE5SNS (Bit 3) */
+#define HRPWM_COM_EECR1_EE5SNS_Msk (0x18UL) /*!< EE5SNS (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR1_EE5POL_Pos (2UL) /*!< EE5POL (Bit 2) */
+#define HRPWM_COM_EECR1_EE5POL_Msk (0x4UL) /*!< EE5POL (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_EECR1_EE5SRC_Pos (0UL) /*!< EE5SRC (Bit 0) */
+#define HRPWM_COM_EECR1_EE5SRC_Msk (0x3UL) /*!< EE5SRC (Bitfield-Mask: 0x03) */
+/* ========================================================= EECR2 ========================================================= */
+#define HRPWM_COM_EECR2_EEVSD_Pos (30UL) /*!< EEVSD (Bit 30) */
+#define HRPWM_COM_EECR2_EEVSD_Msk (0xc0000000UL) /*!< EEVSD (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECR2_EE4F_Pos (16UL) /*!< EE4F (Bit 16) */
+#define HRPWM_COM_EECR2_EE4F_Msk (0xf0000UL) /*!< EE4F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR2_EE3F_Pos (12UL) /*!< EE3F (Bit 12) */
+#define HRPWM_COM_EECR2_EE3F_Msk (0xf000UL) /*!< EE3F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR2_EE2F_Pos (8UL) /*!< EE2F (Bit 8) */
+#define HRPWM_COM_EECR2_EE2F_Msk (0xf00UL) /*!< EE2F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR2_EE1F_Pos (4UL) /*!< EE1F (Bit 4) */
+#define HRPWM_COM_EECR2_EE1F_Msk (0xf0UL) /*!< EE1F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR2_EE0F_Pos (0UL) /*!< EE0F (Bit 0) */
+#define HRPWM_COM_EECR2_EE0F_Msk (0xfUL) /*!< EE0F (Bitfield-Mask: 0x0f) */
+/* ========================================================= EECR3 ========================================================= */
+#define HRPWM_COM_EECR3_EE9F_Pos (16UL) /*!< EE9F (Bit 16) */
+#define HRPWM_COM_EECR3_EE9F_Msk (0xf0000UL) /*!< EE9F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR3_EE8F_Pos (12UL) /*!< EE8F (Bit 12) */
+#define HRPWM_COM_EECR3_EE8F_Msk (0xf000UL) /*!< EE8F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR3_EE7F_Pos (8UL) /*!< EE7F (Bit 8) */
+#define HRPWM_COM_EECR3_EE7F_Msk (0xf00UL) /*!< EE7F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR3_EE6F_Pos (4UL) /*!< EE6F (Bit 4) */
+#define HRPWM_COM_EECR3_EE6F_Msk (0xf0UL) /*!< EE6F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_EECR3_EE5F_Pos (0UL) /*!< EE5F (Bit 0) */
+#define HRPWM_COM_EECR3_EE5F_Msk (0xfUL) /*!< EE5F (Bitfield-Mask: 0x0f) */
+/* ========================================================= ADC0R ========================================================= */
+#define HRPWM_COM_ADC0R_ADC0RST5_Pos (31UL) /*!< ADC0RST5 (Bit 31) */
+#define HRPWM_COM_ADC0R_ADC0RST5_Msk (0x80000000UL) /*!< ADC0RST5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER5_Pos (30UL) /*!< ADC0PER5 (Bit 30) */
+#define HRPWM_COM_ADC0R_ADC0PER5_Msk (0x40000000UL) /*!< ADC0PER5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD5_Pos (29UL) /*!< ADC0CMPD5 (Bit 29) */
+#define HRPWM_COM_ADC0R_ADC0CMPD5_Msk (0x20000000UL) /*!< ADC0CMPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC5_Pos (28UL) /*!< ADC0CMPC5 (Bit 28) */
+#define HRPWM_COM_ADC0R_ADC0CMPC5_Msk (0x10000000UL) /*!< ADC0CMPC5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPB5_Pos (27UL) /*!< ADC0CMPB5 (Bit 27) */
+#define HRPWM_COM_ADC0R_ADC0CMPB5_Msk (0x8000000UL) /*!< ADC0CMPB5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER4_Pos (26UL) /*!< ADC0PER4 (Bit 26) */
+#define HRPWM_COM_ADC0R_ADC0PER4_Msk (0x4000000UL) /*!< ADC0PER4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD4_Pos (25UL) /*!< ADC0CMPD4 (Bit 25) */
+#define HRPWM_COM_ADC0R_ADC0CMPD4_Msk (0x2000000UL) /*!< ADC0CMPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC4_Pos (24UL) /*!< ADC0CMPC4 (Bit 24) */
+#define HRPWM_COM_ADC0R_ADC0CMPC4_Msk (0x1000000UL) /*!< ADC0CMPC4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER3_Pos (23UL) /*!< ADC0PER3 (Bit 23) */
+#define HRPWM_COM_ADC0R_ADC0PER3_Msk (0x800000UL) /*!< ADC0PER3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD3_Pos (22UL) /*!< ADC0CMPD3 (Bit 22) */
+#define HRPWM_COM_ADC0R_ADC0CMPD3_Msk (0x400000UL) /*!< ADC0CMPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC3_Pos (21UL) /*!< ADC0CMPC3 (Bit 21) */
+#define HRPWM_COM_ADC0R_ADC0CMPC3_Msk (0x200000UL) /*!< ADC0CMPC3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER2_Pos (20UL) /*!< ADC0PER2 (Bit 20) */
+#define HRPWM_COM_ADC0R_ADC0PER2_Msk (0x100000UL) /*!< ADC0PER2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD2_Pos (19UL) /*!< ADC0CMPD2 (Bit 19) */
+#define HRPWM_COM_ADC0R_ADC0CMPD2_Msk (0x80000UL) /*!< ADC0CMPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC2_Pos (18UL) /*!< ADC0CMPC2 (Bit 18) */
+#define HRPWM_COM_ADC0R_ADC0CMPC2_Msk (0x40000UL) /*!< ADC0CMPC2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0RST1_Pos (17UL) /*!< ADC0RST1 (Bit 17) */
+#define HRPWM_COM_ADC0R_ADC0RST1_Msk (0x20000UL) /*!< ADC0RST1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER1_Pos (16UL) /*!< ADC0PER1 (Bit 16) */
+#define HRPWM_COM_ADC0R_ADC0PER1_Msk (0x10000UL) /*!< ADC0PER1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD1_Pos (15UL) /*!< ADC0CMPD1 (Bit 15) */
+#define HRPWM_COM_ADC0R_ADC0CMPD1_Msk (0x8000UL) /*!< ADC0CMPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC1_Pos (14UL) /*!< ADC0CMPC1 (Bit 14) */
+#define HRPWM_COM_ADC0R_ADC0CMPC1_Msk (0x4000UL) /*!< ADC0CMPC1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0RST0_Pos (13UL) /*!< ADC0RST0 (Bit 13) */
+#define HRPWM_COM_ADC0R_ADC0RST0_Msk (0x2000UL) /*!< ADC0RST0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0PER0_Pos (12UL) /*!< ADC0PER0 (Bit 12) */
+#define HRPWM_COM_ADC0R_ADC0PER0_Msk (0x1000UL) /*!< ADC0PER0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPD0_Pos (11UL) /*!< ADC0CMPD0 (Bit 11) */
+#define HRPWM_COM_ADC0R_ADC0CMPD0_Msk (0x800UL) /*!< ADC0CMPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0CMPC0_Pos (10UL) /*!< ADC0CMPC0 (Bit 10) */
+#define HRPWM_COM_ADC0R_ADC0CMPC0_Msk (0x400UL) /*!< ADC0CMPC0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0EEV4_Pos (9UL) /*!< ADC0EEV4 (Bit 9) */
+#define HRPWM_COM_ADC0R_ADC0EEV4_Msk (0x200UL) /*!< ADC0EEV4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0EEV3_Pos (8UL) /*!< ADC0EEV3 (Bit 8) */
+#define HRPWM_COM_ADC0R_ADC0EEV3_Msk (0x100UL) /*!< ADC0EEV3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0EEV2_Pos (7UL) /*!< ADC0EEV2 (Bit 7) */
+#define HRPWM_COM_ADC0R_ADC0EEV2_Msk (0x80UL) /*!< ADC0EEV2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0EEV1_Pos (6UL) /*!< ADC0EEV1 (Bit 6) */
+#define HRPWM_COM_ADC0R_ADC0EEV1_Msk (0x40UL) /*!< ADC0EEV1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0EEV0_Pos (5UL) /*!< ADC0EEV0 (Bit 5) */
+#define HRPWM_COM_ADC0R_ADC0EEV0_Msk (0x20UL) /*!< ADC0EEV0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0MPER_Pos (4UL) /*!< ADC0MPER (Bit 4) */
+#define HRPWM_COM_ADC0R_ADC0MPER_Msk (0x10UL) /*!< ADC0MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0MCMPD_Pos (3UL) /*!< ADC0MCMPD (Bit 3) */
+#define HRPWM_COM_ADC0R_ADC0MCMPD_Msk (0x8UL) /*!< ADC0MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0MCMPC_Pos (2UL) /*!< ADC0MCMPC (Bit 2) */
+#define HRPWM_COM_ADC0R_ADC0MCMPC_Msk (0x4UL) /*!< ADC0MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0MCMPB_Pos (1UL) /*!< ADC0MCMPB (Bit 1) */
+#define HRPWM_COM_ADC0R_ADC0MCMPB_Msk (0x2UL) /*!< ADC0MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0R_ADC0MCMPA_Pos (0UL) /*!< ADC0MCMPA (Bit 0) */
+#define HRPWM_COM_ADC0R_ADC0MCMPA_Msk (0x1UL) /*!< ADC0MCMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== ADC0ER ========================================================= */
+#define HRPWM_COM_ADC0ER_ADC0RST7_Pos (7UL) /*!< ADC0RST7 (Bit 7) */
+#define HRPWM_COM_ADC0ER_ADC0RST7_Msk (0x80UL) /*!< ADC0RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0PER7_Pos (6UL) /*!< ADC0PER7 (Bit 6) */
+#define HRPWM_COM_ADC0ER_ADC0PER7_Msk (0x40UL) /*!< ADC0PER7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0CMPD7_Pos (5UL) /*!< ADC0CMPD7 (Bit 5) */
+#define HRPWM_COM_ADC0ER_ADC0CMPD7_Msk (0x20UL) /*!< ADC0CMPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0CMPC7_Pos (4UL) /*!< ADC0CMPC7 (Bit 4) */
+#define HRPWM_COM_ADC0ER_ADC0CMPC7_Msk (0x10UL) /*!< ADC0CMPC7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0RST6_Pos (3UL) /*!< ADC0RST6 (Bit 3) */
+#define HRPWM_COM_ADC0ER_ADC0RST6_Msk (0x8UL) /*!< ADC0RST6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0PER6_Pos (2UL) /*!< ADC0PER6 (Bit 2) */
+#define HRPWM_COM_ADC0ER_ADC0PER6_Msk (0x4UL) /*!< ADC0PER6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0CMPD6_Pos (1UL) /*!< ADC0CMPD6 (Bit 1) */
+#define HRPWM_COM_ADC0ER_ADC0CMPD6_Msk (0x2UL) /*!< ADC0CMPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC0ER_ADC0CMPC6_Pos (0UL) /*!< ADC0CMPC6 (Bit 0) */
+#define HRPWM_COM_ADC0ER_ADC0CMPC6_Msk (0x1UL) /*!< ADC0CMPC6 (Bitfield-Mask: 0x01) */
+/* ========================================================= ADC1R ========================================================= */
+#define HRPWM_COM_ADC1R_ADC1PER5_Pos (31UL) /*!< ADC1PER5 (Bit 31) */
+#define HRPWM_COM_ADC1R_ADC1PER5_Msk (0x80000000UL) /*!< ADC1PER5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD5_Pos (30UL) /*!< ADC1CMPD5 (Bit 30) */
+#define HRPWM_COM_ADC1R_ADC1CMPD5_Msk (0x40000000UL) /*!< ADC1CMPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPC5_Pos (29UL) /*!< ADC1CMPC5 (Bit 29) */
+#define HRPWM_COM_ADC1R_ADC1CMPC5_Msk (0x20000000UL) /*!< ADC1CMPC5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB5_Pos (28UL) /*!< ADC1CMPB5 (Bit 28) */
+#define HRPWM_COM_ADC1R_ADC1CMPB5_Msk (0x10000000UL) /*!< ADC1CMPB5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1RST4_Pos (27UL) /*!< ADC1RST4 (Bit 27) */
+#define HRPWM_COM_ADC1R_ADC1RST4_Msk (0x8000000UL) /*!< ADC1RST4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD4_Pos (26UL) /*!< ADC1CMPD4 (Bit 26) */
+#define HRPWM_COM_ADC1R_ADC1CMPD4_Msk (0x4000000UL) /*!< ADC1CMPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPC4_Pos (25UL) /*!< ADC1CMPC4 (Bit 25) */
+#define HRPWM_COM_ADC1R_ADC1CMPC4_Msk (0x2000000UL) /*!< ADC1CMPC4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB4_Pos (24UL) /*!< ADC1CMPB4 (Bit 24) */
+#define HRPWM_COM_ADC1R_ADC1CMPB4_Msk (0x1000000UL) /*!< ADC1CMPB4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1RST3_Pos (23UL) /*!< ADC1RST3 (Bit 23) */
+#define HRPWM_COM_ADC1R_ADC1RST3_Msk (0x800000UL) /*!< ADC1RST3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1PER3_Pos (22UL) /*!< ADC1PER3 (Bit 22) */
+#define HRPWM_COM_ADC1R_ADC1PER3_Msk (0x400000UL) /*!< ADC1PER3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD3_Pos (21UL) /*!< ADC1CMPD3 (Bit 21) */
+#define HRPWM_COM_ADC1R_ADC1CMPD3_Msk (0x200000UL) /*!< ADC1CMPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB3_Pos (20UL) /*!< ADC1CMPB3 (Bit 20) */
+#define HRPWM_COM_ADC1R_ADC1CMPB3_Msk (0x100000UL) /*!< ADC1CMPB3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1RST2_Pos (19UL) /*!< ADC1RST2 (Bit 19) */
+#define HRPWM_COM_ADC1R_ADC1RST2_Msk (0x80000UL) /*!< ADC1RST2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1PER2_Pos (18UL) /*!< ADC1PER2 (Bit 18) */
+#define HRPWM_COM_ADC1R_ADC1PER2_Msk (0x40000UL) /*!< ADC1PER2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD2_Pos (17UL) /*!< ADC1CMPD2 (Bit 17) */
+#define HRPWM_COM_ADC1R_ADC1CMPD2_Msk (0x20000UL) /*!< ADC1CMPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB2_Pos (16UL) /*!< ADC1CMPB2 (Bit 16) */
+#define HRPWM_COM_ADC1R_ADC1CMPB2_Msk (0x10000UL) /*!< ADC1CMPB2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1PER1_Pos (15UL) /*!< ADC1PER1 (Bit 15) */
+#define HRPWM_COM_ADC1R_ADC1PER1_Msk (0x8000UL) /*!< ADC1PER1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD1_Pos (14UL) /*!< ADC1CMPD1 (Bit 14) */
+#define HRPWM_COM_ADC1R_ADC1CMPD1_Msk (0x4000UL) /*!< ADC1CMPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB1_Pos (13UL) /*!< ADC1CMPB1 (Bit 13) */
+#define HRPWM_COM_ADC1R_ADC1CMPB1_Msk (0x2000UL) /*!< ADC1CMPB1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1PER0_Pos (12UL) /*!< ADC1PER0 (Bit 12) */
+#define HRPWM_COM_ADC1R_ADC1PER0_Msk (0x1000UL) /*!< ADC1PER0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPD0_Pos (11UL) /*!< ADC1CMPD0 (Bit 11) */
+#define HRPWM_COM_ADC1R_ADC1CMPD0_Msk (0x800UL) /*!< ADC1CMPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1CMPB0_Pos (10UL) /*!< ADC1CMPB0 (Bit 10) */
+#define HRPWM_COM_ADC1R_ADC1CMPB0_Msk (0x400UL) /*!< ADC1CMPB0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1EEV9_Pos (9UL) /*!< ADC1EEV9 (Bit 9) */
+#define HRPWM_COM_ADC1R_ADC1EEV9_Msk (0x200UL) /*!< ADC1EEV9 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1EEV8_Pos (8UL) /*!< ADC1EEV8 (Bit 8) */
+#define HRPWM_COM_ADC1R_ADC1EEV8_Msk (0x100UL) /*!< ADC1EEV8 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1EEV7_Pos (7UL) /*!< ADC1EEV7 (Bit 7) */
+#define HRPWM_COM_ADC1R_ADC1EEV7_Msk (0x80UL) /*!< ADC1EEV7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1EEV6_Pos (6UL) /*!< ADC1EEV6 (Bit 6) */
+#define HRPWM_COM_ADC1R_ADC1EEV6_Msk (0x40UL) /*!< ADC1EEV6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1EEV5_Pos (5UL) /*!< ADC1EEV5 (Bit 5) */
+#define HRPWM_COM_ADC1R_ADC1EEV5_Msk (0x20UL) /*!< ADC1EEV5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1MPER_Pos (4UL) /*!< ADC1MPER (Bit 4) */
+#define HRPWM_COM_ADC1R_ADC1MPER_Msk (0x10UL) /*!< ADC1MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1MCMPD_Pos (3UL) /*!< ADC1MCMPD (Bit 3) */
+#define HRPWM_COM_ADC1R_ADC1MCMPD_Msk (0x8UL) /*!< ADC1MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1MCMPC_Pos (2UL) /*!< ADC1MCMPC (Bit 2) */
+#define HRPWM_COM_ADC1R_ADC1MCMPC_Msk (0x4UL) /*!< ADC1MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1MCMPB_Pos (1UL) /*!< ADC1MCMPB (Bit 1) */
+#define HRPWM_COM_ADC1R_ADC1MCMPB_Msk (0x2UL) /*!< ADC1MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1R_ADC1MCMPA_Pos (0UL) /*!< ADC1MCMPA (Bit 0) */
+#define HRPWM_COM_ADC1R_ADC1MCMPA_Msk (0x1UL) /*!< ADC1MCMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== ADC1ER ========================================================= */
+#define HRPWM_COM_ADC1ER_ADC1RST7_Pos (7UL) /*!< ADC1RST7 (Bit 7) */
+#define HRPWM_COM_ADC1ER_ADC1RST7_Msk (0x80UL) /*!< ADC1RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1PER7_Pos (6UL) /*!< ADC1PER7 (Bit 6) */
+#define HRPWM_COM_ADC1ER_ADC1PER7_Msk (0x40UL) /*!< ADC1PER7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1CMPD7_Pos (5UL) /*!< ADC1CMPD7 (Bit 5) */
+#define HRPWM_COM_ADC1ER_ADC1CMPD7_Msk (0x20UL) /*!< ADC1CMPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1CMPB7_Pos (4UL) /*!< ADC1CMPB7 (Bit 4) */
+#define HRPWM_COM_ADC1ER_ADC1CMPB7_Msk (0x10UL) /*!< ADC1CMPB7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1RST6_Pos (3UL) /*!< ADC1RST6 (Bit 3) */
+#define HRPWM_COM_ADC1ER_ADC1RST6_Msk (0x8UL) /*!< ADC1RST6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1PER6_Pos (2UL) /*!< ADC1PER6 (Bit 2) */
+#define HRPWM_COM_ADC1ER_ADC1PER6_Msk (0x4UL) /*!< ADC1PER6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1CMPD6_Pos (1UL) /*!< ADC1CMPD6 (Bit 1) */
+#define HRPWM_COM_ADC1ER_ADC1CMPD6_Msk (0x2UL) /*!< ADC1CMPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC1ER_ADC1CMPB6_Pos (0UL) /*!< ADC1CMPB6 (Bit 0) */
+#define HRPWM_COM_ADC1ER_ADC1CMPB6_Msk (0x1UL) /*!< ADC1CMPB6 (Bitfield-Mask: 0x01) */
+/* ========================================================= ADC2R ========================================================= */
+#define HRPWM_COM_ADC2R_ADC2RST5_Pos (31UL) /*!< ADC2RST5 (Bit 31) */
+#define HRPWM_COM_ADC2R_ADC2RST5_Msk (0x80000000UL) /*!< ADC2RST5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER5_Pos (30UL) /*!< ADC2PER5 (Bit 30) */
+#define HRPWM_COM_ADC2R_ADC2PER5_Msk (0x40000000UL) /*!< ADC2PER5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD5_Pos (29UL) /*!< ADC2CMPD5 (Bit 29) */
+#define HRPWM_COM_ADC2R_ADC2CMPD5_Msk (0x20000000UL) /*!< ADC2CMPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC5_Pos (28UL) /*!< ADC2CMPC5 (Bit 28) */
+#define HRPWM_COM_ADC2R_ADC2CMPC5_Msk (0x10000000UL) /*!< ADC2CMPC5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPB5_Pos (27UL) /*!< ADC2CMPB5 (Bit 27) */
+#define HRPWM_COM_ADC2R_ADC2CMPB5_Msk (0x8000000UL) /*!< ADC2CMPB5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER4_Pos (26UL) /*!< ADC2PER4 (Bit 26) */
+#define HRPWM_COM_ADC2R_ADC2PER4_Msk (0x4000000UL) /*!< ADC2PER4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD4_Pos (25UL) /*!< ADC2CMPD4 (Bit 25) */
+#define HRPWM_COM_ADC2R_ADC2CMPD4_Msk (0x2000000UL) /*!< ADC2CMPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC4_Pos (24UL) /*!< ADC2CMPC4 (Bit 24) */
+#define HRPWM_COM_ADC2R_ADC2CMPC4_Msk (0x1000000UL) /*!< ADC2CMPC4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER3_Pos (23UL) /*!< ADC2PER3 (Bit 23) */
+#define HRPWM_COM_ADC2R_ADC2PER3_Msk (0x800000UL) /*!< ADC2PER3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD3_Pos (22UL) /*!< ADC2CMPD3 (Bit 22) */
+#define HRPWM_COM_ADC2R_ADC2CMPD3_Msk (0x400000UL) /*!< ADC2CMPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC3_Pos (21UL) /*!< ADC2CMPC3 (Bit 21) */
+#define HRPWM_COM_ADC2R_ADC2CMPC3_Msk (0x200000UL) /*!< ADC2CMPC3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER2_Pos (20UL) /*!< ADC2PER2 (Bit 20) */
+#define HRPWM_COM_ADC2R_ADC2PER2_Msk (0x100000UL) /*!< ADC2PER2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD2_Pos (19UL) /*!< ADC2CMPD2 (Bit 19) */
+#define HRPWM_COM_ADC2R_ADC2CMPD2_Msk (0x80000UL) /*!< ADC2CMPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC2_Pos (18UL) /*!< ADC2CMPC2 (Bit 18) */
+#define HRPWM_COM_ADC2R_ADC2CMPC2_Msk (0x40000UL) /*!< ADC2CMPC2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2RST1_Pos (17UL) /*!< ADC2RST1 (Bit 17) */
+#define HRPWM_COM_ADC2R_ADC2RST1_Msk (0x20000UL) /*!< ADC2RST1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER1_Pos (16UL) /*!< ADC2PER1 (Bit 16) */
+#define HRPWM_COM_ADC2R_ADC2PER1_Msk (0x10000UL) /*!< ADC2PER1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD1_Pos (15UL) /*!< ADC2CMPD1 (Bit 15) */
+#define HRPWM_COM_ADC2R_ADC2CMPD1_Msk (0x8000UL) /*!< ADC2CMPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC1_Pos (14UL) /*!< ADC2CMPC1 (Bit 14) */
+#define HRPWM_COM_ADC2R_ADC2CMPC1_Msk (0x4000UL) /*!< ADC2CMPC1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2RST0_Pos (13UL) /*!< ADC2RST0 (Bit 13) */
+#define HRPWM_COM_ADC2R_ADC2RST0_Msk (0x2000UL) /*!< ADC2RST0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2PER0_Pos (12UL) /*!< ADC2PER0 (Bit 12) */
+#define HRPWM_COM_ADC2R_ADC2PER0_Msk (0x1000UL) /*!< ADC2PER0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPD0_Pos (11UL) /*!< ADC2CMPD0 (Bit 11) */
+#define HRPWM_COM_ADC2R_ADC2CMPD0_Msk (0x800UL) /*!< ADC2CMPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2CMPC0_Pos (10UL) /*!< ADC2CMPC0 (Bit 10) */
+#define HRPWM_COM_ADC2R_ADC2CMPC0_Msk (0x400UL) /*!< ADC2CMPC0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2EEV4_Pos (9UL) /*!< ADC2EEV4 (Bit 9) */
+#define HRPWM_COM_ADC2R_ADC2EEV4_Msk (0x200UL) /*!< ADC2EEV4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2EEV3_Pos (8UL) /*!< ADC2EEV3 (Bit 8) */
+#define HRPWM_COM_ADC2R_ADC2EEV3_Msk (0x100UL) /*!< ADC2EEV3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2EEV2_Pos (7UL) /*!< ADC2EEV2 (Bit 7) */
+#define HRPWM_COM_ADC2R_ADC2EEV2_Msk (0x80UL) /*!< ADC2EEV2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2EEV1_Pos (6UL) /*!< ADC2EEV1 (Bit 6) */
+#define HRPWM_COM_ADC2R_ADC2EEV1_Msk (0x40UL) /*!< ADC2EEV1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2EEV0_Pos (5UL) /*!< ADC2EEV0 (Bit 5) */
+#define HRPWM_COM_ADC2R_ADC2EEV0_Msk (0x20UL) /*!< ADC2EEV0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2MPER_Pos (4UL) /*!< ADC2MPER (Bit 4) */
+#define HRPWM_COM_ADC2R_ADC2MPER_Msk (0x10UL) /*!< ADC2MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2MCMPD_Pos (3UL) /*!< ADC2MCMPD (Bit 3) */
+#define HRPWM_COM_ADC2R_ADC2MCMPD_Msk (0x8UL) /*!< ADC2MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2MCMPC_Pos (2UL) /*!< ADC2MCMPC (Bit 2) */
+#define HRPWM_COM_ADC2R_ADC2MCMPC_Msk (0x4UL) /*!< ADC2MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2MCMPB_Pos (1UL) /*!< ADC2MCMPB (Bit 1) */
+#define HRPWM_COM_ADC2R_ADC2MCMPB_Msk (0x2UL) /*!< ADC2MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2R_ADC2MCMPA_Pos (0UL) /*!< ADC2MCMPA (Bit 0) */
+#define HRPWM_COM_ADC2R_ADC2MCMPA_Msk (0x1UL) /*!< ADC2MCMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== ADC2ER ========================================================= */
+#define HRPWM_COM_ADC2ER_ADC2RST7_Pos (7UL) /*!< ADC2RST7 (Bit 7) */
+#define HRPWM_COM_ADC2ER_ADC2RST7_Msk (0x80UL) /*!< ADC2RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2PER7_Pos (6UL) /*!< ADC2PER7 (Bit 6) */
+#define HRPWM_COM_ADC2ER_ADC2PER7_Msk (0x40UL) /*!< ADC2PER7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2CMPD7_Pos (5UL) /*!< ADC2CMPD7 (Bit 5) */
+#define HRPWM_COM_ADC2ER_ADC2CMPD7_Msk (0x20UL) /*!< ADC2CMPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2CMPC7_Pos (4UL) /*!< ADC2CMPC7 (Bit 4) */
+#define HRPWM_COM_ADC2ER_ADC2CMPC7_Msk (0x10UL) /*!< ADC2CMPC7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2RST6_Pos (3UL) /*!< ADC2RST6 (Bit 3) */
+#define HRPWM_COM_ADC2ER_ADC2RST6_Msk (0x8UL) /*!< ADC2RST6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2PER6_Pos (2UL) /*!< ADC2PER6 (Bit 2) */
+#define HRPWM_COM_ADC2ER_ADC2PER6_Msk (0x4UL) /*!< ADC2PER6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2CMPD6_Pos (1UL) /*!< ADC2CMPD6 (Bit 1) */
+#define HRPWM_COM_ADC2ER_ADC2CMPD6_Msk (0x2UL) /*!< ADC2CMPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC2ER_ADC2CMPC6_Pos (0UL) /*!< ADC2CMPC6 (Bit 0) */
+#define HRPWM_COM_ADC2ER_ADC2CMPC6_Msk (0x1UL) /*!< ADC2CMPC6 (Bitfield-Mask: 0x01) */
+/* ========================================================= ADC3R ========================================================= */
+#define HRPWM_COM_ADC3R_ADC3PER5_Pos (31UL) /*!< ADC3PER5 (Bit 31) */
+#define HRPWM_COM_ADC3R_ADC3PER5_Msk (0x80000000UL) /*!< ADC3PER5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD5_Pos (30UL) /*!< ADC3CMPD5 (Bit 30) */
+#define HRPWM_COM_ADC3R_ADC3CMPD5_Msk (0x40000000UL) /*!< ADC3CMPD5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPC5_Pos (29UL) /*!< ADC3CMPC5 (Bit 29) */
+#define HRPWM_COM_ADC3R_ADC3CMPC5_Msk (0x20000000UL) /*!< ADC3CMPC5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB5_Pos (28UL) /*!< ADC3CMPB5 (Bit 28) */
+#define HRPWM_COM_ADC3R_ADC3CMPB5_Msk (0x10000000UL) /*!< ADC3CMPB5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3RST4_Pos (27UL) /*!< ADC3RST4 (Bit 27) */
+#define HRPWM_COM_ADC3R_ADC3RST4_Msk (0x8000000UL) /*!< ADC3RST4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD4_Pos (26UL) /*!< ADC3CMPD4 (Bit 26) */
+#define HRPWM_COM_ADC3R_ADC3CMPD4_Msk (0x4000000UL) /*!< ADC3CMPD4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPC4_Pos (25UL) /*!< ADC3CMPC4 (Bit 25) */
+#define HRPWM_COM_ADC3R_ADC3CMPC4_Msk (0x2000000UL) /*!< ADC3CMPC4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB4_Pos (24UL) /*!< ADC3CMPB4 (Bit 24) */
+#define HRPWM_COM_ADC3R_ADC3CMPB4_Msk (0x1000000UL) /*!< ADC3CMPB4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3RST3_Pos (23UL) /*!< ADC3RST3 (Bit 23) */
+#define HRPWM_COM_ADC3R_ADC3RST3_Msk (0x800000UL) /*!< ADC3RST3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3PER3_Pos (22UL) /*!< ADC3PER3 (Bit 22) */
+#define HRPWM_COM_ADC3R_ADC3PER3_Msk (0x400000UL) /*!< ADC3PER3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD3_Pos (21UL) /*!< ADC3CMPD3 (Bit 21) */
+#define HRPWM_COM_ADC3R_ADC3CMPD3_Msk (0x200000UL) /*!< ADC3CMPD3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB3_Pos (20UL) /*!< ADC3CMPB3 (Bit 20) */
+#define HRPWM_COM_ADC3R_ADC3CMPB3_Msk (0x100000UL) /*!< ADC3CMPB3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3RST2_Pos (19UL) /*!< ADC3RST2 (Bit 19) */
+#define HRPWM_COM_ADC3R_ADC3RST2_Msk (0x80000UL) /*!< ADC3RST2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3PER2_Pos (18UL) /*!< ADC3PER2 (Bit 18) */
+#define HRPWM_COM_ADC3R_ADC3PER2_Msk (0x40000UL) /*!< ADC3PER2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD2_Pos (17UL) /*!< ADC3CMPD2 (Bit 17) */
+#define HRPWM_COM_ADC3R_ADC3CMPD2_Msk (0x20000UL) /*!< ADC3CMPD2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB2_Pos (16UL) /*!< ADC3CMPB2 (Bit 16) */
+#define HRPWM_COM_ADC3R_ADC3CMPB2_Msk (0x10000UL) /*!< ADC3CMPB2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3PER1_Pos (15UL) /*!< ADC3PER1 (Bit 15) */
+#define HRPWM_COM_ADC3R_ADC3PER1_Msk (0x8000UL) /*!< ADC3PER1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD1_Pos (14UL) /*!< ADC3CMPD1 (Bit 14) */
+#define HRPWM_COM_ADC3R_ADC3CMPD1_Msk (0x4000UL) /*!< ADC3CMPD1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB1_Pos (13UL) /*!< ADC3CMPB1 (Bit 13) */
+#define HRPWM_COM_ADC3R_ADC3CMPB1_Msk (0x2000UL) /*!< ADC3CMPB1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3PER0_Pos (12UL) /*!< ADC3PER0 (Bit 12) */
+#define HRPWM_COM_ADC3R_ADC3PER0_Msk (0x1000UL) /*!< ADC3PER0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPD0_Pos (11UL) /*!< ADC3CMPD0 (Bit 11) */
+#define HRPWM_COM_ADC3R_ADC3CMPD0_Msk (0x800UL) /*!< ADC3CMPD0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3CMPB0_Pos (10UL) /*!< ADC3CMPB0 (Bit 10) */
+#define HRPWM_COM_ADC3R_ADC3CMPB0_Msk (0x400UL) /*!< ADC3CMPB0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3EEV9_Pos (9UL) /*!< ADC3EEV9 (Bit 9) */
+#define HRPWM_COM_ADC3R_ADC3EEV9_Msk (0x200UL) /*!< ADC3EEV9 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3EEV8_Pos (8UL) /*!< ADC3EEV8 (Bit 8) */
+#define HRPWM_COM_ADC3R_ADC3EEV8_Msk (0x100UL) /*!< ADC3EEV8 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3EEV7_Pos (7UL) /*!< ADC3EEV7 (Bit 7) */
+#define HRPWM_COM_ADC3R_ADC3EEV7_Msk (0x80UL) /*!< ADC3EEV7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3EEV6_Pos (6UL) /*!< ADC3EEV6 (Bit 6) */
+#define HRPWM_COM_ADC3R_ADC3EEV6_Msk (0x40UL) /*!< ADC3EEV6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3EEV5_Pos (5UL) /*!< ADC3EEV5 (Bit 5) */
+#define HRPWM_COM_ADC3R_ADC3EEV5_Msk (0x20UL) /*!< ADC3EEV5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3MPER_Pos (4UL) /*!< ADC3MPER (Bit 4) */
+#define HRPWM_COM_ADC3R_ADC3MPER_Msk (0x10UL) /*!< ADC3MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3MCMPD_Pos (3UL) /*!< ADC3MCMPD (Bit 3) */
+#define HRPWM_COM_ADC3R_ADC3MCMPD_Msk (0x8UL) /*!< ADC3MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3MCMPC_Pos (2UL) /*!< ADC3MCMPC (Bit 2) */
+#define HRPWM_COM_ADC3R_ADC3MCMPC_Msk (0x4UL) /*!< ADC3MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3MCMPB_Pos (1UL) /*!< ADC3MCMPB (Bit 1) */
+#define HRPWM_COM_ADC3R_ADC3MCMPB_Msk (0x2UL) /*!< ADC3MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3R_ADC3MCMPA_Pos (0UL) /*!< ADC3MCMPA (Bit 0) */
+#define HRPWM_COM_ADC3R_ADC3MCMPA_Msk (0x1UL) /*!< ADC3MCMPA (Bitfield-Mask: 0x01) */
+/* ======================================================== ADC3ER ========================================================= */
+#define HRPWM_COM_ADC3ER_ADC3RST7_Pos (7UL) /*!< ADC3RST7 (Bit 7) */
+#define HRPWM_COM_ADC3ER_ADC3RST7_Msk (0x80UL) /*!< ADC3RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3PER7_Pos (6UL) /*!< ADC3PER7 (Bit 6) */
+#define HRPWM_COM_ADC3ER_ADC3PER7_Msk (0x40UL) /*!< ADC3PER7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3CMPD7_Pos (5UL) /*!< ADC3CMPD7 (Bit 5) */
+#define HRPWM_COM_ADC3ER_ADC3CMPD7_Msk (0x20UL) /*!< ADC3CMPD7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3CMPB7_Pos (4UL) /*!< ADC3CMPB7 (Bit 4) */
+#define HRPWM_COM_ADC3ER_ADC3CMPB7_Msk (0x10UL) /*!< ADC3CMPB7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3RST6_Pos (3UL) /*!< ADC3RST6 (Bit 3) */
+#define HRPWM_COM_ADC3ER_ADC3RST6_Msk (0x8UL) /*!< ADC3RST6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3PER6_Pos (2UL) /*!< ADC3PER6 (Bit 2) */
+#define HRPWM_COM_ADC3ER_ADC3PER6_Msk (0x4UL) /*!< ADC3PER6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3CMPD6_Pos (1UL) /*!< ADC3CMPD6 (Bit 1) */
+#define HRPWM_COM_ADC3ER_ADC3CMPD6_Msk (0x2UL) /*!< ADC3CMPD6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_ADC3ER_ADC3CMPB6_Pos (0UL) /*!< ADC3CMPB6 (Bit 0) */
+#define HRPWM_COM_ADC3ER_ADC3CMPB6_Msk (0x1UL) /*!< ADC3CMPB6 (Bitfield-Mask: 0x01) */
+/* ========================================================= ADC4R ========================================================= */
+#define HRPWM_COM_ADC4R_ADC6TRG_Pos (16UL) /*!< ADC6TRG (Bit 16) */
+#define HRPWM_COM_ADC4R_ADC6TRG_Msk (0x3f0000UL) /*!< ADC6TRG (Bitfield-Mask: 0x3f) */
+#define HRPWM_COM_ADC4R_ADC5TRG_Pos (8UL) /*!< ADC5TRG (Bit 8) */
+#define HRPWM_COM_ADC4R_ADC5TRG_Msk (0x3f00UL) /*!< ADC5TRG (Bitfield-Mask: 0x3f) */
+#define HRPWM_COM_ADC4R_ADC4TRG_Pos (0UL) /*!< ADC4TRG (Bit 0) */
+#define HRPWM_COM_ADC4R_ADC4TRG_Msk (0x3fUL) /*!< ADC4TRG (Bitfield-Mask: 0x3f) */
+/* ========================================================= ADC5R ========================================================= */
+#define HRPWM_COM_ADC5R_ADC9TRG_Pos (16UL) /*!< ADC9TRG (Bit 16) */
+#define HRPWM_COM_ADC5R_ADC9TRG_Msk (0x3f0000UL) /*!< ADC9TRG (Bitfield-Mask: 0x3f) */
+#define HRPWM_COM_ADC5R_ADC8TRG_Pos (8UL) /*!< ADC8TRG (Bit 8) */
+#define HRPWM_COM_ADC5R_ADC8TRG_Msk (0x3f00UL) /*!< ADC8TRG (Bitfield-Mask: 0x3f) */
+#define HRPWM_COM_ADC5R_ADC7TRG_Pos (0UL) /*!< ADC7TRG (Bit 0) */
+#define HRPWM_COM_ADC5R_ADC7TRG_Msk (0x3fUL) /*!< ADC7TRG (Bitfield-Mask: 0x3f) */
+/* ========================================================= ADCUR ========================================================= */
+#define HRPWM_COM_ADCUR_USRC9_Pos (20UL) /*!< USRC9 (Bit 20) */
+#define HRPWM_COM_ADCUR_USRC9_Msk (0xf00000UL) /*!< USRC9 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCUR_USRC8_Pos (16UL) /*!< USRC8 (Bit 16) */
+#define HRPWM_COM_ADCUR_USRC8_Msk (0xf0000UL) /*!< USRC8 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCUR_USRC7_Pos (12UL) /*!< USRC7 (Bit 12) */
+#define HRPWM_COM_ADCUR_USRC7_Msk (0xf000UL) /*!< USRC7 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCUR_USRC6_Pos (8UL) /*!< USRC6 (Bit 8) */
+#define HRPWM_COM_ADCUR_USRC6_Msk (0xf00UL) /*!< USRC6 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCUR_USRC5_Pos (4UL) /*!< USRC5 (Bit 4) */
+#define HRPWM_COM_ADCUR_USRC5_Msk (0xf0UL) /*!< USRC5 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCUR_USRC4_Pos (0UL) /*!< USRC4 (Bit 0) */
+#define HRPWM_COM_ADCUR_USRC4_Msk (0xfUL) /*!< USRC4 (Bitfield-Mask: 0x0f) */
+/* ========================================================= ADCLR ========================================================= */
+#define HRPWM_COM_ADCLR_TLEN9_Pos (20UL) /*!< TLEN9 (Bit 20) */
+#define HRPWM_COM_ADCLR_TLEN9_Msk (0xf00000UL) /*!< TLEN9 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCLR_TLEN8_Pos (16UL) /*!< TLEN8 (Bit 16) */
+#define HRPWM_COM_ADCLR_TLEN8_Msk (0xf0000UL) /*!< TLEN8 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCLR_TLEN7_Pos (12UL) /*!< TLEN7 (Bit 12) */
+#define HRPWM_COM_ADCLR_TLEN7_Msk (0xf000UL) /*!< TLEN7 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCLR_TLEN6_Pos (8UL) /*!< TLEN6 (Bit 8) */
+#define HRPWM_COM_ADCLR_TLEN6_Msk (0xf00UL) /*!< TLEN6 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCLR_TLEN5_Pos (4UL) /*!< TLEN5 (Bit 4) */
+#define HRPWM_COM_ADCLR_TLEN5_Msk (0xf0UL) /*!< TLEN5 (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_ADCLR_TLEN4_Pos (0UL) /*!< TLEN4 (Bit 0) */
+#define HRPWM_COM_ADCLR_TLEN4_Msk (0xfUL) /*!< TLEN4 (Bitfield-Mask: 0x0f) */
+/* ======================================================== ADPSR0 ========================================================= */
+#define HRPWM_COM_ADPSR0_PSC4_Pos (24UL) /*!< PSC4 (Bit 24) */
+#define HRPWM_COM_ADPSR0_PSC4_Msk (0x1f000000UL) /*!< PSC4 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR0_PSC3_Pos (18UL) /*!< PSC3 (Bit 18) */
+#define HRPWM_COM_ADPSR0_PSC3_Msk (0x7c0000UL) /*!< PSC3 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR0_PSC2_Pos (12UL) /*!< PSC2 (Bit 12) */
+#define HRPWM_COM_ADPSR0_PSC2_Msk (0x1f000UL) /*!< PSC2 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR0_PSC1_Pos (6UL) /*!< PSC1 (Bit 6) */
+#define HRPWM_COM_ADPSR0_PSC1_Msk (0x7c0UL) /*!< PSC1 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR0_PSC0_Pos (0UL) /*!< PSC0 (Bit 0) */
+#define HRPWM_COM_ADPSR0_PSC0_Msk (0x1fUL) /*!< PSC0 (Bitfield-Mask: 0x1f) */
+/* ======================================================== ADPSR1 ========================================================= */
+#define HRPWM_COM_ADPSR1_PSC9_Pos (24UL) /*!< PSC9 (Bit 24) */
+#define HRPWM_COM_ADPSR1_PSC9_Msk (0x1f000000UL) /*!< PSC9 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR1_PSC8_Pos (18UL) /*!< PSC8 (Bit 18) */
+#define HRPWM_COM_ADPSR1_PSC8_Msk (0x7c0000UL) /*!< PSC8 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR1_PSC7_Pos (12UL) /*!< PSC7 (Bit 12) */
+#define HRPWM_COM_ADPSR1_PSC7_Msk (0x1f000UL) /*!< PSC7 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR1_PSC6_Pos (6UL) /*!< PSC6 (Bit 6) */
+#define HRPWM_COM_ADPSR1_PSC6_Msk (0x7c0UL) /*!< PSC6 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_ADPSR1_PSC5_Pos (0UL) /*!< PSC5 (Bit 0) */
+#define HRPWM_COM_ADPSR1_PSC5_Msk (0x1fUL) /*!< PSC5 (Bitfield-Mask: 0x1f) */
+/* ========================================================= DLLCR ========================================================= */
+#define HRPWM_COM_DLLCR_DLLLCK_Pos (31UL) /*!< DLLLCK (Bit 31) */
+#define HRPWM_COM_DLLCR_DLLLCK_Msk (0x80000000UL) /*!< DLLLCK (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_DLLCR_DLLTHRES0_Pos (11UL) /*!< DLLTHRES0 (Bit 11) */
+#define HRPWM_COM_DLLCR_DLLTHRES0_Msk (0xf800UL) /*!< DLLTHRES0 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_DLLCR_DLLTHRES1_Pos (6UL) /*!< DLLTHRES1 (Bit 6) */
+#define HRPWM_COM_DLLCR_DLLTHRES1_Msk (0x7c0UL) /*!< DLLTHRES1 (Bitfield-Mask: 0x1f) */
+#define HRPWM_COM_DLLCR_DLLSTART_Pos (3UL) /*!< DLLSTART (Bit 3) */
+#define HRPWM_COM_DLLCR_DLLSTART_Msk (0x8UL) /*!< DLLSTART (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_DLLCR_DLLGCP_Pos (1UL) /*!< DLLGCP (Bit 1) */
+#define HRPWM_COM_DLLCR_DLLGCP_Msk (0x6UL) /*!< DLLGCP (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_DLLCR_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */
+#define HRPWM_COM_DLLCR_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */
+/* ========================================================= EECER ========================================================= */
+#define HRPWM_COM_EECER_EE9SRCH_Pos (18UL) /*!< EE9SRCH (Bit 18) */
+#define HRPWM_COM_EECER_EE9SRCH_Msk (0xc0000UL) /*!< EE9SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE8SRCH_Pos (16UL) /*!< EE8SRCH (Bit 16) */
+#define HRPWM_COM_EECER_EE8SRCH_Msk (0x30000UL) /*!< EE8SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE7SRCH_Pos (14UL) /*!< EE7SRCH (Bit 14) */
+#define HRPWM_COM_EECER_EE7SRCH_Msk (0xc000UL) /*!< EE7SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE6SRCH_Pos (12UL) /*!< EE6SRCH (Bit 12) */
+#define HRPWM_COM_EECER_EE6SRCH_Msk (0x3000UL) /*!< EE6SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE5SRCH_Pos (10UL) /*!< EE5SRCH (Bit 10) */
+#define HRPWM_COM_EECER_EE5SRCH_Msk (0xc00UL) /*!< EE5SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE4SRCH_Pos (8UL) /*!< EE4SRCH (Bit 8) */
+#define HRPWM_COM_EECER_EE4SRCH_Msk (0x300UL) /*!< EE4SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE3SRCH_Pos (6UL) /*!< EE3SRCH (Bit 6) */
+#define HRPWM_COM_EECER_EE3SRCH_Msk (0xc0UL) /*!< EE3SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE2SRCH_Pos (4UL) /*!< EE2SRCH (Bit 4) */
+#define HRPWM_COM_EECER_EE2SRCH_Msk (0x30UL) /*!< EE2SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE1SRCH_Pos (2UL) /*!< EE1SRCH (Bit 2) */
+#define HRPWM_COM_EECER_EE1SRCH_Msk (0xcUL) /*!< EE1SRCH (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_EECER_EE0SRCH_Pos (0UL) /*!< EE0SRCH (Bit 0) */
+#define HRPWM_COM_EECER_EE0SRCH_Msk (0x3UL) /*!< EE0SRCH (Bitfield-Mask: 0x03) */
+/* ======================================================== FLTINR0 ======================================================== */
+#define HRPWM_COM_FLTINR0_FLT7SRC_Pos (30UL) /*!< FLT7SRC (Bit 30) */
+#define HRPWM_COM_FLTINR0_FLT7SRC_Msk (0xc0000000UL) /*!< FLT7SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT7P_Pos (29UL) /*!< FLT7P (Bit 29) */
+#define HRPWM_COM_FLTINR0_FLT7P_Msk (0x20000000UL) /*!< FLT7P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT7E_Pos (28UL) /*!< FLT7E (Bit 28) */
+#define HRPWM_COM_FLTINR0_FLT7E_Msk (0x10000000UL) /*!< FLT7E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT6SRC_Pos (26UL) /*!< FLT6SRC (Bit 26) */
+#define HRPWM_COM_FLTINR0_FLT6SRC_Msk (0xc000000UL) /*!< FLT6SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT6P_Pos (25UL) /*!< FLT6P (Bit 25) */
+#define HRPWM_COM_FLTINR0_FLT6P_Msk (0x2000000UL) /*!< FLT6P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT6E_Pos (24UL) /*!< FLT6E (Bit 24) */
+#define HRPWM_COM_FLTINR0_FLT6E_Msk (0x1000000UL) /*!< FLT6E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT5SRC_Pos (22UL) /*!< FLT5SRC (Bit 22) */
+#define HRPWM_COM_FLTINR0_FLT5SRC_Msk (0xc00000UL) /*!< FLT5SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT5P_Pos (21UL) /*!< FLT5P (Bit 21) */
+#define HRPWM_COM_FLTINR0_FLT5P_Msk (0x200000UL) /*!< FLT5P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT5E_Pos (20UL) /*!< FLT5E (Bit 20) */
+#define HRPWM_COM_FLTINR0_FLT5E_Msk (0x100000UL) /*!< FLT5E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT4SRC_Pos (18UL) /*!< FLT4SRC (Bit 18) */
+#define HRPWM_COM_FLTINR0_FLT4SRC_Msk (0xc0000UL) /*!< FLT4SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT4P_Pos (17UL) /*!< FLT4P (Bit 17) */
+#define HRPWM_COM_FLTINR0_FLT4P_Msk (0x20000UL) /*!< FLT4P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT4E_Pos (16UL) /*!< FLT4E (Bit 16) */
+#define HRPWM_COM_FLTINR0_FLT4E_Msk (0x10000UL) /*!< FLT4E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT3SRC_Pos (14UL) /*!< FLT3SRC (Bit 14) */
+#define HRPWM_COM_FLTINR0_FLT3SRC_Msk (0xc000UL) /*!< FLT3SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT3P_Pos (13UL) /*!< FLT3P (Bit 13) */
+#define HRPWM_COM_FLTINR0_FLT3P_Msk (0x2000UL) /*!< FLT3P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT3E_Pos (12UL) /*!< FLT3E (Bit 12) */
+#define HRPWM_COM_FLTINR0_FLT3E_Msk (0x1000UL) /*!< FLT3E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT2SRC_Pos (10UL) /*!< FLT2SRC (Bit 10) */
+#define HRPWM_COM_FLTINR0_FLT2SRC_Msk (0xc00UL) /*!< FLT2SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT2P_Pos (9UL) /*!< FLT2P (Bit 9) */
+#define HRPWM_COM_FLTINR0_FLT2P_Msk (0x200UL) /*!< FLT2P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT2E_Pos (8UL) /*!< FLT2E (Bit 8) */
+#define HRPWM_COM_FLTINR0_FLT2E_Msk (0x100UL) /*!< FLT2E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT1SRC_Pos (6UL) /*!< FLT1SRC (Bit 6) */
+#define HRPWM_COM_FLTINR0_FLT1SRC_Msk (0xc0UL) /*!< FLT1SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT1P_Pos (5UL) /*!< FLT1P (Bit 5) */
+#define HRPWM_COM_FLTINR0_FLT1P_Msk (0x20UL) /*!< FLT1P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT1E_Pos (4UL) /*!< FLT1E (Bit 4) */
+#define HRPWM_COM_FLTINR0_FLT1E_Msk (0x10UL) /*!< FLT1E (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT0SRC_Pos (2UL) /*!< FLT0SRC (Bit 2) */
+#define HRPWM_COM_FLTINR0_FLT0SRC_Msk (0xcUL) /*!< FLT0SRC (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR0_FLT0P_Pos (1UL) /*!< FLT0P (Bit 1) */
+#define HRPWM_COM_FLTINR0_FLT0P_Msk (0x2UL) /*!< FLT0P (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR0_FLT0E_Pos (0UL) /*!< FLT0E (Bit 0) */
+#define HRPWM_COM_FLTINR0_FLT0E_Msk (0x1UL) /*!< FLT0E (Bitfield-Mask: 0x01) */
+/* ======================================================== FLTINR1 ======================================================== */
+#define HRPWM_COM_FLTINR1_FLTSD_Pos (30UL) /*!< FLTSD (Bit 30) */
+#define HRPWM_COM_FLTINR1_FLTSD_Msk (0xc0000000UL) /*!< FLTSD (Bitfield-Mask: 0x03) */
+#define HRPWM_COM_FLTINR1_FLT5F_Pos (20UL) /*!< FLT5F (Bit 20) */
+#define HRPWM_COM_FLTINR1_FLT5F_Msk (0xf00000UL) /*!< FLT5F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR1_FLT4F_Pos (16UL) /*!< FLT4F (Bit 16) */
+#define HRPWM_COM_FLTINR1_FLT4F_Msk (0xf0000UL) /*!< FLT4F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR1_FLT3F_Pos (12UL) /*!< FLT3F (Bit 12) */
+#define HRPWM_COM_FLTINR1_FLT3F_Msk (0xf000UL) /*!< FLT3F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR1_FLT2F_Pos (8UL) /*!< FLT2F (Bit 8) */
+#define HRPWM_COM_FLTINR1_FLT2F_Msk (0xf00UL) /*!< FLT2F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR1_FLT1F_Pos (4UL) /*!< FLT1F (Bit 4) */
+#define HRPWM_COM_FLTINR1_FLT1F_Msk (0xf0UL) /*!< FLT1F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR1_FLT0F_Pos (0UL) /*!< FLT0F (Bit 0) */
+#define HRPWM_COM_FLTINR1_FLT0F_Msk (0xfUL) /*!< FLT0F (Bitfield-Mask: 0x0f) */
+/* ======================================================== FLTINER ======================================================== */
+#define HRPWM_COM_FLTINER_FLT7F_Pos (4UL) /*!< FLT7F (Bit 4) */
+#define HRPWM_COM_FLTINER_FLT7F_Msk (0xf0UL) /*!< FLT7F (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINER_FLT6F_Pos (0UL) /*!< FLT6F (Bit 0) */
+#define HRPWM_COM_FLTINER_FLT6F_Msk (0xfUL) /*!< FLT6F (Bitfield-Mask: 0x0f) */
+/* ======================================================== FLTINR2 ======================================================== */
+#define HRPWM_COM_FLTINR2_FLT7RSTM_Pos (31UL) /*!< FLT7RSTM (Bit 31) */
+#define HRPWM_COM_FLTINR2_FLT7RSTM_Msk (0x80000000UL) /*!< FLT7RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT7CRES_Pos (30UL) /*!< FLT7CRES (Bit 30) */
+#define HRPWM_COM_FLTINR2_FLT7CRES_Msk (0x40000000UL) /*!< FLT7CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT7BLKS_Pos (29UL) /*!< FLT7BLKS (Bit 29) */
+#define HRPWM_COM_FLTINR2_FLT7BLKS_Msk (0x20000000UL) /*!< FLT7BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT7BLKE_Pos (28UL) /*!< FLT7BLKE (Bit 28) */
+#define HRPWM_COM_FLTINR2_FLT7BLKE_Msk (0x10000000UL) /*!< FLT7BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT6RSTM_Pos (27UL) /*!< FLT6RSTM (Bit 27) */
+#define HRPWM_COM_FLTINR2_FLT6RSTM_Msk (0x8000000UL) /*!< FLT6RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT6CRES_Pos (26UL) /*!< FLT6CRES (Bit 26) */
+#define HRPWM_COM_FLTINR2_FLT6CRES_Msk (0x4000000UL) /*!< FLT6CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT6BLKS_Pos (25UL) /*!< FLT6BLKS (Bit 25) */
+#define HRPWM_COM_FLTINR2_FLT6BLKS_Msk (0x2000000UL) /*!< FLT6BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT6BLKE_Pos (24UL) /*!< FLT6BLKE (Bit 24) */
+#define HRPWM_COM_FLTINR2_FLT6BLKE_Msk (0x1000000UL) /*!< FLT6BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT5RSTM_Pos (23UL) /*!< FLT5RSTM (Bit 23) */
+#define HRPWM_COM_FLTINR2_FLT5RSTM_Msk (0x800000UL) /*!< FLT5RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT5CRES_Pos (22UL) /*!< FLT5CRES (Bit 22) */
+#define HRPWM_COM_FLTINR2_FLT5CRES_Msk (0x400000UL) /*!< FLT5CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT5BLKS_Pos (21UL) /*!< FLT5BLKS (Bit 21) */
+#define HRPWM_COM_FLTINR2_FLT5BLKS_Msk (0x200000UL) /*!< FLT5BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT5BLKE_Pos (20UL) /*!< FLT5BLKE (Bit 20) */
+#define HRPWM_COM_FLTINR2_FLT5BLKE_Msk (0x100000UL) /*!< FLT5BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT4RSTM_Pos (19UL) /*!< FLT4RSTM (Bit 19) */
+#define HRPWM_COM_FLTINR2_FLT4RSTM_Msk (0x80000UL) /*!< FLT4RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT4CRES_Pos (18UL) /*!< FLT4CRES (Bit 18) */
+#define HRPWM_COM_FLTINR2_FLT4CRES_Msk (0x40000UL) /*!< FLT4CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT4BLKS_Pos (17UL) /*!< FLT4BLKS (Bit 17) */
+#define HRPWM_COM_FLTINR2_FLT4BLKS_Msk (0x20000UL) /*!< FLT4BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT4BLKE_Pos (16UL) /*!< FLT4BLKE (Bit 16) */
+#define HRPWM_COM_FLTINR2_FLT4BLKE_Msk (0x10000UL) /*!< FLT4BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT3RSTM_Pos (15UL) /*!< FLT3RSTM (Bit 15) */
+#define HRPWM_COM_FLTINR2_FLT3RSTM_Msk (0x8000UL) /*!< FLT3RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT3CRES_Pos (14UL) /*!< FLT3CRES (Bit 14) */
+#define HRPWM_COM_FLTINR2_FLT3CRES_Msk (0x4000UL) /*!< FLT3CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT3BLKS_Pos (13UL) /*!< FLT3BLKS (Bit 13) */
+#define HRPWM_COM_FLTINR2_FLT3BLKS_Msk (0x2000UL) /*!< FLT3BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT3BLKE_Pos (12UL) /*!< FLT3BLKE (Bit 12) */
+#define HRPWM_COM_FLTINR2_FLT3BLKE_Msk (0x1000UL) /*!< FLT3BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT2RSTM_Pos (11UL) /*!< FLT2RSTM (Bit 11) */
+#define HRPWM_COM_FLTINR2_FLT2RSTM_Msk (0x800UL) /*!< FLT2RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT2CRES_Pos (10UL) /*!< FLT2CRES (Bit 10) */
+#define HRPWM_COM_FLTINR2_FLT2CRES_Msk (0x400UL) /*!< FLT2CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT2BLKS_Pos (9UL) /*!< FLT2BLKS (Bit 9) */
+#define HRPWM_COM_FLTINR2_FLT2BLKS_Msk (0x200UL) /*!< FLT2BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT2BLKE_Pos (8UL) /*!< FLT2BLKE (Bit 8) */
+#define HRPWM_COM_FLTINR2_FLT2BLKE_Msk (0x100UL) /*!< FLT2BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT1RSTM_Pos (7UL) /*!< FLT1RSTM (Bit 7) */
+#define HRPWM_COM_FLTINR2_FLT1RSTM_Msk (0x80UL) /*!< FLT1RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT1CRES_Pos (6UL) /*!< FLT1CRES (Bit 6) */
+#define HRPWM_COM_FLTINR2_FLT1CRES_Msk (0x40UL) /*!< FLT1CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT1BLKS_Pos (5UL) /*!< FLT1BLKS (Bit 5) */
+#define HRPWM_COM_FLTINR2_FLT1BLKS_Msk (0x20UL) /*!< FLT1BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT1BLKE_Pos (4UL) /*!< FLT1BLKE (Bit 4) */
+#define HRPWM_COM_FLTINR2_FLT1BLKE_Msk (0x10UL) /*!< FLT1BLKE (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT0RSTM_Pos (3UL) /*!< FLT0RSTM (Bit 3) */
+#define HRPWM_COM_FLTINR2_FLT0RSTM_Msk (0x8UL) /*!< FLT0RSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT0CRES_Pos (2UL) /*!< FLT0CRES (Bit 2) */
+#define HRPWM_COM_FLTINR2_FLT0CRES_Msk (0x4UL) /*!< FLT0CRES (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT0BLKS_Pos (1UL) /*!< FLT0BLKS (Bit 1) */
+#define HRPWM_COM_FLTINR2_FLT0BLKS_Msk (0x2UL) /*!< FLT0BLKS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_FLTINR2_FLT0BLKE_Pos (0UL) /*!< FLT0BLKE (Bit 0) */
+#define HRPWM_COM_FLTINR2_FLT0BLKE_Msk (0x1UL) /*!< FLT0BLKE (Bitfield-Mask: 0x01) */
+/* ======================================================== FLTINR3 ======================================================== */
+#define HRPWM_COM_FLTINR3_FLT7CNT_Pos (28UL) /*!< FLT7CNT (Bit 28) */
+#define HRPWM_COM_FLTINR3_FLT7CNT_Msk (0xf0000000UL) /*!< FLT7CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT6CNT_Pos (24UL) /*!< FLT6CNT (Bit 24) */
+#define HRPWM_COM_FLTINR3_FLT6CNT_Msk (0xf000000UL) /*!< FLT6CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT5CNT_Pos (20UL) /*!< FLT5CNT (Bit 20) */
+#define HRPWM_COM_FLTINR3_FLT5CNT_Msk (0xf00000UL) /*!< FLT5CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT4CNT_Pos (16UL) /*!< FLT4CNT (Bit 16) */
+#define HRPWM_COM_FLTINR3_FLT4CNT_Msk (0xf0000UL) /*!< FLT4CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT3CNT_Pos (12UL) /*!< FLT3CNT (Bit 12) */
+#define HRPWM_COM_FLTINR3_FLT3CNT_Msk (0xf000UL) /*!< FLT3CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT2CNT_Pos (8UL) /*!< FLT2CNT (Bit 8) */
+#define HRPWM_COM_FLTINR3_FLT2CNT_Msk (0xf00UL) /*!< FLT2CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT1CNT_Pos (4UL) /*!< FLT1CNT (Bit 4) */
+#define HRPWM_COM_FLTINR3_FLT1CNT_Msk (0xf0UL) /*!< FLT1CNT (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_FLTINR3_FLT0CNT_Pos (0UL) /*!< FLT0CNT (Bit 0) */
+#define HRPWM_COM_FLTINR3_FLT0CNT_Msk (0xfUL) /*!< FLT0CNT (Bitfield-Mask: 0x0f) */
+/* ========================================================= BMCR ========================================================== */
+#define HRPWM_COM_BMCR_BMSTAT_Pos (31UL) /*!< BMSTAT (Bit 31) */
+#define HRPWM_COM_BMCR_BMSTAT_Msk (0x80000000UL) /*!< BMSTAT (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMEXIT_Pos (30UL) /*!< BMEXIT (Bit 30) */
+#define HRPWM_COM_BMCR_BMEXIT_Msk (0x40000000UL) /*!< BMEXIT (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS7_Pos (24UL) /*!< BMDIS7 (Bit 24) */
+#define HRPWM_COM_BMCR_BMDIS7_Msk (0x1000000UL) /*!< BMDIS7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS6_Pos (23UL) /*!< BMDIS6 (Bit 23) */
+#define HRPWM_COM_BMCR_BMDIS6_Msk (0x800000UL) /*!< BMDIS6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS5_Pos (22UL) /*!< BMDIS5 (Bit 22) */
+#define HRPWM_COM_BMCR_BMDIS5_Msk (0x400000UL) /*!< BMDIS5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS4_Pos (21UL) /*!< BMDIS4 (Bit 21) */
+#define HRPWM_COM_BMCR_BMDIS4_Msk (0x200000UL) /*!< BMDIS4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS3_Pos (20UL) /*!< BMDIS3 (Bit 20) */
+#define HRPWM_COM_BMCR_BMDIS3_Msk (0x100000UL) /*!< BMDIS3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS2_Pos (19UL) /*!< BMDIS2 (Bit 19) */
+#define HRPWM_COM_BMCR_BMDIS2_Msk (0x80000UL) /*!< BMDIS2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS1_Pos (18UL) /*!< BMDIS1 (Bit 18) */
+#define HRPWM_COM_BMCR_BMDIS1_Msk (0x40000UL) /*!< BMDIS1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMDIS0_Pos (17UL) /*!< BMDIS0 (Bit 17) */
+#define HRPWM_COM_BMCR_BMDIS0_Msk (0x20000UL) /*!< BMDIS0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_MBMDIS_Pos (16UL) /*!< MBMDIS (Bit 16) */
+#define HRPWM_COM_BMCR_MBMDIS_Msk (0x10000UL) /*!< MBMDIS (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMTM_Pos (11UL) /*!< BMTM (Bit 11) */
+#define HRPWM_COM_BMCR_BMTM_Msk (0x800UL) /*!< BMTM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMPREN_Pos (10UL) /*!< BMPREN (Bit 10) */
+#define HRPWM_COM_BMCR_BMPREN_Msk (0x400UL) /*!< BMPREN (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BMPRSC_Pos (6UL) /*!< BMPRSC (Bit 6) */
+#define HRPWM_COM_BMCR_BMPRSC_Msk (0x3c0UL) /*!< BMPRSC (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_BMCR_BMCLK_Pos (2UL) /*!< BMCLK (Bit 2) */
+#define HRPWM_COM_BMCR_BMCLK_Msk (0x3cUL) /*!< BMCLK (Bitfield-Mask: 0x0f) */
+#define HRPWM_COM_BMCR_BMOM_Pos (1UL) /*!< BMOM (Bit 1) */
+#define HRPWM_COM_BMCR_BMOM_Msk (0x2UL) /*!< BMOM (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMCR_BME_Pos (0UL) /*!< BME (Bit 0) */
+#define HRPWM_COM_BMCR_BME_Msk (0x1UL) /*!< BME (Bitfield-Mask: 0x01) */
+/* ======================================================== BMTRGR0 ======================================================== */
+#define HRPWM_COM_BMTRGR0_OCHPEV_Pos (31UL) /*!< OCHPEV (Bit 31) */
+#define HRPWM_COM_BMTRGR0_OCHPEV_Msk (0x80000000UL) /*!< OCHPEV (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_EEV8_Pos (30UL) /*!< EEV8 (Bit 30) */
+#define HRPWM_COM_BMTRGR0_EEV8_Msk (0x40000000UL) /*!< EEV8 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_EEV7_Pos (29UL) /*!< EEV7 (Bit 29) */
+#define HRPWM_COM_BMTRGR0_EEV7_Msk (0x20000000UL) /*!< EEV7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_PER4EEV8_Pos (28UL) /*!< PER4EEV8 (Bit 28) */
+#define HRPWM_COM_BMTRGR0_PER4EEV8_Msk (0x10000000UL) /*!< PER4EEV8 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_PER0EEV7_Pos (27UL) /*!< PER0EEV7 (Bit 27) */
+#define HRPWM_COM_BMTRGR0_PER0EEV7_Msk (0x8000000UL) /*!< PER0EEV7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPA5_Pos (26UL) /*!< CMPA5 (Bit 26) */
+#define HRPWM_COM_BMTRGR0_CMPA5_Msk (0x4000000UL) /*!< CMPA5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP5_Pos (25UL) /*!< REP5 (Bit 25) */
+#define HRPWM_COM_BMTRGR0_REP5_Msk (0x2000000UL) /*!< REP5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_RST5_Pos (24UL) /*!< RST5 (Bit 24) */
+#define HRPWM_COM_BMTRGR0_RST5_Msk (0x1000000UL) /*!< RST5 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPB4_Pos (23UL) /*!< CMPB4 (Bit 23) */
+#define HRPWM_COM_BMTRGR0_CMPB4_Msk (0x800000UL) /*!< CMPB4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPA4_Pos (22UL) /*!< CMPA4 (Bit 22) */
+#define HRPWM_COM_BMTRGR0_CMPA4_Msk (0x400000UL) /*!< CMPA4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP4_Pos (21UL) /*!< REP4 (Bit 21) */
+#define HRPWM_COM_BMTRGR0_REP4_Msk (0x200000UL) /*!< REP4 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPB3_Pos (20UL) /*!< CMPB3 (Bit 20) */
+#define HRPWM_COM_BMTRGR0_CMPB3_Msk (0x100000UL) /*!< CMPB3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP3_Pos (19UL) /*!< REP3 (Bit 19) */
+#define HRPWM_COM_BMTRGR0_REP3_Msk (0x80000UL) /*!< REP3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_RST3_Pos (18UL) /*!< RST3 (Bit 18) */
+#define HRPWM_COM_BMTRGR0_RST3_Msk (0x40000UL) /*!< RST3 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPA2_Pos (17UL) /*!< CMPA2 (Bit 17) */
+#define HRPWM_COM_BMTRGR0_CMPA2_Msk (0x20000UL) /*!< CMPA2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP2_Pos (16UL) /*!< REP2 (Bit 16) */
+#define HRPWM_COM_BMTRGR0_REP2_Msk (0x10000UL) /*!< REP2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_RST2_Pos (15UL) /*!< RST2 (Bit 15) */
+#define HRPWM_COM_BMTRGR0_RST2_Msk (0x8000UL) /*!< RST2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPB1_Pos (14UL) /*!< CMPB1 (Bit 14) */
+#define HRPWM_COM_BMTRGR0_CMPB1_Msk (0x4000UL) /*!< CMPB1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPA1_Pos (13UL) /*!< CMPA1 (Bit 13) */
+#define HRPWM_COM_BMTRGR0_CMPA1_Msk (0x2000UL) /*!< CMPA1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP1_Pos (12UL) /*!< REP1 (Bit 12) */
+#define HRPWM_COM_BMTRGR0_REP1_Msk (0x1000UL) /*!< REP1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_RST1_Pos (11UL) /*!< RST1 (Bit 11) */
+#define HRPWM_COM_BMTRGR0_RST1_Msk (0x800UL) /*!< RST1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPB0_Pos (10UL) /*!< CMPB0 (Bit 10) */
+#define HRPWM_COM_BMTRGR0_CMPB0_Msk (0x400UL) /*!< CMPB0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_CMPA0_Pos (9UL) /*!< CMPA0 (Bit 9) */
+#define HRPWM_COM_BMTRGR0_CMPA0_Msk (0x200UL) /*!< CMPA0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_REP0_Pos (8UL) /*!< REP0 (Bit 8) */
+#define HRPWM_COM_BMTRGR0_REP0_Msk (0x100UL) /*!< REP0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_RST0_Pos (7UL) /*!< RST0 (Bit 7) */
+#define HRPWM_COM_BMTRGR0_RST0_Msk (0x80UL) /*!< RST0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MCMPD_Pos (6UL) /*!< MCMPD (Bit 6) */
+#define HRPWM_COM_BMTRGR0_MCMPD_Msk (0x40UL) /*!< MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MCMPC_Pos (5UL) /*!< MCMPC (Bit 5) */
+#define HRPWM_COM_BMTRGR0_MCMPC_Msk (0x20UL) /*!< MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MCMPB_Pos (4UL) /*!< MCMPB (Bit 4) */
+#define HRPWM_COM_BMTRGR0_MCMPB_Msk (0x10UL) /*!< MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MCMPA_Pos (3UL) /*!< MCMPA (Bit 3) */
+#define HRPWM_COM_BMTRGR0_MCMPA_Msk (0x8UL) /*!< MCMPA (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MREP_Pos (2UL) /*!< MREP (Bit 2) */
+#define HRPWM_COM_BMTRGR0_MREP_Msk (0x4UL) /*!< MREP (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_MRST_Pos (1UL) /*!< MRST (Bit 1) */
+#define HRPWM_COM_BMTRGR0_MRST_Msk (0x2UL) /*!< MRST (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR0_SW_Pos (0UL) /*!< SW (Bit 0) */
+#define HRPWM_COM_BMTRGR0_SW_Msk (0x1UL) /*!< SW (Bitfield-Mask: 0x01) */
+/* ======================================================== BMTRGR1 ======================================================== */
+#define HRPWM_COM_BMTRGR1_CMPB7_Pos (7UL) /*!< CMPB7 (Bit 7) */
+#define HRPWM_COM_BMTRGR1_CMPB7_Msk (0x80UL) /*!< CMPB7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_CMPA7_Pos (6UL) /*!< CMPA7 (Bit 6) */
+#define HRPWM_COM_BMTRGR1_CMPA7_Msk (0x40UL) /*!< CMPA7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_REP7_Pos (5UL) /*!< REP7 (Bit 5) */
+#define HRPWM_COM_BMTRGR1_REP7_Msk (0x20UL) /*!< REP7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_RST7_Pos (4UL) /*!< RST7 (Bit 4) */
+#define HRPWM_COM_BMTRGR1_RST7_Msk (0x10UL) /*!< RST7 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_CMPB6_Pos (3UL) /*!< CMPB6 (Bit 3) */
+#define HRPWM_COM_BMTRGR1_CMPB6_Msk (0x8UL) /*!< CMPB6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_CMPA6_Pos (2UL) /*!< CMPA6 (Bit 2) */
+#define HRPWM_COM_BMTRGR1_CMPA6_Msk (0x4UL) /*!< CMPA6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_REP6_Pos (1UL) /*!< REP6 (Bit 1) */
+#define HRPWM_COM_BMTRGR1_REP6_Msk (0x2UL) /*!< REP6 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BMTRGR1_RST6_Pos (0UL) /*!< RST6 (Bit 0) */
+#define HRPWM_COM_BMTRGR1_RST6_Msk (0x1UL) /*!< RST6 (Bitfield-Mask: 0x01) */
+/* ========================================================= BMPER ========================================================= */
+#define HRPWM_COM_BMPER_BMPER_Pos (0UL) /*!< BMPER (Bit 0) */
+#define HRPWM_COM_BMPER_BMPER_Msk (0xffffUL) /*!< BMPER (Bitfield-Mask: 0xffff) */
+/* ======================================================== BMCMPR ========================================================= */
+#define HRPWM_COM_BMCMPR_BMCMP_Pos (0UL) /*!< BMCMP (Bit 0) */
+#define HRPWM_COM_BMCMPR_BMCMP_Msk (0xffffUL) /*!< BMCMP (Bitfield-Mask: 0xffff) */
+/* ======================================================== BDMUPR ========================================================= */
+#define HRPWM_COM_BDMUPR_MCMPDR_Pos (10UL) /*!< MCMPDR (Bit 10) */
+#define HRPWM_COM_BDMUPR_MCMPDR_Msk (0x400UL) /*!< MCMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCMPCR_Pos (9UL) /*!< MCMPCR (Bit 9) */
+#define HRPWM_COM_BDMUPR_MCMPCR_Msk (0x200UL) /*!< MCMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCMPBR_Pos (8UL) /*!< MCMPBR (Bit 8) */
+#define HRPWM_COM_BDMUPR_MCMPBR_Msk (0x100UL) /*!< MCMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCMPAR_Pos (7UL) /*!< MCMPAR (Bit 7) */
+#define HRPWM_COM_BDMUPR_MCMPAR_Msk (0x80UL) /*!< MCMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MREP_Pos (6UL) /*!< MREP (Bit 6) */
+#define HRPWM_COM_BDMUPR_MREP_Msk (0x40UL) /*!< MREP (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MPER_Pos (5UL) /*!< MPER (Bit 5) */
+#define HRPWM_COM_BDMUPR_MPER_Msk (0x20UL) /*!< MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCNTR_Pos (4UL) /*!< MCNTR (Bit 4) */
+#define HRPWM_COM_BDMUPR_MCNTR_Msk (0x10UL) /*!< MCNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MDIER_Pos (3UL) /*!< MDIER (Bit 3) */
+#define HRPWM_COM_BDMUPR_MDIER_Msk (0x8UL) /*!< MDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MISR_Pos (2UL) /*!< MISR (Bit 2) */
+#define HRPWM_COM_BDMUPR_MISR_Msk (0x4UL) /*!< MISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCR1_Pos (1UL) /*!< MCR1 (Bit 1) */
+#define HRPWM_COM_BDMUPR_MCR1_Msk (0x2UL) /*!< MCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDMUPR_MCR0_Pos (0UL) /*!< MCR0 (Bit 0) */
+#define HRPWM_COM_BDMUPR_MCR0_Msk (0x1UL) /*!< MCR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR0 ========================================================= */
+#define HRPWM_COM_BDUPR0_FLT0R_Pos (29UL) /*!< FLT0R (Bit 29) */
+#define HRPWM_COM_BDUPR0_FLT0R_Msk (0x20000000UL) /*!< FLT0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_OUT0R_Pos (28UL) /*!< OUT0R (Bit 28) */
+#define HRPWM_COM_BDUPR0_OUT0R_Msk (0x10000000UL) /*!< OUT0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPB0CER_Pos (27UL) /*!< CAPB0CER (Bit 27) */
+#define HRPWM_COM_BDUPR0_CAPB0CER_Msk (0x8000000UL) /*!< CAPB0CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPB0CR_Pos (26UL) /*!< CAPB0CR (Bit 26) */
+#define HRPWM_COM_BDUPR0_CAPB0CR_Msk (0x4000000UL) /*!< CAPB0CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPA0CER_Pos (25UL) /*!< CAPA0CER (Bit 25) */
+#define HRPWM_COM_BDUPR0_CAPA0CER_Msk (0x2000000UL) /*!< CAPA0CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPA0CR_Pos (24UL) /*!< CAPA0CR (Bit 24) */
+#define HRPWM_COM_BDUPR0_CAPA0CR_Msk (0x1000000UL) /*!< CAPA0CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CHP0R_Pos (23UL) /*!< CHP0R (Bit 23) */
+#define HRPWM_COM_BDUPR0_CHP0R_Msk (0x800000UL) /*!< CHP0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_RST0ER_Pos (22UL) /*!< RST0ER (Bit 22) */
+#define HRPWM_COM_BDUPR0_RST0ER_Msk (0x400000UL) /*!< RST0ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_RST0R_Pos (21UL) /*!< RST0R (Bit 21) */
+#define HRPWM_COM_BDUPR0_RST0R_Msk (0x200000UL) /*!< RST0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_EEF0R2_Pos (20UL) /*!< EEF0R2 (Bit 20) */
+#define HRPWM_COM_BDUPR0_EEF0R2_Msk (0x100000UL) /*!< EEF0R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_EEF0R1_Pos (19UL) /*!< EEF0R1 (Bit 19) */
+#define HRPWM_COM_BDUPR0_EEF0R1_Msk (0x80000UL) /*!< EEF0R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_EEF0R0_Pos (18UL) /*!< EEF0R0 (Bit 18) */
+#define HRPWM_COM_BDUPR0_EEF0R0_Msk (0x40000UL) /*!< EEF0R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CLR0BR_Pos (17UL) /*!< CLR0BR (Bit 17) */
+#define HRPWM_COM_BDUPR0_CLR0BR_Msk (0x20000UL) /*!< CLR0BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_SET0BR_Pos (16UL) /*!< SET0BR (Bit 16) */
+#define HRPWM_COM_BDUPR0_SET0BR_Msk (0x10000UL) /*!< SET0BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CLR0AR_Pos (15UL) /*!< CLR0AR (Bit 15) */
+#define HRPWM_COM_BDUPR0_CLR0AR_Msk (0x8000UL) /*!< CLR0AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_SET0AR_Pos (14UL) /*!< SET0AR (Bit 14) */
+#define HRPWM_COM_BDUPR0_SET0AR_Msk (0x4000UL) /*!< SET0AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_DT0R_Pos (13UL) /*!< DT0R (Bit 13) */
+#define HRPWM_COM_BDUPR0_DT0R_Msk (0x2000UL) /*!< DT0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPB0R_Pos (12UL) /*!< CAPB0R (Bit 12) */
+#define HRPWM_COM_BDUPR0_CAPB0R_Msk (0x1000UL) /*!< CAPB0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CAPA0R_Pos (11UL) /*!< CAPA0R (Bit 11) */
+#define HRPWM_COM_BDUPR0_CAPA0R_Msk (0x800UL) /*!< CAPA0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CMPD0R_Pos (10UL) /*!< CMPD0R (Bit 10) */
+#define HRPWM_COM_BDUPR0_CMPD0R_Msk (0x400UL) /*!< CMPD0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CMPC0R_Pos (9UL) /*!< CMPC0R (Bit 9) */
+#define HRPWM_COM_BDUPR0_CMPC0R_Msk (0x200UL) /*!< CMPC0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CMPB0R_Pos (8UL) /*!< CMPB0R (Bit 8) */
+#define HRPWM_COM_BDUPR0_CMPB0R_Msk (0x100UL) /*!< CMPB0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CMPA0R_Pos (7UL) /*!< CMPA0R (Bit 7) */
+#define HRPWM_COM_BDUPR0_CMPA0R_Msk (0x80UL) /*!< CMPA0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_REP0R_Pos (6UL) /*!< REP0R (Bit 6) */
+#define HRPWM_COM_BDUPR0_REP0R_Msk (0x40UL) /*!< REP0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_PER0R_Pos (5UL) /*!< PER0R (Bit 5) */
+#define HRPWM_COM_BDUPR0_PER0R_Msk (0x20UL) /*!< PER0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_CNT0R_Pos (4UL) /*!< CNT0R (Bit 4) */
+#define HRPWM_COM_BDUPR0_CNT0R_Msk (0x10UL) /*!< CNT0R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_PWM0DIER_Pos (3UL) /*!< PWM0DIER (Bit 3) */
+#define HRPWM_COM_BDUPR0_PWM0DIER_Msk (0x8UL) /*!< PWM0DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_PWM0ISR_Pos (2UL) /*!< PWM0ISR (Bit 2) */
+#define HRPWM_COM_BDUPR0_PWM0ISR_Msk (0x4UL) /*!< PWM0ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_PWM0CR1_Pos (1UL) /*!< PWM0CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR0_PWM0CR1_Msk (0x2UL) /*!< PWM0CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR0_PWM0CR0_Pos (0UL) /*!< PWM0CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR0_PWM0CR0_Msk (0x1UL) /*!< PWM0CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR1 ========================================================= */
+#define HRPWM_COM_BDUPR1_FLT1R_Pos (29UL) /*!< FLT1R (Bit 29) */
+#define HRPWM_COM_BDUPR1_FLT1R_Msk (0x20000000UL) /*!< FLT1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_OUT1R_Pos (28UL) /*!< OUT1R (Bit 28) */
+#define HRPWM_COM_BDUPR1_OUT1R_Msk (0x10000000UL) /*!< OUT1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPB1CER_Pos (27UL) /*!< CAPB1CER (Bit 27) */
+#define HRPWM_COM_BDUPR1_CAPB1CER_Msk (0x8000000UL) /*!< CAPB1CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPB1CR_Pos (26UL) /*!< CAPB1CR (Bit 26) */
+#define HRPWM_COM_BDUPR1_CAPB1CR_Msk (0x4000000UL) /*!< CAPB1CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPA1CER_Pos (25UL) /*!< CAPA1CER (Bit 25) */
+#define HRPWM_COM_BDUPR1_CAPA1CER_Msk (0x2000000UL) /*!< CAPA1CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPA1CR_Pos (24UL) /*!< CAPA1CR (Bit 24) */
+#define HRPWM_COM_BDUPR1_CAPA1CR_Msk (0x1000000UL) /*!< CAPA1CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CHP1R_Pos (23UL) /*!< CHP1R (Bit 23) */
+#define HRPWM_COM_BDUPR1_CHP1R_Msk (0x800000UL) /*!< CHP1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_RST1ER_Pos (22UL) /*!< RST1ER (Bit 22) */
+#define HRPWM_COM_BDUPR1_RST1ER_Msk (0x400000UL) /*!< RST1ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_RST1R_Pos (21UL) /*!< RST1R (Bit 21) */
+#define HRPWM_COM_BDUPR1_RST1R_Msk (0x200000UL) /*!< RST1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_EEF1R2_Pos (20UL) /*!< EEF1R2 (Bit 20) */
+#define HRPWM_COM_BDUPR1_EEF1R2_Msk (0x100000UL) /*!< EEF1R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_EEF1R1_Pos (19UL) /*!< EEF1R1 (Bit 19) */
+#define HRPWM_COM_BDUPR1_EEF1R1_Msk (0x80000UL) /*!< EEF1R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_EEF1R0_Pos (18UL) /*!< EEF1R0 (Bit 18) */
+#define HRPWM_COM_BDUPR1_EEF1R0_Msk (0x40000UL) /*!< EEF1R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CLR1BR_Pos (17UL) /*!< CLR1BR (Bit 17) */
+#define HRPWM_COM_BDUPR1_CLR1BR_Msk (0x20000UL) /*!< CLR1BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_SET1BR_Pos (16UL) /*!< SET1BR (Bit 16) */
+#define HRPWM_COM_BDUPR1_SET1BR_Msk (0x10000UL) /*!< SET1BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CLR1AR_Pos (15UL) /*!< CLR1AR (Bit 15) */
+#define HRPWM_COM_BDUPR1_CLR1AR_Msk (0x8000UL) /*!< CLR1AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_SET1AR_Pos (14UL) /*!< SET1AR (Bit 14) */
+#define HRPWM_COM_BDUPR1_SET1AR_Msk (0x4000UL) /*!< SET1AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_DT1R_Pos (13UL) /*!< DT1R (Bit 13) */
+#define HRPWM_COM_BDUPR1_DT1R_Msk (0x2000UL) /*!< DT1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPB1R_Pos (12UL) /*!< CAPB1R (Bit 12) */
+#define HRPWM_COM_BDUPR1_CAPB1R_Msk (0x1000UL) /*!< CAPB1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CAPA1R_Pos (11UL) /*!< CAPA1R (Bit 11) */
+#define HRPWM_COM_BDUPR1_CAPA1R_Msk (0x800UL) /*!< CAPA1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CMPD1R_Pos (10UL) /*!< CMPD1R (Bit 10) */
+#define HRPWM_COM_BDUPR1_CMPD1R_Msk (0x400UL) /*!< CMPD1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CMPC1R_Pos (9UL) /*!< CMPC1R (Bit 9) */
+#define HRPWM_COM_BDUPR1_CMPC1R_Msk (0x200UL) /*!< CMPC1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CMPB1R_Pos (8UL) /*!< CMPB1R (Bit 8) */
+#define HRPWM_COM_BDUPR1_CMPB1R_Msk (0x100UL) /*!< CMPB1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CMPA1R_Pos (7UL) /*!< CMPA1R (Bit 7) */
+#define HRPWM_COM_BDUPR1_CMPA1R_Msk (0x80UL) /*!< CMPA1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_REP1R_Pos (6UL) /*!< REP1R (Bit 6) */
+#define HRPWM_COM_BDUPR1_REP1R_Msk (0x40UL) /*!< REP1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_PER1R_Pos (5UL) /*!< PER1R (Bit 5) */
+#define HRPWM_COM_BDUPR1_PER1R_Msk (0x20UL) /*!< PER1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_CNT1R_Pos (4UL) /*!< CNT1R (Bit 4) */
+#define HRPWM_COM_BDUPR1_CNT1R_Msk (0x10UL) /*!< CNT1R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_PWM1DIER_Pos (3UL) /*!< PWM1DIER (Bit 3) */
+#define HRPWM_COM_BDUPR1_PWM1DIER_Msk (0x8UL) /*!< PWM1DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_PWM1ISR_Pos (2UL) /*!< PWM1ISR (Bit 2) */
+#define HRPWM_COM_BDUPR1_PWM1ISR_Msk (0x4UL) /*!< PWM1ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_PWM1CR1_Pos (1UL) /*!< PWM1CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR1_PWM1CR1_Msk (0x2UL) /*!< PWM1CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR1_PWM1CR0_Pos (0UL) /*!< PWM1CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR1_PWM1CR0_Msk (0x1UL) /*!< PWM1CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR2 ========================================================= */
+#define HRPWM_COM_BDUPR2_FLT2R_Pos (29UL) /*!< FLT2R (Bit 29) */
+#define HRPWM_COM_BDUPR2_FLT2R_Msk (0x20000000UL) /*!< FLT2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_OUT2R_Pos (28UL) /*!< OUT2R (Bit 28) */
+#define HRPWM_COM_BDUPR2_OUT2R_Msk (0x10000000UL) /*!< OUT2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPB2CER_Pos (27UL) /*!< CAPB2CER (Bit 27) */
+#define HRPWM_COM_BDUPR2_CAPB2CER_Msk (0x8000000UL) /*!< CAPB2CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPB2CR_Pos (26UL) /*!< CAPB2CR (Bit 26) */
+#define HRPWM_COM_BDUPR2_CAPB2CR_Msk (0x4000000UL) /*!< CAPB2CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPA2CER_Pos (25UL) /*!< CAPA2CER (Bit 25) */
+#define HRPWM_COM_BDUPR2_CAPA2CER_Msk (0x2000000UL) /*!< CAPA2CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPA2CR_Pos (24UL) /*!< CAPA2CR (Bit 24) */
+#define HRPWM_COM_BDUPR2_CAPA2CR_Msk (0x1000000UL) /*!< CAPA2CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CHP2R_Pos (23UL) /*!< CHP2R (Bit 23) */
+#define HRPWM_COM_BDUPR2_CHP2R_Msk (0x800000UL) /*!< CHP2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_RST2ER_Pos (22UL) /*!< RST2ER (Bit 22) */
+#define HRPWM_COM_BDUPR2_RST2ER_Msk (0x400000UL) /*!< RST2ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_RST2R_Pos (21UL) /*!< RST2R (Bit 21) */
+#define HRPWM_COM_BDUPR2_RST2R_Msk (0x200000UL) /*!< RST2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_EEF2R2_Pos (20UL) /*!< EEF2R2 (Bit 20) */
+#define HRPWM_COM_BDUPR2_EEF2R2_Msk (0x100000UL) /*!< EEF2R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_EEF2R1_Pos (19UL) /*!< EEF2R1 (Bit 19) */
+#define HRPWM_COM_BDUPR2_EEF2R1_Msk (0x80000UL) /*!< EEF2R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_EEF2R0_Pos (18UL) /*!< EEF2R0 (Bit 18) */
+#define HRPWM_COM_BDUPR2_EEF2R0_Msk (0x40000UL) /*!< EEF2R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CLR2BR_Pos (17UL) /*!< CLR2BR (Bit 17) */
+#define HRPWM_COM_BDUPR2_CLR2BR_Msk (0x20000UL) /*!< CLR2BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_SET2BR_Pos (16UL) /*!< SET2BR (Bit 16) */
+#define HRPWM_COM_BDUPR2_SET2BR_Msk (0x10000UL) /*!< SET2BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CLR2AR_Pos (15UL) /*!< CLR2AR (Bit 15) */
+#define HRPWM_COM_BDUPR2_CLR2AR_Msk (0x8000UL) /*!< CLR2AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_SET2AR_Pos (14UL) /*!< SET2AR (Bit 14) */
+#define HRPWM_COM_BDUPR2_SET2AR_Msk (0x4000UL) /*!< SET2AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_DT2R_Pos (13UL) /*!< DT2R (Bit 13) */
+#define HRPWM_COM_BDUPR2_DT2R_Msk (0x2000UL) /*!< DT2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPB2R_Pos (12UL) /*!< CAPB2R (Bit 12) */
+#define HRPWM_COM_BDUPR2_CAPB2R_Msk (0x1000UL) /*!< CAPB2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CAPA2R_Pos (11UL) /*!< CAPA2R (Bit 11) */
+#define HRPWM_COM_BDUPR2_CAPA2R_Msk (0x800UL) /*!< CAPA2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CMPD2R_Pos (10UL) /*!< CMPD2R (Bit 10) */
+#define HRPWM_COM_BDUPR2_CMPD2R_Msk (0x400UL) /*!< CMPD2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CMPC2R_Pos (9UL) /*!< CMPC2R (Bit 9) */
+#define HRPWM_COM_BDUPR2_CMPC2R_Msk (0x200UL) /*!< CMPC2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CMPB2R_Pos (8UL) /*!< CMPB2R (Bit 8) */
+#define HRPWM_COM_BDUPR2_CMPB2R_Msk (0x100UL) /*!< CMPB2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CMPA2R_Pos (7UL) /*!< CMPA2R (Bit 7) */
+#define HRPWM_COM_BDUPR2_CMPA2R_Msk (0x80UL) /*!< CMPA2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_REP2R_Pos (6UL) /*!< REP2R (Bit 6) */
+#define HRPWM_COM_BDUPR2_REP2R_Msk (0x40UL) /*!< REP2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_PER2R_Pos (5UL) /*!< PER2R (Bit 5) */
+#define HRPWM_COM_BDUPR2_PER2R_Msk (0x20UL) /*!< PER2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_CNT2R_Pos (4UL) /*!< CNT2R (Bit 4) */
+#define HRPWM_COM_BDUPR2_CNT2R_Msk (0x10UL) /*!< CNT2R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_PWM2DIER_Pos (3UL) /*!< PWM2DIER (Bit 3) */
+#define HRPWM_COM_BDUPR2_PWM2DIER_Msk (0x8UL) /*!< PWM2DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_PWM2ISR_Pos (2UL) /*!< PWM2ISR (Bit 2) */
+#define HRPWM_COM_BDUPR2_PWM2ISR_Msk (0x4UL) /*!< PWM2ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_PWM2CR1_Pos (1UL) /*!< PWM2CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR2_PWM2CR1_Msk (0x2UL) /*!< PWM2CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR2_PWM2CR0_Pos (0UL) /*!< PWM2CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR2_PWM2CR0_Msk (0x1UL) /*!< PWM2CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR3 ========================================================= */
+#define HRPWM_COM_BDUPR3_FLT3R_Pos (29UL) /*!< FLT3R (Bit 29) */
+#define HRPWM_COM_BDUPR3_FLT3R_Msk (0x20000000UL) /*!< FLT3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_OUT3R_Pos (28UL) /*!< OUT3R (Bit 28) */
+#define HRPWM_COM_BDUPR3_OUT3R_Msk (0x10000000UL) /*!< OUT3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPB3CER_Pos (27UL) /*!< CAPB3CER (Bit 27) */
+#define HRPWM_COM_BDUPR3_CAPB3CER_Msk (0x8000000UL) /*!< CAPB3CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPB3CR_Pos (26UL) /*!< CAPB3CR (Bit 26) */
+#define HRPWM_COM_BDUPR3_CAPB3CR_Msk (0x4000000UL) /*!< CAPB3CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPA3CER_Pos (25UL) /*!< CAPA3CER (Bit 25) */
+#define HRPWM_COM_BDUPR3_CAPA3CER_Msk (0x2000000UL) /*!< CAPA3CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPA3CR_Pos (24UL) /*!< CAPA3CR (Bit 24) */
+#define HRPWM_COM_BDUPR3_CAPA3CR_Msk (0x1000000UL) /*!< CAPA3CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CHP3R_Pos (23UL) /*!< CHP3R (Bit 23) */
+#define HRPWM_COM_BDUPR3_CHP3R_Msk (0x800000UL) /*!< CHP3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_RST3ER_Pos (22UL) /*!< RST3ER (Bit 22) */
+#define HRPWM_COM_BDUPR3_RST3ER_Msk (0x400000UL) /*!< RST3ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_RST3R_Pos (21UL) /*!< RST3R (Bit 21) */
+#define HRPWM_COM_BDUPR3_RST3R_Msk (0x200000UL) /*!< RST3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_EEF3R2_Pos (20UL) /*!< EEF3R2 (Bit 20) */
+#define HRPWM_COM_BDUPR3_EEF3R2_Msk (0x100000UL) /*!< EEF3R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_EEF3R1_Pos (19UL) /*!< EEF3R1 (Bit 19) */
+#define HRPWM_COM_BDUPR3_EEF3R1_Msk (0x80000UL) /*!< EEF3R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_EEF3R0_Pos (18UL) /*!< EEF3R0 (Bit 18) */
+#define HRPWM_COM_BDUPR3_EEF3R0_Msk (0x40000UL) /*!< EEF3R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CLR3BR_Pos (17UL) /*!< CLR3BR (Bit 17) */
+#define HRPWM_COM_BDUPR3_CLR3BR_Msk (0x20000UL) /*!< CLR3BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_SET3BR_Pos (16UL) /*!< SET3BR (Bit 16) */
+#define HRPWM_COM_BDUPR3_SET3BR_Msk (0x10000UL) /*!< SET3BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CLR3AR_Pos (15UL) /*!< CLR3AR (Bit 15) */
+#define HRPWM_COM_BDUPR3_CLR3AR_Msk (0x8000UL) /*!< CLR3AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_SET3AR_Pos (14UL) /*!< SET3AR (Bit 14) */
+#define HRPWM_COM_BDUPR3_SET3AR_Msk (0x4000UL) /*!< SET3AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_DT3R_Pos (13UL) /*!< DT3R (Bit 13) */
+#define HRPWM_COM_BDUPR3_DT3R_Msk (0x2000UL) /*!< DT3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPB3R_Pos (12UL) /*!< CAPB3R (Bit 12) */
+#define HRPWM_COM_BDUPR3_CAPB3R_Msk (0x1000UL) /*!< CAPB3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CAPA3R_Pos (11UL) /*!< CAPA3R (Bit 11) */
+#define HRPWM_COM_BDUPR3_CAPA3R_Msk (0x800UL) /*!< CAPA3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CMPD3R_Pos (10UL) /*!< CMPD3R (Bit 10) */
+#define HRPWM_COM_BDUPR3_CMPD3R_Msk (0x400UL) /*!< CMPD3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CMPC3R_Pos (9UL) /*!< CMPC3R (Bit 9) */
+#define HRPWM_COM_BDUPR3_CMPC3R_Msk (0x200UL) /*!< CMPC3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CMPB3R_Pos (8UL) /*!< CMPB3R (Bit 8) */
+#define HRPWM_COM_BDUPR3_CMPB3R_Msk (0x100UL) /*!< CMPB3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CMPA3R_Pos (7UL) /*!< CMPA3R (Bit 7) */
+#define HRPWM_COM_BDUPR3_CMPA3R_Msk (0x80UL) /*!< CMPA3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_REP3R_Pos (6UL) /*!< REP3R (Bit 6) */
+#define HRPWM_COM_BDUPR3_REP3R_Msk (0x40UL) /*!< REP3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_PER3R_Pos (5UL) /*!< PER3R (Bit 5) */
+#define HRPWM_COM_BDUPR3_PER3R_Msk (0x20UL) /*!< PER3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_CNT3R_Pos (4UL) /*!< CNT3R (Bit 4) */
+#define HRPWM_COM_BDUPR3_CNT3R_Msk (0x10UL) /*!< CNT3R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_PWM3DIER_Pos (3UL) /*!< PWM3DIER (Bit 3) */
+#define HRPWM_COM_BDUPR3_PWM3DIER_Msk (0x8UL) /*!< PWM3DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_PWM3ISR_Pos (2UL) /*!< PWM3ISR (Bit 2) */
+#define HRPWM_COM_BDUPR3_PWM3ISR_Msk (0x4UL) /*!< PWM3ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_PWM3CR1_Pos (1UL) /*!< PWM3CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR3_PWM3CR1_Msk (0x2UL) /*!< PWM3CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR3_PWM3CR0_Pos (0UL) /*!< PWM3CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR3_PWM3CR0_Msk (0x1UL) /*!< PWM3CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR4 ========================================================= */
+#define HRPWM_COM_BDUPR4_FLT4R_Pos (29UL) /*!< FLT4R (Bit 29) */
+#define HRPWM_COM_BDUPR4_FLT4R_Msk (0x20000000UL) /*!< FLT4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_OUT4R_Pos (28UL) /*!< OUT4R (Bit 28) */
+#define HRPWM_COM_BDUPR4_OUT4R_Msk (0x10000000UL) /*!< OUT4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPB4CER_Pos (27UL) /*!< CAPB4CER (Bit 27) */
+#define HRPWM_COM_BDUPR4_CAPB4CER_Msk (0x8000000UL) /*!< CAPB4CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPB4CR_Pos (26UL) /*!< CAPB4CR (Bit 26) */
+#define HRPWM_COM_BDUPR4_CAPB4CR_Msk (0x4000000UL) /*!< CAPB4CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPA4CER_Pos (25UL) /*!< CAPA4CER (Bit 25) */
+#define HRPWM_COM_BDUPR4_CAPA4CER_Msk (0x2000000UL) /*!< CAPA4CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPA4CR_Pos (24UL) /*!< CAPA4CR (Bit 24) */
+#define HRPWM_COM_BDUPR4_CAPA4CR_Msk (0x1000000UL) /*!< CAPA4CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CHP4R_Pos (23UL) /*!< CHP4R (Bit 23) */
+#define HRPWM_COM_BDUPR4_CHP4R_Msk (0x800000UL) /*!< CHP4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_RST4ER_Pos (22UL) /*!< RST4ER (Bit 22) */
+#define HRPWM_COM_BDUPR4_RST4ER_Msk (0x400000UL) /*!< RST4ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_RST4R_Pos (21UL) /*!< RST4R (Bit 21) */
+#define HRPWM_COM_BDUPR4_RST4R_Msk (0x200000UL) /*!< RST4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_EEF4R2_Pos (20UL) /*!< EEF4R2 (Bit 20) */
+#define HRPWM_COM_BDUPR4_EEF4R2_Msk (0x100000UL) /*!< EEF4R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_EEF4R1_Pos (19UL) /*!< EEF4R1 (Bit 19) */
+#define HRPWM_COM_BDUPR4_EEF4R1_Msk (0x80000UL) /*!< EEF4R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_EEF4R0_Pos (18UL) /*!< EEF4R0 (Bit 18) */
+#define HRPWM_COM_BDUPR4_EEF4R0_Msk (0x40000UL) /*!< EEF4R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CLR4BR_Pos (17UL) /*!< CLR4BR (Bit 17) */
+#define HRPWM_COM_BDUPR4_CLR4BR_Msk (0x20000UL) /*!< CLR4BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_SET4BR_Pos (16UL) /*!< SET4BR (Bit 16) */
+#define HRPWM_COM_BDUPR4_SET4BR_Msk (0x10000UL) /*!< SET4BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CLR4AR_Pos (15UL) /*!< CLR4AR (Bit 15) */
+#define HRPWM_COM_BDUPR4_CLR4AR_Msk (0x8000UL) /*!< CLR4AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_SET4AR_Pos (14UL) /*!< SET4AR (Bit 14) */
+#define HRPWM_COM_BDUPR4_SET4AR_Msk (0x4000UL) /*!< SET4AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_DT4R_Pos (13UL) /*!< DT4R (Bit 13) */
+#define HRPWM_COM_BDUPR4_DT4R_Msk (0x2000UL) /*!< DT4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPB4R_Pos (12UL) /*!< CAPB4R (Bit 12) */
+#define HRPWM_COM_BDUPR4_CAPB4R_Msk (0x1000UL) /*!< CAPB4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CAPA4R_Pos (11UL) /*!< CAPA4R (Bit 11) */
+#define HRPWM_COM_BDUPR4_CAPA4R_Msk (0x800UL) /*!< CAPA4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CMPD4R_Pos (10UL) /*!< CMPD4R (Bit 10) */
+#define HRPWM_COM_BDUPR4_CMPD4R_Msk (0x400UL) /*!< CMPD4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CMPC4R_Pos (9UL) /*!< CMPC4R (Bit 9) */
+#define HRPWM_COM_BDUPR4_CMPC4R_Msk (0x200UL) /*!< CMPC4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CMPB4R_Pos (8UL) /*!< CMPB4R (Bit 8) */
+#define HRPWM_COM_BDUPR4_CMPB4R_Msk (0x100UL) /*!< CMPB4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CMPA4R_Pos (7UL) /*!< CMPA4R (Bit 7) */
+#define HRPWM_COM_BDUPR4_CMPA4R_Msk (0x80UL) /*!< CMPA4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_REP4R_Pos (6UL) /*!< REP4R (Bit 6) */
+#define HRPWM_COM_BDUPR4_REP4R_Msk (0x40UL) /*!< REP4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_PER4R_Pos (5UL) /*!< PER4R (Bit 5) */
+#define HRPWM_COM_BDUPR4_PER4R_Msk (0x20UL) /*!< PER4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_CNT4R_Pos (4UL) /*!< CNT4R (Bit 4) */
+#define HRPWM_COM_BDUPR4_CNT4R_Msk (0x10UL) /*!< CNT4R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_PWM4DIER_Pos (3UL) /*!< PWM4DIER (Bit 3) */
+#define HRPWM_COM_BDUPR4_PWM4DIER_Msk (0x8UL) /*!< PWM4DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_PWM4ISR_Pos (2UL) /*!< PWM4ISR (Bit 2) */
+#define HRPWM_COM_BDUPR4_PWM4ISR_Msk (0x4UL) /*!< PWM4ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_PWM4CR1_Pos (1UL) /*!< PWM4CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR4_PWM4CR1_Msk (0x2UL) /*!< PWM4CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR4_PWM4CR0_Pos (0UL) /*!< PWM4CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR4_PWM4CR0_Msk (0x1UL) /*!< PWM4CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR5 ========================================================= */
+#define HRPWM_COM_BDUPR5_FLT5R_Pos (29UL) /*!< FLT5R (Bit 29) */
+#define HRPWM_COM_BDUPR5_FLT5R_Msk (0x20000000UL) /*!< FLT5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_OUT5R_Pos (28UL) /*!< OUT5R (Bit 28) */
+#define HRPWM_COM_BDUPR5_OUT5R_Msk (0x10000000UL) /*!< OUT5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPB5CER_Pos (27UL) /*!< CAPB5CER (Bit 27) */
+#define HRPWM_COM_BDUPR5_CAPB5CER_Msk (0x8000000UL) /*!< CAPB5CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPB5CR_Pos (26UL) /*!< CAPB5CR (Bit 26) */
+#define HRPWM_COM_BDUPR5_CAPB5CR_Msk (0x4000000UL) /*!< CAPB5CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPA5CER_Pos (25UL) /*!< CAPA5CER (Bit 25) */
+#define HRPWM_COM_BDUPR5_CAPA5CER_Msk (0x2000000UL) /*!< CAPA5CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPA5CR_Pos (24UL) /*!< CAPA5CR (Bit 24) */
+#define HRPWM_COM_BDUPR5_CAPA5CR_Msk (0x1000000UL) /*!< CAPA5CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CHP5R_Pos (23UL) /*!< CHP5R (Bit 23) */
+#define HRPWM_COM_BDUPR5_CHP5R_Msk (0x800000UL) /*!< CHP5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_RST5ER_Pos (22UL) /*!< RST5ER (Bit 22) */
+#define HRPWM_COM_BDUPR5_RST5ER_Msk (0x400000UL) /*!< RST5ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_RST5R_Pos (21UL) /*!< RST5R (Bit 21) */
+#define HRPWM_COM_BDUPR5_RST5R_Msk (0x200000UL) /*!< RST5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_EEF5R2_Pos (20UL) /*!< EEF5R2 (Bit 20) */
+#define HRPWM_COM_BDUPR5_EEF5R2_Msk (0x100000UL) /*!< EEF5R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_EEF5R1_Pos (19UL) /*!< EEF5R1 (Bit 19) */
+#define HRPWM_COM_BDUPR5_EEF5R1_Msk (0x80000UL) /*!< EEF5R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_EEF5R0_Pos (18UL) /*!< EEF5R0 (Bit 18) */
+#define HRPWM_COM_BDUPR5_EEF5R0_Msk (0x40000UL) /*!< EEF5R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CLR5BR_Pos (17UL) /*!< CLR5BR (Bit 17) */
+#define HRPWM_COM_BDUPR5_CLR5BR_Msk (0x20000UL) /*!< CLR5BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_SET5BR_Pos (16UL) /*!< SET5BR (Bit 16) */
+#define HRPWM_COM_BDUPR5_SET5BR_Msk (0x10000UL) /*!< SET5BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CLR5AR_Pos (15UL) /*!< CLR5AR (Bit 15) */
+#define HRPWM_COM_BDUPR5_CLR5AR_Msk (0x8000UL) /*!< CLR5AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_SET5AR_Pos (14UL) /*!< SET5AR (Bit 14) */
+#define HRPWM_COM_BDUPR5_SET5AR_Msk (0x4000UL) /*!< SET5AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_DT5R_Pos (13UL) /*!< DT5R (Bit 13) */
+#define HRPWM_COM_BDUPR5_DT5R_Msk (0x2000UL) /*!< DT5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPB5R_Pos (12UL) /*!< CAPB5R (Bit 12) */
+#define HRPWM_COM_BDUPR5_CAPB5R_Msk (0x1000UL) /*!< CAPB5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CAPA5R_Pos (11UL) /*!< CAPA5R (Bit 11) */
+#define HRPWM_COM_BDUPR5_CAPA5R_Msk (0x800UL) /*!< CAPA5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CMPD5R_Pos (10UL) /*!< CMPD5R (Bit 10) */
+#define HRPWM_COM_BDUPR5_CMPD5R_Msk (0x400UL) /*!< CMPD5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CMPC5R_Pos (9UL) /*!< CMPC5R (Bit 9) */
+#define HRPWM_COM_BDUPR5_CMPC5R_Msk (0x200UL) /*!< CMPC5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CMPB5R_Pos (8UL) /*!< CMPB5R (Bit 8) */
+#define HRPWM_COM_BDUPR5_CMPB5R_Msk (0x100UL) /*!< CMPB5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CMPA5R_Pos (7UL) /*!< CMPA5R (Bit 7) */
+#define HRPWM_COM_BDUPR5_CMPA5R_Msk (0x80UL) /*!< CMPA5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_REP5R_Pos (6UL) /*!< REP5R (Bit 6) */
+#define HRPWM_COM_BDUPR5_REP5R_Msk (0x40UL) /*!< REP5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_PER5R_Pos (5UL) /*!< PER5R (Bit 5) */
+#define HRPWM_COM_BDUPR5_PER5R_Msk (0x20UL) /*!< PER5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_CNT5R_Pos (4UL) /*!< CNT5R (Bit 4) */
+#define HRPWM_COM_BDUPR5_CNT5R_Msk (0x10UL) /*!< CNT5R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_PWM5DIER_Pos (3UL) /*!< PWM5DIER (Bit 3) */
+#define HRPWM_COM_BDUPR5_PWM5DIER_Msk (0x8UL) /*!< PWM5DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_PWM5ISR_Pos (2UL) /*!< PWM5ISR (Bit 2) */
+#define HRPWM_COM_BDUPR5_PWM5ISR_Msk (0x4UL) /*!< PWM5ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_PWM5CR1_Pos (1UL) /*!< PWM5CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR5_PWM5CR1_Msk (0x2UL) /*!< PWM5CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR5_PWM5CR0_Pos (0UL) /*!< PWM5CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR5_PWM5CR0_Msk (0x1UL) /*!< PWM5CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR6 ========================================================= */
+#define HRPWM_COM_BDUPR6_FLT6R_Pos (29UL) /*!< FLT6R (Bit 29) */
+#define HRPWM_COM_BDUPR6_FLT6R_Msk (0x20000000UL) /*!< FLT6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_OUT6R_Pos (28UL) /*!< OUT6R (Bit 28) */
+#define HRPWM_COM_BDUPR6_OUT6R_Msk (0x10000000UL) /*!< OUT6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPB6CER_Pos (27UL) /*!< CAPB6CER (Bit 27) */
+#define HRPWM_COM_BDUPR6_CAPB6CER_Msk (0x8000000UL) /*!< CAPB6CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPB6CR_Pos (26UL) /*!< CAPB6CR (Bit 26) */
+#define HRPWM_COM_BDUPR6_CAPB6CR_Msk (0x4000000UL) /*!< CAPB6CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPA6CER_Pos (25UL) /*!< CAPA6CER (Bit 25) */
+#define HRPWM_COM_BDUPR6_CAPA6CER_Msk (0x2000000UL) /*!< CAPA6CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPA6CR_Pos (24UL) /*!< CAPA6CR (Bit 24) */
+#define HRPWM_COM_BDUPR6_CAPA6CR_Msk (0x1000000UL) /*!< CAPA6CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CHP6R_Pos (23UL) /*!< CHP6R (Bit 23) */
+#define HRPWM_COM_BDUPR6_CHP6R_Msk (0x800000UL) /*!< CHP6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_RST6ER_Pos (22UL) /*!< RST6ER (Bit 22) */
+#define HRPWM_COM_BDUPR6_RST6ER_Msk (0x400000UL) /*!< RST6ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_RST6R_Pos (21UL) /*!< RST6R (Bit 21) */
+#define HRPWM_COM_BDUPR6_RST6R_Msk (0x200000UL) /*!< RST6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_EEF6R2_Pos (20UL) /*!< EEF6R2 (Bit 20) */
+#define HRPWM_COM_BDUPR6_EEF6R2_Msk (0x100000UL) /*!< EEF6R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_EEF6R1_Pos (19UL) /*!< EEF6R1 (Bit 19) */
+#define HRPWM_COM_BDUPR6_EEF6R1_Msk (0x80000UL) /*!< EEF6R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_EEF6R0_Pos (18UL) /*!< EEF6R0 (Bit 18) */
+#define HRPWM_COM_BDUPR6_EEF6R0_Msk (0x40000UL) /*!< EEF6R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CLR6BR_Pos (17UL) /*!< CLR6BR (Bit 17) */
+#define HRPWM_COM_BDUPR6_CLR6BR_Msk (0x20000UL) /*!< CLR6BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_SET6BR_Pos (16UL) /*!< SET6BR (Bit 16) */
+#define HRPWM_COM_BDUPR6_SET6BR_Msk (0x10000UL) /*!< SET6BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CLR6AR_Pos (15UL) /*!< CLR6AR (Bit 15) */
+#define HRPWM_COM_BDUPR6_CLR6AR_Msk (0x8000UL) /*!< CLR6AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_SET6AR_Pos (14UL) /*!< SET6AR (Bit 14) */
+#define HRPWM_COM_BDUPR6_SET6AR_Msk (0x4000UL) /*!< SET6AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_DT6R_Pos (13UL) /*!< DT6R (Bit 13) */
+#define HRPWM_COM_BDUPR6_DT6R_Msk (0x2000UL) /*!< DT6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPB6R_Pos (12UL) /*!< CAPB6R (Bit 12) */
+#define HRPWM_COM_BDUPR6_CAPB6R_Msk (0x1000UL) /*!< CAPB6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CAPA6R_Pos (11UL) /*!< CAPA6R (Bit 11) */
+#define HRPWM_COM_BDUPR6_CAPA6R_Msk (0x800UL) /*!< CAPA6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CMPD6R_Pos (10UL) /*!< CMPD6R (Bit 10) */
+#define HRPWM_COM_BDUPR6_CMPD6R_Msk (0x400UL) /*!< CMPD6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CMPC6R_Pos (9UL) /*!< CMPC6R (Bit 9) */
+#define HRPWM_COM_BDUPR6_CMPC6R_Msk (0x200UL) /*!< CMPC6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CMPB6R_Pos (8UL) /*!< CMPB6R (Bit 8) */
+#define HRPWM_COM_BDUPR6_CMPB6R_Msk (0x100UL) /*!< CMPB6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CMPA6R_Pos (7UL) /*!< CMPA6R (Bit 7) */
+#define HRPWM_COM_BDUPR6_CMPA6R_Msk (0x80UL) /*!< CMPA6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_REP6R_Pos (6UL) /*!< REP6R (Bit 6) */
+#define HRPWM_COM_BDUPR6_REP6R_Msk (0x40UL) /*!< REP6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_PER6R_Pos (5UL) /*!< PER6R (Bit 5) */
+#define HRPWM_COM_BDUPR6_PER6R_Msk (0x20UL) /*!< PER6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_CNT6R_Pos (4UL) /*!< CNT6R (Bit 4) */
+#define HRPWM_COM_BDUPR6_CNT6R_Msk (0x10UL) /*!< CNT6R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_PWM6DIER_Pos (3UL) /*!< PWM6DIER (Bit 3) */
+#define HRPWM_COM_BDUPR6_PWM6DIER_Msk (0x8UL) /*!< PWM6DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_PWM6ISR_Pos (2UL) /*!< PWM6ISR (Bit 2) */
+#define HRPWM_COM_BDUPR6_PWM6ISR_Msk (0x4UL) /*!< PWM6ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_PWM6CR1_Pos (1UL) /*!< PWM6CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR6_PWM6CR1_Msk (0x2UL) /*!< PWM6CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR6_PWM6CR0_Pos (0UL) /*!< PWM6CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR6_PWM6CR0_Msk (0x1UL) /*!< PWM6CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDUPR7 ========================================================= */
+#define HRPWM_COM_BDUPR7_FLT7R_Pos (29UL) /*!< FLT7R (Bit 29) */
+#define HRPWM_COM_BDUPR7_FLT7R_Msk (0x20000000UL) /*!< FLT7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_OUT7R_Pos (28UL) /*!< OUT7R (Bit 28) */
+#define HRPWM_COM_BDUPR7_OUT7R_Msk (0x10000000UL) /*!< OUT7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPB7CER_Pos (27UL) /*!< CAPB7CER (Bit 27) */
+#define HRPWM_COM_BDUPR7_CAPB7CER_Msk (0x8000000UL) /*!< CAPB7CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPB7CR_Pos (26UL) /*!< CAPB7CR (Bit 26) */
+#define HRPWM_COM_BDUPR7_CAPB7CR_Msk (0x4000000UL) /*!< CAPB7CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPA7CER_Pos (25UL) /*!< CAPA7CER (Bit 25) */
+#define HRPWM_COM_BDUPR7_CAPA7CER_Msk (0x2000000UL) /*!< CAPA7CER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPA7CR_Pos (24UL) /*!< CAPA7CR (Bit 24) */
+#define HRPWM_COM_BDUPR7_CAPA7CR_Msk (0x1000000UL) /*!< CAPA7CR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CHP7R_Pos (23UL) /*!< CHP7R (Bit 23) */
+#define HRPWM_COM_BDUPR7_CHP7R_Msk (0x800000UL) /*!< CHP7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_RST7ER_Pos (22UL) /*!< RST7ER (Bit 22) */
+#define HRPWM_COM_BDUPR7_RST7ER_Msk (0x400000UL) /*!< RST7ER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_RST7R_Pos (21UL) /*!< RST7R (Bit 21) */
+#define HRPWM_COM_BDUPR7_RST7R_Msk (0x200000UL) /*!< RST7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_EEF7R2_Pos (20UL) /*!< EEF7R2 (Bit 20) */
+#define HRPWM_COM_BDUPR7_EEF7R2_Msk (0x100000UL) /*!< EEF7R2 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_EEF7R1_Pos (19UL) /*!< EEF7R1 (Bit 19) */
+#define HRPWM_COM_BDUPR7_EEF7R1_Msk (0x80000UL) /*!< EEF7R1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_EEF7R0_Pos (18UL) /*!< EEF7R0 (Bit 18) */
+#define HRPWM_COM_BDUPR7_EEF7R0_Msk (0x40000UL) /*!< EEF7R0 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CLR7BR_Pos (17UL) /*!< CLR7BR (Bit 17) */
+#define HRPWM_COM_BDUPR7_CLR7BR_Msk (0x20000UL) /*!< CLR7BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_SET7BR_Pos (16UL) /*!< SET7BR (Bit 16) */
+#define HRPWM_COM_BDUPR7_SET7BR_Msk (0x10000UL) /*!< SET7BR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CLR7AR_Pos (15UL) /*!< CLR7AR (Bit 15) */
+#define HRPWM_COM_BDUPR7_CLR7AR_Msk (0x8000UL) /*!< CLR7AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_SET7AR_Pos (14UL) /*!< SET7AR (Bit 14) */
+#define HRPWM_COM_BDUPR7_SET7AR_Msk (0x4000UL) /*!< SET7AR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_DT7R_Pos (13UL) /*!< DT7R (Bit 13) */
+#define HRPWM_COM_BDUPR7_DT7R_Msk (0x2000UL) /*!< DT7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPB7R_Pos (12UL) /*!< CAPB7R (Bit 12) */
+#define HRPWM_COM_BDUPR7_CAPB7R_Msk (0x1000UL) /*!< CAPB7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CAPA7R_Pos (11UL) /*!< CAPA7R (Bit 11) */
+#define HRPWM_COM_BDUPR7_CAPA7R_Msk (0x800UL) /*!< CAPA7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CMPD7R_Pos (10UL) /*!< CMPD7R (Bit 10) */
+#define HRPWM_COM_BDUPR7_CMPD7R_Msk (0x400UL) /*!< CMPD7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CMPC7R_Pos (9UL) /*!< CMPC7R (Bit 9) */
+#define HRPWM_COM_BDUPR7_CMPC7R_Msk (0x200UL) /*!< CMPC7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CMPB7R_Pos (8UL) /*!< CMPB7R (Bit 8) */
+#define HRPWM_COM_BDUPR7_CMPB7R_Msk (0x100UL) /*!< CMPB7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CMPA7R_Pos (7UL) /*!< CMPA7R (Bit 7) */
+#define HRPWM_COM_BDUPR7_CMPA7R_Msk (0x80UL) /*!< CMPA7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_REP7R_Pos (6UL) /*!< REP7R (Bit 6) */
+#define HRPWM_COM_BDUPR7_REP7R_Msk (0x40UL) /*!< REP7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_PER7R_Pos (5UL) /*!< PER7R (Bit 5) */
+#define HRPWM_COM_BDUPR7_PER7R_Msk (0x20UL) /*!< PER7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_CNT7R_Pos (4UL) /*!< CNT7R (Bit 4) */
+#define HRPWM_COM_BDUPR7_CNT7R_Msk (0x10UL) /*!< CNT7R (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_PWM7DIER_Pos (3UL) /*!< PWM7DIER (Bit 3) */
+#define HRPWM_COM_BDUPR7_PWM7DIER_Msk (0x8UL) /*!< PWM7DIER (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_PWM7ISR_Pos (2UL) /*!< PWM7ISR (Bit 2) */
+#define HRPWM_COM_BDUPR7_PWM7ISR_Msk (0x4UL) /*!< PWM7ISR (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_PWM7CR1_Pos (1UL) /*!< PWM7CR1 (Bit 1) */
+#define HRPWM_COM_BDUPR7_PWM7CR1_Msk (0x2UL) /*!< PWM7CR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_COM_BDUPR7_PWM7CR0_Pos (0UL) /*!< PWM7CR0 (Bit 0) */
+#define HRPWM_COM_BDUPR7_PWM7CR0_Msk (0x1UL) /*!< PWM7CR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== BDMWADR ======================================================== */
+#define HRPWM_COM_BDMWADR_BDMADR_Pos (0UL) /*!< BDMADR (Bit 0) */
+#define HRPWM_COM_BDMWADR_BDMADR_Msk (0xffffffffUL) /*!< BDMADR (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== BDMADR ========================================================= */
+#define HRPWM_COM_BDMADR_BDMADR_Pos (0UL) /*!< BDMADR (Bit 0) */
+#define HRPWM_COM_BDMADR_BDMADR_Msk (0xffffffffUL) /*!< BDMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ HRPWM_MST ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= MCR0 ========================================================== */
+#define HRPWM_MST_MCR0_BRSTDMA_Pos (30UL) /*!< BRSTDMA (Bit 30) */
+#define HRPWM_MST_MCR0_BRSTDMA_Msk (0xc0000000UL) /*!< BRSTDMA (Bitfield-Mask: 0x03) */
+#define HRPWM_MST_MCR0_MREPU_Pos (27UL) /*!< MREPU (Bit 27) */
+#define HRPWM_MST_MCR0_MREPU_Msk (0x8000000UL) /*!< MREPU (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_MRSTU_Pos (26UL) /*!< MRSTU (Bit 26) */
+#define HRPWM_MST_MCR0_MRSTU_Msk (0x4000000UL) /*!< MRSTU (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_PREEN_Pos (25UL) /*!< PREEN (Bit 25) */
+#define HRPWM_MST_MCR0_PREEN_Msk (0x2000000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_DACSYNC_Pos (23UL) /*!< DACSYNC (Bit 23) */
+#define HRPWM_MST_MCR0_DACSYNC_Msk (0x1800000UL) /*!< DACSYNC (Bitfield-Mask: 0x03) */
+#define HRPWM_MST_MCR0_SYNCOUTSRC_Pos (14UL) /*!< SYNCOUTSRC (Bit 14) */
+#define HRPWM_MST_MCR0_SYNCOUTSRC_Msk (0xc000UL) /*!< SYNCOUTSRC (Bitfield-Mask: 0x03) */
+#define HRPWM_MST_MCR0_SYNCOUTEN_Pos (13UL) /*!< SYNCOUTEN (Bit 13) */
+#define HRPWM_MST_MCR0_SYNCOUTEN_Msk (0x2000UL) /*!< SYNCOUTEN (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_SYNCOUTPOL_Pos (12UL) /*!< SYNCOUTPOL (Bit 12) */
+#define HRPWM_MST_MCR0_SYNCOUTPOL_Msk (0x1000UL) /*!< SYNCOUTPOL (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_SYNCSTRTM_Pos (11UL) /*!< SYNCSTRTM (Bit 11) */
+#define HRPWM_MST_MCR0_SYNCSTRTM_Msk (0x800UL) /*!< SYNCSTRTM (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_SYNCRSTM_Pos (10UL) /*!< SYNCRSTM (Bit 10) */
+#define HRPWM_MST_MCR0_SYNCRSTM_Msk (0x400UL) /*!< SYNCRSTM (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_SYNCINEN_Pos (9UL) /*!< SYNCINEN (Bit 9) */
+#define HRPWM_MST_MCR0_SYNCINEN_Msk (0x200UL) /*!< SYNCINEN (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_SYNCINSRC_Pos (8UL) /*!< SYNCINSRC (Bit 8) */
+#define HRPWM_MST_MCR0_SYNCINSRC_Msk (0x100UL) /*!< SYNCINSRC (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_INTLVD_Pos (6UL) /*!< INTLVD (Bit 6) */
+#define HRPWM_MST_MCR0_INTLVD_Msk (0xc0UL) /*!< INTLVD (Bitfield-Mask: 0x03) */
+#define HRPWM_MST_MCR0_HALF_Pos (5UL) /*!< HALF (Bit 5) */
+#define HRPWM_MST_MCR0_HALF_Msk (0x20UL) /*!< HALF (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_RETRIG_Pos (4UL) /*!< RETRIG (Bit 4) */
+#define HRPWM_MST_MCR0_RETRIG_Msk (0x10UL) /*!< RETRIG (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_CONT_Pos (3UL) /*!< CONT (Bit 3) */
+#define HRPWM_MST_MCR0_CONT_Msk (0x8UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR0_CKPSC_Pos (0UL) /*!< CKPSC (Bit 0) */
+#define HRPWM_MST_MCR0_CKPSC_Msk (0x7UL) /*!< CKPSC (Bitfield-Mask: 0x07) */
+/* ========================================================= MCR1 ========================================================== */
+#define HRPWM_MST_MCR1_BDMADIS_Pos (31UL) /*!< BDMADIS (Bit 31) */
+#define HRPWM_MST_MCR1_BDMADIS_Msk (0x80000000UL) /*!< BDMADIS (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN7_Pos (24UL) /*!< CEN7 (Bit 24) */
+#define HRPWM_MST_MCR1_CEN7_Msk (0x1000000UL) /*!< CEN7 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN6_Pos (23UL) /*!< CEN6 (Bit 23) */
+#define HRPWM_MST_MCR1_CEN6_Msk (0x800000UL) /*!< CEN6 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN5_Pos (22UL) /*!< CEN5 (Bit 22) */
+#define HRPWM_MST_MCR1_CEN5_Msk (0x400000UL) /*!< CEN5 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN4_Pos (21UL) /*!< CEN4 (Bit 21) */
+#define HRPWM_MST_MCR1_CEN4_Msk (0x200000UL) /*!< CEN4 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN3_Pos (20UL) /*!< CEN3 (Bit 20) */
+#define HRPWM_MST_MCR1_CEN3_Msk (0x100000UL) /*!< CEN3 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN2_Pos (19UL) /*!< CEN2 (Bit 19) */
+#define HRPWM_MST_MCR1_CEN2_Msk (0x80000UL) /*!< CEN2 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN1_Pos (18UL) /*!< CEN1 (Bit 18) */
+#define HRPWM_MST_MCR1_CEN1_Msk (0x40000UL) /*!< CEN1 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_CEN0_Pos (17UL) /*!< CEN0 (Bit 17) */
+#define HRPWM_MST_MCR1_CEN0_Msk (0x20000UL) /*!< CEN0 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCR1_MCEN_Pos (16UL) /*!< MCEN (Bit 16) */
+#define HRPWM_MST_MCR1_MCEN_Msk (0x10000UL) /*!< MCEN (Bitfield-Mask: 0x01) */
+/* ========================================================= MISR ========================================================== */
+#define HRPWM_MST_MISR_MREP_Pos (8UL) /*!< MREP (Bit 8) */
+#define HRPWM_MST_MISR_MREP_Msk (0x100UL) /*!< MREP (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MRST_Pos (7UL) /*!< MRST (Bit 7) */
+#define HRPWM_MST_MISR_MRST_Msk (0x80UL) /*!< MRST (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MUPD_Pos (6UL) /*!< MUPD (Bit 6) */
+#define HRPWM_MST_MISR_MUPD_Msk (0x40UL) /*!< MUPD (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_SYNC_Pos (5UL) /*!< SYNC (Bit 5) */
+#define HRPWM_MST_MISR_SYNC_Msk (0x20UL) /*!< SYNC (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MPER_Pos (4UL) /*!< MPER (Bit 4) */
+#define HRPWM_MST_MISR_MPER_Msk (0x10UL) /*!< MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MCMPD_Pos (3UL) /*!< MCMPD (Bit 3) */
+#define HRPWM_MST_MISR_MCMPD_Msk (0x8UL) /*!< MCMPD (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MCMPC_Pos (2UL) /*!< MCMPC (Bit 2) */
+#define HRPWM_MST_MISR_MCMPC_Msk (0x4UL) /*!< MCMPC (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MCMPB_Pos (1UL) /*!< MCMPB (Bit 1) */
+#define HRPWM_MST_MISR_MCMPB_Msk (0x2UL) /*!< MCMPB (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MISR_MCMPA_Pos (0UL) /*!< MCMPA (Bit 0) */
+#define HRPWM_MST_MISR_MCMPA_Msk (0x1UL) /*!< MCMPA (Bitfield-Mask: 0x01) */
+/* ========================================================= MDIER ========================================================= */
+#define HRPWM_MST_MDIER_MREPDE_Pos (24UL) /*!< MREPDE (Bit 24) */
+#define HRPWM_MST_MDIER_MREPDE_Msk (0x1000000UL) /*!< MREPDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MRSTDE_Pos (23UL) /*!< MRSTDE (Bit 23) */
+#define HRPWM_MST_MDIER_MRSTDE_Msk (0x800000UL) /*!< MRSTDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MUPDDE_Pos (22UL) /*!< MUPDDE (Bit 22) */
+#define HRPWM_MST_MDIER_MUPDDE_Msk (0x400000UL) /*!< MUPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_SYNCDE_Pos (21UL) /*!< SYNCDE (Bit 21) */
+#define HRPWM_MST_MDIER_SYNCDE_Msk (0x200000UL) /*!< SYNCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MPERDE_Pos (20UL) /*!< MPERDE (Bit 20) */
+#define HRPWM_MST_MDIER_MPERDE_Msk (0x100000UL) /*!< MPERDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPDDE_Pos (19UL) /*!< MCMPDDE (Bit 19) */
+#define HRPWM_MST_MDIER_MCMPDDE_Msk (0x80000UL) /*!< MCMPDDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPCDE_Pos (18UL) /*!< MCMPCDE (Bit 18) */
+#define HRPWM_MST_MDIER_MCMPCDE_Msk (0x40000UL) /*!< MCMPCDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPBDE_Pos (17UL) /*!< MCMPBDE (Bit 17) */
+#define HRPWM_MST_MDIER_MCMPBDE_Msk (0x20000UL) /*!< MCMPBDE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPADE_Pos (16UL) /*!< MCMPADE (Bit 16) */
+#define HRPWM_MST_MDIER_MCMPADE_Msk (0x10000UL) /*!< MCMPADE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MREPIE_Pos (8UL) /*!< MREPIE (Bit 8) */
+#define HRPWM_MST_MDIER_MREPIE_Msk (0x100UL) /*!< MREPIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MRSTIE_Pos (7UL) /*!< MRSTIE (Bit 7) */
+#define HRPWM_MST_MDIER_MRSTIE_Msk (0x80UL) /*!< MRSTIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MUPDIE_Pos (6UL) /*!< MUPDIE (Bit 6) */
+#define HRPWM_MST_MDIER_MUPDIE_Msk (0x40UL) /*!< MUPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_SYNCIE_Pos (5UL) /*!< SYNCIE (Bit 5) */
+#define HRPWM_MST_MDIER_SYNCIE_Msk (0x20UL) /*!< SYNCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MPERIE_Pos (4UL) /*!< MPERIE (Bit 4) */
+#define HRPWM_MST_MDIER_MPERIE_Msk (0x10UL) /*!< MPERIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPDIE_Pos (3UL) /*!< MCMPDIE (Bit 3) */
+#define HRPWM_MST_MDIER_MCMPDIE_Msk (0x8UL) /*!< MCMPDIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPCIE_Pos (2UL) /*!< MCMPCIE (Bit 2) */
+#define HRPWM_MST_MDIER_MCMPCIE_Msk (0x4UL) /*!< MCMPCIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPBIE_Pos (1UL) /*!< MCMPBIE (Bit 1) */
+#define HRPWM_MST_MDIER_MCMPBIE_Msk (0x2UL) /*!< MCMPBIE (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDIER_MCMPAIE_Pos (0UL) /*!< MCMPAIE (Bit 0) */
+#define HRPWM_MST_MDIER_MCMPAIE_Msk (0x1UL) /*!< MCMPAIE (Bitfield-Mask: 0x01) */
+/* ========================================================= MCNTR ========================================================= */
+#define HRPWM_MST_MCNTR_CNTWR_Pos (19UL) /*!< CNTWR (Bit 19) */
+#define HRPWM_MST_MCNTR_CNTWR_Msk (0x80000UL) /*!< CNTWR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCNTR_CNTRD_Pos (18UL) /*!< CNTRD (Bit 18) */
+#define HRPWM_MST_MCNTR_CNTRD_Msk (0x40000UL) /*!< CNTRD (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MCNTR_MCNT_Pos (0UL) /*!< MCNT (Bit 0) */
+#define HRPWM_MST_MCNTR_MCNT_Msk (0xffffUL) /*!< MCNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= MPER ========================================================== */
+#define HRPWM_MST_MPER_MPER_Pos (0UL) /*!< MPER (Bit 0) */
+#define HRPWM_MST_MPER_MPER_Msk (0xffffUL) /*!< MPER (Bitfield-Mask: 0xffff) */
+/* ========================================================= MREP ========================================================== */
+#define HRPWM_MST_MREP_MREP_Pos (0UL) /*!< MREP (Bit 0) */
+#define HRPWM_MST_MREP_MREP_Msk (0xffUL) /*!< MREP (Bitfield-Mask: 0xff) */
+/* ======================================================== MCMPAR ========================================================= */
+#define HRPWM_MST_MCMPAR_MCMPA_Pos (0UL) /*!< MCMPA (Bit 0) */
+#define HRPWM_MST_MCMPAR_MCMPA_Msk (0xffffUL) /*!< MCMPA (Bitfield-Mask: 0xffff) */
+/* ======================================================== MCMPBR ========================================================= */
+#define HRPWM_MST_MCMPBR_MCMPB_Pos (0UL) /*!< MCMPB (Bit 0) */
+#define HRPWM_MST_MCMPBR_MCMPB_Msk (0xffffUL) /*!< MCMPB (Bitfield-Mask: 0xffff) */
+/* ======================================================== MCMPCR ========================================================= */
+#define HRPWM_MST_MCMPCR_MCMPC_Pos (0UL) /*!< MCMPC (Bit 0) */
+#define HRPWM_MST_MCMPCR_MCMPC_Msk (0xffffUL) /*!< MCMPC (Bitfield-Mask: 0xffff) */
+/* ======================================================== MCMPDR ========================================================= */
+#define HRPWM_MST_MCMPDR_MCMPD_Pos (0UL) /*!< MCMPD (Bit 0) */
+#define HRPWM_MST_MCMPDR_MCMPD_Msk (0xffffUL) /*!< MCMPD (Bitfield-Mask: 0xffff) */
+/* ======================================================== MDMAUR ========================================================= */
+#define HRPWM_MST_MDMAUR_MCMPDR_Pos (10UL) /*!< MCMPDR (Bit 10) */
+#define HRPWM_MST_MDMAUR_MCMPDR_Msk (0x400UL) /*!< MCMPDR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCMPCR_Pos (9UL) /*!< MCMPCR (Bit 9) */
+#define HRPWM_MST_MDMAUR_MCMPCR_Msk (0x200UL) /*!< MCMPCR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCMPBR_Pos (8UL) /*!< MCMPBR (Bit 8) */
+#define HRPWM_MST_MDMAUR_MCMPBR_Msk (0x100UL) /*!< MCMPBR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCMPAR_Pos (7UL) /*!< MCMPAR (Bit 7) */
+#define HRPWM_MST_MDMAUR_MCMPAR_Msk (0x80UL) /*!< MCMPAR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MREP_Pos (6UL) /*!< MREP (Bit 6) */
+#define HRPWM_MST_MDMAUR_MREP_Msk (0x40UL) /*!< MREP (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MPER_Pos (5UL) /*!< MPER (Bit 5) */
+#define HRPWM_MST_MDMAUR_MPER_Msk (0x20UL) /*!< MPER (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCNTR_Pos (4UL) /*!< MCNTR (Bit 4) */
+#define HRPWM_MST_MDMAUR_MCNTR_Msk (0x10UL) /*!< MCNTR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MDIER_Pos (3UL) /*!< MDIER (Bit 3) */
+#define HRPWM_MST_MDMAUR_MDIER_Msk (0x8UL) /*!< MDIER (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MISR_Pos (2UL) /*!< MISR (Bit 2) */
+#define HRPWM_MST_MDMAUR_MISR_Msk (0x4UL) /*!< MISR (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCR1_Pos (1UL) /*!< MCR1 (Bit 1) */
+#define HRPWM_MST_MDMAUR_MCR1_Msk (0x2UL) /*!< MCR1 (Bitfield-Mask: 0x01) */
+#define HRPWM_MST_MDMAUR_MCR0_Pos (0UL) /*!< MCR0 (Bit 0) */
+#define HRPWM_MST_MDMAUR_MCR0_Msk (0x1UL) /*!< MCR0 (Bitfield-Mask: 0x01) */
+/* ======================================================== MDMADR ========================================================= */
+#define HRPWM_MST_MDMADR_MDMADR_Pos (0UL) /*!< MDMADR (Bit 0) */
+#define HRPWM_MST_MDMADR_MDMADR_Msk (0xffffffffUL) /*!< MDMADR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR3_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR3_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR3_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR3_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR3_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_CMS_Pos (5UL) /*!< CMS (Bit 5) */
+#define TMR3_CR0_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */
+#define TMR3_CR0_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+#define TMR3_CR0_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR3_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR3_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR3_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR3_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR3_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR3_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR3_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR3_SCR_EE_Pos (22UL) /*!< EE (Bit 22) */
+#define TMR3_SCR_EE_Msk (0x400000UL) /*!< EE (Bitfield-Mask: 0x01) */
+#define TMR3_SCR_EMS_Pos (20UL) /*!< EMS (Bit 20) */
+#define TMR3_SCR_EMS_Msk (0x300000UL) /*!< EMS (Bitfield-Mask: 0x03) */
+#define TMR3_SCR_EFS_Pos (16UL) /*!< EFS (Bit 16) */
+#define TMR3_SCR_EFS_Msk (0xf0000UL) /*!< EFS (Bitfield-Mask: 0x0f) */
+#define TMR3_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR3_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR3_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR3_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR3_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR3_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR3_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR3_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C3OIE_Pos (7UL) /*!< C3OIE (Bit 7) */
+#define TMR3_IER_C3OIE_Msk (0x80UL) /*!< C3OIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C3MIE_Pos (6UL) /*!< C3MIE (Bit 6) */
+#define TMR3_IER_C3MIE_Msk (0x40UL) /*!< C3MIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C2OIE_Pos (5UL) /*!< C2OIE (Bit 5) */
+#define TMR3_IER_C2OIE_Msk (0x20UL) /*!< C2OIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C2MIE_Pos (4UL) /*!< C2MIE (Bit 4) */
+#define TMR3_IER_C2MIE_Msk (0x10UL) /*!< C2MIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR3_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR3_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR3_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR3_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR3_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR3_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR3_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR3_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR3_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC3OIF_Pos (7UL) /*!< CC3OIF (Bit 7) */
+#define TMR3_SR_CC3OIF_Msk (0x80UL) /*!< CC3OIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC3MIF_Pos (6UL) /*!< CC3MIF (Bit 6) */
+#define TMR3_SR_CC3MIF_Msk (0x40UL) /*!< CC3MIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC2OIF_Pos (5UL) /*!< CC2OIF (Bit 5) */
+#define TMR3_SR_CC2OIF_Msk (0x20UL) /*!< CC2OIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC2MIF_Pos (4UL) /*!< CC2MIF (Bit 4) */
+#define TMR3_SR_CC2MIF_Msk (0x10UL) /*!< CC2MIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR3_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR3_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR3_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR3_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR3_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR3_UGR_CC3UG_Pos (7UL) /*!< CC3UG (Bit 7) */
+#define TMR3_UGR_CC3UG_Msk (0x80UL) /*!< CC3UG (Bitfield-Mask: 0x01) */
+#define TMR3_UGR_CC2UG_Pos (6UL) /*!< CC2UG (Bit 6) */
+#define TMR3_UGR_CC2UG_Msk (0x40UL) /*!< CC2UG (Bitfield-Mask: 0x01) */
+#define TMR3_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR3_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR3_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR3_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR3_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR3_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR3_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR3_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR3_CCMR_OC3M_Pos (28UL) /*!< OC3M (Bit 28) */
+#define TMR3_CCMR_OC3M_Msk (0xf0000000UL) /*!< OC3M (Bitfield-Mask: 0x0f) */
+#define TMR3_CCMR_CC3PE_Pos (26UL) /*!< CC3PE (Bit 26) */
+#define TMR3_CCMR_CC3PE_Msk (0xc000000UL) /*!< CC3PE (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_CC3S_Pos (24UL) /*!< CC3S (Bit 24) */
+#define TMR3_CCMR_CC3S_Msk (0x3000000UL) /*!< CC3S (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_OC2M_Pos (20UL) /*!< OC2M (Bit 20) */
+#define TMR3_CCMR_OC2M_Msk (0xf00000UL) /*!< OC2M (Bitfield-Mask: 0x0f) */
+#define TMR3_CCMR_CC2PE_Pos (18UL) /*!< CC2PE (Bit 18) */
+#define TMR3_CCMR_CC2PE_Msk (0xc0000UL) /*!< CC2PE (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_CC2S_Pos (16UL) /*!< CC2S (Bit 16) */
+#define TMR3_CCMR_CC2S_Msk (0x30000UL) /*!< CC2S (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR3_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR3_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR3_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR3_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR3_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR3_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR3_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR3_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR3_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR3_CCER_CC3P_Pos (14UL) /*!< CC3P (Bit 14) */
+#define TMR3_CCER_CC3P_Msk (0xc000UL) /*!< CC3P (Bitfield-Mask: 0x03) */
+#define TMR3_CCER_CC3E_Pos (12UL) /*!< CC3E (Bit 12) */
+#define TMR3_CCER_CC3E_Msk (0x1000UL) /*!< CC3E (Bitfield-Mask: 0x01) */
+#define TMR3_CCER_CC2P_Pos (10UL) /*!< CC2P (Bit 10) */
+#define TMR3_CCER_CC2P_Msk (0xc00UL) /*!< CC2P (Bitfield-Mask: 0x03) */
+#define TMR3_CCER_CC2E_Pos (8UL) /*!< CC2E (Bit 8) */
+#define TMR3_CCER_CC2E_Msk (0x100UL) /*!< CC2E (Bitfield-Mask: 0x01) */
+#define TMR3_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR3_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR3_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR3_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR3_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR3_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR3_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR3_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR3_TTCR_TC3E_Pos (11UL) /*!< TC3E (Bit 11) */
+#define TMR3_TTCR_TC3E_Msk (0x800UL) /*!< TC3E (Bitfield-Mask: 0x01) */
+#define TMR3_TTCR_TC2E_Pos (10UL) /*!< TC2E (Bit 10) */
+#define TMR3_TTCR_TC2E_Msk (0x400UL) /*!< TC2E (Bitfield-Mask: 0x01) */
+#define TMR3_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR3_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR3_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR3_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR3_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR3_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR3_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR3_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR3_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR3_CPR_CPV_Msk (0xffffffffUL) /*!< CPV (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR3_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR3_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR3_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR3_CNTR_CNT_Msk (0xffffffffUL) /*!< CNT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR3_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR3_CC0R_CC0V_Msk (0xffffffffUL) /*!< CC0V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR3_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR3_CC1R_CC1V_Msk (0xffffffffUL) /*!< CC1V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC2R ========================================================== */
+#define TMR3_CC2R_CC2V_Pos (0UL) /*!< CC2V (Bit 0) */
+#define TMR3_CC2R_CC2V_Msk (0xffffffffUL) /*!< CC2V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC3R ========================================================== */
+#define TMR3_CC3R_CC3V_Pos (0UL) /*!< CC3V (Bit 0) */
+#define TMR3_CC3R_CC3V_Msk (0xffffffffUL) /*!< CC3V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR3_CIR_C3TIS_Pos (24UL) /*!< C3TIS (Bit 24) */
+#define TMR3_CIR_C3TIS_Msk (0xf000000UL) /*!< C3TIS (Bitfield-Mask: 0x0f) */
+#define TMR3_CIR_C2TIS_Pos (16UL) /*!< C2TIS (Bit 16) */
+#define TMR3_CIR_C2TIS_Msk (0xf0000UL) /*!< C2TIS (Bitfield-Mask: 0x0f) */
+#define TMR3_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR3_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR3_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR3_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR4_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR4_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR4_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR4_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR4_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_CMS_Pos (5UL) /*!< CMS (Bit 5) */
+#define TMR4_CR0_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */
+#define TMR4_CR0_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+#define TMR4_CR0_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR4_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR4_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR4_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR4_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR4_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR4_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR4_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR4_SCR_EE_Pos (22UL) /*!< EE (Bit 22) */
+#define TMR4_SCR_EE_Msk (0x400000UL) /*!< EE (Bitfield-Mask: 0x01) */
+#define TMR4_SCR_EMS_Pos (20UL) /*!< EMS (Bit 20) */
+#define TMR4_SCR_EMS_Msk (0x300000UL) /*!< EMS (Bitfield-Mask: 0x03) */
+#define TMR4_SCR_EFS_Pos (16UL) /*!< EFS (Bit 16) */
+#define TMR4_SCR_EFS_Msk (0xf0000UL) /*!< EFS (Bitfield-Mask: 0x0f) */
+#define TMR4_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR4_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR4_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR4_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR4_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR4_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR4_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR4_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C3OIE_Pos (7UL) /*!< C3OIE (Bit 7) */
+#define TMR4_IER_C3OIE_Msk (0x80UL) /*!< C3OIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C3MIE_Pos (6UL) /*!< C3MIE (Bit 6) */
+#define TMR4_IER_C3MIE_Msk (0x40UL) /*!< C3MIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C2OIE_Pos (5UL) /*!< C2OIE (Bit 5) */
+#define TMR4_IER_C2OIE_Msk (0x20UL) /*!< C2OIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C2MIE_Pos (4UL) /*!< C2MIE (Bit 4) */
+#define TMR4_IER_C2MIE_Msk (0x10UL) /*!< C2MIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR4_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR4_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR4_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR4_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR4_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR4_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR4_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR4_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR4_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC3OIF_Pos (7UL) /*!< CC3OIF (Bit 7) */
+#define TMR4_SR_CC3OIF_Msk (0x80UL) /*!< CC3OIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC3MIF_Pos (6UL) /*!< CC3MIF (Bit 6) */
+#define TMR4_SR_CC3MIF_Msk (0x40UL) /*!< CC3MIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC2OIF_Pos (5UL) /*!< CC2OIF (Bit 5) */
+#define TMR4_SR_CC2OIF_Msk (0x20UL) /*!< CC2OIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC2MIF_Pos (4UL) /*!< CC2MIF (Bit 4) */
+#define TMR4_SR_CC2MIF_Msk (0x10UL) /*!< CC2MIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR4_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR4_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR4_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR4_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR4_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR4_UGR_CC3UG_Pos (7UL) /*!< CC3UG (Bit 7) */
+#define TMR4_UGR_CC3UG_Msk (0x80UL) /*!< CC3UG (Bitfield-Mask: 0x01) */
+#define TMR4_UGR_CC2UG_Pos (6UL) /*!< CC2UG (Bit 6) */
+#define TMR4_UGR_CC2UG_Msk (0x40UL) /*!< CC2UG (Bitfield-Mask: 0x01) */
+#define TMR4_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR4_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR4_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR4_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR4_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR4_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR4_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR4_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR4_CCMR_OC3M_Pos (28UL) /*!< OC3M (Bit 28) */
+#define TMR4_CCMR_OC3M_Msk (0xf0000000UL) /*!< OC3M (Bitfield-Mask: 0x0f) */
+#define TMR4_CCMR_CC3PE_Pos (26UL) /*!< CC3PE (Bit 26) */
+#define TMR4_CCMR_CC3PE_Msk (0xc000000UL) /*!< CC3PE (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_CC3S_Pos (24UL) /*!< CC3S (Bit 24) */
+#define TMR4_CCMR_CC3S_Msk (0x3000000UL) /*!< CC3S (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_OC2M_Pos (20UL) /*!< OC2M (Bit 20) */
+#define TMR4_CCMR_OC2M_Msk (0xf00000UL) /*!< OC2M (Bitfield-Mask: 0x0f) */
+#define TMR4_CCMR_CC2PE_Pos (18UL) /*!< CC2PE (Bit 18) */
+#define TMR4_CCMR_CC2PE_Msk (0xc0000UL) /*!< CC2PE (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_CC2S_Pos (16UL) /*!< CC2S (Bit 16) */
+#define TMR4_CCMR_CC2S_Msk (0x30000UL) /*!< CC2S (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR4_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR4_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR4_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR4_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR4_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR4_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR4_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR4_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR4_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR4_CCER_CC3P_Pos (14UL) /*!< CC3P (Bit 14) */
+#define TMR4_CCER_CC3P_Msk (0xc000UL) /*!< CC3P (Bitfield-Mask: 0x03) */
+#define TMR4_CCER_CC3E_Pos (12UL) /*!< CC3E (Bit 12) */
+#define TMR4_CCER_CC3E_Msk (0x1000UL) /*!< CC3E (Bitfield-Mask: 0x01) */
+#define TMR4_CCER_CC2P_Pos (10UL) /*!< CC2P (Bit 10) */
+#define TMR4_CCER_CC2P_Msk (0xc00UL) /*!< CC2P (Bitfield-Mask: 0x03) */
+#define TMR4_CCER_CC2E_Pos (8UL) /*!< CC2E (Bit 8) */
+#define TMR4_CCER_CC2E_Msk (0x100UL) /*!< CC2E (Bitfield-Mask: 0x01) */
+#define TMR4_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR4_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR4_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR4_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR4_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR4_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR4_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR4_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR4_TTCR_TC3E_Pos (11UL) /*!< TC3E (Bit 11) */
+#define TMR4_TTCR_TC3E_Msk (0x800UL) /*!< TC3E (Bitfield-Mask: 0x01) */
+#define TMR4_TTCR_TC2E_Pos (10UL) /*!< TC2E (Bit 10) */
+#define TMR4_TTCR_TC2E_Msk (0x400UL) /*!< TC2E (Bitfield-Mask: 0x01) */
+#define TMR4_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR4_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR4_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR4_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR4_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR4_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR4_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR4_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR4_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR4_CPR_CPV_Msk (0xffffffffUL) /*!< CPV (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR4_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR4_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR4_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR4_CNTR_CNT_Msk (0xffffffffUL) /*!< CNT (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR4_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR4_CC0R_CC0V_Msk (0xffffffffUL) /*!< CC0V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR4_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR4_CC1R_CC1V_Msk (0xffffffffUL) /*!< CC1V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC2R ========================================================== */
+#define TMR4_CC2R_CC2V_Pos (0UL) /*!< CC2V (Bit 0) */
+#define TMR4_CC2R_CC2V_Msk (0xffffffffUL) /*!< CC2V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CC3R ========================================================== */
+#define TMR4_CC3R_CC3V_Pos (0UL) /*!< CC3V (Bit 0) */
+#define TMR4_CC3R_CC3V_Msk (0xffffffffUL) /*!< CC3V (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR4_CIR_C3TIS_Pos (24UL) /*!< C3TIS (Bit 24) */
+#define TMR4_CIR_C3TIS_Msk (0xf000000UL) /*!< C3TIS (Bitfield-Mask: 0x0f) */
+#define TMR4_CIR_C2TIS_Pos (16UL) /*!< C2TIS (Bit 16) */
+#define TMR4_CIR_C2TIS_Msk (0xf0000UL) /*!< C2TIS (Bitfield-Mask: 0x0f) */
+#define TMR4_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR4_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR4_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR4_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR0_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR0_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR0_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR0_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR0_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR0_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR0_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR0_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR0_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR0_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR0_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR0_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR0_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR0_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR0_CR1_OIS1N_Pos (11UL) /*!< OIS1N (Bit 11) */
+#define TMR0_CR1_OIS1N_Msk (0x800UL) /*!< OIS1N (Bitfield-Mask: 0x01) */
+#define TMR0_CR1_OIS1_Pos (10UL) /*!< OIS1 (Bit 10) */
+#define TMR0_CR1_OIS1_Msk (0x400UL) /*!< OIS1 (Bitfield-Mask: 0x01) */
+#define TMR0_CR1_OIS0N_Pos (9UL) /*!< OIS0N (Bit 9) */
+#define TMR0_CR1_OIS0N_Msk (0x200UL) /*!< OIS0N (Bitfield-Mask: 0x01) */
+#define TMR0_CR1_OIS0_Pos (8UL) /*!< OIS0 (Bit 8) */
+#define TMR0_CR1_OIS0_Msk (0x100UL) /*!< OIS0 (Bitfield-Mask: 0x01) */
+#define TMR0_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR0_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR0_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR0_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR0_SCR_FE_Pos (7UL) /*!< FE (Bit 7) */
+#define TMR0_SCR_FE_Msk (0x80UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define TMR0_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR0_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR0_IER_BIE_Pos (11UL) /*!< BIE (Bit 11) */
+#define TMR0_IER_BIE_Msk (0x800UL) /*!< BIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR0_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR0_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR0_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR0_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR0_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR0_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR0_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR0_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR0_SR_SBIF_Pos (12UL) /*!< SBIF (Bit 12) */
+#define TMR0_SR_SBIF_Msk (0x1000UL) /*!< SBIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_BIF_Pos (11UL) /*!< BIF (Bit 11) */
+#define TMR0_SR_BIF_Msk (0x800UL) /*!< BIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR0_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR0_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR0_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR0_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR0_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR0_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR0_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR0_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR0_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR0_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR0_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR0_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR0_UGR_BG_Pos (2UL) /*!< BG (Bit 2) */
+#define TMR0_UGR_BG_Msk (0x4UL) /*!< BG (Bitfield-Mask: 0x01) */
+#define TMR0_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR0_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR0_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR0_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR0_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR0_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR0_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR0_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR0_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR0_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR0_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR0_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR0_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR0_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR0_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR0_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR0_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR0_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR0_CCER_CC1NE_Pos (5UL) /*!< CC1NE (Bit 5) */
+#define TMR0_CCER_CC1NE_Msk (0x20UL) /*!< CC1NE (Bitfield-Mask: 0x01) */
+#define TMR0_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR0_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR0_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR0_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR0_CCER_CC0NE_Pos (1UL) /*!< CC0NE (Bit 1) */
+#define TMR0_CCER_CC0NE_Msk (0x2UL) /*!< CC0NE (Bitfield-Mask: 0x01) */
+#define TMR0_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR0_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+#define TMR0_DCR_BKF_Pos (14UL) /*!< BKF (Bit 14) */
+#define TMR0_DCR_BKF_Msk (0x3fc000UL) /*!< BKF (Bitfield-Mask: 0xff) */
+#define TMR0_DCR_BKP_Pos (13UL) /*!< BKP (Bit 13) */
+#define TMR0_DCR_BKP_Msk (0x2000UL) /*!< BKP (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_BKE_Pos (12UL) /*!< BKE (Bit 12) */
+#define TMR0_DCR_BKE_Msk (0x1000UL) /*!< BKE (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_MOE_Pos (11UL) /*!< MOE (Bit 11) */
+#define TMR0_DCR_MOE_Msk (0x800UL) /*!< MOE (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_AOE_Pos (10UL) /*!< AOE (Bit 10) */
+#define TMR0_DCR_AOE_Msk (0x400UL) /*!< AOE (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_OSSR_Pos (9UL) /*!< OSSR (Bit 9) */
+#define TMR0_DCR_OSSR_Msk (0x200UL) /*!< OSSR (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_OSSI_Pos (8UL) /*!< OSSI (Bit 8) */
+#define TMR0_DCR_OSSI_Msk (0x100UL) /*!< OSSI (Bitfield-Mask: 0x01) */
+#define TMR0_DCR_DTG_Pos (0UL) /*!< DTG (Bit 0) */
+#define TMR0_DCR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR0_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR0_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR0_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR0_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR0_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR0_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR0_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR0_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR0_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR0_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR0_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR0_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR0_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR0_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================== CRR ========================================================== */
+#define TMR0_CRR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define TMR0_CRR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR0_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR0_CC0R_CC0V_Msk (0xffffUL) /*!< CC0V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR0_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR0_CC1R_CC1V_Msk (0xffffUL) /*!< CC1V (Bitfield-Mask: 0xffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR0_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR0_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR0_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR0_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+/* ========================================================== BPR ========================================================== */
+#define TMR0_BPR_BPOL_Pos (0UL) /*!< BPOL (Bit 0) */
+#define TMR0_BPR_BPOL_Msk (0xffffUL) /*!< BPOL (Bitfield-Mask: 0xffff) */
+/* ========================================================== BER ========================================================== */
+#define TMR0_BER_BIEN_Pos (0UL) /*!< BIEN (Bit 0) */
+#define TMR0_BER_BIEN_Msk (0xffffUL) /*!< BIEN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR1_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR1_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR1_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR1_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR1_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR1_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR1_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR1_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR1_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR1_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR1_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR1_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR1_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR1_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR1_CR1_OIS1N_Pos (11UL) /*!< OIS1N (Bit 11) */
+#define TMR1_CR1_OIS1N_Msk (0x800UL) /*!< OIS1N (Bitfield-Mask: 0x01) */
+#define TMR1_CR1_OIS1_Pos (10UL) /*!< OIS1 (Bit 10) */
+#define TMR1_CR1_OIS1_Msk (0x400UL) /*!< OIS1 (Bitfield-Mask: 0x01) */
+#define TMR1_CR1_OIS0N_Pos (9UL) /*!< OIS0N (Bit 9) */
+#define TMR1_CR1_OIS0N_Msk (0x200UL) /*!< OIS0N (Bitfield-Mask: 0x01) */
+#define TMR1_CR1_OIS0_Pos (8UL) /*!< OIS0 (Bit 8) */
+#define TMR1_CR1_OIS0_Msk (0x100UL) /*!< OIS0 (Bitfield-Mask: 0x01) */
+#define TMR1_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR1_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR1_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR1_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR1_SCR_FE_Pos (7UL) /*!< FE (Bit 7) */
+#define TMR1_SCR_FE_Msk (0x80UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define TMR1_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR1_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR1_IER_BIE_Pos (11UL) /*!< BIE (Bit 11) */
+#define TMR1_IER_BIE_Msk (0x800UL) /*!< BIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR1_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR1_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR1_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR1_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR1_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR1_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR1_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR1_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR1_SR_SBIF_Pos (12UL) /*!< SBIF (Bit 12) */
+#define TMR1_SR_SBIF_Msk (0x1000UL) /*!< SBIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_BIF_Pos (11UL) /*!< BIF (Bit 11) */
+#define TMR1_SR_BIF_Msk (0x800UL) /*!< BIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR1_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR1_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR1_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR1_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR1_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR1_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR1_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR1_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR1_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR1_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR1_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR1_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR1_UGR_BG_Pos (2UL) /*!< BG (Bit 2) */
+#define TMR1_UGR_BG_Msk (0x4UL) /*!< BG (Bitfield-Mask: 0x01) */
+#define TMR1_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR1_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR1_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR1_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR1_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR1_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR1_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR1_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR1_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR1_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR1_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR1_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR1_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR1_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR1_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR1_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR1_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR1_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR1_CCER_CC1NE_Pos (5UL) /*!< CC1NE (Bit 5) */
+#define TMR1_CCER_CC1NE_Msk (0x20UL) /*!< CC1NE (Bitfield-Mask: 0x01) */
+#define TMR1_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR1_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR1_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR1_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR1_CCER_CC0NE_Pos (1UL) /*!< CC0NE (Bit 1) */
+#define TMR1_CCER_CC0NE_Msk (0x2UL) /*!< CC0NE (Bitfield-Mask: 0x01) */
+#define TMR1_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR1_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+#define TMR1_DCR_BKF_Pos (14UL) /*!< BKF (Bit 14) */
+#define TMR1_DCR_BKF_Msk (0x3fc000UL) /*!< BKF (Bitfield-Mask: 0xff) */
+#define TMR1_DCR_BKP_Pos (13UL) /*!< BKP (Bit 13) */
+#define TMR1_DCR_BKP_Msk (0x2000UL) /*!< BKP (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_BKE_Pos (12UL) /*!< BKE (Bit 12) */
+#define TMR1_DCR_BKE_Msk (0x1000UL) /*!< BKE (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_MOE_Pos (11UL) /*!< MOE (Bit 11) */
+#define TMR1_DCR_MOE_Msk (0x800UL) /*!< MOE (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_AOE_Pos (10UL) /*!< AOE (Bit 10) */
+#define TMR1_DCR_AOE_Msk (0x400UL) /*!< AOE (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_OSSR_Pos (9UL) /*!< OSSR (Bit 9) */
+#define TMR1_DCR_OSSR_Msk (0x200UL) /*!< OSSR (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_OSSI_Pos (8UL) /*!< OSSI (Bit 8) */
+#define TMR1_DCR_OSSI_Msk (0x100UL) /*!< OSSI (Bitfield-Mask: 0x01) */
+#define TMR1_DCR_DTG_Pos (0UL) /*!< DTG (Bit 0) */
+#define TMR1_DCR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR1_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR1_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR1_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR1_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR1_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR1_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR1_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR1_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR1_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR1_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR1_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR1_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR1_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR1_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================== CRR ========================================================== */
+#define TMR1_CRR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define TMR1_CRR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR1_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR1_CC0R_CC0V_Msk (0xffffUL) /*!< CC0V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR1_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR1_CC1R_CC1V_Msk (0xffffUL) /*!< CC1V (Bitfield-Mask: 0xffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR1_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR1_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR1_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR1_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+/* ========================================================== BPR ========================================================== */
+#define TMR1_BPR_BPOL_Pos (0UL) /*!< BPOL (Bit 0) */
+#define TMR1_BPR_BPOL_Msk (0xffffUL) /*!< BPOL (Bitfield-Mask: 0xffff) */
+/* ========================================================== BER ========================================================== */
+#define TMR1_BER_BIEN_Pos (0UL) /*!< BIEN (Bit 0) */
+#define TMR1_BER_BIEN_Msk (0xffffUL) /*!< BIEN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR2_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR2_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR2_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR2_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR2_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR2_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR2_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR2_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR2_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR2_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR2_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR2_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR2_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR2_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR2_CR1_OIS1N_Pos (11UL) /*!< OIS1N (Bit 11) */
+#define TMR2_CR1_OIS1N_Msk (0x800UL) /*!< OIS1N (Bitfield-Mask: 0x01) */
+#define TMR2_CR1_OIS1_Pos (10UL) /*!< OIS1 (Bit 10) */
+#define TMR2_CR1_OIS1_Msk (0x400UL) /*!< OIS1 (Bitfield-Mask: 0x01) */
+#define TMR2_CR1_OIS0N_Pos (9UL) /*!< OIS0N (Bit 9) */
+#define TMR2_CR1_OIS0N_Msk (0x200UL) /*!< OIS0N (Bitfield-Mask: 0x01) */
+#define TMR2_CR1_OIS0_Pos (8UL) /*!< OIS0 (Bit 8) */
+#define TMR2_CR1_OIS0_Msk (0x100UL) /*!< OIS0 (Bitfield-Mask: 0x01) */
+#define TMR2_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR2_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR2_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR2_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR2_SCR_FE_Pos (7UL) /*!< FE (Bit 7) */
+#define TMR2_SCR_FE_Msk (0x80UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define TMR2_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR2_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR2_IER_BIE_Pos (11UL) /*!< BIE (Bit 11) */
+#define TMR2_IER_BIE_Msk (0x800UL) /*!< BIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR2_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR2_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR2_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR2_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR2_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR2_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR2_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR2_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR2_SR_SBIF_Pos (12UL) /*!< SBIF (Bit 12) */
+#define TMR2_SR_SBIF_Msk (0x1000UL) /*!< SBIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_BIF_Pos (11UL) /*!< BIF (Bit 11) */
+#define TMR2_SR_BIF_Msk (0x800UL) /*!< BIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR2_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR2_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR2_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR2_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR2_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR2_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR2_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR2_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR2_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR2_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR2_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR2_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR2_UGR_BG_Pos (2UL) /*!< BG (Bit 2) */
+#define TMR2_UGR_BG_Msk (0x4UL) /*!< BG (Bitfield-Mask: 0x01) */
+#define TMR2_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR2_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR2_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR2_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR2_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR2_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR2_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR2_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR2_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR2_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR2_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR2_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR2_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR2_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR2_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR2_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR2_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR2_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR2_CCER_CC1NE_Pos (5UL) /*!< CC1NE (Bit 5) */
+#define TMR2_CCER_CC1NE_Msk (0x20UL) /*!< CC1NE (Bitfield-Mask: 0x01) */
+#define TMR2_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR2_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR2_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR2_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR2_CCER_CC0NE_Pos (1UL) /*!< CC0NE (Bit 1) */
+#define TMR2_CCER_CC0NE_Msk (0x2UL) /*!< CC0NE (Bitfield-Mask: 0x01) */
+#define TMR2_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR2_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+#define TMR2_DCR_BKF_Pos (14UL) /*!< BKF (Bit 14) */
+#define TMR2_DCR_BKF_Msk (0x3fc000UL) /*!< BKF (Bitfield-Mask: 0xff) */
+#define TMR2_DCR_BKP_Pos (13UL) /*!< BKP (Bit 13) */
+#define TMR2_DCR_BKP_Msk (0x2000UL) /*!< BKP (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_BKE_Pos (12UL) /*!< BKE (Bit 12) */
+#define TMR2_DCR_BKE_Msk (0x1000UL) /*!< BKE (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_MOE_Pos (11UL) /*!< MOE (Bit 11) */
+#define TMR2_DCR_MOE_Msk (0x800UL) /*!< MOE (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_AOE_Pos (10UL) /*!< AOE (Bit 10) */
+#define TMR2_DCR_AOE_Msk (0x400UL) /*!< AOE (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_OSSR_Pos (9UL) /*!< OSSR (Bit 9) */
+#define TMR2_DCR_OSSR_Msk (0x200UL) /*!< OSSR (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_OSSI_Pos (8UL) /*!< OSSI (Bit 8) */
+#define TMR2_DCR_OSSI_Msk (0x100UL) /*!< OSSI (Bitfield-Mask: 0x01) */
+#define TMR2_DCR_DTG_Pos (0UL) /*!< DTG (Bit 0) */
+#define TMR2_DCR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR2_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR2_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR2_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR2_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR2_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR2_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR2_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR2_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR2_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR2_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR2_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR2_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR2_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR2_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================== CRR ========================================================== */
+#define TMR2_CRR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define TMR2_CRR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR2_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR2_CC0R_CC0V_Msk (0xffffUL) /*!< CC0V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR2_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR2_CC1R_CC1V_Msk (0xffffUL) /*!< CC1V (Bitfield-Mask: 0xffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR2_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR2_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR2_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR2_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+/* ========================================================== BPR ========================================================== */
+#define TMR2_BPR_BPOL_Pos (0UL) /*!< BPOL (Bit 0) */
+#define TMR2_BPR_BPOL_Msk (0xffffUL) /*!< BPOL (Bitfield-Mask: 0xffff) */
+/* ========================================================== BER ========================================================== */
+#define TMR2_BER_BIEN_Pos (0UL) /*!< BIEN (Bit 0) */
+#define TMR2_BER_BIEN_Msk (0xffffUL) /*!< BIEN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOA ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOA_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOA_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOA_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOA_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOA_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOA_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOA_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOA_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOA_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOA_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOA_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOA_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOA_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOA_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOA_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOA_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOA_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOA_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOA_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOA_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOA_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOA_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOA_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOA_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOA_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOA_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOA_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOA_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOA_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOA_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOA_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOA_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOA_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOA_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOB ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOB_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOB_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOB_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOB_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOB_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOB_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOB_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOB_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOB_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOB_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOB_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOB_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOB_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOB_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOB_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOB_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOB_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOB_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOB_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOB_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOB_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOB_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOB_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOB_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOB_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOB_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOB_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOB_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOB_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOB_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOB_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOB_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOB_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOB_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOC_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOC_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOC_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOC_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOC_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOC_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOC_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOC_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOC_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOC_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOC_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOC_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOC_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOC_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOC_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOC_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOC_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOC_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOC_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOC_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOC_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOC_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOC_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOC_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOC_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOC_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOC_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOC_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOC_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOC_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOC_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOC_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOC_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOC_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOD ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOD_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOD_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOD_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOD_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOD_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOD_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOD_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOD_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOD_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOD_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOD_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOD_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOD_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOD_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOD_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOD_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOD_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOD_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOD_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOD_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOD_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOD_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOD_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOD_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOD_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOD_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOD_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOD_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOD_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOD_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOD_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOD_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOD_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOD_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOE ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOE_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOE_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOE_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOE_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOE_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOE_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOE_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOE_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOE_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOE_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOE_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOE_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOE_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOE_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOE_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOE_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOE_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOE_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOE_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOE_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOE_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOE_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOE_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOE_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOE_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOE_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOE_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOE_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOE_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOE_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOE_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOE_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOE_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOE_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOF ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== BSR ========================================================== */
+#define GPIOF_BSR_BRn_Pos (16UL) /*!< BRn (Bit 16) */
+#define GPIOF_BSR_BRn_Msk (0x10000UL) /*!< BRn (Bitfield-Mask: 0x01) */
+#define GPIOF_BSR_BSn_Pos (0UL) /*!< BSn (Bit 0) */
+#define GPIOF_BSR_BSn_Msk (0x1UL) /*!< BSn (Bitfield-Mask: 0x01) */
+/* ========================================================== DIR ========================================================== */
+#define GPIOF_DIR_DIn_Pos (0UL) /*!< DIn (Bit 0) */
+#define GPIOF_DIR_DIn_Msk (0x1UL) /*!< DIn (Bitfield-Mask: 0x01) */
+/* ========================================================== DOR ========================================================== */
+#define GPIOF_DOR_DOn_Pos (0UL) /*!< DOn (Bit 0) */
+#define GPIOF_DOR_DOn_Msk (0x1UL) /*!< DOn (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define GPIOF_IER_IEn_Pos (0UL) /*!< IEn (Bit 0) */
+#define GPIOF_IER_IEn_Msk (0x1UL) /*!< IEn (Bitfield-Mask: 0x01) */
+/* ========================================================== IMR ========================================================== */
+#define GPIOF_IMR_IMn_Pos (0UL) /*!< IMn (Bit 0) */
+#define GPIOF_IMR_IMn_Msk (0x3UL) /*!< IMn (Bitfield-Mask: 0x03) */
+/* ========================================================== ISR ========================================================== */
+#define GPIOF_ISR_ISn_Pos (0UL) /*!< ISn (Bit 0) */
+#define GPIOF_ISR_ISn_Msk (0x1UL) /*!< ISn (Bitfield-Mask: 0x01) */
+/* ========================================================== MR0 ========================================================== */
+#define GPIOF_MR0_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOF_MR0_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== MR1 ========================================================== */
+#define GPIOF_MR1_PMn_Pos (0UL) /*!< PMn (Bit 0) */
+#define GPIOF_MR1_PMn_Msk (0xfUL) /*!< PMn (Bitfield-Mask: 0x0f) */
+/* ========================================================== SER ========================================================== */
+#define GPIOF_SER_SEn_Pos (0UL) /*!< SEn (Bit 0) */
+#define GPIOF_SER_SEn_Msk (0x1UL) /*!< SEn (Bitfield-Mask: 0x01) */
+/* ========================================================== DER ========================================================== */
+#define GPIOF_DER_DEn_Pos (0UL) /*!< DEn (Bit 0) */
+#define GPIOF_DER_DEn_Msk (0x1UL) /*!< DEn (Bitfield-Mask: 0x01) */
+/* ========================================================== UDR ========================================================== */
+#define GPIOF_UDR_UDn_Pos (0UL) /*!< UDn (Bit 0) */
+#define GPIOF_UDR_UDn_Msk (0x3UL) /*!< UDn (Bitfield-Mask: 0x03) */
+/* ========================================================== ODR ========================================================== */
+#define GPIOF_ODR_ODn_Pos (0UL) /*!< ODn (Bit 0) */
+#define GPIOF_ODR_ODn_Msk (0x1UL) /*!< ODn (Bitfield-Mask: 0x01) */
+/* ========================================================== DHR ========================================================== */
+#define GPIOF_DHR_DRy_Pos (16UL) /*!< DRy (Bit 16) */
+#define GPIOF_DHR_DRy_Msk (0x10000UL) /*!< DRy (Bitfield-Mask: 0x01) */
+#define GPIOF_DHR_DRx_Pos (0UL) /*!< DRx (Bit 0) */
+#define GPIOF_DHR_DRx_Msk (0x1UL) /*!< DRx (Bitfield-Mask: 0x01) */
+/* ========================================================== IHR ========================================================== */
+#define GPIOF_IHR_IDn_Pos (0UL) /*!< IDn (Bit 0) */
+#define GPIOF_IHR_IDn_Msk (0x1UL) /*!< IDn (Bitfield-Mask: 0x01) */
+/* ========================================================== OSR ========================================================== */
+#define GPIOF_OSR_OSn_Pos (0UL) /*!< OSn (Bit 0) */
+#define GPIOF_OSR_OSn_Msk (0x1UL) /*!< OSn (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ FLASH ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define FLASH_CR_LCK_Pos (31UL) /*!< LCK (Bit 31) */
+#define FLASH_CR_LCK_Msk (0x80000000UL) /*!< LCK (Bitfield-Mask: 0x01) */
+#define FLASH_CR_NMIE_Pos (10UL) /*!< NMIE (Bit 10) */
+#define FLASH_CR_NMIE_Msk (0x400UL) /*!< NMIE (Bitfield-Mask: 0x01) */
+#define FLASH_CR_EIE_Pos (7UL) /*!< EIE (Bit 7) */
+#define FLASH_CR_EIE_Msk (0x80UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define FLASH_CR_FLE_Pos (6UL) /*!< FLE (Bit 6) */
+#define FLASH_CR_FLE_Msk (0x40UL) /*!< FLE (Bitfield-Mask: 0x01) */
+#define FLASH_CR_DPE_Pos (5UL) /*!< DPE (Bit 5) */
+#define FLASH_CR_DPE_Msk (0x20UL) /*!< DPE (Bitfield-Mask: 0x01) */
+#define FLASH_CR_IPE_Pos (4UL) /*!< IPE (Bit 4) */
+#define FLASH_CR_IPE_Msk (0x10UL) /*!< IPE (Bitfield-Mask: 0x01) */
+#define FLASH_CR_CRS_Pos (3UL) /*!< CRS (Bit 3) */
+#define FLASH_CR_CRS_Msk (0x8UL) /*!< CRS (Bitfield-Mask: 0x01) */
+#define FLASH_CR_ES_Pos (1UL) /*!< ES (Bit 1) */
+#define FLASH_CR_ES_Msk (0x2UL) /*!< ES (Bitfield-Mask: 0x01) */
+#define FLASH_CR_PS_Pos (0UL) /*!< PS (Bit 0) */
+#define FLASH_CR_PS_Msk (0x1UL) /*!< PS (Bitfield-Mask: 0x01) */
+/* ========================================================== LPR ========================================================== */
+#define FLASH_LPR_LCK_Pos (31UL) /*!< LCK (Bit 31) */
+#define FLASH_LPR_LCK_Msk (0x80000000UL) /*!< LCK (Bitfield-Mask: 0x01) */
+#define FLASH_LPR_SEL_Pos (2UL) /*!< SEL (Bit 2) */
+#define FLASH_LPR_SEL_Msk (0xcUL) /*!< SEL (Bitfield-Mask: 0x03) */
+#define FLASH_LPR_LW_Pos (1UL) /*!< LW (Bit 1) */
+#define FLASH_LPR_LW_Msk (0x2UL) /*!< LW (Bitfield-Mask: 0x01) */
+#define FLASH_LPR_LS_Pos (0UL) /*!< LS (Bit 0) */
+#define FLASH_LPR_LS_Msk (0x1UL) /*!< LS (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define FLASH_SR_BST_Pos (31UL) /*!< BST (Bit 31) */
+#define FLASH_SR_BST_Msk (0x80000000UL) /*!< BST (Bitfield-Mask: 0x01) */
+#define FLASH_SR_BMS_Pos (30UL) /*!< BMS (Bit 30) */
+#define FLASH_SR_BMS_Msk (0x40000000UL) /*!< BMS (Bitfield-Mask: 0x01) */
+#define FLASH_SR_OPE_Pos (10UL) /*!< OPE (Bit 10) */
+#define FLASH_SR_OPE_Msk (0x400UL) /*!< OPE (Bitfield-Mask: 0x01) */
+#define FLASH_SR_PES_Pos (9UL) /*!< PES (Bit 9) */
+#define FLASH_SR_PES_Msk (0x200UL) /*!< PES (Bitfield-Mask: 0x01) */
+#define FLASH_SR_PGE_Pos (8UL) /*!< PGE (Bit 8) */
+#define FLASH_SR_PGE_Msk (0x100UL) /*!< PGE (Bitfield-Mask: 0x01) */
+#define FLASH_SR_BM_Pos (7UL) /*!< BM (Bit 7) */
+#define FLASH_SR_BM_Msk (0x80UL) /*!< BM (Bitfield-Mask: 0x01) */
+#define FLASH_SR_WM_Pos (6UL) /*!< WM (Bit 6) */
+#define FLASH_SR_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */
+#define FLASH_SR_DBC_Pos (5UL) /*!< DBC (Bit 5) */
+#define FLASH_SR_DBC_Msk (0x20UL) /*!< DBC (Bitfield-Mask: 0x01) */
+#define FLASH_SR_SBC_Pos (4UL) /*!< SBC (Bit 4) */
+#define FLASH_SR_SBC_Msk (0x10UL) /*!< SBC (Bitfield-Mask: 0x01) */
+#define FLASH_SR_BSY_Pos (3UL) /*!< BSY (Bit 3) */
+#define FLASH_SR_BSY_Msk (0x8UL) /*!< BSY (Bitfield-Mask: 0x01) */
+#define FLASH_SR_IOS_Pos (2UL) /*!< IOS (Bit 2) */
+#define FLASH_SR_IOS_Msk (0x4UL) /*!< IOS (Bitfield-Mask: 0x01) */
+#define FLASH_SR_WPS_Pos (1UL) /*!< WPS (Bit 1) */
+#define FLASH_SR_WPS_Msk (0x2UL) /*!< WPS (Bitfield-Mask: 0x01) */
+#define FLASH_SR_OES_Pos (0UL) /*!< OES (Bit 0) */
+#define FLASH_SR_OES_Msk (0x1UL) /*!< OES (Bitfield-Mask: 0x01) */
+/* ========================================================= PDR0 ========================================================== */
+#define FLASH_PDR0_PD0_Pos (0UL) /*!< PD0 (Bit 0) */
+#define FLASH_PDR0_PD0_Msk (0xffffffffUL) /*!< PD0 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= PDR1 ========================================================== */
+#define FLASH_PDR1_PD1_Pos (0UL) /*!< PD1 (Bit 0) */
+#define FLASH_PDR1_PD1_Msk (0xffffffffUL) /*!< PD1 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== PAR ========================================================== */
+#define FLASH_PAR_EM_Pos (20UL) /*!< EM (Bit 20) */
+#define FLASH_PAR_EM_Msk (0x300000UL) /*!< EM (Bitfield-Mask: 0x03) */
+#define FLASH_PAR_PA_Pos (0UL) /*!< PA (Bit 0) */
+#define FLASH_PAR_PA_Msk (0x7ffffUL) /*!< PA (Bitfield-Mask: 0x7ffff) */
+/* ========================================================== KR =========================================================== */
+#define FLASH_KR_PLK_Pos (16UL) /*!< PLK (Bit 16) */
+#define FLASH_KR_PLK_Msk (0x10000UL) /*!< PLK (Bitfield-Mask: 0x01) */
+#define FLASH_KR_KEY_Pos (0UL) /*!< KEY (Bit 0) */
+#define FLASH_KR_KEY_Msk (0xffffUL) /*!< KEY (Bitfield-Mask: 0xffff) */
+/* ========================================================== RPR ========================================================== */
+#define FLASH_RPR_RPLV_Pos (0UL) /*!< RPLV (Bit 0) */
+#define FLASH_RPR_RPLV_Msk (0xffUL) /*!< RPLV (Bitfield-Mask: 0xff) */
+/* ========================================================== WPR ========================================================== */
+#define FLASH_WPR_WRPC_Pos (0UL) /*!< WRPC (Bit 0) */
+#define FLASH_WPR_WRPC_Msk (0xffffffffUL) /*!< WRPC (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== TR =========================================================== */
+#define FLASH_TR_APG_Pos (12UL) /*!< APG (Bit 12) */
+#define FLASH_TR_APG_Msk (0x3ff000UL) /*!< APG (Bitfield-Mask: 0x3ff) */
+#define FLASH_TR_UNIT_Pos (4UL) /*!< UNIT (Bit 4) */
+#define FLASH_TR_UNIT_Msk (0xff0UL) /*!< UNIT (Bitfield-Mask: 0xff) */
+#define FLASH_TR_RC_Pos (0UL) /*!< RC (Bit 0) */
+#define FLASH_TR_RC_Msk (0xfUL) /*!< RC (Bitfield-Mask: 0x0f) */
+/* ========================================================= OPDR ========================================================== */
+#define FLASH_OPDR_MAP_Pos (28UL) /*!< MAP (Bit 28) */
+#define FLASH_OPDR_MAP_Msk (0xf0000000UL) /*!< MAP (Bitfield-Mask: 0x0f) */
+#define FLASH_OPDR_BMD_Pos (24UL) /*!< BMD (Bit 24) */
+#define FLASH_OPDR_BMD_Msk (0xf000000UL) /*!< BMD (Bitfield-Mask: 0x0f) */
+#define FLASH_OPDR_WWEN_Pos (20UL) /*!< WWEN (Bit 20) */
+#define FLASH_OPDR_WWEN_Msk (0xf00000UL) /*!< WWEN (Bitfield-Mask: 0x0f) */
+#define FLASH_OPDR_IWEN_Pos (16UL) /*!< IWEN (Bit 16) */
+#define FLASH_OPDR_IWEN_Msk (0xf0000UL) /*!< IWEN (Bitfield-Mask: 0x0f) */
+#define FLASH_OPDR_EBP_Pos (12UL) /*!< EBP (Bit 12) */
+#define FLASH_OPDR_EBP_Msk (0xf000UL) /*!< EBP (Bitfield-Mask: 0x0f) */
+#define FLASH_OPDR_BORLV_Pos (8UL) /*!< BORLV (Bit 8) */
+#define FLASH_OPDR_BORLV_Msk (0x300UL) /*!< BORLV (Bitfield-Mask: 0x03) */
+#define FLASH_OPDR_BSEL_Pos (4UL) /*!< BSEL (Bit 4) */
+#define FLASH_OPDR_BSEL_Msk (0x70UL) /*!< BSEL (Bitfield-Mask: 0x07) */
+#define FLASH_OPDR_BLK_Pos (0UL) /*!< BLK (Bit 0) */
+#define FLASH_OPDR_BLK_Msk (0xfUL) /*!< BLK (Bitfield-Mask: 0x0f) */
+/* ========================================================= EAR0 ========================================================== */
+#define FLASH_EAR0_EAD1_Pos (0UL) /*!< EAD1 (Bit 0) */
+#define FLASH_EAR0_EAD1_Msk (0xffffffffUL) /*!< EAD1 (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= EAR1 ========================================================== */
+#define FLASH_EAR1_EADn_Pos (0UL) /*!< EADn (Bit 0) */
+#define FLASH_EAR1_EADn_Msk (0xffffffffUL) /*!< EADn (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA0_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA0_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA0_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA0_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA0_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA0_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA0_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA0_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA0_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA0_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA0_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA0_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA0_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA0_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA0_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA0_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA0_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA0_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA0_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA0_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA0_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA0_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA0_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA0_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA0_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA0_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA0_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA0_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA0_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA0_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA0_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA0_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA0_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA0_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA0_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA0_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA0_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA0_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA0_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA0_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA0_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA0_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA0_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA1_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA1_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA1_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA1_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA1_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA1_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA1_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA1_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA1_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA1_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA1_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA1_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA1_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA1_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA1_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA1_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA1_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA1_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA1_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA1_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA1_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA1_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA1_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA1_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA1_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA1_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA1_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA1_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA1_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA1_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA1_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA1_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA1_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA1_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA1_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA1_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA1_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA1_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA1_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA1_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA1_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA1_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA1_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA2_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA2_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA2_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA2_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA2_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA2_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA2_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA2_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA2_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA2_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA2_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA2_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA2_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA2_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA2_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA2_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA2_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA2_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA2_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA2_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA2_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA2_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA2_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA2_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA2_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA2_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA2_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA2_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA2_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA2_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA2_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA2_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA2_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA2_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA2_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA2_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA2_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA2_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA2_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA2_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA2_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA2_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA2_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA3_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA3_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA3_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA3_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA3_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA3_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA3_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA3_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA3_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA3_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA3_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA3_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA3_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA3_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA3_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA3_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA3_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA3_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA3_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA3_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA3_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA3_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA3_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA3_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA3_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA3_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA3_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA3_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA3_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA3_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA3_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA3_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA3_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA3_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA3_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA3_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA3_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA3_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA3_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA3_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA3_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA3_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA3_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA4_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA4_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA4_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA4_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA4_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA4_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA4_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA4_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA4_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA4_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA4_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA4_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA4_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA4_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA4_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA4_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA4_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA4_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA4_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA4_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA4_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA4_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA4_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA4_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA4_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA4_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA4_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA4_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA4_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA4_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA4_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA4_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA4_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA4_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA4_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA4_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA4_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA4_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA4_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA4_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA4_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA4_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA4_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DMA5 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== SAR ========================================================== */
+#define DMA5_SAR_SAR_Pos (0UL) /*!< SAR (Bit 0) */
+#define DMA5_SAR_SAR_Msk (0xffffffffUL) /*!< SAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DAR ========================================================== */
+#define DMA5_DAR_DAR_Pos (0UL) /*!< DAR (Bit 0) */
+#define DMA5_DAR_DAR_Msk (0xffffffffUL) /*!< DAR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================== DBL ========================================================== */
+#define DMA5_DBL_BL_Pos (0UL) /*!< BL (Bit 0) */
+#define DMA5_DBL_BL_Msk (0xfffUL) /*!< BL (Bitfield-Mask: 0xfff) */
+/* ========================================================== CTR ========================================================== */
+#define DMA5_CTR_DMS_Pos (31UL) /*!< DMS (Bit 31) */
+#define DMA5_CTR_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_SMS_Pos (30UL) /*!< SMS (Bit 30) */
+#define DMA5_CTR_SMS_Msk (0x40000000UL) /*!< SMS (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_DBL_Pos (28UL) /*!< DBL (Bit 28) */
+#define DMA5_CTR_DBL_Msk (0x30000000UL) /*!< DBL (Bitfield-Mask: 0x03) */
+#define DMA5_CTR_SBL_Pos (26UL) /*!< SBL (Bit 26) */
+#define DMA5_CTR_SBL_Msk (0xc000000UL) /*!< SBL (Bitfield-Mask: 0x03) */
+#define DMA5_CTR_DHF_Pos (21UL) /*!< DHF (Bit 21) */
+#define DMA5_CTR_DHF_Msk (0x3e00000UL) /*!< DHF (Bitfield-Mask: 0x1f) */
+#define DMA5_CTR_SHF_Pos (16UL) /*!< SHF (Bit 16) */
+#define DMA5_CTR_SHF_Msk (0x1f0000UL) /*!< SHF (Bitfield-Mask: 0x1f) */
+#define DMA5_CTR_DDS_Pos (14UL) /*!< DDS (Bit 14) */
+#define DMA5_CTR_DDS_Msk (0xc000UL) /*!< DDS (Bitfield-Mask: 0x03) */
+#define DMA5_CTR_SDS_Pos (12UL) /*!< SDS (Bit 12) */
+#define DMA5_CTR_SDS_Msk (0x3000UL) /*!< SDS (Bitfield-Mask: 0x03) */
+#define DMA5_CTR_CIE_Pos (10UL) /*!< CIE (Bit 10) */
+#define DMA5_CTR_CIE_Msk (0x400UL) /*!< CIE (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_HCIE_Pos (9UL) /*!< HCIE (Bit 9) */
+#define DMA5_CTR_HCIE_Msk (0x200UL) /*!< HCIE (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_EIE_Pos (8UL) /*!< EIE (Bit 8) */
+#define DMA5_CTR_EIE_Msk (0x100UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_DAI_Pos (7UL) /*!< DAI (Bit 7) */
+#define DMA5_CTR_DAI_Msk (0x80UL) /*!< DAI (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_SAI_Pos (6UL) /*!< SAI (Bit 6) */
+#define DMA5_CTR_SAI_Msk (0x40UL) /*!< SAI (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_TC_Pos (4UL) /*!< TC (Bit 4) */
+#define DMA5_CTR_TC_Msk (0x30UL) /*!< TC (Bitfield-Mask: 0x03) */
+#define DMA5_CTR_TM_Pos (3UL) /*!< TM (Bit 3) */
+#define DMA5_CTR_TM_Msk (0x8UL) /*!< TM (Bitfield-Mask: 0x01) */
+#define DMA5_CTR_PRI_Pos (0UL) /*!< PRI (Bit 0) */
+#define DMA5_CTR_PRI_Msk (0x7UL) /*!< PRI (Bitfield-Mask: 0x07) */
+/* ========================================================== CER ========================================================== */
+#define DMA5_CER_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define DMA5_CER_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== STR ========================================================== */
+#define DMA5_STR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
+#define DMA5_STR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
+#define DMA5_STR_CS_Pos (2UL) /*!< CS (Bit 2) */
+#define DMA5_STR_CS_Msk (0x4UL) /*!< CS (Bitfield-Mask: 0x01) */
+#define DMA5_STR_HS_Pos (1UL) /*!< HS (Bit 1) */
+#define DMA5_STR_HS_Msk (0x2UL) /*!< HS (Bitfield-Mask: 0x01) */
+#define DMA5_STR_ES_Pos (0UL) /*!< ES (Bit 0) */
+#define DMA5_STR_ES_Msk (0x1UL) /*!< ES (Bitfield-Mask: 0x01) */
+/* ========================================================== DTL ========================================================== */
+#define DMA5_DTL_DTR_Pos (0UL) /*!< DTR (Bit 0) */
+#define DMA5_DTL_DTR_Msk (0xffffffffUL) /*!< DTR (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC0_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC0_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC0_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC0_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC0_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC0_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC0_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC0_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC0_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC0_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC0_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC0_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC0_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC0_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC0_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC0_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC0_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC0_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC0_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC0_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC0_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC0_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC0_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC0_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC0_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC0_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC0_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC0_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC0_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC0_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC0_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC0_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC0_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC0_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC0_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC0_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC0_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC0_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC0_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC0_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC0_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC0_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC0_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC1_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC1_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC1_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC1_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC1_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC1_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC1_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC1_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC1_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC1_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC1_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC1_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC1_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC1_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC1_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC1_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC1_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC1_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC1_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC1_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC1_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC1_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC1_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC1_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC1_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC1_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC1_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC1_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC1_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC1_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC1_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC1_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC1_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC1_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC1_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC1_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC1_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC1_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC1_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC1_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC1_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC1_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC1_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC1_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC2_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC2_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC2_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC2_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC2_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC2_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC2_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC2_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC2_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC2_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC2_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC2_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC2_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC2_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC2_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC2_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC2_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC2_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC2_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC2_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC2_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC2_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC2_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC2_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC2_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC2_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC2_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC2_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC2_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC2_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC2_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC2_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC2_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC2_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC2_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC2_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC2_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC2_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC2_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC2_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC2_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC2_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC2_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC2_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC3_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC3_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC3_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC3_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC3_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC3_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC3_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC3_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC3_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC3_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC3_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC3_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC3_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC3_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC3_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC3_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC3_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC3_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC3_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC3_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC3_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC3_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC3_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC3_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC3_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC3_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC3_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC3_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC3_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC3_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC3_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC3_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC3_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC3_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC3_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC3_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC3_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC3_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC3_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC3_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC3_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC3_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC3_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC3_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC4_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC4_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC4_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC4_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC4_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC4_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC4_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC4_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC4_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC4_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC4_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC4_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC4_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC4_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC4_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC4_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC4_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC4_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC4_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC4_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC4_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC4_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC4_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC4_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC4_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC4_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC4_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC4_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC4_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC4_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC4_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC4_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC4_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC4_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC4_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC4_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC4_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC4_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC4_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC4_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC4_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC4_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC4_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC4_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC5 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC5_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC5_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC5_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC5_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC5_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC5_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC5_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC5_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC5_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC5_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC5_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC5_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC5_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC5_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC5_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC5_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC5_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC5_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC5_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC5_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC5_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC5_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC5_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC5_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC5_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC5_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC5_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC5_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC5_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC5_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC5_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC5_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC5_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC5_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC5_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC5_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC5_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC5_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC5_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC5_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC5_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC5_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC5_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC5_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC6 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC6_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC6_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC6_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC6_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC6_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC6_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC6_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC6_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC6_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC6_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC6_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC6_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC6_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC6_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC6_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC6_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC6_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC6_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC6_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC6_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC6_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC6_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC6_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC6_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC6_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC6_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC6_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC6_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC6_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC6_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC6_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC6_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC6_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC6_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC6_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC6_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC6_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC6_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC6_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC6_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC6_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC6_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC6_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC6_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC7 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC7_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC7_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC7_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC7_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC7_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC7_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC7_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC7_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC7_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC7_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC7_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC7_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC7_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC7_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC7_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC7_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC7_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC7_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC7_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC7_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC7_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC7_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC7_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC7_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC7_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC7_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC7_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC7_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC7_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC7_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC7_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC7_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC7_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC7_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC7_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC7_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC7_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC7_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC7_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC7_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC7_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC7_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC7_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC7_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ DAC8 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define DAC8_CR_STM_Pos (31UL) /*!< STM (Bit 31) */
+#define DAC8_CR_STM_Msk (0x80000000UL) /*!< STM (Bitfield-Mask: 0x01) */
+#define DAC8_CR_STE_Pos (25UL) /*!< STE (Bit 25) */
+#define DAC8_CR_STE_Msk (0x2000000UL) /*!< STE (Bitfield-Mask: 0x01) */
+#define DAC8_CR_STDIR_Pos (24UL) /*!< STDIR (Bit 24) */
+#define DAC8_CR_STDIR_Msk (0x1000000UL) /*!< STDIR (Bitfield-Mask: 0x01) */
+#define DAC8_CR_STINCTRIG_Pos (20UL) /*!< STINCTRIG (Bit 20) */
+#define DAC8_CR_STINCTRIG_Msk (0xf00000UL) /*!< STINCTRIG (Bitfield-Mask: 0x0f) */
+#define DAC8_CR_STRSTTRIG_Pos (16UL) /*!< STRSTTRIG (Bit 16) */
+#define DAC8_CR_STRSTTRIG_Msk (0xf0000UL) /*!< STRSTTRIG (Bitfield-Mask: 0x0f) */
+#define DAC8_CR_TGE_Pos (13UL) /*!< TGE (Bit 13) */
+#define DAC8_CR_TGE_Msk (0x2000UL) /*!< TGE (Bitfield-Mask: 0x01) */
+#define DAC8_CR_TGDIR_Pos (12UL) /*!< TGDIR (Bit 12) */
+#define DAC8_CR_TGDIR_Msk (0x1000UL) /*!< TGDIR (Bitfield-Mask: 0x01) */
+#define DAC8_CR_TGAMP_Pos (8UL) /*!< TGAMP (Bit 8) */
+#define DAC8_CR_TGAMP_Msk (0xf00UL) /*!< TGAMP (Bitfield-Mask: 0x0f) */
+#define DAC8_CR_TGTRIG_Pos (4UL) /*!< TGTRIG (Bit 4) */
+#define DAC8_CR_TGTRIG_Msk (0xf0UL) /*!< TGTRIG (Bitfield-Mask: 0x0f) */
+#define DAC8_CR_TEN_Pos (3UL) /*!< TEN (Bit 3) */
+#define DAC8_CR_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */
+#define DAC8_CR_OEN_Pos (2UL) /*!< OEN (Bit 2) */
+#define DAC8_CR_OEN_Msk (0x4UL) /*!< OEN (Bitfield-Mask: 0x01) */
+#define DAC8_CR_BEN_Pos (1UL) /*!< BEN (Bit 1) */
+#define DAC8_CR_BEN_Msk (0x2UL) /*!< BEN (Bitfield-Mask: 0x01) */
+#define DAC8_CR_PEN_Pos (0UL) /*!< PEN (Bit 0) */
+#define DAC8_CR_PEN_Msk (0x1UL) /*!< PEN (Bitfield-Mask: 0x01) */
+/* ========================================================== WDR ========================================================== */
+#define DAC8_WDR_WDAT_Pos (0UL) /*!< WDAT (Bit 0) */
+#define DAC8_WDR_WDAT_Msk (0xfffUL) /*!< WDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================== RDR ========================================================== */
+#define DAC8_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
+#define DAC8_RDR_RDAT_Msk (0xfffUL) /*!< RDAT (Bitfield-Mask: 0xfff) */
+/* ========================================================= SIDR ========================================================== */
+#define DAC8_SIDR_SID_Pos (0UL) /*!< SID (Bit 0) */
+#define DAC8_SIDR_SID_Msk (0xffffUL) /*!< SID (Bitfield-Mask: 0xffff) */
+/* ========================================================= SRDR ========================================================== */
+#define DAC8_SRDR_SRD_Pos (4UL) /*!< SRD (Bit 4) */
+#define DAC8_SRDR_SRD_Msk (0xfff0UL) /*!< SRD (Bitfield-Mask: 0xfff) */
+#define DAC8_SRDR_SRDL_Pos (0UL) /*!< SRDL (Bit 0) */
+#define DAC8_SRDR_SRDL_Msk (0xfUL) /*!< SRDL (Bitfield-Mask: 0x0f) */
+/* ========================================================= SWTR ========================================================== */
+#define DAC8_SWTR_SWTB_Pos (1UL) /*!< SWTB (Bit 1) */
+#define DAC8_SWTR_SWTB_Msk (0x2UL) /*!< SWTB (Bitfield-Mask: 0x01) */
+#define DAC8_SWTR_SWT_Pos (0UL) /*!< SWT (Bit 0) */
+#define DAC8_SWTR_SWT_Msk (0x1UL) /*!< SWT (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define DAC8_SR_DONB_Pos (1UL) /*!< DONB (Bit 1) */
+#define DAC8_SR_DONB_Msk (0x2UL) /*!< DONB (Bitfield-Mask: 0x01) */
+#define DAC8_SR_DON_Pos (0UL) /*!< DON (Bit 0) */
+#define DAC8_SR_DON_Msk (0x1UL) /*!< DON (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CORDIC ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CSR0 ========================================================== */
+#define CORDIC_CSR0_RRDY_Pos (31UL) /*!< RRDY (Bit 31) */
+#define CORDIC_CSR0_RRDY_Msk (0x80000000UL) /*!< RRDY (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_ERR_Pos (30UL) /*!< ERR (Bit 30) */
+#define CORDIC_CSR0_ERR_Msk (0x40000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_RRDYCLR_Pos (29UL) /*!< RRDYCLR (Bit 29) */
+#define CORDIC_CSR0_RRDYCLR_Msk (0x20000000UL) /*!< RRDYCLR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_ERRCLR_Pos (28UL) /*!< ERRCLR (Bit 28) */
+#define CORDIC_CSR0_ERRCLR_Msk (0x10000000UL) /*!< ERRCLR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_ARGSIZE_Pos (22UL) /*!< ARGSIZE (Bit 22) */
+#define CORDIC_CSR0_ARGSIZE_Msk (0x400000UL) /*!< ARGSIZE (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_RESSIZE_Pos (21UL) /*!< RESSIZE (Bit 21) */
+#define CORDIC_CSR0_RESSIZE_Msk (0x200000UL) /*!< RESSIZE (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_NARGS_Pos (20UL) /*!< NARGS (Bit 20) */
+#define CORDIC_CSR0_NARGS_Msk (0x100000UL) /*!< NARGS (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_NRES_Pos (19UL) /*!< NRES (Bit 19) */
+#define CORDIC_CSR0_NRES_Msk (0x80000UL) /*!< NRES (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_ERRIEN_Pos (17UL) /*!< ERRIEN (Bit 17) */
+#define CORDIC_CSR0_ERRIEN_Msk (0x20000UL) /*!< ERRIEN (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_RRDYIEN_Pos (16UL) /*!< RRDYIEN (Bit 16) */
+#define CORDIC_CSR0_RRDYIEN_Msk (0x10000UL) /*!< RRDYIEN (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR0_SCALE_Pos (8UL) /*!< SCALE (Bit 8) */
+#define CORDIC_CSR0_SCALE_Msk (0x1f00UL) /*!< SCALE (Bitfield-Mask: 0x1f) */
+#define CORDIC_CSR0_FUNC_Pos (0UL) /*!< FUNC (Bit 0) */
+#define CORDIC_CSR0_FUNC_Msk (0xfUL) /*!< FUNC (Bitfield-Mask: 0x0f) */
+/* ========================================================= ARX0 ========================================================== */
+#define CORDIC_ARX0_ARGRESX_Pos (0UL) /*!< ARGRESX (Bit 0) */
+#define CORDIC_ARX0_ARGRESX_Msk (0xffffffffUL) /*!< ARGRESX (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ARY0 ========================================================== */
+#define CORDIC_ARY0_ARGRESY_Pos (0UL) /*!< ARGRESY (Bit 0) */
+#define CORDIC_ARY0_ARGRESY_Msk (0xffffffffUL) /*!< ARGRESY (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= CSR1 ========================================================== */
+#define CORDIC_CSR1_RRDY_Pos (31UL) /*!< RRDY (Bit 31) */
+#define CORDIC_CSR1_RRDY_Msk (0x80000000UL) /*!< RRDY (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_ERR_Pos (30UL) /*!< ERR (Bit 30) */
+#define CORDIC_CSR1_ERR_Msk (0x40000000UL) /*!< ERR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_RRDYCLR_Pos (29UL) /*!< RRDYCLR (Bit 29) */
+#define CORDIC_CSR1_RRDYCLR_Msk (0x20000000UL) /*!< RRDYCLR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_ERRCLR_Pos (28UL) /*!< ERRCLR (Bit 28) */
+#define CORDIC_CSR1_ERRCLR_Msk (0x10000000UL) /*!< ERRCLR (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_ARGSIZE_Pos (22UL) /*!< ARGSIZE (Bit 22) */
+#define CORDIC_CSR1_ARGSIZE_Msk (0x400000UL) /*!< ARGSIZE (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_RESSIZE_Pos (21UL) /*!< RESSIZE (Bit 21) */
+#define CORDIC_CSR1_RESSIZE_Msk (0x200000UL) /*!< RESSIZE (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_NARGS_Pos (20UL) /*!< NARGS (Bit 20) */
+#define CORDIC_CSR1_NARGS_Msk (0x100000UL) /*!< NARGS (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_NRES_Pos (19UL) /*!< NRES (Bit 19) */
+#define CORDIC_CSR1_NRES_Msk (0x80000UL) /*!< NRES (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_ERRIEN_Pos (17UL) /*!< ERRIEN (Bit 17) */
+#define CORDIC_CSR1_ERRIEN_Msk (0x20000UL) /*!< ERRIEN (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_RRDYIEN_Pos (16UL) /*!< RRDYIEN (Bit 16) */
+#define CORDIC_CSR1_RRDYIEN_Msk (0x10000UL) /*!< RRDYIEN (Bitfield-Mask: 0x01) */
+#define CORDIC_CSR1_SCALE_Pos (8UL) /*!< SCALE (Bit 8) */
+#define CORDIC_CSR1_SCALE_Msk (0x1f00UL) /*!< SCALE (Bitfield-Mask: 0x1f) */
+#define CORDIC_CSR1_FUNC_Pos (0UL) /*!< FUNC (Bit 0) */
+#define CORDIC_CSR1_FUNC_Msk (0xfUL) /*!< FUNC (Bitfield-Mask: 0x0f) */
+/* ========================================================= ARX1 ========================================================== */
+#define CORDIC_ARX1_ARGRESX_Pos (0UL) /*!< ARGRESX (Bit 0) */
+#define CORDIC_ARX1_ARGRESX_Msk (0xffffffffUL) /*!< ARGRESX (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= ARY1 ========================================================== */
+#define CORDIC_ARY1_ARGRESY_Pos (0UL) /*!< ARGRESY (Bit 0) */
+#define CORDIC_ARY1_ARGRESY_Msk (0xffffffffUL) /*!< ARGRESY (Bitfield-Mask: 0xffffffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP0_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP0_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP0_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP0_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP0_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP0_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP0_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP0_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP0_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP0_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP0_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP0_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP0_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP0_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP0_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP0_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP0_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP0_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP0_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP0_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP0_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP0_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP0_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP0_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP0_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP0_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP0_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP0_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP1_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP1_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP1_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP1_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP1_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP1_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP1_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP1_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP1_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP1_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP1_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP1_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP1_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP1_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP1_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP1_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP1_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP1_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP1_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP1_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP1_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP1_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP1_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP1_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP1_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP1_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP1_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP1_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP2_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP2_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP2_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP2_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP2_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP2_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP2_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP2_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP2_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP2_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP2_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP2_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP2_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP2_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP2_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP2_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP2_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP2_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP2_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP2_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP2_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP2_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP2_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP2_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP2_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP2_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP2_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP2_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP3_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP3_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP3_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP3_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP3_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP3_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP3_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP3_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP3_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP3_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP3_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP3_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP3_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP3_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP3_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP3_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP3_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP3_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP3_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP3_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP3_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP3_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP3_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP3_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP3_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP3_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP3_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP3_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP4 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP4_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP4_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP4_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP4_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP4_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP4_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP4_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP4_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP4_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP4_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP4_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP4_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP4_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP4_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP4_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP4_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP4_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP4_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP4_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP4_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP4_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP4_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP4_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP4_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP4_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP4_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP4_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP4_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP5 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP5_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP5_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP5_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP5_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP5_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP5_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP5_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP5_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP5_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP5_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP5_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP5_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP5_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP5_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP5_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP5_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP5_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP5_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP5_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP5_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP5_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP5_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP5_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP5_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP5_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP5_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP5_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP5_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP6 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP6_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP6_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP6_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP6_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP6_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP6_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP6_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP6_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP6_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP6_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP6_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP6_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP6_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP6_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP6_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP6_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP6_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP6_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP6_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP6_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP6_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP6_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP6_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP6_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP6_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP6_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP6_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP6_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP7 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP7_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP7_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP7_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP7_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP7_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP7_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP7_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP7_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP7_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP7_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP7_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP7_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP7_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP7_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP7_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP7_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP7_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP7_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP7_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP7_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP7_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP7_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP7_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP7_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP7_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP7_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP7_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP7_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CMP8 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define CMP8_CR_OPOL_Pos (12UL) /*!< OPOL (Bit 12) */
+#define CMP8_CR_OPOL_Msk (0x1000UL) /*!< OPOL (Bitfield-Mask: 0x01) */
+#define CMP8_CR_ODEB_Pos (11UL) /*!< ODEB (Bit 11) */
+#define CMP8_CR_ODEB_Msk (0x800UL) /*!< ODEB (Bitfield-Mask: 0x01) */
+#define CMP8_CR_BLANKING_Pos (8UL) /*!< BLANKING (Bit 8) */
+#define CMP8_CR_BLANKING_Msk (0x700UL) /*!< BLANKING (Bitfield-Mask: 0x07) */
+#define CMP8_CR_INM_Pos (6UL) /*!< INM (Bit 6) */
+#define CMP8_CR_INM_Msk (0xc0UL) /*!< INM (Bitfield-Mask: 0x03) */
+#define CMP8_CR_HYST_Pos (4UL) /*!< HYST (Bit 4) */
+#define CMP8_CR_HYST_Msk (0x30UL) /*!< HYST (Bitfield-Mask: 0x03) */
+#define CMP8_CR_INP_Pos (3UL) /*!< INP (Bit 3) */
+#define CMP8_CR_INP_Msk (0x8UL) /*!< INP (Bitfield-Mask: 0x01) */
+#define CMP8_CR_CBLK_Pos (2UL) /*!< CBLK (Bit 2) */
+#define CMP8_CR_CBLK_Msk (0x4UL) /*!< CBLK (Bitfield-Mask: 0x01) */
+#define CMP8_CR_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define CMP8_CR_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================= DEBR ========================================================== */
+#define CMP8_DEBR_DEB_Pos (0UL) /*!< DEB (Bit 0) */
+#define CMP8_DEBR_DEB_Msk (0xffUL) /*!< DEB (Bitfield-Mask: 0xff) */
+/* ========================================================== IER ========================================================== */
+#define CMP8_IER_FALIE_Pos (1UL) /*!< FALIE (Bit 1) */
+#define CMP8_IER_FALIE_Msk (0x2UL) /*!< FALIE (Bitfield-Mask: 0x01) */
+#define CMP8_IER_RISIE_Pos (0UL) /*!< RISIE (Bit 0) */
+#define CMP8_IER_RISIE_Msk (0x1UL) /*!< RISIE (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define CMP8_ISR_OVAL_Pos (2UL) /*!< OVAL (Bit 2) */
+#define CMP8_ISR_OVAL_Msk (0x4UL) /*!< OVAL (Bitfield-Mask: 0x01) */
+#define CMP8_ISR_FAL_Pos (1UL) /*!< FAL (Bit 1) */
+#define CMP8_ISR_FAL_Msk (0x2UL) /*!< FAL (Bitfield-Mask: 0x01) */
+#define CMP8_ISR_RIS_Pos (0UL) /*!< RIS (Bit 0) */
+#define CMP8_ISR_RIS_Msk (0x1UL) /*!< RIS (Bitfield-Mask: 0x01) */
+
+
+/* =========================================================================================================================== */
+/* ================ CAN0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CTRL ========================================================== */
+#define CAN0_CTRL_AFWL_Pos (28UL) /*!< AFWL (Bit 28) */
+#define CAN0_CTRL_AFWL_Msk (0xf0000000UL) /*!< AFWL (Bitfield-Mask: 0x0f) */
+#define CAN0_CTRL_EWL_Pos (24UL) /*!< EWL (Bit 24) */
+#define CAN0_CTRL_EWL_Msk (0xf000000UL) /*!< EWL (Bitfield-Mask: 0x0f) */
+#define CAN0_CTRL_EREL_Pos (22UL) /*!< EREL (Bit 22) */
+#define CAN0_CTRL_EREL_Msk (0x400000UL) /*!< EREL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_SREL_Pos (21UL) /*!< SREL (Bit 21) */
+#define CAN0_CTRL_SREL_Msk (0x200000UL) /*!< SREL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_RREL_Pos (20UL) /*!< RREL (Bit 20) */
+#define CAN0_CTRL_RREL_Msk (0x100000UL) /*!< RREL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_FD_EN_Pos (18UL) /*!< FD_EN (Bit 18) */
+#define CAN0_CTRL_FD_EN_Msk (0x40000UL) /*!< FD_EN (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_FD_ISO_Pos (17UL) /*!< FD_ISO (Bit 17) */
+#define CAN0_CTRL_FD_ISO_Msk (0x20000UL) /*!< FD_ISO (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TSNEXT_Pos (16UL) /*!< TSNEXT (Bit 16) */
+#define CAN0_CTRL_TSNEXT_Msk (0x10000UL) /*!< TSNEXT (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_PEDT_Pos (15UL) /*!< PEDT (Bit 15) */
+#define CAN0_CTRL_PEDT_Msk (0x8000UL) /*!< PEDT (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_MUXSEL_Pos (13UL) /*!< MUXSEL (Bit 13) */
+#define CAN0_CTRL_MUXSEL_Msk (0x2000UL) /*!< MUXSEL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TBSEL_Pos (12UL) /*!< TBSEL (Bit 12) */
+#define CAN0_CTRL_TBSEL_Msk (0x1000UL) /*!< TBSEL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_LOM_Pos (11UL) /*!< LOM (Bit 11) */
+#define CAN0_CTRL_LOM_Msk (0x800UL) /*!< LOM (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TPE_Pos (9UL) /*!< TPE (Bit 9) */
+#define CAN0_CTRL_TPE_Msk (0x200UL) /*!< TPE (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TPA_Pos (8UL) /*!< TPA (Bit 8) */
+#define CAN0_CTRL_TPA_Msk (0x100UL) /*!< TPA (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TSONE_Pos (7UL) /*!< TSONE (Bit 7) */
+#define CAN0_CTRL_TSONE_Msk (0x80UL) /*!< TSONE (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TSALL_Pos (6UL) /*!< TSALL (Bit 6) */
+#define CAN0_CTRL_TSALL_Msk (0x40UL) /*!< TSALL (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TSA_Pos (5UL) /*!< TSA (Bit 5) */
+#define CAN0_CTRL_TSA_Msk (0x20UL) /*!< TSA (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_RESET_Pos (4UL) /*!< RESET (Bit 4) */
+#define CAN0_CTRL_RESET_Msk (0x10UL) /*!< RESET (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_LBME_Pos (3UL) /*!< LBME (Bit 3) */
+#define CAN0_CTRL_LBME_Msk (0x8UL) /*!< LBME (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_LBMI_Pos (2UL) /*!< LBMI (Bit 2) */
+#define CAN0_CTRL_LBMI_Msk (0x4UL) /*!< LBMI (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TPSS_Pos (1UL) /*!< TPSS (Bit 1) */
+#define CAN0_CTRL_TPSS_Msk (0x2UL) /*!< TPSS (Bitfield-Mask: 0x01) */
+#define CAN0_CTRL_TSSS_Pos (0UL) /*!< TSSS (Bit 0) */
+#define CAN0_CTRL_TSSS_Msk (0x1UL) /*!< TSSS (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define CAN0_STATUS_SAFWL_Pos (28UL) /*!< SAFWL (Bit 28) */
+#define CAN0_STATUS_SAFWL_Msk (0xf0000000UL) /*!< SAFWL (Bitfield-Mask: 0x0f) */
+#define CAN0_STATUS_EAFWL_Pos (24UL) /*!< EAFWL (Bit 24) */
+#define CAN0_STATUS_EAFWL_Msk (0xf000000UL) /*!< EAFWL (Bitfield-Mask: 0x0f) */
+#define CAN0_STATUS_AEWL_Pos (20UL) /*!< AEWL (Bit 20) */
+#define CAN0_STATUS_AEWL_Msk (0xf00000UL) /*!< AEWL (Bitfield-Mask: 0x0f) */
+#define CAN0_STATUS_ROV_Pos (18UL) /*!< ROV (Bit 18) */
+#define CAN0_STATUS_ROV_Msk (0x40000UL) /*!< ROV (Bitfield-Mask: 0x01) */
+#define CAN0_STATUS_RSTAT_Pos (16UL) /*!< RSTAT (Bit 16) */
+#define CAN0_STATUS_RSTAT_Msk (0x30000UL) /*!< RSTAT (Bitfield-Mask: 0x03) */
+#define CAN0_STATUS_SOV_Pos (15UL) /*!< SOV (Bit 15) */
+#define CAN0_STATUS_SOV_Msk (0x8000UL) /*!< SOV (Bitfield-Mask: 0x01) */
+#define CAN0_STATUS_SSTAT_Pos (13UL) /*!< SSTAT (Bit 13) */
+#define CAN0_STATUS_SSTAT_Msk (0x6000UL) /*!< SSTAT (Bitfield-Mask: 0x03) */
+#define CAN0_STATUS_TSSTAT_Pos (8UL) /*!< TSSTAT (Bit 8) */
+#define CAN0_STATUS_TSSTAT_Msk (0x1f00UL) /*!< TSSTAT (Bitfield-Mask: 0x1f) */
+#define CAN0_STATUS_EOV_Pos (7UL) /*!< EOV (Bit 7) */
+#define CAN0_STATUS_EOV_Msk (0x80UL) /*!< EOV (Bitfield-Mask: 0x01) */
+#define CAN0_STATUS_ESTAT_Pos (5UL) /*!< ESTAT (Bit 5) */
+#define CAN0_STATUS_ESTAT_Msk (0x60UL) /*!< ESTAT (Bitfield-Mask: 0x03) */
+#define CAN0_STATUS_RACTIVE_Pos (2UL) /*!< RACTIVE (Bit 2) */
+#define CAN0_STATUS_RACTIVE_Msk (0x4UL) /*!< RACTIVE (Bitfield-Mask: 0x01) */
+#define CAN0_STATUS_TACTIVE_Pos (1UL) /*!< TACTIVE (Bit 1) */
+#define CAN0_STATUS_TACTIVE_Msk (0x2UL) /*!< TACTIVE (Bitfield-Mask: 0x01) */
+#define CAN0_STATUS_BUSOFF_Pos (0UL) /*!< BUSOFF (Bit 0) */
+#define CAN0_STATUS_BUSOFF_Msk (0x1UL) /*!< BUSOFF (Bitfield-Mask: 0x01) */
+/* ======================================================== INTREN ========================================================= */
+#define CAN0_INTREN_TEIE_Pos (31UL) /*!< TEIE (Bit 31) */
+#define CAN0_INTREN_TEIE_Msk (0x80000000UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_TAEIE_Pos (30UL) /*!< TAEIE (Bit 30) */
+#define CAN0_INTREN_TAEIE_Msk (0x40000000UL) /*!< TAEIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_PMIE_Pos (29UL) /*!< PMIE (Bit 29) */
+#define CAN0_INTREN_PMIE_Msk (0x20000000UL) /*!< PMIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_TSCIE_Pos (28UL) /*!< TSCIE (Bit 28) */
+#define CAN0_INTREN_TSCIE_Msk (0x10000000UL) /*!< TSCIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_RTOIE_Pos (27UL) /*!< RTOIE (Bit 27) */
+#define CAN0_INTREN_RTOIE_Msk (0x8000000UL) /*!< RTOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_STOIE_Pos (26UL) /*!< STOIE (Bit 26) */
+#define CAN0_INTREN_STOIE_Msk (0x4000000UL) /*!< STOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_ETOIE_Pos (25UL) /*!< ETOIE (Bit 25) */
+#define CAN0_INTREN_ETOIE_Msk (0x2000000UL) /*!< ETOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_CTOIE_Pos (24UL) /*!< CTOIE (Bit 24) */
+#define CAN0_INTREN_CTOIE_Msk (0x1000000UL) /*!< CTOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_SOIE_Pos (23UL) /*!< SOIE (Bit 23) */
+#define CAN0_INTREN_SOIE_Msk (0x800000UL) /*!< SOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_SFIE_Pos (22UL) /*!< SFIE (Bit 22) */
+#define CAN0_INTREN_SFIE_Msk (0x400000UL) /*!< SFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_SAFIE_Pos (21UL) /*!< SAFIE (Bit 21) */
+#define CAN0_INTREN_SAFIE_Msk (0x200000UL) /*!< SAFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_EOIE_Pos (20UL) /*!< EOIE (Bit 20) */
+#define CAN0_INTREN_EOIE_Msk (0x100000UL) /*!< EOIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_EFIE_Pos (19UL) /*!< EFIE (Bit 19) */
+#define CAN0_INTREN_EFIE_Msk (0x80000UL) /*!< EFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_EAFIE_Pos (18UL) /*!< EAFIE (Bit 18) */
+#define CAN0_INTREN_EAFIE_Msk (0x40000UL) /*!< EAFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_AIE_Pos (17UL) /*!< AIE (Bit 17) */
+#define CAN0_INTREN_AIE_Msk (0x20000UL) /*!< AIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_SRIE_Pos (13UL) /*!< SRIE (Bit 13) */
+#define CAN0_INTREN_SRIE_Msk (0x2000UL) /*!< SRIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_ERIE_Pos (12UL) /*!< ERIE (Bit 12) */
+#define CAN0_INTREN_ERIE_Msk (0x1000UL) /*!< ERIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_ECIE_Pos (11UL) /*!< ECIE (Bit 11) */
+#define CAN0_INTREN_ECIE_Msk (0x800UL) /*!< ECIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */
+#define CAN0_INTREN_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_ALIE_Pos (9UL) /*!< ALIE (Bit 9) */
+#define CAN0_INTREN_ALIE_Msk (0x200UL) /*!< ALIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */
+#define CAN0_INTREN_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_RIE_Pos (7UL) /*!< RIE (Bit 7) */
+#define CAN0_INTREN_RIE_Msk (0x80UL) /*!< RIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_ROIE_Pos (6UL) /*!< ROIE (Bit 6) */
+#define CAN0_INTREN_ROIE_Msk (0x40UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_RFIE_Pos (5UL) /*!< RFIE (Bit 5) */
+#define CAN0_INTREN_RFIE_Msk (0x20UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_RAFIE_Pos (4UL) /*!< RAFIE (Bit 4) */
+#define CAN0_INTREN_RAFIE_Msk (0x10UL) /*!< RAFIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_TPIE_Pos (3UL) /*!< TPIE (Bit 3) */
+#define CAN0_INTREN_TPIE_Msk (0x8UL) /*!< TPIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_TSIE_Pos (2UL) /*!< TSIE (Bit 2) */
+#define CAN0_INTREN_TSIE_Msk (0x4UL) /*!< TSIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_EIE_Pos (1UL) /*!< EIE (Bit 1) */
+#define CAN0_INTREN_EIE_Msk (0x2UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define CAN0_INTREN_TSFF_Pos (0UL) /*!< TSFF (Bit 0) */
+#define CAN0_INTREN_TSFF_Msk (0x1UL) /*!< TSFF (Bitfield-Mask: 0x01) */
+/* ======================================================== INTRST ========================================================= */
+#define CAN0_INTRST_TEIF_Pos (31UL) /*!< TEIF (Bit 31) */
+#define CAN0_INTRST_TEIF_Msk (0x80000000UL) /*!< TEIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_TAEIF_Pos (30UL) /*!< TAEIF (Bit 30) */
+#define CAN0_INTRST_TAEIF_Msk (0x40000000UL) /*!< TAEIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_PMIF_Pos (29UL) /*!< PMIF (Bit 29) */
+#define CAN0_INTRST_PMIF_Msk (0x20000000UL) /*!< PMIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_TSCIF_Pos (28UL) /*!< TSCIF (Bit 28) */
+#define CAN0_INTRST_TSCIF_Msk (0x10000000UL) /*!< TSCIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_RTOIF_Pos (27UL) /*!< RTOIF (Bit 27) */
+#define CAN0_INTRST_RTOIF_Msk (0x8000000UL) /*!< RTOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_STOIF_Pos (26UL) /*!< STOIF (Bit 26) */
+#define CAN0_INTRST_STOIF_Msk (0x4000000UL) /*!< STOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_ETOIF_Pos (25UL) /*!< ETOIF (Bit 25) */
+#define CAN0_INTRST_ETOIF_Msk (0x2000000UL) /*!< ETOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_CTOIF_Pos (24UL) /*!< CTOIF (Bit 24) */
+#define CAN0_INTRST_CTOIF_Msk (0x1000000UL) /*!< CTOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_SOIF_Pos (23UL) /*!< SOIF (Bit 23) */
+#define CAN0_INTRST_SOIF_Msk (0x800000UL) /*!< SOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_SFIF_Pos (22UL) /*!< SFIF (Bit 22) */
+#define CAN0_INTRST_SFIF_Msk (0x400000UL) /*!< SFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_SAFIF_Pos (21UL) /*!< SAFIF (Bit 21) */
+#define CAN0_INTRST_SAFIF_Msk (0x200000UL) /*!< SAFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EOIF_Pos (20UL) /*!< EOIF (Bit 20) */
+#define CAN0_INTRST_EOIF_Msk (0x100000UL) /*!< EOIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EFIF_Pos (19UL) /*!< EFIF (Bit 19) */
+#define CAN0_INTRST_EFIF_Msk (0x80000UL) /*!< EFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EAFIF_Pos (18UL) /*!< EAFIF (Bit 18) */
+#define CAN0_INTRST_EAFIF_Msk (0x40000UL) /*!< EAFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EWARN_Pos (17UL) /*!< EWARN (Bit 17) */
+#define CAN0_INTRST_EWARN_Msk (0x20000UL) /*!< EWARN (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EPASS_Pos (16UL) /*!< EPASS (Bit 16) */
+#define CAN0_INTRST_EPASS_Msk (0x10000UL) /*!< EPASS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_SRIF_Pos (13UL) /*!< SRIF (Bit 13) */
+#define CAN0_INTRST_SRIF_Msk (0x2000UL) /*!< SRIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_ERIF_Pos (12UL) /*!< ERIF (Bit 12) */
+#define CAN0_INTRST_ERIF_Msk (0x1000UL) /*!< ERIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_ECIF_Pos (11UL) /*!< ECIF (Bit 11) */
+#define CAN0_INTRST_ECIF_Msk (0x800UL) /*!< ECIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EPIF_Pos (10UL) /*!< EPIF (Bit 10) */
+#define CAN0_INTRST_EPIF_Msk (0x400UL) /*!< EPIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_ALIF_Pos (9UL) /*!< ALIF (Bit 9) */
+#define CAN0_INTRST_ALIF_Msk (0x200UL) /*!< ALIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_BEIF_Pos (8UL) /*!< BEIF (Bit 8) */
+#define CAN0_INTRST_BEIF_Msk (0x100UL) /*!< BEIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_RIF_Pos (7UL) /*!< RIF (Bit 7) */
+#define CAN0_INTRST_RIF_Msk (0x80UL) /*!< RIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_ROIF_Pos (6UL) /*!< ROIF (Bit 6) */
+#define CAN0_INTRST_ROIF_Msk (0x40UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_RFIF_Pos (5UL) /*!< RFIF (Bit 5) */
+#define CAN0_INTRST_RFIF_Msk (0x20UL) /*!< RFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_RAFIF_Pos (4UL) /*!< RAFIF (Bit 4) */
+#define CAN0_INTRST_RAFIF_Msk (0x10UL) /*!< RAFIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_TPIF_Pos (3UL) /*!< TPIF (Bit 3) */
+#define CAN0_INTRST_TPIF_Msk (0x8UL) /*!< TPIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_TSIF_Pos (2UL) /*!< TSIF (Bit 2) */
+#define CAN0_INTRST_TSIF_Msk (0x4UL) /*!< TSIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_EIF_Pos (1UL) /*!< EIF (Bit 1) */
+#define CAN0_INTRST_EIF_Msk (0x2UL) /*!< EIF (Bitfield-Mask: 0x01) */
+#define CAN0_INTRST_AIF_Pos (0UL) /*!< AIF (Bit 0) */
+#define CAN0_INTRST_AIF_Msk (0x1UL) /*!< AIF (Bitfield-Mask: 0x01) */
+/* ======================================================== BITTIME ======================================================== */
+#define CAN0_BITTIME_F_SEG1_Pos (20UL) /*!< F_SEG1 (Bit 20) */
+#define CAN0_BITTIME_F_SEG1_Msk (0xf00000UL) /*!< F_SEG1 (Bitfield-Mask: 0x0f) */
+#define CAN0_BITTIME_S_SJW_Pos (16UL) /*!< S_SJW (Bit 16) */
+#define CAN0_BITTIME_S_SJW_Msk (0xf0000UL) /*!< S_SJW (Bitfield-Mask: 0x0f) */
+#define CAN0_BITTIME_F_SEG2_Pos (13UL) /*!< F_SEG2 (Bit 13) */
+#define CAN0_BITTIME_F_SEG2_Msk (0xe000UL) /*!< F_SEG2 (Bitfield-Mask: 0x07) */
+#define CAN0_BITTIME_S_SEG2_Pos (8UL) /*!< S_SEG2 (Bit 8) */
+#define CAN0_BITTIME_S_SEG2_Msk (0x1f00UL) /*!< S_SEG2 (Bitfield-Mask: 0x1f) */
+#define CAN0_BITTIME_F_SJW_Pos (6UL) /*!< F_SJW (Bit 6) */
+#define CAN0_BITTIME_F_SJW_Msk (0xc0UL) /*!< F_SJW (Bitfield-Mask: 0x03) */
+#define CAN0_BITTIME_S_SEG1_Pos (0UL) /*!< S_SEG1 (Bit 0) */
+#define CAN0_BITTIME_S_SEG1_Msk (0x3fUL) /*!< S_SEG1 (Bitfield-Mask: 0x3f) */
+/* ========================================================= PRESC ========================================================= */
+#define CAN0_PRESC_TDCEN_Pos (23UL) /*!< TDCEN (Bit 23) */
+#define CAN0_PRESC_TDCEN_Msk (0x800000UL) /*!< TDCEN (Bitfield-Mask: 0x01) */
+#define CAN0_PRESC_SSPOFF_Pos (16UL) /*!< SSPOFF (Bit 16) */
+#define CAN0_PRESC_SSPOFF_Msk (0x1f0000UL) /*!< SSPOFF (Bitfield-Mask: 0x1f) */
+#define CAN0_PRESC_F_PRESC_Pos (8UL) /*!< F_PRESC (Bit 8) */
+#define CAN0_PRESC_F_PRESC_Msk (0xff00UL) /*!< F_PRESC (Bitfield-Mask: 0xff) */
+#define CAN0_PRESC_S_PRESC_Pos (0UL) /*!< S_PRESC (Bit 0) */
+#define CAN0_PRESC_S_PRESC_Msk (0xffUL) /*!< S_PRESC (Bitfield-Mask: 0xff) */
+/* ========================================================= ERRST ========================================================= */
+#define CAN0_ERRST_RECNT_Pos (24UL) /*!< RECNT (Bit 24) */
+#define CAN0_ERRST_RECNT_Msk (0xff000000UL) /*!< RECNT (Bitfield-Mask: 0xff) */
+#define CAN0_ERRST_TECNT_Pos (16UL) /*!< TECNT (Bit 16) */
+#define CAN0_ERRST_TECNT_Msk (0xff0000UL) /*!< TECNT (Bitfield-Mask: 0xff) */
+#define CAN0_ERRST_ECNT_Pos (8UL) /*!< ECNT (Bit 8) */
+#define CAN0_ERRST_ECNT_Msk (0xff00UL) /*!< ECNT (Bitfield-Mask: 0xff) */
+#define CAN0_ERRST_KOER_Pos (5UL) /*!< KOER (Bit 5) */
+#define CAN0_ERRST_KOER_Msk (0xe0UL) /*!< KOER (Bitfield-Mask: 0x07) */
+#define CAN0_ERRST_ALC_Pos (0UL) /*!< ALC (Bit 0) */
+#define CAN0_ERRST_ALC_Msk (0x1fUL) /*!< ALC (Bitfield-Mask: 0x1f) */
+/* ========================================================= PRTST ========================================================= */
+#define CAN0_PRTST_DKOER_Pos (8UL) /*!< DKOER (Bit 8) */
+#define CAN0_PRTST_DKOER_Msk (0x700UL) /*!< DKOER (Bitfield-Mask: 0x07) */
+#define CAN0_PRTST_FDSTS_Pos (4UL) /*!< FDSTS (Bit 4) */
+#define CAN0_PRTST_FDSTS_Msk (0xf0UL) /*!< FDSTS (Bitfield-Mask: 0x0f) */
+#define CAN0_PRTST_NDSTS_Pos (2UL) /*!< NDSTS (Bit 2) */
+#define CAN0_PRTST_NDSTS_Msk (0xcUL) /*!< NDSTS (Bitfield-Mask: 0x03) */
+#define CAN0_PRTST_RBSTS_Pos (0UL) /*!< RBSTS (Bit 0) */
+#define CAN0_PRTST_RBSTS_Msk (0x3UL) /*!< RBSTS (Bitfield-Mask: 0x03) */
+/* ======================================================== INTRLS ========================================================= */
+#define CAN0_INTRLS_TEILS_Pos (31UL) /*!< TEILS (Bit 31) */
+#define CAN0_INTRLS_TEILS_Msk (0x80000000UL) /*!< TEILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_TAEILS_Pos (30UL) /*!< TAEILS (Bit 30) */
+#define CAN0_INTRLS_TAEILS_Msk (0x40000000UL) /*!< TAEILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_PMILS_Pos (29UL) /*!< PMILS (Bit 29) */
+#define CAN0_INTRLS_PMILS_Msk (0x20000000UL) /*!< PMILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_TSCILS_Pos (28UL) /*!< TSCILS (Bit 28) */
+#define CAN0_INTRLS_TSCILS_Msk (0x10000000UL) /*!< TSCILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_RTOILS_Pos (27UL) /*!< RTOILS (Bit 27) */
+#define CAN0_INTRLS_RTOILS_Msk (0x8000000UL) /*!< RTOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_STOILS_Pos (26UL) /*!< STOILS (Bit 26) */
+#define CAN0_INTRLS_STOILS_Msk (0x4000000UL) /*!< STOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_ETOILS_Pos (25UL) /*!< ETOILS (Bit 25) */
+#define CAN0_INTRLS_ETOILS_Msk (0x2000000UL) /*!< ETOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_CTOILS_Pos (24UL) /*!< CTOILS (Bit 24) */
+#define CAN0_INTRLS_CTOILS_Msk (0x1000000UL) /*!< CTOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_SOILS_Pos (23UL) /*!< SOILS (Bit 23) */
+#define CAN0_INTRLS_SOILS_Msk (0x800000UL) /*!< SOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_SFILS_Pos (22UL) /*!< SFILS (Bit 22) */
+#define CAN0_INTRLS_SFILS_Msk (0x400000UL) /*!< SFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_SAFILS_Pos (21UL) /*!< SAFILS (Bit 21) */
+#define CAN0_INTRLS_SAFILS_Msk (0x200000UL) /*!< SAFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_EOILS_Pos (20UL) /*!< EOILS (Bit 20) */
+#define CAN0_INTRLS_EOILS_Msk (0x100000UL) /*!< EOILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_EFILS_Pos (19UL) /*!< EFILS (Bit 19) */
+#define CAN0_INTRLS_EFILS_Msk (0x80000UL) /*!< EFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_EAFILS_Pos (18UL) /*!< EAFILS (Bit 18) */
+#define CAN0_INTRLS_EAFILS_Msk (0x40000UL) /*!< EAFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_SRILS_Pos (13UL) /*!< SRILS (Bit 13) */
+#define CAN0_INTRLS_SRILS_Msk (0x2000UL) /*!< SRILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_ERILS_Pos (12UL) /*!< ERILS (Bit 12) */
+#define CAN0_INTRLS_ERILS_Msk (0x1000UL) /*!< ERILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_ECILS_Pos (11UL) /*!< ECILS (Bit 11) */
+#define CAN0_INTRLS_ECILS_Msk (0x800UL) /*!< ECILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_EPILS_Pos (10UL) /*!< EPILS (Bit 10) */
+#define CAN0_INTRLS_EPILS_Msk (0x400UL) /*!< EPILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_ALILS_Pos (9UL) /*!< ALILS (Bit 9) */
+#define CAN0_INTRLS_ALILS_Msk (0x200UL) /*!< ALILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_BEILS_Pos (8UL) /*!< BEILS (Bit 8) */
+#define CAN0_INTRLS_BEILS_Msk (0x100UL) /*!< BEILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_RILS_Pos (7UL) /*!< RILS (Bit 7) */
+#define CAN0_INTRLS_RILS_Msk (0x80UL) /*!< RILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_ROILS_Pos (6UL) /*!< ROILS (Bit 6) */
+#define CAN0_INTRLS_ROILS_Msk (0x40UL) /*!< ROILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_RFILS_Pos (5UL) /*!< RFILS (Bit 5) */
+#define CAN0_INTRLS_RFILS_Msk (0x20UL) /*!< RFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_RAFILS_Pos (4UL) /*!< RAFILS (Bit 4) */
+#define CAN0_INTRLS_RAFILS_Msk (0x10UL) /*!< RAFILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_TPILS_Pos (3UL) /*!< TPILS (Bit 3) */
+#define CAN0_INTRLS_TPILS_Msk (0x8UL) /*!< TPILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_TSILS_Pos (2UL) /*!< TSILS (Bit 2) */
+#define CAN0_INTRLS_TSILS_Msk (0x4UL) /*!< TSILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_EILS_Pos (1UL) /*!< EILS (Bit 1) */
+#define CAN0_INTRLS_EILS_Msk (0x2UL) /*!< EILS (Bitfield-Mask: 0x01) */
+#define CAN0_INTRLS_AILS_Pos (0UL) /*!< AILS (Bit 0) */
+#define CAN0_INTRLS_AILS_Msk (0x1UL) /*!< AILS (Bitfield-Mask: 0x01) */
+/* ========================================================= GFCR ========================================================== */
+#define CAN0_GFCR_SRFR_Pos (7UL) /*!< SRFR (Bit 7) */
+#define CAN0_GFCR_SRFR_Msk (0x80UL) /*!< SRFR (Bitfield-Mask: 0x01) */
+#define CAN0_GFCR_ERFR_Pos (6UL) /*!< ERFR (Bit 6) */
+#define CAN0_GFCR_ERFR_Msk (0x40UL) /*!< ERFR (Bitfield-Mask: 0x01) */
+#define CAN0_GFCR_PRBM_Pos (1UL) /*!< PRBM (Bit 1) */
+#define CAN0_GFCR_PRBM_Msk (0x2UL) /*!< PRBM (Bitfield-Mask: 0x01) */
+#define CAN0_GFCR_SRBM_Pos (0UL) /*!< SRBM (Bit 0) */
+#define CAN0_GFCR_SRBM_Msk (0x1UL) /*!< SRBM (Bitfield-Mask: 0x01) */
+/* ========================================================= EMCR ========================================================== */
+#define CAN0_EMCR_EIDM_Pos (0UL) /*!< EIDM (Bit 0) */
+#define CAN0_EMCR_EIDM_Msk (0x1fffffffUL) /*!< EIDM (Bitfield-Mask: 0x1fffffff) */
+/* ========================================================= PMST ========================================================== */
+#define CAN0_PMST_PMAS_Pos (4UL) /*!< PMAS (Bit 4) */
+#define CAN0_PMST_PMAS_Msk (0xf0UL) /*!< PMAS (Bitfield-Mask: 0x0f) */
+#define CAN0_PMST_PMBS_Pos (1UL) /*!< PMBS (Bit 1) */
+#define CAN0_PMST_PMBS_Msk (0x6UL) /*!< PMBS (Bitfield-Mask: 0x03) */
+#define CAN0_PMST_PMIS_Pos (0UL) /*!< PMIS (Bit 0) */
+#define CAN0_PMST_PMIS_Msk (0x1UL) /*!< PMIS (Bitfield-Mask: 0x01) */
+/* ========================================================= ACFEN ========================================================= */
+#define CAN0_ACFEN_AE15_Pos (15UL) /*!< AE15 (Bit 15) */
+#define CAN0_ACFEN_AE15_Msk (0x8000UL) /*!< AE15 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE14_Pos (14UL) /*!< AE14 (Bit 14) */
+#define CAN0_ACFEN_AE14_Msk (0x4000UL) /*!< AE14 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE13_Pos (13UL) /*!< AE13 (Bit 13) */
+#define CAN0_ACFEN_AE13_Msk (0x2000UL) /*!< AE13 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE12_Pos (12UL) /*!< AE12 (Bit 12) */
+#define CAN0_ACFEN_AE12_Msk (0x1000UL) /*!< AE12 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE11_Pos (11UL) /*!< AE11 (Bit 11) */
+#define CAN0_ACFEN_AE11_Msk (0x800UL) /*!< AE11 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE10_Pos (10UL) /*!< AE10 (Bit 10) */
+#define CAN0_ACFEN_AE10_Msk (0x400UL) /*!< AE10 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE9_Pos (9UL) /*!< AE9 (Bit 9) */
+#define CAN0_ACFEN_AE9_Msk (0x200UL) /*!< AE9 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE8_Pos (8UL) /*!< AE8 (Bit 8) */
+#define CAN0_ACFEN_AE8_Msk (0x100UL) /*!< AE8 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE7_Pos (7UL) /*!< AE7 (Bit 7) */
+#define CAN0_ACFEN_AE7_Msk (0x80UL) /*!< AE7 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE6_Pos (6UL) /*!< AE6 (Bit 6) */
+#define CAN0_ACFEN_AE6_Msk (0x40UL) /*!< AE6 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE5_Pos (5UL) /*!< AE5 (Bit 5) */
+#define CAN0_ACFEN_AE5_Msk (0x20UL) /*!< AE5 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE4_Pos (4UL) /*!< AE4 (Bit 4) */
+#define CAN0_ACFEN_AE4_Msk (0x10UL) /*!< AE4 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE3_Pos (3UL) /*!< AE3 (Bit 3) */
+#define CAN0_ACFEN_AE3_Msk (0x8UL) /*!< AE3 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE2_Pos (2UL) /*!< AE2 (Bit 2) */
+#define CAN0_ACFEN_AE2_Msk (0x4UL) /*!< AE2 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE1_Pos (1UL) /*!< AE1 (Bit 1) */
+#define CAN0_ACFEN_AE1_Msk (0x2UL) /*!< AE1 (Bitfield-Mask: 0x01) */
+#define CAN0_ACFEN_AE0_Pos (0UL) /*!< AE0 (Bit 0) */
+#define CAN0_ACFEN_AE0_Msk (0x1UL) /*!< AE0 (Bitfield-Mask: 0x01) */
+/* ======================================================== ACFCTRL ======================================================== */
+#define CAN0_ACFCTRL_SELMASK_Pos (5UL) /*!< SELMASK (Bit 5) */
+#define CAN0_ACFCTRL_SELMASK_Msk (0x20UL) /*!< SELMASK (Bitfield-Mask: 0x01) */
+#define CAN0_ACFCTRL_ACFADR_Pos (0UL) /*!< ACFADR (Bit 0) */
+#define CAN0_ACFCTRL_ACFADR_Msk (0xfUL) /*!< ACFADR (Bitfield-Mask: 0x0f) */
+/* ========================================================== ACF ========================================================== */
+#define CAN0_ACF_AIDEE_Pos (30UL) /*!< AIDEE (Bit 30) */
+#define CAN0_ACF_AIDEE_Msk (0x40000000UL) /*!< AIDEE (Bitfield-Mask: 0x01) */
+#define CAN0_ACF_AIDE_Pos (29UL) /*!< AIDE (Bit 29) */
+#define CAN0_ACF_AIDE_Msk (0x20000000UL) /*!< AIDE (Bitfield-Mask: 0x01) */
+#define CAN0_ACF_ACF_X_Pos (0UL) /*!< ACF_X (Bit 0) */
+#define CAN0_ACF_ACF_X_Msk (0x1fffffffUL) /*!< ACF_X (Bitfield-Mask: 0x1fffffff) */
+/* ========================================================= ACFE ========================================================== */
+#define CAN0_ACFE_ACF_M_Pos (4UL) /*!< ACF_M (Bit 4) */
+#define CAN0_ACFE_ACF_M_Msk (0xf0UL) /*!< ACF_M (Bitfield-Mask: 0x0f) */
+#define CAN0_ACFE_ACF_C_Pos (0UL) /*!< ACF_C (Bit 0) */
+#define CAN0_ACFE_ACF_C_Msk (0xfUL) /*!< ACF_C (Bitfield-Mask: 0x0f) */
+/* ======================================================== RBUFID ========================================================= */
+#define CAN0_RBUFID_RXD_ID_Pos (0UL) /*!< RXD_ID (Bit 0) */
+#define CAN0_RBUFID_RXD_ID_Msk (0xffffffffUL) /*!< RXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== RBUFCR ========================================================= */
+#define CAN0_RBUFCR_RXD_ACF_Pos (24UL) /*!< RXD_ACF (Bit 24) */
+#define CAN0_RBUFCR_RXD_ACF_Msk (0xf000000UL) /*!< RXD_ACF (Bitfield-Mask: 0x0f) */
+#define CAN0_RBUFCR_RXD_TS_Pos (8UL) /*!< RXD_TS (Bit 8) */
+#define CAN0_RBUFCR_RXD_TS_Msk (0xffff00UL) /*!< RXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN0_RBUFCR_RXD_CR_Pos (4UL) /*!< RXD_CR (Bit 4) */
+#define CAN0_RBUFCR_RXD_CR_Msk (0xf0UL) /*!< RXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN0_RBUFCR_RXD_DLC_Pos (0UL) /*!< RXD_DLC (Bit 0) */
+#define CAN0_RBUFCR_RXD_DLC_Msk (0xfUL) /*!< RXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== RBUFDT ========================================================= */
+#define CAN0_RBUFDT_RXD_BYTE3_Pos (24UL) /*!< RXD_BYTE3 (Bit 24) */
+#define CAN0_RBUFDT_RXD_BYTE3_Msk (0xff000000UL) /*!< RXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN0_RBUFDT_RXD_BYTE2_Pos (16UL) /*!< RXD_BYTE2 (Bit 16) */
+#define CAN0_RBUFDT_RXD_BYTE2_Msk (0xff0000UL) /*!< RXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN0_RBUFDT_RXD_BYTE1_Pos (8UL) /*!< RXD_BYTE1 (Bit 8) */
+#define CAN0_RBUFDT_RXD_BYTE1_Msk (0xff00UL) /*!< RXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN0_RBUFDT_RXD_BYTE0_Pos (0UL) /*!< RXD_BYTE0 (Bit 0) */
+#define CAN0_RBUFDT_RXD_BYTE0_Msk (0xffUL) /*!< RXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ======================================================== TBUFID ========================================================= */
+#define CAN0_TBUFID_TXD_ID_Pos (0UL) /*!< TXD_ID (Bit 0) */
+#define CAN0_TBUFID_TXD_ID_Msk (0xffffffffUL) /*!< TXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== TBUFCR ========================================================= */
+#define CAN0_TBUFCR_TXD_ETB_Pos (31UL) /*!< TXD_ETB (Bit 31) */
+#define CAN0_TBUFCR_TXD_ETB_Msk (0x80000000UL) /*!< TXD_ETB (Bitfield-Mask: 0x01) */
+#define CAN0_TBUFCR_TXD_MM_Pos (8UL) /*!< TXD_MM (Bit 8) */
+#define CAN0_TBUFCR_TXD_MM_Msk (0xff00UL) /*!< TXD_MM (Bitfield-Mask: 0xff) */
+#define CAN0_TBUFCR_TXD_CR_Pos (4UL) /*!< TXD_CR (Bit 4) */
+#define CAN0_TBUFCR_TXD_CR_Msk (0xf0UL) /*!< TXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN0_TBUFCR_TXD_DLC_Pos (0UL) /*!< TXD_DLC (Bit 0) */
+#define CAN0_TBUFCR_TXD_DLC_Msk (0xfUL) /*!< TXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== TBUFDT ========================================================= */
+#define CAN0_TBUFDT_TXD_BYTE3_Pos (24UL) /*!< TXD_BYTE3 (Bit 24) */
+#define CAN0_TBUFDT_TXD_BYTE3_Msk (0xff000000UL) /*!< TXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN0_TBUFDT_TXD_BYTE2_Pos (16UL) /*!< TXD_BYTE2 (Bit 16) */
+#define CAN0_TBUFDT_TXD_BYTE2_Msk (0xff0000UL) /*!< TXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN0_TBUFDT_TXD_BYTE1_Pos (8UL) /*!< TXD_BYTE1 (Bit 8) */
+#define CAN0_TBUFDT_TXD_BYTE1_Msk (0xff00UL) /*!< TXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN0_TBUFDT_TXD_BYTE0_Pos (0UL) /*!< TXD_BYTE0 (Bit 0) */
+#define CAN0_TBUFDT_TXD_BYTE0_Msk (0xffUL) /*!< TXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ======================================================== EBUFID ========================================================= */
+#define CAN0_EBUFID_TXD_ID_Pos (0UL) /*!< TXD_ID (Bit 0) */
+#define CAN0_EBUFID_TXD_ID_Msk (0xffffffffUL) /*!< TXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== EBUFDT ========================================================= */
+#define CAN0_EBUFDT_TXD_MM_Pos (24UL) /*!< TXD_MM (Bit 24) */
+#define CAN0_EBUFDT_TXD_MM_Msk (0xff000000UL) /*!< TXD_MM (Bitfield-Mask: 0xff) */
+#define CAN0_EBUFDT_TXD_TS_Pos (8UL) /*!< TXD_TS (Bit 8) */
+#define CAN0_EBUFDT_TXD_TS_Msk (0xffff00UL) /*!< TXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN0_EBUFDT_TXD_CR_Pos (4UL) /*!< TXD_CR (Bit 4) */
+#define CAN0_EBUFDT_TXD_CR_Msk (0xf0UL) /*!< TXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN0_EBUFDT_TXD_DLC_Pos (0UL) /*!< TXD_DLC (Bit 0) */
+#define CAN0_EBUFDT_TXD_DLC_Msk (0xfUL) /*!< TXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== SBUFID ========================================================= */
+#define CAN0_SBUFID_RXD_ID_Pos (0UL) /*!< RXD_ID (Bit 0) */
+#define CAN0_SBUFID_RXD_ID_Msk (0xffffffffUL) /*!< RXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== SBUFCR ========================================================= */
+#define CAN0_SBUFCR_RXD_ACF_Pos (24UL) /*!< RXD_ACF (Bit 24) */
+#define CAN0_SBUFCR_RXD_ACF_Msk (0xf000000UL) /*!< RXD_ACF (Bitfield-Mask: 0x0f) */
+#define CAN0_SBUFCR_RXD_TS_Pos (8UL) /*!< RXD_TS (Bit 8) */
+#define CAN0_SBUFCR_RXD_TS_Msk (0xffff00UL) /*!< RXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN0_SBUFCR_RXD_CR_Pos (4UL) /*!< RXD_CR (Bit 4) */
+#define CAN0_SBUFCR_RXD_CR_Msk (0xf0UL) /*!< RXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN0_SBUFCR_RXD_DLC_Pos (0UL) /*!< RXD_DLC (Bit 0) */
+#define CAN0_SBUFCR_RXD_DLC_Msk (0xfUL) /*!< RXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== SBUFDT ========================================================= */
+#define CAN0_SBUFDT_RXD_BYTE3_Pos (24UL) /*!< RXD_BYTE3 (Bit 24) */
+#define CAN0_SBUFDT_RXD_BYTE3_Msk (0xff000000UL) /*!< RXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN0_SBUFDT_RXD_BYTE2_Pos (16UL) /*!< RXD_BYTE2 (Bit 16) */
+#define CAN0_SBUFDT_RXD_BYTE2_Msk (0xff0000UL) /*!< RXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN0_SBUFDT_RXD_BYTE1_Pos (8UL) /*!< RXD_BYTE1 (Bit 8) */
+#define CAN0_SBUFDT_RXD_BYTE1_Msk (0xff00UL) /*!< RXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN0_SBUFDT_RXD_BYTE0_Pos (0UL) /*!< RXD_BYTE0 (Bit 0) */
+#define CAN0_SBUFDT_RXD_BYTE0_Msk (0xffUL) /*!< RXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ========================================================= TSCR ========================================================== */
+#define CAN0_TSCR_TSP_Pos (20UL) /*!< TSP (Bit 20) */
+#define CAN0_TSCR_TSP_Msk (0xf00000UL) /*!< TSP (Bitfield-Mask: 0x0f) */
+#define CAN0_TSCR_TSS_Pos (16UL) /*!< TSS (Bit 16) */
+#define CAN0_TSCR_TSS_Msk (0xf0000UL) /*!< TSS (Bitfield-Mask: 0x0f) */
+/* ========================================================== TSC ========================================================== */
+#define CAN0_TSC_TSC_Pos (0UL) /*!< TSC (Bit 0) */
+#define CAN0_TSC_TSC_Msk (0xffffUL) /*!< TSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= RTOP ========================================================== */
+#define CAN0_RTOP_RTOE_Pos (24UL) /*!< RTOE (Bit 24) */
+#define CAN0_RTOP_RTOE_Msk (0x1000000UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define CAN0_RTOP_RTOP_Pos (0UL) /*!< RTOP (Bit 0) */
+#define CAN0_RTOP_RTOP_Msk (0xffffUL) /*!< RTOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= RTOC ========================================================== */
+#define CAN0_RTOC_RTOC_Pos (0UL) /*!< RTOC (Bit 0) */
+#define CAN0_RTOC_RTOC_Msk (0xffffUL) /*!< RTOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= STOP ========================================================== */
+#define CAN0_STOP_STOE_Pos (24UL) /*!< STOE (Bit 24) */
+#define CAN0_STOP_STOE_Msk (0x1000000UL) /*!< STOE (Bitfield-Mask: 0x01) */
+#define CAN0_STOP_STOP_Pos (0UL) /*!< STOP (Bit 0) */
+#define CAN0_STOP_STOP_Msk (0xffffUL) /*!< STOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= STOC ========================================================== */
+#define CAN0_STOC_STOC_Pos (0UL) /*!< STOC (Bit 0) */
+#define CAN0_STOC_STOC_Msk (0xffffUL) /*!< STOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= ETOP ========================================================== */
+#define CAN0_ETOP_ETOE_Pos (24UL) /*!< ETOE (Bit 24) */
+#define CAN0_ETOP_ETOE_Msk (0x1000000UL) /*!< ETOE (Bitfield-Mask: 0x01) */
+#define CAN0_ETOP_ETOP_Pos (0UL) /*!< ETOP (Bit 0) */
+#define CAN0_ETOP_ETOP_Msk (0xffffUL) /*!< ETOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= ETOC ========================================================== */
+#define CAN0_ETOC_ETOC_Pos (0UL) /*!< ETOC (Bit 0) */
+#define CAN0_ETOC_ETOC_Msk (0xffffUL) /*!< ETOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CTOP ========================================================== */
+#define CAN0_CTOP_CTOE_Pos (24UL) /*!< CTOE (Bit 24) */
+#define CAN0_CTOP_CTOE_Msk (0x1000000UL) /*!< CTOE (Bitfield-Mask: 0x01) */
+#define CAN0_CTOP_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */
+#define CAN0_CTOP_CTOP_Msk (0xffffUL) /*!< CTOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= CTOC ========================================================== */
+#define CAN0_CTOC_CTOC_Pos (0UL) /*!< CTOC (Bit 0) */
+#define CAN0_CTOC_CTOC_Msk (0xffffUL) /*!< CTOC (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ CAN1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================= CTRL ========================================================== */
+#define CAN1_CTRL_AFWL_Pos (28UL) /*!< AFWL (Bit 28) */
+#define CAN1_CTRL_AFWL_Msk (0xf0000000UL) /*!< AFWL (Bitfield-Mask: 0x0f) */
+#define CAN1_CTRL_EWL_Pos (24UL) /*!< EWL (Bit 24) */
+#define CAN1_CTRL_EWL_Msk (0xf000000UL) /*!< EWL (Bitfield-Mask: 0x0f) */
+#define CAN1_CTRL_EREL_Pos (22UL) /*!< EREL (Bit 22) */
+#define CAN1_CTRL_EREL_Msk (0x400000UL) /*!< EREL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_SREL_Pos (21UL) /*!< SREL (Bit 21) */
+#define CAN1_CTRL_SREL_Msk (0x200000UL) /*!< SREL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_RREL_Pos (20UL) /*!< RREL (Bit 20) */
+#define CAN1_CTRL_RREL_Msk (0x100000UL) /*!< RREL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_FD_EN_Pos (18UL) /*!< FD_EN (Bit 18) */
+#define CAN1_CTRL_FD_EN_Msk (0x40000UL) /*!< FD_EN (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_FD_ISO_Pos (17UL) /*!< FD_ISO (Bit 17) */
+#define CAN1_CTRL_FD_ISO_Msk (0x20000UL) /*!< FD_ISO (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TSNEXT_Pos (16UL) /*!< TSNEXT (Bit 16) */
+#define CAN1_CTRL_TSNEXT_Msk (0x10000UL) /*!< TSNEXT (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_PEDT_Pos (15UL) /*!< PEDT (Bit 15) */
+#define CAN1_CTRL_PEDT_Msk (0x8000UL) /*!< PEDT (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_MUXSEL_Pos (13UL) /*!< MUXSEL (Bit 13) */
+#define CAN1_CTRL_MUXSEL_Msk (0x2000UL) /*!< MUXSEL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TBSEL_Pos (12UL) /*!< TBSEL (Bit 12) */
+#define CAN1_CTRL_TBSEL_Msk (0x1000UL) /*!< TBSEL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_LOM_Pos (11UL) /*!< LOM (Bit 11) */
+#define CAN1_CTRL_LOM_Msk (0x800UL) /*!< LOM (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TPE_Pos (9UL) /*!< TPE (Bit 9) */
+#define CAN1_CTRL_TPE_Msk (0x200UL) /*!< TPE (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TPA_Pos (8UL) /*!< TPA (Bit 8) */
+#define CAN1_CTRL_TPA_Msk (0x100UL) /*!< TPA (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TSONE_Pos (7UL) /*!< TSONE (Bit 7) */
+#define CAN1_CTRL_TSONE_Msk (0x80UL) /*!< TSONE (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TSALL_Pos (6UL) /*!< TSALL (Bit 6) */
+#define CAN1_CTRL_TSALL_Msk (0x40UL) /*!< TSALL (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TSA_Pos (5UL) /*!< TSA (Bit 5) */
+#define CAN1_CTRL_TSA_Msk (0x20UL) /*!< TSA (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_RESET_Pos (4UL) /*!< RESET (Bit 4) */
+#define CAN1_CTRL_RESET_Msk (0x10UL) /*!< RESET (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_LBME_Pos (3UL) /*!< LBME (Bit 3) */
+#define CAN1_CTRL_LBME_Msk (0x8UL) /*!< LBME (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_LBMI_Pos (2UL) /*!< LBMI (Bit 2) */
+#define CAN1_CTRL_LBMI_Msk (0x4UL) /*!< LBMI (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TPSS_Pos (1UL) /*!< TPSS (Bit 1) */
+#define CAN1_CTRL_TPSS_Msk (0x2UL) /*!< TPSS (Bitfield-Mask: 0x01) */
+#define CAN1_CTRL_TSSS_Pos (0UL) /*!< TSSS (Bit 0) */
+#define CAN1_CTRL_TSSS_Msk (0x1UL) /*!< TSSS (Bitfield-Mask: 0x01) */
+/* ======================================================== STATUS ========================================================= */
+#define CAN1_STATUS_SAFWL_Pos (28UL) /*!< SAFWL (Bit 28) */
+#define CAN1_STATUS_SAFWL_Msk (0xf0000000UL) /*!< SAFWL (Bitfield-Mask: 0x0f) */
+#define CAN1_STATUS_EAFWL_Pos (24UL) /*!< EAFWL (Bit 24) */
+#define CAN1_STATUS_EAFWL_Msk (0xf000000UL) /*!< EAFWL (Bitfield-Mask: 0x0f) */
+#define CAN1_STATUS_AEWL_Pos (20UL) /*!< AEWL (Bit 20) */
+#define CAN1_STATUS_AEWL_Msk (0xf00000UL) /*!< AEWL (Bitfield-Mask: 0x0f) */
+#define CAN1_STATUS_ROV_Pos (18UL) /*!< ROV (Bit 18) */
+#define CAN1_STATUS_ROV_Msk (0x40000UL) /*!< ROV (Bitfield-Mask: 0x01) */
+#define CAN1_STATUS_RSTAT_Pos (16UL) /*!< RSTAT (Bit 16) */
+#define CAN1_STATUS_RSTAT_Msk (0x30000UL) /*!< RSTAT (Bitfield-Mask: 0x03) */
+#define CAN1_STATUS_SOV_Pos (15UL) /*!< SOV (Bit 15) */
+#define CAN1_STATUS_SOV_Msk (0x8000UL) /*!< SOV (Bitfield-Mask: 0x01) */
+#define CAN1_STATUS_SSTAT_Pos (13UL) /*!< SSTAT (Bit 13) */
+#define CAN1_STATUS_SSTAT_Msk (0x6000UL) /*!< SSTAT (Bitfield-Mask: 0x03) */
+#define CAN1_STATUS_TSSTAT_Pos (8UL) /*!< TSSTAT (Bit 8) */
+#define CAN1_STATUS_TSSTAT_Msk (0x1f00UL) /*!< TSSTAT (Bitfield-Mask: 0x1f) */
+#define CAN1_STATUS_EOV_Pos (7UL) /*!< EOV (Bit 7) */
+#define CAN1_STATUS_EOV_Msk (0x80UL) /*!< EOV (Bitfield-Mask: 0x01) */
+#define CAN1_STATUS_ESTAT_Pos (5UL) /*!< ESTAT (Bit 5) */
+#define CAN1_STATUS_ESTAT_Msk (0x60UL) /*!< ESTAT (Bitfield-Mask: 0x03) */
+#define CAN1_STATUS_RACTIVE_Pos (2UL) /*!< RACTIVE (Bit 2) */
+#define CAN1_STATUS_RACTIVE_Msk (0x4UL) /*!< RACTIVE (Bitfield-Mask: 0x01) */
+#define CAN1_STATUS_TACTIVE_Pos (1UL) /*!< TACTIVE (Bit 1) */
+#define CAN1_STATUS_TACTIVE_Msk (0x2UL) /*!< TACTIVE (Bitfield-Mask: 0x01) */
+#define CAN1_STATUS_BUSOFF_Pos (0UL) /*!< BUSOFF (Bit 0) */
+#define CAN1_STATUS_BUSOFF_Msk (0x1UL) /*!< BUSOFF (Bitfield-Mask: 0x01) */
+/* ======================================================== INTREN ========================================================= */
+#define CAN1_INTREN_TEIE_Pos (31UL) /*!< TEIE (Bit 31) */
+#define CAN1_INTREN_TEIE_Msk (0x80000000UL) /*!< TEIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_TAEIE_Pos (30UL) /*!< TAEIE (Bit 30) */
+#define CAN1_INTREN_TAEIE_Msk (0x40000000UL) /*!< TAEIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_PMIE_Pos (29UL) /*!< PMIE (Bit 29) */
+#define CAN1_INTREN_PMIE_Msk (0x20000000UL) /*!< PMIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_TSCIE_Pos (28UL) /*!< TSCIE (Bit 28) */
+#define CAN1_INTREN_TSCIE_Msk (0x10000000UL) /*!< TSCIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_RTOIE_Pos (27UL) /*!< RTOIE (Bit 27) */
+#define CAN1_INTREN_RTOIE_Msk (0x8000000UL) /*!< RTOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_STOIE_Pos (26UL) /*!< STOIE (Bit 26) */
+#define CAN1_INTREN_STOIE_Msk (0x4000000UL) /*!< STOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_ETOIE_Pos (25UL) /*!< ETOIE (Bit 25) */
+#define CAN1_INTREN_ETOIE_Msk (0x2000000UL) /*!< ETOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_CTOIE_Pos (24UL) /*!< CTOIE (Bit 24) */
+#define CAN1_INTREN_CTOIE_Msk (0x1000000UL) /*!< CTOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_SOIE_Pos (23UL) /*!< SOIE (Bit 23) */
+#define CAN1_INTREN_SOIE_Msk (0x800000UL) /*!< SOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_SFIE_Pos (22UL) /*!< SFIE (Bit 22) */
+#define CAN1_INTREN_SFIE_Msk (0x400000UL) /*!< SFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_SAFIE_Pos (21UL) /*!< SAFIE (Bit 21) */
+#define CAN1_INTREN_SAFIE_Msk (0x200000UL) /*!< SAFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_EOIE_Pos (20UL) /*!< EOIE (Bit 20) */
+#define CAN1_INTREN_EOIE_Msk (0x100000UL) /*!< EOIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_EFIE_Pos (19UL) /*!< EFIE (Bit 19) */
+#define CAN1_INTREN_EFIE_Msk (0x80000UL) /*!< EFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_EAFIE_Pos (18UL) /*!< EAFIE (Bit 18) */
+#define CAN1_INTREN_EAFIE_Msk (0x40000UL) /*!< EAFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_AIE_Pos (17UL) /*!< AIE (Bit 17) */
+#define CAN1_INTREN_AIE_Msk (0x20000UL) /*!< AIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_SRIE_Pos (13UL) /*!< SRIE (Bit 13) */
+#define CAN1_INTREN_SRIE_Msk (0x2000UL) /*!< SRIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_ERIE_Pos (12UL) /*!< ERIE (Bit 12) */
+#define CAN1_INTREN_ERIE_Msk (0x1000UL) /*!< ERIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_ECIE_Pos (11UL) /*!< ECIE (Bit 11) */
+#define CAN1_INTREN_ECIE_Msk (0x800UL) /*!< ECIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */
+#define CAN1_INTREN_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_ALIE_Pos (9UL) /*!< ALIE (Bit 9) */
+#define CAN1_INTREN_ALIE_Msk (0x200UL) /*!< ALIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */
+#define CAN1_INTREN_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_RIE_Pos (7UL) /*!< RIE (Bit 7) */
+#define CAN1_INTREN_RIE_Msk (0x80UL) /*!< RIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_ROIE_Pos (6UL) /*!< ROIE (Bit 6) */
+#define CAN1_INTREN_ROIE_Msk (0x40UL) /*!< ROIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_RFIE_Pos (5UL) /*!< RFIE (Bit 5) */
+#define CAN1_INTREN_RFIE_Msk (0x20UL) /*!< RFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_RAFIE_Pos (4UL) /*!< RAFIE (Bit 4) */
+#define CAN1_INTREN_RAFIE_Msk (0x10UL) /*!< RAFIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_TPIE_Pos (3UL) /*!< TPIE (Bit 3) */
+#define CAN1_INTREN_TPIE_Msk (0x8UL) /*!< TPIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_TSIE_Pos (2UL) /*!< TSIE (Bit 2) */
+#define CAN1_INTREN_TSIE_Msk (0x4UL) /*!< TSIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_EIE_Pos (1UL) /*!< EIE (Bit 1) */
+#define CAN1_INTREN_EIE_Msk (0x2UL) /*!< EIE (Bitfield-Mask: 0x01) */
+#define CAN1_INTREN_TSFF_Pos (0UL) /*!< TSFF (Bit 0) */
+#define CAN1_INTREN_TSFF_Msk (0x1UL) /*!< TSFF (Bitfield-Mask: 0x01) */
+/* ======================================================== INTRST ========================================================= */
+#define CAN1_INTRST_TEIF_Pos (31UL) /*!< TEIF (Bit 31) */
+#define CAN1_INTRST_TEIF_Msk (0x80000000UL) /*!< TEIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_TAEIF_Pos (30UL) /*!< TAEIF (Bit 30) */
+#define CAN1_INTRST_TAEIF_Msk (0x40000000UL) /*!< TAEIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_PMIF_Pos (29UL) /*!< PMIF (Bit 29) */
+#define CAN1_INTRST_PMIF_Msk (0x20000000UL) /*!< PMIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_TSCIF_Pos (28UL) /*!< TSCIF (Bit 28) */
+#define CAN1_INTRST_TSCIF_Msk (0x10000000UL) /*!< TSCIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_RTOIF_Pos (27UL) /*!< RTOIF (Bit 27) */
+#define CAN1_INTRST_RTOIF_Msk (0x8000000UL) /*!< RTOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_STOIF_Pos (26UL) /*!< STOIF (Bit 26) */
+#define CAN1_INTRST_STOIF_Msk (0x4000000UL) /*!< STOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_ETOIF_Pos (25UL) /*!< ETOIF (Bit 25) */
+#define CAN1_INTRST_ETOIF_Msk (0x2000000UL) /*!< ETOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_CTOIF_Pos (24UL) /*!< CTOIF (Bit 24) */
+#define CAN1_INTRST_CTOIF_Msk (0x1000000UL) /*!< CTOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_SOIF_Pos (23UL) /*!< SOIF (Bit 23) */
+#define CAN1_INTRST_SOIF_Msk (0x800000UL) /*!< SOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_SFIF_Pos (22UL) /*!< SFIF (Bit 22) */
+#define CAN1_INTRST_SFIF_Msk (0x400000UL) /*!< SFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_SAFIF_Pos (21UL) /*!< SAFIF (Bit 21) */
+#define CAN1_INTRST_SAFIF_Msk (0x200000UL) /*!< SAFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EOIF_Pos (20UL) /*!< EOIF (Bit 20) */
+#define CAN1_INTRST_EOIF_Msk (0x100000UL) /*!< EOIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EFIF_Pos (19UL) /*!< EFIF (Bit 19) */
+#define CAN1_INTRST_EFIF_Msk (0x80000UL) /*!< EFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EAFIF_Pos (18UL) /*!< EAFIF (Bit 18) */
+#define CAN1_INTRST_EAFIF_Msk (0x40000UL) /*!< EAFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EWARN_Pos (17UL) /*!< EWARN (Bit 17) */
+#define CAN1_INTRST_EWARN_Msk (0x20000UL) /*!< EWARN (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EPASS_Pos (16UL) /*!< EPASS (Bit 16) */
+#define CAN1_INTRST_EPASS_Msk (0x10000UL) /*!< EPASS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_SRIF_Pos (13UL) /*!< SRIF (Bit 13) */
+#define CAN1_INTRST_SRIF_Msk (0x2000UL) /*!< SRIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_ERIF_Pos (12UL) /*!< ERIF (Bit 12) */
+#define CAN1_INTRST_ERIF_Msk (0x1000UL) /*!< ERIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_ECIF_Pos (11UL) /*!< ECIF (Bit 11) */
+#define CAN1_INTRST_ECIF_Msk (0x800UL) /*!< ECIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EPIF_Pos (10UL) /*!< EPIF (Bit 10) */
+#define CAN1_INTRST_EPIF_Msk (0x400UL) /*!< EPIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_ALIF_Pos (9UL) /*!< ALIF (Bit 9) */
+#define CAN1_INTRST_ALIF_Msk (0x200UL) /*!< ALIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_BEIF_Pos (8UL) /*!< BEIF (Bit 8) */
+#define CAN1_INTRST_BEIF_Msk (0x100UL) /*!< BEIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_RIF_Pos (7UL) /*!< RIF (Bit 7) */
+#define CAN1_INTRST_RIF_Msk (0x80UL) /*!< RIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_ROIF_Pos (6UL) /*!< ROIF (Bit 6) */
+#define CAN1_INTRST_ROIF_Msk (0x40UL) /*!< ROIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_RFIF_Pos (5UL) /*!< RFIF (Bit 5) */
+#define CAN1_INTRST_RFIF_Msk (0x20UL) /*!< RFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_RAFIF_Pos (4UL) /*!< RAFIF (Bit 4) */
+#define CAN1_INTRST_RAFIF_Msk (0x10UL) /*!< RAFIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_TPIF_Pos (3UL) /*!< TPIF (Bit 3) */
+#define CAN1_INTRST_TPIF_Msk (0x8UL) /*!< TPIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_TSIF_Pos (2UL) /*!< TSIF (Bit 2) */
+#define CAN1_INTRST_TSIF_Msk (0x4UL) /*!< TSIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_EIF_Pos (1UL) /*!< EIF (Bit 1) */
+#define CAN1_INTRST_EIF_Msk (0x2UL) /*!< EIF (Bitfield-Mask: 0x01) */
+#define CAN1_INTRST_AIF_Pos (0UL) /*!< AIF (Bit 0) */
+#define CAN1_INTRST_AIF_Msk (0x1UL) /*!< AIF (Bitfield-Mask: 0x01) */
+/* ======================================================== BITTIME ======================================================== */
+#define CAN1_BITTIME_F_SEG1_Pos (20UL) /*!< F_SEG1 (Bit 20) */
+#define CAN1_BITTIME_F_SEG1_Msk (0xf00000UL) /*!< F_SEG1 (Bitfield-Mask: 0x0f) */
+#define CAN1_BITTIME_S_SJW_Pos (16UL) /*!< S_SJW (Bit 16) */
+#define CAN1_BITTIME_S_SJW_Msk (0xf0000UL) /*!< S_SJW (Bitfield-Mask: 0x0f) */
+#define CAN1_BITTIME_F_SEG2_Pos (13UL) /*!< F_SEG2 (Bit 13) */
+#define CAN1_BITTIME_F_SEG2_Msk (0xe000UL) /*!< F_SEG2 (Bitfield-Mask: 0x07) */
+#define CAN1_BITTIME_S_SEG2_Pos (8UL) /*!< S_SEG2 (Bit 8) */
+#define CAN1_BITTIME_S_SEG2_Msk (0x1f00UL) /*!< S_SEG2 (Bitfield-Mask: 0x1f) */
+#define CAN1_BITTIME_F_SJW_Pos (6UL) /*!< F_SJW (Bit 6) */
+#define CAN1_BITTIME_F_SJW_Msk (0xc0UL) /*!< F_SJW (Bitfield-Mask: 0x03) */
+#define CAN1_BITTIME_S_SEG1_Pos (0UL) /*!< S_SEG1 (Bit 0) */
+#define CAN1_BITTIME_S_SEG1_Msk (0x3fUL) /*!< S_SEG1 (Bitfield-Mask: 0x3f) */
+/* ========================================================= PRESC ========================================================= */
+#define CAN1_PRESC_TDCEN_Pos (23UL) /*!< TDCEN (Bit 23) */
+#define CAN1_PRESC_TDCEN_Msk (0x800000UL) /*!< TDCEN (Bitfield-Mask: 0x01) */
+#define CAN1_PRESC_SSPOFF_Pos (16UL) /*!< SSPOFF (Bit 16) */
+#define CAN1_PRESC_SSPOFF_Msk (0x1f0000UL) /*!< SSPOFF (Bitfield-Mask: 0x1f) */
+#define CAN1_PRESC_F_PRESC_Pos (8UL) /*!< F_PRESC (Bit 8) */
+#define CAN1_PRESC_F_PRESC_Msk (0xff00UL) /*!< F_PRESC (Bitfield-Mask: 0xff) */
+#define CAN1_PRESC_S_PRESC_Pos (0UL) /*!< S_PRESC (Bit 0) */
+#define CAN1_PRESC_S_PRESC_Msk (0xffUL) /*!< S_PRESC (Bitfield-Mask: 0xff) */
+/* ========================================================= ERRST ========================================================= */
+#define CAN1_ERRST_RECNT_Pos (24UL) /*!< RECNT (Bit 24) */
+#define CAN1_ERRST_RECNT_Msk (0xff000000UL) /*!< RECNT (Bitfield-Mask: 0xff) */
+#define CAN1_ERRST_TECNT_Pos (16UL) /*!< TECNT (Bit 16) */
+#define CAN1_ERRST_TECNT_Msk (0xff0000UL) /*!< TECNT (Bitfield-Mask: 0xff) */
+#define CAN1_ERRST_ECNT_Pos (8UL) /*!< ECNT (Bit 8) */
+#define CAN1_ERRST_ECNT_Msk (0xff00UL) /*!< ECNT (Bitfield-Mask: 0xff) */
+#define CAN1_ERRST_KOER_Pos (5UL) /*!< KOER (Bit 5) */
+#define CAN1_ERRST_KOER_Msk (0xe0UL) /*!< KOER (Bitfield-Mask: 0x07) */
+#define CAN1_ERRST_ALC_Pos (0UL) /*!< ALC (Bit 0) */
+#define CAN1_ERRST_ALC_Msk (0x1fUL) /*!< ALC (Bitfield-Mask: 0x1f) */
+/* ========================================================= PRTST ========================================================= */
+#define CAN1_PRTST_DKOER_Pos (8UL) /*!< DKOER (Bit 8) */
+#define CAN1_PRTST_DKOER_Msk (0x700UL) /*!< DKOER (Bitfield-Mask: 0x07) */
+#define CAN1_PRTST_FDSTS_Pos (4UL) /*!< FDSTS (Bit 4) */
+#define CAN1_PRTST_FDSTS_Msk (0xf0UL) /*!< FDSTS (Bitfield-Mask: 0x0f) */
+#define CAN1_PRTST_NDSTS_Pos (2UL) /*!< NDSTS (Bit 2) */
+#define CAN1_PRTST_NDSTS_Msk (0xcUL) /*!< NDSTS (Bitfield-Mask: 0x03) */
+#define CAN1_PRTST_RBSTS_Pos (0UL) /*!< RBSTS (Bit 0) */
+#define CAN1_PRTST_RBSTS_Msk (0x3UL) /*!< RBSTS (Bitfield-Mask: 0x03) */
+/* ======================================================== INTRLS ========================================================= */
+#define CAN1_INTRLS_TEILS_Pos (31UL) /*!< TEILS (Bit 31) */
+#define CAN1_INTRLS_TEILS_Msk (0x80000000UL) /*!< TEILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_TAEILS_Pos (30UL) /*!< TAEILS (Bit 30) */
+#define CAN1_INTRLS_TAEILS_Msk (0x40000000UL) /*!< TAEILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_PMILS_Pos (29UL) /*!< PMILS (Bit 29) */
+#define CAN1_INTRLS_PMILS_Msk (0x20000000UL) /*!< PMILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_TSCILS_Pos (28UL) /*!< TSCILS (Bit 28) */
+#define CAN1_INTRLS_TSCILS_Msk (0x10000000UL) /*!< TSCILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_RTOILS_Pos (27UL) /*!< RTOILS (Bit 27) */
+#define CAN1_INTRLS_RTOILS_Msk (0x8000000UL) /*!< RTOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_STOILS_Pos (26UL) /*!< STOILS (Bit 26) */
+#define CAN1_INTRLS_STOILS_Msk (0x4000000UL) /*!< STOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_ETOILS_Pos (25UL) /*!< ETOILS (Bit 25) */
+#define CAN1_INTRLS_ETOILS_Msk (0x2000000UL) /*!< ETOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_CTOILS_Pos (24UL) /*!< CTOILS (Bit 24) */
+#define CAN1_INTRLS_CTOILS_Msk (0x1000000UL) /*!< CTOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_SOILS_Pos (23UL) /*!< SOILS (Bit 23) */
+#define CAN1_INTRLS_SOILS_Msk (0x800000UL) /*!< SOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_SFILS_Pos (22UL) /*!< SFILS (Bit 22) */
+#define CAN1_INTRLS_SFILS_Msk (0x400000UL) /*!< SFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_SAFILS_Pos (21UL) /*!< SAFILS (Bit 21) */
+#define CAN1_INTRLS_SAFILS_Msk (0x200000UL) /*!< SAFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_EOILS_Pos (20UL) /*!< EOILS (Bit 20) */
+#define CAN1_INTRLS_EOILS_Msk (0x100000UL) /*!< EOILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_EFILS_Pos (19UL) /*!< EFILS (Bit 19) */
+#define CAN1_INTRLS_EFILS_Msk (0x80000UL) /*!< EFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_EAFILS_Pos (18UL) /*!< EAFILS (Bit 18) */
+#define CAN1_INTRLS_EAFILS_Msk (0x40000UL) /*!< EAFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_SRILS_Pos (13UL) /*!< SRILS (Bit 13) */
+#define CAN1_INTRLS_SRILS_Msk (0x2000UL) /*!< SRILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_ERILS_Pos (12UL) /*!< ERILS (Bit 12) */
+#define CAN1_INTRLS_ERILS_Msk (0x1000UL) /*!< ERILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_ECILS_Pos (11UL) /*!< ECILS (Bit 11) */
+#define CAN1_INTRLS_ECILS_Msk (0x800UL) /*!< ECILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_EPILS_Pos (10UL) /*!< EPILS (Bit 10) */
+#define CAN1_INTRLS_EPILS_Msk (0x400UL) /*!< EPILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_ALILS_Pos (9UL) /*!< ALILS (Bit 9) */
+#define CAN1_INTRLS_ALILS_Msk (0x200UL) /*!< ALILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_BEILS_Pos (8UL) /*!< BEILS (Bit 8) */
+#define CAN1_INTRLS_BEILS_Msk (0x100UL) /*!< BEILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_RILS_Pos (7UL) /*!< RILS (Bit 7) */
+#define CAN1_INTRLS_RILS_Msk (0x80UL) /*!< RILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_ROILS_Pos (6UL) /*!< ROILS (Bit 6) */
+#define CAN1_INTRLS_ROILS_Msk (0x40UL) /*!< ROILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_RFILS_Pos (5UL) /*!< RFILS (Bit 5) */
+#define CAN1_INTRLS_RFILS_Msk (0x20UL) /*!< RFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_RAFILS_Pos (4UL) /*!< RAFILS (Bit 4) */
+#define CAN1_INTRLS_RAFILS_Msk (0x10UL) /*!< RAFILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_TPILS_Pos (3UL) /*!< TPILS (Bit 3) */
+#define CAN1_INTRLS_TPILS_Msk (0x8UL) /*!< TPILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_TSILS_Pos (2UL) /*!< TSILS (Bit 2) */
+#define CAN1_INTRLS_TSILS_Msk (0x4UL) /*!< TSILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_EILS_Pos (1UL) /*!< EILS (Bit 1) */
+#define CAN1_INTRLS_EILS_Msk (0x2UL) /*!< EILS (Bitfield-Mask: 0x01) */
+#define CAN1_INTRLS_AILS_Pos (0UL) /*!< AILS (Bit 0) */
+#define CAN1_INTRLS_AILS_Msk (0x1UL) /*!< AILS (Bitfield-Mask: 0x01) */
+/* ========================================================= GFCR ========================================================== */
+#define CAN1_GFCR_SRFR_Pos (7UL) /*!< SRFR (Bit 7) */
+#define CAN1_GFCR_SRFR_Msk (0x80UL) /*!< SRFR (Bitfield-Mask: 0x01) */
+#define CAN1_GFCR_ERFR_Pos (6UL) /*!< ERFR (Bit 6) */
+#define CAN1_GFCR_ERFR_Msk (0x40UL) /*!< ERFR (Bitfield-Mask: 0x01) */
+#define CAN1_GFCR_PRBM_Pos (1UL) /*!< PRBM (Bit 1) */
+#define CAN1_GFCR_PRBM_Msk (0x2UL) /*!< PRBM (Bitfield-Mask: 0x01) */
+#define CAN1_GFCR_SRBM_Pos (0UL) /*!< SRBM (Bit 0) */
+#define CAN1_GFCR_SRBM_Msk (0x1UL) /*!< SRBM (Bitfield-Mask: 0x01) */
+/* ========================================================= EMCR ========================================================== */
+#define CAN1_EMCR_EIDM_Pos (0UL) /*!< EIDM (Bit 0) */
+#define CAN1_EMCR_EIDM_Msk (0x1fffffffUL) /*!< EIDM (Bitfield-Mask: 0x1fffffff) */
+/* ========================================================= PMST ========================================================== */
+#define CAN1_PMST_PMAS_Pos (4UL) /*!< PMAS (Bit 4) */
+#define CAN1_PMST_PMAS_Msk (0xf0UL) /*!< PMAS (Bitfield-Mask: 0x0f) */
+#define CAN1_PMST_PMBS_Pos (1UL) /*!< PMBS (Bit 1) */
+#define CAN1_PMST_PMBS_Msk (0x6UL) /*!< PMBS (Bitfield-Mask: 0x03) */
+#define CAN1_PMST_PMIS_Pos (0UL) /*!< PMIS (Bit 0) */
+#define CAN1_PMST_PMIS_Msk (0x1UL) /*!< PMIS (Bitfield-Mask: 0x01) */
+/* ========================================================= ACFEN ========================================================= */
+#define CAN1_ACFEN_AE15_Pos (15UL) /*!< AE15 (Bit 15) */
+#define CAN1_ACFEN_AE15_Msk (0x8000UL) /*!< AE15 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE14_Pos (14UL) /*!< AE14 (Bit 14) */
+#define CAN1_ACFEN_AE14_Msk (0x4000UL) /*!< AE14 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE13_Pos (13UL) /*!< AE13 (Bit 13) */
+#define CAN1_ACFEN_AE13_Msk (0x2000UL) /*!< AE13 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE12_Pos (12UL) /*!< AE12 (Bit 12) */
+#define CAN1_ACFEN_AE12_Msk (0x1000UL) /*!< AE12 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE11_Pos (11UL) /*!< AE11 (Bit 11) */
+#define CAN1_ACFEN_AE11_Msk (0x800UL) /*!< AE11 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE10_Pos (10UL) /*!< AE10 (Bit 10) */
+#define CAN1_ACFEN_AE10_Msk (0x400UL) /*!< AE10 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE9_Pos (9UL) /*!< AE9 (Bit 9) */
+#define CAN1_ACFEN_AE9_Msk (0x200UL) /*!< AE9 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE8_Pos (8UL) /*!< AE8 (Bit 8) */
+#define CAN1_ACFEN_AE8_Msk (0x100UL) /*!< AE8 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE7_Pos (7UL) /*!< AE7 (Bit 7) */
+#define CAN1_ACFEN_AE7_Msk (0x80UL) /*!< AE7 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE6_Pos (6UL) /*!< AE6 (Bit 6) */
+#define CAN1_ACFEN_AE6_Msk (0x40UL) /*!< AE6 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE5_Pos (5UL) /*!< AE5 (Bit 5) */
+#define CAN1_ACFEN_AE5_Msk (0x20UL) /*!< AE5 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE4_Pos (4UL) /*!< AE4 (Bit 4) */
+#define CAN1_ACFEN_AE4_Msk (0x10UL) /*!< AE4 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE3_Pos (3UL) /*!< AE3 (Bit 3) */
+#define CAN1_ACFEN_AE3_Msk (0x8UL) /*!< AE3 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE2_Pos (2UL) /*!< AE2 (Bit 2) */
+#define CAN1_ACFEN_AE2_Msk (0x4UL) /*!< AE2 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE1_Pos (1UL) /*!< AE1 (Bit 1) */
+#define CAN1_ACFEN_AE1_Msk (0x2UL) /*!< AE1 (Bitfield-Mask: 0x01) */
+#define CAN1_ACFEN_AE0_Pos (0UL) /*!< AE0 (Bit 0) */
+#define CAN1_ACFEN_AE0_Msk (0x1UL) /*!< AE0 (Bitfield-Mask: 0x01) */
+/* ======================================================== ACFCTRL ======================================================== */
+#define CAN1_ACFCTRL_SELMASK_Pos (5UL) /*!< SELMASK (Bit 5) */
+#define CAN1_ACFCTRL_SELMASK_Msk (0x20UL) /*!< SELMASK (Bitfield-Mask: 0x01) */
+#define CAN1_ACFCTRL_ACFADR_Pos (0UL) /*!< ACFADR (Bit 0) */
+#define CAN1_ACFCTRL_ACFADR_Msk (0xfUL) /*!< ACFADR (Bitfield-Mask: 0x0f) */
+/* ========================================================== ACF ========================================================== */
+#define CAN1_ACF_AIDEE_Pos (30UL) /*!< AIDEE (Bit 30) */
+#define CAN1_ACF_AIDEE_Msk (0x40000000UL) /*!< AIDEE (Bitfield-Mask: 0x01) */
+#define CAN1_ACF_AIDE_Pos (29UL) /*!< AIDE (Bit 29) */
+#define CAN1_ACF_AIDE_Msk (0x20000000UL) /*!< AIDE (Bitfield-Mask: 0x01) */
+#define CAN1_ACF_ACF_X_Pos (0UL) /*!< ACF_X (Bit 0) */
+#define CAN1_ACF_ACF_X_Msk (0x1fffffffUL) /*!< ACF_X (Bitfield-Mask: 0x1fffffff) */
+/* ========================================================= ACFE ========================================================== */
+#define CAN1_ACFE_ACF_M_Pos (4UL) /*!< ACF_M (Bit 4) */
+#define CAN1_ACFE_ACF_M_Msk (0xf0UL) /*!< ACF_M (Bitfield-Mask: 0x0f) */
+#define CAN1_ACFE_ACF_C_Pos (0UL) /*!< ACF_C (Bit 0) */
+#define CAN1_ACFE_ACF_C_Msk (0xfUL) /*!< ACF_C (Bitfield-Mask: 0x0f) */
+/* ======================================================== RBUFID ========================================================= */
+#define CAN1_RBUFID_RXD_ID_Pos (0UL) /*!< RXD_ID (Bit 0) */
+#define CAN1_RBUFID_RXD_ID_Msk (0xffffffffUL) /*!< RXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== RBUFCR ========================================================= */
+#define CAN1_RBUFCR_RXD_ACF_Pos (24UL) /*!< RXD_ACF (Bit 24) */
+#define CAN1_RBUFCR_RXD_ACF_Msk (0xf000000UL) /*!< RXD_ACF (Bitfield-Mask: 0x0f) */
+#define CAN1_RBUFCR_RXD_TS_Pos (8UL) /*!< RXD_TS (Bit 8) */
+#define CAN1_RBUFCR_RXD_TS_Msk (0xffff00UL) /*!< RXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN1_RBUFCR_RXD_CR_Pos (4UL) /*!< RXD_CR (Bit 4) */
+#define CAN1_RBUFCR_RXD_CR_Msk (0xf0UL) /*!< RXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN1_RBUFCR_RXD_DLC_Pos (0UL) /*!< RXD_DLC (Bit 0) */
+#define CAN1_RBUFCR_RXD_DLC_Msk (0xfUL) /*!< RXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== RBUFDT ========================================================= */
+#define CAN1_RBUFDT_RXD_BYTE3_Pos (24UL) /*!< RXD_BYTE3 (Bit 24) */
+#define CAN1_RBUFDT_RXD_BYTE3_Msk (0xff000000UL) /*!< RXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN1_RBUFDT_RXD_BYTE2_Pos (16UL) /*!< RXD_BYTE2 (Bit 16) */
+#define CAN1_RBUFDT_RXD_BYTE2_Msk (0xff0000UL) /*!< RXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN1_RBUFDT_RXD_BYTE1_Pos (8UL) /*!< RXD_BYTE1 (Bit 8) */
+#define CAN1_RBUFDT_RXD_BYTE1_Msk (0xff00UL) /*!< RXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN1_RBUFDT_RXD_BYTE0_Pos (0UL) /*!< RXD_BYTE0 (Bit 0) */
+#define CAN1_RBUFDT_RXD_BYTE0_Msk (0xffUL) /*!< RXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ======================================================== TBUFID ========================================================= */
+#define CAN1_TBUFID_TXD_ID_Pos (0UL) /*!< TXD_ID (Bit 0) */
+#define CAN1_TBUFID_TXD_ID_Msk (0xffffffffUL) /*!< TXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== TBUFCR ========================================================= */
+#define CAN1_TBUFCR_TXD_ETB_Pos (31UL) /*!< TXD_ETB (Bit 31) */
+#define CAN1_TBUFCR_TXD_ETB_Msk (0x80000000UL) /*!< TXD_ETB (Bitfield-Mask: 0x01) */
+#define CAN1_TBUFCR_TXD_MM_Pos (8UL) /*!< TXD_MM (Bit 8) */
+#define CAN1_TBUFCR_TXD_MM_Msk (0xff00UL) /*!< TXD_MM (Bitfield-Mask: 0xff) */
+#define CAN1_TBUFCR_TXD_CR_Pos (4UL) /*!< TXD_CR (Bit 4) */
+#define CAN1_TBUFCR_TXD_CR_Msk (0xf0UL) /*!< TXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN1_TBUFCR_TXD_DLC_Pos (0UL) /*!< TXD_DLC (Bit 0) */
+#define CAN1_TBUFCR_TXD_DLC_Msk (0xfUL) /*!< TXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== TBUFDT ========================================================= */
+#define CAN1_TBUFDT_TXD_BYTE3_Pos (24UL) /*!< TXD_BYTE3 (Bit 24) */
+#define CAN1_TBUFDT_TXD_BYTE3_Msk (0xff000000UL) /*!< TXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN1_TBUFDT_TXD_BYTE2_Pos (16UL) /*!< TXD_BYTE2 (Bit 16) */
+#define CAN1_TBUFDT_TXD_BYTE2_Msk (0xff0000UL) /*!< TXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN1_TBUFDT_TXD_BYTE1_Pos (8UL) /*!< TXD_BYTE1 (Bit 8) */
+#define CAN1_TBUFDT_TXD_BYTE1_Msk (0xff00UL) /*!< TXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN1_TBUFDT_TXD_BYTE0_Pos (0UL) /*!< TXD_BYTE0 (Bit 0) */
+#define CAN1_TBUFDT_TXD_BYTE0_Msk (0xffUL) /*!< TXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ======================================================== EBUFID ========================================================= */
+#define CAN1_EBUFID_TXD_ID_Pos (0UL) /*!< TXD_ID (Bit 0) */
+#define CAN1_EBUFID_TXD_ID_Msk (0xffffffffUL) /*!< TXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== EBUFDT ========================================================= */
+#define CAN1_EBUFDT_TXD_MM_Pos (24UL) /*!< TXD_MM (Bit 24) */
+#define CAN1_EBUFDT_TXD_MM_Msk (0xff000000UL) /*!< TXD_MM (Bitfield-Mask: 0xff) */
+#define CAN1_EBUFDT_TXD_TS_Pos (8UL) /*!< TXD_TS (Bit 8) */
+#define CAN1_EBUFDT_TXD_TS_Msk (0xffff00UL) /*!< TXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN1_EBUFDT_TXD_CR_Pos (4UL) /*!< TXD_CR (Bit 4) */
+#define CAN1_EBUFDT_TXD_CR_Msk (0xf0UL) /*!< TXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN1_EBUFDT_TXD_DLC_Pos (0UL) /*!< TXD_DLC (Bit 0) */
+#define CAN1_EBUFDT_TXD_DLC_Msk (0xfUL) /*!< TXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== SBUFID ========================================================= */
+#define CAN1_SBUFID_RXD_ID_Pos (0UL) /*!< RXD_ID (Bit 0) */
+#define CAN1_SBUFID_RXD_ID_Msk (0xffffffffUL) /*!< RXD_ID (Bitfield-Mask: 0xffffffff) */
+/* ======================================================== SBUFCR ========================================================= */
+#define CAN1_SBUFCR_RXD_ACF_Pos (24UL) /*!< RXD_ACF (Bit 24) */
+#define CAN1_SBUFCR_RXD_ACF_Msk (0xf000000UL) /*!< RXD_ACF (Bitfield-Mask: 0x0f) */
+#define CAN1_SBUFCR_RXD_TS_Pos (8UL) /*!< RXD_TS (Bit 8) */
+#define CAN1_SBUFCR_RXD_TS_Msk (0xffff00UL) /*!< RXD_TS (Bitfield-Mask: 0xffff) */
+#define CAN1_SBUFCR_RXD_CR_Pos (4UL) /*!< RXD_CR (Bit 4) */
+#define CAN1_SBUFCR_RXD_CR_Msk (0xf0UL) /*!< RXD_CR (Bitfield-Mask: 0x0f) */
+#define CAN1_SBUFCR_RXD_DLC_Pos (0UL) /*!< RXD_DLC (Bit 0) */
+#define CAN1_SBUFCR_RXD_DLC_Msk (0xfUL) /*!< RXD_DLC (Bitfield-Mask: 0x0f) */
+/* ======================================================== SBUFDT ========================================================= */
+#define CAN1_SBUFDT_RXD_BYTE3_Pos (24UL) /*!< RXD_BYTE3 (Bit 24) */
+#define CAN1_SBUFDT_RXD_BYTE3_Msk (0xff000000UL) /*!< RXD_BYTE3 (Bitfield-Mask: 0xff) */
+#define CAN1_SBUFDT_RXD_BYTE2_Pos (16UL) /*!< RXD_BYTE2 (Bit 16) */
+#define CAN1_SBUFDT_RXD_BYTE2_Msk (0xff0000UL) /*!< RXD_BYTE2 (Bitfield-Mask: 0xff) */
+#define CAN1_SBUFDT_RXD_BYTE1_Pos (8UL) /*!< RXD_BYTE1 (Bit 8) */
+#define CAN1_SBUFDT_RXD_BYTE1_Msk (0xff00UL) /*!< RXD_BYTE1 (Bitfield-Mask: 0xff) */
+#define CAN1_SBUFDT_RXD_BYTE0_Pos (0UL) /*!< RXD_BYTE0 (Bit 0) */
+#define CAN1_SBUFDT_RXD_BYTE0_Msk (0xffUL) /*!< RXD_BYTE0 (Bitfield-Mask: 0xff) */
+/* ========================================================= TSCR ========================================================== */
+#define CAN1_TSCR_TSP_Pos (20UL) /*!< TSP (Bit 20) */
+#define CAN1_TSCR_TSP_Msk (0xf00000UL) /*!< TSP (Bitfield-Mask: 0x0f) */
+#define CAN1_TSCR_TSS_Pos (16UL) /*!< TSS (Bit 16) */
+#define CAN1_TSCR_TSS_Msk (0xf0000UL) /*!< TSS (Bitfield-Mask: 0x0f) */
+/* ========================================================== TSC ========================================================== */
+#define CAN1_TSC_TSC_Pos (0UL) /*!< TSC (Bit 0) */
+#define CAN1_TSC_TSC_Msk (0xffffUL) /*!< TSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= RTOP ========================================================== */
+#define CAN1_RTOP_RTOE_Pos (24UL) /*!< RTOE (Bit 24) */
+#define CAN1_RTOP_RTOE_Msk (0x1000000UL) /*!< RTOE (Bitfield-Mask: 0x01) */
+#define CAN1_RTOP_RTOP_Pos (0UL) /*!< RTOP (Bit 0) */
+#define CAN1_RTOP_RTOP_Msk (0xffffUL) /*!< RTOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= RTOC ========================================================== */
+#define CAN1_RTOC_RTOC_Pos (0UL) /*!< RTOC (Bit 0) */
+#define CAN1_RTOC_RTOC_Msk (0xffffUL) /*!< RTOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= STOP ========================================================== */
+#define CAN1_STOP_STOE_Pos (24UL) /*!< STOE (Bit 24) */
+#define CAN1_STOP_STOE_Msk (0x1000000UL) /*!< STOE (Bitfield-Mask: 0x01) */
+#define CAN1_STOP_STOP_Pos (0UL) /*!< STOP (Bit 0) */
+#define CAN1_STOP_STOP_Msk (0xffffUL) /*!< STOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= STOC ========================================================== */
+#define CAN1_STOC_STOC_Pos (0UL) /*!< STOC (Bit 0) */
+#define CAN1_STOC_STOC_Msk (0xffffUL) /*!< STOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= ETOP ========================================================== */
+#define CAN1_ETOP_ETOE_Pos (24UL) /*!< ETOE (Bit 24) */
+#define CAN1_ETOP_ETOE_Msk (0x1000000UL) /*!< ETOE (Bitfield-Mask: 0x01) */
+#define CAN1_ETOP_ETOP_Pos (0UL) /*!< ETOP (Bit 0) */
+#define CAN1_ETOP_ETOP_Msk (0xffffUL) /*!< ETOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= ETOC ========================================================== */
+#define CAN1_ETOC_ETOC_Pos (0UL) /*!< ETOC (Bit 0) */
+#define CAN1_ETOC_ETOC_Msk (0xffffUL) /*!< ETOC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CTOP ========================================================== */
+#define CAN1_CTOP_CTOE_Pos (24UL) /*!< CTOE (Bit 24) */
+#define CAN1_CTOP_CTOE_Msk (0x1000000UL) /*!< CTOE (Bitfield-Mask: 0x01) */
+#define CAN1_CTOP_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */
+#define CAN1_CTOP_CTOP_Msk (0xffffUL) /*!< CTOP (Bitfield-Mask: 0xffff) */
+/* ========================================================= CTOC ========================================================== */
+#define CAN1_CTOC_CTOC_Pos (0UL) /*!< CTOC (Bit 0) */
+#define CAN1_CTOC_CTOC_Msk (0xffffUL) /*!< CTOC (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR7 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR7_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR7_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR7_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR7_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR7_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR7_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR7_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR7_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR7_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR7_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR7_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR7_CR1_MMS_Msk (0x3UL) /*!< MMS (Bitfield-Mask: 0x03) */
+/* ========================================================== IER ========================================================== */
+#define TMR7_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR7_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR7_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR7_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR7_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR7_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR7_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR7_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR7_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR7_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================== TCR ========================================================== */
+#define TMR7_TCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR7_TCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR7_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR7_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR7_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR7_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR7_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR7_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR8 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR8_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR8_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR8_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR8_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR8_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR8_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR8_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR8_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR8_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR8_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR8_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR8_CR1_MMS_Msk (0x3UL) /*!< MMS (Bitfield-Mask: 0x03) */
+/* ========================================================== IER ========================================================== */
+#define TMR8_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR8_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR8_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR8_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR8_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR8_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR8_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR8_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR8_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR8_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================== TCR ========================================================== */
+#define TMR8_TCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR8_TCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR8_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR8_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR8_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR8_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR8_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR8_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR9 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR9_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR9_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR9_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR9_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR9_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_CMS_Pos (5UL) /*!< CMS (Bit 5) */
+#define TMR9_CR0_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */
+#define TMR9_CR0_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+#define TMR9_CR0_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR9_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR9_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR9_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR9_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR9_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR9_CR1_OIS3N_Pos (15UL) /*!< OIS3N (Bit 15) */
+#define TMR9_CR1_OIS3N_Msk (0x8000UL) /*!< OIS3N (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS3_Pos (14UL) /*!< OIS3 (Bit 14) */
+#define TMR9_CR1_OIS3_Msk (0x4000UL) /*!< OIS3 (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS2N_Pos (13UL) /*!< OIS2N (Bit 13) */
+#define TMR9_CR1_OIS2N_Msk (0x2000UL) /*!< OIS2N (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS2_Pos (12UL) /*!< OIS2 (Bit 12) */
+#define TMR9_CR1_OIS2_Msk (0x1000UL) /*!< OIS2 (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS1N_Pos (11UL) /*!< OIS1N (Bit 11) */
+#define TMR9_CR1_OIS1N_Msk (0x800UL) /*!< OIS1N (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS1_Pos (10UL) /*!< OIS1 (Bit 10) */
+#define TMR9_CR1_OIS1_Msk (0x400UL) /*!< OIS1 (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS0N_Pos (9UL) /*!< OIS0N (Bit 9) */
+#define TMR9_CR1_OIS0N_Msk (0x200UL) /*!< OIS0N (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_OIS0_Pos (8UL) /*!< OIS0 (Bit 8) */
+#define TMR9_CR1_OIS0_Msk (0x100UL) /*!< OIS0 (Bitfield-Mask: 0x01) */
+#define TMR9_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR9_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR9_SCR_ETS_Pos (24UL) /*!< ETS (Bit 24) */
+#define TMR9_SCR_ETS_Msk (0xf000000UL) /*!< ETS (Bitfield-Mask: 0x0f) */
+#define TMR9_SCR_EE_Pos (22UL) /*!< EE (Bit 22) */
+#define TMR9_SCR_EE_Msk (0x400000UL) /*!< EE (Bitfield-Mask: 0x01) */
+#define TMR9_SCR_EMS_Pos (20UL) /*!< EMS (Bit 20) */
+#define TMR9_SCR_EMS_Msk (0x300000UL) /*!< EMS (Bitfield-Mask: 0x03) */
+#define TMR9_SCR_EFS_Pos (16UL) /*!< EFS (Bit 16) */
+#define TMR9_SCR_EFS_Msk (0xf0000UL) /*!< EFS (Bitfield-Mask: 0x0f) */
+#define TMR9_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR9_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR9_SCR_FE_Pos (7UL) /*!< FE (Bit 7) */
+#define TMR9_SCR_FE_Msk (0x80UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define TMR9_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR9_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR9_IER_BIE_Pos (11UL) /*!< BIE (Bit 11) */
+#define TMR9_IER_BIE_Msk (0x800UL) /*!< BIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR9_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR9_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR9_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C3OIE_Pos (7UL) /*!< C3OIE (Bit 7) */
+#define TMR9_IER_C3OIE_Msk (0x80UL) /*!< C3OIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C3MIE_Pos (6UL) /*!< C3MIE (Bit 6) */
+#define TMR9_IER_C3MIE_Msk (0x40UL) /*!< C3MIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C2OIE_Pos (5UL) /*!< C2OIE (Bit 5) */
+#define TMR9_IER_C2OIE_Msk (0x20UL) /*!< C2OIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C2MIE_Pos (4UL) /*!< C2MIE (Bit 4) */
+#define TMR9_IER_C2MIE_Msk (0x10UL) /*!< C2MIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR9_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR9_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR9_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR9_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR9_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR9_SR_B1IF_Pos (13UL) /*!< B1IF (Bit 13) */
+#define TMR9_SR_B1IF_Msk (0x2000UL) /*!< B1IF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_SBIF_Pos (12UL) /*!< SBIF (Bit 12) */
+#define TMR9_SR_SBIF_Msk (0x1000UL) /*!< SBIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_B0IF_Pos (11UL) /*!< B0IF (Bit 11) */
+#define TMR9_SR_B0IF_Msk (0x800UL) /*!< B0IF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR9_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR9_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR9_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC3OIF_Pos (7UL) /*!< CC3OIF (Bit 7) */
+#define TMR9_SR_CC3OIF_Msk (0x80UL) /*!< CC3OIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC3MIF_Pos (6UL) /*!< CC3MIF (Bit 6) */
+#define TMR9_SR_CC3MIF_Msk (0x40UL) /*!< CC3MIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC2OIF_Pos (5UL) /*!< CC2OIF (Bit 5) */
+#define TMR9_SR_CC2OIF_Msk (0x20UL) /*!< CC2OIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC2MIF_Pos (4UL) /*!< CC2MIF (Bit 4) */
+#define TMR9_SR_CC2MIF_Msk (0x10UL) /*!< CC2MIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR9_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR9_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR9_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR9_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR9_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR9_UGR_CC3UG_Pos (7UL) /*!< CC3UG (Bit 7) */
+#define TMR9_UGR_CC3UG_Msk (0x80UL) /*!< CC3UG (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_CC2UG_Pos (6UL) /*!< CC2UG (Bit 6) */
+#define TMR9_UGR_CC2UG_Msk (0x40UL) /*!< CC2UG (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR9_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR9_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_B1G_Pos (3UL) /*!< B1G (Bit 3) */
+#define TMR9_UGR_B1G_Msk (0x8UL) /*!< B1G (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_B0G_Pos (2UL) /*!< B0G (Bit 2) */
+#define TMR9_UGR_B0G_Msk (0x4UL) /*!< B0G (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR9_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR9_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR9_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR9_CCMR_OC3M_Pos (28UL) /*!< OC3M (Bit 28) */
+#define TMR9_CCMR_OC3M_Msk (0xf0000000UL) /*!< OC3M (Bitfield-Mask: 0x0f) */
+#define TMR9_CCMR_CC3PE_Pos (26UL) /*!< CC3PE (Bit 26) */
+#define TMR9_CCMR_CC3PE_Msk (0xc000000UL) /*!< CC3PE (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_CC3S_Pos (24UL) /*!< CC3S (Bit 24) */
+#define TMR9_CCMR_CC3S_Msk (0x3000000UL) /*!< CC3S (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_OC2M_Pos (20UL) /*!< OC2M (Bit 20) */
+#define TMR9_CCMR_OC2M_Msk (0xf00000UL) /*!< OC2M (Bitfield-Mask: 0x0f) */
+#define TMR9_CCMR_CC2PE_Pos (18UL) /*!< CC2PE (Bit 18) */
+#define TMR9_CCMR_CC2PE_Msk (0xc0000UL) /*!< CC2PE (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_CC2S_Pos (16UL) /*!< CC2S (Bit 16) */
+#define TMR9_CCMR_CC2S_Msk (0x30000UL) /*!< CC2S (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR9_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR9_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR9_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR9_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR9_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR9_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR9_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR9_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR9_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR9_CCER_CC3P_Pos (14UL) /*!< CC3P (Bit 14) */
+#define TMR9_CCER_CC3P_Msk (0xc000UL) /*!< CC3P (Bitfield-Mask: 0x03) */
+#define TMR9_CCER_CC3NE_Pos (13UL) /*!< CC3NE (Bit 13) */
+#define TMR9_CCER_CC3NE_Msk (0x2000UL) /*!< CC3NE (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC3E_Pos (12UL) /*!< CC3E (Bit 12) */
+#define TMR9_CCER_CC3E_Msk (0x1000UL) /*!< CC3E (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC2P_Pos (10UL) /*!< CC2P (Bit 10) */
+#define TMR9_CCER_CC2P_Msk (0xc00UL) /*!< CC2P (Bitfield-Mask: 0x03) */
+#define TMR9_CCER_CC2NE_Pos (9UL) /*!< CC2NE (Bit 9) */
+#define TMR9_CCER_CC2NE_Msk (0x200UL) /*!< CC2NE (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC2E_Pos (8UL) /*!< CC2E (Bit 8) */
+#define TMR9_CCER_CC2E_Msk (0x100UL) /*!< CC2E (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR9_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR9_CCER_CC1NE_Pos (5UL) /*!< CC1NE (Bit 5) */
+#define TMR9_CCER_CC1NE_Msk (0x20UL) /*!< CC1NE (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR9_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR9_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR9_CCER_CC0NE_Pos (1UL) /*!< CC0NE (Bit 1) */
+#define TMR9_CCER_CC0NE_Msk (0x2UL) /*!< CC0NE (Bitfield-Mask: 0x01) */
+#define TMR9_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR9_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+#define TMR9_DCR_BK1F_Pos (24UL) /*!< BK1F (Bit 24) */
+#define TMR9_DCR_BK1F_Msk (0xff000000UL) /*!< BK1F (Bitfield-Mask: 0xff) */
+#define TMR9_DCR_BK1P_Pos (23UL) /*!< BK1P (Bit 23) */
+#define TMR9_DCR_BK1P_Msk (0x800000UL) /*!< BK1P (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_BK1E_Pos (22UL) /*!< BK1E (Bit 22) */
+#define TMR9_DCR_BK1E_Msk (0x400000UL) /*!< BK1E (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_BK0F_Pos (14UL) /*!< BK0F (Bit 14) */
+#define TMR9_DCR_BK0F_Msk (0x3fc000UL) /*!< BK0F (Bitfield-Mask: 0xff) */
+#define TMR9_DCR_BK0P_Pos (13UL) /*!< BK0P (Bit 13) */
+#define TMR9_DCR_BK0P_Msk (0x2000UL) /*!< BK0P (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_BK0E_Pos (12UL) /*!< BK0E (Bit 12) */
+#define TMR9_DCR_BK0E_Msk (0x1000UL) /*!< BK0E (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_MOE_Pos (11UL) /*!< MOE (Bit 11) */
+#define TMR9_DCR_MOE_Msk (0x800UL) /*!< MOE (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_AOE_Pos (10UL) /*!< AOE (Bit 10) */
+#define TMR9_DCR_AOE_Msk (0x400UL) /*!< AOE (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_OSSR_Pos (9UL) /*!< OSSR (Bit 9) */
+#define TMR9_DCR_OSSR_Msk (0x200UL) /*!< OSSR (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_OSSI_Pos (8UL) /*!< OSSI (Bit 8) */
+#define TMR9_DCR_OSSI_Msk (0x100UL) /*!< OSSI (Bitfield-Mask: 0x01) */
+#define TMR9_DCR_DTG_Pos (0UL) /*!< DTG (Bit 0) */
+#define TMR9_DCR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR9_TTCR_TC3E_Pos (11UL) /*!< TC3E (Bit 11) */
+#define TMR9_TTCR_TC3E_Msk (0x800UL) /*!< TC3E (Bitfield-Mask: 0x01) */
+#define TMR9_TTCR_TC2E_Pos (10UL) /*!< TC2E (Bit 10) */
+#define TMR9_TTCR_TC2E_Msk (0x400UL) /*!< TC2E (Bitfield-Mask: 0x01) */
+#define TMR9_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR9_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR9_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR9_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR9_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR9_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR9_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR9_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR9_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR9_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR9_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR9_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR9_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR9_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================== CRR ========================================================== */
+#define TMR9_CRR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define TMR9_CRR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR9_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR9_CC0R_CC0V_Msk (0xffffUL) /*!< CC0V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR9_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR9_CC1R_CC1V_Msk (0xffffUL) /*!< CC1V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC2R ========================================================== */
+#define TMR9_CC2R_CC2V_Pos (0UL) /*!< CC2V (Bit 0) */
+#define TMR9_CC2R_CC2V_Msk (0xffffUL) /*!< CC2V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC3R ========================================================== */
+#define TMR9_CC3R_CC3V_Pos (0UL) /*!< CC3V (Bit 0) */
+#define TMR9_CC3R_CC3V_Msk (0xffffUL) /*!< CC3V (Bitfield-Mask: 0xffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR9_CIR_C3TIS_Pos (24UL) /*!< C3TIS (Bit 24) */
+#define TMR9_CIR_C3TIS_Msk (0xf000000UL) /*!< C3TIS (Bitfield-Mask: 0x0f) */
+#define TMR9_CIR_C2TIS_Pos (16UL) /*!< C2TIS (Bit 16) */
+#define TMR9_CIR_C2TIS_Msk (0xf0000UL) /*!< C2TIS (Bitfield-Mask: 0x0f) */
+#define TMR9_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR9_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR9_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR9_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+/* ========================================================== BPR ========================================================== */
+#define TMR9_BPR_B1POL_Pos (16UL) /*!< B1POL (Bit 16) */
+#define TMR9_BPR_B1POL_Msk (0xffff0000UL) /*!< B1POL (Bitfield-Mask: 0xffff) */
+#define TMR9_BPR_B0POL_Pos (0UL) /*!< B0POL (Bit 0) */
+#define TMR9_BPR_B0POL_Msk (0xffffUL) /*!< B0POL (Bitfield-Mask: 0xffff) */
+/* ========================================================== BER ========================================================== */
+#define TMR9_BER_B1IEN_Pos (16UL) /*!< B1IEN (Bit 16) */
+#define TMR9_BER_B1IEN_Msk (0xffff0000UL) /*!< B1IEN (Bitfield-Mask: 0xffff) */
+#define TMR9_BER_B0IEN_Pos (0UL) /*!< B0IEN (Bit 0) */
+#define TMR9_BER_B0IEN_Msk (0xffffUL) /*!< B0IEN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR10 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR10_CR0_TI0S_Pos (10UL) /*!< TI0S (Bit 10) */
+#define TMR10_CR0_TI0S_Msk (0x400UL) /*!< TI0S (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_DCD_Pos (8UL) /*!< DCD (Bit 8) */
+#define TMR10_CR0_DCD_Msk (0x300UL) /*!< DCD (Bitfield-Mask: 0x03) */
+#define TMR10_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR10_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_CMS_Pos (5UL) /*!< CMS (Bit 5) */
+#define TMR10_CR0_CMS_Msk (0x60UL) /*!< CMS (Bitfield-Mask: 0x03) */
+#define TMR10_CR0_DIR_Pos (4UL) /*!< DIR (Bit 4) */
+#define TMR10_CR0_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR10_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_URS_Pos (2UL) /*!< URS (Bit 2) */
+#define TMR10_CR0_URS_Msk (0x4UL) /*!< URS (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_UDIS_Pos (1UL) /*!< UDIS (Bit 1) */
+#define TMR10_CR0_UDIS_Msk (0x2UL) /*!< UDIS (Bitfield-Mask: 0x01) */
+#define TMR10_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR10_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== CR1 ========================================================== */
+#define TMR10_CR1_OIS3N_Pos (15UL) /*!< OIS3N (Bit 15) */
+#define TMR10_CR1_OIS3N_Msk (0x8000UL) /*!< OIS3N (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS3_Pos (14UL) /*!< OIS3 (Bit 14) */
+#define TMR10_CR1_OIS3_Msk (0x4000UL) /*!< OIS3 (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS2N_Pos (13UL) /*!< OIS2N (Bit 13) */
+#define TMR10_CR1_OIS2N_Msk (0x2000UL) /*!< OIS2N (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS2_Pos (12UL) /*!< OIS2 (Bit 12) */
+#define TMR10_CR1_OIS2_Msk (0x1000UL) /*!< OIS2 (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS1N_Pos (11UL) /*!< OIS1N (Bit 11) */
+#define TMR10_CR1_OIS1N_Msk (0x800UL) /*!< OIS1N (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS1_Pos (10UL) /*!< OIS1 (Bit 10) */
+#define TMR10_CR1_OIS1_Msk (0x400UL) /*!< OIS1 (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS0N_Pos (9UL) /*!< OIS0N (Bit 9) */
+#define TMR10_CR1_OIS0N_Msk (0x200UL) /*!< OIS0N (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_OIS0_Pos (8UL) /*!< OIS0 (Bit 8) */
+#define TMR10_CR1_OIS0_Msk (0x100UL) /*!< OIS0 (Bitfield-Mask: 0x01) */
+#define TMR10_CR1_MMS_Pos (0UL) /*!< MMS (Bit 0) */
+#define TMR10_CR1_MMS_Msk (0x7UL) /*!< MMS (Bitfield-Mask: 0x07) */
+/* ========================================================== SCR ========================================================== */
+#define TMR10_SCR_ETS_Pos (24UL) /*!< ETS (Bit 24) */
+#define TMR10_SCR_ETS_Msk (0xf000000UL) /*!< ETS (Bitfield-Mask: 0x0f) */
+#define TMR10_SCR_EE_Pos (22UL) /*!< EE (Bit 22) */
+#define TMR10_SCR_EE_Msk (0x400000UL) /*!< EE (Bitfield-Mask: 0x01) */
+#define TMR10_SCR_EMS_Pos (20UL) /*!< EMS (Bit 20) */
+#define TMR10_SCR_EMS_Msk (0x300000UL) /*!< EMS (Bitfield-Mask: 0x03) */
+#define TMR10_SCR_EFS_Pos (16UL) /*!< EFS (Bit 16) */
+#define TMR10_SCR_EFS_Msk (0xf0000UL) /*!< EFS (Bitfield-Mask: 0x0f) */
+#define TMR10_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR10_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR10_SCR_FE_Pos (7UL) /*!< FE (Bit 7) */
+#define TMR10_SCR_FE_Msk (0x80UL) /*!< FE (Bitfield-Mask: 0x01) */
+#define TMR10_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR10_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR10_IER_BIE_Pos (11UL) /*!< BIE (Bit 11) */
+#define TMR10_IER_BIE_Msk (0x800UL) /*!< BIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR10_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_OVIE_Pos (9UL) /*!< OVIE (Bit 9) */
+#define TMR10_IER_OVIE_Msk (0x200UL) /*!< OVIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR10_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C3OIE_Pos (7UL) /*!< C3OIE (Bit 7) */
+#define TMR10_IER_C3OIE_Msk (0x80UL) /*!< C3OIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C3MIE_Pos (6UL) /*!< C3MIE (Bit 6) */
+#define TMR10_IER_C3MIE_Msk (0x40UL) /*!< C3MIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C2OIE_Pos (5UL) /*!< C2OIE (Bit 5) */
+#define TMR10_IER_C2OIE_Msk (0x20UL) /*!< C2OIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C2MIE_Pos (4UL) /*!< C2MIE (Bit 4) */
+#define TMR10_IER_C2MIE_Msk (0x10UL) /*!< C2MIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C1OIE_Pos (3UL) /*!< C1OIE (Bit 3) */
+#define TMR10_IER_C1OIE_Msk (0x8UL) /*!< C1OIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C1MIE_Pos (2UL) /*!< C1MIE (Bit 2) */
+#define TMR10_IER_C1MIE_Msk (0x4UL) /*!< C1MIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C0OIE_Pos (1UL) /*!< C0OIE (Bit 1) */
+#define TMR10_IER_C0OIE_Msk (0x2UL) /*!< C0OIE (Bitfield-Mask: 0x01) */
+#define TMR10_IER_C0MIE_Pos (0UL) /*!< C0MIE (Bit 0) */
+#define TMR10_IER_C0MIE_Msk (0x1UL) /*!< C0MIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR10_SR_B1IF_Pos (13UL) /*!< B1IF (Bit 13) */
+#define TMR10_SR_B1IF_Msk (0x2000UL) /*!< B1IF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_SBIF_Pos (12UL) /*!< SBIF (Bit 12) */
+#define TMR10_SR_SBIF_Msk (0x1000UL) /*!< SBIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_B0IF_Pos (11UL) /*!< B0IF (Bit 11) */
+#define TMR10_SR_B0IF_Msk (0x800UL) /*!< B0IF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR10_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_OVIF_Pos (9UL) /*!< OVIF (Bit 9) */
+#define TMR10_SR_OVIF_Msk (0x200UL) /*!< OVIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR10_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC3OIF_Pos (7UL) /*!< CC3OIF (Bit 7) */
+#define TMR10_SR_CC3OIF_Msk (0x80UL) /*!< CC3OIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC3MIF_Pos (6UL) /*!< CC3MIF (Bit 6) */
+#define TMR10_SR_CC3MIF_Msk (0x40UL) /*!< CC3MIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC2OIF_Pos (5UL) /*!< CC2OIF (Bit 5) */
+#define TMR10_SR_CC2OIF_Msk (0x20UL) /*!< CC2OIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC2MIF_Pos (4UL) /*!< CC2MIF (Bit 4) */
+#define TMR10_SR_CC2MIF_Msk (0x10UL) /*!< CC2MIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC1OIF_Pos (3UL) /*!< CC1OIF (Bit 3) */
+#define TMR10_SR_CC1OIF_Msk (0x8UL) /*!< CC1OIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC1MIF_Pos (2UL) /*!< CC1MIF (Bit 2) */
+#define TMR10_SR_CC1MIF_Msk (0x4UL) /*!< CC1MIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC0OIF_Pos (1UL) /*!< CC0OIF (Bit 1) */
+#define TMR10_SR_CC0OIF_Msk (0x2UL) /*!< CC0OIF (Bitfield-Mask: 0x01) */
+#define TMR10_SR_CC0MIF_Pos (0UL) /*!< CC0MIF (Bit 0) */
+#define TMR10_SR_CC0MIF_Msk (0x1UL) /*!< CC0MIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR10_UGR_CC3UG_Pos (7UL) /*!< CC3UG (Bit 7) */
+#define TMR10_UGR_CC3UG_Msk (0x80UL) /*!< CC3UG (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_CC2UG_Pos (6UL) /*!< CC2UG (Bit 6) */
+#define TMR10_UGR_CC2UG_Msk (0x40UL) /*!< CC2UG (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_CC1UG_Pos (5UL) /*!< CC1UG (Bit 5) */
+#define TMR10_UGR_CC1UG_Msk (0x20UL) /*!< CC1UG (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_CC0UG_Pos (4UL) /*!< CC0UG (Bit 4) */
+#define TMR10_UGR_CC0UG_Msk (0x10UL) /*!< CC0UG (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_B1G_Pos (3UL) /*!< B1G (Bit 3) */
+#define TMR10_UGR_B1G_Msk (0x8UL) /*!< B1G (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_B0G_Pos (2UL) /*!< B0G (Bit 2) */
+#define TMR10_UGR_B0G_Msk (0x4UL) /*!< B0G (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR10_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR10_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR10_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR10_CCMR_OC3M_Pos (28UL) /*!< OC3M (Bit 28) */
+#define TMR10_CCMR_OC3M_Msk (0xf0000000UL) /*!< OC3M (Bitfield-Mask: 0x0f) */
+#define TMR10_CCMR_CC3PE_Pos (26UL) /*!< CC3PE (Bit 26) */
+#define TMR10_CCMR_CC3PE_Msk (0xc000000UL) /*!< CC3PE (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_CC3S_Pos (24UL) /*!< CC3S (Bit 24) */
+#define TMR10_CCMR_CC3S_Msk (0x3000000UL) /*!< CC3S (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_OC2M_Pos (20UL) /*!< OC2M (Bit 20) */
+#define TMR10_CCMR_OC2M_Msk (0xf00000UL) /*!< OC2M (Bitfield-Mask: 0x0f) */
+#define TMR10_CCMR_CC2PE_Pos (18UL) /*!< CC2PE (Bit 18) */
+#define TMR10_CCMR_CC2PE_Msk (0xc0000UL) /*!< CC2PE (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_CC2S_Pos (16UL) /*!< CC2S (Bit 16) */
+#define TMR10_CCMR_CC2S_Msk (0x30000UL) /*!< CC2S (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_OC1M_Pos (12UL) /*!< OC1M (Bit 12) */
+#define TMR10_CCMR_OC1M_Msk (0xf000UL) /*!< OC1M (Bitfield-Mask: 0x0f) */
+#define TMR10_CCMR_CC1PE_Pos (10UL) /*!< CC1PE (Bit 10) */
+#define TMR10_CCMR_CC1PE_Msk (0xc00UL) /*!< CC1PE (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_CC1S_Pos (8UL) /*!< CC1S (Bit 8) */
+#define TMR10_CCMR_CC1S_Msk (0x300UL) /*!< CC1S (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_OC0M_Pos (4UL) /*!< OC0M (Bit 4) */
+#define TMR10_CCMR_OC0M_Msk (0xf0UL) /*!< OC0M (Bitfield-Mask: 0x0f) */
+#define TMR10_CCMR_CC0PE_Pos (2UL) /*!< CC0PE (Bit 2) */
+#define TMR10_CCMR_CC0PE_Msk (0xcUL) /*!< CC0PE (Bitfield-Mask: 0x03) */
+#define TMR10_CCMR_CC0S_Pos (0UL) /*!< CC0S (Bit 0) */
+#define TMR10_CCMR_CC0S_Msk (0x3UL) /*!< CC0S (Bitfield-Mask: 0x03) */
+/* ========================================================= CCER ========================================================== */
+#define TMR10_CCER_CC3P_Pos (14UL) /*!< CC3P (Bit 14) */
+#define TMR10_CCER_CC3P_Msk (0xc000UL) /*!< CC3P (Bitfield-Mask: 0x03) */
+#define TMR10_CCER_CC3NE_Pos (13UL) /*!< CC3NE (Bit 13) */
+#define TMR10_CCER_CC3NE_Msk (0x2000UL) /*!< CC3NE (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC3E_Pos (12UL) /*!< CC3E (Bit 12) */
+#define TMR10_CCER_CC3E_Msk (0x1000UL) /*!< CC3E (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC2P_Pos (10UL) /*!< CC2P (Bit 10) */
+#define TMR10_CCER_CC2P_Msk (0xc00UL) /*!< CC2P (Bitfield-Mask: 0x03) */
+#define TMR10_CCER_CC2NE_Pos (9UL) /*!< CC2NE (Bit 9) */
+#define TMR10_CCER_CC2NE_Msk (0x200UL) /*!< CC2NE (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC2E_Pos (8UL) /*!< CC2E (Bit 8) */
+#define TMR10_CCER_CC2E_Msk (0x100UL) /*!< CC2E (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC1P_Pos (6UL) /*!< CC1P (Bit 6) */
+#define TMR10_CCER_CC1P_Msk (0xc0UL) /*!< CC1P (Bitfield-Mask: 0x03) */
+#define TMR10_CCER_CC1NE_Pos (5UL) /*!< CC1NE (Bit 5) */
+#define TMR10_CCER_CC1NE_Msk (0x20UL) /*!< CC1NE (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC1E_Pos (4UL) /*!< CC1E (Bit 4) */
+#define TMR10_CCER_CC1E_Msk (0x10UL) /*!< CC1E (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC0P_Pos (2UL) /*!< CC0P (Bit 2) */
+#define TMR10_CCER_CC0P_Msk (0xcUL) /*!< CC0P (Bitfield-Mask: 0x03) */
+#define TMR10_CCER_CC0NE_Pos (1UL) /*!< CC0NE (Bit 1) */
+#define TMR10_CCER_CC0NE_Msk (0x2UL) /*!< CC0NE (Bitfield-Mask: 0x01) */
+#define TMR10_CCER_CC0E_Pos (0UL) /*!< CC0E (Bit 0) */
+#define TMR10_CCER_CC0E_Msk (0x1UL) /*!< CC0E (Bitfield-Mask: 0x01) */
+/* ========================================================== DCR ========================================================== */
+#define TMR10_DCR_BK1F_Pos (24UL) /*!< BK1F (Bit 24) */
+#define TMR10_DCR_BK1F_Msk (0xff000000UL) /*!< BK1F (Bitfield-Mask: 0xff) */
+#define TMR10_DCR_BK1P_Pos (23UL) /*!< BK1P (Bit 23) */
+#define TMR10_DCR_BK1P_Msk (0x800000UL) /*!< BK1P (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_BK1E_Pos (22UL) /*!< BK1E (Bit 22) */
+#define TMR10_DCR_BK1E_Msk (0x400000UL) /*!< BK1E (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_BK0F_Pos (14UL) /*!< BK0F (Bit 14) */
+#define TMR10_DCR_BK0F_Msk (0x3fc000UL) /*!< BK0F (Bitfield-Mask: 0xff) */
+#define TMR10_DCR_BK0P_Pos (13UL) /*!< BK0P (Bit 13) */
+#define TMR10_DCR_BK0P_Msk (0x2000UL) /*!< BK0P (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_BK0E_Pos (12UL) /*!< BK0E (Bit 12) */
+#define TMR10_DCR_BK0E_Msk (0x1000UL) /*!< BK0E (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_MOE_Pos (11UL) /*!< MOE (Bit 11) */
+#define TMR10_DCR_MOE_Msk (0x800UL) /*!< MOE (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_AOE_Pos (10UL) /*!< AOE (Bit 10) */
+#define TMR10_DCR_AOE_Msk (0x400UL) /*!< AOE (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_OSSR_Pos (9UL) /*!< OSSR (Bit 9) */
+#define TMR10_DCR_OSSR_Msk (0x200UL) /*!< OSSR (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_OSSI_Pos (8UL) /*!< OSSI (Bit 8) */
+#define TMR10_DCR_OSSI_Msk (0x100UL) /*!< OSSI (Bitfield-Mask: 0x01) */
+#define TMR10_DCR_DTG_Pos (0UL) /*!< DTG (Bit 0) */
+#define TMR10_DCR_DTG_Msk (0xffUL) /*!< DTG (Bitfield-Mask: 0xff) */
+/* ========================================================= TTCR ========================================================== */
+#define TMR10_TTCR_TC3E_Pos (11UL) /*!< TC3E (Bit 11) */
+#define TMR10_TTCR_TC3E_Msk (0x800UL) /*!< TC3E (Bitfield-Mask: 0x01) */
+#define TMR10_TTCR_TC2E_Pos (10UL) /*!< TC2E (Bit 10) */
+#define TMR10_TTCR_TC2E_Msk (0x400UL) /*!< TC2E (Bitfield-Mask: 0x01) */
+#define TMR10_TTCR_TC1E_Pos (9UL) /*!< TC1E (Bit 9) */
+#define TMR10_TTCR_TC1E_Msk (0x200UL) /*!< TC1E (Bitfield-Mask: 0x01) */
+#define TMR10_TTCR_TC0E_Pos (8UL) /*!< TC0E (Bit 8) */
+#define TMR10_TTCR_TC0E_Msk (0x100UL) /*!< TC0E (Bitfield-Mask: 0x01) */
+#define TMR10_TTCR_TCW_Pos (4UL) /*!< TCW (Bit 4) */
+#define TMR10_TTCR_TCW_Msk (0xf0UL) /*!< TCW (Bitfield-Mask: 0x0f) */
+#define TMR10_TTCR_TOW_Pos (0UL) /*!< TOW (Bit 0) */
+#define TMR10_TTCR_TOW_Msk (0xfUL) /*!< TOW (Bitfield-Mask: 0x0f) */
+/* ========================================================== CPR ========================================================== */
+#define TMR10_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR10_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR10_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR10_PSCR_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR10_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR10_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================== CRR ========================================================== */
+#define TMR10_CRR_REP_Pos (0UL) /*!< REP (Bit 0) */
+#define TMR10_CRR_REP_Msk (0xffUL) /*!< REP (Bitfield-Mask: 0xff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR10_CC0R_CC0V_Pos (0UL) /*!< CC0V (Bit 0) */
+#define TMR10_CC0R_CC0V_Msk (0xffffUL) /*!< CC0V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC1R ========================================================== */
+#define TMR10_CC1R_CC1V_Pos (0UL) /*!< CC1V (Bit 0) */
+#define TMR10_CC1R_CC1V_Msk (0xffffUL) /*!< CC1V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC2R ========================================================== */
+#define TMR10_CC2R_CC2V_Pos (0UL) /*!< CC2V (Bit 0) */
+#define TMR10_CC2R_CC2V_Msk (0xffffUL) /*!< CC2V (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC3R ========================================================== */
+#define TMR10_CC3R_CC3V_Pos (0UL) /*!< CC3V (Bit 0) */
+#define TMR10_CC3R_CC3V_Msk (0xffffUL) /*!< CC3V (Bitfield-Mask: 0xffff) */
+/* ========================================================== CIR ========================================================== */
+#define TMR10_CIR_C3TIS_Pos (24UL) /*!< C3TIS (Bit 24) */
+#define TMR10_CIR_C3TIS_Msk (0xf000000UL) /*!< C3TIS (Bitfield-Mask: 0x0f) */
+#define TMR10_CIR_C2TIS_Pos (16UL) /*!< C2TIS (Bit 16) */
+#define TMR10_CIR_C2TIS_Msk (0xf0000UL) /*!< C2TIS (Bitfield-Mask: 0x0f) */
+#define TMR10_CIR_C1TIS_Pos (8UL) /*!< C1TIS (Bit 8) */
+#define TMR10_CIR_C1TIS_Msk (0xf00UL) /*!< C1TIS (Bitfield-Mask: 0x0f) */
+#define TMR10_CIR_C0TIS_Pos (0UL) /*!< C0TIS (Bit 0) */
+#define TMR10_CIR_C0TIS_Msk (0xfUL) /*!< C0TIS (Bitfield-Mask: 0x0f) */
+/* ========================================================== BPR ========================================================== */
+#define TMR10_BPR_B1POL_Pos (16UL) /*!< B1POL (Bit 16) */
+#define TMR10_BPR_B1POL_Msk (0xffff0000UL) /*!< B1POL (Bitfield-Mask: 0xffff) */
+#define TMR10_BPR_B0POL_Pos (0UL) /*!< B0POL (Bit 0) */
+#define TMR10_BPR_B0POL_Msk (0xffffUL) /*!< B0POL (Bitfield-Mask: 0xffff) */
+/* ========================================================== BER ========================================================== */
+#define TMR10_BER_B1IEN_Pos (16UL) /*!< B1IEN (Bit 16) */
+#define TMR10_BER_B1IEN_Msk (0xffff0000UL) /*!< B1IEN (Bitfield-Mask: 0xffff) */
+#define TMR10_BER_B0IEN_Pos (0UL) /*!< B0IEN (Bit 0) */
+#define TMR10_BER_B0IEN_Msk (0xffffUL) /*!< B0IEN (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ ADC0 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define ADC0_CR_ADCALDIF_Pos (7UL) /*!< ADCALDIF (Bit 7) */
+#define ADC0_CR_ADCALDIF_Msk (0x80UL) /*!< ADCALDIF (Bitfield-Mask: 0x01) */
+#define ADC0_CR_ADCAL_Pos (6UL) /*!< ADCAL (Bit 6) */
+#define ADC0_CR_ADCAL_Msk (0x40UL) /*!< ADCAL (Bitfield-Mask: 0x01) */
+#define ADC0_CR_JADSTP_Pos (5UL) /*!< JADSTP (Bit 5) */
+#define ADC0_CR_JADSTP_Msk (0x20UL) /*!< JADSTP (Bitfield-Mask: 0x01) */
+#define ADC0_CR_ADSTP_Pos (4UL) /*!< ADSTP (Bit 4) */
+#define ADC0_CR_ADSTP_Msk (0x10UL) /*!< ADSTP (Bitfield-Mask: 0x01) */
+#define ADC0_CR_JADSTART_Pos (3UL) /*!< JADSTART (Bit 3) */
+#define ADC0_CR_JADSTART_Msk (0x8UL) /*!< JADSTART (Bitfield-Mask: 0x01) */
+#define ADC0_CR_ADSTART_Pos (2UL) /*!< ADSTART (Bit 2) */
+#define ADC0_CR_ADSTART_Msk (0x4UL) /*!< ADSTART (Bitfield-Mask: 0x01) */
+#define ADC0_CR_ADDIS_Pos (1UL) /*!< ADDIS (Bit 1) */
+#define ADC0_CR_ADDIS_Msk (0x2UL) /*!< ADDIS (Bitfield-Mask: 0x01) */
+#define ADC0_CR_ADEN_Pos (0UL) /*!< ADEN (Bit 0) */
+#define ADC0_CR_ADEN_Msk (0x1UL) /*!< ADEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR0 ========================================================= */
+#define ADC0_CFGR0_OVSCAL_Pos (28UL) /*!< OVSCAL (Bit 28) */
+#define ADC0_CFGR0_OVSCAL_Msk (0x70000000UL) /*!< OVSCAL (Bitfield-Mask: 0x07) */
+#define ADC0_CFGR0_CONT_Pos (23UL) /*!< CONT (Bit 23) */
+#define ADC0_CFGR0_CONT_Msk (0x800000UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_JAUTO_Pos (22UL) /*!< JAUTO (Bit 22) */
+#define ADC0_CFGR0_JAUTO_Msk (0x400000UL) /*!< JAUTO (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_JDISCEN_Pos (20UL) /*!< JDISCEN (Bit 20) */
+#define ADC0_CFGR0_JDISCEN_Msk (0x100000UL) /*!< JDISCEN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_DISCNUM_Pos (17UL) /*!< DISCNUM (Bit 17) */
+#define ADC0_CFGR0_DISCNUM_Msk (0xe0000UL) /*!< DISCNUM (Bitfield-Mask: 0x07) */
+#define ADC0_CFGR0_DISCEN_Pos (16UL) /*!< DISCEN (Bit 16) */
+#define ADC0_CFGR0_DISCEN_Msk (0x10000UL) /*!< DISCEN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_OVRMOD_Pos (15UL) /*!< OVRMOD (Bit 15) */
+#define ADC0_CFGR0_OVRMOD_Msk (0x8000UL) /*!< OVRMOD (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_SDMAEN_Pos (14UL) /*!< SDMAEN (Bit 14) */
+#define ADC0_CFGR0_SDMAEN_Msk (0x4000UL) /*!< SDMAEN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_TROVS_Pos (12UL) /*!< TROVS (Bit 12) */
+#define ADC0_CFGR0_TROVS_Msk (0x1000UL) /*!< TROVS (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_OVSS_Pos (8UL) /*!< OVSS (Bit 8) */
+#define ADC0_CFGR0_OVSS_Msk (0xf00UL) /*!< OVSS (Bitfield-Mask: 0x0f) */
+#define ADC0_CFGR0_ROVSM_Pos (7UL) /*!< ROVSM (Bit 7) */
+#define ADC0_CFGR0_ROVSM_Msk (0x80UL) /*!< ROVSM (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_OVSR_Pos (4UL) /*!< OVSR (Bit 4) */
+#define ADC0_CFGR0_OVSR_Msk (0x70UL) /*!< OVSR (Bitfield-Mask: 0x07) */
+#define ADC0_CFGR0_JOVSE_Pos (1UL) /*!< JOVSE (Bit 1) */
+#define ADC0_CFGR0_JOVSE_Msk (0x2UL) /*!< JOVSE (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR0_ROVSE_Pos (0UL) /*!< ROVSE (Bit 0) */
+#define ADC0_CFGR0_ROVSE_Msk (0x1UL) /*!< ROVSE (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR1 ========================================================= */
+#define ADC0_CFGR1_JAWD2EN_Pos (14UL) /*!< JAWD2EN (Bit 14) */
+#define ADC0_CFGR1_JAWD2EN_Msk (0x4000UL) /*!< JAWD2EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_JAWD1EN_Pos (13UL) /*!< JAWD1EN (Bit 13) */
+#define ADC0_CFGR1_JAWD1EN_Msk (0x2000UL) /*!< JAWD1EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_JAWD0EN_Pos (12UL) /*!< JAWD0EN (Bit 12) */
+#define ADC0_CFGR1_JAWD0EN_Msk (0x1000UL) /*!< JAWD0EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_AWD2EN_Pos (10UL) /*!< AWD2EN (Bit 10) */
+#define ADC0_CFGR1_AWD2EN_Msk (0x400UL) /*!< AWD2EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_AWD1EN_Pos (9UL) /*!< AWD1EN (Bit 9) */
+#define ADC0_CFGR1_AWD1EN_Msk (0x200UL) /*!< AWD1EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_AWD0EN_Pos (8UL) /*!< AWD0EN (Bit 8) */
+#define ADC0_CFGR1_AWD0EN_Msk (0x100UL) /*!< AWD0EN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_ISEL_Pos (4UL) /*!< ISEL (Bit 4) */
+#define ADC0_CFGR1_ISEL_Msk (0x30UL) /*!< ISEL (Bitfield-Mask: 0x03) */
+#define ADC0_CFGR1_CHEN_Pos (3UL) /*!< CHEN (Bit 3) */
+#define ADC0_CFGR1_CHEN_Msk (0x8UL) /*!< CHEN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_REFEN_Pos (1UL) /*!< REFEN (Bit 1) */
+#define ADC0_CFGR1_REFEN_Msk (0x2UL) /*!< REFEN (Bitfield-Mask: 0x01) */
+#define ADC0_CFGR1_BIASEN_Pos (0UL) /*!< BIASEN (Bit 0) */
+#define ADC0_CFGR1_BIASEN_Msk (0x1UL) /*!< BIASEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define ADC0_ISR_EOSMP_Pos (9UL) /*!< EOSMP (Bit 9) */
+#define ADC0_ISR_EOSMP_Msk (0x200UL) /*!< EOSMP (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_ADRDY_Pos (8UL) /*!< ADRDY (Bit 8) */
+#define ADC0_ISR_ADRDY_Msk (0x100UL) /*!< ADRDY (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_AWD2_Pos (7UL) /*!< AWD2 (Bit 7) */
+#define ADC0_ISR_AWD2_Msk (0x80UL) /*!< AWD2 (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_AWD1_Pos (6UL) /*!< AWD1 (Bit 6) */
+#define ADC0_ISR_AWD1_Msk (0x40UL) /*!< AWD1 (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_AWD0_Pos (5UL) /*!< AWD0 (Bit 5) */
+#define ADC0_ISR_AWD0_Msk (0x20UL) /*!< AWD0 (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_OVR_Pos (4UL) /*!< OVR (Bit 4) */
+#define ADC0_ISR_OVR_Msk (0x10UL) /*!< OVR (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_JEOS_Pos (3UL) /*!< JEOS (Bit 3) */
+#define ADC0_ISR_JEOS_Msk (0x8UL) /*!< JEOS (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_JEOC_Pos (2UL) /*!< JEOC (Bit 2) */
+#define ADC0_ISR_JEOC_Msk (0x4UL) /*!< JEOC (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */
+#define ADC0_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */
+#define ADC0_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */
+#define ADC0_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define ADC0_IER_EOSMPIE_Pos (9UL) /*!< EOSMPIE (Bit 9) */
+#define ADC0_IER_EOSMPIE_Msk (0x200UL) /*!< EOSMPIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_ADRDYIE_Pos (8UL) /*!< ADRDYIE (Bit 8) */
+#define ADC0_IER_ADRDYIE_Msk (0x100UL) /*!< ADRDYIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_AWD2IE_Pos (7UL) /*!< AWD2IE (Bit 7) */
+#define ADC0_IER_AWD2IE_Msk (0x80UL) /*!< AWD2IE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_AWD1IE_Pos (6UL) /*!< AWD1IE (Bit 6) */
+#define ADC0_IER_AWD1IE_Msk (0x40UL) /*!< AWD1IE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_AWD0IE_Pos (5UL) /*!< AWD0IE (Bit 5) */
+#define ADC0_IER_AWD0IE_Msk (0x20UL) /*!< AWD0IE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_OVRIE_Pos (4UL) /*!< OVRIE (Bit 4) */
+#define ADC0_IER_OVRIE_Msk (0x10UL) /*!< OVRIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_JEOSIE_Pos (3UL) /*!< JEOSIE (Bit 3) */
+#define ADC0_IER_JEOSIE_Msk (0x8UL) /*!< JEOSIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_JEOCIE_Pos (2UL) /*!< JEOCIE (Bit 2) */
+#define ADC0_IER_JEOCIE_Msk (0x4UL) /*!< JEOCIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_EOSIE_Pos (1UL) /*!< EOSIE (Bit 1) */
+#define ADC0_IER_EOSIE_Msk (0x2UL) /*!< EOSIE (Bitfield-Mask: 0x01) */
+#define ADC0_IER_EOCIE_Pos (0UL) /*!< EOCIE (Bit 0) */
+#define ADC0_IER_EOCIE_Msk (0x1UL) /*!< EOCIE (Bitfield-Mask: 0x01) */
+/* ======================================================== SIGSEL ========================================================= */
+#define ADC0_SIGSEL_SIGSEL_Pos (0UL) /*!< SIGSEL (Bit 0) */
+#define ADC0_SIGSEL_SIGSEL_Msk (0xfffffUL) /*!< SIGSEL (Bitfield-Mask: 0xfffff) */
+/* ========================================================= SMPR0 ========================================================= */
+#define ADC0_SMPR0_SMP7_Pos (28UL) /*!< SMP7 (Bit 28) */
+#define ADC0_SMPR0_SMP7_Msk (0x70000000UL) /*!< SMP7 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP6_Pos (24UL) /*!< SMP6 (Bit 24) */
+#define ADC0_SMPR0_SMP6_Msk (0x7000000UL) /*!< SMP6 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP5_Pos (20UL) /*!< SMP5 (Bit 20) */
+#define ADC0_SMPR0_SMP5_Msk (0x700000UL) /*!< SMP5 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP4_Pos (16UL) /*!< SMP4 (Bit 16) */
+#define ADC0_SMPR0_SMP4_Msk (0x70000UL) /*!< SMP4 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP3_Pos (12UL) /*!< SMP3 (Bit 12) */
+#define ADC0_SMPR0_SMP3_Msk (0x7000UL) /*!< SMP3 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP2_Pos (8UL) /*!< SMP2 (Bit 8) */
+#define ADC0_SMPR0_SMP2_Msk (0x700UL) /*!< SMP2 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP1_Pos (4UL) /*!< SMP1 (Bit 4) */
+#define ADC0_SMPR0_SMP1_Msk (0x70UL) /*!< SMP1 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR0_SMP0_Pos (0UL) /*!< SMP0 (Bit 0) */
+#define ADC0_SMPR0_SMP0_Msk (0x7UL) /*!< SMP0 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR1 ========================================================= */
+#define ADC0_SMPR1_SMP15_Pos (28UL) /*!< SMP15 (Bit 28) */
+#define ADC0_SMPR1_SMP15_Msk (0x70000000UL) /*!< SMP15 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP14_Pos (24UL) /*!< SMP14 (Bit 24) */
+#define ADC0_SMPR1_SMP14_Msk (0x7000000UL) /*!< SMP14 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP13_Pos (20UL) /*!< SMP13 (Bit 20) */
+#define ADC0_SMPR1_SMP13_Msk (0x700000UL) /*!< SMP13 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP12_Pos (16UL) /*!< SMP12 (Bit 16) */
+#define ADC0_SMPR1_SMP12_Msk (0x70000UL) /*!< SMP12 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP11_Pos (12UL) /*!< SMP11 (Bit 12) */
+#define ADC0_SMPR1_SMP11_Msk (0x7000UL) /*!< SMP11 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP10_Pos (8UL) /*!< SMP10 (Bit 8) */
+#define ADC0_SMPR1_SMP10_Msk (0x700UL) /*!< SMP10 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP9_Pos (4UL) /*!< SMP9 (Bit 4) */
+#define ADC0_SMPR1_SMP9_Msk (0x70UL) /*!< SMP9 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR1_SMP8_Pos (0UL) /*!< SMP8 (Bit 0) */
+#define ADC0_SMPR1_SMP8_Msk (0x7UL) /*!< SMP8 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR2 ========================================================= */
+#define ADC0_SMPR2_SMP19_Pos (12UL) /*!< SMP19 (Bit 12) */
+#define ADC0_SMPR2_SMP19_Msk (0x7000UL) /*!< SMP19 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR2_SMP18_Pos (8UL) /*!< SMP18 (Bit 8) */
+#define ADC0_SMPR2_SMP18_Msk (0x700UL) /*!< SMP18 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR2_SMP17_Pos (4UL) /*!< SMP17 (Bit 4) */
+#define ADC0_SMPR2_SMP17_Msk (0x70UL) /*!< SMP17 (Bitfield-Mask: 0x07) */
+#define ADC0_SMPR2_SMP16_Pos (0UL) /*!< SMP16 (Bit 0) */
+#define ADC0_SMPR2_SMP16_Msk (0x7UL) /*!< SMP16 (Bitfield-Mask: 0x07) */
+/* ========================================================= CALR0 ========================================================= */
+#define ADC0_CALR0_SAT7_Pos (31UL) /*!< SAT7 (Bit 31) */
+#define ADC0_CALR0_SAT7_Msk (0x80000000UL) /*!< SAT7 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL7_Pos (28UL) /*!< CAL7 (Bit 28) */
+#define ADC0_CALR0_CAL7_Msk (0x30000000UL) /*!< CAL7 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT6_Pos (27UL) /*!< SAT6 (Bit 27) */
+#define ADC0_CALR0_SAT6_Msk (0x8000000UL) /*!< SAT6 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL6_Pos (24UL) /*!< CAL6 (Bit 24) */
+#define ADC0_CALR0_CAL6_Msk (0x3000000UL) /*!< CAL6 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT5_Pos (23UL) /*!< SAT5 (Bit 23) */
+#define ADC0_CALR0_SAT5_Msk (0x800000UL) /*!< SAT5 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL5_Pos (20UL) /*!< CAL5 (Bit 20) */
+#define ADC0_CALR0_CAL5_Msk (0x300000UL) /*!< CAL5 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT4_Pos (19UL) /*!< SAT4 (Bit 19) */
+#define ADC0_CALR0_SAT4_Msk (0x80000UL) /*!< SAT4 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL4_Pos (16UL) /*!< CAL4 (Bit 16) */
+#define ADC0_CALR0_CAL4_Msk (0x30000UL) /*!< CAL4 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT3_Pos (15UL) /*!< SAT3 (Bit 15) */
+#define ADC0_CALR0_SAT3_Msk (0x8000UL) /*!< SAT3 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL3_Pos (12UL) /*!< CAL3 (Bit 12) */
+#define ADC0_CALR0_CAL3_Msk (0x3000UL) /*!< CAL3 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT2_Pos (11UL) /*!< SAT2 (Bit 11) */
+#define ADC0_CALR0_SAT2_Msk (0x800UL) /*!< SAT2 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL2_Pos (8UL) /*!< CAL2 (Bit 8) */
+#define ADC0_CALR0_CAL2_Msk (0x300UL) /*!< CAL2 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT1_Pos (7UL) /*!< SAT1 (Bit 7) */
+#define ADC0_CALR0_SAT1_Msk (0x80UL) /*!< SAT1 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL1_Pos (4UL) /*!< CAL1 (Bit 4) */
+#define ADC0_CALR0_CAL1_Msk (0x30UL) /*!< CAL1 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR0_SAT0_Pos (3UL) /*!< SAT0 (Bit 3) */
+#define ADC0_CALR0_SAT0_Msk (0x8UL) /*!< SAT0 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR0_CAL0_Pos (0UL) /*!< CAL0 (Bit 0) */
+#define ADC0_CALR0_CAL0_Msk (0x3UL) /*!< CAL0 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR1 ========================================================= */
+#define ADC0_CALR1_SAT15_Pos (31UL) /*!< SAT15 (Bit 31) */
+#define ADC0_CALR1_SAT15_Msk (0x80000000UL) /*!< SAT15 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL15_Pos (28UL) /*!< CAL15 (Bit 28) */
+#define ADC0_CALR1_CAL15_Msk (0x30000000UL) /*!< CAL15 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT14_Pos (27UL) /*!< SAT14 (Bit 27) */
+#define ADC0_CALR1_SAT14_Msk (0x8000000UL) /*!< SAT14 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL14_Pos (24UL) /*!< CAL14 (Bit 24) */
+#define ADC0_CALR1_CAL14_Msk (0x3000000UL) /*!< CAL14 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT13_Pos (23UL) /*!< SAT13 (Bit 23) */
+#define ADC0_CALR1_SAT13_Msk (0x800000UL) /*!< SAT13 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL13_Pos (20UL) /*!< CAL13 (Bit 20) */
+#define ADC0_CALR1_CAL13_Msk (0x300000UL) /*!< CAL13 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT12_Pos (19UL) /*!< SAT12 (Bit 19) */
+#define ADC0_CALR1_SAT12_Msk (0x80000UL) /*!< SAT12 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL12_Pos (16UL) /*!< CAL12 (Bit 16) */
+#define ADC0_CALR1_CAL12_Msk (0x30000UL) /*!< CAL12 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT11_Pos (15UL) /*!< SAT11 (Bit 15) */
+#define ADC0_CALR1_SAT11_Msk (0x8000UL) /*!< SAT11 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL11_Pos (12UL) /*!< CAL11 (Bit 12) */
+#define ADC0_CALR1_CAL11_Msk (0x3000UL) /*!< CAL11 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT10_Pos (11UL) /*!< SAT10 (Bit 11) */
+#define ADC0_CALR1_SAT10_Msk (0x800UL) /*!< SAT10 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL10_Pos (8UL) /*!< CAL10 (Bit 8) */
+#define ADC0_CALR1_CAL10_Msk (0x300UL) /*!< CAL10 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT9_Pos (7UL) /*!< SAT9 (Bit 7) */
+#define ADC0_CALR1_SAT9_Msk (0x80UL) /*!< SAT9 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL9_Pos (4UL) /*!< CAL9 (Bit 4) */
+#define ADC0_CALR1_CAL9_Msk (0x30UL) /*!< CAL9 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR1_SAT8_Pos (3UL) /*!< SAT8 (Bit 3) */
+#define ADC0_CALR1_SAT8_Msk (0x8UL) /*!< SAT8 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR1_CAL8_Pos (0UL) /*!< CAL8 (Bit 0) */
+#define ADC0_CALR1_CAL8_Msk (0x3UL) /*!< CAL8 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR2 ========================================================= */
+#define ADC0_CALR2_SAT19_Pos (15UL) /*!< SAT19 (Bit 15) */
+#define ADC0_CALR2_SAT19_Msk (0x8000UL) /*!< SAT19 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR2_CAL19_Pos (12UL) /*!< CAL19 (Bit 12) */
+#define ADC0_CALR2_CAL19_Msk (0x3000UL) /*!< CAL19 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR2_SAT18_Pos (11UL) /*!< SAT18 (Bit 11) */
+#define ADC0_CALR2_SAT18_Msk (0x800UL) /*!< SAT18 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR2_CAL18_Pos (8UL) /*!< CAL18 (Bit 8) */
+#define ADC0_CALR2_CAL18_Msk (0x300UL) /*!< CAL18 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR2_SAT17_Pos (7UL) /*!< SAT17 (Bit 7) */
+#define ADC0_CALR2_SAT17_Msk (0x80UL) /*!< SAT17 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR2_CAL17_Pos (4UL) /*!< CAL17 (Bit 4) */
+#define ADC0_CALR2_CAL17_Msk (0x30UL) /*!< CAL17 (Bitfield-Mask: 0x03) */
+#define ADC0_CALR2_SAT16_Pos (3UL) /*!< SAT16 (Bit 3) */
+#define ADC0_CALR2_SAT16_Msk (0x8UL) /*!< SAT16 (Bitfield-Mask: 0x01) */
+#define ADC0_CALR2_CAL16_Pos (0UL) /*!< CAL16 (Bit 0) */
+#define ADC0_CALR2_CAL16_Msk (0x3UL) /*!< CAL16 (Bitfield-Mask: 0x03) */
+/* ========================================================= SQR0 ========================================================== */
+#define ADC0_SQR0_SQ5_Pos (24UL) /*!< SQ5 (Bit 24) */
+#define ADC0_SQR0_SQ5_Msk (0x1f000000UL) /*!< SQ5 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR0_SQ4_Pos (18UL) /*!< SQ4 (Bit 18) */
+#define ADC0_SQR0_SQ4_Msk (0x7c0000UL) /*!< SQ4 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR0_SQ3_Pos (12UL) /*!< SQ3 (Bit 12) */
+#define ADC0_SQR0_SQ3_Msk (0x1f000UL) /*!< SQ3 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR0_SQ2_Pos (6UL) /*!< SQ2 (Bit 6) */
+#define ADC0_SQR0_SQ2_Msk (0x7c0UL) /*!< SQ2 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR0_SQ1_Pos (0UL) /*!< SQ1 (Bit 0) */
+#define ADC0_SQR0_SQ1_Msk (0x1fUL) /*!< SQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR1 ========================================================== */
+#define ADC0_SQR1_SQ10_Pos (24UL) /*!< SQ10 (Bit 24) */
+#define ADC0_SQR1_SQ10_Msk (0x1f000000UL) /*!< SQ10 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR1_SQ9_Pos (18UL) /*!< SQ9 (Bit 18) */
+#define ADC0_SQR1_SQ9_Msk (0x7c0000UL) /*!< SQ9 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR1_SQ8_Pos (12UL) /*!< SQ8 (Bit 12) */
+#define ADC0_SQR1_SQ8_Msk (0x1f000UL) /*!< SQ8 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR1_SQ7_Pos (6UL) /*!< SQ7 (Bit 6) */
+#define ADC0_SQR1_SQ7_Msk (0x7c0UL) /*!< SQ7 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR1_SQ6_Pos (0UL) /*!< SQ6 (Bit 0) */
+#define ADC0_SQR1_SQ6_Msk (0x1fUL) /*!< SQ6 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR2 ========================================================== */
+#define ADC0_SQR2_SQ15_Pos (24UL) /*!< SQ15 (Bit 24) */
+#define ADC0_SQR2_SQ15_Msk (0x1f000000UL) /*!< SQ15 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR2_SQ14_Pos (18UL) /*!< SQ14 (Bit 18) */
+#define ADC0_SQR2_SQ14_Msk (0x7c0000UL) /*!< SQ14 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR2_SQ13_Pos (12UL) /*!< SQ13 (Bit 12) */
+#define ADC0_SQR2_SQ13_Msk (0x1f000UL) /*!< SQ13 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR2_SQ12_Pos (6UL) /*!< SQ12 (Bit 6) */
+#define ADC0_SQR2_SQ12_Msk (0x7c0UL) /*!< SQ12 (Bitfield-Mask: 0x1f) */
+#define ADC0_SQR2_SQ11_Pos (0UL) /*!< SQ11 (Bit 0) */
+#define ADC0_SQR2_SQ11_Msk (0x1fUL) /*!< SQ11 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR3 ========================================================== */
+#define ADC0_SQR3_SQ16_Pos (0UL) /*!< SQ16 (Bit 0) */
+#define ADC0_SQR3_SQ16_Msk (0x1fUL) /*!< SQ16 (Bitfield-Mask: 0x1f) */
+/* ========================================================== LR =========================================================== */
+#define ADC0_LR_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define ADC0_LR_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define ADC0_LR_EXTEN_Pos (6UL) /*!< EXTEN (Bit 6) */
+#define ADC0_LR_EXTEN_Msk (0xc0UL) /*!< EXTEN (Bitfield-Mask: 0x03) */
+#define ADC0_LR_EXTSEL_Pos (0UL) /*!< EXTSEL (Bit 0) */
+#define ADC0_LR_EXTSEL_Msk (0x1fUL) /*!< EXTSEL (Bitfield-Mask: 0x1f) */
+/* ========================================================== DR =========================================================== */
+#define ADC0_DR_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */
+#define ADC0_DR_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MAXDR ========================================================= */
+#define ADC0_MAXDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC0_MAXDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MINDR ========================================================= */
+#define ADC0_MINDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC0_MINDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JSQR ========================================================== */
+#define ADC0_JSQR_JSQ4_Pos (18UL) /*!< JSQ4 (Bit 18) */
+#define ADC0_JSQR_JSQ4_Msk (0x7c0000UL) /*!< JSQ4 (Bitfield-Mask: 0x1f) */
+#define ADC0_JSQR_JSQ3_Pos (12UL) /*!< JSQ3 (Bit 12) */
+#define ADC0_JSQR_JSQ3_Msk (0x1f000UL) /*!< JSQ3 (Bitfield-Mask: 0x1f) */
+#define ADC0_JSQR_JSQ2_Pos (6UL) /*!< JSQ2 (Bit 6) */
+#define ADC0_JSQR_JSQ2_Msk (0x7c0UL) /*!< JSQ2 (Bitfield-Mask: 0x1f) */
+#define ADC0_JSQR_JSQ1_Pos (0UL) /*!< JSQ1 (Bit 0) */
+#define ADC0_JSQR_JSQ1_Msk (0x1fUL) /*!< JSQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================== JLR ========================================================== */
+#define ADC0_JLR_JLEN_Pos (8UL) /*!< JLEN (Bit 8) */
+#define ADC0_JLR_JLEN_Msk (0x300UL) /*!< JLEN (Bitfield-Mask: 0x03) */
+#define ADC0_JLR_JEXTEN_Pos (6UL) /*!< JEXTEN (Bit 6) */
+#define ADC0_JLR_JEXTEN_Msk (0xc0UL) /*!< JEXTEN (Bitfield-Mask: 0x03) */
+#define ADC0_JLR_JEXTSEL_Pos (0UL) /*!< JEXTSEL (Bit 0) */
+#define ADC0_JLR_JEXTSEL_Msk (0x1fUL) /*!< JEXTSEL (Bitfield-Mask: 0x1f) */
+/* ======================================================== MAXJDR ========================================================= */
+#define ADC0_MAXJDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC0_MAXJDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ======================================================== MINJDR ========================================================= */
+#define ADC0_MINJDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC0_MINJDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR0 ========================================================== */
+#define ADC0_JDR0_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC0_JDR0_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR1 ========================================================== */
+#define ADC0_JDR1_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC0_JDR1_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR2 ========================================================== */
+#define ADC0_JDR2_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC0_JDR2_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR3 ========================================================== */
+#define ADC0_JDR3_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC0_JDR3_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR0 ========================================================== */
+#define ADC0_TR0_HT0_Pos (16UL) /*!< HT0 (Bit 16) */
+#define ADC0_TR0_HT0_Msk (0xffff0000UL) /*!< HT0 (Bitfield-Mask: 0xffff) */
+#define ADC0_TR0_LT0_Pos (0UL) /*!< LT0 (Bit 0) */
+#define ADC0_TR0_LT0_Msk (0xffffUL) /*!< LT0 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR1 ========================================================== */
+#define ADC0_TR1_HT1_Pos (16UL) /*!< HT1 (Bit 16) */
+#define ADC0_TR1_HT1_Msk (0xffff0000UL) /*!< HT1 (Bitfield-Mask: 0xffff) */
+#define ADC0_TR1_LT1_Pos (0UL) /*!< LT1 (Bit 0) */
+#define ADC0_TR1_LT1_Msk (0xffffUL) /*!< LT1 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR2 ========================================================== */
+#define ADC0_TR2_HT2_Pos (16UL) /*!< HT2 (Bit 16) */
+#define ADC0_TR2_HT2_Msk (0xffff0000UL) /*!< HT2 (Bitfield-Mask: 0xffff) */
+#define ADC0_TR2_LT2_Pos (0UL) /*!< LT2 (Bit 0) */
+#define ADC0_TR2_LT2_Msk (0xffffUL) /*!< LT2 (Bitfield-Mask: 0xffff) */
+/* ======================================================== AWD0CR ========================================================= */
+#define ADC0_AWD0CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC0_AWD0CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC0_AWD0CR_AW0CH_Pos (0UL) /*!< AW0CH (Bit 0) */
+#define ADC0_AWD0CR_AW0CH_Msk (0xfffffUL) /*!< AW0CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD1CR ========================================================= */
+#define ADC0_AWD1CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC0_AWD1CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC0_AWD1CR_AW1CH_Pos (0UL) /*!< AW1CH (Bit 0) */
+#define ADC0_AWD1CR_AW1CH_Msk (0xfffffUL) /*!< AW1CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD2CR ========================================================= */
+#define ADC0_AWD2CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC0_AWD2CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC0_AWD2CR_AW2CH_Pos (0UL) /*!< AW2CH (Bit 0) */
+#define ADC0_AWD2CR_AW2CH_Msk (0xfffffUL) /*!< AW2CH (Bitfield-Mask: 0xfffff) */
+/* ========================================================= OFR0 ========================================================== */
+#define ADC0_OFR0_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC0_OFR0_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR1 ========================================================== */
+#define ADC0_OFR1_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC0_OFR1_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR2 ========================================================== */
+#define ADC0_OFR2_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC0_OFR2_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR3 ========================================================== */
+#define ADC0_OFR3_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC0_OFR3_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= GCR0 ========================================================== */
+#define ADC0_GCR0_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC0_GCR0_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR1 ========================================================== */
+#define ADC0_GCR1_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC0_GCR1_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR2 ========================================================== */
+#define ADC0_GCR2_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC0_GCR2_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR3 ========================================================== */
+#define ADC0_GCR3_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC0_GCR3_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= DISR ========================================================== */
+#define ADC0_DISR_DON19_Pos (19UL) /*!< DON19 (Bit 19) */
+#define ADC0_DISR_DON19_Msk (0x80000UL) /*!< DON19 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON18_Pos (18UL) /*!< DON18 (Bit 18) */
+#define ADC0_DISR_DON18_Msk (0x40000UL) /*!< DON18 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON17_Pos (17UL) /*!< DON17 (Bit 17) */
+#define ADC0_DISR_DON17_Msk (0x20000UL) /*!< DON17 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON16_Pos (16UL) /*!< DON16 (Bit 16) */
+#define ADC0_DISR_DON16_Msk (0x10000UL) /*!< DON16 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON15_Pos (15UL) /*!< DON15 (Bit 15) */
+#define ADC0_DISR_DON15_Msk (0x8000UL) /*!< DON15 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON14_Pos (14UL) /*!< DON14 (Bit 14) */
+#define ADC0_DISR_DON14_Msk (0x4000UL) /*!< DON14 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON13_Pos (13UL) /*!< DON13 (Bit 13) */
+#define ADC0_DISR_DON13_Msk (0x2000UL) /*!< DON13 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON12_Pos (12UL) /*!< DON12 (Bit 12) */
+#define ADC0_DISR_DON12_Msk (0x1000UL) /*!< DON12 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON11_Pos (11UL) /*!< DON11 (Bit 11) */
+#define ADC0_DISR_DON11_Msk (0x800UL) /*!< DON11 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON10_Pos (10UL) /*!< DON10 (Bit 10) */
+#define ADC0_DISR_DON10_Msk (0x400UL) /*!< DON10 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON9_Pos (9UL) /*!< DON9 (Bit 9) */
+#define ADC0_DISR_DON9_Msk (0x200UL) /*!< DON9 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON8_Pos (8UL) /*!< DON8 (Bit 8) */
+#define ADC0_DISR_DON8_Msk (0x100UL) /*!< DON8 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON7_Pos (7UL) /*!< DON7 (Bit 7) */
+#define ADC0_DISR_DON7_Msk (0x80UL) /*!< DON7 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON6_Pos (6UL) /*!< DON6 (Bit 6) */
+#define ADC0_DISR_DON6_Msk (0x40UL) /*!< DON6 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON5_Pos (5UL) /*!< DON5 (Bit 5) */
+#define ADC0_DISR_DON5_Msk (0x20UL) /*!< DON5 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON4_Pos (4UL) /*!< DON4 (Bit 4) */
+#define ADC0_DISR_DON4_Msk (0x10UL) /*!< DON4 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON3_Pos (3UL) /*!< DON3 (Bit 3) */
+#define ADC0_DISR_DON3_Msk (0x8UL) /*!< DON3 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON2_Pos (2UL) /*!< DON2 (Bit 2) */
+#define ADC0_DISR_DON2_Msk (0x4UL) /*!< DON2 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON1_Pos (1UL) /*!< DON1 (Bit 1) */
+#define ADC0_DISR_DON1_Msk (0x2UL) /*!< DON1 (Bitfield-Mask: 0x01) */
+#define ADC0_DISR_DON0_Pos (0UL) /*!< DON0 (Bit 0) */
+#define ADC0_DISR_DON0_Msk (0x1UL) /*!< DON0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DIER ========================================================== */
+#define ADC0_DIER_DONIE19_Pos (19UL) /*!< DONIE19 (Bit 19) */
+#define ADC0_DIER_DONIE19_Msk (0x80000UL) /*!< DONIE19 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE18_Pos (18UL) /*!< DONIE18 (Bit 18) */
+#define ADC0_DIER_DONIE18_Msk (0x40000UL) /*!< DONIE18 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE17_Pos (17UL) /*!< DONIE17 (Bit 17) */
+#define ADC0_DIER_DONIE17_Msk (0x20000UL) /*!< DONIE17 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE16_Pos (16UL) /*!< DONIE16 (Bit 16) */
+#define ADC0_DIER_DONIE16_Msk (0x10000UL) /*!< DONIE16 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE15_Pos (15UL) /*!< DONIE15 (Bit 15) */
+#define ADC0_DIER_DONIE15_Msk (0x8000UL) /*!< DONIE15 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE14_Pos (14UL) /*!< DONIE14 (Bit 14) */
+#define ADC0_DIER_DONIE14_Msk (0x4000UL) /*!< DONIE14 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE13_Pos (13UL) /*!< DONIE13 (Bit 13) */
+#define ADC0_DIER_DONIE13_Msk (0x2000UL) /*!< DONIE13 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE12_Pos (12UL) /*!< DONIE12 (Bit 12) */
+#define ADC0_DIER_DONIE12_Msk (0x1000UL) /*!< DONIE12 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE11_Pos (11UL) /*!< DONIE11 (Bit 11) */
+#define ADC0_DIER_DONIE11_Msk (0x800UL) /*!< DONIE11 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE10_Pos (10UL) /*!< DONIE10 (Bit 10) */
+#define ADC0_DIER_DONIE10_Msk (0x400UL) /*!< DONIE10 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE9_Pos (9UL) /*!< DONIE9 (Bit 9) */
+#define ADC0_DIER_DONIE9_Msk (0x200UL) /*!< DONIE9 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE8_Pos (8UL) /*!< DONIE8 (Bit 8) */
+#define ADC0_DIER_DONIE8_Msk (0x100UL) /*!< DONIE8 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE7_Pos (7UL) /*!< DONIE7 (Bit 7) */
+#define ADC0_DIER_DONIE7_Msk (0x80UL) /*!< DONIE7 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE6_Pos (6UL) /*!< DONIE6 (Bit 6) */
+#define ADC0_DIER_DONIE6_Msk (0x40UL) /*!< DONIE6 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE5_Pos (5UL) /*!< DONIE5 (Bit 5) */
+#define ADC0_DIER_DONIE5_Msk (0x20UL) /*!< DONIE5 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE4_Pos (4UL) /*!< DONIE4 (Bit 4) */
+#define ADC0_DIER_DONIE4_Msk (0x10UL) /*!< DONIE4 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE3_Pos (3UL) /*!< DONIE3 (Bit 3) */
+#define ADC0_DIER_DONIE3_Msk (0x8UL) /*!< DONIE3 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE2_Pos (2UL) /*!< DONIE2 (Bit 2) */
+#define ADC0_DIER_DONIE2_Msk (0x4UL) /*!< DONIE2 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE1_Pos (1UL) /*!< DONIE1 (Bit 1) */
+#define ADC0_DIER_DONIE1_Msk (0x2UL) /*!< DONIE1 (Bitfield-Mask: 0x01) */
+#define ADC0_DIER_DONIE0_Pos (0UL) /*!< DONIE0 (Bit 0) */
+#define ADC0_DIER_DONIE0_Msk (0x1UL) /*!< DONIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= CDR0 ========================================================== */
+#define ADC0_CDR0_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR0_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR1 ========================================================== */
+#define ADC0_CDR1_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR1_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR2 ========================================================== */
+#define ADC0_CDR2_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR2_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR3 ========================================================== */
+#define ADC0_CDR3_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR3_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR4 ========================================================== */
+#define ADC0_CDR4_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR4_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR5 ========================================================== */
+#define ADC0_CDR5_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR5_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR6 ========================================================== */
+#define ADC0_CDR6_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR6_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR7 ========================================================== */
+#define ADC0_CDR7_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR7_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR8 ========================================================== */
+#define ADC0_CDR8_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR8_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR9 ========================================================== */
+#define ADC0_CDR9_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR9_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR10 ========================================================= */
+#define ADC0_CDR10_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR10_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR11 ========================================================= */
+#define ADC0_CDR11_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR11_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR12 ========================================================= */
+#define ADC0_CDR12_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR12_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR13 ========================================================= */
+#define ADC0_CDR13_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR13_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR14 ========================================================= */
+#define ADC0_CDR14_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR14_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR15 ========================================================= */
+#define ADC0_CDR15_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR15_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR16 ========================================================= */
+#define ADC0_CDR16_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR16_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR17 ========================================================= */
+#define ADC0_CDR17_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR17_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR18 ========================================================= */
+#define ADC0_CDR18_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR18_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR19 ========================================================= */
+#define ADC0_CDR19_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC0_CDR19_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= HISR ========================================================== */
+#define ADC0_HISR_HLF19_Pos (19UL) /*!< HLF19 (Bit 19) */
+#define ADC0_HISR_HLF19_Msk (0x80000UL) /*!< HLF19 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF18_Pos (18UL) /*!< HLF18 (Bit 18) */
+#define ADC0_HISR_HLF18_Msk (0x40000UL) /*!< HLF18 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF17_Pos (17UL) /*!< HLF17 (Bit 17) */
+#define ADC0_HISR_HLF17_Msk (0x20000UL) /*!< HLF17 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF16_Pos (16UL) /*!< HLF16 (Bit 16) */
+#define ADC0_HISR_HLF16_Msk (0x10000UL) /*!< HLF16 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF15_Pos (15UL) /*!< HLF15 (Bit 15) */
+#define ADC0_HISR_HLF15_Msk (0x8000UL) /*!< HLF15 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF14_Pos (14UL) /*!< HLF14 (Bit 14) */
+#define ADC0_HISR_HLF14_Msk (0x4000UL) /*!< HLF14 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF13_Pos (13UL) /*!< HLF13 (Bit 13) */
+#define ADC0_HISR_HLF13_Msk (0x2000UL) /*!< HLF13 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF12_Pos (12UL) /*!< HLF12 (Bit 12) */
+#define ADC0_HISR_HLF12_Msk (0x1000UL) /*!< HLF12 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF11_Pos (11UL) /*!< HLF11 (Bit 11) */
+#define ADC0_HISR_HLF11_Msk (0x800UL) /*!< HLF11 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF10_Pos (10UL) /*!< HLF10 (Bit 10) */
+#define ADC0_HISR_HLF10_Msk (0x400UL) /*!< HLF10 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF9_Pos (9UL) /*!< HLF9 (Bit 9) */
+#define ADC0_HISR_HLF9_Msk (0x200UL) /*!< HLF9 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF8_Pos (8UL) /*!< HLF8 (Bit 8) */
+#define ADC0_HISR_HLF8_Msk (0x100UL) /*!< HLF8 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF7_Pos (7UL) /*!< HLF7 (Bit 7) */
+#define ADC0_HISR_HLF7_Msk (0x80UL) /*!< HLF7 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF6_Pos (6UL) /*!< HLF6 (Bit 6) */
+#define ADC0_HISR_HLF6_Msk (0x40UL) /*!< HLF6 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF5_Pos (5UL) /*!< HLF5 (Bit 5) */
+#define ADC0_HISR_HLF5_Msk (0x20UL) /*!< HLF5 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF4_Pos (4UL) /*!< HLF4 (Bit 4) */
+#define ADC0_HISR_HLF4_Msk (0x10UL) /*!< HLF4 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF3_Pos (3UL) /*!< HLF3 (Bit 3) */
+#define ADC0_HISR_HLF3_Msk (0x8UL) /*!< HLF3 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF2_Pos (2UL) /*!< HLF2 (Bit 2) */
+#define ADC0_HISR_HLF2_Msk (0x4UL) /*!< HLF2 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF1_Pos (1UL) /*!< HLF1 (Bit 1) */
+#define ADC0_HISR_HLF1_Msk (0x2UL) /*!< HLF1 (Bitfield-Mask: 0x01) */
+#define ADC0_HISR_HLF0_Pos (0UL) /*!< HLF0 (Bit 0) */
+#define ADC0_HISR_HLF0_Msk (0x1UL) /*!< HLF0 (Bitfield-Mask: 0x01) */
+/* ========================================================= HIER ========================================================== */
+#define ADC0_HIER_HLFIE19_Pos (19UL) /*!< HLFIE19 (Bit 19) */
+#define ADC0_HIER_HLFIE19_Msk (0x80000UL) /*!< HLFIE19 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE18_Pos (18UL) /*!< HLFIE18 (Bit 18) */
+#define ADC0_HIER_HLFIE18_Msk (0x40000UL) /*!< HLFIE18 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE17_Pos (17UL) /*!< HLFIE17 (Bit 17) */
+#define ADC0_HIER_HLFIE17_Msk (0x20000UL) /*!< HLFIE17 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE16_Pos (16UL) /*!< HLFIE16 (Bit 16) */
+#define ADC0_HIER_HLFIE16_Msk (0x10000UL) /*!< HLFIE16 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE15_Pos (15UL) /*!< HLFIE15 (Bit 15) */
+#define ADC0_HIER_HLFIE15_Msk (0x8000UL) /*!< HLFIE15 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE14_Pos (14UL) /*!< HLFIE14 (Bit 14) */
+#define ADC0_HIER_HLFIE14_Msk (0x4000UL) /*!< HLFIE14 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE13_Pos (13UL) /*!< HLFIE13 (Bit 13) */
+#define ADC0_HIER_HLFIE13_Msk (0x2000UL) /*!< HLFIE13 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE12_Pos (12UL) /*!< HLFIE12 (Bit 12) */
+#define ADC0_HIER_HLFIE12_Msk (0x1000UL) /*!< HLFIE12 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE11_Pos (11UL) /*!< HLFIE11 (Bit 11) */
+#define ADC0_HIER_HLFIE11_Msk (0x800UL) /*!< HLFIE11 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE10_Pos (10UL) /*!< HLFIE10 (Bit 10) */
+#define ADC0_HIER_HLFIE10_Msk (0x400UL) /*!< HLFIE10 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE9_Pos (9UL) /*!< HLFIE9 (Bit 9) */
+#define ADC0_HIER_HLFIE9_Msk (0x200UL) /*!< HLFIE9 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE8_Pos (8UL) /*!< HLFIE8 (Bit 8) */
+#define ADC0_HIER_HLFIE8_Msk (0x100UL) /*!< HLFIE8 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE7_Pos (7UL) /*!< HLFIE7 (Bit 7) */
+#define ADC0_HIER_HLFIE7_Msk (0x80UL) /*!< HLFIE7 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE6_Pos (6UL) /*!< HLFIE6 (Bit 6) */
+#define ADC0_HIER_HLFIE6_Msk (0x40UL) /*!< HLFIE6 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE5_Pos (5UL) /*!< HLFIE5 (Bit 5) */
+#define ADC0_HIER_HLFIE5_Msk (0x20UL) /*!< HLFIE5 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE4_Pos (4UL) /*!< HLFIE4 (Bit 4) */
+#define ADC0_HIER_HLFIE4_Msk (0x10UL) /*!< HLFIE4 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE3_Pos (3UL) /*!< HLFIE3 (Bit 3) */
+#define ADC0_HIER_HLFIE3_Msk (0x8UL) /*!< HLFIE3 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE2_Pos (2UL) /*!< HLFIE2 (Bit 2) */
+#define ADC0_HIER_HLFIE2_Msk (0x4UL) /*!< HLFIE2 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE1_Pos (1UL) /*!< HLFIE1 (Bit 1) */
+#define ADC0_HIER_HLFIE1_Msk (0x2UL) /*!< HLFIE1 (Bitfield-Mask: 0x01) */
+#define ADC0_HIER_HLFIE0_Pos (0UL) /*!< HLFIE0 (Bit 0) */
+#define ADC0_HIER_HLFIE0_Msk (0x1UL) /*!< HLFIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FISR ========================================================== */
+#define ADC0_FISR_FUL19_Pos (19UL) /*!< FUL19 (Bit 19) */
+#define ADC0_FISR_FUL19_Msk (0x80000UL) /*!< FUL19 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL18_Pos (18UL) /*!< FUL18 (Bit 18) */
+#define ADC0_FISR_FUL18_Msk (0x40000UL) /*!< FUL18 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL17_Pos (17UL) /*!< FUL17 (Bit 17) */
+#define ADC0_FISR_FUL17_Msk (0x20000UL) /*!< FUL17 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL16_Pos (16UL) /*!< FUL16 (Bit 16) */
+#define ADC0_FISR_FUL16_Msk (0x10000UL) /*!< FUL16 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL15_Pos (15UL) /*!< FUL15 (Bit 15) */
+#define ADC0_FISR_FUL15_Msk (0x8000UL) /*!< FUL15 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL14_Pos (14UL) /*!< FUL14 (Bit 14) */
+#define ADC0_FISR_FUL14_Msk (0x4000UL) /*!< FUL14 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL13_Pos (13UL) /*!< FUL13 (Bit 13) */
+#define ADC0_FISR_FUL13_Msk (0x2000UL) /*!< FUL13 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL12_Pos (12UL) /*!< FUL12 (Bit 12) */
+#define ADC0_FISR_FUL12_Msk (0x1000UL) /*!< FUL12 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL11_Pos (11UL) /*!< FUL11 (Bit 11) */
+#define ADC0_FISR_FUL11_Msk (0x800UL) /*!< FUL11 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL10_Pos (10UL) /*!< FUL10 (Bit 10) */
+#define ADC0_FISR_FUL10_Msk (0x400UL) /*!< FUL10 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL9_Pos (9UL) /*!< FUL9 (Bit 9) */
+#define ADC0_FISR_FUL9_Msk (0x200UL) /*!< FUL9 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL8_Pos (8UL) /*!< FUL8 (Bit 8) */
+#define ADC0_FISR_FUL8_Msk (0x100UL) /*!< FUL8 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL7_Pos (7UL) /*!< FUL7 (Bit 7) */
+#define ADC0_FISR_FUL7_Msk (0x80UL) /*!< FUL7 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL6_Pos (6UL) /*!< FUL6 (Bit 6) */
+#define ADC0_FISR_FUL6_Msk (0x40UL) /*!< FUL6 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL5_Pos (5UL) /*!< FUL5 (Bit 5) */
+#define ADC0_FISR_FUL5_Msk (0x20UL) /*!< FUL5 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL4_Pos (4UL) /*!< FUL4 (Bit 4) */
+#define ADC0_FISR_FUL4_Msk (0x10UL) /*!< FUL4 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL3_Pos (3UL) /*!< FUL3 (Bit 3) */
+#define ADC0_FISR_FUL3_Msk (0x8UL) /*!< FUL3 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL2_Pos (2UL) /*!< FUL2 (Bit 2) */
+#define ADC0_FISR_FUL2_Msk (0x4UL) /*!< FUL2 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL1_Pos (1UL) /*!< FUL1 (Bit 1) */
+#define ADC0_FISR_FUL1_Msk (0x2UL) /*!< FUL1 (Bitfield-Mask: 0x01) */
+#define ADC0_FISR_FUL0_Pos (0UL) /*!< FUL0 (Bit 0) */
+#define ADC0_FISR_FUL0_Msk (0x1UL) /*!< FUL0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FIER ========================================================== */
+#define ADC0_FIER_FULIE19_Pos (19UL) /*!< FULIE19 (Bit 19) */
+#define ADC0_FIER_FULIE19_Msk (0x80000UL) /*!< FULIE19 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE18_Pos (18UL) /*!< FULIE18 (Bit 18) */
+#define ADC0_FIER_FULIE18_Msk (0x40000UL) /*!< FULIE18 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE17_Pos (17UL) /*!< FULIE17 (Bit 17) */
+#define ADC0_FIER_FULIE17_Msk (0x20000UL) /*!< FULIE17 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE16_Pos (16UL) /*!< FULIE16 (Bit 16) */
+#define ADC0_FIER_FULIE16_Msk (0x10000UL) /*!< FULIE16 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE15_Pos (15UL) /*!< FULIE15 (Bit 15) */
+#define ADC0_FIER_FULIE15_Msk (0x8000UL) /*!< FULIE15 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE14_Pos (14UL) /*!< FULIE14 (Bit 14) */
+#define ADC0_FIER_FULIE14_Msk (0x4000UL) /*!< FULIE14 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE13_Pos (13UL) /*!< FULIE13 (Bit 13) */
+#define ADC0_FIER_FULIE13_Msk (0x2000UL) /*!< FULIE13 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE12_Pos (12UL) /*!< FULIE12 (Bit 12) */
+#define ADC0_FIER_FULIE12_Msk (0x1000UL) /*!< FULIE12 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE11_Pos (11UL) /*!< FULIE11 (Bit 11) */
+#define ADC0_FIER_FULIE11_Msk (0x800UL) /*!< FULIE11 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE10_Pos (10UL) /*!< FULIE10 (Bit 10) */
+#define ADC0_FIER_FULIE10_Msk (0x400UL) /*!< FULIE10 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE9_Pos (9UL) /*!< FULIE9 (Bit 9) */
+#define ADC0_FIER_FULIE9_Msk (0x200UL) /*!< FULIE9 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE8_Pos (8UL) /*!< FULIE8 (Bit 8) */
+#define ADC0_FIER_FULIE8_Msk (0x100UL) /*!< FULIE8 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE7_Pos (7UL) /*!< FULIE7 (Bit 7) */
+#define ADC0_FIER_FULIE7_Msk (0x80UL) /*!< FULIE7 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE6_Pos (6UL) /*!< FULIE6 (Bit 6) */
+#define ADC0_FIER_FULIE6_Msk (0x40UL) /*!< FULIE6 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE5_Pos (5UL) /*!< FULIE5 (Bit 5) */
+#define ADC0_FIER_FULIE5_Msk (0x20UL) /*!< FULIE5 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE4_Pos (4UL) /*!< FULIE4 (Bit 4) */
+#define ADC0_FIER_FULIE4_Msk (0x10UL) /*!< FULIE4 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE3_Pos (3UL) /*!< FULIE3 (Bit 3) */
+#define ADC0_FIER_FULIE3_Msk (0x8UL) /*!< FULIE3 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE2_Pos (2UL) /*!< FULIE2 (Bit 2) */
+#define ADC0_FIER_FULIE2_Msk (0x4UL) /*!< FULIE2 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE1_Pos (1UL) /*!< FULIE1 (Bit 1) */
+#define ADC0_FIER_FULIE1_Msk (0x2UL) /*!< FULIE1 (Bitfield-Mask: 0x01) */
+#define ADC0_FIER_FULIE0_Pos (0UL) /*!< FULIE0 (Bit 0) */
+#define ADC0_FIER_FULIE0_Msk (0x1UL) /*!< FULIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= TCR0 ========================================================== */
+#define ADC0_TCR0_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR0_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR0_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR0_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR0_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR0_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR0_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR0 ========================================================== */
+#define ADC0_TAR0_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR0_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR0 ========================================================== */
+#define ADC0_TLR0_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR0_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR1 ========================================================== */
+#define ADC0_TCR1_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR1_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR1_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR1_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR1_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR1_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR1_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR1 ========================================================== */
+#define ADC0_TAR1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR1_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR1 ========================================================== */
+#define ADC0_TLR1_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR1_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR2 ========================================================== */
+#define ADC0_TCR2_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR2_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR2_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR2_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR2_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR2_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR2_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR2 ========================================================== */
+#define ADC0_TAR2_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR2_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR2 ========================================================== */
+#define ADC0_TLR2_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR2_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR3 ========================================================== */
+#define ADC0_TCR3_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR3_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR3_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR3_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR3_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR3_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR3_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR3 ========================================================== */
+#define ADC0_TAR3_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR3_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR3 ========================================================== */
+#define ADC0_TLR3_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR3_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR4 ========================================================== */
+#define ADC0_TCR4_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR4_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR4_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR4_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR4_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR4_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR4_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR4_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR4 ========================================================== */
+#define ADC0_TAR4_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR4_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR4 ========================================================== */
+#define ADC0_TLR4_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR4_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR5 ========================================================== */
+#define ADC0_TCR5_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR5_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR5_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR5_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR5_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR5_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR5_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR5_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR5 ========================================================== */
+#define ADC0_TAR5_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR5_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR5 ========================================================== */
+#define ADC0_TLR5_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR5_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR6 ========================================================== */
+#define ADC0_TCR6_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR6_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR6_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR6_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR6_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR6_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR6_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR6_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR6 ========================================================== */
+#define ADC0_TAR6_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR6_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR6 ========================================================== */
+#define ADC0_TLR6_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR6_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR7 ========================================================== */
+#define ADC0_TCR7_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR7_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR7_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR7_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR7_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR7_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR7_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR7_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR7 ========================================================== */
+#define ADC0_TAR7_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR7_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR7 ========================================================== */
+#define ADC0_TLR7_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR7_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR8 ========================================================== */
+#define ADC0_TCR8_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR8_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR8_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR8_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR8_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR8_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR8_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR8_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR8 ========================================================== */
+#define ADC0_TAR8_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR8_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR8 ========================================================== */
+#define ADC0_TLR8_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR8_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR9 ========================================================== */
+#define ADC0_TCR9_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR9_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR9_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR9_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR9_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR9_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR9_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR9_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR9 ========================================================== */
+#define ADC0_TAR9_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR9_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR9 ========================================================== */
+#define ADC0_TLR9_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR9_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR10 ========================================================= */
+#define ADC0_TCR10_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR10_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR10_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR10_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR10_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR10_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR10_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR10_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR10 ========================================================= */
+#define ADC0_TAR10_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR10_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR10 ========================================================= */
+#define ADC0_TLR10_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR10_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR11 ========================================================= */
+#define ADC0_TCR11_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR11_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR11_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR11_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR11_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR11_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR11_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR11_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR11 ========================================================= */
+#define ADC0_TAR11_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR11_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR11 ========================================================= */
+#define ADC0_TLR11_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR11_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR12 ========================================================= */
+#define ADC0_TCR12_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR12_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR12_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR12_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR12_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR12_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR12_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR12_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR12 ========================================================= */
+#define ADC0_TAR12_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR12_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR12 ========================================================= */
+#define ADC0_TLR12_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR12_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR13 ========================================================= */
+#define ADC0_TCR13_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR13_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR13_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR13_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR13_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR13_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR13_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR13_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR13 ========================================================= */
+#define ADC0_TAR13_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR13_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR13 ========================================================= */
+#define ADC0_TLR13_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR13_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR14 ========================================================= */
+#define ADC0_TCR14_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR14_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR14_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR14_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR14_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR14_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR14_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR14_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR14 ========================================================= */
+#define ADC0_TAR14_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR14_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR14 ========================================================= */
+#define ADC0_TLR14_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR14_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR15 ========================================================= */
+#define ADC0_TCR15_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR15_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR15_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR15_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR15_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR15_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR15_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR15_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR15 ========================================================= */
+#define ADC0_TAR15_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR15_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR15 ========================================================= */
+#define ADC0_TLR15_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR15_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR16 ========================================================= */
+#define ADC0_TCR16_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR16_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR16_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR16_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR16_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR16_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR16_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR16_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR16 ========================================================= */
+#define ADC0_TAR16_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR16_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR16 ========================================================= */
+#define ADC0_TLR16_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR16_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR17 ========================================================= */
+#define ADC0_TCR17_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR17_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR17_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR17_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR17_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR17_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR17_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR17_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR17 ========================================================= */
+#define ADC0_TAR17_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR17_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR17 ========================================================= */
+#define ADC0_TLR17_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR17_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR18 ========================================================= */
+#define ADC0_TCR18_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR18_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR18_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR18_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR18_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR18_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR18_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR18_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR18 ========================================================= */
+#define ADC0_TAR18_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR18_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR18 ========================================================= */
+#define ADC0_TLR18_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR18_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR19 ========================================================= */
+#define ADC0_TCR19_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC0_TCR19_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC0_TCR19_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC0_TCR19_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC0_TCR19_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC0_TCR19_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC0_TCR19_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC0_TCR19_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR19 ========================================================= */
+#define ADC0_TAR19_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC0_TAR19_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR19 ========================================================= */
+#define ADC0_TLR19_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC0_TLR19_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================== CCR ========================================================== */
+#define ADC0_CCR_DELAY_Pos (8UL) /*!< DELAY (Bit 8) */
+#define ADC0_CCR_DELAY_Msk (0x3ff00UL) /*!< DELAY (Bitfield-Mask: 0x3ff) */
+#define ADC0_CCR_DUAL_Pos (0UL) /*!< DUAL (Bit 0) */
+#define ADC0_CCR_DUAL_Msk (0xfUL) /*!< DUAL (Bitfield-Mask: 0x0f) */
+/* ========================================================== CSR ========================================================== */
+#define ADC0_CSR_EOSMP_SLV_Pos (25UL) /*!< EOSMP_SLV (Bit 25) */
+#define ADC0_CSR_EOSMP_SLV_Msk (0x2000000UL) /*!< EOSMP_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_ADRDY_SLV_Pos (24UL) /*!< ADRDY_SLV (Bit 24) */
+#define ADC0_CSR_ADRDY_SLV_Msk (0x1000000UL) /*!< ADRDY_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD2_SLV_Pos (23UL) /*!< AWD2_SLV (Bit 23) */
+#define ADC0_CSR_AWD2_SLV_Msk (0x800000UL) /*!< AWD2_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD1_SLV_Pos (22UL) /*!< AWD1_SLV (Bit 22) */
+#define ADC0_CSR_AWD1_SLV_Msk (0x400000UL) /*!< AWD1_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD0_SLV_Pos (21UL) /*!< AWD0_SLV (Bit 21) */
+#define ADC0_CSR_AWD0_SLV_Msk (0x200000UL) /*!< AWD0_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_OVR_SLV_Pos (20UL) /*!< OVR_SLV (Bit 20) */
+#define ADC0_CSR_OVR_SLV_Msk (0x100000UL) /*!< OVR_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_JEOS_SLV_Pos (19UL) /*!< JEOS_SLV (Bit 19) */
+#define ADC0_CSR_JEOS_SLV_Msk (0x80000UL) /*!< JEOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_JEOC_SLV_Pos (18UL) /*!< JEOC_SLV (Bit 18) */
+#define ADC0_CSR_JEOC_SLV_Msk (0x40000UL) /*!< JEOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_EOS_SLV_Pos (17UL) /*!< EOS_SLV (Bit 17) */
+#define ADC0_CSR_EOS_SLV_Msk (0x20000UL) /*!< EOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_EOC_SLV_Pos (16UL) /*!< EOC_SLV (Bit 16) */
+#define ADC0_CSR_EOC_SLV_Msk (0x10000UL) /*!< EOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_EOSMP_MST_Pos (9UL) /*!< EOSMP_MST (Bit 9) */
+#define ADC0_CSR_EOSMP_MST_Msk (0x200UL) /*!< EOSMP_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_ADRDY_MST_Pos (8UL) /*!< ADRDY_MST (Bit 8) */
+#define ADC0_CSR_ADRDY_MST_Msk (0x100UL) /*!< ADRDY_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD2_MST_Pos (7UL) /*!< AWD2_MST (Bit 7) */
+#define ADC0_CSR_AWD2_MST_Msk (0x80UL) /*!< AWD2_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD1_MST_Pos (6UL) /*!< AWD1_MST (Bit 6) */
+#define ADC0_CSR_AWD1_MST_Msk (0x40UL) /*!< AWD1_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_AWD0_MST_Pos (5UL) /*!< AWD0_MST (Bit 5) */
+#define ADC0_CSR_AWD0_MST_Msk (0x20UL) /*!< AWD0_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_OVR_MST_Pos (4UL) /*!< OVR_MST (Bit 4) */
+#define ADC0_CSR_OVR_MST_Msk (0x10UL) /*!< OVR_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_JEOS_MST_Pos (3UL) /*!< JEOS_MST (Bit 3) */
+#define ADC0_CSR_JEOS_MST_Msk (0x8UL) /*!< JEOS_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_JEOC_MST_Pos (2UL) /*!< JEOC_MST (Bit 2) */
+#define ADC0_CSR_JEOC_MST_Msk (0x4UL) /*!< JEOC_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_EOS_MST_Pos (1UL) /*!< EOS_MST (Bit 1) */
+#define ADC0_CSR_EOS_MST_Msk (0x2UL) /*!< EOS_MST (Bitfield-Mask: 0x01) */
+#define ADC0_CSR_EOC_MST_Pos (0UL) /*!< EOC_MST (Bit 0) */
+#define ADC0_CSR_EOC_MST_Msk (0x1UL) /*!< EOC_MST (Bitfield-Mask: 0x01) */
+/* ========================================================== CDR ========================================================== */
+#define ADC0_CDR_RDATA_SLV_Pos (16UL) /*!< RDATA_SLV (Bit 16) */
+#define ADC0_CDR_RDATA_SLV_Msk (0xffff0000UL) /*!< RDATA_SLV (Bitfield-Mask: 0xffff) */
+#define ADC0_CDR_RDATA_MST_Pos (0UL) /*!< RDATA_MST (Bit 0) */
+#define ADC0_CDR_RDATA_MST_Msk (0xffffUL) /*!< RDATA_MST (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ ADC1 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define ADC1_CR_ADCALDIF_Pos (7UL) /*!< ADCALDIF (Bit 7) */
+#define ADC1_CR_ADCALDIF_Msk (0x80UL) /*!< ADCALDIF (Bitfield-Mask: 0x01) */
+#define ADC1_CR_ADCAL_Pos (6UL) /*!< ADCAL (Bit 6) */
+#define ADC1_CR_ADCAL_Msk (0x40UL) /*!< ADCAL (Bitfield-Mask: 0x01) */
+#define ADC1_CR_JADSTP_Pos (5UL) /*!< JADSTP (Bit 5) */
+#define ADC1_CR_JADSTP_Msk (0x20UL) /*!< JADSTP (Bitfield-Mask: 0x01) */
+#define ADC1_CR_ADSTP_Pos (4UL) /*!< ADSTP (Bit 4) */
+#define ADC1_CR_ADSTP_Msk (0x10UL) /*!< ADSTP (Bitfield-Mask: 0x01) */
+#define ADC1_CR_JADSTART_Pos (3UL) /*!< JADSTART (Bit 3) */
+#define ADC1_CR_JADSTART_Msk (0x8UL) /*!< JADSTART (Bitfield-Mask: 0x01) */
+#define ADC1_CR_ADSTART_Pos (2UL) /*!< ADSTART (Bit 2) */
+#define ADC1_CR_ADSTART_Msk (0x4UL) /*!< ADSTART (Bitfield-Mask: 0x01) */
+#define ADC1_CR_ADDIS_Pos (1UL) /*!< ADDIS (Bit 1) */
+#define ADC1_CR_ADDIS_Msk (0x2UL) /*!< ADDIS (Bitfield-Mask: 0x01) */
+#define ADC1_CR_ADEN_Pos (0UL) /*!< ADEN (Bit 0) */
+#define ADC1_CR_ADEN_Msk (0x1UL) /*!< ADEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR0 ========================================================= */
+#define ADC1_CFGR0_OVSCAL_Pos (28UL) /*!< OVSCAL (Bit 28) */
+#define ADC1_CFGR0_OVSCAL_Msk (0x70000000UL) /*!< OVSCAL (Bitfield-Mask: 0x07) */
+#define ADC1_CFGR0_CONT_Pos (23UL) /*!< CONT (Bit 23) */
+#define ADC1_CFGR0_CONT_Msk (0x800000UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_JAUTO_Pos (22UL) /*!< JAUTO (Bit 22) */
+#define ADC1_CFGR0_JAUTO_Msk (0x400000UL) /*!< JAUTO (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_JDISCEN_Pos (20UL) /*!< JDISCEN (Bit 20) */
+#define ADC1_CFGR0_JDISCEN_Msk (0x100000UL) /*!< JDISCEN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_DISCNUM_Pos (17UL) /*!< DISCNUM (Bit 17) */
+#define ADC1_CFGR0_DISCNUM_Msk (0xe0000UL) /*!< DISCNUM (Bitfield-Mask: 0x07) */
+#define ADC1_CFGR0_DISCEN_Pos (16UL) /*!< DISCEN (Bit 16) */
+#define ADC1_CFGR0_DISCEN_Msk (0x10000UL) /*!< DISCEN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_OVRMOD_Pos (15UL) /*!< OVRMOD (Bit 15) */
+#define ADC1_CFGR0_OVRMOD_Msk (0x8000UL) /*!< OVRMOD (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_SDMAEN_Pos (14UL) /*!< SDMAEN (Bit 14) */
+#define ADC1_CFGR0_SDMAEN_Msk (0x4000UL) /*!< SDMAEN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_TROVS_Pos (12UL) /*!< TROVS (Bit 12) */
+#define ADC1_CFGR0_TROVS_Msk (0x1000UL) /*!< TROVS (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_OVSS_Pos (8UL) /*!< OVSS (Bit 8) */
+#define ADC1_CFGR0_OVSS_Msk (0xf00UL) /*!< OVSS (Bitfield-Mask: 0x0f) */
+#define ADC1_CFGR0_ROVSM_Pos (7UL) /*!< ROVSM (Bit 7) */
+#define ADC1_CFGR0_ROVSM_Msk (0x80UL) /*!< ROVSM (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_OVSR_Pos (4UL) /*!< OVSR (Bit 4) */
+#define ADC1_CFGR0_OVSR_Msk (0x70UL) /*!< OVSR (Bitfield-Mask: 0x07) */
+#define ADC1_CFGR0_JOVSE_Pos (1UL) /*!< JOVSE (Bit 1) */
+#define ADC1_CFGR0_JOVSE_Msk (0x2UL) /*!< JOVSE (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR0_ROVSE_Pos (0UL) /*!< ROVSE (Bit 0) */
+#define ADC1_CFGR0_ROVSE_Msk (0x1UL) /*!< ROVSE (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR1 ========================================================= */
+#define ADC1_CFGR1_JAWD2EN_Pos (14UL) /*!< JAWD2EN (Bit 14) */
+#define ADC1_CFGR1_JAWD2EN_Msk (0x4000UL) /*!< JAWD2EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_JAWD1EN_Pos (13UL) /*!< JAWD1EN (Bit 13) */
+#define ADC1_CFGR1_JAWD1EN_Msk (0x2000UL) /*!< JAWD1EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_JAWD0EN_Pos (12UL) /*!< JAWD0EN (Bit 12) */
+#define ADC1_CFGR1_JAWD0EN_Msk (0x1000UL) /*!< JAWD0EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_AWD2EN_Pos (10UL) /*!< AWD2EN (Bit 10) */
+#define ADC1_CFGR1_AWD2EN_Msk (0x400UL) /*!< AWD2EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_AWD1EN_Pos (9UL) /*!< AWD1EN (Bit 9) */
+#define ADC1_CFGR1_AWD1EN_Msk (0x200UL) /*!< AWD1EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_AWD0EN_Pos (8UL) /*!< AWD0EN (Bit 8) */
+#define ADC1_CFGR1_AWD0EN_Msk (0x100UL) /*!< AWD0EN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_ISEL_Pos (4UL) /*!< ISEL (Bit 4) */
+#define ADC1_CFGR1_ISEL_Msk (0x30UL) /*!< ISEL (Bitfield-Mask: 0x03) */
+#define ADC1_CFGR1_CHEN_Pos (3UL) /*!< CHEN (Bit 3) */
+#define ADC1_CFGR1_CHEN_Msk (0x8UL) /*!< CHEN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_REFEN_Pos (1UL) /*!< REFEN (Bit 1) */
+#define ADC1_CFGR1_REFEN_Msk (0x2UL) /*!< REFEN (Bitfield-Mask: 0x01) */
+#define ADC1_CFGR1_BIASEN_Pos (0UL) /*!< BIASEN (Bit 0) */
+#define ADC1_CFGR1_BIASEN_Msk (0x1UL) /*!< BIASEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define ADC1_ISR_EOSMP_Pos (9UL) /*!< EOSMP (Bit 9) */
+#define ADC1_ISR_EOSMP_Msk (0x200UL) /*!< EOSMP (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_ADRDY_Pos (8UL) /*!< ADRDY (Bit 8) */
+#define ADC1_ISR_ADRDY_Msk (0x100UL) /*!< ADRDY (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_AWD2_Pos (7UL) /*!< AWD2 (Bit 7) */
+#define ADC1_ISR_AWD2_Msk (0x80UL) /*!< AWD2 (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_AWD1_Pos (6UL) /*!< AWD1 (Bit 6) */
+#define ADC1_ISR_AWD1_Msk (0x40UL) /*!< AWD1 (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_AWD0_Pos (5UL) /*!< AWD0 (Bit 5) */
+#define ADC1_ISR_AWD0_Msk (0x20UL) /*!< AWD0 (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_OVR_Pos (4UL) /*!< OVR (Bit 4) */
+#define ADC1_ISR_OVR_Msk (0x10UL) /*!< OVR (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_JEOS_Pos (3UL) /*!< JEOS (Bit 3) */
+#define ADC1_ISR_JEOS_Msk (0x8UL) /*!< JEOS (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_JEOC_Pos (2UL) /*!< JEOC (Bit 2) */
+#define ADC1_ISR_JEOC_Msk (0x4UL) /*!< JEOC (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */
+#define ADC1_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */
+#define ADC1_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */
+#define ADC1_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define ADC1_IER_EOSMPIE_Pos (9UL) /*!< EOSMPIE (Bit 9) */
+#define ADC1_IER_EOSMPIE_Msk (0x200UL) /*!< EOSMPIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_ADRDYIE_Pos (8UL) /*!< ADRDYIE (Bit 8) */
+#define ADC1_IER_ADRDYIE_Msk (0x100UL) /*!< ADRDYIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_AWD2IE_Pos (7UL) /*!< AWD2IE (Bit 7) */
+#define ADC1_IER_AWD2IE_Msk (0x80UL) /*!< AWD2IE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_AWD1IE_Pos (6UL) /*!< AWD1IE (Bit 6) */
+#define ADC1_IER_AWD1IE_Msk (0x40UL) /*!< AWD1IE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_AWD0IE_Pos (5UL) /*!< AWD0IE (Bit 5) */
+#define ADC1_IER_AWD0IE_Msk (0x20UL) /*!< AWD0IE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_OVRIE_Pos (4UL) /*!< OVRIE (Bit 4) */
+#define ADC1_IER_OVRIE_Msk (0x10UL) /*!< OVRIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_JEOSIE_Pos (3UL) /*!< JEOSIE (Bit 3) */
+#define ADC1_IER_JEOSIE_Msk (0x8UL) /*!< JEOSIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_JEOCIE_Pos (2UL) /*!< JEOCIE (Bit 2) */
+#define ADC1_IER_JEOCIE_Msk (0x4UL) /*!< JEOCIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_EOSIE_Pos (1UL) /*!< EOSIE (Bit 1) */
+#define ADC1_IER_EOSIE_Msk (0x2UL) /*!< EOSIE (Bitfield-Mask: 0x01) */
+#define ADC1_IER_EOCIE_Pos (0UL) /*!< EOCIE (Bit 0) */
+#define ADC1_IER_EOCIE_Msk (0x1UL) /*!< EOCIE (Bitfield-Mask: 0x01) */
+/* ======================================================== SIGSEL ========================================================= */
+#define ADC1_SIGSEL_SIGSEL_Pos (0UL) /*!< SIGSEL (Bit 0) */
+#define ADC1_SIGSEL_SIGSEL_Msk (0xfffffUL) /*!< SIGSEL (Bitfield-Mask: 0xfffff) */
+/* ========================================================= SMPR0 ========================================================= */
+#define ADC1_SMPR0_SMP7_Pos (28UL) /*!< SMP7 (Bit 28) */
+#define ADC1_SMPR0_SMP7_Msk (0x70000000UL) /*!< SMP7 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP6_Pos (24UL) /*!< SMP6 (Bit 24) */
+#define ADC1_SMPR0_SMP6_Msk (0x7000000UL) /*!< SMP6 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP5_Pos (20UL) /*!< SMP5 (Bit 20) */
+#define ADC1_SMPR0_SMP5_Msk (0x700000UL) /*!< SMP5 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP4_Pos (16UL) /*!< SMP4 (Bit 16) */
+#define ADC1_SMPR0_SMP4_Msk (0x70000UL) /*!< SMP4 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP3_Pos (12UL) /*!< SMP3 (Bit 12) */
+#define ADC1_SMPR0_SMP3_Msk (0x7000UL) /*!< SMP3 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP2_Pos (8UL) /*!< SMP2 (Bit 8) */
+#define ADC1_SMPR0_SMP2_Msk (0x700UL) /*!< SMP2 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP1_Pos (4UL) /*!< SMP1 (Bit 4) */
+#define ADC1_SMPR0_SMP1_Msk (0x70UL) /*!< SMP1 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR0_SMP0_Pos (0UL) /*!< SMP0 (Bit 0) */
+#define ADC1_SMPR0_SMP0_Msk (0x7UL) /*!< SMP0 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR1 ========================================================= */
+#define ADC1_SMPR1_SMP15_Pos (28UL) /*!< SMP15 (Bit 28) */
+#define ADC1_SMPR1_SMP15_Msk (0x70000000UL) /*!< SMP15 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP14_Pos (24UL) /*!< SMP14 (Bit 24) */
+#define ADC1_SMPR1_SMP14_Msk (0x7000000UL) /*!< SMP14 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP13_Pos (20UL) /*!< SMP13 (Bit 20) */
+#define ADC1_SMPR1_SMP13_Msk (0x700000UL) /*!< SMP13 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP12_Pos (16UL) /*!< SMP12 (Bit 16) */
+#define ADC1_SMPR1_SMP12_Msk (0x70000UL) /*!< SMP12 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP11_Pos (12UL) /*!< SMP11 (Bit 12) */
+#define ADC1_SMPR1_SMP11_Msk (0x7000UL) /*!< SMP11 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP10_Pos (8UL) /*!< SMP10 (Bit 8) */
+#define ADC1_SMPR1_SMP10_Msk (0x700UL) /*!< SMP10 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP9_Pos (4UL) /*!< SMP9 (Bit 4) */
+#define ADC1_SMPR1_SMP9_Msk (0x70UL) /*!< SMP9 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR1_SMP8_Pos (0UL) /*!< SMP8 (Bit 0) */
+#define ADC1_SMPR1_SMP8_Msk (0x7UL) /*!< SMP8 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR2 ========================================================= */
+#define ADC1_SMPR2_SMP19_Pos (12UL) /*!< SMP19 (Bit 12) */
+#define ADC1_SMPR2_SMP19_Msk (0x7000UL) /*!< SMP19 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR2_SMP18_Pos (8UL) /*!< SMP18 (Bit 8) */
+#define ADC1_SMPR2_SMP18_Msk (0x700UL) /*!< SMP18 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR2_SMP17_Pos (4UL) /*!< SMP17 (Bit 4) */
+#define ADC1_SMPR2_SMP17_Msk (0x70UL) /*!< SMP17 (Bitfield-Mask: 0x07) */
+#define ADC1_SMPR2_SMP16_Pos (0UL) /*!< SMP16 (Bit 0) */
+#define ADC1_SMPR2_SMP16_Msk (0x7UL) /*!< SMP16 (Bitfield-Mask: 0x07) */
+/* ========================================================= CALR0 ========================================================= */
+#define ADC1_CALR0_SAT7_Pos (31UL) /*!< SAT7 (Bit 31) */
+#define ADC1_CALR0_SAT7_Msk (0x80000000UL) /*!< SAT7 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL7_Pos (28UL) /*!< CAL7 (Bit 28) */
+#define ADC1_CALR0_CAL7_Msk (0x30000000UL) /*!< CAL7 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT6_Pos (27UL) /*!< SAT6 (Bit 27) */
+#define ADC1_CALR0_SAT6_Msk (0x8000000UL) /*!< SAT6 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL6_Pos (24UL) /*!< CAL6 (Bit 24) */
+#define ADC1_CALR0_CAL6_Msk (0x3000000UL) /*!< CAL6 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT5_Pos (23UL) /*!< SAT5 (Bit 23) */
+#define ADC1_CALR0_SAT5_Msk (0x800000UL) /*!< SAT5 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL5_Pos (20UL) /*!< CAL5 (Bit 20) */
+#define ADC1_CALR0_CAL5_Msk (0x300000UL) /*!< CAL5 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT4_Pos (19UL) /*!< SAT4 (Bit 19) */
+#define ADC1_CALR0_SAT4_Msk (0x80000UL) /*!< SAT4 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL4_Pos (16UL) /*!< CAL4 (Bit 16) */
+#define ADC1_CALR0_CAL4_Msk (0x30000UL) /*!< CAL4 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT3_Pos (15UL) /*!< SAT3 (Bit 15) */
+#define ADC1_CALR0_SAT3_Msk (0x8000UL) /*!< SAT3 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL3_Pos (12UL) /*!< CAL3 (Bit 12) */
+#define ADC1_CALR0_CAL3_Msk (0x3000UL) /*!< CAL3 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT2_Pos (11UL) /*!< SAT2 (Bit 11) */
+#define ADC1_CALR0_SAT2_Msk (0x800UL) /*!< SAT2 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL2_Pos (8UL) /*!< CAL2 (Bit 8) */
+#define ADC1_CALR0_CAL2_Msk (0x300UL) /*!< CAL2 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT1_Pos (7UL) /*!< SAT1 (Bit 7) */
+#define ADC1_CALR0_SAT1_Msk (0x80UL) /*!< SAT1 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL1_Pos (4UL) /*!< CAL1 (Bit 4) */
+#define ADC1_CALR0_CAL1_Msk (0x30UL) /*!< CAL1 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR0_SAT0_Pos (3UL) /*!< SAT0 (Bit 3) */
+#define ADC1_CALR0_SAT0_Msk (0x8UL) /*!< SAT0 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR0_CAL0_Pos (0UL) /*!< CAL0 (Bit 0) */
+#define ADC1_CALR0_CAL0_Msk (0x3UL) /*!< CAL0 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR1 ========================================================= */
+#define ADC1_CALR1_SAT15_Pos (31UL) /*!< SAT15 (Bit 31) */
+#define ADC1_CALR1_SAT15_Msk (0x80000000UL) /*!< SAT15 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL15_Pos (28UL) /*!< CAL15 (Bit 28) */
+#define ADC1_CALR1_CAL15_Msk (0x30000000UL) /*!< CAL15 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT14_Pos (27UL) /*!< SAT14 (Bit 27) */
+#define ADC1_CALR1_SAT14_Msk (0x8000000UL) /*!< SAT14 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL14_Pos (24UL) /*!< CAL14 (Bit 24) */
+#define ADC1_CALR1_CAL14_Msk (0x3000000UL) /*!< CAL14 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT13_Pos (23UL) /*!< SAT13 (Bit 23) */
+#define ADC1_CALR1_SAT13_Msk (0x800000UL) /*!< SAT13 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL13_Pos (20UL) /*!< CAL13 (Bit 20) */
+#define ADC1_CALR1_CAL13_Msk (0x300000UL) /*!< CAL13 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT12_Pos (19UL) /*!< SAT12 (Bit 19) */
+#define ADC1_CALR1_SAT12_Msk (0x80000UL) /*!< SAT12 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL12_Pos (16UL) /*!< CAL12 (Bit 16) */
+#define ADC1_CALR1_CAL12_Msk (0x30000UL) /*!< CAL12 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT11_Pos (15UL) /*!< SAT11 (Bit 15) */
+#define ADC1_CALR1_SAT11_Msk (0x8000UL) /*!< SAT11 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL11_Pos (12UL) /*!< CAL11 (Bit 12) */
+#define ADC1_CALR1_CAL11_Msk (0x3000UL) /*!< CAL11 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT10_Pos (11UL) /*!< SAT10 (Bit 11) */
+#define ADC1_CALR1_SAT10_Msk (0x800UL) /*!< SAT10 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL10_Pos (8UL) /*!< CAL10 (Bit 8) */
+#define ADC1_CALR1_CAL10_Msk (0x300UL) /*!< CAL10 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT9_Pos (7UL) /*!< SAT9 (Bit 7) */
+#define ADC1_CALR1_SAT9_Msk (0x80UL) /*!< SAT9 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL9_Pos (4UL) /*!< CAL9 (Bit 4) */
+#define ADC1_CALR1_CAL9_Msk (0x30UL) /*!< CAL9 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR1_SAT8_Pos (3UL) /*!< SAT8 (Bit 3) */
+#define ADC1_CALR1_SAT8_Msk (0x8UL) /*!< SAT8 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR1_CAL8_Pos (0UL) /*!< CAL8 (Bit 0) */
+#define ADC1_CALR1_CAL8_Msk (0x3UL) /*!< CAL8 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR2 ========================================================= */
+#define ADC1_CALR2_SAT19_Pos (15UL) /*!< SAT19 (Bit 15) */
+#define ADC1_CALR2_SAT19_Msk (0x8000UL) /*!< SAT19 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR2_CAL19_Pos (12UL) /*!< CAL19 (Bit 12) */
+#define ADC1_CALR2_CAL19_Msk (0x3000UL) /*!< CAL19 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR2_SAT18_Pos (11UL) /*!< SAT18 (Bit 11) */
+#define ADC1_CALR2_SAT18_Msk (0x800UL) /*!< SAT18 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR2_CAL18_Pos (8UL) /*!< CAL18 (Bit 8) */
+#define ADC1_CALR2_CAL18_Msk (0x300UL) /*!< CAL18 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR2_SAT17_Pos (7UL) /*!< SAT17 (Bit 7) */
+#define ADC1_CALR2_SAT17_Msk (0x80UL) /*!< SAT17 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR2_CAL17_Pos (4UL) /*!< CAL17 (Bit 4) */
+#define ADC1_CALR2_CAL17_Msk (0x30UL) /*!< CAL17 (Bitfield-Mask: 0x03) */
+#define ADC1_CALR2_SAT16_Pos (3UL) /*!< SAT16 (Bit 3) */
+#define ADC1_CALR2_SAT16_Msk (0x8UL) /*!< SAT16 (Bitfield-Mask: 0x01) */
+#define ADC1_CALR2_CAL16_Pos (0UL) /*!< CAL16 (Bit 0) */
+#define ADC1_CALR2_CAL16_Msk (0x3UL) /*!< CAL16 (Bitfield-Mask: 0x03) */
+/* ========================================================= SQR0 ========================================================== */
+#define ADC1_SQR0_SQ5_Pos (24UL) /*!< SQ5 (Bit 24) */
+#define ADC1_SQR0_SQ5_Msk (0x1f000000UL) /*!< SQ5 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR0_SQ4_Pos (18UL) /*!< SQ4 (Bit 18) */
+#define ADC1_SQR0_SQ4_Msk (0x7c0000UL) /*!< SQ4 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR0_SQ3_Pos (12UL) /*!< SQ3 (Bit 12) */
+#define ADC1_SQR0_SQ3_Msk (0x1f000UL) /*!< SQ3 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR0_SQ2_Pos (6UL) /*!< SQ2 (Bit 6) */
+#define ADC1_SQR0_SQ2_Msk (0x7c0UL) /*!< SQ2 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR0_SQ1_Pos (0UL) /*!< SQ1 (Bit 0) */
+#define ADC1_SQR0_SQ1_Msk (0x1fUL) /*!< SQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR1 ========================================================== */
+#define ADC1_SQR1_SQ10_Pos (24UL) /*!< SQ10 (Bit 24) */
+#define ADC1_SQR1_SQ10_Msk (0x1f000000UL) /*!< SQ10 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR1_SQ9_Pos (18UL) /*!< SQ9 (Bit 18) */
+#define ADC1_SQR1_SQ9_Msk (0x7c0000UL) /*!< SQ9 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR1_SQ8_Pos (12UL) /*!< SQ8 (Bit 12) */
+#define ADC1_SQR1_SQ8_Msk (0x1f000UL) /*!< SQ8 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR1_SQ7_Pos (6UL) /*!< SQ7 (Bit 6) */
+#define ADC1_SQR1_SQ7_Msk (0x7c0UL) /*!< SQ7 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR1_SQ6_Pos (0UL) /*!< SQ6 (Bit 0) */
+#define ADC1_SQR1_SQ6_Msk (0x1fUL) /*!< SQ6 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR2 ========================================================== */
+#define ADC1_SQR2_SQ15_Pos (24UL) /*!< SQ15 (Bit 24) */
+#define ADC1_SQR2_SQ15_Msk (0x1f000000UL) /*!< SQ15 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR2_SQ14_Pos (18UL) /*!< SQ14 (Bit 18) */
+#define ADC1_SQR2_SQ14_Msk (0x7c0000UL) /*!< SQ14 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR2_SQ13_Pos (12UL) /*!< SQ13 (Bit 12) */
+#define ADC1_SQR2_SQ13_Msk (0x1f000UL) /*!< SQ13 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR2_SQ12_Pos (6UL) /*!< SQ12 (Bit 6) */
+#define ADC1_SQR2_SQ12_Msk (0x7c0UL) /*!< SQ12 (Bitfield-Mask: 0x1f) */
+#define ADC1_SQR2_SQ11_Pos (0UL) /*!< SQ11 (Bit 0) */
+#define ADC1_SQR2_SQ11_Msk (0x1fUL) /*!< SQ11 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR3 ========================================================== */
+#define ADC1_SQR3_SQ16_Pos (0UL) /*!< SQ16 (Bit 0) */
+#define ADC1_SQR3_SQ16_Msk (0x1fUL) /*!< SQ16 (Bitfield-Mask: 0x1f) */
+/* ========================================================== LR =========================================================== */
+#define ADC1_LR_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define ADC1_LR_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define ADC1_LR_EXTEN_Pos (6UL) /*!< EXTEN (Bit 6) */
+#define ADC1_LR_EXTEN_Msk (0xc0UL) /*!< EXTEN (Bitfield-Mask: 0x03) */
+#define ADC1_LR_EXTSEL_Pos (0UL) /*!< EXTSEL (Bit 0) */
+#define ADC1_LR_EXTSEL_Msk (0x1fUL) /*!< EXTSEL (Bitfield-Mask: 0x1f) */
+/* ========================================================== DR =========================================================== */
+#define ADC1_DR_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */
+#define ADC1_DR_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MAXDR ========================================================= */
+#define ADC1_MAXDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC1_MAXDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MINDR ========================================================= */
+#define ADC1_MINDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC1_MINDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JSQR ========================================================== */
+#define ADC1_JSQR_JSQ4_Pos (18UL) /*!< JSQ4 (Bit 18) */
+#define ADC1_JSQR_JSQ4_Msk (0x7c0000UL) /*!< JSQ4 (Bitfield-Mask: 0x1f) */
+#define ADC1_JSQR_JSQ3_Pos (12UL) /*!< JSQ3 (Bit 12) */
+#define ADC1_JSQR_JSQ3_Msk (0x1f000UL) /*!< JSQ3 (Bitfield-Mask: 0x1f) */
+#define ADC1_JSQR_JSQ2_Pos (6UL) /*!< JSQ2 (Bit 6) */
+#define ADC1_JSQR_JSQ2_Msk (0x7c0UL) /*!< JSQ2 (Bitfield-Mask: 0x1f) */
+#define ADC1_JSQR_JSQ1_Pos (0UL) /*!< JSQ1 (Bit 0) */
+#define ADC1_JSQR_JSQ1_Msk (0x1fUL) /*!< JSQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================== JLR ========================================================== */
+#define ADC1_JLR_JLEN_Pos (8UL) /*!< JLEN (Bit 8) */
+#define ADC1_JLR_JLEN_Msk (0x300UL) /*!< JLEN (Bitfield-Mask: 0x03) */
+#define ADC1_JLR_JEXTEN_Pos (6UL) /*!< JEXTEN (Bit 6) */
+#define ADC1_JLR_JEXTEN_Msk (0xc0UL) /*!< JEXTEN (Bitfield-Mask: 0x03) */
+#define ADC1_JLR_JEXTSEL_Pos (0UL) /*!< JEXTSEL (Bit 0) */
+#define ADC1_JLR_JEXTSEL_Msk (0x1fUL) /*!< JEXTSEL (Bitfield-Mask: 0x1f) */
+/* ======================================================== MAXJDR ========================================================= */
+#define ADC1_MAXJDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC1_MAXJDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ======================================================== MINJDR ========================================================= */
+#define ADC1_MINJDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC1_MINJDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR0 ========================================================== */
+#define ADC1_JDR0_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC1_JDR0_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR1 ========================================================== */
+#define ADC1_JDR1_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC1_JDR1_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR2 ========================================================== */
+#define ADC1_JDR2_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC1_JDR2_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR3 ========================================================== */
+#define ADC1_JDR3_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC1_JDR3_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR0 ========================================================== */
+#define ADC1_TR0_HT0_Pos (16UL) /*!< HT0 (Bit 16) */
+#define ADC1_TR0_HT0_Msk (0xffff0000UL) /*!< HT0 (Bitfield-Mask: 0xffff) */
+#define ADC1_TR0_LT0_Pos (0UL) /*!< LT0 (Bit 0) */
+#define ADC1_TR0_LT0_Msk (0xffffUL) /*!< LT0 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR1 ========================================================== */
+#define ADC1_TR1_HT1_Pos (16UL) /*!< HT1 (Bit 16) */
+#define ADC1_TR1_HT1_Msk (0xffff0000UL) /*!< HT1 (Bitfield-Mask: 0xffff) */
+#define ADC1_TR1_LT1_Pos (0UL) /*!< LT1 (Bit 0) */
+#define ADC1_TR1_LT1_Msk (0xffffUL) /*!< LT1 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR2 ========================================================== */
+#define ADC1_TR2_HT2_Pos (16UL) /*!< HT2 (Bit 16) */
+#define ADC1_TR2_HT2_Msk (0xffff0000UL) /*!< HT2 (Bitfield-Mask: 0xffff) */
+#define ADC1_TR2_LT2_Pos (0UL) /*!< LT2 (Bit 0) */
+#define ADC1_TR2_LT2_Msk (0xffffUL) /*!< LT2 (Bitfield-Mask: 0xffff) */
+/* ======================================================== AWD0CR ========================================================= */
+#define ADC1_AWD0CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC1_AWD0CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC1_AWD0CR_AW0CH_Pos (0UL) /*!< AW0CH (Bit 0) */
+#define ADC1_AWD0CR_AW0CH_Msk (0xfffffUL) /*!< AW0CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD1CR ========================================================= */
+#define ADC1_AWD1CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC1_AWD1CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC1_AWD1CR_AW1CH_Pos (0UL) /*!< AW1CH (Bit 0) */
+#define ADC1_AWD1CR_AW1CH_Msk (0xfffffUL) /*!< AW1CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD2CR ========================================================= */
+#define ADC1_AWD2CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC1_AWD2CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC1_AWD2CR_AW2CH_Pos (0UL) /*!< AW2CH (Bit 0) */
+#define ADC1_AWD2CR_AW2CH_Msk (0xfffffUL) /*!< AW2CH (Bitfield-Mask: 0xfffff) */
+/* ========================================================= OFR0 ========================================================== */
+#define ADC1_OFR0_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC1_OFR0_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR1 ========================================================== */
+#define ADC1_OFR1_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC1_OFR1_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR2 ========================================================== */
+#define ADC1_OFR2_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC1_OFR2_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR3 ========================================================== */
+#define ADC1_OFR3_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC1_OFR3_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= GCR0 ========================================================== */
+#define ADC1_GCR0_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC1_GCR0_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR1 ========================================================== */
+#define ADC1_GCR1_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC1_GCR1_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR2 ========================================================== */
+#define ADC1_GCR2_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC1_GCR2_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR3 ========================================================== */
+#define ADC1_GCR3_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC1_GCR3_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= DISR ========================================================== */
+#define ADC1_DISR_DON19_Pos (19UL) /*!< DON19 (Bit 19) */
+#define ADC1_DISR_DON19_Msk (0x80000UL) /*!< DON19 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON18_Pos (18UL) /*!< DON18 (Bit 18) */
+#define ADC1_DISR_DON18_Msk (0x40000UL) /*!< DON18 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON17_Pos (17UL) /*!< DON17 (Bit 17) */
+#define ADC1_DISR_DON17_Msk (0x20000UL) /*!< DON17 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON16_Pos (16UL) /*!< DON16 (Bit 16) */
+#define ADC1_DISR_DON16_Msk (0x10000UL) /*!< DON16 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON15_Pos (15UL) /*!< DON15 (Bit 15) */
+#define ADC1_DISR_DON15_Msk (0x8000UL) /*!< DON15 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON14_Pos (14UL) /*!< DON14 (Bit 14) */
+#define ADC1_DISR_DON14_Msk (0x4000UL) /*!< DON14 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON13_Pos (13UL) /*!< DON13 (Bit 13) */
+#define ADC1_DISR_DON13_Msk (0x2000UL) /*!< DON13 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON12_Pos (12UL) /*!< DON12 (Bit 12) */
+#define ADC1_DISR_DON12_Msk (0x1000UL) /*!< DON12 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON11_Pos (11UL) /*!< DON11 (Bit 11) */
+#define ADC1_DISR_DON11_Msk (0x800UL) /*!< DON11 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON10_Pos (10UL) /*!< DON10 (Bit 10) */
+#define ADC1_DISR_DON10_Msk (0x400UL) /*!< DON10 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON9_Pos (9UL) /*!< DON9 (Bit 9) */
+#define ADC1_DISR_DON9_Msk (0x200UL) /*!< DON9 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON8_Pos (8UL) /*!< DON8 (Bit 8) */
+#define ADC1_DISR_DON8_Msk (0x100UL) /*!< DON8 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON7_Pos (7UL) /*!< DON7 (Bit 7) */
+#define ADC1_DISR_DON7_Msk (0x80UL) /*!< DON7 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON6_Pos (6UL) /*!< DON6 (Bit 6) */
+#define ADC1_DISR_DON6_Msk (0x40UL) /*!< DON6 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON5_Pos (5UL) /*!< DON5 (Bit 5) */
+#define ADC1_DISR_DON5_Msk (0x20UL) /*!< DON5 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON4_Pos (4UL) /*!< DON4 (Bit 4) */
+#define ADC1_DISR_DON4_Msk (0x10UL) /*!< DON4 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON3_Pos (3UL) /*!< DON3 (Bit 3) */
+#define ADC1_DISR_DON3_Msk (0x8UL) /*!< DON3 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON2_Pos (2UL) /*!< DON2 (Bit 2) */
+#define ADC1_DISR_DON2_Msk (0x4UL) /*!< DON2 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON1_Pos (1UL) /*!< DON1 (Bit 1) */
+#define ADC1_DISR_DON1_Msk (0x2UL) /*!< DON1 (Bitfield-Mask: 0x01) */
+#define ADC1_DISR_DON0_Pos (0UL) /*!< DON0 (Bit 0) */
+#define ADC1_DISR_DON0_Msk (0x1UL) /*!< DON0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DIER ========================================================== */
+#define ADC1_DIER_DONIE19_Pos (19UL) /*!< DONIE19 (Bit 19) */
+#define ADC1_DIER_DONIE19_Msk (0x80000UL) /*!< DONIE19 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE18_Pos (18UL) /*!< DONIE18 (Bit 18) */
+#define ADC1_DIER_DONIE18_Msk (0x40000UL) /*!< DONIE18 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE17_Pos (17UL) /*!< DONIE17 (Bit 17) */
+#define ADC1_DIER_DONIE17_Msk (0x20000UL) /*!< DONIE17 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE16_Pos (16UL) /*!< DONIE16 (Bit 16) */
+#define ADC1_DIER_DONIE16_Msk (0x10000UL) /*!< DONIE16 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE15_Pos (15UL) /*!< DONIE15 (Bit 15) */
+#define ADC1_DIER_DONIE15_Msk (0x8000UL) /*!< DONIE15 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE14_Pos (14UL) /*!< DONIE14 (Bit 14) */
+#define ADC1_DIER_DONIE14_Msk (0x4000UL) /*!< DONIE14 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE13_Pos (13UL) /*!< DONIE13 (Bit 13) */
+#define ADC1_DIER_DONIE13_Msk (0x2000UL) /*!< DONIE13 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE12_Pos (12UL) /*!< DONIE12 (Bit 12) */
+#define ADC1_DIER_DONIE12_Msk (0x1000UL) /*!< DONIE12 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE11_Pos (11UL) /*!< DONIE11 (Bit 11) */
+#define ADC1_DIER_DONIE11_Msk (0x800UL) /*!< DONIE11 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE10_Pos (10UL) /*!< DONIE10 (Bit 10) */
+#define ADC1_DIER_DONIE10_Msk (0x400UL) /*!< DONIE10 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE9_Pos (9UL) /*!< DONIE9 (Bit 9) */
+#define ADC1_DIER_DONIE9_Msk (0x200UL) /*!< DONIE9 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE8_Pos (8UL) /*!< DONIE8 (Bit 8) */
+#define ADC1_DIER_DONIE8_Msk (0x100UL) /*!< DONIE8 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE7_Pos (7UL) /*!< DONIE7 (Bit 7) */
+#define ADC1_DIER_DONIE7_Msk (0x80UL) /*!< DONIE7 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE6_Pos (6UL) /*!< DONIE6 (Bit 6) */
+#define ADC1_DIER_DONIE6_Msk (0x40UL) /*!< DONIE6 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE5_Pos (5UL) /*!< DONIE5 (Bit 5) */
+#define ADC1_DIER_DONIE5_Msk (0x20UL) /*!< DONIE5 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE4_Pos (4UL) /*!< DONIE4 (Bit 4) */
+#define ADC1_DIER_DONIE4_Msk (0x10UL) /*!< DONIE4 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE3_Pos (3UL) /*!< DONIE3 (Bit 3) */
+#define ADC1_DIER_DONIE3_Msk (0x8UL) /*!< DONIE3 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE2_Pos (2UL) /*!< DONIE2 (Bit 2) */
+#define ADC1_DIER_DONIE2_Msk (0x4UL) /*!< DONIE2 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE1_Pos (1UL) /*!< DONIE1 (Bit 1) */
+#define ADC1_DIER_DONIE1_Msk (0x2UL) /*!< DONIE1 (Bitfield-Mask: 0x01) */
+#define ADC1_DIER_DONIE0_Pos (0UL) /*!< DONIE0 (Bit 0) */
+#define ADC1_DIER_DONIE0_Msk (0x1UL) /*!< DONIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= CDR0 ========================================================== */
+#define ADC1_CDR0_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR0_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR1 ========================================================== */
+#define ADC1_CDR1_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR1_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR2 ========================================================== */
+#define ADC1_CDR2_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR2_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR3 ========================================================== */
+#define ADC1_CDR3_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR3_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR4 ========================================================== */
+#define ADC1_CDR4_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR4_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR5 ========================================================== */
+#define ADC1_CDR5_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR5_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR6 ========================================================== */
+#define ADC1_CDR6_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR6_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR7 ========================================================== */
+#define ADC1_CDR7_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR7_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR8 ========================================================== */
+#define ADC1_CDR8_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR8_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR9 ========================================================== */
+#define ADC1_CDR9_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR9_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR10 ========================================================= */
+#define ADC1_CDR10_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR10_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR11 ========================================================= */
+#define ADC1_CDR11_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR11_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR12 ========================================================= */
+#define ADC1_CDR12_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR12_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR13 ========================================================= */
+#define ADC1_CDR13_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR13_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR14 ========================================================= */
+#define ADC1_CDR14_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR14_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR15 ========================================================= */
+#define ADC1_CDR15_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR15_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR16 ========================================================= */
+#define ADC1_CDR16_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR16_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR17 ========================================================= */
+#define ADC1_CDR17_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR17_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR18 ========================================================= */
+#define ADC1_CDR18_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR18_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR19 ========================================================= */
+#define ADC1_CDR19_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC1_CDR19_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= HISR ========================================================== */
+#define ADC1_HISR_HLF19_Pos (19UL) /*!< HLF19 (Bit 19) */
+#define ADC1_HISR_HLF19_Msk (0x80000UL) /*!< HLF19 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF18_Pos (18UL) /*!< HLF18 (Bit 18) */
+#define ADC1_HISR_HLF18_Msk (0x40000UL) /*!< HLF18 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF17_Pos (17UL) /*!< HLF17 (Bit 17) */
+#define ADC1_HISR_HLF17_Msk (0x20000UL) /*!< HLF17 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF16_Pos (16UL) /*!< HLF16 (Bit 16) */
+#define ADC1_HISR_HLF16_Msk (0x10000UL) /*!< HLF16 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF15_Pos (15UL) /*!< HLF15 (Bit 15) */
+#define ADC1_HISR_HLF15_Msk (0x8000UL) /*!< HLF15 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF14_Pos (14UL) /*!< HLF14 (Bit 14) */
+#define ADC1_HISR_HLF14_Msk (0x4000UL) /*!< HLF14 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF13_Pos (13UL) /*!< HLF13 (Bit 13) */
+#define ADC1_HISR_HLF13_Msk (0x2000UL) /*!< HLF13 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF12_Pos (12UL) /*!< HLF12 (Bit 12) */
+#define ADC1_HISR_HLF12_Msk (0x1000UL) /*!< HLF12 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF11_Pos (11UL) /*!< HLF11 (Bit 11) */
+#define ADC1_HISR_HLF11_Msk (0x800UL) /*!< HLF11 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF10_Pos (10UL) /*!< HLF10 (Bit 10) */
+#define ADC1_HISR_HLF10_Msk (0x400UL) /*!< HLF10 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF9_Pos (9UL) /*!< HLF9 (Bit 9) */
+#define ADC1_HISR_HLF9_Msk (0x200UL) /*!< HLF9 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF8_Pos (8UL) /*!< HLF8 (Bit 8) */
+#define ADC1_HISR_HLF8_Msk (0x100UL) /*!< HLF8 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF7_Pos (7UL) /*!< HLF7 (Bit 7) */
+#define ADC1_HISR_HLF7_Msk (0x80UL) /*!< HLF7 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF6_Pos (6UL) /*!< HLF6 (Bit 6) */
+#define ADC1_HISR_HLF6_Msk (0x40UL) /*!< HLF6 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF5_Pos (5UL) /*!< HLF5 (Bit 5) */
+#define ADC1_HISR_HLF5_Msk (0x20UL) /*!< HLF5 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF4_Pos (4UL) /*!< HLF4 (Bit 4) */
+#define ADC1_HISR_HLF4_Msk (0x10UL) /*!< HLF4 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF3_Pos (3UL) /*!< HLF3 (Bit 3) */
+#define ADC1_HISR_HLF3_Msk (0x8UL) /*!< HLF3 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF2_Pos (2UL) /*!< HLF2 (Bit 2) */
+#define ADC1_HISR_HLF2_Msk (0x4UL) /*!< HLF2 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF1_Pos (1UL) /*!< HLF1 (Bit 1) */
+#define ADC1_HISR_HLF1_Msk (0x2UL) /*!< HLF1 (Bitfield-Mask: 0x01) */
+#define ADC1_HISR_HLF0_Pos (0UL) /*!< HLF0 (Bit 0) */
+#define ADC1_HISR_HLF0_Msk (0x1UL) /*!< HLF0 (Bitfield-Mask: 0x01) */
+/* ========================================================= HIER ========================================================== */
+#define ADC1_HIER_HLFIE19_Pos (19UL) /*!< HLFIE19 (Bit 19) */
+#define ADC1_HIER_HLFIE19_Msk (0x80000UL) /*!< HLFIE19 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE18_Pos (18UL) /*!< HLFIE18 (Bit 18) */
+#define ADC1_HIER_HLFIE18_Msk (0x40000UL) /*!< HLFIE18 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE17_Pos (17UL) /*!< HLFIE17 (Bit 17) */
+#define ADC1_HIER_HLFIE17_Msk (0x20000UL) /*!< HLFIE17 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE16_Pos (16UL) /*!< HLFIE16 (Bit 16) */
+#define ADC1_HIER_HLFIE16_Msk (0x10000UL) /*!< HLFIE16 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE15_Pos (15UL) /*!< HLFIE15 (Bit 15) */
+#define ADC1_HIER_HLFIE15_Msk (0x8000UL) /*!< HLFIE15 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE14_Pos (14UL) /*!< HLFIE14 (Bit 14) */
+#define ADC1_HIER_HLFIE14_Msk (0x4000UL) /*!< HLFIE14 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE13_Pos (13UL) /*!< HLFIE13 (Bit 13) */
+#define ADC1_HIER_HLFIE13_Msk (0x2000UL) /*!< HLFIE13 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE12_Pos (12UL) /*!< HLFIE12 (Bit 12) */
+#define ADC1_HIER_HLFIE12_Msk (0x1000UL) /*!< HLFIE12 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE11_Pos (11UL) /*!< HLFIE11 (Bit 11) */
+#define ADC1_HIER_HLFIE11_Msk (0x800UL) /*!< HLFIE11 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE10_Pos (10UL) /*!< HLFIE10 (Bit 10) */
+#define ADC1_HIER_HLFIE10_Msk (0x400UL) /*!< HLFIE10 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE9_Pos (9UL) /*!< HLFIE9 (Bit 9) */
+#define ADC1_HIER_HLFIE9_Msk (0x200UL) /*!< HLFIE9 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE8_Pos (8UL) /*!< HLFIE8 (Bit 8) */
+#define ADC1_HIER_HLFIE8_Msk (0x100UL) /*!< HLFIE8 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE7_Pos (7UL) /*!< HLFIE7 (Bit 7) */
+#define ADC1_HIER_HLFIE7_Msk (0x80UL) /*!< HLFIE7 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE6_Pos (6UL) /*!< HLFIE6 (Bit 6) */
+#define ADC1_HIER_HLFIE6_Msk (0x40UL) /*!< HLFIE6 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE5_Pos (5UL) /*!< HLFIE5 (Bit 5) */
+#define ADC1_HIER_HLFIE5_Msk (0x20UL) /*!< HLFIE5 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE4_Pos (4UL) /*!< HLFIE4 (Bit 4) */
+#define ADC1_HIER_HLFIE4_Msk (0x10UL) /*!< HLFIE4 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE3_Pos (3UL) /*!< HLFIE3 (Bit 3) */
+#define ADC1_HIER_HLFIE3_Msk (0x8UL) /*!< HLFIE3 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE2_Pos (2UL) /*!< HLFIE2 (Bit 2) */
+#define ADC1_HIER_HLFIE2_Msk (0x4UL) /*!< HLFIE2 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE1_Pos (1UL) /*!< HLFIE1 (Bit 1) */
+#define ADC1_HIER_HLFIE1_Msk (0x2UL) /*!< HLFIE1 (Bitfield-Mask: 0x01) */
+#define ADC1_HIER_HLFIE0_Pos (0UL) /*!< HLFIE0 (Bit 0) */
+#define ADC1_HIER_HLFIE0_Msk (0x1UL) /*!< HLFIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FISR ========================================================== */
+#define ADC1_FISR_FUL19_Pos (19UL) /*!< FUL19 (Bit 19) */
+#define ADC1_FISR_FUL19_Msk (0x80000UL) /*!< FUL19 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL18_Pos (18UL) /*!< FUL18 (Bit 18) */
+#define ADC1_FISR_FUL18_Msk (0x40000UL) /*!< FUL18 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL17_Pos (17UL) /*!< FUL17 (Bit 17) */
+#define ADC1_FISR_FUL17_Msk (0x20000UL) /*!< FUL17 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL16_Pos (16UL) /*!< FUL16 (Bit 16) */
+#define ADC1_FISR_FUL16_Msk (0x10000UL) /*!< FUL16 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL15_Pos (15UL) /*!< FUL15 (Bit 15) */
+#define ADC1_FISR_FUL15_Msk (0x8000UL) /*!< FUL15 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL14_Pos (14UL) /*!< FUL14 (Bit 14) */
+#define ADC1_FISR_FUL14_Msk (0x4000UL) /*!< FUL14 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL13_Pos (13UL) /*!< FUL13 (Bit 13) */
+#define ADC1_FISR_FUL13_Msk (0x2000UL) /*!< FUL13 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL12_Pos (12UL) /*!< FUL12 (Bit 12) */
+#define ADC1_FISR_FUL12_Msk (0x1000UL) /*!< FUL12 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL11_Pos (11UL) /*!< FUL11 (Bit 11) */
+#define ADC1_FISR_FUL11_Msk (0x800UL) /*!< FUL11 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL10_Pos (10UL) /*!< FUL10 (Bit 10) */
+#define ADC1_FISR_FUL10_Msk (0x400UL) /*!< FUL10 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL9_Pos (9UL) /*!< FUL9 (Bit 9) */
+#define ADC1_FISR_FUL9_Msk (0x200UL) /*!< FUL9 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL8_Pos (8UL) /*!< FUL8 (Bit 8) */
+#define ADC1_FISR_FUL8_Msk (0x100UL) /*!< FUL8 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL7_Pos (7UL) /*!< FUL7 (Bit 7) */
+#define ADC1_FISR_FUL7_Msk (0x80UL) /*!< FUL7 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL6_Pos (6UL) /*!< FUL6 (Bit 6) */
+#define ADC1_FISR_FUL6_Msk (0x40UL) /*!< FUL6 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL5_Pos (5UL) /*!< FUL5 (Bit 5) */
+#define ADC1_FISR_FUL5_Msk (0x20UL) /*!< FUL5 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL4_Pos (4UL) /*!< FUL4 (Bit 4) */
+#define ADC1_FISR_FUL4_Msk (0x10UL) /*!< FUL4 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL3_Pos (3UL) /*!< FUL3 (Bit 3) */
+#define ADC1_FISR_FUL3_Msk (0x8UL) /*!< FUL3 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL2_Pos (2UL) /*!< FUL2 (Bit 2) */
+#define ADC1_FISR_FUL2_Msk (0x4UL) /*!< FUL2 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL1_Pos (1UL) /*!< FUL1 (Bit 1) */
+#define ADC1_FISR_FUL1_Msk (0x2UL) /*!< FUL1 (Bitfield-Mask: 0x01) */
+#define ADC1_FISR_FUL0_Pos (0UL) /*!< FUL0 (Bit 0) */
+#define ADC1_FISR_FUL0_Msk (0x1UL) /*!< FUL0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FIER ========================================================== */
+#define ADC1_FIER_FULIE19_Pos (19UL) /*!< FULIE19 (Bit 19) */
+#define ADC1_FIER_FULIE19_Msk (0x80000UL) /*!< FULIE19 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE18_Pos (18UL) /*!< FULIE18 (Bit 18) */
+#define ADC1_FIER_FULIE18_Msk (0x40000UL) /*!< FULIE18 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE17_Pos (17UL) /*!< FULIE17 (Bit 17) */
+#define ADC1_FIER_FULIE17_Msk (0x20000UL) /*!< FULIE17 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE16_Pos (16UL) /*!< FULIE16 (Bit 16) */
+#define ADC1_FIER_FULIE16_Msk (0x10000UL) /*!< FULIE16 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE15_Pos (15UL) /*!< FULIE15 (Bit 15) */
+#define ADC1_FIER_FULIE15_Msk (0x8000UL) /*!< FULIE15 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE14_Pos (14UL) /*!< FULIE14 (Bit 14) */
+#define ADC1_FIER_FULIE14_Msk (0x4000UL) /*!< FULIE14 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE13_Pos (13UL) /*!< FULIE13 (Bit 13) */
+#define ADC1_FIER_FULIE13_Msk (0x2000UL) /*!< FULIE13 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE12_Pos (12UL) /*!< FULIE12 (Bit 12) */
+#define ADC1_FIER_FULIE12_Msk (0x1000UL) /*!< FULIE12 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE11_Pos (11UL) /*!< FULIE11 (Bit 11) */
+#define ADC1_FIER_FULIE11_Msk (0x800UL) /*!< FULIE11 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE10_Pos (10UL) /*!< FULIE10 (Bit 10) */
+#define ADC1_FIER_FULIE10_Msk (0x400UL) /*!< FULIE10 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE9_Pos (9UL) /*!< FULIE9 (Bit 9) */
+#define ADC1_FIER_FULIE9_Msk (0x200UL) /*!< FULIE9 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE8_Pos (8UL) /*!< FULIE8 (Bit 8) */
+#define ADC1_FIER_FULIE8_Msk (0x100UL) /*!< FULIE8 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE7_Pos (7UL) /*!< FULIE7 (Bit 7) */
+#define ADC1_FIER_FULIE7_Msk (0x80UL) /*!< FULIE7 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE6_Pos (6UL) /*!< FULIE6 (Bit 6) */
+#define ADC1_FIER_FULIE6_Msk (0x40UL) /*!< FULIE6 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE5_Pos (5UL) /*!< FULIE5 (Bit 5) */
+#define ADC1_FIER_FULIE5_Msk (0x20UL) /*!< FULIE5 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE4_Pos (4UL) /*!< FULIE4 (Bit 4) */
+#define ADC1_FIER_FULIE4_Msk (0x10UL) /*!< FULIE4 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE3_Pos (3UL) /*!< FULIE3 (Bit 3) */
+#define ADC1_FIER_FULIE3_Msk (0x8UL) /*!< FULIE3 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE2_Pos (2UL) /*!< FULIE2 (Bit 2) */
+#define ADC1_FIER_FULIE2_Msk (0x4UL) /*!< FULIE2 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE1_Pos (1UL) /*!< FULIE1 (Bit 1) */
+#define ADC1_FIER_FULIE1_Msk (0x2UL) /*!< FULIE1 (Bitfield-Mask: 0x01) */
+#define ADC1_FIER_FULIE0_Pos (0UL) /*!< FULIE0 (Bit 0) */
+#define ADC1_FIER_FULIE0_Msk (0x1UL) /*!< FULIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= TCR0 ========================================================== */
+#define ADC1_TCR0_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR0_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR0_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR0_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR0_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR0_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR0_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR0 ========================================================== */
+#define ADC1_TAR0_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR0_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR0 ========================================================== */
+#define ADC1_TLR0_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR0_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR1 ========================================================== */
+#define ADC1_TCR1_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR1_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR1_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR1_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR1_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR1_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR1_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR1 ========================================================== */
+#define ADC1_TAR1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR1_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR1 ========================================================== */
+#define ADC1_TLR1_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR1_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR2 ========================================================== */
+#define ADC1_TCR2_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR2_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR2_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR2_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR2_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR2_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR2_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR2 ========================================================== */
+#define ADC1_TAR2_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR2_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR2 ========================================================== */
+#define ADC1_TLR2_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR2_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR3 ========================================================== */
+#define ADC1_TCR3_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR3_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR3_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR3_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR3_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR3_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR3_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR3 ========================================================== */
+#define ADC1_TAR3_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR3_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR3 ========================================================== */
+#define ADC1_TLR3_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR3_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR4 ========================================================== */
+#define ADC1_TCR4_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR4_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR4_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR4_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR4_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR4_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR4_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR4_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR4 ========================================================== */
+#define ADC1_TAR4_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR4_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR4 ========================================================== */
+#define ADC1_TLR4_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR4_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR5 ========================================================== */
+#define ADC1_TCR5_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR5_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR5_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR5_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR5_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR5_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR5_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR5_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR5 ========================================================== */
+#define ADC1_TAR5_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR5_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR5 ========================================================== */
+#define ADC1_TLR5_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR5_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR6 ========================================================== */
+#define ADC1_TCR6_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR6_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR6_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR6_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR6_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR6_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR6_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR6_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR6 ========================================================== */
+#define ADC1_TAR6_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR6_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR6 ========================================================== */
+#define ADC1_TLR6_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR6_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR7 ========================================================== */
+#define ADC1_TCR7_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR7_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR7_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR7_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR7_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR7_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR7_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR7_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR7 ========================================================== */
+#define ADC1_TAR7_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR7_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR7 ========================================================== */
+#define ADC1_TLR7_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR7_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR8 ========================================================== */
+#define ADC1_TCR8_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR8_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR8_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR8_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR8_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR8_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR8_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR8_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR8 ========================================================== */
+#define ADC1_TAR8_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR8_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR8 ========================================================== */
+#define ADC1_TLR8_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR8_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR9 ========================================================== */
+#define ADC1_TCR9_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR9_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR9_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR9_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR9_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR9_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR9_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR9_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR9 ========================================================== */
+#define ADC1_TAR9_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR9_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR9 ========================================================== */
+#define ADC1_TLR9_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR9_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR10 ========================================================= */
+#define ADC1_TCR10_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR10_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR10_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR10_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR10_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR10_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR10_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR10_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR10 ========================================================= */
+#define ADC1_TAR10_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR10_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR10 ========================================================= */
+#define ADC1_TLR10_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR10_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR11 ========================================================= */
+#define ADC1_TCR11_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR11_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR11_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR11_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR11_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR11_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR11_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR11_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR11 ========================================================= */
+#define ADC1_TAR11_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR11_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR11 ========================================================= */
+#define ADC1_TLR11_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR11_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR12 ========================================================= */
+#define ADC1_TCR12_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR12_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR12_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR12_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR12_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR12_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR12_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR12_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR12 ========================================================= */
+#define ADC1_TAR12_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR12_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR12 ========================================================= */
+#define ADC1_TLR12_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR12_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR13 ========================================================= */
+#define ADC1_TCR13_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR13_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR13_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR13_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR13_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR13_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR13_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR13_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR13 ========================================================= */
+#define ADC1_TAR13_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR13_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR13 ========================================================= */
+#define ADC1_TLR13_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR13_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR14 ========================================================= */
+#define ADC1_TCR14_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR14_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR14_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR14_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR14_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR14_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR14_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR14_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR14 ========================================================= */
+#define ADC1_TAR14_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR14_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR14 ========================================================= */
+#define ADC1_TLR14_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR14_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR15 ========================================================= */
+#define ADC1_TCR15_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR15_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR15_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR15_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR15_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR15_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR15_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR15_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR15 ========================================================= */
+#define ADC1_TAR15_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR15_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR15 ========================================================= */
+#define ADC1_TLR15_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR15_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR16 ========================================================= */
+#define ADC1_TCR16_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR16_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR16_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR16_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR16_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR16_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR16_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR16_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR16 ========================================================= */
+#define ADC1_TAR16_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR16_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR16 ========================================================= */
+#define ADC1_TLR16_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR16_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR17 ========================================================= */
+#define ADC1_TCR17_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR17_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR17_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR17_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR17_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR17_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR17_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR17_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR17 ========================================================= */
+#define ADC1_TAR17_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR17_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR17 ========================================================= */
+#define ADC1_TLR17_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR17_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR18 ========================================================= */
+#define ADC1_TCR18_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR18_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR18_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR18_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR18_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR18_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR18_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR18_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR18 ========================================================= */
+#define ADC1_TAR18_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR18_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR18 ========================================================= */
+#define ADC1_TLR18_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR18_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR19 ========================================================= */
+#define ADC1_TCR19_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC1_TCR19_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC1_TCR19_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC1_TCR19_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC1_TCR19_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC1_TCR19_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC1_TCR19_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC1_TCR19_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR19 ========================================================= */
+#define ADC1_TAR19_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC1_TAR19_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR19 ========================================================= */
+#define ADC1_TLR19_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC1_TLR19_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================== CCR ========================================================== */
+#define ADC1_CCR_DELAY_Pos (8UL) /*!< DELAY (Bit 8) */
+#define ADC1_CCR_DELAY_Msk (0x3ff00UL) /*!< DELAY (Bitfield-Mask: 0x3ff) */
+#define ADC1_CCR_DUAL_Pos (0UL) /*!< DUAL (Bit 0) */
+#define ADC1_CCR_DUAL_Msk (0xfUL) /*!< DUAL (Bitfield-Mask: 0x0f) */
+/* ========================================================== CSR ========================================================== */
+#define ADC1_CSR_EOSMP_SLV_Pos (25UL) /*!< EOSMP_SLV (Bit 25) */
+#define ADC1_CSR_EOSMP_SLV_Msk (0x2000000UL) /*!< EOSMP_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_ADRDY_SLV_Pos (24UL) /*!< ADRDY_SLV (Bit 24) */
+#define ADC1_CSR_ADRDY_SLV_Msk (0x1000000UL) /*!< ADRDY_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD2_SLV_Pos (23UL) /*!< AWD2_SLV (Bit 23) */
+#define ADC1_CSR_AWD2_SLV_Msk (0x800000UL) /*!< AWD2_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD1_SLV_Pos (22UL) /*!< AWD1_SLV (Bit 22) */
+#define ADC1_CSR_AWD1_SLV_Msk (0x400000UL) /*!< AWD1_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD0_SLV_Pos (21UL) /*!< AWD0_SLV (Bit 21) */
+#define ADC1_CSR_AWD0_SLV_Msk (0x200000UL) /*!< AWD0_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_OVR_SLV_Pos (20UL) /*!< OVR_SLV (Bit 20) */
+#define ADC1_CSR_OVR_SLV_Msk (0x100000UL) /*!< OVR_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_JEOS_SLV_Pos (19UL) /*!< JEOS_SLV (Bit 19) */
+#define ADC1_CSR_JEOS_SLV_Msk (0x80000UL) /*!< JEOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_JEOC_SLV_Pos (18UL) /*!< JEOC_SLV (Bit 18) */
+#define ADC1_CSR_JEOC_SLV_Msk (0x40000UL) /*!< JEOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_EOS_SLV_Pos (17UL) /*!< EOS_SLV (Bit 17) */
+#define ADC1_CSR_EOS_SLV_Msk (0x20000UL) /*!< EOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_EOC_SLV_Pos (16UL) /*!< EOC_SLV (Bit 16) */
+#define ADC1_CSR_EOC_SLV_Msk (0x10000UL) /*!< EOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_EOSMP_MST_Pos (9UL) /*!< EOSMP_MST (Bit 9) */
+#define ADC1_CSR_EOSMP_MST_Msk (0x200UL) /*!< EOSMP_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_ADRDY_MST_Pos (8UL) /*!< ADRDY_MST (Bit 8) */
+#define ADC1_CSR_ADRDY_MST_Msk (0x100UL) /*!< ADRDY_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD2_MST_Pos (7UL) /*!< AWD2_MST (Bit 7) */
+#define ADC1_CSR_AWD2_MST_Msk (0x80UL) /*!< AWD2_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD1_MST_Pos (6UL) /*!< AWD1_MST (Bit 6) */
+#define ADC1_CSR_AWD1_MST_Msk (0x40UL) /*!< AWD1_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_AWD0_MST_Pos (5UL) /*!< AWD0_MST (Bit 5) */
+#define ADC1_CSR_AWD0_MST_Msk (0x20UL) /*!< AWD0_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_OVR_MST_Pos (4UL) /*!< OVR_MST (Bit 4) */
+#define ADC1_CSR_OVR_MST_Msk (0x10UL) /*!< OVR_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_JEOS_MST_Pos (3UL) /*!< JEOS_MST (Bit 3) */
+#define ADC1_CSR_JEOS_MST_Msk (0x8UL) /*!< JEOS_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_JEOC_MST_Pos (2UL) /*!< JEOC_MST (Bit 2) */
+#define ADC1_CSR_JEOC_MST_Msk (0x4UL) /*!< JEOC_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_EOS_MST_Pos (1UL) /*!< EOS_MST (Bit 1) */
+#define ADC1_CSR_EOS_MST_Msk (0x2UL) /*!< EOS_MST (Bitfield-Mask: 0x01) */
+#define ADC1_CSR_EOC_MST_Pos (0UL) /*!< EOC_MST (Bit 0) */
+#define ADC1_CSR_EOC_MST_Msk (0x1UL) /*!< EOC_MST (Bitfield-Mask: 0x01) */
+/* ========================================================== CDR ========================================================== */
+#define ADC1_CDR_RDATA_SLV_Pos (16UL) /*!< RDATA_SLV (Bit 16) */
+#define ADC1_CDR_RDATA_SLV_Msk (0xffff0000UL) /*!< RDATA_SLV (Bitfield-Mask: 0xffff) */
+#define ADC1_CDR_RDATA_MST_Pos (0UL) /*!< RDATA_MST (Bit 0) */
+#define ADC1_CDR_RDATA_MST_Msk (0xffffUL) /*!< RDATA_MST (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ ADC2 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define ADC2_CR_ADCALDIF_Pos (7UL) /*!< ADCALDIF (Bit 7) */
+#define ADC2_CR_ADCALDIF_Msk (0x80UL) /*!< ADCALDIF (Bitfield-Mask: 0x01) */
+#define ADC2_CR_ADCAL_Pos (6UL) /*!< ADCAL (Bit 6) */
+#define ADC2_CR_ADCAL_Msk (0x40UL) /*!< ADCAL (Bitfield-Mask: 0x01) */
+#define ADC2_CR_JADSTP_Pos (5UL) /*!< JADSTP (Bit 5) */
+#define ADC2_CR_JADSTP_Msk (0x20UL) /*!< JADSTP (Bitfield-Mask: 0x01) */
+#define ADC2_CR_ADSTP_Pos (4UL) /*!< ADSTP (Bit 4) */
+#define ADC2_CR_ADSTP_Msk (0x10UL) /*!< ADSTP (Bitfield-Mask: 0x01) */
+#define ADC2_CR_JADSTART_Pos (3UL) /*!< JADSTART (Bit 3) */
+#define ADC2_CR_JADSTART_Msk (0x8UL) /*!< JADSTART (Bitfield-Mask: 0x01) */
+#define ADC2_CR_ADSTART_Pos (2UL) /*!< ADSTART (Bit 2) */
+#define ADC2_CR_ADSTART_Msk (0x4UL) /*!< ADSTART (Bitfield-Mask: 0x01) */
+#define ADC2_CR_ADDIS_Pos (1UL) /*!< ADDIS (Bit 1) */
+#define ADC2_CR_ADDIS_Msk (0x2UL) /*!< ADDIS (Bitfield-Mask: 0x01) */
+#define ADC2_CR_ADEN_Pos (0UL) /*!< ADEN (Bit 0) */
+#define ADC2_CR_ADEN_Msk (0x1UL) /*!< ADEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR0 ========================================================= */
+#define ADC2_CFGR0_OVSCAL_Pos (28UL) /*!< OVSCAL (Bit 28) */
+#define ADC2_CFGR0_OVSCAL_Msk (0x70000000UL) /*!< OVSCAL (Bitfield-Mask: 0x07) */
+#define ADC2_CFGR0_CONT_Pos (23UL) /*!< CONT (Bit 23) */
+#define ADC2_CFGR0_CONT_Msk (0x800000UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_JAUTO_Pos (22UL) /*!< JAUTO (Bit 22) */
+#define ADC2_CFGR0_JAUTO_Msk (0x400000UL) /*!< JAUTO (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_JDISCEN_Pos (20UL) /*!< JDISCEN (Bit 20) */
+#define ADC2_CFGR0_JDISCEN_Msk (0x100000UL) /*!< JDISCEN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_DISCNUM_Pos (17UL) /*!< DISCNUM (Bit 17) */
+#define ADC2_CFGR0_DISCNUM_Msk (0xe0000UL) /*!< DISCNUM (Bitfield-Mask: 0x07) */
+#define ADC2_CFGR0_DISCEN_Pos (16UL) /*!< DISCEN (Bit 16) */
+#define ADC2_CFGR0_DISCEN_Msk (0x10000UL) /*!< DISCEN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_OVRMOD_Pos (15UL) /*!< OVRMOD (Bit 15) */
+#define ADC2_CFGR0_OVRMOD_Msk (0x8000UL) /*!< OVRMOD (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_SDMAEN_Pos (14UL) /*!< SDMAEN (Bit 14) */
+#define ADC2_CFGR0_SDMAEN_Msk (0x4000UL) /*!< SDMAEN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_TROVS_Pos (12UL) /*!< TROVS (Bit 12) */
+#define ADC2_CFGR0_TROVS_Msk (0x1000UL) /*!< TROVS (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_OVSS_Pos (8UL) /*!< OVSS (Bit 8) */
+#define ADC2_CFGR0_OVSS_Msk (0xf00UL) /*!< OVSS (Bitfield-Mask: 0x0f) */
+#define ADC2_CFGR0_ROVSM_Pos (7UL) /*!< ROVSM (Bit 7) */
+#define ADC2_CFGR0_ROVSM_Msk (0x80UL) /*!< ROVSM (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_OVSR_Pos (4UL) /*!< OVSR (Bit 4) */
+#define ADC2_CFGR0_OVSR_Msk (0x70UL) /*!< OVSR (Bitfield-Mask: 0x07) */
+#define ADC2_CFGR0_JOVSE_Pos (1UL) /*!< JOVSE (Bit 1) */
+#define ADC2_CFGR0_JOVSE_Msk (0x2UL) /*!< JOVSE (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR0_ROVSE_Pos (0UL) /*!< ROVSE (Bit 0) */
+#define ADC2_CFGR0_ROVSE_Msk (0x1UL) /*!< ROVSE (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR1 ========================================================= */
+#define ADC2_CFGR1_JAWD2EN_Pos (14UL) /*!< JAWD2EN (Bit 14) */
+#define ADC2_CFGR1_JAWD2EN_Msk (0x4000UL) /*!< JAWD2EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_JAWD1EN_Pos (13UL) /*!< JAWD1EN (Bit 13) */
+#define ADC2_CFGR1_JAWD1EN_Msk (0x2000UL) /*!< JAWD1EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_JAWD0EN_Pos (12UL) /*!< JAWD0EN (Bit 12) */
+#define ADC2_CFGR1_JAWD0EN_Msk (0x1000UL) /*!< JAWD0EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_AWD2EN_Pos (10UL) /*!< AWD2EN (Bit 10) */
+#define ADC2_CFGR1_AWD2EN_Msk (0x400UL) /*!< AWD2EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_AWD1EN_Pos (9UL) /*!< AWD1EN (Bit 9) */
+#define ADC2_CFGR1_AWD1EN_Msk (0x200UL) /*!< AWD1EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_AWD0EN_Pos (8UL) /*!< AWD0EN (Bit 8) */
+#define ADC2_CFGR1_AWD0EN_Msk (0x100UL) /*!< AWD0EN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_ISEL_Pos (4UL) /*!< ISEL (Bit 4) */
+#define ADC2_CFGR1_ISEL_Msk (0x30UL) /*!< ISEL (Bitfield-Mask: 0x03) */
+#define ADC2_CFGR1_CHEN_Pos (3UL) /*!< CHEN (Bit 3) */
+#define ADC2_CFGR1_CHEN_Msk (0x8UL) /*!< CHEN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_REFEN_Pos (1UL) /*!< REFEN (Bit 1) */
+#define ADC2_CFGR1_REFEN_Msk (0x2UL) /*!< REFEN (Bitfield-Mask: 0x01) */
+#define ADC2_CFGR1_BIASEN_Pos (0UL) /*!< BIASEN (Bit 0) */
+#define ADC2_CFGR1_BIASEN_Msk (0x1UL) /*!< BIASEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define ADC2_ISR_EOSMP_Pos (9UL) /*!< EOSMP (Bit 9) */
+#define ADC2_ISR_EOSMP_Msk (0x200UL) /*!< EOSMP (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_ADRDY_Pos (8UL) /*!< ADRDY (Bit 8) */
+#define ADC2_ISR_ADRDY_Msk (0x100UL) /*!< ADRDY (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_AWD2_Pos (7UL) /*!< AWD2 (Bit 7) */
+#define ADC2_ISR_AWD2_Msk (0x80UL) /*!< AWD2 (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_AWD1_Pos (6UL) /*!< AWD1 (Bit 6) */
+#define ADC2_ISR_AWD1_Msk (0x40UL) /*!< AWD1 (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_AWD0_Pos (5UL) /*!< AWD0 (Bit 5) */
+#define ADC2_ISR_AWD0_Msk (0x20UL) /*!< AWD0 (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_OVR_Pos (4UL) /*!< OVR (Bit 4) */
+#define ADC2_ISR_OVR_Msk (0x10UL) /*!< OVR (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_JEOS_Pos (3UL) /*!< JEOS (Bit 3) */
+#define ADC2_ISR_JEOS_Msk (0x8UL) /*!< JEOS (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_JEOC_Pos (2UL) /*!< JEOC (Bit 2) */
+#define ADC2_ISR_JEOC_Msk (0x4UL) /*!< JEOC (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */
+#define ADC2_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */
+#define ADC2_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */
+#define ADC2_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define ADC2_IER_EOSMPIE_Pos (9UL) /*!< EOSMPIE (Bit 9) */
+#define ADC2_IER_EOSMPIE_Msk (0x200UL) /*!< EOSMPIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_ADRDYIE_Pos (8UL) /*!< ADRDYIE (Bit 8) */
+#define ADC2_IER_ADRDYIE_Msk (0x100UL) /*!< ADRDYIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_AWD2IE_Pos (7UL) /*!< AWD2IE (Bit 7) */
+#define ADC2_IER_AWD2IE_Msk (0x80UL) /*!< AWD2IE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_AWD1IE_Pos (6UL) /*!< AWD1IE (Bit 6) */
+#define ADC2_IER_AWD1IE_Msk (0x40UL) /*!< AWD1IE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_AWD0IE_Pos (5UL) /*!< AWD0IE (Bit 5) */
+#define ADC2_IER_AWD0IE_Msk (0x20UL) /*!< AWD0IE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_OVRIE_Pos (4UL) /*!< OVRIE (Bit 4) */
+#define ADC2_IER_OVRIE_Msk (0x10UL) /*!< OVRIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_JEOSIE_Pos (3UL) /*!< JEOSIE (Bit 3) */
+#define ADC2_IER_JEOSIE_Msk (0x8UL) /*!< JEOSIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_JEOCIE_Pos (2UL) /*!< JEOCIE (Bit 2) */
+#define ADC2_IER_JEOCIE_Msk (0x4UL) /*!< JEOCIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_EOSIE_Pos (1UL) /*!< EOSIE (Bit 1) */
+#define ADC2_IER_EOSIE_Msk (0x2UL) /*!< EOSIE (Bitfield-Mask: 0x01) */
+#define ADC2_IER_EOCIE_Pos (0UL) /*!< EOCIE (Bit 0) */
+#define ADC2_IER_EOCIE_Msk (0x1UL) /*!< EOCIE (Bitfield-Mask: 0x01) */
+/* ======================================================== SIGSEL ========================================================= */
+#define ADC2_SIGSEL_SIGSEL_Pos (0UL) /*!< SIGSEL (Bit 0) */
+#define ADC2_SIGSEL_SIGSEL_Msk (0xfffffUL) /*!< SIGSEL (Bitfield-Mask: 0xfffff) */
+/* ========================================================= SMPR0 ========================================================= */
+#define ADC2_SMPR0_SMP7_Pos (28UL) /*!< SMP7 (Bit 28) */
+#define ADC2_SMPR0_SMP7_Msk (0x70000000UL) /*!< SMP7 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP6_Pos (24UL) /*!< SMP6 (Bit 24) */
+#define ADC2_SMPR0_SMP6_Msk (0x7000000UL) /*!< SMP6 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP5_Pos (20UL) /*!< SMP5 (Bit 20) */
+#define ADC2_SMPR0_SMP5_Msk (0x700000UL) /*!< SMP5 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP4_Pos (16UL) /*!< SMP4 (Bit 16) */
+#define ADC2_SMPR0_SMP4_Msk (0x70000UL) /*!< SMP4 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP3_Pos (12UL) /*!< SMP3 (Bit 12) */
+#define ADC2_SMPR0_SMP3_Msk (0x7000UL) /*!< SMP3 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP2_Pos (8UL) /*!< SMP2 (Bit 8) */
+#define ADC2_SMPR0_SMP2_Msk (0x700UL) /*!< SMP2 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP1_Pos (4UL) /*!< SMP1 (Bit 4) */
+#define ADC2_SMPR0_SMP1_Msk (0x70UL) /*!< SMP1 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR0_SMP0_Pos (0UL) /*!< SMP0 (Bit 0) */
+#define ADC2_SMPR0_SMP0_Msk (0x7UL) /*!< SMP0 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR1 ========================================================= */
+#define ADC2_SMPR1_SMP15_Pos (28UL) /*!< SMP15 (Bit 28) */
+#define ADC2_SMPR1_SMP15_Msk (0x70000000UL) /*!< SMP15 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP14_Pos (24UL) /*!< SMP14 (Bit 24) */
+#define ADC2_SMPR1_SMP14_Msk (0x7000000UL) /*!< SMP14 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP13_Pos (20UL) /*!< SMP13 (Bit 20) */
+#define ADC2_SMPR1_SMP13_Msk (0x700000UL) /*!< SMP13 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP12_Pos (16UL) /*!< SMP12 (Bit 16) */
+#define ADC2_SMPR1_SMP12_Msk (0x70000UL) /*!< SMP12 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP11_Pos (12UL) /*!< SMP11 (Bit 12) */
+#define ADC2_SMPR1_SMP11_Msk (0x7000UL) /*!< SMP11 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP10_Pos (8UL) /*!< SMP10 (Bit 8) */
+#define ADC2_SMPR1_SMP10_Msk (0x700UL) /*!< SMP10 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP9_Pos (4UL) /*!< SMP9 (Bit 4) */
+#define ADC2_SMPR1_SMP9_Msk (0x70UL) /*!< SMP9 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR1_SMP8_Pos (0UL) /*!< SMP8 (Bit 0) */
+#define ADC2_SMPR1_SMP8_Msk (0x7UL) /*!< SMP8 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR2 ========================================================= */
+#define ADC2_SMPR2_SMP19_Pos (12UL) /*!< SMP19 (Bit 12) */
+#define ADC2_SMPR2_SMP19_Msk (0x7000UL) /*!< SMP19 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR2_SMP18_Pos (8UL) /*!< SMP18 (Bit 8) */
+#define ADC2_SMPR2_SMP18_Msk (0x700UL) /*!< SMP18 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR2_SMP17_Pos (4UL) /*!< SMP17 (Bit 4) */
+#define ADC2_SMPR2_SMP17_Msk (0x70UL) /*!< SMP17 (Bitfield-Mask: 0x07) */
+#define ADC2_SMPR2_SMP16_Pos (0UL) /*!< SMP16 (Bit 0) */
+#define ADC2_SMPR2_SMP16_Msk (0x7UL) /*!< SMP16 (Bitfield-Mask: 0x07) */
+/* ========================================================= CALR0 ========================================================= */
+#define ADC2_CALR0_SAT7_Pos (31UL) /*!< SAT7 (Bit 31) */
+#define ADC2_CALR0_SAT7_Msk (0x80000000UL) /*!< SAT7 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL7_Pos (28UL) /*!< CAL7 (Bit 28) */
+#define ADC2_CALR0_CAL7_Msk (0x30000000UL) /*!< CAL7 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT6_Pos (27UL) /*!< SAT6 (Bit 27) */
+#define ADC2_CALR0_SAT6_Msk (0x8000000UL) /*!< SAT6 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL6_Pos (24UL) /*!< CAL6 (Bit 24) */
+#define ADC2_CALR0_CAL6_Msk (0x3000000UL) /*!< CAL6 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT5_Pos (23UL) /*!< SAT5 (Bit 23) */
+#define ADC2_CALR0_SAT5_Msk (0x800000UL) /*!< SAT5 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL5_Pos (20UL) /*!< CAL5 (Bit 20) */
+#define ADC2_CALR0_CAL5_Msk (0x300000UL) /*!< CAL5 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT4_Pos (19UL) /*!< SAT4 (Bit 19) */
+#define ADC2_CALR0_SAT4_Msk (0x80000UL) /*!< SAT4 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL4_Pos (16UL) /*!< CAL4 (Bit 16) */
+#define ADC2_CALR0_CAL4_Msk (0x30000UL) /*!< CAL4 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT3_Pos (15UL) /*!< SAT3 (Bit 15) */
+#define ADC2_CALR0_SAT3_Msk (0x8000UL) /*!< SAT3 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL3_Pos (12UL) /*!< CAL3 (Bit 12) */
+#define ADC2_CALR0_CAL3_Msk (0x3000UL) /*!< CAL3 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT2_Pos (11UL) /*!< SAT2 (Bit 11) */
+#define ADC2_CALR0_SAT2_Msk (0x800UL) /*!< SAT2 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL2_Pos (8UL) /*!< CAL2 (Bit 8) */
+#define ADC2_CALR0_CAL2_Msk (0x300UL) /*!< CAL2 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT1_Pos (7UL) /*!< SAT1 (Bit 7) */
+#define ADC2_CALR0_SAT1_Msk (0x80UL) /*!< SAT1 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL1_Pos (4UL) /*!< CAL1 (Bit 4) */
+#define ADC2_CALR0_CAL1_Msk (0x30UL) /*!< CAL1 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR0_SAT0_Pos (3UL) /*!< SAT0 (Bit 3) */
+#define ADC2_CALR0_SAT0_Msk (0x8UL) /*!< SAT0 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR0_CAL0_Pos (0UL) /*!< CAL0 (Bit 0) */
+#define ADC2_CALR0_CAL0_Msk (0x3UL) /*!< CAL0 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR1 ========================================================= */
+#define ADC2_CALR1_SAT15_Pos (31UL) /*!< SAT15 (Bit 31) */
+#define ADC2_CALR1_SAT15_Msk (0x80000000UL) /*!< SAT15 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL15_Pos (28UL) /*!< CAL15 (Bit 28) */
+#define ADC2_CALR1_CAL15_Msk (0x30000000UL) /*!< CAL15 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT14_Pos (27UL) /*!< SAT14 (Bit 27) */
+#define ADC2_CALR1_SAT14_Msk (0x8000000UL) /*!< SAT14 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL14_Pos (24UL) /*!< CAL14 (Bit 24) */
+#define ADC2_CALR1_CAL14_Msk (0x3000000UL) /*!< CAL14 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT13_Pos (23UL) /*!< SAT13 (Bit 23) */
+#define ADC2_CALR1_SAT13_Msk (0x800000UL) /*!< SAT13 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL13_Pos (20UL) /*!< CAL13 (Bit 20) */
+#define ADC2_CALR1_CAL13_Msk (0x300000UL) /*!< CAL13 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT12_Pos (19UL) /*!< SAT12 (Bit 19) */
+#define ADC2_CALR1_SAT12_Msk (0x80000UL) /*!< SAT12 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL12_Pos (16UL) /*!< CAL12 (Bit 16) */
+#define ADC2_CALR1_CAL12_Msk (0x30000UL) /*!< CAL12 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT11_Pos (15UL) /*!< SAT11 (Bit 15) */
+#define ADC2_CALR1_SAT11_Msk (0x8000UL) /*!< SAT11 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL11_Pos (12UL) /*!< CAL11 (Bit 12) */
+#define ADC2_CALR1_CAL11_Msk (0x3000UL) /*!< CAL11 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT10_Pos (11UL) /*!< SAT10 (Bit 11) */
+#define ADC2_CALR1_SAT10_Msk (0x800UL) /*!< SAT10 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL10_Pos (8UL) /*!< CAL10 (Bit 8) */
+#define ADC2_CALR1_CAL10_Msk (0x300UL) /*!< CAL10 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT9_Pos (7UL) /*!< SAT9 (Bit 7) */
+#define ADC2_CALR1_SAT9_Msk (0x80UL) /*!< SAT9 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL9_Pos (4UL) /*!< CAL9 (Bit 4) */
+#define ADC2_CALR1_CAL9_Msk (0x30UL) /*!< CAL9 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR1_SAT8_Pos (3UL) /*!< SAT8 (Bit 3) */
+#define ADC2_CALR1_SAT8_Msk (0x8UL) /*!< SAT8 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR1_CAL8_Pos (0UL) /*!< CAL8 (Bit 0) */
+#define ADC2_CALR1_CAL8_Msk (0x3UL) /*!< CAL8 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR2 ========================================================= */
+#define ADC2_CALR2_SAT19_Pos (15UL) /*!< SAT19 (Bit 15) */
+#define ADC2_CALR2_SAT19_Msk (0x8000UL) /*!< SAT19 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR2_CAL19_Pos (12UL) /*!< CAL19 (Bit 12) */
+#define ADC2_CALR2_CAL19_Msk (0x3000UL) /*!< CAL19 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR2_SAT18_Pos (11UL) /*!< SAT18 (Bit 11) */
+#define ADC2_CALR2_SAT18_Msk (0x800UL) /*!< SAT18 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR2_CAL18_Pos (8UL) /*!< CAL18 (Bit 8) */
+#define ADC2_CALR2_CAL18_Msk (0x300UL) /*!< CAL18 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR2_SAT17_Pos (7UL) /*!< SAT17 (Bit 7) */
+#define ADC2_CALR2_SAT17_Msk (0x80UL) /*!< SAT17 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR2_CAL17_Pos (4UL) /*!< CAL17 (Bit 4) */
+#define ADC2_CALR2_CAL17_Msk (0x30UL) /*!< CAL17 (Bitfield-Mask: 0x03) */
+#define ADC2_CALR2_SAT16_Pos (3UL) /*!< SAT16 (Bit 3) */
+#define ADC2_CALR2_SAT16_Msk (0x8UL) /*!< SAT16 (Bitfield-Mask: 0x01) */
+#define ADC2_CALR2_CAL16_Pos (0UL) /*!< CAL16 (Bit 0) */
+#define ADC2_CALR2_CAL16_Msk (0x3UL) /*!< CAL16 (Bitfield-Mask: 0x03) */
+/* ========================================================= SQR0 ========================================================== */
+#define ADC2_SQR0_SQ5_Pos (24UL) /*!< SQ5 (Bit 24) */
+#define ADC2_SQR0_SQ5_Msk (0x1f000000UL) /*!< SQ5 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR0_SQ4_Pos (18UL) /*!< SQ4 (Bit 18) */
+#define ADC2_SQR0_SQ4_Msk (0x7c0000UL) /*!< SQ4 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR0_SQ3_Pos (12UL) /*!< SQ3 (Bit 12) */
+#define ADC2_SQR0_SQ3_Msk (0x1f000UL) /*!< SQ3 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR0_SQ2_Pos (6UL) /*!< SQ2 (Bit 6) */
+#define ADC2_SQR0_SQ2_Msk (0x7c0UL) /*!< SQ2 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR0_SQ1_Pos (0UL) /*!< SQ1 (Bit 0) */
+#define ADC2_SQR0_SQ1_Msk (0x1fUL) /*!< SQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR1 ========================================================== */
+#define ADC2_SQR1_SQ10_Pos (24UL) /*!< SQ10 (Bit 24) */
+#define ADC2_SQR1_SQ10_Msk (0x1f000000UL) /*!< SQ10 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR1_SQ9_Pos (18UL) /*!< SQ9 (Bit 18) */
+#define ADC2_SQR1_SQ9_Msk (0x7c0000UL) /*!< SQ9 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR1_SQ8_Pos (12UL) /*!< SQ8 (Bit 12) */
+#define ADC2_SQR1_SQ8_Msk (0x1f000UL) /*!< SQ8 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR1_SQ7_Pos (6UL) /*!< SQ7 (Bit 6) */
+#define ADC2_SQR1_SQ7_Msk (0x7c0UL) /*!< SQ7 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR1_SQ6_Pos (0UL) /*!< SQ6 (Bit 0) */
+#define ADC2_SQR1_SQ6_Msk (0x1fUL) /*!< SQ6 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR2 ========================================================== */
+#define ADC2_SQR2_SQ15_Pos (24UL) /*!< SQ15 (Bit 24) */
+#define ADC2_SQR2_SQ15_Msk (0x1f000000UL) /*!< SQ15 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR2_SQ14_Pos (18UL) /*!< SQ14 (Bit 18) */
+#define ADC2_SQR2_SQ14_Msk (0x7c0000UL) /*!< SQ14 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR2_SQ13_Pos (12UL) /*!< SQ13 (Bit 12) */
+#define ADC2_SQR2_SQ13_Msk (0x1f000UL) /*!< SQ13 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR2_SQ12_Pos (6UL) /*!< SQ12 (Bit 6) */
+#define ADC2_SQR2_SQ12_Msk (0x7c0UL) /*!< SQ12 (Bitfield-Mask: 0x1f) */
+#define ADC2_SQR2_SQ11_Pos (0UL) /*!< SQ11 (Bit 0) */
+#define ADC2_SQR2_SQ11_Msk (0x1fUL) /*!< SQ11 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR3 ========================================================== */
+#define ADC2_SQR3_SQ16_Pos (0UL) /*!< SQ16 (Bit 0) */
+#define ADC2_SQR3_SQ16_Msk (0x1fUL) /*!< SQ16 (Bitfield-Mask: 0x1f) */
+/* ========================================================== LR =========================================================== */
+#define ADC2_LR_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define ADC2_LR_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define ADC2_LR_EXTEN_Pos (6UL) /*!< EXTEN (Bit 6) */
+#define ADC2_LR_EXTEN_Msk (0xc0UL) /*!< EXTEN (Bitfield-Mask: 0x03) */
+#define ADC2_LR_EXTSEL_Pos (0UL) /*!< EXTSEL (Bit 0) */
+#define ADC2_LR_EXTSEL_Msk (0x1fUL) /*!< EXTSEL (Bitfield-Mask: 0x1f) */
+/* ========================================================== DR =========================================================== */
+#define ADC2_DR_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */
+#define ADC2_DR_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MAXDR ========================================================= */
+#define ADC2_MAXDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC2_MAXDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MINDR ========================================================= */
+#define ADC2_MINDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC2_MINDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JSQR ========================================================== */
+#define ADC2_JSQR_JSQ4_Pos (18UL) /*!< JSQ4 (Bit 18) */
+#define ADC2_JSQR_JSQ4_Msk (0x7c0000UL) /*!< JSQ4 (Bitfield-Mask: 0x1f) */
+#define ADC2_JSQR_JSQ3_Pos (12UL) /*!< JSQ3 (Bit 12) */
+#define ADC2_JSQR_JSQ3_Msk (0x1f000UL) /*!< JSQ3 (Bitfield-Mask: 0x1f) */
+#define ADC2_JSQR_JSQ2_Pos (6UL) /*!< JSQ2 (Bit 6) */
+#define ADC2_JSQR_JSQ2_Msk (0x7c0UL) /*!< JSQ2 (Bitfield-Mask: 0x1f) */
+#define ADC2_JSQR_JSQ1_Pos (0UL) /*!< JSQ1 (Bit 0) */
+#define ADC2_JSQR_JSQ1_Msk (0x1fUL) /*!< JSQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================== JLR ========================================================== */
+#define ADC2_JLR_JLEN_Pos (8UL) /*!< JLEN (Bit 8) */
+#define ADC2_JLR_JLEN_Msk (0x300UL) /*!< JLEN (Bitfield-Mask: 0x03) */
+#define ADC2_JLR_JEXTEN_Pos (6UL) /*!< JEXTEN (Bit 6) */
+#define ADC2_JLR_JEXTEN_Msk (0xc0UL) /*!< JEXTEN (Bitfield-Mask: 0x03) */
+#define ADC2_JLR_JEXTSEL_Pos (0UL) /*!< JEXTSEL (Bit 0) */
+#define ADC2_JLR_JEXTSEL_Msk (0x1fUL) /*!< JEXTSEL (Bitfield-Mask: 0x1f) */
+/* ======================================================== MAXJDR ========================================================= */
+#define ADC2_MAXJDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC2_MAXJDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ======================================================== MINJDR ========================================================= */
+#define ADC2_MINJDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC2_MINJDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR0 ========================================================== */
+#define ADC2_JDR0_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC2_JDR0_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR1 ========================================================== */
+#define ADC2_JDR1_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC2_JDR1_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR2 ========================================================== */
+#define ADC2_JDR2_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC2_JDR2_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR3 ========================================================== */
+#define ADC2_JDR3_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC2_JDR3_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR0 ========================================================== */
+#define ADC2_TR0_HT0_Pos (16UL) /*!< HT0 (Bit 16) */
+#define ADC2_TR0_HT0_Msk (0xffff0000UL) /*!< HT0 (Bitfield-Mask: 0xffff) */
+#define ADC2_TR0_LT0_Pos (0UL) /*!< LT0 (Bit 0) */
+#define ADC2_TR0_LT0_Msk (0xffffUL) /*!< LT0 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR1 ========================================================== */
+#define ADC2_TR1_HT1_Pos (16UL) /*!< HT1 (Bit 16) */
+#define ADC2_TR1_HT1_Msk (0xffff0000UL) /*!< HT1 (Bitfield-Mask: 0xffff) */
+#define ADC2_TR1_LT1_Pos (0UL) /*!< LT1 (Bit 0) */
+#define ADC2_TR1_LT1_Msk (0xffffUL) /*!< LT1 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR2 ========================================================== */
+#define ADC2_TR2_HT2_Pos (16UL) /*!< HT2 (Bit 16) */
+#define ADC2_TR2_HT2_Msk (0xffff0000UL) /*!< HT2 (Bitfield-Mask: 0xffff) */
+#define ADC2_TR2_LT2_Pos (0UL) /*!< LT2 (Bit 0) */
+#define ADC2_TR2_LT2_Msk (0xffffUL) /*!< LT2 (Bitfield-Mask: 0xffff) */
+/* ======================================================== AWD0CR ========================================================= */
+#define ADC2_AWD0CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC2_AWD0CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC2_AWD0CR_AW0CH_Pos (0UL) /*!< AW0CH (Bit 0) */
+#define ADC2_AWD0CR_AW0CH_Msk (0xfffffUL) /*!< AW0CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD1CR ========================================================= */
+#define ADC2_AWD1CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC2_AWD1CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC2_AWD1CR_AW1CH_Pos (0UL) /*!< AW1CH (Bit 0) */
+#define ADC2_AWD1CR_AW1CH_Msk (0xfffffUL) /*!< AW1CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD2CR ========================================================= */
+#define ADC2_AWD2CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC2_AWD2CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC2_AWD2CR_AW2CH_Pos (0UL) /*!< AW2CH (Bit 0) */
+#define ADC2_AWD2CR_AW2CH_Msk (0xfffffUL) /*!< AW2CH (Bitfield-Mask: 0xfffff) */
+/* ========================================================= OFR0 ========================================================== */
+#define ADC2_OFR0_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC2_OFR0_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR1 ========================================================== */
+#define ADC2_OFR1_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC2_OFR1_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR2 ========================================================== */
+#define ADC2_OFR2_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC2_OFR2_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR3 ========================================================== */
+#define ADC2_OFR3_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC2_OFR3_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= GCR0 ========================================================== */
+#define ADC2_GCR0_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC2_GCR0_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR1 ========================================================== */
+#define ADC2_GCR1_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC2_GCR1_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR2 ========================================================== */
+#define ADC2_GCR2_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC2_GCR2_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR3 ========================================================== */
+#define ADC2_GCR3_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC2_GCR3_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= DISR ========================================================== */
+#define ADC2_DISR_DON19_Pos (19UL) /*!< DON19 (Bit 19) */
+#define ADC2_DISR_DON19_Msk (0x80000UL) /*!< DON19 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON18_Pos (18UL) /*!< DON18 (Bit 18) */
+#define ADC2_DISR_DON18_Msk (0x40000UL) /*!< DON18 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON17_Pos (17UL) /*!< DON17 (Bit 17) */
+#define ADC2_DISR_DON17_Msk (0x20000UL) /*!< DON17 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON16_Pos (16UL) /*!< DON16 (Bit 16) */
+#define ADC2_DISR_DON16_Msk (0x10000UL) /*!< DON16 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON15_Pos (15UL) /*!< DON15 (Bit 15) */
+#define ADC2_DISR_DON15_Msk (0x8000UL) /*!< DON15 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON14_Pos (14UL) /*!< DON14 (Bit 14) */
+#define ADC2_DISR_DON14_Msk (0x4000UL) /*!< DON14 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON13_Pos (13UL) /*!< DON13 (Bit 13) */
+#define ADC2_DISR_DON13_Msk (0x2000UL) /*!< DON13 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON12_Pos (12UL) /*!< DON12 (Bit 12) */
+#define ADC2_DISR_DON12_Msk (0x1000UL) /*!< DON12 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON11_Pos (11UL) /*!< DON11 (Bit 11) */
+#define ADC2_DISR_DON11_Msk (0x800UL) /*!< DON11 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON10_Pos (10UL) /*!< DON10 (Bit 10) */
+#define ADC2_DISR_DON10_Msk (0x400UL) /*!< DON10 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON9_Pos (9UL) /*!< DON9 (Bit 9) */
+#define ADC2_DISR_DON9_Msk (0x200UL) /*!< DON9 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON8_Pos (8UL) /*!< DON8 (Bit 8) */
+#define ADC2_DISR_DON8_Msk (0x100UL) /*!< DON8 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON7_Pos (7UL) /*!< DON7 (Bit 7) */
+#define ADC2_DISR_DON7_Msk (0x80UL) /*!< DON7 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON6_Pos (6UL) /*!< DON6 (Bit 6) */
+#define ADC2_DISR_DON6_Msk (0x40UL) /*!< DON6 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON5_Pos (5UL) /*!< DON5 (Bit 5) */
+#define ADC2_DISR_DON5_Msk (0x20UL) /*!< DON5 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON4_Pos (4UL) /*!< DON4 (Bit 4) */
+#define ADC2_DISR_DON4_Msk (0x10UL) /*!< DON4 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON3_Pos (3UL) /*!< DON3 (Bit 3) */
+#define ADC2_DISR_DON3_Msk (0x8UL) /*!< DON3 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON2_Pos (2UL) /*!< DON2 (Bit 2) */
+#define ADC2_DISR_DON2_Msk (0x4UL) /*!< DON2 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON1_Pos (1UL) /*!< DON1 (Bit 1) */
+#define ADC2_DISR_DON1_Msk (0x2UL) /*!< DON1 (Bitfield-Mask: 0x01) */
+#define ADC2_DISR_DON0_Pos (0UL) /*!< DON0 (Bit 0) */
+#define ADC2_DISR_DON0_Msk (0x1UL) /*!< DON0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DIER ========================================================== */
+#define ADC2_DIER_DONIE19_Pos (19UL) /*!< DONIE19 (Bit 19) */
+#define ADC2_DIER_DONIE19_Msk (0x80000UL) /*!< DONIE19 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE18_Pos (18UL) /*!< DONIE18 (Bit 18) */
+#define ADC2_DIER_DONIE18_Msk (0x40000UL) /*!< DONIE18 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE17_Pos (17UL) /*!< DONIE17 (Bit 17) */
+#define ADC2_DIER_DONIE17_Msk (0x20000UL) /*!< DONIE17 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE16_Pos (16UL) /*!< DONIE16 (Bit 16) */
+#define ADC2_DIER_DONIE16_Msk (0x10000UL) /*!< DONIE16 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE15_Pos (15UL) /*!< DONIE15 (Bit 15) */
+#define ADC2_DIER_DONIE15_Msk (0x8000UL) /*!< DONIE15 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE14_Pos (14UL) /*!< DONIE14 (Bit 14) */
+#define ADC2_DIER_DONIE14_Msk (0x4000UL) /*!< DONIE14 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE13_Pos (13UL) /*!< DONIE13 (Bit 13) */
+#define ADC2_DIER_DONIE13_Msk (0x2000UL) /*!< DONIE13 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE12_Pos (12UL) /*!< DONIE12 (Bit 12) */
+#define ADC2_DIER_DONIE12_Msk (0x1000UL) /*!< DONIE12 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE11_Pos (11UL) /*!< DONIE11 (Bit 11) */
+#define ADC2_DIER_DONIE11_Msk (0x800UL) /*!< DONIE11 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE10_Pos (10UL) /*!< DONIE10 (Bit 10) */
+#define ADC2_DIER_DONIE10_Msk (0x400UL) /*!< DONIE10 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE9_Pos (9UL) /*!< DONIE9 (Bit 9) */
+#define ADC2_DIER_DONIE9_Msk (0x200UL) /*!< DONIE9 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE8_Pos (8UL) /*!< DONIE8 (Bit 8) */
+#define ADC2_DIER_DONIE8_Msk (0x100UL) /*!< DONIE8 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE7_Pos (7UL) /*!< DONIE7 (Bit 7) */
+#define ADC2_DIER_DONIE7_Msk (0x80UL) /*!< DONIE7 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE6_Pos (6UL) /*!< DONIE6 (Bit 6) */
+#define ADC2_DIER_DONIE6_Msk (0x40UL) /*!< DONIE6 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE5_Pos (5UL) /*!< DONIE5 (Bit 5) */
+#define ADC2_DIER_DONIE5_Msk (0x20UL) /*!< DONIE5 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE4_Pos (4UL) /*!< DONIE4 (Bit 4) */
+#define ADC2_DIER_DONIE4_Msk (0x10UL) /*!< DONIE4 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE3_Pos (3UL) /*!< DONIE3 (Bit 3) */
+#define ADC2_DIER_DONIE3_Msk (0x8UL) /*!< DONIE3 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE2_Pos (2UL) /*!< DONIE2 (Bit 2) */
+#define ADC2_DIER_DONIE2_Msk (0x4UL) /*!< DONIE2 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE1_Pos (1UL) /*!< DONIE1 (Bit 1) */
+#define ADC2_DIER_DONIE1_Msk (0x2UL) /*!< DONIE1 (Bitfield-Mask: 0x01) */
+#define ADC2_DIER_DONIE0_Pos (0UL) /*!< DONIE0 (Bit 0) */
+#define ADC2_DIER_DONIE0_Msk (0x1UL) /*!< DONIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= CDR0 ========================================================== */
+#define ADC2_CDR0_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR0_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR1 ========================================================== */
+#define ADC2_CDR1_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR1_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR2 ========================================================== */
+#define ADC2_CDR2_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR2_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR3 ========================================================== */
+#define ADC2_CDR3_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR3_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR4 ========================================================== */
+#define ADC2_CDR4_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR4_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR5 ========================================================== */
+#define ADC2_CDR5_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR5_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR6 ========================================================== */
+#define ADC2_CDR6_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR6_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR7 ========================================================== */
+#define ADC2_CDR7_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR7_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR8 ========================================================== */
+#define ADC2_CDR8_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR8_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR9 ========================================================== */
+#define ADC2_CDR9_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR9_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR10 ========================================================= */
+#define ADC2_CDR10_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR10_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR11 ========================================================= */
+#define ADC2_CDR11_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR11_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR12 ========================================================= */
+#define ADC2_CDR12_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR12_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR13 ========================================================= */
+#define ADC2_CDR13_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR13_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR14 ========================================================= */
+#define ADC2_CDR14_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR14_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR15 ========================================================= */
+#define ADC2_CDR15_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR15_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR16 ========================================================= */
+#define ADC2_CDR16_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR16_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR17 ========================================================= */
+#define ADC2_CDR17_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR17_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR18 ========================================================= */
+#define ADC2_CDR18_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR18_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR19 ========================================================= */
+#define ADC2_CDR19_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC2_CDR19_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= HISR ========================================================== */
+#define ADC2_HISR_HLF19_Pos (19UL) /*!< HLF19 (Bit 19) */
+#define ADC2_HISR_HLF19_Msk (0x80000UL) /*!< HLF19 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF18_Pos (18UL) /*!< HLF18 (Bit 18) */
+#define ADC2_HISR_HLF18_Msk (0x40000UL) /*!< HLF18 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF17_Pos (17UL) /*!< HLF17 (Bit 17) */
+#define ADC2_HISR_HLF17_Msk (0x20000UL) /*!< HLF17 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF16_Pos (16UL) /*!< HLF16 (Bit 16) */
+#define ADC2_HISR_HLF16_Msk (0x10000UL) /*!< HLF16 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF15_Pos (15UL) /*!< HLF15 (Bit 15) */
+#define ADC2_HISR_HLF15_Msk (0x8000UL) /*!< HLF15 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF14_Pos (14UL) /*!< HLF14 (Bit 14) */
+#define ADC2_HISR_HLF14_Msk (0x4000UL) /*!< HLF14 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF13_Pos (13UL) /*!< HLF13 (Bit 13) */
+#define ADC2_HISR_HLF13_Msk (0x2000UL) /*!< HLF13 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF12_Pos (12UL) /*!< HLF12 (Bit 12) */
+#define ADC2_HISR_HLF12_Msk (0x1000UL) /*!< HLF12 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF11_Pos (11UL) /*!< HLF11 (Bit 11) */
+#define ADC2_HISR_HLF11_Msk (0x800UL) /*!< HLF11 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF10_Pos (10UL) /*!< HLF10 (Bit 10) */
+#define ADC2_HISR_HLF10_Msk (0x400UL) /*!< HLF10 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF9_Pos (9UL) /*!< HLF9 (Bit 9) */
+#define ADC2_HISR_HLF9_Msk (0x200UL) /*!< HLF9 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF8_Pos (8UL) /*!< HLF8 (Bit 8) */
+#define ADC2_HISR_HLF8_Msk (0x100UL) /*!< HLF8 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF7_Pos (7UL) /*!< HLF7 (Bit 7) */
+#define ADC2_HISR_HLF7_Msk (0x80UL) /*!< HLF7 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF6_Pos (6UL) /*!< HLF6 (Bit 6) */
+#define ADC2_HISR_HLF6_Msk (0x40UL) /*!< HLF6 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF5_Pos (5UL) /*!< HLF5 (Bit 5) */
+#define ADC2_HISR_HLF5_Msk (0x20UL) /*!< HLF5 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF4_Pos (4UL) /*!< HLF4 (Bit 4) */
+#define ADC2_HISR_HLF4_Msk (0x10UL) /*!< HLF4 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF3_Pos (3UL) /*!< HLF3 (Bit 3) */
+#define ADC2_HISR_HLF3_Msk (0x8UL) /*!< HLF3 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF2_Pos (2UL) /*!< HLF2 (Bit 2) */
+#define ADC2_HISR_HLF2_Msk (0x4UL) /*!< HLF2 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF1_Pos (1UL) /*!< HLF1 (Bit 1) */
+#define ADC2_HISR_HLF1_Msk (0x2UL) /*!< HLF1 (Bitfield-Mask: 0x01) */
+#define ADC2_HISR_HLF0_Pos (0UL) /*!< HLF0 (Bit 0) */
+#define ADC2_HISR_HLF0_Msk (0x1UL) /*!< HLF0 (Bitfield-Mask: 0x01) */
+/* ========================================================= HIER ========================================================== */
+#define ADC2_HIER_HLFIE19_Pos (19UL) /*!< HLFIE19 (Bit 19) */
+#define ADC2_HIER_HLFIE19_Msk (0x80000UL) /*!< HLFIE19 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE18_Pos (18UL) /*!< HLFIE18 (Bit 18) */
+#define ADC2_HIER_HLFIE18_Msk (0x40000UL) /*!< HLFIE18 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE17_Pos (17UL) /*!< HLFIE17 (Bit 17) */
+#define ADC2_HIER_HLFIE17_Msk (0x20000UL) /*!< HLFIE17 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE16_Pos (16UL) /*!< HLFIE16 (Bit 16) */
+#define ADC2_HIER_HLFIE16_Msk (0x10000UL) /*!< HLFIE16 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE15_Pos (15UL) /*!< HLFIE15 (Bit 15) */
+#define ADC2_HIER_HLFIE15_Msk (0x8000UL) /*!< HLFIE15 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE14_Pos (14UL) /*!< HLFIE14 (Bit 14) */
+#define ADC2_HIER_HLFIE14_Msk (0x4000UL) /*!< HLFIE14 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE13_Pos (13UL) /*!< HLFIE13 (Bit 13) */
+#define ADC2_HIER_HLFIE13_Msk (0x2000UL) /*!< HLFIE13 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE12_Pos (12UL) /*!< HLFIE12 (Bit 12) */
+#define ADC2_HIER_HLFIE12_Msk (0x1000UL) /*!< HLFIE12 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE11_Pos (11UL) /*!< HLFIE11 (Bit 11) */
+#define ADC2_HIER_HLFIE11_Msk (0x800UL) /*!< HLFIE11 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE10_Pos (10UL) /*!< HLFIE10 (Bit 10) */
+#define ADC2_HIER_HLFIE10_Msk (0x400UL) /*!< HLFIE10 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE9_Pos (9UL) /*!< HLFIE9 (Bit 9) */
+#define ADC2_HIER_HLFIE9_Msk (0x200UL) /*!< HLFIE9 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE8_Pos (8UL) /*!< HLFIE8 (Bit 8) */
+#define ADC2_HIER_HLFIE8_Msk (0x100UL) /*!< HLFIE8 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE7_Pos (7UL) /*!< HLFIE7 (Bit 7) */
+#define ADC2_HIER_HLFIE7_Msk (0x80UL) /*!< HLFIE7 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE6_Pos (6UL) /*!< HLFIE6 (Bit 6) */
+#define ADC2_HIER_HLFIE6_Msk (0x40UL) /*!< HLFIE6 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE5_Pos (5UL) /*!< HLFIE5 (Bit 5) */
+#define ADC2_HIER_HLFIE5_Msk (0x20UL) /*!< HLFIE5 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE4_Pos (4UL) /*!< HLFIE4 (Bit 4) */
+#define ADC2_HIER_HLFIE4_Msk (0x10UL) /*!< HLFIE4 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE3_Pos (3UL) /*!< HLFIE3 (Bit 3) */
+#define ADC2_HIER_HLFIE3_Msk (0x8UL) /*!< HLFIE3 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE2_Pos (2UL) /*!< HLFIE2 (Bit 2) */
+#define ADC2_HIER_HLFIE2_Msk (0x4UL) /*!< HLFIE2 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE1_Pos (1UL) /*!< HLFIE1 (Bit 1) */
+#define ADC2_HIER_HLFIE1_Msk (0x2UL) /*!< HLFIE1 (Bitfield-Mask: 0x01) */
+#define ADC2_HIER_HLFIE0_Pos (0UL) /*!< HLFIE0 (Bit 0) */
+#define ADC2_HIER_HLFIE0_Msk (0x1UL) /*!< HLFIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FISR ========================================================== */
+#define ADC2_FISR_FUL19_Pos (19UL) /*!< FUL19 (Bit 19) */
+#define ADC2_FISR_FUL19_Msk (0x80000UL) /*!< FUL19 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL18_Pos (18UL) /*!< FUL18 (Bit 18) */
+#define ADC2_FISR_FUL18_Msk (0x40000UL) /*!< FUL18 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL17_Pos (17UL) /*!< FUL17 (Bit 17) */
+#define ADC2_FISR_FUL17_Msk (0x20000UL) /*!< FUL17 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL16_Pos (16UL) /*!< FUL16 (Bit 16) */
+#define ADC2_FISR_FUL16_Msk (0x10000UL) /*!< FUL16 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL15_Pos (15UL) /*!< FUL15 (Bit 15) */
+#define ADC2_FISR_FUL15_Msk (0x8000UL) /*!< FUL15 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL14_Pos (14UL) /*!< FUL14 (Bit 14) */
+#define ADC2_FISR_FUL14_Msk (0x4000UL) /*!< FUL14 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL13_Pos (13UL) /*!< FUL13 (Bit 13) */
+#define ADC2_FISR_FUL13_Msk (0x2000UL) /*!< FUL13 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL12_Pos (12UL) /*!< FUL12 (Bit 12) */
+#define ADC2_FISR_FUL12_Msk (0x1000UL) /*!< FUL12 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL11_Pos (11UL) /*!< FUL11 (Bit 11) */
+#define ADC2_FISR_FUL11_Msk (0x800UL) /*!< FUL11 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL10_Pos (10UL) /*!< FUL10 (Bit 10) */
+#define ADC2_FISR_FUL10_Msk (0x400UL) /*!< FUL10 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL9_Pos (9UL) /*!< FUL9 (Bit 9) */
+#define ADC2_FISR_FUL9_Msk (0x200UL) /*!< FUL9 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL8_Pos (8UL) /*!< FUL8 (Bit 8) */
+#define ADC2_FISR_FUL8_Msk (0x100UL) /*!< FUL8 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL7_Pos (7UL) /*!< FUL7 (Bit 7) */
+#define ADC2_FISR_FUL7_Msk (0x80UL) /*!< FUL7 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL6_Pos (6UL) /*!< FUL6 (Bit 6) */
+#define ADC2_FISR_FUL6_Msk (0x40UL) /*!< FUL6 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL5_Pos (5UL) /*!< FUL5 (Bit 5) */
+#define ADC2_FISR_FUL5_Msk (0x20UL) /*!< FUL5 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL4_Pos (4UL) /*!< FUL4 (Bit 4) */
+#define ADC2_FISR_FUL4_Msk (0x10UL) /*!< FUL4 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL3_Pos (3UL) /*!< FUL3 (Bit 3) */
+#define ADC2_FISR_FUL3_Msk (0x8UL) /*!< FUL3 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL2_Pos (2UL) /*!< FUL2 (Bit 2) */
+#define ADC2_FISR_FUL2_Msk (0x4UL) /*!< FUL2 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL1_Pos (1UL) /*!< FUL1 (Bit 1) */
+#define ADC2_FISR_FUL1_Msk (0x2UL) /*!< FUL1 (Bitfield-Mask: 0x01) */
+#define ADC2_FISR_FUL0_Pos (0UL) /*!< FUL0 (Bit 0) */
+#define ADC2_FISR_FUL0_Msk (0x1UL) /*!< FUL0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FIER ========================================================== */
+#define ADC2_FIER_FULIE19_Pos (19UL) /*!< FULIE19 (Bit 19) */
+#define ADC2_FIER_FULIE19_Msk (0x80000UL) /*!< FULIE19 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE18_Pos (18UL) /*!< FULIE18 (Bit 18) */
+#define ADC2_FIER_FULIE18_Msk (0x40000UL) /*!< FULIE18 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE17_Pos (17UL) /*!< FULIE17 (Bit 17) */
+#define ADC2_FIER_FULIE17_Msk (0x20000UL) /*!< FULIE17 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE16_Pos (16UL) /*!< FULIE16 (Bit 16) */
+#define ADC2_FIER_FULIE16_Msk (0x10000UL) /*!< FULIE16 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE15_Pos (15UL) /*!< FULIE15 (Bit 15) */
+#define ADC2_FIER_FULIE15_Msk (0x8000UL) /*!< FULIE15 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE14_Pos (14UL) /*!< FULIE14 (Bit 14) */
+#define ADC2_FIER_FULIE14_Msk (0x4000UL) /*!< FULIE14 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE13_Pos (13UL) /*!< FULIE13 (Bit 13) */
+#define ADC2_FIER_FULIE13_Msk (0x2000UL) /*!< FULIE13 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE12_Pos (12UL) /*!< FULIE12 (Bit 12) */
+#define ADC2_FIER_FULIE12_Msk (0x1000UL) /*!< FULIE12 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE11_Pos (11UL) /*!< FULIE11 (Bit 11) */
+#define ADC2_FIER_FULIE11_Msk (0x800UL) /*!< FULIE11 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE10_Pos (10UL) /*!< FULIE10 (Bit 10) */
+#define ADC2_FIER_FULIE10_Msk (0x400UL) /*!< FULIE10 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE9_Pos (9UL) /*!< FULIE9 (Bit 9) */
+#define ADC2_FIER_FULIE9_Msk (0x200UL) /*!< FULIE9 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE8_Pos (8UL) /*!< FULIE8 (Bit 8) */
+#define ADC2_FIER_FULIE8_Msk (0x100UL) /*!< FULIE8 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE7_Pos (7UL) /*!< FULIE7 (Bit 7) */
+#define ADC2_FIER_FULIE7_Msk (0x80UL) /*!< FULIE7 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE6_Pos (6UL) /*!< FULIE6 (Bit 6) */
+#define ADC2_FIER_FULIE6_Msk (0x40UL) /*!< FULIE6 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE5_Pos (5UL) /*!< FULIE5 (Bit 5) */
+#define ADC2_FIER_FULIE5_Msk (0x20UL) /*!< FULIE5 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE4_Pos (4UL) /*!< FULIE4 (Bit 4) */
+#define ADC2_FIER_FULIE4_Msk (0x10UL) /*!< FULIE4 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE3_Pos (3UL) /*!< FULIE3 (Bit 3) */
+#define ADC2_FIER_FULIE3_Msk (0x8UL) /*!< FULIE3 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE2_Pos (2UL) /*!< FULIE2 (Bit 2) */
+#define ADC2_FIER_FULIE2_Msk (0x4UL) /*!< FULIE2 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE1_Pos (1UL) /*!< FULIE1 (Bit 1) */
+#define ADC2_FIER_FULIE1_Msk (0x2UL) /*!< FULIE1 (Bitfield-Mask: 0x01) */
+#define ADC2_FIER_FULIE0_Pos (0UL) /*!< FULIE0 (Bit 0) */
+#define ADC2_FIER_FULIE0_Msk (0x1UL) /*!< FULIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= TCR0 ========================================================== */
+#define ADC2_TCR0_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR0_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR0_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR0_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR0_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR0_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR0_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR0 ========================================================== */
+#define ADC2_TAR0_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR0_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR0 ========================================================== */
+#define ADC2_TLR0_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR0_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR1 ========================================================== */
+#define ADC2_TCR1_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR1_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR1_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR1_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR1_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR1_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR1_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR1 ========================================================== */
+#define ADC2_TAR1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR1_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR1 ========================================================== */
+#define ADC2_TLR1_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR1_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR2 ========================================================== */
+#define ADC2_TCR2_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR2_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR2_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR2_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR2_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR2_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR2_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR2 ========================================================== */
+#define ADC2_TAR2_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR2_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR2 ========================================================== */
+#define ADC2_TLR2_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR2_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR3 ========================================================== */
+#define ADC2_TCR3_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR3_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR3_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR3_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR3_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR3_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR3_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR3 ========================================================== */
+#define ADC2_TAR3_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR3_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR3 ========================================================== */
+#define ADC2_TLR3_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR3_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR4 ========================================================== */
+#define ADC2_TCR4_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR4_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR4_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR4_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR4_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR4_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR4_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR4_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR4 ========================================================== */
+#define ADC2_TAR4_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR4_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR4 ========================================================== */
+#define ADC2_TLR4_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR4_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR5 ========================================================== */
+#define ADC2_TCR5_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR5_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR5_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR5_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR5_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR5_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR5_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR5_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR5 ========================================================== */
+#define ADC2_TAR5_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR5_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR5 ========================================================== */
+#define ADC2_TLR5_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR5_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR6 ========================================================== */
+#define ADC2_TCR6_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR6_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR6_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR6_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR6_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR6_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR6_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR6_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR6 ========================================================== */
+#define ADC2_TAR6_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR6_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR6 ========================================================== */
+#define ADC2_TLR6_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR6_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR7 ========================================================== */
+#define ADC2_TCR7_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR7_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR7_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR7_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR7_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR7_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR7_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR7_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR7 ========================================================== */
+#define ADC2_TAR7_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR7_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR7 ========================================================== */
+#define ADC2_TLR7_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR7_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR8 ========================================================== */
+#define ADC2_TCR8_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR8_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR8_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR8_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR8_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR8_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR8_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR8_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR8 ========================================================== */
+#define ADC2_TAR8_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR8_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR8 ========================================================== */
+#define ADC2_TLR8_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR8_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR9 ========================================================== */
+#define ADC2_TCR9_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR9_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR9_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR9_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR9_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR9_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR9_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR9_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR9 ========================================================== */
+#define ADC2_TAR9_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR9_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR9 ========================================================== */
+#define ADC2_TLR9_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR9_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR10 ========================================================= */
+#define ADC2_TCR10_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR10_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR10_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR10_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR10_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR10_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR10_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR10_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR10 ========================================================= */
+#define ADC2_TAR10_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR10_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR10 ========================================================= */
+#define ADC2_TLR10_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR10_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR11 ========================================================= */
+#define ADC2_TCR11_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR11_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR11_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR11_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR11_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR11_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR11_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR11_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR11 ========================================================= */
+#define ADC2_TAR11_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR11_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR11 ========================================================= */
+#define ADC2_TLR11_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR11_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR12 ========================================================= */
+#define ADC2_TCR12_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR12_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR12_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR12_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR12_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR12_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR12_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR12_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR12 ========================================================= */
+#define ADC2_TAR12_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR12_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR12 ========================================================= */
+#define ADC2_TLR12_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR12_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR13 ========================================================= */
+#define ADC2_TCR13_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR13_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR13_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR13_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR13_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR13_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR13_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR13_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR13 ========================================================= */
+#define ADC2_TAR13_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR13_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR13 ========================================================= */
+#define ADC2_TLR13_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR13_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR14 ========================================================= */
+#define ADC2_TCR14_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR14_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR14_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR14_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR14_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR14_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR14_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR14_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR14 ========================================================= */
+#define ADC2_TAR14_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR14_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR14 ========================================================= */
+#define ADC2_TLR14_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR14_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR15 ========================================================= */
+#define ADC2_TCR15_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR15_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR15_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR15_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR15_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR15_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR15_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR15_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR15 ========================================================= */
+#define ADC2_TAR15_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR15_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR15 ========================================================= */
+#define ADC2_TLR15_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR15_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR16 ========================================================= */
+#define ADC2_TCR16_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR16_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR16_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR16_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR16_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR16_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR16_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR16_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR16 ========================================================= */
+#define ADC2_TAR16_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR16_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR16 ========================================================= */
+#define ADC2_TLR16_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR16_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR17 ========================================================= */
+#define ADC2_TCR17_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR17_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR17_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR17_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR17_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR17_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR17_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR17_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR17 ========================================================= */
+#define ADC2_TAR17_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR17_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR17 ========================================================= */
+#define ADC2_TLR17_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR17_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR18 ========================================================= */
+#define ADC2_TCR18_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR18_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR18_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR18_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR18_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR18_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR18_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR18_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR18 ========================================================= */
+#define ADC2_TAR18_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR18_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR18 ========================================================= */
+#define ADC2_TLR18_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR18_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR19 ========================================================= */
+#define ADC2_TCR19_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC2_TCR19_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC2_TCR19_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC2_TCR19_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC2_TCR19_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC2_TCR19_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC2_TCR19_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC2_TCR19_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR19 ========================================================= */
+#define ADC2_TAR19_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC2_TAR19_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR19 ========================================================= */
+#define ADC2_TLR19_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC2_TLR19_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================== CCR ========================================================== */
+#define ADC2_CCR_DELAY_Pos (8UL) /*!< DELAY (Bit 8) */
+#define ADC2_CCR_DELAY_Msk (0x3ff00UL) /*!< DELAY (Bitfield-Mask: 0x3ff) */
+#define ADC2_CCR_DUAL_Pos (0UL) /*!< DUAL (Bit 0) */
+#define ADC2_CCR_DUAL_Msk (0xfUL) /*!< DUAL (Bitfield-Mask: 0x0f) */
+/* ========================================================== CSR ========================================================== */
+#define ADC2_CSR_EOSMP_SLV_Pos (25UL) /*!< EOSMP_SLV (Bit 25) */
+#define ADC2_CSR_EOSMP_SLV_Msk (0x2000000UL) /*!< EOSMP_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_ADRDY_SLV_Pos (24UL) /*!< ADRDY_SLV (Bit 24) */
+#define ADC2_CSR_ADRDY_SLV_Msk (0x1000000UL) /*!< ADRDY_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD2_SLV_Pos (23UL) /*!< AWD2_SLV (Bit 23) */
+#define ADC2_CSR_AWD2_SLV_Msk (0x800000UL) /*!< AWD2_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD1_SLV_Pos (22UL) /*!< AWD1_SLV (Bit 22) */
+#define ADC2_CSR_AWD1_SLV_Msk (0x400000UL) /*!< AWD1_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD0_SLV_Pos (21UL) /*!< AWD0_SLV (Bit 21) */
+#define ADC2_CSR_AWD0_SLV_Msk (0x200000UL) /*!< AWD0_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_OVR_SLV_Pos (20UL) /*!< OVR_SLV (Bit 20) */
+#define ADC2_CSR_OVR_SLV_Msk (0x100000UL) /*!< OVR_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_JEOS_SLV_Pos (19UL) /*!< JEOS_SLV (Bit 19) */
+#define ADC2_CSR_JEOS_SLV_Msk (0x80000UL) /*!< JEOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_JEOC_SLV_Pos (18UL) /*!< JEOC_SLV (Bit 18) */
+#define ADC2_CSR_JEOC_SLV_Msk (0x40000UL) /*!< JEOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_EOS_SLV_Pos (17UL) /*!< EOS_SLV (Bit 17) */
+#define ADC2_CSR_EOS_SLV_Msk (0x20000UL) /*!< EOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_EOC_SLV_Pos (16UL) /*!< EOC_SLV (Bit 16) */
+#define ADC2_CSR_EOC_SLV_Msk (0x10000UL) /*!< EOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_EOSMP_MST_Pos (9UL) /*!< EOSMP_MST (Bit 9) */
+#define ADC2_CSR_EOSMP_MST_Msk (0x200UL) /*!< EOSMP_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_ADRDY_MST_Pos (8UL) /*!< ADRDY_MST (Bit 8) */
+#define ADC2_CSR_ADRDY_MST_Msk (0x100UL) /*!< ADRDY_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD2_MST_Pos (7UL) /*!< AWD2_MST (Bit 7) */
+#define ADC2_CSR_AWD2_MST_Msk (0x80UL) /*!< AWD2_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD1_MST_Pos (6UL) /*!< AWD1_MST (Bit 6) */
+#define ADC2_CSR_AWD1_MST_Msk (0x40UL) /*!< AWD1_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_AWD0_MST_Pos (5UL) /*!< AWD0_MST (Bit 5) */
+#define ADC2_CSR_AWD0_MST_Msk (0x20UL) /*!< AWD0_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_OVR_MST_Pos (4UL) /*!< OVR_MST (Bit 4) */
+#define ADC2_CSR_OVR_MST_Msk (0x10UL) /*!< OVR_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_JEOS_MST_Pos (3UL) /*!< JEOS_MST (Bit 3) */
+#define ADC2_CSR_JEOS_MST_Msk (0x8UL) /*!< JEOS_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_JEOC_MST_Pos (2UL) /*!< JEOC_MST (Bit 2) */
+#define ADC2_CSR_JEOC_MST_Msk (0x4UL) /*!< JEOC_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_EOS_MST_Pos (1UL) /*!< EOS_MST (Bit 1) */
+#define ADC2_CSR_EOS_MST_Msk (0x2UL) /*!< EOS_MST (Bitfield-Mask: 0x01) */
+#define ADC2_CSR_EOC_MST_Pos (0UL) /*!< EOC_MST (Bit 0) */
+#define ADC2_CSR_EOC_MST_Msk (0x1UL) /*!< EOC_MST (Bitfield-Mask: 0x01) */
+/* ========================================================== CDR ========================================================== */
+#define ADC2_CDR_RDATA_SLV_Pos (16UL) /*!< RDATA_SLV (Bit 16) */
+#define ADC2_CDR_RDATA_SLV_Msk (0xffff0000UL) /*!< RDATA_SLV (Bitfield-Mask: 0xffff) */
+#define ADC2_CDR_RDATA_MST_Pos (0UL) /*!< RDATA_MST (Bit 0) */
+#define ADC2_CDR_RDATA_MST_Msk (0xffffUL) /*!< RDATA_MST (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ ADC3 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR =========================================================== */
+#define ADC3_CR_ADCALDIF_Pos (7UL) /*!< ADCALDIF (Bit 7) */
+#define ADC3_CR_ADCALDIF_Msk (0x80UL) /*!< ADCALDIF (Bitfield-Mask: 0x01) */
+#define ADC3_CR_ADCAL_Pos (6UL) /*!< ADCAL (Bit 6) */
+#define ADC3_CR_ADCAL_Msk (0x40UL) /*!< ADCAL (Bitfield-Mask: 0x01) */
+#define ADC3_CR_JADSTP_Pos (5UL) /*!< JADSTP (Bit 5) */
+#define ADC3_CR_JADSTP_Msk (0x20UL) /*!< JADSTP (Bitfield-Mask: 0x01) */
+#define ADC3_CR_ADSTP_Pos (4UL) /*!< ADSTP (Bit 4) */
+#define ADC3_CR_ADSTP_Msk (0x10UL) /*!< ADSTP (Bitfield-Mask: 0x01) */
+#define ADC3_CR_JADSTART_Pos (3UL) /*!< JADSTART (Bit 3) */
+#define ADC3_CR_JADSTART_Msk (0x8UL) /*!< JADSTART (Bitfield-Mask: 0x01) */
+#define ADC3_CR_ADSTART_Pos (2UL) /*!< ADSTART (Bit 2) */
+#define ADC3_CR_ADSTART_Msk (0x4UL) /*!< ADSTART (Bitfield-Mask: 0x01) */
+#define ADC3_CR_ADDIS_Pos (1UL) /*!< ADDIS (Bit 1) */
+#define ADC3_CR_ADDIS_Msk (0x2UL) /*!< ADDIS (Bitfield-Mask: 0x01) */
+#define ADC3_CR_ADEN_Pos (0UL) /*!< ADEN (Bit 0) */
+#define ADC3_CR_ADEN_Msk (0x1UL) /*!< ADEN (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR0 ========================================================= */
+#define ADC3_CFGR0_OVSCAL_Pos (28UL) /*!< OVSCAL (Bit 28) */
+#define ADC3_CFGR0_OVSCAL_Msk (0x70000000UL) /*!< OVSCAL (Bitfield-Mask: 0x07) */
+#define ADC3_CFGR0_CONT_Pos (23UL) /*!< CONT (Bit 23) */
+#define ADC3_CFGR0_CONT_Msk (0x800000UL) /*!< CONT (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_JAUTO_Pos (22UL) /*!< JAUTO (Bit 22) */
+#define ADC3_CFGR0_JAUTO_Msk (0x400000UL) /*!< JAUTO (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_JDISCEN_Pos (20UL) /*!< JDISCEN (Bit 20) */
+#define ADC3_CFGR0_JDISCEN_Msk (0x100000UL) /*!< JDISCEN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_DISCNUM_Pos (17UL) /*!< DISCNUM (Bit 17) */
+#define ADC3_CFGR0_DISCNUM_Msk (0xe0000UL) /*!< DISCNUM (Bitfield-Mask: 0x07) */
+#define ADC3_CFGR0_DISCEN_Pos (16UL) /*!< DISCEN (Bit 16) */
+#define ADC3_CFGR0_DISCEN_Msk (0x10000UL) /*!< DISCEN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_OVRMOD_Pos (15UL) /*!< OVRMOD (Bit 15) */
+#define ADC3_CFGR0_OVRMOD_Msk (0x8000UL) /*!< OVRMOD (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_SDMAEN_Pos (14UL) /*!< SDMAEN (Bit 14) */
+#define ADC3_CFGR0_SDMAEN_Msk (0x4000UL) /*!< SDMAEN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_TROVS_Pos (12UL) /*!< TROVS (Bit 12) */
+#define ADC3_CFGR0_TROVS_Msk (0x1000UL) /*!< TROVS (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_OVSS_Pos (8UL) /*!< OVSS (Bit 8) */
+#define ADC3_CFGR0_OVSS_Msk (0xf00UL) /*!< OVSS (Bitfield-Mask: 0x0f) */
+#define ADC3_CFGR0_ROVSM_Pos (7UL) /*!< ROVSM (Bit 7) */
+#define ADC3_CFGR0_ROVSM_Msk (0x80UL) /*!< ROVSM (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_OVSR_Pos (4UL) /*!< OVSR (Bit 4) */
+#define ADC3_CFGR0_OVSR_Msk (0x70UL) /*!< OVSR (Bitfield-Mask: 0x07) */
+#define ADC3_CFGR0_JOVSE_Pos (1UL) /*!< JOVSE (Bit 1) */
+#define ADC3_CFGR0_JOVSE_Msk (0x2UL) /*!< JOVSE (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR0_ROVSE_Pos (0UL) /*!< ROVSE (Bit 0) */
+#define ADC3_CFGR0_ROVSE_Msk (0x1UL) /*!< ROVSE (Bitfield-Mask: 0x01) */
+/* ========================================================= CFGR1 ========================================================= */
+#define ADC3_CFGR1_JAWD2EN_Pos (14UL) /*!< JAWD2EN (Bit 14) */
+#define ADC3_CFGR1_JAWD2EN_Msk (0x4000UL) /*!< JAWD2EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_JAWD1EN_Pos (13UL) /*!< JAWD1EN (Bit 13) */
+#define ADC3_CFGR1_JAWD1EN_Msk (0x2000UL) /*!< JAWD1EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_JAWD0EN_Pos (12UL) /*!< JAWD0EN (Bit 12) */
+#define ADC3_CFGR1_JAWD0EN_Msk (0x1000UL) /*!< JAWD0EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_AWD2EN_Pos (10UL) /*!< AWD2EN (Bit 10) */
+#define ADC3_CFGR1_AWD2EN_Msk (0x400UL) /*!< AWD2EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_AWD1EN_Pos (9UL) /*!< AWD1EN (Bit 9) */
+#define ADC3_CFGR1_AWD1EN_Msk (0x200UL) /*!< AWD1EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_AWD0EN_Pos (8UL) /*!< AWD0EN (Bit 8) */
+#define ADC3_CFGR1_AWD0EN_Msk (0x100UL) /*!< AWD0EN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_ISEL_Pos (4UL) /*!< ISEL (Bit 4) */
+#define ADC3_CFGR1_ISEL_Msk (0x30UL) /*!< ISEL (Bitfield-Mask: 0x03) */
+#define ADC3_CFGR1_CHEN_Pos (3UL) /*!< CHEN (Bit 3) */
+#define ADC3_CFGR1_CHEN_Msk (0x8UL) /*!< CHEN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_REFEN_Pos (1UL) /*!< REFEN (Bit 1) */
+#define ADC3_CFGR1_REFEN_Msk (0x2UL) /*!< REFEN (Bitfield-Mask: 0x01) */
+#define ADC3_CFGR1_BIASEN_Pos (0UL) /*!< BIASEN (Bit 0) */
+#define ADC3_CFGR1_BIASEN_Msk (0x1UL) /*!< BIASEN (Bitfield-Mask: 0x01) */
+/* ========================================================== ISR ========================================================== */
+#define ADC3_ISR_EOSMP_Pos (9UL) /*!< EOSMP (Bit 9) */
+#define ADC3_ISR_EOSMP_Msk (0x200UL) /*!< EOSMP (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_ADRDY_Pos (8UL) /*!< ADRDY (Bit 8) */
+#define ADC3_ISR_ADRDY_Msk (0x100UL) /*!< ADRDY (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_AWD2_Pos (7UL) /*!< AWD2 (Bit 7) */
+#define ADC3_ISR_AWD2_Msk (0x80UL) /*!< AWD2 (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_AWD1_Pos (6UL) /*!< AWD1 (Bit 6) */
+#define ADC3_ISR_AWD1_Msk (0x40UL) /*!< AWD1 (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_AWD0_Pos (5UL) /*!< AWD0 (Bit 5) */
+#define ADC3_ISR_AWD0_Msk (0x20UL) /*!< AWD0 (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_OVR_Pos (4UL) /*!< OVR (Bit 4) */
+#define ADC3_ISR_OVR_Msk (0x10UL) /*!< OVR (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_JEOS_Pos (3UL) /*!< JEOS (Bit 3) */
+#define ADC3_ISR_JEOS_Msk (0x8UL) /*!< JEOS (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_JEOC_Pos (2UL) /*!< JEOC (Bit 2) */
+#define ADC3_ISR_JEOC_Msk (0x4UL) /*!< JEOC (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_EOS_Pos (1UL) /*!< EOS (Bit 1) */
+#define ADC3_ISR_EOS_Msk (0x2UL) /*!< EOS (Bitfield-Mask: 0x01) */
+#define ADC3_ISR_EOC_Pos (0UL) /*!< EOC (Bit 0) */
+#define ADC3_ISR_EOC_Msk (0x1UL) /*!< EOC (Bitfield-Mask: 0x01) */
+/* ========================================================== IER ========================================================== */
+#define ADC3_IER_EOSMPIE_Pos (9UL) /*!< EOSMPIE (Bit 9) */
+#define ADC3_IER_EOSMPIE_Msk (0x200UL) /*!< EOSMPIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_ADRDYIE_Pos (8UL) /*!< ADRDYIE (Bit 8) */
+#define ADC3_IER_ADRDYIE_Msk (0x100UL) /*!< ADRDYIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_AWD2IE_Pos (7UL) /*!< AWD2IE (Bit 7) */
+#define ADC3_IER_AWD2IE_Msk (0x80UL) /*!< AWD2IE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_AWD1IE_Pos (6UL) /*!< AWD1IE (Bit 6) */
+#define ADC3_IER_AWD1IE_Msk (0x40UL) /*!< AWD1IE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_AWD0IE_Pos (5UL) /*!< AWD0IE (Bit 5) */
+#define ADC3_IER_AWD0IE_Msk (0x20UL) /*!< AWD0IE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_OVRIE_Pos (4UL) /*!< OVRIE (Bit 4) */
+#define ADC3_IER_OVRIE_Msk (0x10UL) /*!< OVRIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_JEOSIE_Pos (3UL) /*!< JEOSIE (Bit 3) */
+#define ADC3_IER_JEOSIE_Msk (0x8UL) /*!< JEOSIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_JEOCIE_Pos (2UL) /*!< JEOCIE (Bit 2) */
+#define ADC3_IER_JEOCIE_Msk (0x4UL) /*!< JEOCIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_EOSIE_Pos (1UL) /*!< EOSIE (Bit 1) */
+#define ADC3_IER_EOSIE_Msk (0x2UL) /*!< EOSIE (Bitfield-Mask: 0x01) */
+#define ADC3_IER_EOCIE_Pos (0UL) /*!< EOCIE (Bit 0) */
+#define ADC3_IER_EOCIE_Msk (0x1UL) /*!< EOCIE (Bitfield-Mask: 0x01) */
+/* ======================================================== SIGSEL ========================================================= */
+#define ADC3_SIGSEL_SIGSEL_Pos (0UL) /*!< SIGSEL (Bit 0) */
+#define ADC3_SIGSEL_SIGSEL_Msk (0xfffffUL) /*!< SIGSEL (Bitfield-Mask: 0xfffff) */
+/* ========================================================= SMPR0 ========================================================= */
+#define ADC3_SMPR0_SMP7_Pos (28UL) /*!< SMP7 (Bit 28) */
+#define ADC3_SMPR0_SMP7_Msk (0x70000000UL) /*!< SMP7 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP6_Pos (24UL) /*!< SMP6 (Bit 24) */
+#define ADC3_SMPR0_SMP6_Msk (0x7000000UL) /*!< SMP6 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP5_Pos (20UL) /*!< SMP5 (Bit 20) */
+#define ADC3_SMPR0_SMP5_Msk (0x700000UL) /*!< SMP5 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP4_Pos (16UL) /*!< SMP4 (Bit 16) */
+#define ADC3_SMPR0_SMP4_Msk (0x70000UL) /*!< SMP4 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP3_Pos (12UL) /*!< SMP3 (Bit 12) */
+#define ADC3_SMPR0_SMP3_Msk (0x7000UL) /*!< SMP3 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP2_Pos (8UL) /*!< SMP2 (Bit 8) */
+#define ADC3_SMPR0_SMP2_Msk (0x700UL) /*!< SMP2 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP1_Pos (4UL) /*!< SMP1 (Bit 4) */
+#define ADC3_SMPR0_SMP1_Msk (0x70UL) /*!< SMP1 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR0_SMP0_Pos (0UL) /*!< SMP0 (Bit 0) */
+#define ADC3_SMPR0_SMP0_Msk (0x7UL) /*!< SMP0 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR1 ========================================================= */
+#define ADC3_SMPR1_SMP15_Pos (28UL) /*!< SMP15 (Bit 28) */
+#define ADC3_SMPR1_SMP15_Msk (0x70000000UL) /*!< SMP15 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP14_Pos (24UL) /*!< SMP14 (Bit 24) */
+#define ADC3_SMPR1_SMP14_Msk (0x7000000UL) /*!< SMP14 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP13_Pos (20UL) /*!< SMP13 (Bit 20) */
+#define ADC3_SMPR1_SMP13_Msk (0x700000UL) /*!< SMP13 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP12_Pos (16UL) /*!< SMP12 (Bit 16) */
+#define ADC3_SMPR1_SMP12_Msk (0x70000UL) /*!< SMP12 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP11_Pos (12UL) /*!< SMP11 (Bit 12) */
+#define ADC3_SMPR1_SMP11_Msk (0x7000UL) /*!< SMP11 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP10_Pos (8UL) /*!< SMP10 (Bit 8) */
+#define ADC3_SMPR1_SMP10_Msk (0x700UL) /*!< SMP10 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP9_Pos (4UL) /*!< SMP9 (Bit 4) */
+#define ADC3_SMPR1_SMP9_Msk (0x70UL) /*!< SMP9 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR1_SMP8_Pos (0UL) /*!< SMP8 (Bit 0) */
+#define ADC3_SMPR1_SMP8_Msk (0x7UL) /*!< SMP8 (Bitfield-Mask: 0x07) */
+/* ========================================================= SMPR2 ========================================================= */
+#define ADC3_SMPR2_SMP19_Pos (12UL) /*!< SMP19 (Bit 12) */
+#define ADC3_SMPR2_SMP19_Msk (0x7000UL) /*!< SMP19 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR2_SMP18_Pos (8UL) /*!< SMP18 (Bit 8) */
+#define ADC3_SMPR2_SMP18_Msk (0x700UL) /*!< SMP18 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR2_SMP17_Pos (4UL) /*!< SMP17 (Bit 4) */
+#define ADC3_SMPR2_SMP17_Msk (0x70UL) /*!< SMP17 (Bitfield-Mask: 0x07) */
+#define ADC3_SMPR2_SMP16_Pos (0UL) /*!< SMP16 (Bit 0) */
+#define ADC3_SMPR2_SMP16_Msk (0x7UL) /*!< SMP16 (Bitfield-Mask: 0x07) */
+/* ========================================================= CALR0 ========================================================= */
+#define ADC3_CALR0_SAT7_Pos (31UL) /*!< SAT7 (Bit 31) */
+#define ADC3_CALR0_SAT7_Msk (0x80000000UL) /*!< SAT7 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL7_Pos (28UL) /*!< CAL7 (Bit 28) */
+#define ADC3_CALR0_CAL7_Msk (0x30000000UL) /*!< CAL7 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT6_Pos (27UL) /*!< SAT6 (Bit 27) */
+#define ADC3_CALR0_SAT6_Msk (0x8000000UL) /*!< SAT6 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL6_Pos (24UL) /*!< CAL6 (Bit 24) */
+#define ADC3_CALR0_CAL6_Msk (0x3000000UL) /*!< CAL6 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT5_Pos (23UL) /*!< SAT5 (Bit 23) */
+#define ADC3_CALR0_SAT5_Msk (0x800000UL) /*!< SAT5 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL5_Pos (20UL) /*!< CAL5 (Bit 20) */
+#define ADC3_CALR0_CAL5_Msk (0x300000UL) /*!< CAL5 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT4_Pos (19UL) /*!< SAT4 (Bit 19) */
+#define ADC3_CALR0_SAT4_Msk (0x80000UL) /*!< SAT4 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL4_Pos (16UL) /*!< CAL4 (Bit 16) */
+#define ADC3_CALR0_CAL4_Msk (0x30000UL) /*!< CAL4 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT3_Pos (15UL) /*!< SAT3 (Bit 15) */
+#define ADC3_CALR0_SAT3_Msk (0x8000UL) /*!< SAT3 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL3_Pos (12UL) /*!< CAL3 (Bit 12) */
+#define ADC3_CALR0_CAL3_Msk (0x3000UL) /*!< CAL3 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT2_Pos (11UL) /*!< SAT2 (Bit 11) */
+#define ADC3_CALR0_SAT2_Msk (0x800UL) /*!< SAT2 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL2_Pos (8UL) /*!< CAL2 (Bit 8) */
+#define ADC3_CALR0_CAL2_Msk (0x300UL) /*!< CAL2 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT1_Pos (7UL) /*!< SAT1 (Bit 7) */
+#define ADC3_CALR0_SAT1_Msk (0x80UL) /*!< SAT1 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL1_Pos (4UL) /*!< CAL1 (Bit 4) */
+#define ADC3_CALR0_CAL1_Msk (0x30UL) /*!< CAL1 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR0_SAT0_Pos (3UL) /*!< SAT0 (Bit 3) */
+#define ADC3_CALR0_SAT0_Msk (0x8UL) /*!< SAT0 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR0_CAL0_Pos (0UL) /*!< CAL0 (Bit 0) */
+#define ADC3_CALR0_CAL0_Msk (0x3UL) /*!< CAL0 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR1 ========================================================= */
+#define ADC3_CALR1_SAT15_Pos (31UL) /*!< SAT15 (Bit 31) */
+#define ADC3_CALR1_SAT15_Msk (0x80000000UL) /*!< SAT15 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL15_Pos (28UL) /*!< CAL15 (Bit 28) */
+#define ADC3_CALR1_CAL15_Msk (0x30000000UL) /*!< CAL15 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT14_Pos (27UL) /*!< SAT14 (Bit 27) */
+#define ADC3_CALR1_SAT14_Msk (0x8000000UL) /*!< SAT14 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL14_Pos (24UL) /*!< CAL14 (Bit 24) */
+#define ADC3_CALR1_CAL14_Msk (0x3000000UL) /*!< CAL14 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT13_Pos (23UL) /*!< SAT13 (Bit 23) */
+#define ADC3_CALR1_SAT13_Msk (0x800000UL) /*!< SAT13 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL13_Pos (20UL) /*!< CAL13 (Bit 20) */
+#define ADC3_CALR1_CAL13_Msk (0x300000UL) /*!< CAL13 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT12_Pos (19UL) /*!< SAT12 (Bit 19) */
+#define ADC3_CALR1_SAT12_Msk (0x80000UL) /*!< SAT12 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL12_Pos (16UL) /*!< CAL12 (Bit 16) */
+#define ADC3_CALR1_CAL12_Msk (0x30000UL) /*!< CAL12 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT11_Pos (15UL) /*!< SAT11 (Bit 15) */
+#define ADC3_CALR1_SAT11_Msk (0x8000UL) /*!< SAT11 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL11_Pos (12UL) /*!< CAL11 (Bit 12) */
+#define ADC3_CALR1_CAL11_Msk (0x3000UL) /*!< CAL11 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT10_Pos (11UL) /*!< SAT10 (Bit 11) */
+#define ADC3_CALR1_SAT10_Msk (0x800UL) /*!< SAT10 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL10_Pos (8UL) /*!< CAL10 (Bit 8) */
+#define ADC3_CALR1_CAL10_Msk (0x300UL) /*!< CAL10 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT9_Pos (7UL) /*!< SAT9 (Bit 7) */
+#define ADC3_CALR1_SAT9_Msk (0x80UL) /*!< SAT9 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL9_Pos (4UL) /*!< CAL9 (Bit 4) */
+#define ADC3_CALR1_CAL9_Msk (0x30UL) /*!< CAL9 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR1_SAT8_Pos (3UL) /*!< SAT8 (Bit 3) */
+#define ADC3_CALR1_SAT8_Msk (0x8UL) /*!< SAT8 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR1_CAL8_Pos (0UL) /*!< CAL8 (Bit 0) */
+#define ADC3_CALR1_CAL8_Msk (0x3UL) /*!< CAL8 (Bitfield-Mask: 0x03) */
+/* ========================================================= CALR2 ========================================================= */
+#define ADC3_CALR2_SAT19_Pos (15UL) /*!< SAT19 (Bit 15) */
+#define ADC3_CALR2_SAT19_Msk (0x8000UL) /*!< SAT19 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR2_CAL19_Pos (12UL) /*!< CAL19 (Bit 12) */
+#define ADC3_CALR2_CAL19_Msk (0x3000UL) /*!< CAL19 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR2_SAT18_Pos (11UL) /*!< SAT18 (Bit 11) */
+#define ADC3_CALR2_SAT18_Msk (0x800UL) /*!< SAT18 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR2_CAL18_Pos (8UL) /*!< CAL18 (Bit 8) */
+#define ADC3_CALR2_CAL18_Msk (0x300UL) /*!< CAL18 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR2_SAT17_Pos (7UL) /*!< SAT17 (Bit 7) */
+#define ADC3_CALR2_SAT17_Msk (0x80UL) /*!< SAT17 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR2_CAL17_Pos (4UL) /*!< CAL17 (Bit 4) */
+#define ADC3_CALR2_CAL17_Msk (0x30UL) /*!< CAL17 (Bitfield-Mask: 0x03) */
+#define ADC3_CALR2_SAT16_Pos (3UL) /*!< SAT16 (Bit 3) */
+#define ADC3_CALR2_SAT16_Msk (0x8UL) /*!< SAT16 (Bitfield-Mask: 0x01) */
+#define ADC3_CALR2_CAL16_Pos (0UL) /*!< CAL16 (Bit 0) */
+#define ADC3_CALR2_CAL16_Msk (0x3UL) /*!< CAL16 (Bitfield-Mask: 0x03) */
+/* ========================================================= SQR0 ========================================================== */
+#define ADC3_SQR0_SQ5_Pos (24UL) /*!< SQ5 (Bit 24) */
+#define ADC3_SQR0_SQ5_Msk (0x1f000000UL) /*!< SQ5 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR0_SQ4_Pos (18UL) /*!< SQ4 (Bit 18) */
+#define ADC3_SQR0_SQ4_Msk (0x7c0000UL) /*!< SQ4 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR0_SQ3_Pos (12UL) /*!< SQ3 (Bit 12) */
+#define ADC3_SQR0_SQ3_Msk (0x1f000UL) /*!< SQ3 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR0_SQ2_Pos (6UL) /*!< SQ2 (Bit 6) */
+#define ADC3_SQR0_SQ2_Msk (0x7c0UL) /*!< SQ2 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR0_SQ1_Pos (0UL) /*!< SQ1 (Bit 0) */
+#define ADC3_SQR0_SQ1_Msk (0x1fUL) /*!< SQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR1 ========================================================== */
+#define ADC3_SQR1_SQ10_Pos (24UL) /*!< SQ10 (Bit 24) */
+#define ADC3_SQR1_SQ10_Msk (0x1f000000UL) /*!< SQ10 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR1_SQ9_Pos (18UL) /*!< SQ9 (Bit 18) */
+#define ADC3_SQR1_SQ9_Msk (0x7c0000UL) /*!< SQ9 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR1_SQ8_Pos (12UL) /*!< SQ8 (Bit 12) */
+#define ADC3_SQR1_SQ8_Msk (0x1f000UL) /*!< SQ8 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR1_SQ7_Pos (6UL) /*!< SQ7 (Bit 6) */
+#define ADC3_SQR1_SQ7_Msk (0x7c0UL) /*!< SQ7 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR1_SQ6_Pos (0UL) /*!< SQ6 (Bit 0) */
+#define ADC3_SQR1_SQ6_Msk (0x1fUL) /*!< SQ6 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR2 ========================================================== */
+#define ADC3_SQR2_SQ15_Pos (24UL) /*!< SQ15 (Bit 24) */
+#define ADC3_SQR2_SQ15_Msk (0x1f000000UL) /*!< SQ15 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR2_SQ14_Pos (18UL) /*!< SQ14 (Bit 18) */
+#define ADC3_SQR2_SQ14_Msk (0x7c0000UL) /*!< SQ14 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR2_SQ13_Pos (12UL) /*!< SQ13 (Bit 12) */
+#define ADC3_SQR2_SQ13_Msk (0x1f000UL) /*!< SQ13 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR2_SQ12_Pos (6UL) /*!< SQ12 (Bit 6) */
+#define ADC3_SQR2_SQ12_Msk (0x7c0UL) /*!< SQ12 (Bitfield-Mask: 0x1f) */
+#define ADC3_SQR2_SQ11_Pos (0UL) /*!< SQ11 (Bit 0) */
+#define ADC3_SQR2_SQ11_Msk (0x1fUL) /*!< SQ11 (Bitfield-Mask: 0x1f) */
+/* ========================================================= SQR3 ========================================================== */
+#define ADC3_SQR3_SQ16_Pos (0UL) /*!< SQ16 (Bit 0) */
+#define ADC3_SQR3_SQ16_Msk (0x1fUL) /*!< SQ16 (Bitfield-Mask: 0x1f) */
+/* ========================================================== LR =========================================================== */
+#define ADC3_LR_LEN_Pos (8UL) /*!< LEN (Bit 8) */
+#define ADC3_LR_LEN_Msk (0xf00UL) /*!< LEN (Bitfield-Mask: 0x0f) */
+#define ADC3_LR_EXTEN_Pos (6UL) /*!< EXTEN (Bit 6) */
+#define ADC3_LR_EXTEN_Msk (0xc0UL) /*!< EXTEN (Bitfield-Mask: 0x03) */
+#define ADC3_LR_EXTSEL_Pos (0UL) /*!< EXTSEL (Bit 0) */
+#define ADC3_LR_EXTSEL_Msk (0x1fUL) /*!< EXTSEL (Bitfield-Mask: 0x1f) */
+/* ========================================================== DR =========================================================== */
+#define ADC3_DR_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */
+#define ADC3_DR_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MAXDR ========================================================= */
+#define ADC3_MAXDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC3_MAXDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= MINDR ========================================================= */
+#define ADC3_MINDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC3_MINDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JSQR ========================================================== */
+#define ADC3_JSQR_JSQ4_Pos (18UL) /*!< JSQ4 (Bit 18) */
+#define ADC3_JSQR_JSQ4_Msk (0x7c0000UL) /*!< JSQ4 (Bitfield-Mask: 0x1f) */
+#define ADC3_JSQR_JSQ3_Pos (12UL) /*!< JSQ3 (Bit 12) */
+#define ADC3_JSQR_JSQ3_Msk (0x1f000UL) /*!< JSQ3 (Bitfield-Mask: 0x1f) */
+#define ADC3_JSQR_JSQ2_Pos (6UL) /*!< JSQ2 (Bit 6) */
+#define ADC3_JSQR_JSQ2_Msk (0x7c0UL) /*!< JSQ2 (Bitfield-Mask: 0x1f) */
+#define ADC3_JSQR_JSQ1_Pos (0UL) /*!< JSQ1 (Bit 0) */
+#define ADC3_JSQR_JSQ1_Msk (0x1fUL) /*!< JSQ1 (Bitfield-Mask: 0x1f) */
+/* ========================================================== JLR ========================================================== */
+#define ADC3_JLR_JLEN_Pos (8UL) /*!< JLEN (Bit 8) */
+#define ADC3_JLR_JLEN_Msk (0x300UL) /*!< JLEN (Bitfield-Mask: 0x03) */
+#define ADC3_JLR_JEXTEN_Pos (6UL) /*!< JEXTEN (Bit 6) */
+#define ADC3_JLR_JEXTEN_Msk (0xc0UL) /*!< JEXTEN (Bitfield-Mask: 0x03) */
+#define ADC3_JLR_JEXTSEL_Pos (0UL) /*!< JEXTSEL (Bit 0) */
+#define ADC3_JLR_JEXTSEL_Msk (0x1fUL) /*!< JEXTSEL (Bitfield-Mask: 0x1f) */
+/* ======================================================== MAXJDR ========================================================= */
+#define ADC3_MAXJDR_MAXDATA_Pos (0UL) /*!< MAXDATA (Bit 0) */
+#define ADC3_MAXJDR_MAXDATA_Msk (0xffffUL) /*!< MAXDATA (Bitfield-Mask: 0xffff) */
+/* ======================================================== MINJDR ========================================================= */
+#define ADC3_MINJDR_MINDATA_Pos (0UL) /*!< MINDATA (Bit 0) */
+#define ADC3_MINJDR_MINDATA_Msk (0xffffUL) /*!< MINDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR0 ========================================================== */
+#define ADC3_JDR0_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC3_JDR0_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR1 ========================================================== */
+#define ADC3_JDR1_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC3_JDR1_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR2 ========================================================== */
+#define ADC3_JDR2_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC3_JDR2_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= JDR3 ========================================================== */
+#define ADC3_JDR3_JDATA_Pos (0UL) /*!< JDATA (Bit 0) */
+#define ADC3_JDR3_JDATA_Msk (0xffffUL) /*!< JDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR0 ========================================================== */
+#define ADC3_TR0_HT0_Pos (16UL) /*!< HT0 (Bit 16) */
+#define ADC3_TR0_HT0_Msk (0xffff0000UL) /*!< HT0 (Bitfield-Mask: 0xffff) */
+#define ADC3_TR0_LT0_Pos (0UL) /*!< LT0 (Bit 0) */
+#define ADC3_TR0_LT0_Msk (0xffffUL) /*!< LT0 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR1 ========================================================== */
+#define ADC3_TR1_HT1_Pos (16UL) /*!< HT1 (Bit 16) */
+#define ADC3_TR1_HT1_Msk (0xffff0000UL) /*!< HT1 (Bitfield-Mask: 0xffff) */
+#define ADC3_TR1_LT1_Pos (0UL) /*!< LT1 (Bit 0) */
+#define ADC3_TR1_LT1_Msk (0xffffUL) /*!< LT1 (Bitfield-Mask: 0xffff) */
+/* ========================================================== TR2 ========================================================== */
+#define ADC3_TR2_HT2_Pos (16UL) /*!< HT2 (Bit 16) */
+#define ADC3_TR2_HT2_Msk (0xffff0000UL) /*!< HT2 (Bitfield-Mask: 0xffff) */
+#define ADC3_TR2_LT2_Pos (0UL) /*!< LT2 (Bit 0) */
+#define ADC3_TR2_LT2_Msk (0xffffUL) /*!< LT2 (Bitfield-Mask: 0xffff) */
+/* ======================================================== AWD0CR ========================================================= */
+#define ADC3_AWD0CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC3_AWD0CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC3_AWD0CR_AW0CH_Pos (0UL) /*!< AW0CH (Bit 0) */
+#define ADC3_AWD0CR_AW0CH_Msk (0xfffffUL) /*!< AW0CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD1CR ========================================================= */
+#define ADC3_AWD1CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC3_AWD1CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC3_AWD1CR_AW1CH_Pos (0UL) /*!< AW1CH (Bit 0) */
+#define ADC3_AWD1CR_AW1CH_Msk (0xfffffUL) /*!< AW1CH (Bitfield-Mask: 0xfffff) */
+/* ======================================================== AWD2CR ========================================================= */
+#define ADC3_AWD2CR_AWDFILT_Pos (24UL) /*!< AWDFILT (Bit 24) */
+#define ADC3_AWD2CR_AWDFILT_Msk (0xf000000UL) /*!< AWDFILT (Bitfield-Mask: 0x0f) */
+#define ADC3_AWD2CR_AW2CH_Pos (0UL) /*!< AW2CH (Bit 0) */
+#define ADC3_AWD2CR_AW2CH_Msk (0xfffffUL) /*!< AW2CH (Bitfield-Mask: 0xfffff) */
+/* ========================================================= OFR0 ========================================================== */
+#define ADC3_OFR0_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC3_OFR0_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR1 ========================================================== */
+#define ADC3_OFR1_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC3_OFR1_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR2 ========================================================== */
+#define ADC3_OFR2_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC3_OFR2_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= OFR3 ========================================================== */
+#define ADC3_OFR3_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */
+#define ADC3_OFR3_OFFSET_Msk (0xffffUL) /*!< OFFSET (Bitfield-Mask: 0xffff) */
+/* ========================================================= GCR0 ========================================================== */
+#define ADC3_GCR0_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC3_GCR0_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR1 ========================================================== */
+#define ADC3_GCR1_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC3_GCR1_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR2 ========================================================== */
+#define ADC3_GCR2_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC3_GCR2_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= GCR3 ========================================================== */
+#define ADC3_GCR3_COEFF_Pos (0UL) /*!< COEFF (Bit 0) */
+#define ADC3_GCR3_COEFF_Msk (0x7fffUL) /*!< COEFF (Bitfield-Mask: 0x7fff) */
+/* ========================================================= DISR ========================================================== */
+#define ADC3_DISR_DON19_Pos (19UL) /*!< DON19 (Bit 19) */
+#define ADC3_DISR_DON19_Msk (0x80000UL) /*!< DON19 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON18_Pos (18UL) /*!< DON18 (Bit 18) */
+#define ADC3_DISR_DON18_Msk (0x40000UL) /*!< DON18 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON17_Pos (17UL) /*!< DON17 (Bit 17) */
+#define ADC3_DISR_DON17_Msk (0x20000UL) /*!< DON17 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON16_Pos (16UL) /*!< DON16 (Bit 16) */
+#define ADC3_DISR_DON16_Msk (0x10000UL) /*!< DON16 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON15_Pos (15UL) /*!< DON15 (Bit 15) */
+#define ADC3_DISR_DON15_Msk (0x8000UL) /*!< DON15 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON14_Pos (14UL) /*!< DON14 (Bit 14) */
+#define ADC3_DISR_DON14_Msk (0x4000UL) /*!< DON14 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON13_Pos (13UL) /*!< DON13 (Bit 13) */
+#define ADC3_DISR_DON13_Msk (0x2000UL) /*!< DON13 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON12_Pos (12UL) /*!< DON12 (Bit 12) */
+#define ADC3_DISR_DON12_Msk (0x1000UL) /*!< DON12 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON11_Pos (11UL) /*!< DON11 (Bit 11) */
+#define ADC3_DISR_DON11_Msk (0x800UL) /*!< DON11 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON10_Pos (10UL) /*!< DON10 (Bit 10) */
+#define ADC3_DISR_DON10_Msk (0x400UL) /*!< DON10 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON9_Pos (9UL) /*!< DON9 (Bit 9) */
+#define ADC3_DISR_DON9_Msk (0x200UL) /*!< DON9 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON8_Pos (8UL) /*!< DON8 (Bit 8) */
+#define ADC3_DISR_DON8_Msk (0x100UL) /*!< DON8 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON7_Pos (7UL) /*!< DON7 (Bit 7) */
+#define ADC3_DISR_DON7_Msk (0x80UL) /*!< DON7 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON6_Pos (6UL) /*!< DON6 (Bit 6) */
+#define ADC3_DISR_DON6_Msk (0x40UL) /*!< DON6 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON5_Pos (5UL) /*!< DON5 (Bit 5) */
+#define ADC3_DISR_DON5_Msk (0x20UL) /*!< DON5 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON4_Pos (4UL) /*!< DON4 (Bit 4) */
+#define ADC3_DISR_DON4_Msk (0x10UL) /*!< DON4 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON3_Pos (3UL) /*!< DON3 (Bit 3) */
+#define ADC3_DISR_DON3_Msk (0x8UL) /*!< DON3 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON2_Pos (2UL) /*!< DON2 (Bit 2) */
+#define ADC3_DISR_DON2_Msk (0x4UL) /*!< DON2 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON1_Pos (1UL) /*!< DON1 (Bit 1) */
+#define ADC3_DISR_DON1_Msk (0x2UL) /*!< DON1 (Bitfield-Mask: 0x01) */
+#define ADC3_DISR_DON0_Pos (0UL) /*!< DON0 (Bit 0) */
+#define ADC3_DISR_DON0_Msk (0x1UL) /*!< DON0 (Bitfield-Mask: 0x01) */
+/* ========================================================= DIER ========================================================== */
+#define ADC3_DIER_DONIE19_Pos (19UL) /*!< DONIE19 (Bit 19) */
+#define ADC3_DIER_DONIE19_Msk (0x80000UL) /*!< DONIE19 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE18_Pos (18UL) /*!< DONIE18 (Bit 18) */
+#define ADC3_DIER_DONIE18_Msk (0x40000UL) /*!< DONIE18 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE17_Pos (17UL) /*!< DONIE17 (Bit 17) */
+#define ADC3_DIER_DONIE17_Msk (0x20000UL) /*!< DONIE17 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE16_Pos (16UL) /*!< DONIE16 (Bit 16) */
+#define ADC3_DIER_DONIE16_Msk (0x10000UL) /*!< DONIE16 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE15_Pos (15UL) /*!< DONIE15 (Bit 15) */
+#define ADC3_DIER_DONIE15_Msk (0x8000UL) /*!< DONIE15 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE14_Pos (14UL) /*!< DONIE14 (Bit 14) */
+#define ADC3_DIER_DONIE14_Msk (0x4000UL) /*!< DONIE14 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE13_Pos (13UL) /*!< DONIE13 (Bit 13) */
+#define ADC3_DIER_DONIE13_Msk (0x2000UL) /*!< DONIE13 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE12_Pos (12UL) /*!< DONIE12 (Bit 12) */
+#define ADC3_DIER_DONIE12_Msk (0x1000UL) /*!< DONIE12 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE11_Pos (11UL) /*!< DONIE11 (Bit 11) */
+#define ADC3_DIER_DONIE11_Msk (0x800UL) /*!< DONIE11 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE10_Pos (10UL) /*!< DONIE10 (Bit 10) */
+#define ADC3_DIER_DONIE10_Msk (0x400UL) /*!< DONIE10 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE9_Pos (9UL) /*!< DONIE9 (Bit 9) */
+#define ADC3_DIER_DONIE9_Msk (0x200UL) /*!< DONIE9 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE8_Pos (8UL) /*!< DONIE8 (Bit 8) */
+#define ADC3_DIER_DONIE8_Msk (0x100UL) /*!< DONIE8 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE7_Pos (7UL) /*!< DONIE7 (Bit 7) */
+#define ADC3_DIER_DONIE7_Msk (0x80UL) /*!< DONIE7 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE6_Pos (6UL) /*!< DONIE6 (Bit 6) */
+#define ADC3_DIER_DONIE6_Msk (0x40UL) /*!< DONIE6 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE5_Pos (5UL) /*!< DONIE5 (Bit 5) */
+#define ADC3_DIER_DONIE5_Msk (0x20UL) /*!< DONIE5 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE4_Pos (4UL) /*!< DONIE4 (Bit 4) */
+#define ADC3_DIER_DONIE4_Msk (0x10UL) /*!< DONIE4 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE3_Pos (3UL) /*!< DONIE3 (Bit 3) */
+#define ADC3_DIER_DONIE3_Msk (0x8UL) /*!< DONIE3 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE2_Pos (2UL) /*!< DONIE2 (Bit 2) */
+#define ADC3_DIER_DONIE2_Msk (0x4UL) /*!< DONIE2 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE1_Pos (1UL) /*!< DONIE1 (Bit 1) */
+#define ADC3_DIER_DONIE1_Msk (0x2UL) /*!< DONIE1 (Bitfield-Mask: 0x01) */
+#define ADC3_DIER_DONIE0_Pos (0UL) /*!< DONIE0 (Bit 0) */
+#define ADC3_DIER_DONIE0_Msk (0x1UL) /*!< DONIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= CDR0 ========================================================== */
+#define ADC3_CDR0_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR0_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR1 ========================================================== */
+#define ADC3_CDR1_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR1_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR2 ========================================================== */
+#define ADC3_CDR2_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR2_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR3 ========================================================== */
+#define ADC3_CDR3_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR3_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR4 ========================================================== */
+#define ADC3_CDR4_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR4_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR5 ========================================================== */
+#define ADC3_CDR5_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR5_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR6 ========================================================== */
+#define ADC3_CDR6_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR6_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR7 ========================================================== */
+#define ADC3_CDR7_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR7_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR8 ========================================================== */
+#define ADC3_CDR8_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR8_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR9 ========================================================== */
+#define ADC3_CDR9_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR9_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR10 ========================================================= */
+#define ADC3_CDR10_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR10_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR11 ========================================================= */
+#define ADC3_CDR11_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR11_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR12 ========================================================= */
+#define ADC3_CDR12_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR12_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR13 ========================================================= */
+#define ADC3_CDR13_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR13_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR14 ========================================================= */
+#define ADC3_CDR14_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR14_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR15 ========================================================= */
+#define ADC3_CDR15_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR15_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR16 ========================================================= */
+#define ADC3_CDR16_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR16_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR17 ========================================================= */
+#define ADC3_CDR17_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR17_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR18 ========================================================= */
+#define ADC3_CDR18_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR18_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= CDR19 ========================================================= */
+#define ADC3_CDR19_CDATA_Pos (0UL) /*!< CDATA (Bit 0) */
+#define ADC3_CDR19_CDATA_Msk (0xffffUL) /*!< CDATA (Bitfield-Mask: 0xffff) */
+/* ========================================================= HISR ========================================================== */
+#define ADC3_HISR_HLF19_Pos (19UL) /*!< HLF19 (Bit 19) */
+#define ADC3_HISR_HLF19_Msk (0x80000UL) /*!< HLF19 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF18_Pos (18UL) /*!< HLF18 (Bit 18) */
+#define ADC3_HISR_HLF18_Msk (0x40000UL) /*!< HLF18 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF17_Pos (17UL) /*!< HLF17 (Bit 17) */
+#define ADC3_HISR_HLF17_Msk (0x20000UL) /*!< HLF17 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF16_Pos (16UL) /*!< HLF16 (Bit 16) */
+#define ADC3_HISR_HLF16_Msk (0x10000UL) /*!< HLF16 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF15_Pos (15UL) /*!< HLF15 (Bit 15) */
+#define ADC3_HISR_HLF15_Msk (0x8000UL) /*!< HLF15 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF14_Pos (14UL) /*!< HLF14 (Bit 14) */
+#define ADC3_HISR_HLF14_Msk (0x4000UL) /*!< HLF14 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF13_Pos (13UL) /*!< HLF13 (Bit 13) */
+#define ADC3_HISR_HLF13_Msk (0x2000UL) /*!< HLF13 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF12_Pos (12UL) /*!< HLF12 (Bit 12) */
+#define ADC3_HISR_HLF12_Msk (0x1000UL) /*!< HLF12 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF11_Pos (11UL) /*!< HLF11 (Bit 11) */
+#define ADC3_HISR_HLF11_Msk (0x800UL) /*!< HLF11 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF10_Pos (10UL) /*!< HLF10 (Bit 10) */
+#define ADC3_HISR_HLF10_Msk (0x400UL) /*!< HLF10 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF9_Pos (9UL) /*!< HLF9 (Bit 9) */
+#define ADC3_HISR_HLF9_Msk (0x200UL) /*!< HLF9 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF8_Pos (8UL) /*!< HLF8 (Bit 8) */
+#define ADC3_HISR_HLF8_Msk (0x100UL) /*!< HLF8 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF7_Pos (7UL) /*!< HLF7 (Bit 7) */
+#define ADC3_HISR_HLF7_Msk (0x80UL) /*!< HLF7 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF6_Pos (6UL) /*!< HLF6 (Bit 6) */
+#define ADC3_HISR_HLF6_Msk (0x40UL) /*!< HLF6 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF5_Pos (5UL) /*!< HLF5 (Bit 5) */
+#define ADC3_HISR_HLF5_Msk (0x20UL) /*!< HLF5 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF4_Pos (4UL) /*!< HLF4 (Bit 4) */
+#define ADC3_HISR_HLF4_Msk (0x10UL) /*!< HLF4 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF3_Pos (3UL) /*!< HLF3 (Bit 3) */
+#define ADC3_HISR_HLF3_Msk (0x8UL) /*!< HLF3 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF2_Pos (2UL) /*!< HLF2 (Bit 2) */
+#define ADC3_HISR_HLF2_Msk (0x4UL) /*!< HLF2 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF1_Pos (1UL) /*!< HLF1 (Bit 1) */
+#define ADC3_HISR_HLF1_Msk (0x2UL) /*!< HLF1 (Bitfield-Mask: 0x01) */
+#define ADC3_HISR_HLF0_Pos (0UL) /*!< HLF0 (Bit 0) */
+#define ADC3_HISR_HLF0_Msk (0x1UL) /*!< HLF0 (Bitfield-Mask: 0x01) */
+/* ========================================================= HIER ========================================================== */
+#define ADC3_HIER_HLFIE19_Pos (19UL) /*!< HLFIE19 (Bit 19) */
+#define ADC3_HIER_HLFIE19_Msk (0x80000UL) /*!< HLFIE19 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE18_Pos (18UL) /*!< HLFIE18 (Bit 18) */
+#define ADC3_HIER_HLFIE18_Msk (0x40000UL) /*!< HLFIE18 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE17_Pos (17UL) /*!< HLFIE17 (Bit 17) */
+#define ADC3_HIER_HLFIE17_Msk (0x20000UL) /*!< HLFIE17 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE16_Pos (16UL) /*!< HLFIE16 (Bit 16) */
+#define ADC3_HIER_HLFIE16_Msk (0x10000UL) /*!< HLFIE16 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE15_Pos (15UL) /*!< HLFIE15 (Bit 15) */
+#define ADC3_HIER_HLFIE15_Msk (0x8000UL) /*!< HLFIE15 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE14_Pos (14UL) /*!< HLFIE14 (Bit 14) */
+#define ADC3_HIER_HLFIE14_Msk (0x4000UL) /*!< HLFIE14 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE13_Pos (13UL) /*!< HLFIE13 (Bit 13) */
+#define ADC3_HIER_HLFIE13_Msk (0x2000UL) /*!< HLFIE13 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE12_Pos (12UL) /*!< HLFIE12 (Bit 12) */
+#define ADC3_HIER_HLFIE12_Msk (0x1000UL) /*!< HLFIE12 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE11_Pos (11UL) /*!< HLFIE11 (Bit 11) */
+#define ADC3_HIER_HLFIE11_Msk (0x800UL) /*!< HLFIE11 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE10_Pos (10UL) /*!< HLFIE10 (Bit 10) */
+#define ADC3_HIER_HLFIE10_Msk (0x400UL) /*!< HLFIE10 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE9_Pos (9UL) /*!< HLFIE9 (Bit 9) */
+#define ADC3_HIER_HLFIE9_Msk (0x200UL) /*!< HLFIE9 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE8_Pos (8UL) /*!< HLFIE8 (Bit 8) */
+#define ADC3_HIER_HLFIE8_Msk (0x100UL) /*!< HLFIE8 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE7_Pos (7UL) /*!< HLFIE7 (Bit 7) */
+#define ADC3_HIER_HLFIE7_Msk (0x80UL) /*!< HLFIE7 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE6_Pos (6UL) /*!< HLFIE6 (Bit 6) */
+#define ADC3_HIER_HLFIE6_Msk (0x40UL) /*!< HLFIE6 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE5_Pos (5UL) /*!< HLFIE5 (Bit 5) */
+#define ADC3_HIER_HLFIE5_Msk (0x20UL) /*!< HLFIE5 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE4_Pos (4UL) /*!< HLFIE4 (Bit 4) */
+#define ADC3_HIER_HLFIE4_Msk (0x10UL) /*!< HLFIE4 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE3_Pos (3UL) /*!< HLFIE3 (Bit 3) */
+#define ADC3_HIER_HLFIE3_Msk (0x8UL) /*!< HLFIE3 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE2_Pos (2UL) /*!< HLFIE2 (Bit 2) */
+#define ADC3_HIER_HLFIE2_Msk (0x4UL) /*!< HLFIE2 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE1_Pos (1UL) /*!< HLFIE1 (Bit 1) */
+#define ADC3_HIER_HLFIE1_Msk (0x2UL) /*!< HLFIE1 (Bitfield-Mask: 0x01) */
+#define ADC3_HIER_HLFIE0_Pos (0UL) /*!< HLFIE0 (Bit 0) */
+#define ADC3_HIER_HLFIE0_Msk (0x1UL) /*!< HLFIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FISR ========================================================== */
+#define ADC3_FISR_FUL19_Pos (19UL) /*!< FUL19 (Bit 19) */
+#define ADC3_FISR_FUL19_Msk (0x80000UL) /*!< FUL19 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL18_Pos (18UL) /*!< FUL18 (Bit 18) */
+#define ADC3_FISR_FUL18_Msk (0x40000UL) /*!< FUL18 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL17_Pos (17UL) /*!< FUL17 (Bit 17) */
+#define ADC3_FISR_FUL17_Msk (0x20000UL) /*!< FUL17 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL16_Pos (16UL) /*!< FUL16 (Bit 16) */
+#define ADC3_FISR_FUL16_Msk (0x10000UL) /*!< FUL16 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL15_Pos (15UL) /*!< FUL15 (Bit 15) */
+#define ADC3_FISR_FUL15_Msk (0x8000UL) /*!< FUL15 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL14_Pos (14UL) /*!< FUL14 (Bit 14) */
+#define ADC3_FISR_FUL14_Msk (0x4000UL) /*!< FUL14 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL13_Pos (13UL) /*!< FUL13 (Bit 13) */
+#define ADC3_FISR_FUL13_Msk (0x2000UL) /*!< FUL13 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL12_Pos (12UL) /*!< FUL12 (Bit 12) */
+#define ADC3_FISR_FUL12_Msk (0x1000UL) /*!< FUL12 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL11_Pos (11UL) /*!< FUL11 (Bit 11) */
+#define ADC3_FISR_FUL11_Msk (0x800UL) /*!< FUL11 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL10_Pos (10UL) /*!< FUL10 (Bit 10) */
+#define ADC3_FISR_FUL10_Msk (0x400UL) /*!< FUL10 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL9_Pos (9UL) /*!< FUL9 (Bit 9) */
+#define ADC3_FISR_FUL9_Msk (0x200UL) /*!< FUL9 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL8_Pos (8UL) /*!< FUL8 (Bit 8) */
+#define ADC3_FISR_FUL8_Msk (0x100UL) /*!< FUL8 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL7_Pos (7UL) /*!< FUL7 (Bit 7) */
+#define ADC3_FISR_FUL7_Msk (0x80UL) /*!< FUL7 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL6_Pos (6UL) /*!< FUL6 (Bit 6) */
+#define ADC3_FISR_FUL6_Msk (0x40UL) /*!< FUL6 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL5_Pos (5UL) /*!< FUL5 (Bit 5) */
+#define ADC3_FISR_FUL5_Msk (0x20UL) /*!< FUL5 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL4_Pos (4UL) /*!< FUL4 (Bit 4) */
+#define ADC3_FISR_FUL4_Msk (0x10UL) /*!< FUL4 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL3_Pos (3UL) /*!< FUL3 (Bit 3) */
+#define ADC3_FISR_FUL3_Msk (0x8UL) /*!< FUL3 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL2_Pos (2UL) /*!< FUL2 (Bit 2) */
+#define ADC3_FISR_FUL2_Msk (0x4UL) /*!< FUL2 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL1_Pos (1UL) /*!< FUL1 (Bit 1) */
+#define ADC3_FISR_FUL1_Msk (0x2UL) /*!< FUL1 (Bitfield-Mask: 0x01) */
+#define ADC3_FISR_FUL0_Pos (0UL) /*!< FUL0 (Bit 0) */
+#define ADC3_FISR_FUL0_Msk (0x1UL) /*!< FUL0 (Bitfield-Mask: 0x01) */
+/* ========================================================= FIER ========================================================== */
+#define ADC3_FIER_FULIE19_Pos (19UL) /*!< FULIE19 (Bit 19) */
+#define ADC3_FIER_FULIE19_Msk (0x80000UL) /*!< FULIE19 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE18_Pos (18UL) /*!< FULIE18 (Bit 18) */
+#define ADC3_FIER_FULIE18_Msk (0x40000UL) /*!< FULIE18 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE17_Pos (17UL) /*!< FULIE17 (Bit 17) */
+#define ADC3_FIER_FULIE17_Msk (0x20000UL) /*!< FULIE17 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE16_Pos (16UL) /*!< FULIE16 (Bit 16) */
+#define ADC3_FIER_FULIE16_Msk (0x10000UL) /*!< FULIE16 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE15_Pos (15UL) /*!< FULIE15 (Bit 15) */
+#define ADC3_FIER_FULIE15_Msk (0x8000UL) /*!< FULIE15 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE14_Pos (14UL) /*!< FULIE14 (Bit 14) */
+#define ADC3_FIER_FULIE14_Msk (0x4000UL) /*!< FULIE14 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE13_Pos (13UL) /*!< FULIE13 (Bit 13) */
+#define ADC3_FIER_FULIE13_Msk (0x2000UL) /*!< FULIE13 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE12_Pos (12UL) /*!< FULIE12 (Bit 12) */
+#define ADC3_FIER_FULIE12_Msk (0x1000UL) /*!< FULIE12 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE11_Pos (11UL) /*!< FULIE11 (Bit 11) */
+#define ADC3_FIER_FULIE11_Msk (0x800UL) /*!< FULIE11 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE10_Pos (10UL) /*!< FULIE10 (Bit 10) */
+#define ADC3_FIER_FULIE10_Msk (0x400UL) /*!< FULIE10 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE9_Pos (9UL) /*!< FULIE9 (Bit 9) */
+#define ADC3_FIER_FULIE9_Msk (0x200UL) /*!< FULIE9 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE8_Pos (8UL) /*!< FULIE8 (Bit 8) */
+#define ADC3_FIER_FULIE8_Msk (0x100UL) /*!< FULIE8 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE7_Pos (7UL) /*!< FULIE7 (Bit 7) */
+#define ADC3_FIER_FULIE7_Msk (0x80UL) /*!< FULIE7 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE6_Pos (6UL) /*!< FULIE6 (Bit 6) */
+#define ADC3_FIER_FULIE6_Msk (0x40UL) /*!< FULIE6 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE5_Pos (5UL) /*!< FULIE5 (Bit 5) */
+#define ADC3_FIER_FULIE5_Msk (0x20UL) /*!< FULIE5 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE4_Pos (4UL) /*!< FULIE4 (Bit 4) */
+#define ADC3_FIER_FULIE4_Msk (0x10UL) /*!< FULIE4 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE3_Pos (3UL) /*!< FULIE3 (Bit 3) */
+#define ADC3_FIER_FULIE3_Msk (0x8UL) /*!< FULIE3 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE2_Pos (2UL) /*!< FULIE2 (Bit 2) */
+#define ADC3_FIER_FULIE2_Msk (0x4UL) /*!< FULIE2 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE1_Pos (1UL) /*!< FULIE1 (Bit 1) */
+#define ADC3_FIER_FULIE1_Msk (0x2UL) /*!< FULIE1 (Bitfield-Mask: 0x01) */
+#define ADC3_FIER_FULIE0_Pos (0UL) /*!< FULIE0 (Bit 0) */
+#define ADC3_FIER_FULIE0_Msk (0x1UL) /*!< FULIE0 (Bitfield-Mask: 0x01) */
+/* ========================================================= TCR0 ========================================================== */
+#define ADC3_TCR0_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR0_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR0_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR0_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR0_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR0_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR0_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR0_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR0 ========================================================== */
+#define ADC3_TAR0_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR0_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR0 ========================================================== */
+#define ADC3_TLR0_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR0_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR1 ========================================================== */
+#define ADC3_TCR1_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR1_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR1_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR1_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR1_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR1_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR1_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR1 ========================================================== */
+#define ADC3_TAR1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR1_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR1 ========================================================== */
+#define ADC3_TLR1_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR1_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR2 ========================================================== */
+#define ADC3_TCR2_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR2_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR2_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR2_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR2_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR2_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR2_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR2 ========================================================== */
+#define ADC3_TAR2_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR2_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR2 ========================================================== */
+#define ADC3_TLR2_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR2_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR3 ========================================================== */
+#define ADC3_TCR3_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR3_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR3_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR3_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR3_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR3_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR3_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR3_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR3 ========================================================== */
+#define ADC3_TAR3_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR3_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR3 ========================================================== */
+#define ADC3_TLR3_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR3_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR4 ========================================================== */
+#define ADC3_TCR4_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR4_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR4_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR4_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR4_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR4_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR4_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR4_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR4 ========================================================== */
+#define ADC3_TAR4_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR4_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR4 ========================================================== */
+#define ADC3_TLR4_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR4_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR5 ========================================================== */
+#define ADC3_TCR5_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR5_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR5_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR5_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR5_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR5_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR5_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR5_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR5 ========================================================== */
+#define ADC3_TAR5_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR5_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR5 ========================================================== */
+#define ADC3_TLR5_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR5_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR6 ========================================================== */
+#define ADC3_TCR6_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR6_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR6_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR6_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR6_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR6_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR6_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR6_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR6 ========================================================== */
+#define ADC3_TAR6_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR6_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR6 ========================================================== */
+#define ADC3_TLR6_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR6_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR7 ========================================================== */
+#define ADC3_TCR7_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR7_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR7_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR7_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR7_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR7_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR7_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR7_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR7 ========================================================== */
+#define ADC3_TAR7_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR7_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR7 ========================================================== */
+#define ADC3_TLR7_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR7_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR8 ========================================================== */
+#define ADC3_TCR8_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR8_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR8_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR8_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR8_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR8_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR8_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR8_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR8 ========================================================== */
+#define ADC3_TAR8_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR8_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR8 ========================================================== */
+#define ADC3_TLR8_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR8_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR9 ========================================================== */
+#define ADC3_TCR9_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR9_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR9_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR9_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR9_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR9_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR9_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR9_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR9 ========================================================== */
+#define ADC3_TAR9_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR9_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR9 ========================================================== */
+#define ADC3_TLR9_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR9_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR10 ========================================================= */
+#define ADC3_TCR10_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR10_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR10_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR10_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR10_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR10_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR10_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR10_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR10 ========================================================= */
+#define ADC3_TAR10_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR10_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR10 ========================================================= */
+#define ADC3_TLR10_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR10_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR11 ========================================================= */
+#define ADC3_TCR11_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR11_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR11_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR11_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR11_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR11_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR11_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR11_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR11 ========================================================= */
+#define ADC3_TAR11_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR11_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR11 ========================================================= */
+#define ADC3_TLR11_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR11_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR12 ========================================================= */
+#define ADC3_TCR12_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR12_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR12_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR12_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR12_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR12_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR12_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR12_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR12 ========================================================= */
+#define ADC3_TAR12_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR12_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR12 ========================================================= */
+#define ADC3_TLR12_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR12_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR13 ========================================================= */
+#define ADC3_TCR13_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR13_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR13_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR13_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR13_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR13_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR13_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR13_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR13 ========================================================= */
+#define ADC3_TAR13_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR13_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR13 ========================================================= */
+#define ADC3_TLR13_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR13_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR14 ========================================================= */
+#define ADC3_TCR14_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR14_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR14_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR14_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR14_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR14_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR14_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR14_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR14 ========================================================= */
+#define ADC3_TAR14_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR14_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR14 ========================================================= */
+#define ADC3_TLR14_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR14_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR15 ========================================================= */
+#define ADC3_TCR15_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR15_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR15_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR15_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR15_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR15_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR15_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR15_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR15 ========================================================= */
+#define ADC3_TAR15_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR15_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR15 ========================================================= */
+#define ADC3_TLR15_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR15_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR16 ========================================================= */
+#define ADC3_TCR16_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR16_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR16_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR16_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR16_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR16_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR16_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR16_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR16 ========================================================= */
+#define ADC3_TAR16_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR16_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR16 ========================================================= */
+#define ADC3_TLR16_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR16_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR17 ========================================================= */
+#define ADC3_TCR17_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR17_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR17_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR17_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR17_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR17_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR17_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR17_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR17 ========================================================= */
+#define ADC3_TAR17_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR17_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR17 ========================================================= */
+#define ADC3_TLR17_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR17_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR18 ========================================================= */
+#define ADC3_TCR18_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR18_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR18_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR18_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR18_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR18_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR18_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR18_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR18 ========================================================= */
+#define ADC3_TAR18_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR18_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR18 ========================================================= */
+#define ADC3_TLR18_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR18_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================= TCR19 ========================================================= */
+#define ADC3_TCR19_FIX_Pos (3UL) /*!< FIX (Bit 3) */
+#define ADC3_TCR19_FIX_Msk (0x8UL) /*!< FIX (Bitfield-Mask: 0x01) */
+#define ADC3_TCR19_CIRC_Pos (2UL) /*!< CIRC (Bit 2) */
+#define ADC3_TCR19_CIRC_Msk (0x4UL) /*!< CIRC (Bitfield-Mask: 0x01) */
+#define ADC3_TCR19_STP_Pos (1UL) /*!< STP (Bit 1) */
+#define ADC3_TCR19_STP_Msk (0x2UL) /*!< STP (Bitfield-Mask: 0x01) */
+#define ADC3_TCR19_START_Pos (0UL) /*!< START (Bit 0) */
+#define ADC3_TCR19_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
+/* ========================================================= TAR19 ========================================================= */
+#define ADC3_TAR19_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
+#define ADC3_TAR19_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
+/* ========================================================= TLR19 ========================================================= */
+#define ADC3_TLR19_LENG_Pos (0UL) /*!< LENG (Bit 0) */
+#define ADC3_TLR19_LENG_Msk (0xffffUL) /*!< LENG (Bitfield-Mask: 0xffff) */
+/* ========================================================== CCR ========================================================== */
+#define ADC3_CCR_DELAY_Pos (8UL) /*!< DELAY (Bit 8) */
+#define ADC3_CCR_DELAY_Msk (0x3ff00UL) /*!< DELAY (Bitfield-Mask: 0x3ff) */
+#define ADC3_CCR_DUAL_Pos (0UL) /*!< DUAL (Bit 0) */
+#define ADC3_CCR_DUAL_Msk (0xfUL) /*!< DUAL (Bitfield-Mask: 0x0f) */
+/* ========================================================== CSR ========================================================== */
+#define ADC3_CSR_EOSMP_SLV_Pos (25UL) /*!< EOSMP_SLV (Bit 25) */
+#define ADC3_CSR_EOSMP_SLV_Msk (0x2000000UL) /*!< EOSMP_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_ADRDY_SLV_Pos (24UL) /*!< ADRDY_SLV (Bit 24) */
+#define ADC3_CSR_ADRDY_SLV_Msk (0x1000000UL) /*!< ADRDY_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD2_SLV_Pos (23UL) /*!< AWD2_SLV (Bit 23) */
+#define ADC3_CSR_AWD2_SLV_Msk (0x800000UL) /*!< AWD2_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD1_SLV_Pos (22UL) /*!< AWD1_SLV (Bit 22) */
+#define ADC3_CSR_AWD1_SLV_Msk (0x400000UL) /*!< AWD1_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD0_SLV_Pos (21UL) /*!< AWD0_SLV (Bit 21) */
+#define ADC3_CSR_AWD0_SLV_Msk (0x200000UL) /*!< AWD0_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_OVR_SLV_Pos (20UL) /*!< OVR_SLV (Bit 20) */
+#define ADC3_CSR_OVR_SLV_Msk (0x100000UL) /*!< OVR_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_JEOS_SLV_Pos (19UL) /*!< JEOS_SLV (Bit 19) */
+#define ADC3_CSR_JEOS_SLV_Msk (0x80000UL) /*!< JEOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_JEOC_SLV_Pos (18UL) /*!< JEOC_SLV (Bit 18) */
+#define ADC3_CSR_JEOC_SLV_Msk (0x40000UL) /*!< JEOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_EOS_SLV_Pos (17UL) /*!< EOS_SLV (Bit 17) */
+#define ADC3_CSR_EOS_SLV_Msk (0x20000UL) /*!< EOS_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_EOC_SLV_Pos (16UL) /*!< EOC_SLV (Bit 16) */
+#define ADC3_CSR_EOC_SLV_Msk (0x10000UL) /*!< EOC_SLV (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_EOSMP_MST_Pos (9UL) /*!< EOSMP_MST (Bit 9) */
+#define ADC3_CSR_EOSMP_MST_Msk (0x200UL) /*!< EOSMP_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_ADRDY_MST_Pos (8UL) /*!< ADRDY_MST (Bit 8) */
+#define ADC3_CSR_ADRDY_MST_Msk (0x100UL) /*!< ADRDY_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD2_MST_Pos (7UL) /*!< AWD2_MST (Bit 7) */
+#define ADC3_CSR_AWD2_MST_Msk (0x80UL) /*!< AWD2_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD1_MST_Pos (6UL) /*!< AWD1_MST (Bit 6) */
+#define ADC3_CSR_AWD1_MST_Msk (0x40UL) /*!< AWD1_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_AWD0_MST_Pos (5UL) /*!< AWD0_MST (Bit 5) */
+#define ADC3_CSR_AWD0_MST_Msk (0x20UL) /*!< AWD0_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_OVR_MST_Pos (4UL) /*!< OVR_MST (Bit 4) */
+#define ADC3_CSR_OVR_MST_Msk (0x10UL) /*!< OVR_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_JEOS_MST_Pos (3UL) /*!< JEOS_MST (Bit 3) */
+#define ADC3_CSR_JEOS_MST_Msk (0x8UL) /*!< JEOS_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_JEOC_MST_Pos (2UL) /*!< JEOC_MST (Bit 2) */
+#define ADC3_CSR_JEOC_MST_Msk (0x4UL) /*!< JEOC_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_EOS_MST_Pos (1UL) /*!< EOS_MST (Bit 1) */
+#define ADC3_CSR_EOS_MST_Msk (0x2UL) /*!< EOS_MST (Bitfield-Mask: 0x01) */
+#define ADC3_CSR_EOC_MST_Pos (0UL) /*!< EOC_MST (Bit 0) */
+#define ADC3_CSR_EOC_MST_Msk (0x1UL) /*!< EOC_MST (Bitfield-Mask: 0x01) */
+/* ========================================================== CDR ========================================================== */
+#define ADC3_CDR_RDATA_SLV_Pos (16UL) /*!< RDATA_SLV (Bit 16) */
+#define ADC3_CDR_RDATA_SLV_Msk (0xffff0000UL) /*!< RDATA_SLV (Bitfield-Mask: 0xffff) */
+#define ADC3_CDR_RDATA_MST_Pos (0UL) /*!< RDATA_MST (Bit 0) */
+#define ADC3_CDR_RDATA_MST_Msk (0xffffUL) /*!< RDATA_MST (Bitfield-Mask: 0xffff) */
+
+
+/* =========================================================================================================================== */
+/* ================ TMR6 ================ */
+/* =========================================================================================================================== */
+
+/* ========================================================== CR0 ========================================================== */
+#define TMR6_CR0_ARE_Pos (7UL) /*!< ARE (Bit 7) */
+#define TMR6_CR0_ARE_Msk (0x80UL) /*!< ARE (Bitfield-Mask: 0x01) */
+#define TMR6_CR0_OPM_Pos (3UL) /*!< OPM (Bit 3) */
+#define TMR6_CR0_OPM_Msk (0x8UL) /*!< OPM (Bitfield-Mask: 0x01) */
+#define TMR6_CR0_CEN_Pos (0UL) /*!< CEN (Bit 0) */
+#define TMR6_CR0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */
+/* ========================================================== SCR ========================================================== */
+#define TMR6_SCR_EE_Pos (22UL) /*!< EE (Bit 22) */
+#define TMR6_SCR_EE_Msk (0x400000UL) /*!< EE (Bitfield-Mask: 0x01) */
+#define TMR6_SCR_EMS_Pos (20UL) /*!< EMS (Bit 20) */
+#define TMR6_SCR_EMS_Msk (0x300000UL) /*!< EMS (Bitfield-Mask: 0x03) */
+#define TMR6_SCR_EFS_Pos (16UL) /*!< EFS (Bit 16) */
+#define TMR6_SCR_EFS_Msk (0xf0000UL) /*!< EFS (Bitfield-Mask: 0x0f) */
+#define TMR6_SCR_TS_Pos (8UL) /*!< TS (Bit 8) */
+#define TMR6_SCR_TS_Msk (0x1f00UL) /*!< TS (Bitfield-Mask: 0x1f) */
+#define TMR6_SCR_SMS_Pos (0UL) /*!< SMS (Bit 0) */
+#define TMR6_SCR_SMS_Msk (0xfUL) /*!< SMS (Bitfield-Mask: 0x0f) */
+/* ========================================================== IER ========================================================== */
+#define TMR6_IER_TIE_Pos (10UL) /*!< TIE (Bit 10) */
+#define TMR6_IER_TIE_Msk (0x400UL) /*!< TIE (Bitfield-Mask: 0x01) */
+#define TMR6_IER_UIE_Pos (8UL) /*!< UIE (Bit 8) */
+#define TMR6_IER_UIE_Msk (0x100UL) /*!< UIE (Bitfield-Mask: 0x01) */
+#define TMR6_IER_CIE_Pos (0UL) /*!< CIE (Bit 0) */
+#define TMR6_IER_CIE_Msk (0x1UL) /*!< CIE (Bitfield-Mask: 0x01) */
+/* ========================================================== SR =========================================================== */
+#define TMR6_SR_STS_Pos (18UL) /*!< STS (Bit 18) */
+#define TMR6_SR_STS_Msk (0x40000UL) /*!< STS (Bitfield-Mask: 0x01) */
+#define TMR6_SR_CUS_Pos (17UL) /*!< CUS (Bit 17) */
+#define TMR6_SR_CUS_Msk (0x20000UL) /*!< CUS (Bitfield-Mask: 0x01) */
+#define TMR6_SR_PUS_Pos (16UL) /*!< PUS (Bit 16) */
+#define TMR6_SR_PUS_Msk (0x10000UL) /*!< PUS (Bitfield-Mask: 0x01) */
+#define TMR6_SR_TIF_Pos (10UL) /*!< TIF (Bit 10) */
+#define TMR6_SR_TIF_Msk (0x400UL) /*!< TIF (Bitfield-Mask: 0x01) */
+#define TMR6_SR_UIF_Pos (8UL) /*!< UIF (Bit 8) */
+#define TMR6_SR_UIF_Msk (0x100UL) /*!< UIF (Bitfield-Mask: 0x01) */
+#define TMR6_SR_CIF_Pos (0UL) /*!< CIF (Bit 0) */
+#define TMR6_SR_CIF_Msk (0x1UL) /*!< CIF (Bitfield-Mask: 0x01) */
+/* ========================================================== UGR ========================================================== */
+#define TMR6_UGR_SG_Pos (12UL) /*!< SG (Bit 12) */
+#define TMR6_UGR_SG_Msk (0x1000UL) /*!< SG (Bitfield-Mask: 0x01) */
+#define TMR6_UGR_CG_Pos (4UL) /*!< CG (Bit 4) */
+#define TMR6_UGR_CG_Msk (0x10UL) /*!< CG (Bitfield-Mask: 0x01) */
+#define TMR6_UGR_TG_Pos (1UL) /*!< TG (Bit 1) */
+#define TMR6_UGR_TG_Msk (0x2UL) /*!< TG (Bitfield-Mask: 0x01) */
+#define TMR6_UGR_UG_Pos (0UL) /*!< UG (Bit 0) */
+#define TMR6_UGR_UG_Msk (0x1UL) /*!< UG (Bitfield-Mask: 0x01) */
+/* ========================================================= CCMR ========================================================== */
+#define TMR6_CCMR_RLD_Pos (2UL) /*!< RLD (Bit 2) */
+#define TMR6_CCMR_RLD_Msk (0x4UL) /*!< RLD (Bitfield-Mask: 0x01) */
+/* ========================================================= CCER ========================================================== */
+#define TMR6_CCER_CCP_Pos (2UL) /*!< CCP (Bit 2) */
+#define TMR6_CCER_CCP_Msk (0x4UL) /*!< CCP (Bitfield-Mask: 0x01) */
+#define TMR6_CCER_CCE_Pos (0UL) /*!< CCE (Bit 0) */
+#define TMR6_CCER_CCE_Msk (0x1UL) /*!< CCE (Bitfield-Mask: 0x01) */
+/* ========================================================== CPR ========================================================== */
+#define TMR6_CPR_CPV_Pos (0UL) /*!< CPV (Bit 0) */
+#define TMR6_CPR_CPV_Msk (0xffffUL) /*!< CPV (Bitfield-Mask: 0xffff) */
+/* ========================================================= PSCR ========================================================== */
+#define TMR6_PSCR_PSC_Pos (0UL) /*!< PSC (Bit 0) */
+#define TMR6_PSCR_PSC_Msk (0xffUL) /*!< PSC (Bitfield-Mask: 0xff) */
+/* ========================================================= CNTR ========================================================== */
+#define TMR6_CNTR_CNT_Pos (0UL) /*!< CNT (Bit 0) */
+#define TMR6_CNTR_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
+/* ========================================================= CC0R ========================================================== */
+#define TMR6_CC0R_CMP_Pos (0UL) /*!< CMP (Bit 0) */
+#define TMR6_CC0R_CMP_Msk (0xffffUL) /*!< CMP (Bitfield-Mask: 0xffff) */
+
+/** @} */ /* End of group PosMask_peripherals */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MYCHIP_H */
+
+
+/** @} */ /* End of group myChip */
+
+/** @} */ /* End of group ARM Ltd. */
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Inc/system_myChip.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Inc/system_myChip.h
new file mode 100644
index 0000000000..9cde8ed200
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Inc/system_myChip.h
@@ -0,0 +1,86 @@
+/**
+ ******************************************************************************
+ * @file system_myChip.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Header File.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. Flash Configuration
+; Flash Base Address <0x0-0xFFFFFFFF:8>
+; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x08000000
+#define __ROM_SIZE 0x00020000
+
+/*--------------------- RAMCODE Section Configuration ------------------------
+; RAMCODE Configuration
+; RAMCODE Base Address <0x0-0xFFFFFFFF:8>
+; RAMCODE Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMCODE_BASE 0x10000000
+#define __RAMCODE_SIZE 0x00000000
+
+/*--------------------- Embedded RAMA Configuration --------------------------
+; RAMA Configuration
+; RAMA Base Address <0x0-0xFFFFFFFF:8>
+; RAMA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMA_BASE 0x20000000
+#define __RAMA_SIZE 0x00010000
+
+/*--------------------- Embedded RAMB Configuration --------------------------
+; RAMB Configuration
+; RAMB Base Address <0x0-0xFFFFFFFF:8>
+; RAMB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMB_BASE 0x20010000
+#define __RAMB_SIZE 0x00010000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; Stack / Heap Configuration
+; Stack and Heap will be placed in RAMA
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000400
+#define __HEAP_SIZE 0x00000000
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAMA_BASE + __RAMA_SIZE) /* starts at end of RAMA */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAMA section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_CODE_BASE __RAMCODE_BASE
+#define __RW_CODE_SIZE __RAMCODE_SIZE
+
+#define __RW_BASE (__RAMA_BASE + __RAMCODE_SIZE)
+#define __RW_SIZE (__RAMA_SIZE - __RAMCODE_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+#if __RW_CODE_SIZE > 0
+ RW_CODE __RW_CODE_BASE __RW_CODE_SIZE {
+ *.o (RAMCODE)
+ }
+#endif
+
+ RW_RAMA __RW_BASE __RW_SIZE { ; RWA data
+ *.o (SECTION_RAMA)
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+ RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region
+ *.o (SECTION_RAMB)
+ }
+}
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/ARM/tae32g58xx_ac5_sram.sct b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/ARM/tae32g58xx_ac5_sram.sct
new file mode 100644
index 0000000000..6f5934eccc
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/ARM/tae32g58xx_ac5_sram.sct
@@ -0,0 +1,110 @@
+#! armcc -E
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; Flash Configuration
+; Flash Base Address <0x0-0xFFFFFFFF:8>
+; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x20000000
+#define __ROM_SIZE 0x00010000
+
+/*--------------------- RAMCODE Section Configuration ------------------------
+; RAMCODE Configuration
+; RAMCODE Base Address <0x0-0xFFFFFFFF:8>
+; RAMCODE Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMCODE_BASE 0x10000000
+#define __RAMCODE_SIZE 0x00000000
+
+/*--------------------- Embedded RAMA Configuration --------------------------
+; RAMA Configuration
+; RAMA Base Address <0x0-0xFFFFFFFF:8>
+; RAMA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMA_BASE 0x20010000
+#define __RAMA_SIZE 0x00008000
+
+/*--------------------- Embedded RAMB Configuration --------------------------
+; RAMB Configuration
+; RAMB Base Address <0x0-0xFFFFFFFF:8>
+; RAMB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMB_BASE 0x20018000
+#define __RAMB_SIZE 0x00008000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; Stack / Heap Configuration
+; Stack and Heap will be placed in RAMA
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000400
+#define __HEAP_SIZE 0x00000000
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAMA_BASE + __RAMA_SIZE) /* starts at end of RAMA */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAMA section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_CODE_BASE __RAMCODE_BASE
+#define __RW_CODE_SIZE __RAMCODE_SIZE
+
+#define __RW_BASE (__RAMA_BASE + __RAMCODE_SIZE)
+#define __RW_SIZE (__RAMA_SIZE - __RAMCODE_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+#if __RW_CODE_SIZE > 0
+ RW_CODE __RW_CODE_BASE __RW_CODE_SIZE {
+ *.o (RAMCODE)
+ }
+#endif
+
+ RW_RAMA __RW_BASE __RW_SIZE { ; RWA data
+ *.o (SECTION_RAMA)
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+ RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region
+ *.o (SECTION_RAMB)
+ }
+}
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/ARM/tae32g58xx_ac6_flash.sct b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/ARM/tae32g58xx_ac6_flash.sct
new file mode 100644
index 0000000000..8fb31c9c61
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/ARM/tae32g58xx_ac6_flash.sct
@@ -0,0 +1,110 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; Flash Configuration
+; Flash Base Address <0x0-0xFFFFFFFF:8>
+; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x08000000
+#define __ROM_SIZE 0x00020000
+
+/*--------------------- RAMCODE Section Configuration ------------------------
+; RAMCODE Configuration
+; RAMCODE Base Address <0x0-0xFFFFFFFF:8>
+; RAMCODE Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMCODE_BASE 0x10000000
+#define __RAMCODE_SIZE 0x00000000
+
+/*--------------------- Embedded RAMA Configuration --------------------------
+; RAMA Configuration
+; RAMA Base Address <0x0-0xFFFFFFFF:8>
+; RAMA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMA_BASE 0x20000000
+#define __RAMA_SIZE 0x00010000
+
+/*--------------------- Embedded RAMB Configuration --------------------------
+; RAMB Configuration
+; RAMB Base Address <0x0-0xFFFFFFFF:8>
+; RAMB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMB_BASE 0x20010000
+#define __RAMB_SIZE 0x00010000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; Stack / Heap Configuration
+; Stack and Heap will be placed in RAMA
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000400
+#define __HEAP_SIZE 0x00000000
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAMA_BASE + __RAMA_SIZE) /* starts at end of RAMA */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAMA section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_CODE_BASE __RAMCODE_BASE
+#define __RW_CODE_SIZE __RAMCODE_SIZE
+
+#define __RW_BASE (__RAMA_BASE + __RAMCODE_SIZE)
+#define __RW_SIZE (__RAMA_SIZE - __RAMCODE_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+#if __RW_CODE_SIZE > 0
+ RW_CODE __RW_CODE_BASE __RW_CODE_SIZE {
+ *.o (RAMCODE)
+ }
+#endif
+
+ RW_RAMA __RW_BASE __RW_SIZE { ; RWA data
+ *.o (SECTION_RAMA)
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+ RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region
+ *.o (SECTION_RAMB)
+ }
+}
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/ARM/tae32g58xx_ac6_sram.sct b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/ARM/tae32g58xx_ac6_sram.sct
new file mode 100644
index 0000000000..e84cdfbcb2
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/ARM/tae32g58xx_ac6_sram.sct
@@ -0,0 +1,110 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; Flash Configuration
+; Flash Base Address <0x0-0xFFFFFFFF:8>
+; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x20000000
+#define __ROM_SIZE 0x00010000
+
+/*--------------------- RAMCODE Section Configuration ------------------------
+; RAMCODE Configuration
+; RAMCODE Base Address <0x0-0xFFFFFFFF:8>
+; RAMCODE Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMCODE_BASE 0x10000000
+#define __RAMCODE_SIZE 0x00000000
+
+/*--------------------- Embedded RAMA Configuration --------------------------
+; RAMA Configuration
+; RAMA Base Address <0x0-0xFFFFFFFF:8>
+; RAMA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMA_BASE 0x20010000
+#define __RAMA_SIZE 0x00008000
+
+/*--------------------- Embedded RAMB Configuration --------------------------
+; RAMB Configuration
+; RAMB Base Address <0x0-0xFFFFFFFF:8>
+; RAMB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __RAMB_BASE 0x20018000
+#define __RAMB_SIZE 0x00008000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; Stack / Heap Configuration
+; Stack and Heap will be placed in RAMA
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000400
+#define __HEAP_SIZE 0x00000000
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAMA_BASE + __RAMA_SIZE) /* starts at end of RAMA */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAMA section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_CODE_BASE __RAMCODE_BASE
+#define __RW_CODE_SIZE __RAMCODE_SIZE
+
+#define __RW_BASE (__RAMA_BASE + __RAMCODE_SIZE)
+#define __RW_SIZE (__RAMA_SIZE - __RAMCODE_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+#if __RW_CODE_SIZE > 0
+ RW_CODE __RW_CODE_BASE __RW_CODE_SIZE {
+ *.o (RAMCODE)
+ }
+#endif
+
+ RW_RAMA __RW_BASE __RW_SIZE { ; RWA data
+ *.o (SECTION_RAMA)
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+ RW_RAMB __RAMB_BASE __RAMB_SIZE { ; RWB region
+ *.o (SECTION_RAMB)
+ }
+}
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/gcc_arm-flash.ld b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/gcc_arm-flash.ld
new file mode 100644
index 0000000000..4dfc76d0c2
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/gcc_arm-flash.ld
@@ -0,0 +1,317 @@
+/******************************************************************************
+ * @file gcc_arm-flash.ld
+ * @brief GNU Linker Script for Cortex-M based device
+ * @version V2.0.0
+ * @date 11. Jul 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+ */
+
+/*---------------------- Flash Configuration ----------------------------------
+ Flash Configuration
+ Flash Base Address <0x0-0xFFFFFFFF:8>
+ Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x08000000;
+__ROM_SIZE = 0x00020000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+ RAM Configuration
+ RAM Base Address <0x0-0xFFFFFFFF:8>
+ RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__RAMA_BASE = 0x20000000;
+__RAMA_SIZE = 0x00010000;
+
+__RAMB_BASE = 0x20010000;
+__RAMB_SIZE = 0x00010000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+ Stack / Heap Configuration
+ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE = 0x00000000;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+ RAMA (rwx) : ORIGIN = __RAMA_BASE, LENGTH = __RAMA_SIZE
+ RAMB (rwx) : ORIGIN = __RAMB_BASE, LENGTH = __RAMB_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ /* ---< text sections Config >--- */
+ .text :
+ {
+ KEEP(*(.vectors))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+
+ /*
+ * SG veneers:
+ * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ * must be set, either with the command line option --section-start or in a linker script,
+ * to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+*/
+
+ /* ---< Copy&Zero table sections Config >--- */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG ((__data_end__ - __data_start__) / 4)
+
+ /* Add each additional data section here */
+/*
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG ((__data2_end__ - __data2_start__) / 4)
+*/
+
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+
+ LONG (__bss_start__)
+ LONG ((__bss_end__ - __bss_start__) / 4)
+
+ /* Add each additional bss section here */
+/*
+ LONG (__bss2_start__)
+ LONG ((__bss2_end__ - __bss2_start__) / 4)
+*/
+
+ __zero_table_end__ = .;
+ } > FLASH
+
+
+ /**
+ * Location counter can end up 2byte aligned with narrow Thumb code but
+ * __etext is assumed by startup code to be the LMA of a section in RAM
+ * which must be 4byte aligned
+ */
+ __etext = ALIGN (4);
+
+
+ /* ---< data sections Config >--- */
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data)
+ *(.data.*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAMA
+
+ /*
+ * Secondary data section, optional
+ *
+ * Remember to add each additional data section
+ * to the .copy.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ __etext2 = ALIGN (4);
+
+ .data2 : AT (__etext2)
+ {
+ . = ALIGN(4);
+ __data2_start__ = .;
+ *(.data2)
+ *(.data2.*)
+ . = ALIGN(4);
+ __data2_end__ = .;
+
+ } > RAMB
+*/
+
+
+ /* ---< bss sections Config >--- */
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAMA AT > RAMA
+
+ /*
+ * Secondary bss section, optional
+ *
+ * Remember to add each additional bss section
+ * to the .zero.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ .bss2 :
+ {
+ . = ALIGN(4);
+ __bss2_start__ = .;
+ *(.bss2)
+ *(.bss2.*)
+ . = ALIGN(4);
+ __bss2_end__ = .;
+ } > RAMB AT > RAMB
+*/
+
+
+ /* ---< Heap and Stack Config >--- */
+ .heap (COPY) :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ . = . + __HEAP_SIZE;
+ . = ALIGN(8);
+ __HeapLimit = .;
+ } > RAMA
+
+ .stack (ORIGIN(RAMA) + LENGTH(RAMA) - __STACK_SIZE) (COPY) :
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ . = . + __STACK_SIZE;
+ . = ALIGN(8);
+ __StackTop = .;
+ } > RAMA
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/gcc_arm-sram.ld b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/gcc_arm-sram.ld
new file mode 100644
index 0000000000..53b982753e
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/gcc_arm-sram.ld
@@ -0,0 +1,317 @@
+/******************************************************************************
+ * @file gcc_arm-sram.ld
+ * @brief GNU Linker Script for Cortex-M based device
+ * @version V2.0.0
+ * @date 11. Jul 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+ */
+
+/*---------------------- Flash Configuration ----------------------------------
+ Flash Configuration
+ Flash Base Address <0x0-0xFFFFFFFF:8>
+ Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x20000000;
+__ROM_SIZE = 0x00010000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+ RAM Configuration
+ RAM Base Address <0x0-0xFFFFFFFF:8>
+ RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__RAMA_BASE = 0x20010000;
+__RAMA_SIZE = 0x00008000;
+
+__RAMB_BASE = 0x20018000;
+__RAMB_SIZE = 0x00008000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+ Stack / Heap Configuration
+ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE = 0x00000000;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+ RAMA (rwx) : ORIGIN = __RAMA_BASE, LENGTH = __RAMA_SIZE
+ RAMB (rwx) : ORIGIN = __RAMB_BASE, LENGTH = __RAMB_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ /* ---< text sections Config >--- */
+ .text :
+ {
+ KEEP(*(.vectors))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+
+ /*
+ * SG veneers:
+ * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ * must be set, either with the command line option --section-start or in a linker script,
+ * to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+*/
+
+ /* ---< Copy&Zero table sections Config >--- */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG ((__data_end__ - __data_start__) / 4)
+
+ /* Add each additional data section here */
+/*
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG ((__data2_end__ - __data2_start__) / 4)
+*/
+
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+
+ LONG (__bss_start__)
+ LONG ((__bss_end__ - __bss_start__) / 4)
+
+ /* Add each additional bss section here */
+/*
+ LONG (__bss2_start__)
+ LONG ((__bss2_end__ - __bss2_start__) / 4)
+*/
+
+ __zero_table_end__ = .;
+ } > FLASH
+
+
+ /**
+ * Location counter can end up 2byte aligned with narrow Thumb code but
+ * __etext is assumed by startup code to be the LMA of a section in RAM
+ * which must be 4byte aligned
+ */
+ __etext = ALIGN (4);
+
+
+ /* ---< data sections Config >--- */
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data)
+ *(.data.*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAMA
+
+ /*
+ * Secondary data section, optional
+ *
+ * Remember to add each additional data section
+ * to the .copy.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ __etext2 = ALIGN (4);
+
+ .data2 : AT (__etext2)
+ {
+ . = ALIGN(4);
+ __data2_start__ = .;
+ *(.data2)
+ *(.data2.*)
+ . = ALIGN(4);
+ __data2_end__ = .;
+
+ } > RAMB
+*/
+
+
+ /* ---< bss sections Config >--- */
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAMA AT > RAMA
+
+ /*
+ * Secondary bss section, optional
+ *
+ * Remember to add each additional bss section
+ * to the .zero.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ .bss2 :
+ {
+ . = ALIGN(4);
+ __bss2_start__ = .;
+ *(.bss2)
+ *(.bss2.*)
+ . = ALIGN(4);
+ __bss2_end__ = .;
+ } > RAMB AT > RAMB
+*/
+
+
+ /* ---< Heap and Stack Config >--- */
+ .heap (COPY) :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ . = . + __HEAP_SIZE;
+ . = ALIGN(8);
+ __HeapLimit = .;
+ } > RAMA
+
+ .stack (ORIGIN(RAMA) + LENGTH(RAMA) - __STACK_SIZE) (COPY) :
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ . = . + __STACK_SIZE;
+ . = ALIGN(8);
+ __StackTop = .;
+ } > RAMA
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/tae32g5800_eval.cfg b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/tae32g5800_eval.cfg
new file mode 100644
index 0000000000..8a99c6c3ab
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/tae32g5800_eval.cfg
@@ -0,0 +1,12 @@
+# This is an TAE32 evaluation board with a single TAE32G58xx chip.
+
+source [find interface/cmsis-dap.cfg]
+
+transport select swd
+
+# increase working area to 32KB
+#set WORKAREASIZE 0x8000
+
+source [find target/tae32g58xx.cfg]
+
+#reset_config srst_only
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/tae32g58xx.cfg b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/tae32g58xx.cfg
new file mode 100644
index 0000000000..cc736e4bf5
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/GCC/tae32g58xx.cfg
@@ -0,0 +1,88 @@
+# script for tae32g58xx family
+
+#
+# tae32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME tae32g58xx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB (as found on some TAE32G58xx)
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x8000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+ set _FLASH_SIZE $FLASH_SIZE
+} else {
+ # autodetect size
+ set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ if { [using_jtag] } {
+ set _CPUTAPID 0x2ba01477
+ } {
+ # this is the SW-DP tap id not the jtag tap id
+ set _CPUTAPID 0x2ba01477
+ }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+ jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+#flash bank $_FLASHNAME tae32g58xx 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+ # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+ # DBG_STANDBY | DBG_STOP | DBG_SLEEP
+ mmw 0xE0042004 0x00000307 0
+}
+
+$_TARGETNAME configure -event trace-config {
+ # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+ # change this value accordingly to configure trace pins
+ # assignment
+ mmw 0xE0042004 0x00000020 0
+}
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/startup_tae32g58xx.c b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/startup_tae32g58xx.c
new file mode 100644
index 0000000000..77d87c0a44
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/startup_tae32g58xx.c
@@ -0,0 +1,400 @@
+/**
+ ******************************************************************************
+ * @file startup_tae32g58xx.c
+ * @author MCD Application Team
+ * @brief CMSIS-Core(M) Device Startup File for a tae32g58xx(Cortex-M4) Device
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+#include "tae32g58xx.h"
+
+
+/** @addtogroup TAE32G58xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup DEFINE_LL DEFINE LL
+ * @brief DEFINE LL
+ * @{
+ */
+
+
+/* Exported Constants --------------------------------------------------------*/
+/** @defgroup DEFINE_LL_Exported_Constants DEFINE LL Exported Constants
+ * @brief DEFINE LL Exported Constants
+ * @{
+ */
+
+/**
+ * @brief LL wait forever time definition
+ */
+#define LL_WAIT_FOREVER 0xFFFFFFFFUL
+
+/**
+ * @brief LL wait max delay time definition
+ */
+#define LL_MAX_DELAY (LL_WAIT_FOREVER - 1U)
+
+/**
+ * @}
+ */
+
+
+/* Exported Types ------------------------------------------------------------*/
+/** @defgroup DEFINE_LL_Exported_Types DEFINE LL Exported Types
+ * @brief DEFINE LL Exported Types
+ * @{
+ */
+
+/**
+ * @brief LL Status type definition
+ */
+typedef enum {
+ LL_OK = 0x00U, /*! LL status OK */
+ LL_ERROR = 0x01U, /*! LL status Error */
+ LL_BUSY = 0x02U, /*! LL status Busy */
+ LL_TIMEOUT = 0x03U, /*! LL status Timeout */
+ LL_FAILED = 0x04U, /*! LL status Failed */
+ LL_INVALID = 0x05U, /*! LL status Invalid */
+} LL_StatusETypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup DEFINE_LL_Exported_Macros DEFINE LL Exported Macros
+ * @brief DEFINE LL Exported Macros
+ * @{
+ */
+
+/* Compiler ALIAS and WEAK attribute definition */
+#if defined (__CC_ARM) /*!< AC5 Compiler */
+#define __ALIAS_FUNC(FUNC) __attribute__ ((weak, alias(#FUNC)))
+#define __WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS) void FUNC(void) __attribute__ ((weak, alias(#FUNC_ALIAS)));
+#elif defined (__ICCARM__) /*!< IAR Compiler */
+#define __WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS) void FUNC(void);_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS)))
+#define _WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS) weak WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /*!< AC6 Compiler */
+#define __ALIAS_FUNC(FUNC) __attribute__ ((weak, alias(#FUNC)))
+#define __WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS) void FUNC(void) __attribute__ ((weak, alias(#FUNC_ALIAS)));
+#elif defined (__GNUC__) /*!< GCC Compiler */
+#define __ALIAS_FUNC(FUNC) __attribute__ ((weak, alias(#FUNC)))
+#define __WEAK_ALIAS_FUNC(FUNC, FUNC_ALIAS) void FUNC(void) __attribute__ ((weak, alias(#FUNC_ALIAS)));
+#else
+#error Not supported compiler type
+#endif
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+/* Compiler aligned on 4-bytes attribute definition */
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__ ((aligned (4)))
+#endif
+
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif
+
+#else
+
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif
+
+#ifndef __ALIGN_BEGIN
+#if defined (__CC_ARM) /* ARM Compiler */
+#define __ALIGN_BEGIN __align(4)
+#elif defined (__ICCARM__) /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif
+#endif
+#endif
+
+
+/* Compiler __NOINLINE attribute definition */
+#if defined (__CC_ARM) || defined (__GNUC__) /* ARM & GNUCompiler */
+#define __NOINLINE __attribute__ ( (noinline) )
+#elif defined (__ICCARM__) /* ICCARM Compiler */
+#define __NOINLINE _Pragma("optimize = no_inline")
+#endif
+
+
+/* Compiler misc attribute definition */
+#if defined (__CC_ARM) /*!< AC5 Compiler */
+#define __NO_INIT __attribute__((zero_init))
+#define __AT(n) __attribute__((at(n)))
+#define __SECTION(SECT) __attribute__((section(#SECT)))
+#elif defined (__ICCARM__) /*!< IAR Compiler */
+#define __NO_INIT __no_init
+#define __AT(n) @(n)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /*!< AC6 Compiler */
+#define __NO_INIT
+#define __AT(n) __attribute__ ((section(".ARM.__at_"#n)))
+#define __SECTION(SECT) __attribute__((section(#SECT)))
+#elif defined (__GNUC__) /*!< GCC Compiler */
+#define __NO_INIT __attribute__((zero_init))
+#define __AT(n)
+#define __SECTION(SECT) __attribute__((section(#SECT)))
+#endif
+
+
+/**
+ * @brief Bit left shift definition
+ * @param pos left shift position
+ * @return Bit left shift value
+ */
+#define BIT(pos) (1U << (pos))
+
+/**
+ * @brief Set bit definition
+ * @param REG register
+ * @param BIT Bit to set
+ * @return None
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+/**
+ * @brief Clear bit definition
+ * @param REG register
+ * @param BIT Bit to clear
+ * @return None
+ */
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+/**
+ * @brief Read bit definition
+ * @param REG register
+ * @param BIT Bit to read
+ * @return Read bit value
+ */
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+/**
+ * @brief Read bit shift definition
+ * @param REG register
+ * @param BIT Bit to read
+ * @param SHIFT right shift after read
+ * @return Read bit shift value
+ */
+#define READ_BIT_SHIFT(REG, BIT, SHIFT) (((REG) & (BIT)) >> (SHIFT))
+
+/**
+ * @brief Clear register definiton
+ * @param REG register
+ * @return None
+ */
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+/**
+ * @brief Write register definiton
+ * @param REG register
+ * @param VAL write value
+ * @return None
+ */
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+/**
+ * @brief Read register definition
+ * @param REG register
+ * @return Read register Value
+ */
+#define READ_REG(REG) ((REG))
+
+/**
+ * @brief Modify register definition
+ * @param REG register
+ * @param CLEARMASK clear mask
+ * @param SETMASK set mask
+ * @return None
+ */
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | ((SETMASK) & (CLEARMASK))))
+
+/**
+ * @brief Position value definition
+ * @param VAL value
+ * @return Position value
+ */
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+
+/**
+ * @brief Return the Minimum Value between Two Input Params
+ * @param a One Input Param
+ * @param b The other Input Param
+ * @return the Minimum Value between Two Input Params
+ */
+#define LL_MIN(a, b) (((a) < (b)) ? (a) : (b))
+
+/**
+ * @brief Return the Maximum Value between Two Input Params
+ * @param a One Input Params
+ * @param b The other Input Params
+ * @return the Maximum Value between Two Input Params
+ */
+#define LL_MAX(a, b) (((a) > (b)) ? (a) : (b))
+
+/**
+ * @brief To avoid gcc/g++ warnings
+ * @param X avoid warning param
+ * @return None
+ */
+#define LL_UNUSED(X) (void)(X)
+
+/**
+ * @brief Macro for counting the element number of an array
+ * @param a Array to be Counted
+ * @return size of Array
+ */
+#define ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0]))
+
+/**
+ * @brief LL Function Alternative
+ * @param flag Condition Flag
+ * @param func_t True Funciton
+ * @param func_f False Function
+ * @return None
+ */
+#define LL_FUNC_ALTER(flag, func_t, func_f) \
+ do{ \
+ if((flag)) { \
+ func_t; \
+ } else { \
+ func_f; \
+ } \
+ } while(0)
+
+/**
+ * @}
+ */
+
+
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE32G58XX_LL_DEF_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Inc/tae32g58xx_ll_dma.h b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Inc/tae32g58xx_ll_dma.h
new file mode 100644
index 0000000000..39f9768033
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Inc/tae32g58xx_ll_dma.h
@@ -0,0 +1,720 @@
+/**
+ ******************************************************************************
+ * @file tae32g58xx_ll_dma.h
+ * @author MCD Application Team
+ * @brief Header file for DMA LL module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+
+
+#define DBG_TAG "CAN LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae_dbg.h"
+
+
+/** @addtogroup TAE32G58xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CAN_LL CAN LL
+ * @brief CAN LL Module Driver
+ * @{
+ */
+
+#ifdef LL_CAN_MODULE_ENABLED
+
+/* Private Constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+/** @defgroup CAN_LL_Private_Constants CAN LL Private Constants
+ * @brief CAN LL Private Constants
+ * @{
+ */
+
+/**
+ * @brief CAN Defaul Timeout definition in ms Unit
+ */
+#define CAN_DEFAULT_TIMEOUT (25)
+
+/**
+ * @}
+ */
+
+/* Private Types -------------------------------------------------------------*/
+/** @defgroup CAN_LL_Private_Types CAN LL Private Types
+ * @brief CAN LL Private Types
+ * @{
+ */
+
+/**
+ * @brief CAN IRQ callback function type definition
+ */
+typedef void (*CAN_LLIRQCallback)(CAN_TypeDef *Instance);
+
+/**
+ * @brief CAN Transmission Tx definition
+ */
+typedef struct __CAN_TransTxTypeDef {
+ CAN_StateETypeDef state; /*!< CAN Transmission State */
+ CAN_LLIRQCallback isr; /*!< Interrupt Service Routine */
+} CAN_TransTxTypeDef;
+
+/**
+ * @brief CAN Transmission Rx definition
+ */
+typedef struct __CAN_TransRxTypeDef {
+ uint32_t *buf; /*!< CAN Rx Buffer Pointer */
+ CAN_RxBufFormatTypeDef *buf_fmt; /*!< CAN Rx Buffer Format Pointer */
+ CAN_StateETypeDef state; /*!< CAN Transmission State */
+ CAN_LLIRQCallback isr; /*!< Interrupt Service Routine */
+} CAN_TransRxTypeDef;
+
+/**
+ * @brief CAN Tx Event definition
+ */
+typedef struct __CAN_TxEventTypeDef {
+ uint32_t *buf; /*!< CAN Tx Event Buffer Pointer */
+ CAN_TxEvtBufFormatTypeDef *buf_fmt; /*!< CAN Tx Event Format Pointer */
+ CAN_StateETypeDef state; /*!< CAN Transmission State */
+ CAN_LLIRQCallback isr; /*!< Interrupt Service Routine */
+} CAN_TxEventTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct __CAN_HandleTypeDef {
+ volatile CAN_TransTxTypeDef tx_ctrl_ptb; /*!< CAN PTB Transmission Tx Control */
+ volatile CAN_TransTxTypeDef tx_ctrl_stb; /*!< CAN STB Transmission Tx Control */
+ volatile CAN_TransRxTypeDef rx_ctrl; /*!< CAN Transmission Rx Control */
+ volatile CAN_TransRxTypeDef rx_ctrl_srb; /*!< CAN SRB Transmission Rx Control */
+ volatile CAN_TxEventTypeDef evt_ctrl_etb; /*!< CAN ETB Tx Event Control */
+
+ CAN_UserCallbackTypeDef user_callback; /*!< User Callback */
+} CAN_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Private Variables ---------------------------------------------------------*/
+/** @defgroup CAN_LL_Private_Variables CAN LL Private Variables
+ * @brief CAN LL Private Variables
+ * @{
+ */
+
+/**
+ * @brief Default CAN LL Config
+ */
+static const CAN_LLCfgTypeDef can_ll_cfg_def = {
+ .prot_exc_detect_dis = true,
+ .srb_almost_full_limit = CAN_BUF_ALMOST_FULL_LIMIT_2,
+ .etb_almost_full_limit = CAN_BUF_ALMOST_FULL_LIMIT_2,
+ .stb_almost_empty_limit = CAN_BUF_ALMOST_EMPTY_LIMIT_2,
+ .global_fil = {
+ .rej_std_remote_frm = false,
+ .rej_ext_remote_frm = false,
+ .prb_work_mode = CAN_RX_BUF_WORK_MODE_COVER,
+ .srb_work_mode = CAN_RX_BUF_WORK_MODE_COVER,
+ .ext_id_mask = 0x1FFFFFFFUL,
+ }
+};
+
+/**
+ * @brief CAN Handle global variable
+ */
+static CAN_HandleTypeDef can_hdl_global[CAN_INSTANCE_NUMS];
+
+/**
+ * @}
+ */
+
+
+/* Private Function Prototypes -----------------------------------------------*/
+/** @addtogroup CAN_LL_Private_Functions
+ * @{
+ */
+static CAN_HandleTypeDef *CAN_Handle_Get(CAN_TypeDef *Instance);
+static void CAN_TxISR_PTB(CAN_TypeDef *Instance);
+static void CAN_TxISR_STB(CAN_TypeDef *Instance);
+static void CAN_RxISR(CAN_TypeDef *Instance);
+static void CAN_RxISR_SRB(CAN_TypeDef *Instance);
+static void CAN_GetTxEvtISR_ETB(CAN_TypeDef *Instance);
+static void CAN_AbortISR(CAN_TypeDef *Instance);
+
+static LL_StatusETypeDef CAN_AcceptFilRst(CAN_TypeDef *Instance, CAN_AcceptFilSlotETypeDef slot);
+static LL_StatusETypeDef CAN_AcceptFilCfg(CAN_TypeDef *Instance, CAN_AcceptFilCfgTypeDef *fil_cfg);
+static LL_StatusETypeDef CAN_GlobalFilRst(CAN_TypeDef *Instance);
+static LL_StatusETypeDef CAN_GlobalFilCfg(CAN_TypeDef *Instance, CAN_GlobalFilCfgTypeDef *fil_cfg);
+
+static LL_StatusETypeDef CAN_TimeCounterCfg(CAN_TypeDef *Instance, CAN_TimeCntrCfgTypeDef *cntr_cfg);
+
+/**
+ * @}
+ */
+
+
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+/** @defgroup CAN_LL_Exported_Functions CAN LL Exported Functions
+ * @brief CAN LL Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_LL_Exported_Functions_Group1 CAN Init and DeInit Functions
+ * @brief CAN Init and DeInit Functions
+ * @{
+ */
+
+/**
+ * @brief CAN LL Init
+ * @param Instance Specifies CAN peripheral
+ * @param user_cfg user config pointer
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_CAN_Init(CAN_TypeDef *Instance, CAN_UserCfgTypeDef *user_cfg)
+{
+ CAN_HandleTypeDef *can_hdl;
+ CAN_LLCfgTypeDef *ll_cfg;
+ uint32_t state_reset;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(user_cfg != NULL);
+ assert_param(user_cfg->baudrate_ss);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || user_cfg == NULL || !user_cfg->baudrate_ss) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ }
+
+ state_reset = can_hdl->tx_ctrl_ptb.state | can_hdl->tx_ctrl_stb.state | can_hdl->rx_ctrl.state |
+ can_hdl->rx_ctrl_srb.state | can_hdl->evt_ctrl_etb.state;
+
+ if (state_reset != CAN_STATE_RESET) {
+ LOG_E("This CAN[0x%08" PRIx32 "] is being used!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_BUSY;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_BUSY;
+ can_hdl->rx_ctrl.state = CAN_STATE_BUSY;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_BUSY;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_BUSY;
+
+ //LL config pointer config
+ LL_FUNC_ALTER(user_cfg->ll_cfg == NULL, ll_cfg = (CAN_LLCfgTypeDef *)&can_ll_cfg_def, ll_cfg = user_cfg->ll_cfg);
+
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_CAN_MspInit(Instance);
+
+ /* Set reset status to config some register which can config in reset status only */
+ __LL_CAN_Reset_Set(Instance);
+
+ //Set all interrupt line select bit to zero
+ __LL_CAN_AllIntLine_Clr(Instance);
+
+ //LL Config
+ if ((__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) && (LL_IsExtCfgEnGrp(LL_EXT_CFG_GRP_MASK_CAN))) {
+ //Buffer Full Almost Warning limit
+ __LL_CAN_STBAlmostEmptyWarnLimit_Set(Instance, ll_cfg->stb_almost_empty_limit);
+ __LL_CAN_ETBAlmostFullWarnLimit_Set(Instance, ll_cfg->etb_almost_full_limit);
+ __LL_CAN_SRBAlmostFullWarnLimit_Set(Instance, ll_cfg->srb_almost_full_limit);
+
+ //Acceptance filter Reset
+ CAN_GlobalFilRst(Instance);
+
+ //Acceptance filter config
+ CAN_GlobalFilCfg(Instance, &ll_cfg->global_fil);
+
+ //Disable Protocol Exception Detect
+ LL_FUNC_ALTER(ll_cfg->prot_exc_detect_dis, __LL_CAN_ProtExcDetectDis_Assert(Instance), __LL_CAN_ProtExcDetectDis_Release(Instance));
+ }
+
+
+ //SS Baudrate and Bit timing config
+ __LL_CAN_SS_Prescaler_Set(Instance,
+ (user_cfg->func_clk_freq / (user_cfg->bit_timing_seg1_ss + user_cfg->bit_timing_seg2_ss + 3) / user_cfg->baudrate_ss - 1));
+ __LL_CAN_SS_BitTimingSeg1_Set(Instance, user_cfg->bit_timing_seg1_ss);
+ __LL_CAN_SS_BitTimingSeg2_Set(Instance, user_cfg->bit_timing_seg2_ss);
+ __LL_CAN_SS_SyncJumpWidth_Set(Instance, user_cfg->bit_timing_sjw_ss);
+
+ //FS(FD) Baudrate and Bit timing config
+ if (user_cfg->fd_en) {
+ __LL_CAN_FD_En(Instance);
+ LL_FUNC_ALTER(user_cfg->fd_iso_en, __LL_CAN_FD_ISO_En(Instance), __LL_CAN_FD_ISO_Dis(Instance));
+
+ assert_param(user_cfg->baudrate_fs);
+
+ if (!user_cfg->baudrate_fs) {
+ return LL_INVALID;
+ }
+
+ __LL_CAN_FS_Prescaler_Set(Instance,
+ (user_cfg->func_clk_freq / (user_cfg->bit_timing_seg1_fs + user_cfg->bit_timing_seg2_fs + 3) / user_cfg->baudrate_fs - 1));
+ __LL_CAN_FS_BitTimingSeg1_Set(Instance, user_cfg->bit_timing_seg1_fs);
+ __LL_CAN_FS_BitTimingSeg2_Set(Instance, user_cfg->bit_timing_seg2_fs);
+ __LL_CAN_FS_SyncJumpWidth_Set(Instance, user_cfg->bit_timing_sjw_fs);
+ } else {
+ __LL_CAN_FD_Dis(Instance);
+ }
+
+ //Acceptance filter Reset
+ for (uint8_t i = 0; i < CAN_ACCEPT_FILT_SLOT_NUMS; i++) {
+ CAN_AcceptFilRst(Instance, (CAN_AcceptFilSlotETypeDef)i);
+ }
+
+ //Acceptance filter config
+ for (uint8_t i = 0; i < user_cfg->accept_fil_cfg_num; i++) {
+ CAN_AcceptFilCfg(Instance, (CAN_AcceptFilCfgTypeDef *)&user_cfg->accept_fil_cfg_ptr[i]);
+ }
+
+ /* Clear reset status to config other register */
+ __LL_CAN_Reset_Clr(Instance);
+
+ //RX buffer almost full and error warning limit set
+ __LL_CAN_RxBufAlmostFullLimit_Set(Instance, user_cfg->rx_almost_full_limit);
+ __LL_CAN_ErrWarnLimit_Set(Instance, user_cfg->err_limit);
+
+ //rx receive multiplexer select set
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 2) {
+ __LL_CAN_RxMuxSel_Set(Instance, user_cfg->rx_muxsel);
+ }
+
+ //All Interrupt Pending Clear
+ __LL_CAN_AllIntPnd_Clr(Instance);
+
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_READY;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_READY;
+ can_hdl->rx_ctrl.state = CAN_STATE_READY;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_READY;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_READY;
+ can_hdl->user_callback = user_cfg->user_callback;
+
+ return LL_OK;
+}
+
+/**
+ * @brief CAN LL DeInit
+ * @param Instance Specifies CAN peripheral
+ * @return Status of the DeInitialization
+ */
+LL_StatusETypeDef LL_CAN_DeInit(CAN_TypeDef *Instance)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ }
+
+ if (can_hdl->tx_ctrl_ptb.state == CAN_STATE_BUSY_TX ||
+ can_hdl->tx_ctrl_stb.state == CAN_STATE_BUSY_TX ||
+ can_hdl->rx_ctrl.state == CAN_STATE_BUSY_RX ||
+ can_hdl->rx_ctrl_srb.state == CAN_STATE_BUSY_RX ||
+ can_hdl->evt_ctrl_etb.state == CAN_STATE_BUSY_RX) {
+ LOG_E("This CAN[0x%08" PRIx32 "] is being used!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_BUSY;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_BUSY;
+ can_hdl->rx_ctrl.state = CAN_STATE_BUSY;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_BUSY;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_BUSY;
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_CAN_MspDeInit(Instance);
+
+ memset((void *)can_hdl, 0, sizeof(CAN_HandleTypeDef));
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_RESET;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_RESET;
+ can_hdl->rx_ctrl.state = CAN_STATE_RESET;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_RESET;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_RESET;
+
+ return LL_OK;
+}
+
+/**
+ * @brief CAN LL Reset
+ * @param Instance Specifies CAN peripheral
+ * @return Status of the Reset
+ */
+LL_StatusETypeDef LL_CAN_Reset(CAN_TypeDef *Instance)
+{
+ CAN_HandleTypeDef *can_hdl;
+ IRQn_Type irq_num;
+ IRQn_Type irq_num1;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ }
+
+ irq_num = GET_CAN_INT0_IRQ_NUMBER(Instance);
+ if (irq_num < 0) {
+ LOG_E("CAN IRQ does not exist!\n");
+ return LL_ERROR;
+ }
+
+ irq_num1 = GET_CAN_INT1_IRQ_NUMBER(Instance);
+ if (irq_num1 < 0) {
+ LOG_E("CAN INT1 IRQ does not exist!\n");
+ return LL_ERROR;
+ }
+
+ //Clear pending and interrupt disable
+ __disable_irq();
+ CLEAR_BIT(Instance->INTREN, 0xfffffffeUL);
+ SET_BIT(Instance->INTRST, 0x3ffcfffeUL);
+ NVIC_ClearPendingIRQ(irq_num);
+ NVIC_DisableIRQ(irq_num);
+ NVIC_ClearPendingIRQ(irq_num1);
+ NVIC_DisableIRQ(irq_num1);
+ __LL_CAN_AllIntLine_Clr(Instance);
+ __enable_irq();
+
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_BUSY;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_BUSY;
+ can_hdl->rx_ctrl.state = CAN_STATE_BUSY;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_BUSY;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_BUSY;
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_CAN_MspDeInit(Instance);
+
+ memset((void *)can_hdl, 0, sizeof(CAN_HandleTypeDef));
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_RESET;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_RESET;
+ can_hdl->rx_ctrl.state = CAN_STATE_RESET;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_RESET;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_RESET;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_MspInit(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_MspDeInit(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Register an User CAN Callback
+ * @note User can register callback only in CAN Ready State
+ * @param Instance Specifies CAN peripheral
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_RegisterCallback(CAN_TypeDef *Instance, CAN_UserCallbackIdETypeDef CallbackID, CAN_UserCallback pCallback)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Check callback pointer valid or not
+ if (pCallback == NULL) {
+ LOG_E("The callback pointer which to be registered is NULL!\n");
+ return LL_INVALID;
+ }
+
+ //Register user callback
+ switch (CallbackID) {
+ case CAN_PTB_TX_CPLT_CB_ID:
+ if (can_hdl->tx_ctrl_ptb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] PTB Tx isn't in Ready state, can't register Tx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->user_callback.TxCpltCallback_ptb = pCallback;
+ break;
+
+ case CAN_STB_TX_CPLT_CB_ID:
+ if (can_hdl->tx_ctrl_stb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] STB Tx isn't in Ready state, can't register Tx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->user_callback.TxCpltCallback_stb = pCallback;
+ break;
+
+ case CAN_RX_CPLT_CB_ID:
+ if (can_hdl->rx_ctrl.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->user_callback.RxCpltCallback = pCallback;
+ break;
+
+ case CAN_SRB_RX_CPLT_CB_ID:
+ if (can_hdl->rx_ctrl_srb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] SRB Rx isn't in Ready state, can't register Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->user_callback.RxCpltCallback_srb = pCallback;
+ break;
+
+ case CAN_ETB_CPLT_CB_ID:
+ if (can_hdl->evt_ctrl_etb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] ETB isn't in Ready state, can't register ETB Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->user_callback.TxEvtCpltCallback_etb = pCallback;
+ break;
+
+ default:
+ LOG_E("CAN user callback ID-[%d] is Invalid!\n", CallbackID);
+ return LL_INVALID;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief UnRegister an User CAN Callback
+ * @note User can unregister callback only in CAN Ready State
+ * @param Instance Specifies CAN peripheral
+ * @param CallbackID ID of the callback to be unregistered
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_UnRegisterCallback(CAN_TypeDef *Instance, CAN_UserCallbackIdETypeDef CallbackID)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ }
+
+ //UnRegister user callback
+ switch (CallbackID) {
+ case CAN_PTB_TX_CPLT_CB_ID:
+ if (can_hdl->tx_ctrl_ptb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] PTB Tx isn't in Ready state, can't unregister Tx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->user_callback.TxCpltCallback_ptb = NULL;
+ break;
+
+ case CAN_STB_TX_CPLT_CB_ID:
+ if (can_hdl->tx_ctrl_stb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] STB Tx isn't in Ready state, can't unregister Tx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->user_callback.TxCpltCallback_stb = NULL;
+ break;
+
+ case CAN_RX_CPLT_CB_ID:
+ if (can_hdl->rx_ctrl.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->user_callback.RxCpltCallback = NULL;
+ break;
+
+ case CAN_SRB_RX_CPLT_CB_ID:
+ if (can_hdl->rx_ctrl_srb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] SRB Rx isn't in Ready state, can't unregister Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->user_callback.RxCpltCallback_srb = NULL;
+ break;
+
+ case CAN_ETB_CPLT_CB_ID:
+ if (can_hdl->evt_ctrl_etb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] ETB isn't in Ready state, can't unregister ETB Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->user_callback.TxEvtCpltCallback_etb = NULL;
+ break;
+
+ default:
+ LOG_E("CAN user callback ID-[%d] is Invalid!\n", CallbackID);
+ return LL_INVALID;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_LL_Exported_Functions_Group2 CAN LL Exported Functions Misc
+ * @brief CAN LL Exported Functions Misc
+ * @{
+ */
+
+/**
+ * @brief CAN LL reset enter
+ * @param Instance Specifies CAN peripheral
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_ResetEnter(CAN_TypeDef *Instance)
+{
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //CAN reset set
+ __LL_CAN_Reset_Set(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief CAN LL reset exit
+ * @param Instance Specifies CAN peripheral
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_ResetExit(CAN_TypeDef *Instance)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ }
+
+ //CAN reset clear
+ __LL_CAN_Reset_Clr(Instance);
+
+ memset((void *)can_hdl, 0, sizeof(CAN_HandleTypeDef));
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_READY;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_READY;
+ can_hdl->rx_ctrl.state = CAN_STATE_READY;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_READY;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_READY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief CAN LL acceptance filter config
+ * @param Instance Specifies CAN peripheral
+ * @param fil_cfg filter config pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_AcceptFilCfg(CAN_TypeDef *Instance, CAN_AcceptFilCfgTypeDef *fil_cfg)
+{
+ uint8_t rst_sta;
+ LL_StatusETypeDef ret;
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(fil_cfg != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || fil_cfg == NULL) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ }
+
+ //CAN reset status save
+ rst_sta = __LL_CAN_ResetSta_Get(Instance);
+
+ //CAN reset set
+ __LL_CAN_Reset_Set(Instance);
+
+ //CAN accept filter config
+ ret = CAN_AcceptFilCfg(Instance, fil_cfg);
+
+ //CAN reset status restroe
+ LL_FUNC_ALTER(rst_sta, __LL_CAN_Reset_Set(Instance), __LL_CAN_Reset_Clr(Instance));
+
+ memset((void *)can_hdl, 0, sizeof(CAN_HandleTypeDef));
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_READY;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_READY;
+ can_hdl->rx_ctrl.state = CAN_STATE_READY;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_READY;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_READY;
+
+ return ret;
+}
+
+/**
+ * @brief CAN Data Length Get
+ * @param Instance Specifies CAN peripheral
+ * @param dat_len_code Data length code
+ * @return Data length in bytes unit
+ */
+uint8_t LL_CAN_DatLen_Get(CAN_TypeDef *Instance, uint8_t dat_len_code)
+{
+ //Check params to be valid
+ if (!IS_CAN_ALL_INSTANCE(Instance) || dat_len_code >= 16) {
+ return 0;
+ }
+
+ uint8_t dat_len = ((uint8_t []) {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64
+ })[dat_len_code];
+
+ return __LL_CAN_IsFDEn(Instance) ? dat_len : LL_MIN(dat_len, CAN_20_DAT_LEN_MAX);
+}
+
+/**
+ * @brief CAN Data Length Code Get
+ * @param Instance Specifies CAN peripheral
+ * @param dat_len Data length that can only config in [0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64]
+ * @return Data length code @ref CAN_DatLenCodeETypeDef
+ */
+CAN_DatLenCodeETypeDef LL_CAN_DatLenCode_Get(CAN_TypeDef *Instance, uint8_t dat_len)
+{
+ //Check params to be valid
+ if (!IS_CAN_ALL_INSTANCE(Instance) || (__LL_CAN_IsFDEn(Instance) && dat_len > 64) ||
+ (!__LL_CAN_IsFDEn(Instance) && dat_len > CAN_20_DAT_LEN_MAX)) {
+ return CAN_DAT_LEN_CODE_BYTE_0;
+ }
+
+ const uint8_t dat_len_array[] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64
+ };
+
+ for (uint8_t i = 0; i < sizeof dat_len_array; i++) {
+ if (dat_len_array[i] == dat_len) {
+ return (CAN_DatLenCodeETypeDef)i;
+ }
+ }
+
+ return CAN_DAT_LEN_CODE_BYTE_0;
+}
+
+/**
+ * @brief CAN LL Global filter config
+ * @param Instance Specifies CAN peripheral
+ * @param fil_cfg Global filter config pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_GlobalFilCfg(CAN_TypeDef *Instance, CAN_GlobalFilCfgTypeDef *fil_cfg)
+{
+ uint8_t rst_sta;
+ LL_StatusETypeDef ret;
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(fil_cfg != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || fil_cfg == NULL) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ }
+
+ //CAN reset status save
+ rst_sta = __LL_CAN_ResetSta_Get(Instance);
+
+ //CAN reset set
+ __LL_CAN_Reset_Set(Instance);
+
+ //CAN accept filter config
+ ret = CAN_GlobalFilCfg(Instance, fil_cfg);
+
+ //CAN reset status restroe
+ LL_FUNC_ALTER(rst_sta, __LL_CAN_Reset_Set(Instance), __LL_CAN_Reset_Clr(Instance));
+
+ memset((void *)can_hdl, 0, sizeof(CAN_HandleTypeDef));
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_READY;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_READY;
+ can_hdl->rx_ctrl.state = CAN_STATE_READY;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_READY;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_READY;
+
+ return ret;
+}
+
+/**
+ * @brief CAN LL Timestamp Counter config
+ * @param Instance Specifies CAN peripheral
+ * @param cntr_cfg Timestamp Counter config pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_TimeCounterCfg(CAN_TypeDef *Instance, CAN_TimeCntrCfgTypeDef *cntr_cfg)
+{
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(cntr_cfg != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || cntr_cfg == NULL) {
+ return LL_INVALID;
+ }
+
+ //CAN Timestamp Counter config
+ return CAN_TimeCounterCfg(Instance, cntr_cfg);
+}
+
+/**
+ * @brief CAN Rx frame status get
+ * @param Instance Specifies CAN peripheral
+ * @param sta Rx frame status pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_RxFrmSta_Get(CAN_TypeDef *Instance, CAN_ProtStaTypeDef *sta)
+{
+ uint32_t fd_sta_msk;
+ uint32_t fd_frm_type_msk;
+ volatile uint32_t prot_sta;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(sta != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || sta == NULL) {
+ return LL_INVALID;
+ }
+
+ //Read Protocol Status
+ prot_sta = __LL_CAN_ProtStaReg_Read(Instance);
+
+ sta->fd_dat_frm = false;
+ sta->fd_acc_dat = false;
+ sta->fd_ext_dat = false;
+
+ sta->rx_store_mode = (CAN_FrmStoreModeETypeDef)__LL_CAN_RxFrmStoreMode_Extract(prot_sta);
+ sta->node_sta = (CAN_NodeStaETypeDef)__LL_CAN_NodeSta_Extract(prot_sta);
+ sta->err_code = (CAN_DatFieldErrETypeDef)__LL_CAN_DataErrType_Extract(prot_sta);
+
+ fd_sta_msk = __LL_CAN_RxFDDatFrmType_Extract(prot_sta);
+ (fd_sta_msk & 0x4UL) ? (sta->fd_prot_mistake = true) : (sta->fd_prot_mistake = false);
+
+ fd_frm_type_msk = fd_sta_msk & 0xBUL;
+
+ if (fd_frm_type_msk == 0xBUL) {
+ sta->fd_dat_frm = true;
+ sta->fd_acc_dat = true;
+ sta->fd_ext_dat = true;
+ } else {
+ (fd_frm_type_msk & 0x2UL) ? (sta->fd_dat_frm = true) : (sta->fd_dat_frm = false);
+ (fd_frm_type_msk & 0x1UL) ? (sta->fd_acc_dat = true) : (sta->fd_acc_dat = false);
+ (fd_frm_type_msk & 0x8UL) ? (sta->fd_ext_dat = true) : (sta->fd_ext_dat = false);
+ }
+
+ if (sta->fd_prot_mistake == true) {
+ return LL_ERROR;
+ }
+
+ if (fd_frm_type_msk != 0x2UL && fd_frm_type_msk != 0x3UL &&
+ fd_frm_type_msk != 0xaUL && fd_frm_type_msk != 0xbUL) {
+ return LL_ERROR;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief CAN Priority message status get
+ * @param Instance Specifies CAN peripheral
+ * @param sta Priority message status pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_PrioMsgSta_Get(CAN_TypeDef *Instance, CAN_PrioMsgStaTypeDef *sta)
+{
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(sta != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || sta == NULL) {
+ return LL_INVALID;
+ }
+
+ //Get priority message status
+ if (__LL_CAN_PrioMesgIDESta_Get(Instance)) {
+ sta->ext_frm_flag = true;
+ } else {
+ sta->ext_frm_flag = false;
+ }
+
+ sta->msg_store_mode = (CAN_FrmStoreModeETypeDef)__LL_CAN_PrioMesgBufSta_Get(Instance);
+ sta->accept_fil_num = (CAN_AcceptFilSlotETypeDef)__LL_CAN_PrioMesgAcceptSta_Get(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_LL_Exported_Functions_Group3 CAN Operation Functions
+ * @brief CAN Operation Functions
+ * @{
+ */
+
+/**
+ * @brief PTB transmit one frame in CPU blocking mode
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt Tx buffer format pointer
+ * @param buf Tx buffer pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_TransmitPTB_CPU(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ uint8_t dat_len;
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(buf_fmt != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || buf_fmt == NULL) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ } else if (can_hdl->tx_ctrl_ptb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] PTB Tx isn't in READY state, can't start Tx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check last frame transmit complete or not
+ if (__LL_CAN_TxPriEn_Get(Instance)) {
+ return LL_ERROR;
+ }
+
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_BUSY_TX;
+ can_hdl->tx_ctrl_ptb.isr = NULL;
+
+ //TX buffer select PTB
+ __LL_CAN_TxBufSel_PTB(Instance);
+
+ //Write buffer format data
+ __LL_CAN_TxBufReg_ID_Write(Instance, *((uint32_t *)buf_fmt));
+ __LL_CAN_TxBufReg_Ctrl_Write(Instance, *(((uint32_t *)buf_fmt) + 1));
+
+ //Write data to TX buffer
+ if (buf != NULL) {
+ dat_len = LL_CAN_DatLen_Get(Instance, buf_fmt->data_len_code);
+
+ for (uint32_t i = 0; i < (dat_len + 3) / 4; i++) {
+ __LL_CAN_TxBufReg_Data_Write(Instance, i, *buf++);
+ }
+ }
+
+ //TX primary enable
+ __LL_CAN_TxPriEn_Set(Instance);
+
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_READY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief STB transmit one frame in CPU blocking mode
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt Tx buffer format pointer
+ * @param buf Tx buffer pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_TransmitSTB_CPU(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ uint8_t dat_len;
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(buf_fmt != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || buf_fmt == NULL) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ } else if (can_hdl->tx_ctrl_stb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] STB Tx isn't in READY state, can't start Tx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check last frame transmit complete or not
+ if (__LL_CAN_TxSecOne_Get(Instance)) {
+ return LL_ERROR;
+ }
+
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_BUSY_TX;
+ can_hdl->tx_ctrl_stb.isr = NULL;
+
+ //TX buffer select STB
+ __LL_CAN_TxBufSel_STB(Instance);
+
+ //Write buffer format data
+ __LL_CAN_TxBufReg_ID_Write(Instance, *((uint32_t *)buf_fmt));
+ __LL_CAN_TxBufReg_Ctrl_Write(Instance, *(((uint32_t *)buf_fmt) + 1));
+
+ //Write data to TX buffer
+ if (buf != NULL) {
+ dat_len = LL_CAN_DatLen_Get(Instance, buf_fmt->data_len_code);
+
+ for (uint32_t i = 0; i < (dat_len + 3) / 4; i++) {
+ __LL_CAN_TxBufReg_Data_Write(Instance, i, *buf++);
+ }
+ }
+
+ //TX buffer Secondary next
+ __LL_CAN_TxSecNext_Set(Instance);
+
+ //TX secondary send one start
+ __LL_CAN_TxSecOne_Set(Instance);
+
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_READY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Receive one frame in CPU blocking mode
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt Rx buffer format pointer
+ * @param buf Rx buffer pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_Receive_CPU(CAN_TypeDef *Instance, CAN_RxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ } else if (can_hdl->rx_ctrl.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] Rx isn't in READY state, can't start Rx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ if (!__LL_CAN_IsRxIntPnd(Instance)) {
+ return LL_ERROR;
+ }
+
+ can_hdl->rx_ctrl.state = CAN_STATE_BUSY_RX;
+ can_hdl->rx_ctrl.isr = NULL;
+ can_hdl->rx_ctrl.buf = buf;
+ can_hdl->rx_ctrl.buf_fmt = buf_fmt;
+
+ //Clear Receive Interrupt Pending
+ __LL_CAN_RxIntPnd_Clr(Instance);
+
+ //Read data from RxFIFO
+ if (buf_fmt != NULL) {
+ *((uint32_t *)buf_fmt + 0) = __LL_CAN_RxBufReg_ID_Read(Instance);
+ *((uint32_t *)buf_fmt + 1) = __LL_CAN_RxBufReg_Ctrl_Read(Instance);
+
+ if (buf != NULL) {
+ memcpy((void *)buf, (void *)Instance->RBUFDT, LL_CAN_DatLen_Get(Instance, buf_fmt->data_len_code));
+ }
+ }
+
+ //RxFIFO Release(Clear)
+ __LL_CAN_RxBufRelease(Instance);
+
+ can_hdl->rx_ctrl.state = CAN_STATE_READY;
+
+ return LL_OK;
+
+}
+
+/**
+ * @brief SRB Receive one frame in CPU blocking mode
+ * @note Read one frame at a time, but only when there is data in the buffer.
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt Rx buffer format pointer
+ * @param buf Rx buffer pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_ReceiveSRB_CPU(CAN_TypeDef *Instance, CAN_RxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ CAN_HandleTypeDef *can_hdl;
+ uint32_t tickstart;
+ uint32_t buf_depth;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //Check whether this function is supported
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ LOG_E("The chip not support SRB!\n");
+ return LL_FAILED;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ } else if (can_hdl->rx_ctrl_srb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] SRB Rx isn't in READY state, can't start Rx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check Rx frame complete or not
+ if (!__LL_CAN_IsSRBRcvIntPnd(Instance)) {
+ return LL_ERROR;
+ }
+
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_BUSY_RX;
+ can_hdl->rx_ctrl_srb.isr = NULL;
+ can_hdl->rx_ctrl_srb.buf = buf;
+ can_hdl->rx_ctrl_srb.buf_fmt = buf_fmt;
+
+ if (buf_fmt != NULL) {
+ //Read data from SRB
+ *((uint32_t *)buf_fmt + 0) = __LL_CAN_SRBBufReg_ID_Read(Instance);
+ *((uint32_t *)buf_fmt + 1) = __LL_CAN_SRBBufReg_Ctrl_Read(Instance);
+
+ if (buf != NULL) {
+ memcpy((void *)buf, (void *)Instance->SBUFDT, LL_CAN_DatLen_Get(Instance, buf_fmt->data_len_code));
+ }
+
+ __LL_CAN_SRBBufRelease(Instance);
+ tickstart = LL_GetTick();
+ while (!__LL_CAN_IsSRBBufReleaseDone(Instance)) {
+ if ((LL_GetTick() - tickstart) > CAN_DEFAULT_TIMEOUT) {
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_READY;
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ return LL_TIMEOUT;
+ }
+ };
+ }
+
+ buf_depth = __LL_CAN_SRBRxBufSta_Get(Instance);
+
+ if (buf_depth < 3) {
+ if (__LL_CAN_IsSRBFullIntPnd(Instance)) {
+ __LL_CAN_SRBFullIntPnd_Clr(Instance);
+ }
+ }
+
+ if (buf_depth < 2) {
+ if (__LL_CAN_IsSRBAlmostFullIntPnd(Instance)) {
+ __LL_CAN_SRBAlmostFullIntPnd_Clr(Instance);
+ }
+ }
+
+ if (buf_depth == 0) {
+ if (__LL_CAN_IsSRBRcvIntPnd(Instance)) {
+ __LL_CAN_SRBRcvIntPnd_Clr(Instance);
+
+ }
+ }
+
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_READY;
+
+ return LL_OK;
+
+
+}
+
+/**
+ * @brief Get one frame from ETB in CPU blocking mode
+ * @note User must ensure that the bus does not enter transmission status
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt ETB Buffer format pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_GetTxEvent_CPU(CAN_TypeDef *Instance, CAN_TxEvtBufFormatTypeDef *buf_fmt)
+{
+ CAN_HandleTypeDef *can_hdl;
+ uint32_t tickstart;
+ uint32_t buf_depth;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if ((!IS_CAN_ALL_INSTANCE(Instance)) || (buf_fmt == NULL)) {
+ return LL_INVALID;
+ }
+
+ //Check whether this function is supported
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ LOG_E("The chip not support ETB!\n");
+ return LL_FAILED;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ } else if (can_hdl->tx_ctrl_ptb.state != CAN_STATE_READY || can_hdl->tx_ctrl_stb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] Tx isn't in READY state, can't transfer ETB!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ } else if (can_hdl->evt_ctrl_etb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] ETB isn't in READY state, can't transfer ETB!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check last frame transmit complete or not
+ if ((__LL_CAN_TxSecAll_Get(Instance)) || (__LL_CAN_TxPriEn_Get(Instance)) || (!__LL_CAN_IsETBRcvIntPnd(Instance))) {
+ return LL_ERROR;
+ }
+
+ //Tx should not be used while now
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_BUSY;
+ can_hdl->tx_ctrl_ptb.isr = NULL;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_BUSY;
+ can_hdl->tx_ctrl_stb.isr = NULL;
+
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_BUSY_RX;
+ can_hdl->evt_ctrl_etb.isr = NULL;
+ can_hdl->evt_ctrl_etb.buf = NULL;
+ can_hdl->evt_ctrl_etb.buf_fmt = buf_fmt;
+
+ //Read data from ETB
+ if (buf_fmt != NULL) {
+ *((uint32_t *)buf_fmt + 0) = __LL_CAN_ETBBufReg_ID_Read(Instance);
+ *((uint32_t *)buf_fmt + 1) = __LL_CAN_ETBBufReg_Data_Read(Instance);
+ }
+
+ //ETB Release(Clear)
+ __LL_CAN_ETBBufRelease(Instance);
+ tickstart = LL_GetTick();
+ while (!__LL_CAN_IsETBBufReleaseDone(Instance)) {
+ if ((LL_GetTick() - tickstart) > CAN_DEFAULT_TIMEOUT) {
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_READY;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_READY;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_READY;
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ return LL_TIMEOUT;
+ }
+ }
+
+ buf_depth = __LL_CAN_ETBRxBufSta_Get(Instance);
+
+ if (buf_depth < 3) {
+ if (__LL_CAN_IsETBFullIntPnd(Instance)) {
+ __LL_CAN_ETBFullIntPnd_Clr(Instance);
+ }
+ }
+
+ if (buf_depth < 2) {
+ if (__LL_CAN_IsETBAlmostFullIntPnd(Instance)) {
+ __LL_CAN_ETBAlmostFullIntPnd_Clr(Instance);
+ }
+ }
+
+ if (buf_depth == 0) {
+ if (__LL_CAN_IsETBRcvIntPnd(Instance)) {
+ __LL_CAN_ETBRcvIntPnd_Clr(Instance);
+
+ }
+ }
+
+ //Tx can be used while now
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_READY;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_READY;
+
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_READY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief PTB transmit one frame in non-blocking mode with Interrupt
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt Tx buffer format pointer
+ * @param buf Tx buffer pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_TransmitPTB_IT(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ uint8_t dat_len;
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(buf_fmt != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || buf_fmt == NULL) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ } else if (can_hdl->tx_ctrl_ptb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] PTB Tx isn't in READY state, can't start Tx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check last frame transmit complete or not
+ if (__LL_CAN_TxPriEn_Get(Instance)) {
+ return LL_ERROR;
+ }
+
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_BUSY_TX;
+ can_hdl->tx_ctrl_ptb.isr = CAN_TxISR_PTB;
+
+ //Clear Transmission Primary Interrupt Pending
+ __LL_CAN_TxPriIntPnd_Clr(Instance);
+
+ //TX buffer select PTB
+ __LL_CAN_TxBufSel_PTB(Instance);
+
+ //Write buffer format data
+ __LL_CAN_TxBufReg_ID_Write(Instance, *((uint32_t *)buf_fmt));
+ __LL_CAN_TxBufReg_Ctrl_Write(Instance, *(((uint32_t *)buf_fmt) + 1));
+
+ //Write data to TX buffer
+ if (buf != NULL) {
+ dat_len = LL_CAN_DatLen_Get(Instance, buf_fmt->data_len_code);
+
+ for (uint32_t i = 0; i < (dat_len + 3) / 4; i++) {
+ __LL_CAN_TxBufReg_Data_Write(Instance, i, *buf++);
+ }
+ }
+
+ //TX primary enable
+ __LL_CAN_TxPriEn_Set(Instance);
+
+ //Transmission Primary Interrupt Enable
+ __LL_CAN_TxPri_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief STB transmit one frame in non-blocking mode with Interrupt
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt Tx buffer format pointer
+ * @param buf Tx buffer pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_TransmitSTB_IT(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ uint8_t dat_len;
+ CAN_HandleTypeDef *can_hdl;
+ uint32_t tickstart;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(buf_fmt != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || buf_fmt == NULL) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ } else if (can_hdl->tx_ctrl_stb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] STB Tx isn't in READY state, can't start Tx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check last frame transmit complete or not
+ if (__LL_CAN_TxSecOne_Get(Instance)) {
+ return LL_ERROR;
+ }
+
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_BUSY_TX;
+ can_hdl->tx_ctrl_stb.isr = CAN_TxISR_STB;
+
+ //Clear Secondary Primary Interrupt Pending
+ __LL_CAN_TxSecIntPnd_Clr(Instance);
+
+ //TX buffer select STB
+ __LL_CAN_TxBufSel_STB(Instance);
+ tickstart = LL_GetTick();
+ while (__LL_CAN_IsTxBufSelPTB(Instance)) {
+ if ((LL_GetTick() - tickstart) > CAN_DEFAULT_TIMEOUT) {
+ LOG_E("<%s> Tx buffer swtich timeout! \n", __FUNCTION__);
+ return LL_TIMEOUT;
+ }
+ }
+
+ //Write buffer format data
+ __LL_CAN_TxBufReg_ID_Write(Instance, *((uint32_t *)buf_fmt));
+ __LL_CAN_TxBufReg_Ctrl_Write(Instance, *(((uint32_t *)buf_fmt) + 1));
+
+ //Write data to TX buffer
+ if (buf != NULL) {
+ dat_len = LL_CAN_DatLen_Get(Instance, buf_fmt->data_len_code);
+
+ for (uint32_t i = 0; i < (dat_len + 3) / 4; i++) {
+ __LL_CAN_TxBufReg_Data_Write(Instance, i, *buf++);
+ }
+ }
+
+ //TX buffer Secondary next
+ __LL_CAN_TxSecNext_Set(Instance);
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) {
+ tickstart = LL_GetTick();
+ while (__LL_CAN_TxSecNext_Get(Instance)) {
+ if ((LL_GetTick() - tickstart) > CAN_DEFAULT_TIMEOUT) {
+ LOG_E("<%s> STB buffer swtich timeout!\n", __FUNCTION__);
+ return LL_TIMEOUT;
+ }
+ }
+ }
+
+
+ //TX secondary send one start
+ __LL_CAN_TxSecOne_Set(Instance);
+
+ //Transmission Secondary Interrupt Enable
+ __LL_CAN_TxSec_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Receive one frame in non-blocking mode with Interrupt
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt Rx buffer format pointer
+ * @param buf Rx buffer pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_Receive_IT(CAN_TypeDef *Instance, CAN_RxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ } else if (can_hdl->rx_ctrl.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] Rx isn't in READY state, can't start Rx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->rx_ctrl.state = CAN_STATE_BUSY_RX;
+ can_hdl->rx_ctrl.isr = CAN_RxISR;
+ can_hdl->rx_ctrl.buf = buf;
+ can_hdl->rx_ctrl.buf_fmt = buf_fmt;
+
+ //Receive Interrupt Enable
+ __LL_CAN_Rx_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SRB Receive one frame in non-blocking mode with Interrupt
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt Rx buffer format pointer
+ * @param buf Rx buffer pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_ReceiveSRB_IT(CAN_TypeDef *Instance, CAN_RxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //Check whether this function is supported
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ LOG_E("The chip not support SRB!\n");
+ return LL_FAILED;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ } else if (can_hdl->rx_ctrl_srb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] SRB RX isn't in READY state, can't start Rx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_BUSY_RX;
+ can_hdl->rx_ctrl_srb.isr = CAN_RxISR_SRB;
+ can_hdl->rx_ctrl_srb.buf = buf;
+ can_hdl->rx_ctrl_srb.buf_fmt = buf_fmt;
+
+ //Receive Interrupt Enable
+ __LL_CAN_SRBRcv_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Transfer one frame from ETB in non-blocking mode with Interrupt
+ * @note User must ensure that the bus does not enter transmission status
+ * @param Instance Specifies CAN peripheral
+ * @param buf_fmt ETB buffer format pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_CAN_GetTxEvent_IT(CAN_TypeDef *Instance, CAN_TxEvtBufFormatTypeDef *buf_fmt)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if ((!IS_CAN_ALL_INSTANCE(Instance)) || (buf_fmt == NULL)) {
+ return LL_INVALID;
+ }
+
+ //Check whether this function is supported
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ LOG_E("The chip not support ETB!\n");
+ return LL_FAILED;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return LL_ERROR;
+ } else if (can_hdl->tx_ctrl_ptb.state != CAN_STATE_READY || can_hdl->tx_ctrl_stb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] Tx isn't in READY state, can't transfer ETB!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ } else if (can_hdl->evt_ctrl_etb.state != CAN_STATE_READY) {
+ LOG_E("This CAN[0x%08" PRIx32 "] ETB isn't in READY state, can't transfer ETB!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check last frame transmit complete or not
+ if ((__LL_CAN_TxSecOne_Get(Instance)) || (__LL_CAN_TxPriEn_Get(Instance))) {
+ return LL_ERROR;
+ }
+
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_BUSY_RX;
+ can_hdl->evt_ctrl_etb.isr = CAN_GetTxEvtISR_ETB;
+ can_hdl->evt_ctrl_etb.buf = NULL;
+ can_hdl->evt_ctrl_etb.buf_fmt = buf_fmt;
+
+ //Receive Interrupt Enable
+ __LL_CAN_ETBRcv_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_LL_Exported_Functions_Interrupt CAN Interrupt Handler and Callback
+ * @brief CAN Interrupt Handler and Callback
+ * @{
+ */
+
+/**
+ * @brief CAN IRQ Handler
+ * @param Instance Specifies CAN peripheral
+ * @note All interrupt pending will be reset immediately after a read access
+ * @return None
+ */
+void LL_CAN_IRQHandler(CAN_TypeDef *Instance)
+{
+ CAN_HandleTypeDef *can_hdl;
+ uint32_t int_en, int_pending;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return;
+ }
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return;
+ }
+
+ //All Interrupt Enalbe and Pending Get
+ int_en = __LL_CAN_AllIntEn_Get(Instance);
+ int_pending = __LL_CAN_AllIntPnd_Get(Instance);
+
+
+ //Rx Interrupt Handler
+ if ((int_en & CAN0_INTREN_RIE_Msk) && (int_pending & CAN0_INTRST_RIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_RxIntPnd_Clr(Instance);
+
+ if (can_hdl->rx_ctrl.isr) {
+ can_hdl->rx_ctrl.isr(Instance);
+ }
+
+ //Callback
+ LL_CAN_RxCallback(Instance);
+ }
+
+ //Rx Overrun Interrupt Handler
+ if ((int_en & CAN0_INTREN_ROIE_Msk) && (int_pending & CAN0_INTRST_ROIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_RxOverIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_RxOverCallback(Instance);
+ }
+
+ //Rx Full Interrupt Handler
+ if ((int_en & CAN0_INTREN_RFIE_Msk) && (int_pending & CAN0_INTRST_RFIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_RxFullIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_RxFullCallback(Instance);
+ }
+
+ //Rx Almost Full Interrupt Handler
+ if ((int_en & CAN0_INTREN_RAFIE_Msk) && (int_pending & CAN0_INTRST_RAFIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_RxAlmostFullIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_RxAlmostFullCallback(Instance);
+ }
+
+
+ //Transmission Primary Interrupt Handler
+ if ((int_en & CAN0_INTREN_TPIE_Msk) && (int_pending & CAN0_INTRST_TPIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_TxPriIntPnd_Clr(Instance);
+
+ if (can_hdl->tx_ctrl_ptb.isr) {
+ can_hdl->tx_ctrl_ptb.isr(Instance);
+ }
+
+ //Callback
+ LL_CAN_TxPriCallback(Instance);
+ }
+
+ //Transmission Secondary Interrupt Handler
+ if ((int_en & CAN0_INTREN_TSIE_Msk) && (int_pending & CAN0_INTRST_TSIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_TxSecIntPnd_Clr(Instance);
+
+ if (can_hdl->tx_ctrl_stb.isr) {
+ can_hdl->tx_ctrl_stb.isr(Instance);
+ }
+
+ //Callback
+ LL_CAN_TxSecCallback(Instance);
+ }
+
+
+ //Error Interrupt Handler
+ if ((int_en & CAN0_INTREN_EIE_Msk) && (int_pending & CAN0_INTRST_EIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_ErrIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_ErrCallback(Instance);
+ }
+
+ //Abort Interrupt Handler
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) {
+ if ((int_en & CAN0_INTREN_AIE_Msk) && (int_pending & CAN0_INTRST_AIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_AbortIntPnd_Clr(Instance);
+
+ //Status refresh
+ CAN_AbortISR(Instance);
+
+ //Callback
+ LL_CAN_AbortCallback(Instance);
+ }
+ } else {
+ if (int_pending & CAN0_INTRST_AIF_Msk) {
+ //Clear Interrupt Pending
+ __LL_CAN_AbortIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_AbortCallback(Instance);
+ }
+ }
+
+ //Error Passive Interrupt Handler
+ if ((int_en & CAN0_INTREN_EPIE_Msk) && (int_pending & CAN0_INTRST_EPIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_ErrPassiveIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_ErrPassiveCallback(Instance);
+ }
+
+ //Arbitration Lost Interrupt Handler
+ if ((int_en & CAN0_INTREN_ALIE_Msk) && (int_pending & CAN0_INTRST_ALIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_ArbLostIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_ArbLostCallback(Instance);
+ }
+
+ //Bus Error Interrupt Handler
+ if ((int_en & CAN0_INTREN_BEIE_Msk) && (int_pending & CAN0_INTRST_BEIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_BusErrIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_BusErrCallback(Instance);
+ }
+
+ //The following features are available for later versions
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ return;
+ }
+
+ //Error Counter Error Interrupt Handler
+ if ((int_en & CAN0_INTREN_ECIE_Msk) && (int_pending & CAN0_INTRST_ECIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_ErrCntIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_ErrCntCallback(Instance);
+ }
+
+ //ETB Receive Interrupt Handler
+ if ((int_en & CAN0_INTREN_ERIE_Msk) && (int_pending & CAN0_INTRST_ERIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_ETBRcvIntPnd_Clr(Instance);
+
+ if (can_hdl->evt_ctrl_etb.isr) {
+ can_hdl->evt_ctrl_etb.isr(Instance);
+ }
+
+ //Callback
+ LL_CAN_ETBRcvCallback(Instance);
+ }
+
+ //SRB Receive Interrupt Handler
+ if ((int_en & CAN0_INTREN_SRIE_Msk) && (int_pending & CAN0_INTRST_SRIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_SRBRcvIntPnd_Clr(Instance);
+
+ if (can_hdl->rx_ctrl_srb.isr) {
+ can_hdl->rx_ctrl_srb.isr(Instance);
+ }
+
+ //Callback
+ LL_CAN_SRBRcvCallback(Instance);
+ }
+
+ //ETB Almost Full Interrupt Handler
+ if ((int_en & CAN0_INTREN_EAFIE_Msk) && (int_pending & CAN0_INTRST_EAFIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_ETBAlmostFullIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_ETBAlmostFullCallback(Instance);
+ }
+
+ //ETB Full Interrupt Handler
+ if ((int_en & CAN0_INTREN_EFIE_Msk) && (int_pending & CAN0_INTRST_EFIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_ETBFullIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_ETBFullCallback(Instance);
+ }
+
+ //ETB Overflow Interrupt Handler
+ if ((int_en & CAN0_INTREN_EOIE_Msk) && (int_pending & CAN0_INTRST_EOIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_ETBOverIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_ETBOverCallback(Instance);
+ }
+
+ //SRB Almost Full Interrupt Handler
+ if ((int_en & CAN0_INTREN_SAFIE_Msk) && (int_pending & CAN0_INTRST_SAFIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_SRBAlmostFullIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_SRBAlmostFullCallback(Instance);
+ }
+
+ //SRB Full Interrupt Handler
+ if ((int_en & CAN0_INTREN_SFIE_Msk) && (int_pending & CAN0_INTRST_SFIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_SRBFullIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_SRBFullCallback(Instance);
+ }
+
+ //SRB Overflow Interrupt Handler
+ if ((int_en & CAN0_INTREN_SOIE_Msk) && (int_pending & CAN0_INTRST_SOIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_SRBOverIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_SRBOverCallback(Instance);
+ }
+
+ //Continuous Count Timeout Interrupt Handler
+ if ((int_en & CAN0_INTREN_CTOIE_Msk) && (int_pending & CAN0_INTRST_CTOIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_ContCntTimeoutIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_ContCntTimeoutCallback(Instance);
+ }
+
+ //ETB Timeout Interrupt Handler
+ if ((int_en & CAN0_INTREN_ETOIE_Msk) && (int_pending & CAN0_INTRST_ETOIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_ETBTimeoutIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_ETBTimeoutCallback(Instance);
+ }
+
+ //SRB Timeout Interrupt Handler
+ if ((int_en & CAN0_INTREN_STOIE_Msk) && (int_pending & CAN0_INTRST_STOIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_SRBTimeoutIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_SRBTimeoutCallback(Instance);
+ }
+
+ //PRB Timeout Interrupt Handler
+ if ((int_en & CAN0_INTREN_RTOIE_Msk) && (int_pending & CAN0_INTRST_RTOIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_PRBTimeoutIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_PRBTimeoutCallback(Instance);
+ }
+
+ //Timestamp Interrupt Handler
+ if ((int_en & CAN0_INTREN_TSCIE_Msk) && (int_pending & CAN0_INTRST_TSCIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_TimestampIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_TimestampCallback(Instance);
+ }
+
+ //Priority Message Interrupt Handler
+ if ((int_en & CAN0_INTREN_PMIE_Msk) && (int_pending & CAN0_INTRST_PMIF_Msk)) {
+ //Clear Interrupt Pending
+ __LL_CAN_PrioMesgIntPnd_Clr(Instance);
+
+ //Callback
+ LL_CAN_PrioMesgCallback(Instance);
+ }
+
+ //STB Almost Empty Interrupt Handler
+ if ((int_en & CAN0_INTREN_TAEIE_Msk) && (int_pending & CAN0_INTRST_TAEIF_Msk)) {
+ //Clear Interrupt Pending
+ //User should use STB to send message to clear this pending
+
+ //Callback
+ LL_CAN_STBAlmostEmptyCallback(Instance);
+ }
+
+ //STB Empty Interrupt Handler
+ if ((int_en & CAN0_INTREN_TEIE_Msk) && (int_pending & CAN0_INTRST_TEIF_Msk)) {
+ //Clear Interrupt Pending
+ //User should use STB to send message to clear this pending
+
+ //Callback
+ LL_CAN_STBEmptyCallback(Instance);
+ }
+}
+
+
+/**
+ * @brief STB Empty Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_STBEmptyCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_STBEmptyCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief STB Almost Empty Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_STBAlmostEmptyCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_STBAlmostEmptyCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Priority Message Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_PrioMesgCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_PrioMesgCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timestamp Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_TimestampCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_TimestampCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PRB Timeout Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_PRBTimeoutCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_PRBTimeoutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SRB Timeout Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_SRBTimeoutCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_SRBTimeoutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ETB Timeout Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ETBTimeoutCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ETBTimeoutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Continuous Count Timeout Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ContCntTimeoutCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ContCntTimeoutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SRB Overflow Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_SRBOverCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_SRBOverCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SRB Full Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_SRBFullCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_SRBFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SRB Almost Full Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_SRBAlmostFullCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_SRBAlmostFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ETB Overflow Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ETBOverCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ETBOverCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ETB Full Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ETBFullCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ETBFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ETB Almost Full Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ETBAlmostFullCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ETBAlmostFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SRB Receive Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_SRBRcvCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_SRBRcvCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ETB Receive Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ETBRcvCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ETBRcvCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error Counter Error Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ErrCntCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ErrCntCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN RX Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_RxCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_RxCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN RX Over Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_RxOverCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_RxOverCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN RX Full Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_RxFullCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_RxFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN RX Almost Full Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_RxAlmostFullCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_RxAlmostFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN TX Primary Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_TxPriCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_TxPriCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN TX Secondary Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_TxSecCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_TxSecCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN Error Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ErrCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ErrCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN Abort Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_AbortCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_AbortCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN Error Passive Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ErrPassiveCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ErrPassiveCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN Arbitration Lost Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_ArbLostCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_ArbLostCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief CAN Bus Error Interrupt Callback
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+__WEAK void LL_CAN_BusErrCallback(CAN_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_CAN_BusErrCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup CAN_LL_Private_Functions CAN LL Private Functions
+ * @brief CAN LL Private Functions
+ * @{
+ */
+
+/**
+ * @brief CAN Handle Get
+ * @param Instance Specifies CAN peripheral
+ * @return CAN_HandleTypeDef pointer
+ */
+static CAN_HandleTypeDef *CAN_Handle_Get(CAN_TypeDef *Instance)
+{
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (Instance == CAN0) {
+ return &can_hdl_global[CAN_INSTANCE_0];
+ } else if (Instance == CAN1) {
+ return &can_hdl_global[CAN_INSTANCE_1];
+ }
+
+ return NULL;
+}
+
+/**
+ * @brief CAN PTB transmit data handle in Interrupt mode
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+static void CAN_TxISR_PTB(CAN_TypeDef *Instance)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return;
+ }
+
+ //Transmission Primary Interrupt Disable
+ __LL_CAN_TxPri_INT_Dis(Instance);
+
+ can_hdl->tx_ctrl_ptb.isr = NULL;
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_READY;
+
+ if (can_hdl->user_callback.TxCpltCallback_ptb) {
+ can_hdl->user_callback.TxCpltCallback_ptb();
+ }
+}
+
+/**
+ * @brief CAN STB transmit data handle in Interrupt mode
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+static void CAN_TxISR_STB(CAN_TypeDef *Instance)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return;
+ }
+
+ //Transmission Secondary Interrupt Disable
+ __LL_CAN_TxSec_INT_Dis(Instance);
+
+ can_hdl->tx_ctrl_stb.isr = NULL;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_READY;
+
+ if (can_hdl->user_callback.TxCpltCallback_stb) {
+ can_hdl->user_callback.TxCpltCallback_stb();
+ }
+}
+
+/**
+ * @brief CAN receive data handle in Interrupt mode
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+static void CAN_RxISR(CAN_TypeDef *Instance)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return;
+ }
+
+ //Receive Interrupt Disable
+ __LL_CAN_Rx_INT_Dis(Instance);
+
+ //Read data from RxFIFO
+ if (can_hdl->rx_ctrl.buf_fmt != NULL) {
+ *((uint32_t *)can_hdl->rx_ctrl.buf_fmt + 0) = __LL_CAN_RxBufReg_ID_Read(Instance);
+ *((uint32_t *)can_hdl->rx_ctrl.buf_fmt + 1) = __LL_CAN_RxBufReg_Ctrl_Read(Instance);
+
+ if (can_hdl->rx_ctrl.buf != NULL) {
+ memcpy((void *)can_hdl->rx_ctrl.buf, (void *)Instance->RBUFDT,
+ LL_CAN_DatLen_Get(Instance, can_hdl->rx_ctrl.buf_fmt->data_len_code));
+ }
+ }
+
+ //RxFIFO Release(Clear)
+ __LL_CAN_RxBufRelease(Instance);
+
+ can_hdl->rx_ctrl.isr = NULL;
+ can_hdl->rx_ctrl.state = CAN_STATE_READY;
+
+ if (can_hdl->user_callback.RxCpltCallback) {
+ can_hdl->user_callback.RxCpltCallback();
+ }
+}
+
+/**
+ * @brief CAN SRB receive data handle in Interrupt mode
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+static void CAN_RxISR_SRB(CAN_TypeDef *Instance)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return;
+ }
+
+ if (can_hdl->rx_ctrl_srb.buf_fmt != NULL) {
+ //Receive Interrupt Disable
+ __LL_CAN_SRBRcv_INT_Dis(Instance);
+
+ //Read data from SRB
+ *((uint32_t *)can_hdl->rx_ctrl_srb.buf_fmt + 0) = __LL_CAN_SRBBufReg_ID_Read(Instance);
+ *((uint32_t *)can_hdl->rx_ctrl_srb.buf_fmt + 1) = __LL_CAN_SRBBufReg_Ctrl_Read(Instance);
+
+ if (can_hdl->rx_ctrl_srb.buf != NULL) {
+ memcpy((void *)can_hdl->rx_ctrl_srb.buf, (void *)Instance->SBUFDT,
+ LL_CAN_DatLen_Get(Instance, can_hdl->rx_ctrl_srb.buf_fmt->data_len_code));
+ }
+
+ __LL_CAN_SRBBufRelease(Instance);
+ }
+
+ can_hdl->rx_ctrl_srb.isr = NULL;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_READY;
+
+ if (can_hdl->user_callback.RxCpltCallback_srb) {
+ can_hdl->user_callback.RxCpltCallback_srb();
+ }
+}
+
+
+/**
+ * @brief CAN ETB get Tx event handle in Interrupt mode
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+static void CAN_GetTxEvtISR_ETB(CAN_TypeDef *Instance)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return;
+ }
+
+ //Receive Interrupt Disable
+ __LL_CAN_ETBRcv_INT_Dis(Instance);
+
+ //Read data from ETB
+ if (can_hdl->evt_ctrl_etb.buf_fmt != NULL) {
+ *((uint32_t *)can_hdl->evt_ctrl_etb.buf_fmt + 0) = __LL_CAN_ETBBufReg_ID_Read(Instance);
+ *((uint32_t *)can_hdl->evt_ctrl_etb.buf_fmt + 1) = __LL_CAN_ETBBufReg_Data_Read(Instance);
+ }
+
+ //ETB Release(Clear)
+ __LL_CAN_ETBBufRelease(Instance);
+
+ can_hdl->evt_ctrl_etb.isr = NULL;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_READY;
+
+ if (can_hdl->user_callback.TxEvtCpltCallback_etb) {
+ can_hdl->user_callback.TxEvtCpltCallback_etb();
+ }
+}
+
+/**
+ * @brief CAN Abort handle in Interrupt mode
+ * @param Instance Specifies CAN peripheral
+ * @return None
+ */
+static void CAN_AbortISR(CAN_TypeDef *Instance)
+{
+ CAN_HandleTypeDef *can_hdl;
+
+ //CAN handle get
+ can_hdl = CAN_Handle_Get(Instance);
+
+ if (can_hdl == NULL) {
+ LOG_E("Get CAN handle error!\n");
+ return;
+ }
+
+ can_hdl->tx_ctrl_ptb.state = CAN_STATE_ABORT;
+ can_hdl->tx_ctrl_stb.state = CAN_STATE_ABORT;
+ can_hdl->rx_ctrl.state = CAN_STATE_ABORT;
+ can_hdl->rx_ctrl_srb.state = CAN_STATE_ABORT;
+ can_hdl->evt_ctrl_etb.state = CAN_STATE_ABORT;
+}
+
+/**
+ * @brief CAN acceptance filter reset
+ * @param Instance Specifies CAN peripheral
+ * @param slot Acceptance filter slot
+ * @return Reset result
+ */
+static LL_StatusETypeDef CAN_AcceptFilRst(CAN_TypeDef *Instance, CAN_AcceptFilSlotETypeDef slot)
+{
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(slot < CAN_ACCEPT_FILT_SLOT_NUMS);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || slot >= CAN_ACCEPT_FILT_SLOT_NUMS) {
+ return LL_INVALID;
+ }
+
+ //Check in reset status or not
+ if (!__LL_CAN_ResetSta_Get(Instance)) {
+ LOG_E("Acceptance filter register can config in reset status only!\n");
+ return LL_ERROR;
+ }
+
+ //CAN acceptance filter Code and Mask config
+ __LL_CAN_AcceptFilAddr_Set(Instance, slot);
+ __LL_CAN_AcceptFilContentSel_Mask(Instance);
+ __LL_CAN_AcceptFilCodeOrMaskVal_Set(Instance, 0);
+ __LL_CAN_AcceptFilRxFrm_Set(Instance, CAN_ACCEPT_FILT_FRM_STD_EXT);
+ __LL_CAN_AcceptFilContentSel_Code(Instance);
+ __LL_CAN_AcceptFilCodeOrMaskVal_Set(Instance, 0);
+
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) {
+ __LL_CAN_AcceptMode_Set(Instance, CAN_ACCEPT_MODE_AND);
+ __LL_CAN_AcceptCtrl_Set(Instance, CAN_ACCEPT_CTRL_STORE_PRB);
+ }
+
+ //CAN acceptance filter disable
+ __LL_CAN_AcceptFil_Dis(Instance, ((uint8_t)slot));
+
+ return LL_OK;
+}
+
+/**
+ * @brief CAN acceptance filter config
+ * @param Instance Specifies CAN peripheral
+ * @param fil_cfg filter config pointer
+ * @return Config result
+ */
+static LL_StatusETypeDef CAN_AcceptFilCfg(CAN_TypeDef *Instance, CAN_AcceptFilCfgTypeDef *fil_cfg)
+{
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(fil_cfg != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || fil_cfg == NULL) {
+ return LL_INVALID;
+ }
+
+ //Check in reset status or not
+ if (!__LL_CAN_ResetSta_Get(Instance)) {
+ LOG_E("Acceptance filter register can config in reset status only!\n");
+ return LL_ERROR;
+ }
+
+ //CAN acceptance filter Code and Mask config
+ __LL_CAN_AcceptFilAddr_Set(Instance, fil_cfg->slot);
+ __LL_CAN_AcceptFilContentSel_Mask(Instance);
+ __LL_CAN_AcceptFilCodeOrMaskVal_Set(Instance, fil_cfg->mask_val);
+ __LL_CAN_AcceptFilRxFrm_Set(Instance, fil_cfg->rx_frm);
+ __LL_CAN_AcceptFilContentSel_Code(Instance);
+ __LL_CAN_AcceptFilCodeOrMaskVal_Set(Instance, fil_cfg->code_val);
+
+ if ((__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) && (LL_IsExtCfgEnGrp(LL_EXT_CFG_GRP_MASK_CAN))) {
+ if (fil_cfg->ex_cfg_no_default) {
+ __LL_CAN_AcceptMode_Set(Instance, fil_cfg->ex_cfg_mode);
+ __LL_CAN_AcceptCtrl_Set(Instance, fil_cfg->ex_cfg_ctrl);
+ } else {
+ __LL_CAN_AcceptMode_Set(Instance, CAN_ACCEPT_MODE_AND);
+ __LL_CAN_AcceptCtrl_Set(Instance, CAN_ACCEPT_CTRL_STORE_PRB);
+ }
+ }
+
+ //CAN acceptance filter enable
+ __LL_CAN_AcceptFil_En(Instance, ((uint8_t)fil_cfg->slot));
+
+ return LL_OK;
+}
+
+/**
+ * @brief CAN Global filter reset
+ * @param Instance Specifies CAN peripheral
+ * @return Reset result
+ */
+static LL_StatusETypeDef CAN_GlobalFilRst(CAN_TypeDef *Instance)
+{
+ CAN_LLCfgTypeDef const *ll_cfg = &can_ll_cfg_def;
+
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+
+ if (!IS_CAN_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //Check in reset status or not
+ if (!__LL_CAN_ResetSta_Get(Instance)) {
+ LOG_E("Global filter register can config in reset status only!\n");
+ return LL_ERROR;
+ }
+
+ //Check whether the config is supported
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ LOG_E("The chip not support global filter reset!\n");
+ return LL_FAILED;
+ }
+
+ //CAN Global filter config
+ __LL_CAN_PRBWorkMode_Set(Instance, ll_cfg->global_fil.prb_work_mode);
+ __LL_CAN_SRBWorkMode_Set(Instance, ll_cfg->global_fil.srb_work_mode);
+ __LL_CAN_ExtIdMask_Set(Instance, ll_cfg->global_fil.ext_id_mask);
+ LL_FUNC_ALTER(ll_cfg->global_fil.rej_std_remote_frm, __LL_CAN_StdRmtFrmRjct_En(Instance), __LL_CAN_StdRmtFrmRjct_Dis(Instance));
+ LL_FUNC_ALTER(ll_cfg->global_fil.rej_ext_remote_frm, __LL_CAN_ExtRmtFrmRjct_En(Instance), __LL_CAN_ExtRmtFrmRjct_Dis(Instance));
+
+ return LL_OK;
+}
+
+/**
+ * @brief CAN Global filter config
+ * @param Instance Specifies CAN peripheral
+ * @param fil_cfg Global config pointer
+ * @return Config result
+ */
+static LL_StatusETypeDef CAN_GlobalFilCfg(CAN_TypeDef *Instance, CAN_GlobalFilCfgTypeDef *fil_cfg)
+{
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(fil_cfg != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || fil_cfg == NULL) {
+ return LL_INVALID;
+ }
+
+ //Check in reset status or not
+ if (!__LL_CAN_ResetSta_Get(Instance)) {
+ LOG_E("Global filter register can config in reset status only!\n");
+ return LL_ERROR;
+ }
+
+ //Check whether the config is supported
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ LOG_E("The chip not support global filter config!\n");
+ return LL_FAILED;
+ }
+
+ //CAN Global config
+ __LL_CAN_PRBWorkMode_Set(Instance, fil_cfg->prb_work_mode);
+ __LL_CAN_SRBWorkMode_Set(Instance, fil_cfg->srb_work_mode);
+ __LL_CAN_ExtIdMask_Set(Instance, fil_cfg->ext_id_mask);
+ LL_FUNC_ALTER(fil_cfg->rej_std_remote_frm, __LL_CAN_StdRmtFrmRjct_En(Instance), __LL_CAN_StdRmtFrmRjct_Dis(Instance));
+ LL_FUNC_ALTER(fil_cfg->rej_ext_remote_frm, __LL_CAN_ExtRmtFrmRjct_En(Instance), __LL_CAN_ExtRmtFrmRjct_Dis(Instance));
+
+ return LL_OK;
+}
+
+/**
+ * @brief CAN Timestamp counter config
+ * @param Instance Specifies CAN peripheral
+ * @param cntr_cfg Timestamp counter pointer
+ * @return Config result
+ */
+static LL_StatusETypeDef CAN_TimeCounterCfg(CAN_TypeDef *Instance, CAN_TimeCntrCfgTypeDef *cntr_cfg)
+{
+ //Assert param
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(cntr_cfg != NULL);
+
+ if (!IS_CAN_ALL_INSTANCE(Instance) || cntr_cfg == NULL) {
+ return LL_INVALID;
+ }
+
+ if (cntr_cfg->base_ctl.timebase_type != CAN_TIMESTAMP_TIMEBASE_CLOSE &&
+ cntr_cfg->base_ctl.timebase_type != CAN_TIMESTAMP_TIMEBASE_INT_TSC &&
+ cntr_cfg->base_ctl.timebase_type != CAN_TIMESTAMP_TIMEBASE_EXT_TMR0 &&
+ cntr_cfg->base_ctl.timebase_type != CAN_TIMESTAMP_TIMEBASE_EXT_TMR1 &&
+ cntr_cfg->base_ctl.timebase_type != CAN_TIMESTAMP_TIMEBASE_EXT_TMR2) {
+ return LL_INVALID;
+ }
+
+ //Check whether the config is supported
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ LOG_E("The chip not support Timestamp counter config!\n");
+ return LL_FAILED;
+ }
+
+ //CAN Timestamp Counter config
+ __LL_CAN_TimestampTimebase_Set(Instance, cntr_cfg->base_ctl.timebase_type);
+ __LL_CAN_TimestampPrescaler_Set(Instance, cntr_cfg->base_ctl.timestamp_prescaler);
+
+ //PRB Timeout Counter config
+ __LL_CAN_PRBTimeoutPeriod_Set(Instance, cntr_cfg->prb_timeout_cntr.period);
+ LL_FUNC_ALTER(cntr_cfg->prb_timeout_cntr.cnt_enable, __LL_CAN_PRBTimeout_En(Instance), __LL_CAN_PRBTimeout_Dis(Instance));
+ LL_FUNC_ALTER(cntr_cfg->prb_timeout_cntr.int_enable, __LL_CAN_PRBTimeout_INT_En(Instance), __LL_CAN_PRBTimeout_INT_Dis(Instance));
+
+ //SRB Timeout Counter config
+ __LL_CAN_SRBTimeoutPeriod_Set(Instance, cntr_cfg->srb_timeout_cntr.period);
+ LL_FUNC_ALTER(cntr_cfg->srb_timeout_cntr.cnt_enable, __LL_CAN_SRBTimeout_En(Instance), __LL_CAN_SRBTimeout_Dis(Instance));
+ LL_FUNC_ALTER(cntr_cfg->srb_timeout_cntr.int_enable, __LL_CAN_SRBTimeout_INT_En(Instance), __LL_CAN_SRBTimeout_INT_Dis(Instance));
+
+ //ETB Timeout Counter config
+ __LL_CAN_ETBTimeoutPeriod_Set(Instance, cntr_cfg->etb_timeout_cntr.period);
+ LL_FUNC_ALTER(cntr_cfg->etb_timeout_cntr.cnt_enable, __LL_CAN_ETBTimeout_En(Instance), __LL_CAN_ETBTimeout_Dis(Instance));
+ LL_FUNC_ALTER(cntr_cfg->etb_timeout_cntr.int_enable, __LL_CAN_ETBTimeout_INT_En(Instance), __LL_CAN_ETBTimeout_INT_Dis(Instance));
+
+ //Continuous Count Timeout Counter config
+ __LL_CAN_ContTimeoutPeriod_Set(Instance, cntr_cfg->cont_timeout_cntr.period);
+ LL_FUNC_ALTER(cntr_cfg->cont_timeout_cntr.cnt_enable, __LL_CAN_ContCntTimeout_En(Instance), __LL_CAN_ContCntTimeout_Dis(Instance));
+ LL_FUNC_ALTER(cntr_cfg->cont_timeout_cntr.int_enable, __LL_CAN_ContCntTimeout_INT_En(Instance), __LL_CAN_ContCntTimeout_INT_Dis(Instance));
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+#endif /* LL_CAN_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_cmp.c b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_cmp.c
new file mode 100644
index 0000000000..3fcb7b7f23
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_cmp.c
@@ -0,0 +1,365 @@
+/**
+ ******************************************************************************
+ * @file tae32g58xx_ll_cmp.c
+ * @author MCD Application Team
+ * @brief CMP LL module driver
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+
+
+#define DBG_TAG "I2C LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae_dbg.h"
+
+
+/** @addtogroup TAE32G58xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup I2C_LL I2C LL
+ * @brief I2C LL module driver
+ * @{
+ */
+
+#ifdef LL_I2C_MODULE_ENABLED
+
+/* Private Constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C LL Private Constants
+ * @brief I2C LL Private Constants
+ * @{
+ */
+
+/**
+ * @brief I2C Defaul Timeout definition in ms Unit
+ */
+#define I2C_DEFAULT_TIMEOUT (25)
+
+/**
+ * @brief I2C Slave Wait for Master Start Timeout definition in ms Unit
+ * @note Only use in Interrupt and DMA transmit mode
+ */
+#define I2C_SLV_WAIT_FOR_MST_START_TIMEOUT (30000)
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------*/
+/* Private Types -------------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Types I2C LL Private Types
+ * @brief I2C LL Private Types
+ * @{
+ */
+
+/**
+ * @brief I2C IRQ callback function type definition
+ */
+typedef void (*I2C_LLIRQCallback)(I2C_TypeDef *Instance);
+
+/**
+ * @brief I2C Transmission definition
+ */
+typedef struct __I2C_TransTypeDef {
+ uint8_t *buf; /*!< I2C Transmission Buffer Pointer */
+ uint16_t size; /*!< I2C Transmission Buffer Size */
+ uint16_t cnt; /*!< I2C Transmission Counter */
+ I2C_LLIRQCallback isr; /*!< Interrupt Service Routine */
+ I2C_StateETypeDef state; /*!< I2C Transmission State */
+#ifdef LL_DMA_MODULE_ENABLED
+ DMA_ChannelETypeDef dma_ch; /*!< I2C Transmission DMA Channel */
+#endif
+} I2C_TransTypeDef;
+
+/**
+ * @brief I2C handle Structure definition
+ */
+typedef struct __I2C_HandleTypeDef {
+ I2C_RoleETypeDef role; /*!< I2C role */
+
+ volatile I2C_TransTypeDef tx_ctrl; /*!< I2C Transmission Tx Control */
+ volatile I2C_TransTypeDef rx_ctrl; /*!< I2C Transmission Rx Control */
+
+ I2C_UserCallbackTypeDef user_callback; /*!< User Callback */
+} I2C_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Private Variables ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Variables I2C LL Private Variables
+ * @brief I2C LL Private Variables
+ * @{
+ */
+
+/**
+ * @brief Default I2C LL Config
+ */
+static const I2C_LLCfgTypeDef i2c_ll_cfg_def = {
+ .tx_fifo_empty_thres = 0, // 0~15
+ .rx_fifo_full_thres = 1, // 1~16
+ .mst_tmext_timing = 0x4f,
+ .slv_tsext_timing = 0x7a2,
+ .rcv_clk_strch_en = false,
+ .rcv_clk_strch_mode = I2C_RCV_CLK_STRCH_MODE_NON_EMPTY,
+ .slv_opt_addr_en = false,
+ .slv_opt_addr = 0,
+ .slv_opt_addr_mask = 0,
+ .timing_cfg_en = true,
+ .timing_cfg_auto_set = false,
+ .spike_suppr_limit = 0,
+ .slv_data_setup_time = 0x18,
+ .data_setup_time = 0,
+ .data_hold_time = 2,
+};
+
+/**
+ * @brief I2C Handle global variable
+ */
+static I2C_HandleTypeDef i2c_hdl_global[I2C_INSTANCE_NUMS];
+
+/**
+ * @}
+ */
+
+
+/* Private Function Prototypes -----------------------------------------------*/
+/** @defgroup I2C_LL_Private_Functions I2C LL Private Functions
+ * @brief I2C LL Private Functions
+ * @{
+ */
+static I2C_HandleTypeDef *I2C_Handle_Get(I2C_TypeDef *Instance);
+
+static void I2C_Read_ISR(I2C_TypeDef *Instance);
+static void I2C_Write_ISR(I2C_TypeDef *Instance);
+
+#ifdef LL_DMA_MODULE_ENABLED
+ static DMA_ChannelETypeDef I2C_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg);
+ static void I2C_DMA_DeInit(DMA_ChannelETypeDef ch);
+ static void I2C_Write_DMACplt(I2C_TypeDef *Instance);
+ static void I2C_Read_DMACplt(I2C_TypeDef *Instance);
+ static void I2C_Write_DMAHalfCplt(I2C_TypeDef *Instance);
+ static void I2C_Read_DMAHalfCplt(I2C_TypeDef *Instance);
+ static void I2C_Write_DMAError(I2C_TypeDef *Instance);
+ static void I2C_Read_DMAError(I2C_TypeDef *Instance);
+#endif
+/**
+ * @}
+ */
+
+
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Functions I2C LL Exported Functions
+ * @brief I2C LL Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_LL_Exported_Functions_Group1 I2C Init and DeInit Functions
+ * @brief I2C Init and DeInit Functions
+ * @{
+ */
+
+/**
+ * @brief I2C LL Init
+ * @param Instance Specifies I2C peripheral
+ * @param user_cfg user config pointer
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_I2C_Init(I2C_TypeDef *Instance, I2C_UserCfgTypeDef *user_cfg)
+{
+ bool dcn_3_is = false;
+ uint32_t baudrate_cnt;
+ I2C_HandleTypeDef *i2c_hdl;
+ I2C_LLCfgTypeDef *ll_cfg;
+ uint32_t spk_pclk_cnt;
+ volatile double hold_pclk_tmp;
+ uint32_t hold_pclk_cnt;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(user_cfg != NULL);
+ assert_param(user_cfg->baudrate);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || user_cfg == NULL || !user_cfg->baudrate) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->tx_ctrl.state != I2C_STATE_RESET || i2c_hdl->rx_ctrl.state != I2C_STATE_RESET) {
+ LOG_E("This I2C[0x%08" PRIx32 "] is being used!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ i2c_hdl->tx_ctrl.state = I2C_STATE_BUSY;
+ i2c_hdl->rx_ctrl.state = I2C_STATE_BUSY;
+
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) {
+ dcn_3_is = true;
+ }
+
+ //LL config pointer config
+ LL_FUNC_ALTER(user_cfg->ll_cfg == NULL, ll_cfg = (I2C_LLCfgTypeDef *)&i2c_ll_cfg_def, ll_cfg = user_cfg->ll_cfg);
+ baudrate_cnt = LL_RCU_APB0ClkGet() / user_cfg->baudrate / 2;
+
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_I2C_MspInit(Instance);
+
+ //Module disable and TX/RX FIFO reset
+ __LL_I2C_Disable(Instance);
+ __LL_I2C_TxFIFO_Reset(Instance);
+ __LL_I2C_RxFIFO_Reset(Instance);
+
+ //LL Config
+ __LL_I2C_TxFIFOEmptyThres_Set(Instance, ll_cfg->tx_fifo_empty_thres);
+ __LL_I2C_RxFIFOFullThres_Set(Instance, ll_cfg->rx_fifo_full_thres);
+ __LL_I2C_MST_TmextTiming_Set(Instance, ll_cfg->mst_tmext_timing);
+ __LL_I2C_SLV_TsextTiming_Set(Instance, ll_cfg->slv_tsext_timing);
+
+ if (dcn_3_is && (LL_IsExtCfgEnGrp(LL_EXT_CFG_GRP_MASK_I2C))) {
+ __LL_I2C_RxDatSCLStrchMode_Set(Instance, ll_cfg->rcv_clk_strch_mode);
+ if (user_cfg->role == I2C_ROLE_SLAVE) {
+ __LL_I2C_SLV_SCLStrchDis_Release(Instance);
+ }
+
+ LL_FUNC_ALTER(ll_cfg->rcv_clk_strch_en == true, __LL_I2C_RxDatSCLStrch_En(Instance), __LL_I2C_RxDatSCLStrch_Dis(Instance));
+
+ __LL_I2C_SLV_OptSlvAddr_Set(Instance, ll_cfg->slv_opt_addr);
+ __LL_I2C_SLV_OptSlvAddrMask_Set(Instance, ll_cfg->slv_opt_addr_mask);
+ LL_FUNC_ALTER(ll_cfg->slv_opt_addr_en == true, __LL_I2C_SLV_OptSlvAddr_En(Instance), __LL_I2C_SLV_OptSlvAddr_Dis(Instance));
+ }
+
+ //User Config
+ if (!dcn_3_is) {
+ LL_FUNC_ALTER(user_cfg->role == I2C_ROLE_MASTER, __LL_I2C_MasterRole_Set(Instance), __LL_I2C_SlaveRole_Set(Instance));
+ }
+
+ LL_FUNC_ALTER(user_cfg->addr_mode == I2C_ADDR_7BIT, __LL_I2C_7bAddr_Set(Instance), __LL_I2C_10bAddr_Set(Instance));
+ __LL_I2C_SCLHighLowCnt_Set(Instance, baudrate_cnt, baudrate_cnt);
+ __LL_I2C_SLV_SAR_Set(Instance, user_cfg->slave_addr);
+
+ if (ll_cfg->timing_cfg_en) {
+ if (dcn_3_is) {
+ if (ll_cfg->timing_cfg_auto_set) {
+ spk_pclk_cnt = 50UL / (1000000000UL / LL_RCU_APB0ClkGet());
+ if (spk_pclk_cnt >= 0x05UL) {
+ __LL_I2C_SpikeSupprLimit_Set(Instance, 0x05UL);
+ spk_pclk_cnt = 5;
+ } else {
+ __LL_I2C_SpikeSupprLimit_Set(Instance, (spk_pclk_cnt > (baudrate_cnt - 1)) ? (baudrate_cnt - 1) : (spk_pclk_cnt));
+ }
+
+ hold_pclk_tmp = (((double)LL_RCU_APB0ClkGet()) / ((double)user_cfg->baudrate) / 2.0 - (4.0 + spk_pclk_cnt)) * 1000.0 / 3.0;
+ hold_pclk_tmp = hold_pclk_tmp / 1000.0;
+ hold_pclk_cnt = (hold_pclk_tmp > 0) ? hold_pclk_tmp : (LL_RCU_APB0ClkGet() / user_cfg->baudrate / 6);
+ if ((hold_pclk_cnt - 1) >= 0xffUL) {
+ __LL_I2C_TxTransmitDelay_Set(Instance, 0xffUL);
+ __LL_I2C_RxCaptureDelay_Set(Instance, 0xffUL);
+ } else {
+ __LL_I2C_TxTransmitDelay_Set(Instance, hold_pclk_cnt - 1);
+ __LL_I2C_RxCaptureDelay_Set(Instance, hold_pclk_cnt - 1);
+ }
+ __LL_I2C_SCLHighLowCnt_Set(Instance, hold_pclk_cnt * 3 , hold_pclk_cnt);
+
+ __LL_I2C_SLV_TxTransmitDelay_Set(Instance, i2c_ll_cfg_def.slv_data_setup_time);
+
+ } else {
+ __LL_I2C_SpikeSupprLimit_Set(Instance, ll_cfg->spike_suppr_limit);
+ __LL_I2C_SLV_TxTransmitDelay_Set(Instance, ll_cfg->slv_data_setup_time);
+ __LL_I2C_RxCaptureDelay_Set(Instance, ll_cfg->data_setup_time);
+ __LL_I2C_TxTransmitDelay_Set(Instance, ll_cfg->data_hold_time);
+ }
+ } else {
+ //Data Hold Time Config to Fix Slave Timing
+ __LL_I2C_TxTransmitDelay_Set(Instance, 2);
+ }
+ }
+
+ //All Interrupt Pending Clear
+ __LL_I2C_AllIntPnd_Clr(Instance);
+
+ //I2C Enable
+ __LL_I2C_Enable(Instance);
+
+ //I2C Handle Init
+ if (dcn_3_is) {
+ //This parameter does not update in real-time and requires manual updating by the user
+ i2c_hdl->role = (I2C_RoleETypeDef)__LL_I2C_CurrRole_Get(Instance);
+ } else {
+ i2c_hdl->role = user_cfg->role;
+ }
+
+ i2c_hdl->tx_ctrl.state = I2C_STATE_READY;
+ i2c_hdl->rx_ctrl.state = I2C_STATE_READY;
+ i2c_hdl->user_callback = user_cfg->user_callback;
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C LL DeInit
+ * @param Instance Specifies I2C peripheral
+ * @return Status of the DeInitialization
+ */
+LL_StatusETypeDef LL_I2C_DeInit(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if (!IS_I2C_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->tx_ctrl.state == I2C_STATE_BUSY_TX || i2c_hdl->rx_ctrl.state == I2C_STATE_BUSY_RX) {
+ LOG_E("This I2C[0x%08" PRIx32 "] is being used!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ i2c_hdl->tx_ctrl.state = I2C_STATE_BUSY;
+ i2c_hdl->rx_ctrl.state = I2C_STATE_BUSY;
+
+ //I2C Module Disable
+ __LL_I2C_Disable(Instance);
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_I2C_MspDeInit(Instance);
+
+ memset((void *)i2c_hdl, 0, sizeof(I2C_HandleTypeDef));
+ i2c_hdl->tx_ctrl.state = I2C_STATE_RESET;
+ i2c_hdl->rx_ctrl.state = I2C_STATE_RESET;
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C LL Reset
+ * @param Instance Specifies I2C peripheral
+ * @return Status of the Reset
+ */
+LL_StatusETypeDef LL_I2C_Reset(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+ IRQn_Type irq_num;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if (!IS_I2C_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ }
+
+ irq_num = GET_I2C_IRQ_NUMBER(Instance);
+ if (irq_num < 0) {
+ LOG_E("I2C IRQ does not exist!\n");
+ return LL_ERROR;
+ }
+
+ //Clear pending and interrupt disable
+ __disable_irq();
+ __LL_I2C_Disable(Instance);
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) {
+ CLEAR_BIT(Instance->INTREN, 0xffffffUL);
+ SET_BIT(Instance->INTR, 0xbffffcUL);
+ } else {
+ CLEAR_BIT(Instance->INTREN, 0x7fffffUL);
+ SET_BIT(Instance->INTR, 0x3ffffcUL);
+ }
+ NVIC_ClearPendingIRQ(irq_num);
+ NVIC_DisableIRQ(irq_num);
+ __enable_irq();
+
+ i2c_hdl->tx_ctrl.state = I2C_STATE_BUSY;
+ i2c_hdl->rx_ctrl.state = I2C_STATE_BUSY;
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_I2C_MspDeInit(Instance);
+
+ memset((void *)i2c_hdl, 0, sizeof(I2C_HandleTypeDef));
+ i2c_hdl->tx_ctrl.state = I2C_STATE_RESET;
+ i2c_hdl->rx_ctrl.state = I2C_STATE_RESET;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the I2C MSP
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_MspInit(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the I2C MSP
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_MspDeInit(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Register an User I2C Callback
+ * @note User can register callback only in I2C Ready State
+ * @param Instance Specifies I2C peripheral
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_RegisterCallback(I2C_TypeDef *Instance, I2C_UserCallbackIdETypeDef CallbackID, I2C_UserCallback pCallback)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if (!IS_I2C_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Check callback pointer valid or not
+ if (pCallback == NULL) {
+ LOG_E("The callback pointer which to be registered is NULL!\n");
+ return LL_INVALID;
+ }
+
+ //Register user callback
+ switch (CallbackID) {
+ case I2C_TX_CPLT_CB_ID:
+ if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx isn't in Ready state, can't register Tx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ i2c_hdl->user_callback.TxCpltCallback = pCallback;
+ break;
+
+ case I2C_RX_CPLT_CB_ID:
+ if (i2c_hdl->rx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ i2c_hdl->user_callback.RxCpltCallback = pCallback;
+ break;
+
+ case I2C_TX_HALF_CPLT_CB_ID:
+ if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx isn't in Ready state, can't register Tx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ i2c_hdl->user_callback.TxHalfCpltCallback = pCallback;
+ break;
+
+ case I2C_RX_HALF_CPLT_CB_ID:
+ if (i2c_hdl->rx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Rx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ i2c_hdl->user_callback.RxHalfCpltCallback = pCallback;
+ break;
+
+ case I2C_ERROR_CB_ID:
+ if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY || i2c_hdl->rx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx&Rx are both not in Ready state, can't register Error callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ i2c_hdl->user_callback.ErrorCallback = pCallback;
+ break;
+
+ default:
+ LOG_E("I2C user callback ID-[%d] is Invalid!\n", CallbackID);
+ return LL_INVALID;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief UnRegister an User I2C Callback
+ * @note User can unregister callback only in I2C Ready State
+ * @param Instance Specifies I2C peripheral
+ * @param CallbackID ID of the callback to be unregistered
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_UnRegisterCallback(I2C_TypeDef *Instance, I2C_UserCallbackIdETypeDef CallbackID)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if (!IS_I2C_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ }
+
+ //UnRegister user callback
+ switch (CallbackID) {
+ case I2C_TX_CPLT_CB_ID:
+ if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx isn't in Ready state, can't unregister Tx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ i2c_hdl->user_callback.TxCpltCallback = NULL;
+ break;
+
+ case I2C_RX_CPLT_CB_ID:
+ if (i2c_hdl->rx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ i2c_hdl->user_callback.RxCpltCallback = NULL;
+ break;
+
+ case I2C_TX_HALF_CPLT_CB_ID:
+ if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx isn't in Ready state, can't unregister Tx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ i2c_hdl->user_callback.TxHalfCpltCallback = NULL;
+ break;
+
+ case I2C_RX_HALF_CPLT_CB_ID:
+ if (i2c_hdl->rx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Rx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ i2c_hdl->user_callback.RxHalfCpltCallback = NULL;
+ break;
+
+ case I2C_ERROR_CB_ID:
+ if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY || i2c_hdl->rx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx&Rx are both not in Ready state, can't unregister Error callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ i2c_hdl->user_callback.ErrorCallback = NULL;
+ break;
+
+ default:
+ LOG_E("I2C user callback ID-[%d] is Invalid!\n", CallbackID);
+ return LL_INVALID;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_LL_Exported_Functions_Group2 I2C Read Write Functions
+ * @brief I2C Read Write Functions
+ * @{
+ */
+
+/**
+ * @brief I2C Master Read an amount of data in CPU blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_MasterRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t timeout)
+{
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->rx_ctrl.state != I2C_STATE_READY || i2c_hdl->tx_ctrl.state == I2C_STATE_BUSY_TX) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Rx isn't in READY state or Tx is Ongoing, can't start Read operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ i2c_hdl->rx_ctrl.state = I2C_STATE_BUSY_RX;
+ i2c_hdl->rx_ctrl.buf = frame->buf;
+ i2c_hdl->rx_ctrl.size = frame->buf_len;
+ i2c_hdl->rx_ctrl.cnt = 0;
+ i2c_hdl->rx_ctrl.isr = NULL;
+
+ //Clear RxFIFO and interrupt pending which will be used following
+ __LL_I2C_RxFIFO_Reset(Instance);
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+ tickstart = LL_GetTick();
+
+ //TAR config
+ __LL_I2C_MST_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_StartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_StartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_StartAddr32b(Instance, frame->mem_addr);
+ }
+
+ /*** First transmit (TAR+)memory address if need ***/
+ if (frame->mem_addr_size != I2C_MEMADDR_SIZE_INVALID) {
+ //Wait for Master TX/RX Done
+ while (!__LL_I2C_MST_IsTxRxDone(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear Master TX/RX Done Pending
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+ }
+
+ /*** Second Start to read data ***/
+ __LL_I2C_Timing_StartReadStop(Instance, frame->buf_len);
+
+ //Read data loop
+ while (i2c_hdl->rx_ctrl.cnt < i2c_hdl->rx_ctrl.size) {
+ if (!__LL_I2C_IsRxFIFOEmpty(Instance)) {
+ *i2c_hdl->rx_ctrl.buf = (uint8_t)__LL_I2C_Dat_Read(Instance);
+ i2c_hdl->rx_ctrl.buf++;
+ i2c_hdl->rx_ctrl.cnt++;
+ } else {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+ }
+
+ //Wait for Stop Detect
+ while (!__LL_I2C_IsDetStop(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear Stop Detect and Tx Done interrupt Pending
+ __LL_I2C_DetStop_Clr(Instance);
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+
+ ret = LL_OK;
+
+exit:
+ i2c_hdl->rx_ctrl.state = I2C_STATE_READY;
+ return ret;
+}
+
+/**
+ * @brief I2C Master Write an amount of data in CPU blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_MasterWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t timeout)
+{
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY || i2c_hdl->rx_ctrl.state == I2C_STATE_BUSY_RX) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx isn't in READY state or Rx is Ongoing, can't start Write operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ i2c_hdl->tx_ctrl.state = I2C_STATE_BUSY_TX;
+ i2c_hdl->tx_ctrl.buf = frame->buf;
+ i2c_hdl->tx_ctrl.size = frame->buf_len;
+ i2c_hdl->tx_ctrl.cnt = 0;
+ i2c_hdl->tx_ctrl.isr = NULL;
+
+ //Clear TxFIFO and interrupt pending which will be used following
+ __LL_I2C_TxFIFO_Reset(Instance);
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+ tickstart = LL_GetTick();
+
+ //TAR config
+ __LL_I2C_MST_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_StartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_StartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_StartAddr32b(Instance, frame->mem_addr);
+ }
+
+ /*** First transmit (TAR+)memory address if need, Second continue to write data ***/
+ if (frame->mem_addr_size != I2C_MEMADDR_SIZE_INVALID) {
+ //Wait for Master TX/RX Done
+ while (!__LL_I2C_MST_IsTxRxDone(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear Master TX/RX Done Pending
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+
+ //Continue Write data, don't need Restart signgal
+ __LL_I2C_Timing_WriteStop(Instance, frame->buf_len);
+ } else {
+ //No need to send memory address, so need Start signal to start write data
+ __LL_I2C_Timing_StartWriteStop(Instance, frame->buf_len);
+ }
+
+ //Write data loop
+ while (i2c_hdl->tx_ctrl.cnt < i2c_hdl->tx_ctrl.size) {
+ if (!__LL_I2C_IsTxFIFOFull(Instance)) {
+ __LL_I2C_Dat_Write(Instance, *i2c_hdl->tx_ctrl.buf);
+ i2c_hdl->tx_ctrl.buf++;
+ i2c_hdl->tx_ctrl.cnt++;
+ } else {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+ }
+
+ //Wait for Stop Detect
+ while (!__LL_I2C_IsDetStop(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear Stop Detect and Tx Done interrupt Pending
+ __LL_I2C_DetStop_Clr(Instance);
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+
+ ret = LL_OK;
+
+exit:
+ i2c_hdl->tx_ctrl.state = I2C_STATE_READY;
+ return ret;
+}
+
+/**
+ * @brief I2C Slave Read an amount of data in CPU blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_SlaveRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t timeout)
+{
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->rx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Rx isn't in READY state, can't start Read operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ i2c_hdl->rx_ctrl.state = I2C_STATE_BUSY_RX;
+ i2c_hdl->rx_ctrl.buf = frame->buf;
+ i2c_hdl->rx_ctrl.size = frame->buf_len;
+ i2c_hdl->rx_ctrl.cnt = 0;
+ i2c_hdl->rx_ctrl.isr = NULL;
+
+ //Clear RxFIFO and interrupt pending which will be used following
+ __LL_I2C_RxFIFO_Reset(Instance);
+ __LL_I2C_SLV_RxAddrAndCmdIsSlvRX_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+ tickstart = LL_GetTick();
+
+ // Wait for Master Start transmit
+ while (!__LL_I2C_SLV_IsRxAddrAndCmdIsSlvRX(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear Slave Rx Pending
+ __LL_I2C_SLV_RxAddrAndCmdIsSlvRX_Clr(Instance);
+
+ //Read data loop
+ while (i2c_hdl->rx_ctrl.cnt < i2c_hdl->rx_ctrl.size) {
+ if (!__LL_I2C_IsRxFIFOEmpty(Instance)) {
+ *i2c_hdl->rx_ctrl.buf = (uint8_t)__LL_I2C_Dat_Read(Instance);
+ i2c_hdl->rx_ctrl.buf++;
+ i2c_hdl->rx_ctrl.cnt++;
+ } else {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+ }
+
+ //Wait for Stop Detect
+ while (!__LL_I2C_IsDetStop(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear Stop Detect Pending
+ __LL_I2C_DetStop_Clr(Instance);
+
+ ret = LL_OK;
+
+exit:
+ i2c_hdl->rx_ctrl.state = I2C_STATE_READY;
+ return ret;
+}
+
+/**
+ * @brief I2C Slave Write an amount of data in CPU blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_SlaveWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t timeout)
+{
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx isn't in READY state, can't start Write operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ i2c_hdl->tx_ctrl.state = I2C_STATE_BUSY_TX;
+ i2c_hdl->tx_ctrl.buf = frame->buf;
+ i2c_hdl->tx_ctrl.size = frame->buf_len;
+ i2c_hdl->tx_ctrl.cnt = 0;
+ i2c_hdl->tx_ctrl.isr = NULL;
+
+ //Clear TxFIFO and interrupt pending which will be used following
+ __LL_I2C_TxFIFO_Reset(Instance);
+ __LL_I2C_SLV_RxAddrAndCmdIsSlvTX_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+ tickstart = LL_GetTick();
+
+ // Wait for Master Start transmit
+ while (!__LL_I2C_SLV_IsRxAddrAndCmdIsSlvTX(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear Slave Tx Pending
+ __LL_I2C_SLV_RxAddrAndCmdIsSlvTX_Clr(Instance);
+
+ //Write data loop
+ while (i2c_hdl->tx_ctrl.cnt < i2c_hdl->tx_ctrl.size) {
+ if (!__LL_I2C_IsTxFIFOFull(Instance)) {
+ __LL_I2C_Dat_Write(Instance, *i2c_hdl->tx_ctrl.buf);
+ i2c_hdl->tx_ctrl.buf++;
+ i2c_hdl->tx_ctrl.cnt++;
+ } else {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+ }
+
+ //Wait for Stop Detect
+ while (!__LL_I2C_IsDetStop(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear Stop Detect Pending
+ __LL_I2C_DetStop_Clr(Instance);
+
+ ret = LL_OK;
+
+exit:
+ i2c_hdl->tx_ctrl.state = I2C_STATE_READY;
+ return ret;
+}
+
+/**
+ * @brief SMBUS Master Read an amount of data in CPU blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_MasterRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t timeout)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ frame->mem_addr_size = I2C_MEMADDR_SIZE_8BIT;
+ frame->mem_addr = frame->smbus_cmd;
+
+ return LL_I2C_MasterRead_CPU(Instance, frame, timeout);
+}
+
+/**
+ * @brief SMBUS Master Write an amount of data in CPU blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_MasterWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t timeout)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ frame->mem_addr_size = I2C_MEMADDR_SIZE_8BIT;
+ frame->mem_addr = frame->smbus_cmd;
+
+ return LL_I2C_MasterWrite_CPU(Instance, frame, timeout);
+}
+
+/**
+ * @brief SMBUS Slave Read an amount of data in CPU blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveRead_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t timeout)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ return LL_I2C_SlaveRead_CPU(Instance, frame, timeout);
+}
+
+/**
+ * @brief SMBUS Slave Write an amount of data in CPU blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveWrite_CPU(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame, uint32_t timeout)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ return LL_I2C_SlaveWrite_CPU(Instance, frame, timeout);
+}
+
+
+/**
+ * @brief I2C Master Read an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_MasterRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ uint32_t tickstart;
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->rx_ctrl.state != I2C_STATE_READY || i2c_hdl->tx_ctrl.state == I2C_STATE_BUSY_TX) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Rx isn't in READY state or Tx is Ongoing, can't start Read operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ i2c_hdl->rx_ctrl.state = I2C_STATE_BUSY_RX;
+ i2c_hdl->rx_ctrl.buf = frame->buf;
+ i2c_hdl->rx_ctrl.size = frame->buf_len;
+ i2c_hdl->rx_ctrl.cnt = 0;
+ i2c_hdl->rx_ctrl.isr = I2C_Read_ISR;
+
+ //Clear RxFIFO and interrupt pending which will be used following
+ __LL_I2C_RxFIFO_Reset(Instance);
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+ tickstart = LL_GetTick();
+
+ //TAR config
+ __LL_I2C_MST_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_StartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_StartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_StartAddr32b(Instance, frame->mem_addr);
+ }
+
+ /*** First transmit (TAR+)memory address if need ***/
+ if (frame->mem_addr_size != I2C_MEMADDR_SIZE_INVALID) {
+ //Wait for Master TX/RX Done
+ while (!__LL_I2C_MST_IsTxRxDone(Instance)) {
+ if ((LL_GetTick() - tickstart) > I2C_DEFAULT_TIMEOUT) {
+ i2c_hdl->rx_ctrl.state = I2C_STATE_READY;
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ return LL_TIMEOUT;
+ }
+ }
+
+ //Clear Master TX/RX Done Pending
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+ }
+
+ /*** Second Start to read data ***/
+ __LL_I2C_Timing_StartReadStop(Instance, frame->buf_len);
+
+ //Enable RxFIFO Full interrupt
+ __LL_I2C_RxFIFOFull_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C Master Write an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_MasterWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ uint32_t tickstart;
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY || i2c_hdl->rx_ctrl.state == I2C_STATE_BUSY_RX) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx isn't in READY state or Rx is Ongoing, can't start Write operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ i2c_hdl->tx_ctrl.state = I2C_STATE_BUSY_TX;
+ i2c_hdl->tx_ctrl.buf = frame->buf;
+ i2c_hdl->tx_ctrl.size = frame->buf_len;
+ i2c_hdl->tx_ctrl.cnt = 0;
+ i2c_hdl->tx_ctrl.isr = I2C_Write_ISR;
+
+ //Clear TxFIFO and interrupt pending which will be used following
+ __LL_I2C_TxFIFO_Reset(Instance);
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+ tickstart = LL_GetTick();
+
+ //TAR config
+ __LL_I2C_MST_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_StartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_StartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_StartAddr32b(Instance, frame->mem_addr);
+ }
+
+ /*** First transmit (TAR+)memory address if need, Second continue to write data ***/
+ if (frame->mem_addr_size != I2C_MEMADDR_SIZE_INVALID) {
+ //Wait for Master TX/RX Done
+ while (!__LL_I2C_MST_IsTxRxDone(Instance)) {
+ if ((LL_GetTick() - tickstart) > I2C_DEFAULT_TIMEOUT) {
+ i2c_hdl->tx_ctrl.state = I2C_STATE_READY;
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ return LL_TIMEOUT;
+ }
+ }
+
+ //Clear Master TX/RX Done Pending
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+
+ //Continue Write data, don't need Restart signgal
+ __LL_I2C_Timing_WriteStop(Instance, frame->buf_len);
+ } else {
+ //No need to send memory address, so need Start signal to start write data
+ __LL_I2C_Timing_StartWriteStop(Instance, frame->buf_len);
+ }
+
+ //Enable TxFIFO Empty interrupt
+ __LL_I2C_TxFIFOEmpty_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C Slave Read an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_SlaveRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->rx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Rx isn't in READY state, can't start Read operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ i2c_hdl->rx_ctrl.state = I2C_STATE_BUSY_RX;
+ i2c_hdl->rx_ctrl.buf = frame->buf;
+ i2c_hdl->rx_ctrl.size = frame->buf_len;
+ i2c_hdl->rx_ctrl.cnt = 0;
+ i2c_hdl->rx_ctrl.isr = I2C_Read_ISR;
+
+ //Clear RxFIFO and interrupt pending which will be used following
+ __LL_I2C_RxFIFO_Reset(Instance);
+ __LL_I2C_SLV_RxAddrAndCmdIsSlvRX_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+
+ //Enable RxFIFO Full interrupt
+ __LL_I2C_RxFIFOFull_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C Slave Write an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_SlaveWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx isn't in READY state, can't start Write operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ i2c_hdl->tx_ctrl.state = I2C_STATE_BUSY_TX;
+ i2c_hdl->tx_ctrl.buf = frame->buf;
+ i2c_hdl->tx_ctrl.size = frame->buf_len;
+ i2c_hdl->tx_ctrl.cnt = 0;
+ i2c_hdl->tx_ctrl.isr = I2C_Write_ISR;
+
+ //Clear TxFIFO and interrupt pending which will be used following
+ __LL_I2C_TxFIFO_Reset(Instance);
+ __LL_I2C_SLV_RxAddrAndCmdIsSlvTX_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+
+ //Enable TxFIFO Empty interrupt
+ __LL_I2C_TxFIFOEmpty_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SMBUS Master Read an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_MasterRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ frame->mem_addr_size = I2C_MEMADDR_SIZE_8BIT;
+ frame->mem_addr = frame->smbus_cmd;
+
+ return LL_I2C_MasterRead_IT(Instance, frame);
+}
+
+/**
+ * @brief SMBUS Master Write an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param frame Write frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_MasterWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ frame->mem_addr_size = I2C_MEMADDR_SIZE_8BIT;
+ frame->mem_addr = frame->smbus_cmd;
+
+ return LL_I2C_MasterWrite_IT(Instance, frame);
+}
+
+/**
+ * @brief SMBUS Slave Read an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveRead_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ return LL_I2C_SlaveRead_IT(Instance, frame);
+}
+
+/**
+ * @brief SMBUS Slave Write an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveWrite_IT(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ return LL_I2C_SlaveWrite_IT(Instance, frame);
+}
+
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief I2C Master Read an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_MasterRead_DMA(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ uint32_t tickstart;
+ I2C_HandleTypeDef *i2c_hdl;
+ DMA_UserCfgTypeDef dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->rx_ctrl.state != I2C_STATE_READY || i2c_hdl->tx_ctrl.state == I2C_STATE_BUSY_TX) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Rx isn't in READY state or Tx is Ongoing, can't start Read operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //DMA Init
+ memset((void *)&dma_user_cfg, 0x0, sizeof(dma_user_cfg));
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_8b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_8b;
+
+ dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_FIX;
+ dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == I2C0) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_I2C0_RX;
+ } else if (Instance == I2C1) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_I2C1_RX;
+ } else if (Instance == I2C2) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_I2C2_RX;
+ } else {
+ LOG_E("I2C DMA source handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Receive Default Config
+ dma_user_cfg.trans_type = DMA_TRANS_TYPE_P2M;
+ dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_INC;
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ dma_user_cfg.end_callback = (DMA_IRQCallback)I2C_Read_DMACplt;
+ dma_user_cfg.end_arg = Instance;
+ dma_user_cfg.err_callback = (DMA_IRQCallback)I2C_Read_DMAError;
+ dma_user_cfg.err_arg = Instance;
+ dma_user_cfg.half_callback = (DMA_IRQCallback)I2C_Read_DMAHalfCplt;
+ dma_user_cfg.half_arg = Instance;
+
+ i2c_hdl->rx_ctrl.dma_ch = I2C_DMA_Init(&dma_user_cfg);
+
+ if (i2c_hdl->rx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("I2C read request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Transmit config
+ i2c_hdl->rx_ctrl.state = I2C_STATE_BUSY_RX;
+ i2c_hdl->rx_ctrl.buf = frame->buf;
+ i2c_hdl->rx_ctrl.size = frame->buf_len;
+ i2c_hdl->rx_ctrl.cnt = 0;
+ i2c_hdl->rx_ctrl.isr = NULL;
+
+ //Clear RxFIFO and interrupt pending which will be used following
+ __LL_I2C_RxFIFO_Reset(Instance);
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+ tickstart = LL_GetTick();
+
+ //TAR config
+ __LL_I2C_MST_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_StartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_StartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_StartAddr32b(Instance, frame->mem_addr);
+ }
+
+ /*** First transmit (TAR+)memory address if need ***/
+ if (frame->mem_addr_size != I2C_MEMADDR_SIZE_INVALID) {
+ //Wait for Master TX/RX Done
+ while (!__LL_I2C_MST_IsTxRxDone(Instance)) {
+ if ((LL_GetTick() - tickstart) > I2C_DEFAULT_TIMEOUT) {
+ I2C_DMA_DeInit(i2c_hdl->rx_ctrl.dma_ch);
+ i2c_hdl->rx_ctrl.state = I2C_STATE_READY;
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ return LL_TIMEOUT;
+ }
+ }
+
+ //Clear Master TX/RX Done Pending
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+ }
+
+ /*** Second Start to read data ***/
+ __LL_I2C_Timing_StartReadStop(Instance, frame->buf_len);
+
+ //Enable Rx DMA Requset
+ __LL_I2C_RxDMA_En(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, i2c_hdl->rx_ctrl.dma_ch, (uint32_t)&Instance->RXDATA, (uint32_t)i2c_hdl->rx_ctrl.buf, i2c_hdl->rx_ctrl.size);
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C Master Write an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_MasterWrite_DMA(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ uint32_t tickstart;
+ I2C_HandleTypeDef *i2c_hdl;
+ DMA_UserCfgTypeDef dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY || i2c_hdl->rx_ctrl.state == I2C_STATE_BUSY_RX) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx isn't in READY state or Rx is Ongoing, can't start Write operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //DMA Init
+ memset((void *)&dma_user_cfg, 0x0, sizeof(dma_user_cfg));
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_8b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_8b;
+
+ dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_FIX;
+ dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == I2C0) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_I2C0_TX;
+ } else if (Instance == I2C1) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_I2C1_TX;
+ } else if (Instance == I2C2) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_I2C2_TX;
+ } else {
+ LOG_E("I2C DMA destination handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Transmit Default Config
+ dma_user_cfg.trans_type = DMA_TRANS_TYPE_M2P;
+ dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_INC;
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ dma_user_cfg.end_callback = (DMA_IRQCallback)I2C_Write_DMACplt;
+ dma_user_cfg.end_arg = Instance;
+ dma_user_cfg.err_callback = (DMA_IRQCallback)I2C_Write_DMAError;
+ dma_user_cfg.err_arg = Instance;
+ dma_user_cfg.half_callback = (DMA_IRQCallback)I2C_Write_DMAHalfCplt;
+ dma_user_cfg.half_arg = Instance;
+
+ i2c_hdl->tx_ctrl.dma_ch = I2C_DMA_Init(&dma_user_cfg);
+
+ if (i2c_hdl->tx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("I2C write request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Transmit config
+ i2c_hdl->tx_ctrl.state = I2C_STATE_BUSY_TX;
+ i2c_hdl->tx_ctrl.buf = frame->buf;
+ i2c_hdl->tx_ctrl.size = frame->buf_len;
+ i2c_hdl->tx_ctrl.cnt = 0;
+ i2c_hdl->tx_ctrl.isr = NULL;
+
+ //Clear TxFIFO and interrupt pending which will be used following
+ __LL_I2C_TxFIFO_Reset(Instance);
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+ tickstart = LL_GetTick();
+
+ //TAR config
+ __LL_I2C_MST_TAR_Set(Instance, frame->target_addr);
+
+ //start and send read memory address if has memory address to send
+ if (frame->mem_addr_size == I2C_MEMADDR_SIZE_8BIT) {
+ __LL_I2C_Timing_StartAddr8b(Instance, (frame->mem_addr & 0xffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_16BIT) {
+ __LL_I2C_Timing_StartAddr16b(Instance, (frame->mem_addr & 0xffffUL));
+ } else if (frame->mem_addr_size == I2C_MEMADDR_SIZE_32BIT) {
+ __LL_I2C_Timing_StartAddr32b(Instance, frame->mem_addr);
+ }
+
+ /*** First transmit (TAR+)memory address if need, Second continue to write data ***/
+ if (frame->mem_addr_size != I2C_MEMADDR_SIZE_INVALID) {
+ //Wait for Master TX/RX Done
+ while (!__LL_I2C_MST_IsTxRxDone(Instance)) {
+ if ((LL_GetTick() - tickstart) > I2C_DEFAULT_TIMEOUT) {
+ I2C_DMA_DeInit(i2c_hdl->tx_ctrl.dma_ch);
+ i2c_hdl->tx_ctrl.state = I2C_STATE_READY;
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ return LL_TIMEOUT;
+ }
+ }
+
+ //Clear Master TX/RX Done Pending
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+
+ //Continue Write data, don't need Restart signgal
+ __LL_I2C_Timing_WriteStop(Instance, frame->buf_len);
+ } else {
+ //No need to send memory address, so need Start signal to start write data
+ __LL_I2C_Timing_StartWriteStop(Instance, frame->buf_len);
+ }
+
+ //Enable Tx DMA Requset
+ __LL_I2C_TxDMA_En(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, i2c_hdl->tx_ctrl.dma_ch, (uint32_t)i2c_hdl->tx_ctrl.buf, (uint32_t)&Instance->TXDATA, i2c_hdl->tx_ctrl.size);
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C Slave Read an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_SlaveRead_DMA(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+ DMA_UserCfgTypeDef dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->rx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Rx isn't in READY state, can't start Read operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //DMA Init
+ memset((void *)&dma_user_cfg, 0x0, sizeof(dma_user_cfg));
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_8b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_8b;
+
+ dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_FIX;
+ dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == I2C0) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_I2C0_RX;
+ } else if (Instance == I2C1) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_I2C1_RX;
+ } else if (Instance == I2C2) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_I2C2_RX;
+ } else {
+ LOG_E("I2C DMA source handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Receive Default Config
+ dma_user_cfg.trans_type = DMA_TRANS_TYPE_P2M;
+ dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_INC;
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ dma_user_cfg.end_callback = (DMA_IRQCallback)I2C_Read_DMACplt;
+ dma_user_cfg.end_arg = Instance;
+ dma_user_cfg.err_callback = (DMA_IRQCallback)I2C_Read_DMAError;
+ dma_user_cfg.err_arg = Instance;
+ dma_user_cfg.half_callback = (DMA_IRQCallback)I2C_Read_DMAHalfCplt;
+ dma_user_cfg.half_arg = Instance;
+
+ i2c_hdl->rx_ctrl.dma_ch = I2C_DMA_Init(&dma_user_cfg);
+
+ if (i2c_hdl->rx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("I2C read request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Transmit config
+ i2c_hdl->rx_ctrl.state = I2C_STATE_BUSY_RX;
+ i2c_hdl->rx_ctrl.buf = frame->buf;
+ i2c_hdl->rx_ctrl.size = frame->buf_len;
+ i2c_hdl->rx_ctrl.cnt = 0;
+ i2c_hdl->rx_ctrl.isr = NULL;
+
+ //Clear RxFIFO and interrupt pending which will be used following
+ __LL_I2C_RxFIFO_Reset(Instance);
+ __LL_I2C_SLV_RxAddrAndCmdIsSlvRX_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+
+ //Enable Rx DMA Requset
+ __LL_I2C_RxDMA_En(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, i2c_hdl->rx_ctrl.dma_ch, (uint32_t)&Instance->RXDATA, (uint32_t)i2c_hdl->rx_ctrl.buf, i2c_hdl->rx_ctrl.size);
+
+ return LL_OK;
+}
+
+/**
+ * @brief I2C Slave Write an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_SlaveWrite_DMA(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+ DMA_UserCfgTypeDef dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return LL_ERROR;
+ } else if (i2c_hdl->tx_ctrl.state != I2C_STATE_READY) {
+ LOG_E("This I2C[0x%08" PRIx32 "] Tx isn't in READY state, can't start Write operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //DMA Init
+ memset((void *)&dma_user_cfg, 0x0, sizeof(dma_user_cfg));
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_8b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_8b;
+
+ dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_FIX;
+ dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == I2C0) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_I2C0_TX;
+ } else if (Instance == I2C1) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_I2C1_TX;
+ } else if (Instance == I2C2) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_I2C2_TX;
+ } else {
+ LOG_E("I2C DMA destination handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Transmit Default Config
+ dma_user_cfg.trans_type = DMA_TRANS_TYPE_M2P;
+ dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_INC;
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ dma_user_cfg.end_callback = (DMA_IRQCallback)I2C_Write_DMACplt;
+ dma_user_cfg.end_arg = Instance;
+ dma_user_cfg.err_callback = (DMA_IRQCallback)I2C_Write_DMAError;
+ dma_user_cfg.err_arg = Instance;
+ dma_user_cfg.half_callback = (DMA_IRQCallback)I2C_Write_DMAHalfCplt;
+ dma_user_cfg.half_arg = Instance;
+
+ i2c_hdl->tx_ctrl.dma_ch = I2C_DMA_Init(&dma_user_cfg);
+
+ if (i2c_hdl->tx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("I2C write request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Transmit config
+ i2c_hdl->tx_ctrl.state = I2C_STATE_BUSY_TX;
+ i2c_hdl->tx_ctrl.buf = frame->buf;
+ i2c_hdl->tx_ctrl.size = frame->buf_len;
+ i2c_hdl->tx_ctrl.cnt = 0;
+ i2c_hdl->tx_ctrl.isr = NULL;
+
+ //Clear TxFIFO and interrupt pending which will be used following
+ __LL_I2C_TxFIFO_Reset(Instance);
+ __LL_I2C_SLV_RxAddrAndCmdIsSlvTX_Clr(Instance);
+ __LL_I2C_DetStop_Clr(Instance);
+
+ //Enable Tx DMA Requset
+ __LL_I2C_TxDMA_En(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, i2c_hdl->tx_ctrl.dma_ch, (uint32_t)i2c_hdl->tx_ctrl.buf, (uint32_t)&Instance->TXDATA, i2c_hdl->tx_ctrl.size);
+
+ return LL_OK;
+}
+
+/**
+ * @brief SMBUS Master Read an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_MasterRead_DMA(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ frame->mem_addr_size = I2C_MEMADDR_SIZE_8BIT;
+ frame->mem_addr = frame->smbus_cmd;
+
+ return LL_I2C_MasterRead_DMA(Instance, frame);
+}
+
+/**
+ * @brief SMBUS Master Write an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_MasterWrite_DMA(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ frame->mem_addr_size = I2C_MEMADDR_SIZE_8BIT;
+ frame->mem_addr = frame->smbus_cmd;
+
+ return LL_I2C_MasterWrite_DMA(Instance, frame);
+}
+
+/**
+ * @brief SMBUS Slave Read an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame read frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveRead_DMA(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ return LL_I2C_SlaveRead_DMA(Instance, frame);
+}
+
+/**
+ * @brief SMBUS Slave Write an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param frame write frame pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SMBUS_SlaveWrite_DMA(I2C_TypeDef *Instance, I2C_FrameTypeDef *frame)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+ assert_param(frame != NULL);
+ assert_param(frame->buf != NULL);
+ assert_param(frame->buf_len);
+
+ if (!IS_I2C_ALL_INSTANCE(Instance) || frame == NULL || frame->buf == NULL || !frame->buf_len) {
+ return LL_INVALID;
+ }
+
+ return LL_I2C_SlaveWrite_DMA(Instance, frame);
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_LL_Exported_Functions_Group3 I2C Read Write Functions Extension
+ * @brief I2C Read Write Functions Extension
+ * @{
+ */
+
+/**
+ * @brief Transmits in master mode an amount of data in blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Master_Transmit(I2C_TypeDef *Instance, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_MasterWrite_CPU(Instance, &frame, Timeout);
+}
+
+/**
+ * @brief Receives in master mode an amount of data in blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Master_Receive(I2C_TypeDef *Instance, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_MasterRead_CPU(Instance, &frame, Timeout);
+}
+
+/**
+ * @brief Transmits in slave mode an amount of data in blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Slave_Transmit(I2C_TypeDef *Instance, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_SlaveWrite_CPU(Instance, &frame, Timeout);
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in blocking mode
+ * @param Instance Specifies I2C peripheral
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Slave_Receive(I2C_TypeDef *Instance, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_SlaveRead_CPU(Instance, &frame, Timeout);
+}
+
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Master_Transmit_IT(I2C_TypeDef *Instance, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_MasterWrite_IT(Instance, &frame);
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Master_Receive_IT(I2C_TypeDef *Instance, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_MasterRead_IT(Instance, &frame);
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Slave_Transmit_IT(I2C_TypeDef *Instance, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_SlaveWrite_IT(Instance, &frame);
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies I2C peripheral
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Slave_Receive_IT(I2C_TypeDef *Instance, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_SlaveRead_IT(Instance, &frame);
+}
+
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Master_Transmit_DMA(I2C_TypeDef *Instance, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_MasterWrite_DMA(Instance, &frame);
+}
+
+/**
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Master_Receive_DMA(I2C_TypeDef *Instance, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_MasterRead_DMA(Instance, &frame);
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Slave_Transmit_DMA(I2C_TypeDef *Instance, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_SlaveWrite_DMA(Instance, &frame);
+}
+
+/**
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies I2C peripheral
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Slave_Receive_DMA(I2C_TypeDef *Instance, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.buf = pData;
+ frame.buf_len = Size;
+ frame.mem_addr_size = I2C_MEMADDR_SIZE_INVALID;
+
+ return LL_I2C_SlaveRead_DMA(Instance, &frame);
+}
+
+#endif
+
+
+/**
+ * @brief Write an amount of data in blocking mode to a specific memory address
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be written
+ * @param Timeout Timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Mem_Write(I2C_TypeDef *Instance, uint16_t DevAddress, uint32_t MemAddress,
+ I2C_MemAddrSizeETypeDef MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.mem_addr = MemAddress;
+ frame.mem_addr_size = MemAddSize;
+ frame.buf = pData;
+ frame.buf_len = Size;
+
+ return LL_I2C_MasterWrite_CPU(Instance, &frame, Timeout);
+}
+
+/**
+ * @brief Read an amount of data in blocking mode from a specific memory address
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be read
+ * @param Timeout Timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Mem_Read(I2C_TypeDef *Instance, uint16_t DevAddress, uint32_t MemAddress,
+ I2C_MemAddrSizeETypeDef MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.mem_addr = MemAddress;
+ frame.mem_addr_size = MemAddSize;
+ frame.buf = pData;
+ frame.buf_len = Size;
+
+ return LL_I2C_MasterRead_CPU(Instance, &frame, Timeout);
+}
+
+/**
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be written
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Mem_Write_IT(I2C_TypeDef *Instance, uint16_t DevAddress, uint32_t MemAddress,
+ I2C_MemAddrSizeETypeDef MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.mem_addr = MemAddress;
+ frame.mem_addr_size = MemAddSize;
+ frame.buf = pData;
+ frame.buf_len = Size;
+
+ return LL_I2C_MasterWrite_IT(Instance, &frame);
+}
+
+/**
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be Read
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Mem_Read_IT(I2C_TypeDef *Instance, uint16_t DevAddress, uint32_t MemAddress,
+ I2C_MemAddrSizeETypeDef MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.mem_addr = MemAddress;
+ frame.mem_addr_size = MemAddSize;
+ frame.buf = pData;
+ frame.buf_len = Size;
+
+ return LL_I2C_MasterRead_IT(Instance, &frame);
+}
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be written
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Mem_Write_DMA(I2C_TypeDef *Instance, uint16_t DevAddress, uint32_t MemAddress,
+ I2C_MemAddrSizeETypeDef MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.mem_addr = MemAddress;
+ frame.mem_addr_size = MemAddSize;
+ frame.buf = pData;
+ frame.buf_len = Size;
+
+ return LL_I2C_MasterWrite_DMA(Instance, &frame);
+}
+
+/**
+ * @brief Read an amount of data in non-blocking mode with DMA from a specific memory address
+ * @param Instance Specifies I2C peripheral
+ * @param DevAddress Target device address
+ * @param MemAddress Internal memory address
+ * @param MemAddSize Size of internal memory address
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be Read
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_I2C_Mem_Read_DMA(I2C_TypeDef *Instance, uint16_t DevAddress, uint32_t MemAddress,
+ I2C_MemAddrSizeETypeDef MemAddSize, uint8_t *pData, uint16_t Size)
+{
+ I2C_FrameTypeDef frame;
+
+ if (pData == NULL) {
+ return LL_INVALID;
+ }
+
+ memset((void *)&frame, 0x0, sizeof frame);
+ frame.target_addr = DevAddress;
+ frame.mem_addr = MemAddress;
+ frame.mem_addr_size = MemAddSize;
+ frame.buf = pData;
+ frame.buf_len = Size;
+
+ return LL_I2C_MasterRead_DMA(Instance, &frame);
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_LL_Exported_Functions_Interrupt I2C Interrupt Handler and Callback
+ * @brief I2C Interrupt Handler and Callback
+ * @{
+ */
+
+/**
+ * @brief I2C IRQ Handler
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+void LL_I2C_IRQHandler(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+ uint32_t int_en, int_pending;
+
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if (!IS_I2C_ALL_INSTANCE(Instance)) {
+ return;
+ }
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ //All Interrupt Enalbe and Pending Get
+ int_en = __LL_I2C_AllIntEn_Get(Instance);
+ int_pending = __LL_I2C_AllIntPnd_Get(Instance);
+
+
+ //RxFIFO Full Interrupt Pending
+ if ((int_en & I2C0_INTREN_RXFIE_Msk) && (int_pending & I2C0_INTR_RXFI_Msk)) {
+ //Interrupt Pending auto clear
+
+ if (i2c_hdl->rx_ctrl.isr) {
+ i2c_hdl->rx_ctrl.isr(Instance);
+ }
+
+ //Callback
+ LL_I2C_RxFullCallback(Instance);
+ }
+
+ //TxFIFO Empty Interrupt Pending
+ if ((int_en & I2C0_INTREN_TXEIE_Msk) && (int_pending & I2C0_INTR_TXEI_Msk)) {
+ //Interrupt Pending auto clear
+
+ if (i2c_hdl->tx_ctrl.isr) {
+ i2c_hdl->tx_ctrl.isr(Instance);
+ }
+
+ //Callback
+ LL_I2C_TxEmptyCallback(Instance);
+ }
+
+ //RxFIFO Overflow Interrupt Pending
+ if ((int_en & I2C0_INTREN_RXOFIE_Msk) && (int_pending & I2C0_INTR_RXOFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_RxFIFOOverflow_Clr(Instance);
+
+ //Callback
+ LL_I2C_RxOverflowCallback(Instance);
+ }
+
+ //RxFIFO Underflow Interrupt Pending
+ if ((int_en & I2C0_INTREN_RXUFIE_Msk) && (int_pending & I2C0_INTR_RXUFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_RxFIFOUnderflow_Clr(Instance);
+
+ //Callback
+ LL_I2C_RxUnderflowCallback(Instance);
+ }
+
+ //TxFIFO Overflow Interrupt Pending
+ if ((int_en & I2C0_INTREN_TXOFIE_Msk) && (int_pending & I2C0_INTR_TXOFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_TxFIFOOverflow_Clr(Instance);
+
+ //Callback
+ LL_I2C_TxOverflowCallback(Instance);
+ }
+
+ //Arbitration Fail Interrupt Pending
+ if ((int_en & I2C0_INTREN_ARBFIE_Msk) && (int_pending & I2C0_INTR_ARBFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_ArbFail_Clr(Instance);
+
+ //Callback
+ LL_I2C_ArbFailCallback(Instance);
+ }
+
+ //Bus Error Interrupt Pending
+ if ((int_en & I2C0_INTREN_BUSEIE_Msk) && (int_pending & I2C0_INTR_BUSEI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_BusErr_Clr(Instance);
+
+ //Callback
+ LL_I2C_BusErrCallback(Instance);
+ }
+
+ //Master TxRx Done Interrupt Pending
+ if ((int_en & I2C0_INTREN_MDEIE_Msk) && (int_pending & I2C0_INTR_MDEI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+
+ //Callback
+ LL_I2C_MST_TxRxDoneCallback(Instance);
+ }
+
+ //Slave Rx Address and Command is Slave TX Interrupt Pending
+ if ((int_en & I2C0_INTREN_TXADIE_Msk) && (int_pending & I2C0_INTR_TXADI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_SLV_RxAddrAndCmdIsSlvTX_Clr(Instance);
+
+ //Callback
+ LL_I2C_SLV_RxAddrAndCmdIsSlvTXCallback(Instance);
+ }
+
+ //Slave Rx Address and Command is Slave RX Interrupt Pending
+ if ((int_en & I2C0_INTREN_RXADIE_Msk) && (int_pending & I2C0_INTR_RXADI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_SLV_RxAddrAndCmdIsSlvRX_Clr(Instance);
+
+ //Callback
+ LL_I2C_SLV_RxAddrAndCmdIsSlvRXCallback(Instance);
+ }
+
+ //Detect Start Interrupt Pending
+ if ((int_en & I2C0_INTREN_STDETIE_Msk) && (int_pending & I2C0_INTR_STDETI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_DetStart_Clr(Instance);
+
+ //Callback
+ LL_I2C_DetStartCallback(Instance);
+ }
+
+ //Detect Stop Interrupt Pending
+ if ((int_en & I2C0_INTREN_SPDETIE_Msk) && (int_pending & I2C0_INTR_SPETI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_DetStop_Clr(Instance);
+
+ if (i2c_hdl->tx_ctrl.cnt >= i2c_hdl->tx_ctrl.size && i2c_hdl->tx_ctrl.isr) {
+ i2c_hdl->tx_ctrl.isr(Instance);
+ }
+
+ if (i2c_hdl->rx_ctrl.cnt >= i2c_hdl->rx_ctrl.size && i2c_hdl->rx_ctrl.isr) {
+ i2c_hdl->rx_ctrl.isr(Instance);
+ }
+
+ //Callback
+ LL_I2C_DetStopCallback(Instance);
+ }
+
+ //Detect Restart Interrupt Pending
+ if ((int_en & I2C0_INTREN_RSDETIE_Msk) && (int_pending & I2C0_INTR_RSDETI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_DetRestart_Clr(Instance);
+
+ //Callback
+ LL_I2C_DetRestartCallback(Instance);
+ }
+
+ //Rx NACK Interrupt Pending
+ if ((int_en & I2C0_INTREN_NACKIE_Msk) && (int_pending & I2C0_INTR_NACKI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_RxNACK_Clr(Instance);
+
+ //Callback
+ LL_I2C_RxNACKCallback(Instance);
+ }
+
+ //Master Detect Alert Signal Interrupt Pending
+ if ((int_en & I2C0_INTREN_ALDETIE_Msk) && (int_pending & I2C0_INTR_ALDETI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_MST_DetAlertSig_Clr(Instance);
+
+ //Callback
+ LL_I2C_MST_DetAlertSigCallback(Instance);
+ }
+
+ //Master Tmext Timeout Interrupt Pending
+ if ((int_en & I2C0_INTREN_MEXTOIE_Msk) && (int_pending & I2C0_INTR_MEXTOI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_MST_TmextTimeout_Clr(Instance);
+
+ //Callback
+ LL_I2C_MST_TmextTimeoutCallback(Instance);
+ }
+
+ //Slave Tsext Timeout Interrupt Pending
+ if ((int_en & I2C0_INTREN_SEXTOIE_Msk) && (int_pending & I2C0_INTR_SEXTOI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_SLV_TsextTimeout_Clr(Instance);
+
+ //Callback
+ LL_I2C_SLV_TsextTimeoutCallback(Instance);
+ }
+
+ //Rx PEC Error Interrupt Pending
+ if ((int_en & I2C0_INTREN_PECRXIE_Msk) && (int_pending & I2C0_INTR_PECRXI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_RxPECErr_Clr(Instance);
+
+ //Callback
+ LL_I2C_RxPECErrCallback(Instance);
+ }
+
+ //Slave Rx General Call Interrupt Pending
+ if ((int_en & I2C0_INTREN_RXGCIE_Msk) && (int_pending & I2C0_INTR_RXGCI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_SLV_RxGenCall_Clr(Instance);
+
+ //Callback
+ LL_I2C_SLV_RxGenCallCallback(Instance);
+ }
+
+ //Master Tx Address Done Interrupt Pending
+ if ((int_en & I2C0_INTREN_MTXAIE_Msk) && (int_pending & I2C0_INTR_MTXAI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_MST_TxAddrDone_Clr(Instance);
+
+ //Callback
+ LL_I2C_MST_TxAddrDoneCallback(Instance);
+ }
+
+ //Slave Wait Tx Data Interrupt Pending
+ if ((int_en & I2C0_INTREN_SWTXIE_Msk) && (int_pending & I2C0_INTR_SWTXI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_SLV_WaitTxDat_Clr(Instance);
+
+ //Callback
+ LL_I2C_SLV_WaitTxDatCallback(Instance);
+ }
+
+ //Master On Hold Interrupt Pending
+ if ((int_en & I2C0_INTREN_MOHIE_Msk) && (int_pending & I2C0_INTR_MOHI_Msk)) {
+ //Interrupt Pending auto clear
+
+ //Callback
+ LL_I2C_MST_OnHoldCallback(Instance);
+ }
+
+ //The following features are available for later versions
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ return;
+ }
+
+ //Bus Timeout Interrupt Pending
+ if ((int_en & I2C0_INTREN_BTOIE_Msk) && (int_pending & I2C0_INTR_BTOI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_I2C_BusTimeoutPnd_Clr(Instance);
+
+ //Callback
+ LL_I2C_BusTimeoutCallback(Instance);
+ }
+}
+
+/**
+ * @brief I2C RxFIFO Full Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_RxFullCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_RxFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C TxFIFO Empty Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_TxEmptyCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_TxEmptyCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C RxFIFO Overflow Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_RxOverflowCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_RxOverflowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C RxFIFO Underflow Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_RxUnderflowCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_RxUnderflowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C TxFIFO Overflow Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_TxOverflowCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_TxOverflowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Arbitration Fail Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_ArbFailCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_ArbFailCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Bus Error Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_BusErrCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_BusErrCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Master TxRx Done Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_MST_TxRxDoneCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_MST_TxRxDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Slave Rx Address and Command is Slave TX Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_SLV_RxAddrAndCmdIsSlvTXCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_SLV_RxAddrAndCmdIsSlvTXCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Slave Rx Address and Command is Slave RX Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_SLV_RxAddrAndCmdIsSlvRXCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_SLV_RxAddrAndCmdIsSlvRXCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Detect Start Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_DetStartCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_DetStartCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Detect Stop Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_DetStopCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_DetStopCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Detect Restart Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_DetRestartCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_DetRestartCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Rx NACK Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_RxNACKCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_RxNACKCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Master Detect Alert Signal Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_MST_DetAlertSigCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_MST_DetAlertSigCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Master Tmext Timeout Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_MST_TmextTimeoutCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_MST_TmextTimeoutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Slave Tsext Timeout Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_SLV_TsextTimeoutCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_SLV_TsextTimeoutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Rx PEC Error Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_RxPECErrCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_RxPECErrCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Slave Rx General Call Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_SLV_RxGenCallCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_SLV_RxGenCallCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Master Tx Address Done Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_MST_TxAddrDoneCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_MST_TxAddrDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Slave Wait Tx Data Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_SLV_WaitTxDatCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_SLV_WaitTxDatCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Master On Hold Interrupt Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_MST_OnHoldCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_MST_OnHoldCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C Bus Timeout Interrupt Interrupt Callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+__WEAK void LL_I2C_BusTimeoutCallback(I2C_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_I2C_BusTimeoutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private Functions ---------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief I2C Handle Get
+ * @param Instance Specifies I2C peripheral
+ * @return I2C_HandleTypeDef pointer
+ */
+static I2C_HandleTypeDef *I2C_Handle_Get(I2C_TypeDef *Instance)
+{
+ //Assert param
+ assert_param(IS_I2C_ALL_INSTANCE(Instance));
+
+ if (Instance == I2C0) {
+ return &i2c_hdl_global[I2C_INSTANCE_0];
+ } else if (Instance == I2C1) {
+ return &i2c_hdl_global[I2C_INSTANCE_1];
+ } else if (Instance == I2C2) {
+ return &i2c_hdl_global[I2C_INSTANCE_2];
+ }
+
+ return NULL;
+}
+
+/**
+ * @brief I2C Read Detect Stop Interrupt Service Routine
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+static void I2C_Read_DetStop_ISR(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ if (i2c_hdl->rx_ctrl.cnt >= i2c_hdl->rx_ctrl.size) {
+ //Disable Detect Stop Interrupt and clear Tx Done
+ __LL_I2C_DetStop_INT_Dis(Instance);
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+
+ i2c_hdl->rx_ctrl.isr = NULL;
+ i2c_hdl->rx_ctrl.state = I2C_STATE_READY;
+
+ //Rx Complete Callback
+ if (i2c_hdl->user_callback.RxCpltCallback) {
+ i2c_hdl->user_callback.RxCpltCallback();
+ }
+ }
+}
+
+/**
+ * @brief I2C read data handle in Interrupt mode
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+static void I2C_Read_ISR(I2C_TypeDef *Instance)
+{
+ uint8_t rx_fifo_trig_lvl;
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ rx_fifo_trig_lvl = __LL_I2C_RxFIFOFullThres_Get(Instance);
+
+ //Read data from RxFIFO
+ while (rx_fifo_trig_lvl-- && i2c_hdl->rx_ctrl.cnt < i2c_hdl->rx_ctrl.size) {
+ *i2c_hdl->rx_ctrl.buf = (uint8_t)__LL_I2C_Dat_Read(Instance);
+ i2c_hdl->rx_ctrl.buf++;
+ i2c_hdl->rx_ctrl.cnt++;
+ }
+
+ //Read Complete
+ if (i2c_hdl->rx_ctrl.cnt >= i2c_hdl->rx_ctrl.size) {
+ //Disable RxFIFO Full interrupt
+ __LL_I2C_RxFIFOFull_INT_Dis(Instance);
+
+ //Switch isr to Detect Stop ISR
+ i2c_hdl->rx_ctrl.isr = I2C_Read_DetStop_ISR;
+
+ //Detect Stop Interrupt Enable
+ __LL_I2C_DetStop_INT_En(Instance);
+ }
+}
+
+/**
+ * @brief I2C Write Detect Stop Interrupt Service Routine
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+static void I2C_Write_DetStop_ISR(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ if (i2c_hdl->tx_ctrl.cnt >= i2c_hdl->tx_ctrl.size) {
+ //Disable Detect Stop Interrupt and clear Tx Done
+ __LL_I2C_DetStop_INT_Dis(Instance);
+ __LL_I2C_MST_TxRxDone_Clr(Instance);
+
+ i2c_hdl->tx_ctrl.isr = NULL;
+ i2c_hdl->tx_ctrl.state = I2C_STATE_READY;
+
+ //Tx Complete Callback
+ if (i2c_hdl->user_callback.TxCpltCallback) {
+ i2c_hdl->user_callback.TxCpltCallback();
+ }
+ }
+}
+
+/**
+ * @brief I2C write data handle in Interrupt mode
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+static void I2C_Write_ISR(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ //Write data to TxFIFO
+ if (!__LL_I2C_IsTxFIFOFull(Instance) && i2c_hdl->tx_ctrl.cnt < i2c_hdl->tx_ctrl.size) {
+ __LL_I2C_Dat_Write(Instance, *i2c_hdl->tx_ctrl.buf);
+ i2c_hdl->tx_ctrl.buf++;
+ i2c_hdl->tx_ctrl.cnt++;
+ }
+
+ //Tx Complete
+ if (i2c_hdl->tx_ctrl.cnt >= i2c_hdl->tx_ctrl.size) {
+ //Disable TxFIFO Empty interrupt
+ __LL_I2C_TxFIFOEmpty_INT_Dis(Instance);
+
+ //Switch isr to Detect Stop ISR
+ i2c_hdl->tx_ctrl.isr = I2C_Write_DetStop_ISR;
+
+ //Detect Stop Interrupt Enable
+ __LL_I2C_DetStop_INT_En(Instance);
+ }
+}
+
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief I2C DMA Init
+ * @param dma_user_cfg user dma config pointer
+ * @return DMA_ChannelETypeDef
+ */
+static DMA_ChannelETypeDef I2C_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg)
+{
+ LL_StatusETypeDef ret;
+ DMA_ChannelETypeDef ch;
+
+ if (dma_user_cfg == NULL) {
+ return DMA_CHANNEL_INVALID;
+ }
+
+ /* User DAM channel request */
+ ch = LL_DMA_ChannelRequest();
+
+ if (ch == DMA_CHANNEL_INVALID) {
+ LOG_E("Requset DMA channel Fail!\n");
+ return DMA_CHANNEL_INVALID;
+ }
+
+ /* User DMA init */
+ ret = LL_DMA_Init(DMA, ch, dma_user_cfg);
+
+ if (ret != LL_OK) {
+ LOG_E("DMA LL init fail!\n");
+ LL_DMA_ChannelRelease(ch);
+ return DMA_CHANNEL_INVALID;
+ }
+
+ return ch;
+}
+
+/**
+ * @brief I2C DMA DeInit
+ * @param ch DMA channel to Deinit
+ * @return None
+ */
+static void I2C_DMA_DeInit(DMA_ChannelETypeDef ch)
+{
+ if (ch == DMA_CHANNEL_INVALID) {
+ return;
+ }
+
+ LL_DMA_Stop_IT(DMA, ch);
+ LL_DMA_DeInit(DMA, ch);
+ LL_DMA_ChannelRelease(ch);
+}
+
+/**
+ * @brief I2C Write with DMA process complete callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+static void I2C_Write_DMACplt(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ //Disable Tx DMA Request
+ __LL_I2C_TxDMA_Dis(Instance);
+
+ //DMA DeInit
+ I2C_DMA_DeInit(i2c_hdl->tx_ctrl.dma_ch);
+ i2c_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ i2c_hdl->tx_ctrl.cnt = i2c_hdl->tx_ctrl.size;
+
+ //Switch isr to Detect Stop ISR
+ i2c_hdl->tx_ctrl.isr = I2C_Write_DetStop_ISR;
+
+ //Detect Stop Interrupt Enable
+ __LL_I2C_DetStop_INT_En(Instance);
+}
+
+/**
+ * @brief I2C Read with DMA process complete callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+static void I2C_Read_DMACplt(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ //Disable Rx DMA Request
+ __LL_I2C_RxDMA_Dis(Instance);
+
+ //DMA DeInit
+ I2C_DMA_DeInit(i2c_hdl->rx_ctrl.dma_ch);
+ i2c_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ i2c_hdl->rx_ctrl.cnt = i2c_hdl->rx_ctrl.size;
+
+ //Switch isr to Detect Stop ISR
+ i2c_hdl->rx_ctrl.isr = I2C_Read_DetStop_ISR;
+
+ //Detect Stop Interrupt Enable
+ __LL_I2C_DetStop_INT_En(Instance);
+}
+
+/**
+ * @brief I2C Write with DMA process half complete callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+static void I2C_Write_DMAHalfCplt(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ //Tx Half Complete Callback
+ if (i2c_hdl->user_callback.TxHalfCpltCallback) {
+ i2c_hdl->user_callback.TxHalfCpltCallback();
+ }
+}
+
+/**
+ * @brief I2C Read with DMA process half complete callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+static void I2C_Read_DMAHalfCplt(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ //Rx Half Complete Callback
+ if (i2c_hdl->user_callback.RxHalfCpltCallback) {
+ i2c_hdl->user_callback.RxHalfCpltCallback();
+ }
+}
+
+/**
+ * @brief I2C Write with DMA error callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+static void I2C_Write_DMAError(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ //Disable Tx DMA Request
+ __LL_I2C_TxDMA_Dis(Instance);
+
+ //Tx DMA DeInit
+ I2C_DMA_DeInit(i2c_hdl->tx_ctrl.dma_ch);
+
+ i2c_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ i2c_hdl->tx_ctrl.state = I2C_STATE_READY;
+
+ if (i2c_hdl->user_callback.ErrorCallback) {
+ i2c_hdl->user_callback.ErrorCallback();
+ }
+}
+
+/**
+ * @brief I2C Read with DMA error callback
+ * @param Instance Specifies I2C peripheral
+ * @return None
+ */
+static void I2C_Read_DMAError(I2C_TypeDef *Instance)
+{
+ I2C_HandleTypeDef *i2c_hdl;
+
+ //I2C handle get
+ i2c_hdl = I2C_Handle_Get(Instance);
+
+ if (i2c_hdl == NULL) {
+ LOG_E("Get I2C handle error!\n");
+ return;
+ }
+
+ //Disable Rx DMA Request
+ __LL_I2C_RxDMA_Dis(Instance);
+
+ //Rx DMA DeInit
+ I2C_DMA_DeInit(i2c_hdl->rx_ctrl.dma_ch);
+
+ i2c_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ i2c_hdl->rx_ctrl.state = I2C_STATE_READY;
+
+ if (i2c_hdl->user_callback.ErrorCallback) {
+ i2c_hdl->user_callback.ErrorCallback();
+ }
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LL_I2C_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_iir.c b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_iir.c
new file mode 100644
index 0000000000..b08b0b572b
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_iir.c
@@ -0,0 +1,407 @@
+/**
+ ******************************************************************************
+ * @file tae32g58xx_ll_iir.c
+ * @author MCD Application Team
+ * @brief IIR LL module driver
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. 8M,PLLOut->360M */
+ {8000000, 380000000, 1, 23, 0xC000, PLL_BAND_3, PLL_GVCO_2}, /*!8M,PLLOut->380M */
+ {8000000, 400000000, 1, 25, 0, PLL_BAND_3, PLL_GVCO_2}, /*!8M,PLLOut->400M */
+ {8000000, 420000000, 1, 26, 0x4000, PLL_BAND_3, PLL_GVCO_2}, /*!8M,PLLOut->420M */
+ {8000000, 440000000, 1, 27, 0x8000, PLL_BAND_3, PLL_GVCO_2}, /*!8M,PLLOut->440M */
+ {8000000, 460000000, 1, 28, 0xC000, PLL_BAND_3, PLL_GVCO_2}, /*!8M,PLLOut->460M */
+ {8000000, 480000000, 1, 30, 0, PLL_BAND_3, PLL_GVCO_2}, /*!8M,PLLOut->480M */
+
+ {12000000, 360000000, 1, 15, 0, PLL_BAND_3, PLL_GVCO_2}, /*!12M,PLLOut->360M */
+ {12000000, 380000000, 1, 15, 0xD555, PLL_BAND_3, PLL_GVCO_2}, /*!12M,PLLOut->380M */
+ {12000000, 400000000, 1, 16, 0xAAAA, PLL_BAND_3, PLL_GVCO_2}, /*!12M,PLLOut->400M */
+ {12000000, 420000000, 1, 17, 0x8000, PLL_BAND_3, PLL_GVCO_2}, /*!12M,PLLOut->420M */
+ {12000000, 440000000, 1, 18, 0x5555, PLL_BAND_3, PLL_GVCO_2}, /*!12M,PLLOut->440M */
+ {12000000, 460000000, 1, 19, 0x2AAA, PLL_BAND_3, PLL_GVCO_2}, /*!12M,PLLOut->460M */
+ {12000000, 480000000, 1, 20, 0, PLL_BAND_3, PLL_GVCO_2}, /*!12M,PLLOut->480M */
+
+ {8000000, 100000000, 1, 6, 0x4000, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->100M */
+ {8000000, 110000000, 1, 6, 0xe000, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->110M */
+ {8000000, 120000000, 1, 7, 0x8000, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->120M */
+ {8000000, 130000000, 1, 8, 0x2000, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->130M */
+
+ {8000000, 140000000, 1, 8, 0xc000, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->140M */
+ {8000000, 150000000, 1, 9, 0x6000, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->150M */
+ {8000000, 160000000, 1, 10, 0, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->160M */
+ {8000000, 170000000, 1, 10, 0xa000, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->170M */
+
+ {8000000, 180000000, 1, 11, 0x4000, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->180M */
+ {8000000, 190000000, 1, 11, 0xe000, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->190M */
+ {8000000, 200000000, 1, 12, 0x8000, PLL_BAND_0, PLL_GVCO_2}, /*!8M,PLLOut->200M */
+
+ {8000000, 210000000, 1, 13, 0x2000, PLL_BAND_1, PLL_GVCO_2}, /*!8M,PLLOut->210M */
+ {8000000, 220000000, 1, 13, 0xc000, PLL_BAND_1, PLL_GVCO_2}, /*!8M,PLLOut->220M */
+ {8000000, 230000000, 1, 14, 0x6000, PLL_BAND_1, PLL_GVCO_2}, /*!8M,PLLOut->230M */
+};
+
+/**
+ * @}
+ */
+
+
+/* Private Function Prototypes -----------------------------------------------*/
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+/** @defgroup RCU_LL_Exported_Functions RCU LL Exported Functions
+ * @brief RCU LL Exported Functions
+ * @{
+ */
+
+/** @defgroup RCU_LL_Exported_Functions_Group1 RCU Clock Config Functions
+ * @brief RCU Clock Config Functions
+ * @{
+ */
+
+/**
+ * @brief RCU LL SYSCLK Init
+ * @param Instance Specifies RCU peripheral
+ * @param sysclk_cfg SYSCLK Config Pointer
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_RCU_SysclkInit(RCU_TypeDef *Instance, RCU_SysclkUserCfgTypeDef *sysclk_cfg)
+{
+ RCU_PLLUserCfgTypeDef pll0_cfg;
+ LL_StatusETypeDef ret = LL_ERROR;
+
+ //Assert param
+ assert_param(IS_RCU_ALL_INSTANCE(Instance));
+ assert_param(sysclk_cfg != NULL);
+ assert_param(sysclk_cfg->sysclk_freq);
+
+ if (!IS_RCU_ALL_INSTANCE(Instance) || sysclk_cfg == NULL || !sysclk_cfg->sysclk_freq) {
+ return LL_INVALID;
+ }
+
+ //Auto Freq Config
+ if (sysclk_cfg->sysclk_src == SYSCLK_SRC_PLL0DivClk) {
+ if (sysclk_cfg->pll0clk_src == PLLCLK_SRC_HSE) { //PLL0 CLK Source HSE
+ sysclk_cfg->pll0clk_src_freq = HSE_VALUE;
+ } else if (sysclk_cfg->pll0clk_src == PLLCLK_SRC_HSI) { //PLL0 CLK Source HSI
+ sysclk_cfg->pll0clk_src_freq = HSI_VALUE;
+ }
+ } else if (sysclk_cfg->sysclk_src == SYSCLK_SRC_RC32K) {
+ sysclk_cfg->sysclk_freq = LSI_VALUE;
+ } else if (sysclk_cfg->sysclk_src == SYSCLK_SRC_RC8M) {
+ sysclk_cfg->sysclk_freq = HSI_VALUE;
+ } else if (sysclk_cfg->sysclk_src == SYSCLK_SRC_XOSC) {
+ sysclk_cfg->sysclk_freq = HSE_VALUE;
+ }
+
+ //Check APB0/APB1/AHB Clock Div to be valid
+ if (sysclk_cfg->apb0_clk_div == RCU_CLK_DIV_IVD || sysclk_cfg->apb0_clk_div < RCU_CLK_DIV_2 ||
+ sysclk_cfg->apb0_clk_div > RCU_CLK_DIV_16) {
+ sysclk_cfg->apb0_clk_div = RCU_CLK_DIV_2;
+ }
+
+ if (sysclk_cfg->apb1_clk_div == RCU_CLK_DIV_IVD || sysclk_cfg->apb1_clk_div < RCU_CLK_DIV_2 ||
+ sysclk_cfg->apb1_clk_div > RCU_CLK_DIV_16) {
+ sysclk_cfg->apb1_clk_div = RCU_CLK_DIV_2;
+ }
+
+ if (sysclk_cfg->ahb_clk_div == RCU_CLK_DIV_IVD || sysclk_cfg->ahb_clk_div > RCU_CLK_DIV_64) {
+ sysclk_cfg->ahb_clk_div = RCU_CLK_DIV_1;
+ }
+
+ //RCU Register Write Unlock
+ __LL_RCU_RegWrite_Unlock(Instance);
+
+ //Config SYSCLK
+ switch (sysclk_cfg->sysclk_src) {
+ case SYSCLK_SRC_RC32K:
+ LOG_I("SYSCLK-[%d] source select RC32K.\n", sysclk_cfg->sysclk_freq);
+ __LL_RCU_SysClkSrc_Set(Instance, SYSCLK_SRC_RC32K);
+ ret = LL_OK;
+ break;
+
+ case SYSCLK_SRC_RC8M:
+ LOG_I("SYSCLK-[%d] source select RC8M.\n", sysclk_cfg->sysclk_freq);
+ __LL_RCU_HSI_En(Instance);
+ __LL_RCU_SysClkSrc_Set(Instance, SYSCLK_SRC_RC8M);
+ ret = LL_OK;
+ break;
+
+ case SYSCLK_SRC_PLL0DivClk:
+
+ //SYSCLK Select RC8M Temporary if current SYSCLK select PLL0
+ if ((RCU_SysclkSrcETypeDef)__LL_RCU_SysClkSrc_Get(Instance) == SYSCLK_SRC_PLL0DivClk) {
+ __LL_RCU_HSI_En(Instance);
+ __LL_RCU_SysClkSrc_Set(Instance, SYSCLK_SRC_RC8M);
+ }
+
+ //SYSCLK PLL0 Config
+ pll0_cfg.pll_clk_src = sysclk_cfg->pll0clk_src;
+ pll0_cfg.pll_in_freq = sysclk_cfg->pll0clk_src_freq;
+ pll0_cfg.pll_user_freq = sysclk_cfg->sysclk_freq;
+ ret = LL_RCU_Pll0Cfg(Instance, &pll0_cfg);
+
+ //SYCTRL CTRL Reg Unlock because Pll0Cfg function has lock before return
+ __LL_RCU_RegWrite_Unlock(Instance);
+
+ //SYSCLK Source Select PLL0DivClk
+ if (ret == LL_OK) {
+ LOG_I("SYSCLK-[%d] source select PLL0DivClk.\n", sysclk_cfg->sysclk_freq);
+ __LL_RCU_SysClkSrc_Set(Instance, SYSCLK_SRC_PLL0DivClk);
+ }
+
+ break;
+
+ case SYSCLK_SRC_XOSC:
+ LOG_I("SYSCLK-[%d] source select XOSC.\n", sysclk_cfg->sysclk_freq);
+ __LL_RCU_HSE_En(Instance);
+ __LL_RCU_SysClkSrc_Set(Instance, SYSCLK_SRC_XOSC);
+ ret = LL_OK;
+ break;
+
+ default:
+ LOG_E("SYSCLK Source Select-[%d] Error!\n", sysclk_cfg->sysclk_src);
+ ret = LL_ERROR;
+ break;
+ }
+
+ if (ret == LL_OK) {
+ //APB0/APB1/AHB Clock Div Config
+ __LL_RCU_APB0ClkDiv_Set(Instance, sysclk_cfg->apb0_clk_div);
+ __LL_RCU_APB1ClkDiv_Set(Instance, sysclk_cfg->apb1_clk_div);
+ __LL_RCU_AHBClkDiv_Set(Instance, sysclk_cfg->ahb_clk_div);
+
+ //APB0/APB1/AHB0/AHB1 Bus Clock Enable
+ __LL_RCU_APB0Clk_En(Instance);
+ __LL_RCU_APB1Clk_En(Instance);
+ __LL_RCU_AHB0Clk_En(Instance);
+ __LL_RCU_AHB1Clk_En(Instance);
+ }
+
+ //RCU Register Lock
+ __LL_RCU_RegWrite_Lock(Instance);
+
+ return ret;
+}
+
+/**
+ * @brief RCU LL ADC Clock Config
+ * @param src ADC Clock Source
+ * @param div ADC Clock Div
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_RCU_ADC_ClkCfg(RCU_ClkSrcETypeDef src, RCU_ClkDivETypeDef div)
+{
+ //Assert param
+ assert_param(div > RCU_CLK_DIV_IVD && div <= RCU_CLK_DIV_16);
+
+ if (div <= RCU_CLK_DIV_IVD || div > RCU_CLK_DIV_16) {
+ return LL_INVALID;
+ }
+
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_ADCClkSrc_Set(RCU, src);
+ __LL_RCU_ADCClkDiv_Set(RCU, div);
+ __LL_RCU_RegWrite_Lock(RCU);
+
+ return LL_OK;
+}
+
+/**
+ * @brief RCU LL HRPWM Clock Config
+ * @param src HRPWM Clock Source
+ * @param div HRPWM Clock Div
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_RCU_HRPWM_ClkCfg(RCU_ClkSrcETypeDef src, RCU_ClkDivETypeDef div)
+{
+ //Assert param
+ assert_param(div > RCU_CLK_DIV_IVD && div <= RCU_CLK_DIV_16);
+
+ if (div <= RCU_CLK_DIV_IVD || div > RCU_CLK_DIV_16) {
+ return LL_INVALID;
+ }
+
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWMClkSrc_Set(RCU, src);
+ __LL_RCU_HRPWMClkDiv_Set(RCU, div);
+ __LL_RCU_RegWrite_Lock(RCU);
+
+ return LL_OK;
+}
+
+/**
+ * @brief RCU LL CAN Clock Config
+ * @param src CAN Clock Source
+ * @param div CAN Clock Div
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_RCU_CAN_ClkCfg(RCU_ClkSrcETypeDef src, RCU_ClkDivETypeDef div)
+{
+ //Assert param
+ assert_param(div > RCU_CLK_DIV_IVD && div <= RCU_CLK_DIV_16);
+
+ if (div <= RCU_CLK_DIV_IVD || div > RCU_CLK_DIV_16) {
+ return LL_INVALID;
+ }
+
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_CANClkSrc_Set(RCU, src);
+ __LL_RCU_CANClkDiv_Set(RCU, div);
+ __LL_RCU_RegWrite_Lock(RCU);
+
+ return LL_OK;
+}
+
+/**
+ * @brief RCU LL USB Clock Config
+ * @param src USB Clock Source
+ * @param div USB Clock Div
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_RCU_USB_ClkCfg(RCU_ClkSrcETypeDef src, RCU_ClkDivETypeDef div)
+{
+ //Assert param
+ assert_param(div > RCU_CLK_DIV_IVD && div <= RCU_CLK_DIV_16);
+
+ if (div <= RCU_CLK_DIV_IVD || div > RCU_CLK_DIV_16) {
+ return LL_INVALID;
+ }
+
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_USBClkSrc_Set(RCU, src);
+ __LL_RCU_USBClkDiv_Set(RCU, div);
+ __LL_RCU_RegWrite_Lock(RCU);
+
+ return LL_OK;
+}
+
+/**
+ * @brief RCU LL LPTMR Clock Config
+ * @param src LPTMR Clock Source
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_RCU_LPTMR_ClkCfg(RCU_ClkSrcExETypeDef src)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_LPTMRClkSrc_Set(RCU, src);
+ __LL_RCU_RegWrite_Lock(RCU);
+
+ return LL_OK;
+}
+
+/**
+ * @brief RCU LL SYSCLK freq get
+ * @param None
+ * @return SYSCLK freq
+ */
+uint32_t LL_RCU_SysclkGet(void)
+{
+ return SystemCoreClock;
+}
+
+/**
+ * @brief RCU LL AHB Clock freq get
+ * @note AHB Clock is Div from SYSCLK
+ * @param None
+ * @return AHB Clock freq
+ */
+uint32_t LL_RCU_AHBClkGet(void)
+{
+ return LL_RCU_SysclkGet() / __LL_RCU_AHBClkDiv_Get(RCU);
+}
+
+/**
+ * @brief RCU LL APB0 Clock freq get
+ * @note APB0 Clock is Div from SYSCLK
+ * @param None
+ * @return APB0 Clock freq
+ */
+uint32_t LL_RCU_APB0ClkGet(void)
+{
+ return LL_RCU_SysclkGet() / __LL_RCU_APB0ClkDiv_Get(RCU);
+}
+
+/**
+ * @brief RCU LL APB1 Clock freq get
+ * @note APB1 Clock is Div from SYSCLK
+ * @param None
+ * @return APB1 Clock freq
+ */
+uint32_t LL_RCU_APB1ClkGet(void)
+{
+ return LL_RCU_SysclkGet() / __LL_RCU_APB1ClkDiv_Get(RCU);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RCU_LL_Exported_Functions_Group2 RCU PLL Config Functions
+ * @brief RCU PLL Config Functions
+ * @{
+ */
+
+/**
+ * @brief RCU LL PLL0 Config
+ * @param Instance Specifies RCU peripheral
+ * @param pll0_cfg PLL0 Config Pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_RCU_Pll0Cfg(RCU_TypeDef *Instance, RCU_PLLUserCfgTypeDef *pll0_cfg)
+{
+ uint8_t i;
+ uint16_t pll_int = 0, pll_frac = 0;
+ uint32_t pll_vco_band = 0, pll_vco_gain = 0;
+ RCU_ClkDivETypeDef pre_div = RCU_CLK_DIV_IVD;
+ volatile uint8_t pll0_adc0_set = 0;
+
+ //Assert param
+ assert_param(IS_RCU_ALL_INSTANCE(Instance));
+ assert_param(pll0_cfg != NULL);
+
+ if (!IS_RCU_ALL_INSTANCE(Instance) || pll0_cfg == NULL) {
+ return LL_INVALID;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(rcu_pll_cfg); i++) {
+ if (rcu_pll_cfg[i].pll_in_freq == pll0_cfg->pll_in_freq && rcu_pll_cfg[i].pll_out_freq / 2 == pll0_cfg->pll_user_freq) {
+ pre_div = (RCU_ClkDivETypeDef)rcu_pll_cfg[i].pll_pre_div;
+ pll_int = rcu_pll_cfg[i].pll_int;
+ pll_frac = rcu_pll_cfg[i].pll_frac;
+ pll_vco_band = rcu_pll_cfg[i].pll_vco_band;
+ pll_vco_gain = rcu_pll_cfg[i].pll_vco_gain;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(rcu_pll_cfg)) {
+ if (pll0_cfg->pll_clk_src == PLLCLK_SRC_HSI) {
+ pll0_cfg->pll_in_freq = HSI_VALUE;
+ }
+
+ if (pll0_cfg->pll_in_freq) {
+ double pll_coef = (double)pll0_cfg->pll_user_freq / pll0_cfg->pll_in_freq;
+ pll_int = pll_coef;
+ pll_frac = (pll_coef - pll_int) * 65536;
+
+ pre_div = RCU_CLK_DIV_1;
+ pll_vco_band = PLL_BAND_1;
+ pll_vco_gain = PLL_GVCO_2;
+ } else {
+ LOG_E("Don't match pll0_in_freq-[%" PRIu32 "] to generate pll0_out_freq-[%" PRIu32 "], please add the config to rcu_pll_cfg array!\n", \
+ pll0_cfg->pll_in_freq, pll0_cfg->pll_user_freq);
+ return LL_ERROR;
+ }
+ }
+
+ //RCU CTRL Register Unlock
+ __LL_RCU_RegWrite_Unlock(Instance);
+
+ //ADC0 for PLL0 Band value calibration
+ if (pll0_cfg->pll_user_freq == LL_RCU_SYS_CLK_MAX) {
+ if (pll0_cfg->pll_clk_src == PLLCLK_SRC_HSE && pll0_cfg->pll_in_freq == 8000000) {
+ pll0_adc0_set = 0;
+ } else if (pll0_cfg->pll_clk_src == PLLCLK_SRC_HSI) {
+ pll0_adc0_set = 0;
+ } else {
+ LL_RCU_PLL0Cali_ADC0ClkCfgRst(RCU, RCU_CLK_SRC_RC8M, RCU_CLK_DIV_1);
+ pll0_adc0_set = 1;
+ }
+ } else {
+ LL_RCU_PLL0Cali_ADC0ClkCfgRst(RCU, RCU_CLK_SRC_RC8M, RCU_CLK_DIV_1);
+ pll0_adc0_set = 1;
+ }
+
+ //PLL0 Disable before config
+ __LL_RCU_PLL0_Dis(Instance);
+
+ switch (pll0_cfg->pll_clk_src) {
+ case PLLCLK_SRC_HSE:
+ __LL_RCU_HSE_En(Instance);
+
+ LOG_I("PLL0 CLK Source Select HSE.\n");
+ __LL_RCU_PLL0_RefClk_Set(Instance, PLLCLK_SRC_HSE);
+ break;
+
+ case PLLCLK_SRC_HSI:
+ __LL_RCU_HSI_En(Instance);
+
+ LOG_I("PLL0 CLK Source Select HSI.\n");
+ __LL_RCU_PLL0_RefClk_Set(Instance, PLLCLK_SRC_HSI);
+ break;
+
+ case PLLCLK_SRC_EXT:
+ LOG_I("PLL0 CLK Source Select EXT.\n");
+ __LL_RCU_PLL0_RefClk_Set(Instance, PLLCLK_SRC_EXT);
+ break;
+
+ default:
+ LOG_E("PLL0 CLK Source Select-[%d] Error!\n", pll0_cfg->pll_clk_src);
+ return LL_ERROR;
+ }
+
+ //PLL0 Pre-Div Config
+ if (pre_div == RCU_CLK_DIV_1) {
+ __LL_RCU_PLL0_PreDiv_1(Instance);
+ } else if (pre_div == RCU_CLK_DIV_2) {
+ __LL_RCU_PLL0_PreDiv_2(Instance);
+ } else {
+ LOG_E("PLL0 Pre-Div Config-[%d] Error, set to default 1 division!\n", pre_div);
+ pre_div = RCU_CLK_DIV_1;
+ __LL_RCU_PLL0_PreDiv_1(Instance);
+ }
+
+ //PLL0 LPF Config
+ if (pll0_cfg->pll_in_freq / pre_div > 12000000) {
+ __LL_RCU_PLL0_12MHigh_Set(Instance);
+ } else {
+ __LL_RCU_PLL0_12MLow_Set(Instance);
+ }
+
+ //PLL0 integer/fraction and Gain Config
+ __LL_RCU_PLL0_DivInt_Set(Instance, pll_int);
+ __LL_RCU_PLL0_DivFrac_Set(Instance, pll_frac);
+ __LL_RCU_PLL0_GVCO_Set(Instance, pll_vco_gain);
+
+ //PLL0 Band value calibration
+ if (pll0_cfg->pll_user_freq == LL_RCU_SYS_CLK_MAX) { //400000000/2
+ if (pll0_cfg->pll_clk_src == PLLCLK_SRC_HSE && pll0_cfg->pll_in_freq == 8000000) {
+ pll_vco_band = __LL_SYSCTRL_XOSC_PLL0BandValue_Get(SYSCTRL);
+ } else if (pll0_cfg->pll_clk_src == PLLCLK_SRC_HSI) {
+ pll_vco_band = __LL_SYSCTRL_RC8M_PLL0BandValue_Get(SYSCTRL);
+ } else {
+ pll_vco_band = LL_RCU_PLL0Cali(RCU);
+ __LL_RCU_RegWrite_Unlock(Instance); //SYCTRL CTRL Reg Unlock because PLL0Cali function has lock before return
+ }
+ } else {
+ pll_vco_band = LL_RCU_PLL0Cali(RCU);
+ __LL_RCU_RegWrite_Unlock(Instance); //SYCTRL CTRL Reg Unlock because PLL0Cali function has lock before return
+ }
+
+ if (pll0_adc0_set) {
+ LL_RCU_PLL0Cali_ADC0ClkRstDis(RCU);
+ }
+
+ //PLL0 VCO Band Config and Enable
+ __LL_RCU_PLL0_Band_Set(Instance, pll_vco_band);
+ __LL_RCU_PLL0_En(Instance);
+
+ //Wait for PLL0 Lock
+ LOG_D("Wait for PLL0 lock output\n");
+
+ while (!__LL_RCU_PLL0_IsLocked(Instance))
+ ;
+
+ LOG_D("PLL0 lock Success\n");
+
+ //RCU Register Lock
+ __LL_RCU_RegWrite_Lock(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RCU_LL_Exported_Functions_Group3 RCU Peripherals Clock and Reset control Functions
+ * @brief RCU Peripherals Clock and Reset control Functions
+ * @{
+ */
+
+/**
+ * @brief RCU EFLASH Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_EFLASH_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_EFLASHClk_En(RCU);
+ __LL_RCU_EFLASHSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU EFLASH Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_EFLASH_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_EFLASHClk_Dis(RCU);
+ __LL_RCU_EFLASHSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU DMA Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_DMA_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_DMAClk_En(RCU);
+ __LL_RCU_DMASoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU DMA Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_DMA_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_DMAClk_Dis(RCU);
+ __LL_RCU_DMASoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU CORDIC Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_CORDIC_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_CORDICClk_En(RCU);
+ __LL_RCU_CORDICSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU CORDIC Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_CORDIC_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_CORDICClk_Dis(RCU);
+ __LL_RCU_CORDICSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR0_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR0Clk_En(RCU);
+ __LL_RCU_TMR0SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR0_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR0Clk_Dis(RCU);
+ __LL_RCU_TMR0SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR1_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR1Clk_En(RCU);
+ __LL_RCU_TMR1SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR1_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR1Clk_Dis(RCU);
+ __LL_RCU_TMR1SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR2 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR2_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR2Clk_En(RCU);
+ __LL_RCU_TMR2SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR2 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR2_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR2Clk_Dis(RCU);
+ __LL_RCU_TMR2SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR3 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR3_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR3Clk_En(RCU);
+ __LL_RCU_TMR3SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR3 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR3_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR3Clk_Dis(RCU);
+ __LL_RCU_TMR3SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR4 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR4_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR4Clk_En(RCU);
+ __LL_RCU_TMR4SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR4 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR4_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR4Clk_Dis(RCU);
+ __LL_RCU_TMR4SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR7 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR7_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR7Clk_En(RCU);
+ __LL_RCU_TMR7SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR7 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR7_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR7Clk_Dis(RCU);
+ __LL_RCU_TMR7SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR8 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR8_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR8Clk_En(RCU);
+ __LL_RCU_TMR8SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR8 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR8_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR8Clk_Dis(RCU);
+ __LL_RCU_TMR8SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR9 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR9_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR9Clk_En(RCU);
+ __LL_RCU_TMR9SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR9 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR9_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR9Clk_Dis(RCU);
+ __LL_RCU_TMR9SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR10 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR10_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR10Clk_En(RCU);
+ __LL_RCU_TMR10SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR10 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR10_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR10Clk_Dis(RCU);
+ __LL_RCU_TMR10SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR6 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR6_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR6Clk_En(RCU);
+ __LL_RCU_TMR6FunClk_En(RCU);
+ __LL_RCU_TMR6SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU TMR6 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_TMR6_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_TMR6Clk_Dis(RCU);
+ __LL_RCU_TMR6FunClk_Dis(RCU);
+ __LL_RCU_TMR6SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU QEI0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_QEI0_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_QEI0Clk_En(RCU);
+ __LL_RCU_QEI0SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU QEI0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_QEI0_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_QEI0Clk_Dis(RCU);
+ __LL_RCU_QEI0SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU QEI1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_QEI1_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_QEI1Clk_En(RCU);
+ __LL_RCU_QEI1SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU QEI1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_QEI1_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_QEI1Clk_Dis(RCU);
+ __LL_RCU_QEI1SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU QEI2 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_QEI2_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_QEI2Clk_En(RCU);
+ __LL_RCU_QEI2SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU QEI2 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_QEI2_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_QEI2Clk_Dis(RCU);
+ __LL_RCU_QEI2SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR0_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR0Clk_En(RCU);
+ __LL_RCU_IIR0SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR0_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR0Clk_Dis(RCU);
+ __LL_RCU_IIR0SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR1_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR1Clk_En(RCU);
+ __LL_RCU_IIR1SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR1_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR1Clk_Dis(RCU);
+ __LL_RCU_IIR1SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR2 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR2_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR2Clk_En(RCU);
+ __LL_RCU_IIR2SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR2 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR2_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR2Clk_Dis(RCU);
+ __LL_RCU_IIR2SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR3 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR3_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR3Clk_En(RCU);
+ __LL_RCU_IIR3SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR3 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR3_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR3Clk_Dis(RCU);
+ __LL_RCU_IIR3SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR4 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR4_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR4Clk_En(RCU);
+ __LL_RCU_IIR4SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR4 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR4_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR4Clk_Dis(RCU);
+ __LL_RCU_IIR4SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR5 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR5_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR5Clk_En(RCU);
+ __LL_RCU_IIR5SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU IIR5 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_IIR5_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_IIR5Clk_Dis(RCU);
+ __LL_RCU_IIR5SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+
+/**
+ * @brief RCU GPIOA Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOA_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIOAClk_En(RCU);
+ __LL_RCU_GPIOASoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOA Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOA_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIOAClk_Dis(RCU);
+ __LL_RCU_GPIOASoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOB Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOB_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIOBClk_En(RCU);
+ __LL_RCU_GPIOBSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOB Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOB_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIOBClk_Dis(RCU);
+ __LL_RCU_GPIOBSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOC Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOC_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIOCClk_En(RCU);
+ __LL_RCU_GPIOCSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOC Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOC_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIOCClk_Dis(RCU);
+ __LL_RCU_GPIOCSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOD Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOD_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIODClk_En(RCU);
+ __LL_RCU_GPIODSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOD Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOD_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIODClk_Dis(RCU);
+ __LL_RCU_GPIODSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOE Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOE_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIOEClk_En(RCU);
+ __LL_RCU_GPIOESoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOE Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOE_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIOEClk_Dis(RCU);
+ __LL_RCU_GPIOESoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOF Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOF_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIOFClk_En(RCU);
+ __LL_RCU_GPIOFSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU GPIOF Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_GPIOF_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_GPIOFClk_Dis(RCU);
+ __LL_RCU_GPIOFSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU I2C0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_I2C0_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_I2C0Clk_En(RCU);
+ __LL_RCU_I2C0SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU I2C0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_I2C0_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_I2C0Clk_Dis(RCU);
+ __LL_RCU_I2C0SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU I2C1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_I2C1_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_I2C1Clk_En(RCU);
+ __LL_RCU_I2C1SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU I2C1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_I2C1_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_I2C1Clk_Dis(RCU);
+ __LL_RCU_I2C1SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU I2C2 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_I2C2_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_I2C2Clk_En(RCU);
+ __LL_RCU_I2C2SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU I2C2 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_I2C2_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_I2C2Clk_Dis(RCU);
+ __LL_RCU_I2C2SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU UART0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_UART0_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_UART0Clk_En(RCU);
+ __LL_RCU_UART0SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU UART0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_UART0_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_UART0Clk_Dis(RCU);
+ __LL_RCU_UART0SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU UART1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_UART1_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_UART1Clk_En(RCU);
+ __LL_RCU_UART1SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU UART1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_UART1_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_UART1Clk_Dis(RCU);
+ __LL_RCU_UART1SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU UART2 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_UART2_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_UART2Clk_En(RCU);
+ __LL_RCU_UART2SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU UART2 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_UART2_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_UART2Clk_Dis(RCU);
+ __LL_RCU_UART2SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU UART3 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_UART3_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_UART3Clk_En(RCU);
+ __LL_RCU_UART3SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU UART3 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_UART3_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_UART3Clk_Dis(RCU);
+ __LL_RCU_UART3SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU UART4 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_UART4_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_UART4Clk_En(RCU);
+ __LL_RCU_UART4SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU UART4 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_UART4_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_UART4Clk_Dis(RCU);
+ __LL_RCU_UART4SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU SPI0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_SPI0_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_SPI0Clk_En(RCU);
+ __LL_RCU_SPI0SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU SPI0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_SPI0_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_SPI0Clk_Dis(RCU);
+ __LL_RCU_SPI0SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU SPI1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_SPI1_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_SPI1Clk_En(RCU);
+ __LL_RCU_SPI1SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU SPI1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_SPI1_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_SPI1Clk_Dis(RCU);
+ __LL_RCU_SPI1SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU CAN0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_CAN0_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_CAN0Clk_En(RCU);
+ __LL_RCU_CAN0FunClk_En(RCU);
+ __LL_RCU_CAN0SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU CAN0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_CAN0_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_CAN0Clk_Dis(RCU);
+ __LL_RCU_CAN0FunClk_Dis(RCU);
+ __LL_RCU_CAN0SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU CAN1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_CAN1_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_CAN1Clk_En(RCU);
+ __LL_RCU_CAN1FunClk_En(RCU);
+ __LL_RCU_CAN1SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU CAN1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_CAN1_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_CAN1Clk_Dis(RCU);
+ __LL_RCU_CAN1FunClk_Dis(RCU);
+ __LL_RCU_CAN1SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU USB Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_USB_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_USBClk_En(RCU);
+ __LL_RCU_USBFunClk_En(RCU);
+ __LL_RCU_USBSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU USB Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_USB_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_USBClk_Dis(RCU);
+ __LL_RCU_USBFunClk_Dis(RCU);
+ __LL_RCU_USBSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU XIF Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_XIF_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_XIFClk_En(RCU);
+ __LL_RCU_XIFSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU XIF Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_XIF_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_XIFClk_Dis(RCU);
+ __LL_RCU_XIFSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+
+/**
+ * @brief RCU ADC0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_ADC0_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_ADC0Clk_En(RCU);
+ __LL_RCU_ADC0FunClk_En(RCU);
+ __LL_RCU_ADCSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU ADC0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_ADC0_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_ADC0Clk_Dis(RCU);
+ __LL_RCU_ADC0FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsADCClkEn(RCU)) {
+ __LL_RCU_ADCSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU ADC1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_ADC1_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_ADC1Clk_En(RCU);
+ __LL_RCU_ADC1FunClk_En(RCU);
+ __LL_RCU_ADCSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU ADC1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_ADC1_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_ADC1Clk_Dis(RCU);
+ __LL_RCU_ADC1FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsADCClkEn(RCU)) {
+ __LL_RCU_ADCSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU ADC2 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_ADC2_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_ADC2Clk_En(RCU);
+ __LL_RCU_ADC2FunClk_En(RCU);
+ __LL_RCU_ADCSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU ADC2 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_ADC2_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_ADC2Clk_Dis(RCU);
+ __LL_RCU_ADC2FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsADCClkEn(RCU)) {
+ __LL_RCU_ADCSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU ADC3 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_ADC3_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_ADC3Clk_En(RCU);
+ __LL_RCU_ADC3FunClk_En(RCU);
+ __LL_RCU_ADCSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU ADC3 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_ADC3_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_ADC3Clk_Dis(RCU);
+ __LL_RCU_ADC3FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsADCClkEn(RCU)) {
+ __LL_RCU_ADCSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU DAC Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_DAC_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_DACClk_En(RCU);
+ __LL_RCU_DACSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU DAC Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_DAC_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_DACClk_Dis(RCU);
+ __LL_RCU_DACSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU CMP Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_CMP_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_CMPClk_En(RCU);
+ __LL_RCU_CMPSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU CMP Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_CMP_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_CMPClk_Dis(RCU);
+ __LL_RCU_CMPSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM0Clk_En(RCU);
+ __LL_RCU_HRPWM1Clk_En(RCU);
+ __LL_RCU_HRPWM2Clk_En(RCU);
+ __LL_RCU_HRPWM3Clk_En(RCU);
+ __LL_RCU_HRPWM4Clk_En(RCU);
+ __LL_RCU_HRPWM5Clk_En(RCU);
+ __LL_RCU_HRPWM6Clk_En(RCU);
+ __LL_RCU_HRPWM7Clk_En(RCU);
+ __LL_RCU_HRPWM0FunClk_En(RCU);
+ __LL_RCU_HRPWM1FunClk_En(RCU);
+ __LL_RCU_HRPWM2FunClk_En(RCU);
+ __LL_RCU_HRPWM3FunClk_En(RCU);
+ __LL_RCU_HRPWM4FunClk_En(RCU);
+ __LL_RCU_HRPWM5FunClk_En(RCU);
+ __LL_RCU_HRPWM6FunClk_En(RCU);
+ __LL_RCU_HRPWM7FunClk_En(RCU);
+ __LL_RCU_HRPWMSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM0Clk_Dis(RCU);
+ __LL_RCU_HRPWM1Clk_Dis(RCU);
+ __LL_RCU_HRPWM2Clk_Dis(RCU);
+ __LL_RCU_HRPWM3Clk_Dis(RCU);
+ __LL_RCU_HRPWM4Clk_Dis(RCU);
+ __LL_RCU_HRPWM5Clk_Dis(RCU);
+ __LL_RCU_HRPWM6Clk_Dis(RCU);
+ __LL_RCU_HRPWM7Clk_Dis(RCU);
+ __LL_RCU_HRPWM0FunClk_Dis(RCU);
+ __LL_RCU_HRPWM1FunClk_Dis(RCU);
+ __LL_RCU_HRPWM2FunClk_Dis(RCU);
+ __LL_RCU_HRPWM3FunClk_Dis(RCU);
+ __LL_RCU_HRPWM4FunClk_Dis(RCU);
+ __LL_RCU_HRPWM5FunClk_Dis(RCU);
+ __LL_RCU_HRPWM6FunClk_Dis(RCU);
+ __LL_RCU_HRPWM7FunClk_Dis(RCU);
+ __LL_RCU_HRPWMSoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM0_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM0Clk_En(RCU);
+ __LL_RCU_HRPWM0FunClk_En(RCU);
+ __LL_RCU_HRPWMSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM0_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM0Clk_Dis(RCU);
+ __LL_RCU_HRPWM0FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsHRPWMClkEn(RCU)) {
+ __LL_RCU_HRPWMSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM1_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM1Clk_En(RCU);
+ __LL_RCU_HRPWM1FunClk_En(RCU);
+ __LL_RCU_HRPWMSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM1_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM1Clk_Dis(RCU);
+ __LL_RCU_HRPWM1FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsHRPWMClkEn(RCU)) {
+ __LL_RCU_HRPWMSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM2 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM2_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM2Clk_En(RCU);
+ __LL_RCU_HRPWM2FunClk_En(RCU);
+ __LL_RCU_HRPWMSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM2 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM2_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM2Clk_Dis(RCU);
+ __LL_RCU_HRPWM2FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsHRPWMClkEn(RCU)) {
+ __LL_RCU_HRPWMSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM3 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM3_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM3Clk_En(RCU);
+ __LL_RCU_HRPWM3FunClk_En(RCU);
+ __LL_RCU_HRPWMSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM3 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM3_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM3Clk_Dis(RCU);
+ __LL_RCU_HRPWM3FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsHRPWMClkEn(RCU)) {
+ __LL_RCU_HRPWMSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM4 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM4_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM4Clk_En(RCU);
+ __LL_RCU_HRPWM4FunClk_En(RCU);
+ __LL_RCU_HRPWMSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM4 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM4_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM4Clk_Dis(RCU);
+ __LL_RCU_HRPWM4FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsHRPWMClkEn(RCU)) {
+ __LL_RCU_HRPWMSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM5 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM5_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM5Clk_En(RCU);
+ __LL_RCU_HRPWM5FunClk_En(RCU);
+ __LL_RCU_HRPWMSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM5 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM5_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM5Clk_Dis(RCU);
+ __LL_RCU_HRPWM5FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsHRPWMClkEn(RCU)) {
+ __LL_RCU_HRPWMSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM6 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM6_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM6Clk_En(RCU);
+ __LL_RCU_HRPWM6FunClk_En(RCU);
+ __LL_RCU_HRPWMSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM6 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM6_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM6Clk_Dis(RCU);
+ __LL_RCU_HRPWM6FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsHRPWMClkEn(RCU)) {
+ __LL_RCU_HRPWMSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM7 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM7_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM7Clk_En(RCU);
+ __LL_RCU_HRPWM7FunClk_En(RCU);
+ __LL_RCU_HRPWMSoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU HRPWM7 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_HRPWM7_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_HRPWM7Clk_Dis(RCU);
+ __LL_RCU_HRPWM7FunClk_Dis(RCU);
+
+ if (!__LL_RCU_IsHRPWMClkEn(RCU)) {
+ __LL_RCU_HRPWMSoftRst_Assert(RCU);
+ }
+
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU PDM0 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_PDM0_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_PDM0Clk_En(RCU);
+ __LL_RCU_PDM0SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU PDM0 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_PDM0_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_PDM0Clk_Dis(RCU);
+ __LL_RCU_PDM0SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU PDM1 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_PDM1_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_PDM1Clk_En(RCU);
+ __LL_RCU_PDM1SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU PDM1 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_PDM1_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_PDM1Clk_Dis(RCU);
+ __LL_RCU_PDM1SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU PDM2 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_PDM2_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_PDM2Clk_En(RCU);
+ __LL_RCU_PDM2SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU PDM2 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_PDM2_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_PDM2Clk_Dis(RCU);
+ __LL_RCU_PDM2SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU PDM3 Bus Clock Enable and Reset Release
+ * @param None
+ * @return None
+ */
+void LL_RCU_PDM3_ClkEnRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_PDM3Clk_En(RCU);
+ __LL_RCU_PDM3SoftRst_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU PDM3 Bus Clock Disable and Reset Assert
+ * @param None
+ * @return None
+ */
+void LL_RCU_PDM3_ClkDisRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_PDM3Clk_Dis(RCU);
+ __LL_RCU_PDM3SoftRst_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+
+/**
+ * @brief RCU LL all peripheral reset assert
+ * @note All peripheral include system bus(AHB0/AHB1/APB0/APB1)
+ * @param None
+ * @return None
+ */
+void LL_RCU_AllPeriphRstAssert(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_APB0SoftRstAll_Assert(RCU);
+ __LL_RCU_APB1SoftRstAll_Assert(RCU);
+ __LL_RCU_AHB0SoftRstAll_Assert(RCU);
+ __LL_RCU_AHB1SoftRstAll_Assert(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @brief RCU LL all peripheral reset release
+ * @note All peripheral include system bus(AHB0/AHB1/APB0/APB1)
+ * @param None
+ * @return None
+ */
+void LL_RCU_AllPeriphRstRelease(void)
+{
+ __LL_RCU_RegWrite_Unlock(RCU);
+ __LL_RCU_APB0SoftRstAll_Release(RCU);
+ __LL_RCU_APB1SoftRstAll_Release(RCU);
+ __LL_RCU_AHB0SoftRstAll_Release(RCU);
+ __LL_RCU_AHB1SoftRstAll_Release(RCU);
+ __LL_RCU_RegWrite_Lock(RCU);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private Functions ---------------------------------------------------------*/
+/** @addtogroup RCU_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief ADC0 Clock Config and Soft Reset Release for PLL Calibrate
+ * @note Unlock the RCU register before use
+ * @param Instance Specifies RCU peripheral
+ * @param src ADC Clock Source
+ * @param div ADC Clock Div
+ * @return None
+ */
+static void LL_RCU_PLL0Cali_ADC0ClkCfgRst(RCU_TypeDef *Instance, RCU_ClkSrcETypeDef src, RCU_ClkDivETypeDef div)
+{
+ //Clock Disable
+ __LL_RCU_ADC0Clk_Dis(Instance);
+ __LL_RCU_ADC0FunClk_Dis(Instance);
+
+ //Clock Config
+ __LL_RCU_ADCClkSrc_Set(Instance, src);
+ __LL_RCU_ADCClkDiv_Set(Instance, div);
+
+ //Clock Enable
+ __LL_RCU_ADC0Clk_En(Instance);
+ __LL_RCU_ADC0FunClk_En(Instance);
+
+ //ADC Reset
+ __LL_RCU_ADCSoftRst_Assert(Instance);
+ __LL_RCU_ADCSoftRst_Release(Instance);
+}
+
+/**
+ * @brief ADC0 Clock Disable and Soft Reset Release for PLL Calibrate
+ * @note Unlock the RCU register before use
+ * @param Instance Specifies RCU peripheral
+ * @return None
+ */
+static void LL_RCU_PLL0Cali_ADC0ClkRstDis(RCU_TypeDef *Instance)
+{
+ //ADC Reset
+ __LL_RCU_ADCSoftRst_Assert(Instance);
+ __LL_RCU_ADCSoftRst_Release(Instance);
+
+ //Clock Disable
+ __LL_RCU_ADC0Clk_Dis(Instance);
+ __LL_RCU_ADC0FunClk_Dis(Instance);
+}
+
+/**
+ * @brief RCU LL PLL0 calibrate
+ * @param Instance Specifies RCU peripheral
+ * @return Fitband
+ */
+static uint8_t LL_RCU_PLL0Cali(RCU_TypeDef *Instance)
+{
+ uint32_t CPOUT_Vout[4];
+ uint8_t FitBand = 0;
+ uint32_t atcr = READ_REG(SYSCTRL->ATCR);
+ uint32_t sysatr = READ_REG(SYSCTRL->SYSATR);
+ uint8_t pll0_status = READ_BIT(RCU->PLL0CR, RCU_PLL0CR_EN_Msk);
+ int32_t Trim_Value;
+ uint32_t cr_store = 0;
+
+ //Assert param
+ assert_param(IS_RCU_ALL_INSTANCE(Instance));
+
+ if (!IS_RCU_ALL_INSTANCE(Instance)) {
+ return 0;
+ }
+
+ //RCU/SYSCTRL Reg Unlock
+ __LL_RCU_RegWrite_Unlock(Instance);
+ __LL_SYSCTRL_SysRegWrite_Unlock(SYSCTRL);
+ __LL_SYSCTRL_SpRegWrite_Unlock(SYSCTRL);
+
+ //Vref Buf output 2.5V
+ __LL_SYSCTRL_VREFBUFOutputVol_Set(SYSCTRL, SYSCTRL_VREFBUF_VOL_2V5);
+ __LL_SYSCTRL_VREFBUF_En(SYSCTRL);
+
+ //ADC BUF select VRIP2
+ __LL_SYSCTRL_ADCBuf_En(SYSCTRL);
+ __LL_SYSCTRL_ADCBufSrc_Sel(SYSCTRL, 0x3);
+
+ //Enable DWT
+ cr_store = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk;
+ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+
+ //delay 1.2ms
+ DWT->CYCCNT = (uint32_t)0U;
+ DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+
+ while (DWT->CYCCNT < (uint32_t)(((float)HSI_VALUE / 1000000) * 1200));
+
+ //ADC0 Config
+ WRITE_REG(ADC0->CFGR0, 0x00808321);
+ WRITE_REG(ADC0->CFGR1, 0x0000002B);
+ WRITE_REG(ADC0->SIGSEL, 0);
+ WRITE_REG(ADC0->SMPR2, 0x20);
+ WRITE_REG(ADC0->SQR0, 0x00000011);
+
+ ADC0->CR |= BIT(0);
+
+ while (((ADC0->ISR & BIT(8)) >> 8U) != 1);
+
+ ADC0->CR |= BIT(2);
+
+ //ADC REG Start Conversion
+ SET_BIT(ADC0->DISR, BIT(17));
+
+ while (((ADC0->DISR & BIT(17)) >> 17U) != 1);
+
+ Trim_Value = ADC0->DR;
+ SET_BIT(ADC0->DISR, BIT(17));
+
+ //ADC BUF select PLL0 CPOUT
+ __LL_SYSCTRL_ADCBufSrc_Sel(SYSCTRL, 0x12);
+
+ //PLL0 VCODET Enable
+ SET_BIT(Instance->PLL0CR, BIT(17));
+
+ for (uint8_t pll_band_index = 0; pll_band_index < 4; pll_band_index++) {
+ __LL_RCU_PLL0_Dis(Instance);
+ __LL_RCU_PLL0_Band_Set(Instance, pll_band_index);
+ __LL_RCU_PLL0_En(Instance);
+
+ //delay 1.5ms
+ DWT->CYCCNT = (uint32_t)0U;
+ DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+
+ while (DWT->CYCCNT < (uint32_t)(((float)HSI_VALUE / 1000000) * 1500));
+
+ CPOUT_Vout[pll_band_index] = abs((int)ADC0->DR - Trim_Value / 2);
+ SET_BIT(ADC0->DISR, BIT(17));
+ }
+
+ //Restore PLL0 status
+ MODIFY_REG(RCU->PLL0CR, RCU_PLL0CR_EN_Msk, pll0_status);
+
+ //PLL0 VCODET Disable
+ CLEAR_BIT(Instance->PLL0CR, BIT(17));
+
+ //Disable DWT
+ DWT->CTRL &= ~DWT_CTRL_CYCCNTENA_Msk;
+ CoreDebug->DEMCR |= cr_store;
+
+ for (uint8_t pll_band_index = 0; pll_band_index < 4; pll_band_index++) {
+ if (CPOUT_Vout[pll_band_index] < CPOUT_Vout[FitBand]) {
+ FitBand = pll_band_index;
+ }
+ }
+
+ //Stop ADC
+ SET_BIT(ADC0->CR, 0x01UL);
+
+ //Restore SYSATR Reg
+ WRITE_REG(SYSCTRL->SYSATR, sysatr);
+
+ //Restore ATCR Reg
+ WRITE_REG(SYSCTRL->ATCR, atcr);
+
+ //RCU/SYSCTRL Reg Lock
+ __LL_RCU_RegWrite_Lock(Instance);
+ __LL_SYSCTRL_SysRegWrite_Lock(SYSCTRL);
+ __LL_SYSCTRL_SpRegWrite_Lock(SYSCTRL);
+
+ return FitBand;
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_spi.c b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_spi.c
new file mode 100644
index 0000000000..a22302eae5
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_spi.c
@@ -0,0 +1,2341 @@
+/**
+ ******************************************************************************
+ * @file tae32g58xx_ll_spi.c
+ * @author MCD Application Team
+ * @brief SPI LL module driver
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+
+
+#define DBG_TAG "SPI LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae_dbg.h"
+
+
+/** @addtogroup TAE32G58xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup SPI_LL SPI LL
+ * @brief SPI LL module driver
+ * @{
+ */
+
+#ifdef LL_SPI_MODULE_ENABLED
+
+/* Private Constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+/* Private Types -------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Types SPI LL Private Types
+ * @brief SPI LL Private Types
+ * @{
+ */
+
+/**
+ * @brief SPI IRQ callback function type definition
+ */
+typedef void (*SPI_LLIRQCallback)(SPI_TypeDef *Instance);
+
+/**
+ * @brief SPI Transmission definition
+ */
+typedef struct __SPI_TransTypeDef {
+ uint8_t *buf; /*!< SPI Transmission Buffer Pointer */
+ uint16_t size; /*!< SPI Transmission Buffer Size */
+ uint16_t cnt; /*!< SPI Transmission Counter */
+ SPI_LLIRQCallback isr; /*!< Interrupt Service Routine */
+ SPI_StateETypeDef state; /*!< SPI Transmission State */
+#ifdef LL_DMA_MODULE_ENABLED
+ DMA_ChannelETypeDef dma_ch; /*!< SPI Transmission DMA Channel */
+#endif
+} SPI_TransTypeDef;
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef {
+ SPI_RoleETypeDef role; /*!< SPI Role */
+
+ volatile SPI_TransTypeDef tx_ctrl; /*!< SPI Transmission Tx Control */
+ volatile SPI_TransTypeDef rx_ctrl; /*!< SPI Transmission Rx Control */
+
+ SPI_UserCallbackTypeDef user_callback; /*!< User Callback */
+} SPI_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Private Variables ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Variables SPI LL Private Variables
+ * @brief SPI LL Private Variables
+ * @{
+ */
+
+/**
+ * @brief Default SPI LL Config
+ */
+static const SPI_LLCfgTypeDef spi_ll_cfg_def = {
+ .wire_mode = SPI_WIRE_MODE_4,
+ .cs_mode = SPI_CS_MODE_CONTINUE,
+ .cs_pol = SPI_CS_POL_INACT_HIGH,
+ .cs_input_mode = SPI_CS_INPUT_MODE_GPIO,
+ .bit_order = SPI_BIT_ORDER_MSB,
+
+ .cs_sw_out_en = true,
+ .mosi_miso_swap_en = false,
+ .tx_fifo_empty_thres = 1, // 0~15
+ .rx_fifo_full_thres = 1, // 1~16
+ .mst_rx_delay = 0, // 0~7
+ .mst_ss_idleness = 1, //1~32
+ .mst_inter_dat_idleness = 1,//1~32, while 1 means no delay
+
+ .loopback_en = false,
+};
+
+/**
+ * @brief SPI Handle global variable
+ */
+static SPI_HandleTypeDef spi_hdl_global[SPI_INSTANCE_NUMS];
+
+/**
+ * @}
+ */
+
+
+/* Private Function Prototypes -----------------------------------------------*/
+/** @defgroup SPI_LL_Private_Functions SPI LL Private Functions
+ * @brief SPI LL Private Functions
+ * @{
+ */
+static SPI_HandleTypeDef *SPI_Handle_Get(SPI_TypeDef *Instance);
+
+static void SPI_CloseRx_ISR(SPI_TypeDef *Instance);
+
+static void SPI_TxISR_8BIT(SPI_TypeDef *Instance);
+static void SPI_TxISR_16BIT(SPI_TypeDef *Instance);
+static void SPI_RxISR_8BIT(SPI_TypeDef *Instance);
+static void SPI_RxISR_16BIT(SPI_TypeDef *Instance);
+static void SPI_TxDone_ISR(SPI_TypeDef *Instance);
+
+#ifdef LL_DMA_MODULE_ENABLED
+ static DMA_ChannelETypeDef SPI_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg);
+ static void SPI_DMA_DeInit(DMA_ChannelETypeDef ch);
+ static void SPI_DMATransmitCplt(SPI_TypeDef *Instance);
+ static void SPI_DMAReceiveCplt(SPI_TypeDef *Instance);
+ static void SPI_DMAHalfTransmitCplt(SPI_TypeDef *Instance);
+ static void SPI_DMAHalfReceiveCplt(SPI_TypeDef *Instance);
+ static void SPI_DMATransmitError(SPI_TypeDef *Instance);
+ static void SPI_DMAReceiveError(SPI_TypeDef *Instance);
+#endif
+/**
+ * @}
+ */
+
+
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI LL Exported Functions
+ * @brief SPI LL Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_LL_Exported_Functions_Group1 SPI Init and DeInit Function
+ * @brief SPI Init and DeInit function
+ * @{
+ */
+
+/**
+ * @brief SPI LL Init
+ * @param Instance Specifies SPI peripheral
+ * @param user_cfg SPI User Config Pointer
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_SPI_Init(SPI_TypeDef *Instance, SPI_UserCfgTypeDef *user_cfg)
+{
+ SPI_HandleTypeDef *spi_hdl;
+ SPI_LLCfgTypeDef *ll_cfg;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+ assert_param(user_cfg != NULL);
+ assert_param(user_cfg->baudrate);
+
+ if (!IS_SPI_ALL_INSTANCE(Instance) || user_cfg == NULL || !user_cfg->baudrate) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ } else if (spi_hdl->tx_ctrl.state != SPI_STATE_RESET || spi_hdl->rx_ctrl.state != SPI_STATE_RESET) {
+ LOG_E("This SPI[0x%08" PRIx32 "] is being used!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ spi_hdl->tx_ctrl.state = SPI_STATE_BUSY;
+ spi_hdl->rx_ctrl.state = SPI_STATE_BUSY;
+
+ //LL config pointer config
+ LL_FUNC_ALTER(user_cfg->ll_cfg == NULL, ll_cfg = (SPI_LLCfgTypeDef *)&spi_ll_cfg_def, ll_cfg = user_cfg->ll_cfg);
+
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_SPI_MspInit(Instance);
+ __LL_SPI_CS_SwOut_Inactive(Instance);
+
+ //Module disable and TX/RX FIFO reset
+ __LL_SPI_Dis(Instance);
+ __LL_SPI_TxFIFO_Reset(Instance);
+ __LL_SPI_RxFIFO_Reset(Instance);
+
+ //LL Config
+ __LL_SPI_WireMode_Set(Instance, ll_cfg->wire_mode);
+ __LL_SPI_CSMode_Set(Instance, ll_cfg->cs_mode);
+ __LL_SPI_CSPol_Set(Instance, ll_cfg->cs_pol);
+ __LL_SPI_BitOrder_Set(Instance, ll_cfg->bit_order);
+ __LL_SPI_TxFIFOEmptyThres_Set(Instance, ll_cfg->tx_fifo_empty_thres);
+ __LL_SPI_RxFIFOFullThres_Set(Instance, ll_cfg->rx_fifo_full_thres);
+ __LL_SPI_Mst_RxDelay_Set(Instance, ll_cfg->mst_rx_delay);
+ __LL_SPI_CS_SlvInputMode_Set(Instance, ll_cfg->cs_input_mode);
+ __LL_SPI_Mst_SSIdleness_Set(Instance, ll_cfg->mst_ss_idleness);
+ __LL_SPI_Mst_InterDatIdleness_Set(Instance, ll_cfg->mst_inter_dat_idleness);
+ LL_FUNC_ALTER(ll_cfg->cs_sw_out_en, __LL_SPI_CS_SwOut_En(Instance), __LL_SPI_CS_SwOut_Dis(Instance));
+ LL_FUNC_ALTER(ll_cfg->mosi_miso_swap_en, __LL_SPI_MOSI_MISO_Swap_En(Instance), __LL_SPI_MOSI_MISO_Swap_Dis(Instance));
+
+ if ((__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) && (LL_IsExtCfgEnGrp(LL_EXT_CFG_GRP_MASK_SPI))) {
+ if ((ll_cfg->wire_mode == SPI_WIRE_MODE_4) && (__LL_SPI_WireMode_Get(Instance) == SPI_WIRE_MODE_4)) {
+ LL_FUNC_ALTER(ll_cfg->loopback_en, __LL_SPI_Loopback_En(Instance), __LL_SPI_Loopback_Dis(Instance));
+ } else {
+ __LL_SPI_Loopback_Dis(Instance);
+ }
+ }
+
+ //User Config
+ __LL_SPI_Role_Set(Instance, user_cfg->role);
+ __LL_SPI_SclkPhase_Set(Instance, user_cfg->sclk_phase);
+ __LL_SPI_SclkPolarity_Set(Instance, user_cfg->sclk_pol);
+ __LL_SPI_SerialDataLen_Set(Instance, user_cfg->data_width);
+ __LL_SPI_BaudRate_Set(Instance, LL_RCU_APB1ClkGet() / user_cfg->baudrate / 2);
+
+ //All Interrupt Pending Clear
+ __LL_SPI_AllIntPnd_Clr(Instance);
+
+ //SPI Enable
+ __LL_SPI_En(Instance);
+
+ //SPI Handle Init
+ spi_hdl->role = user_cfg->role;
+ spi_hdl->tx_ctrl.state = SPI_STATE_READY;
+ spi_hdl->rx_ctrl.state = SPI_STATE_READY;
+ spi_hdl->user_callback = user_cfg->user_callback;
+
+ return LL_OK;
+}
+
+/**
+ * @brief SPI LL DeInit
+ * @param Instance Specifies SPI peripheral
+ * @return Status of the DeInitialization
+ */
+LL_StatusETypeDef LL_SPI_DeInit(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+
+ if (!IS_SPI_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ } else if (spi_hdl->tx_ctrl.state == SPI_STATE_BUSY_TX || spi_hdl->rx_ctrl.state == SPI_STATE_BUSY_RX) {
+ LOG_E("This SPI[0x%08" PRIx32 "] is being used!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ spi_hdl->tx_ctrl.state = SPI_STATE_BUSY;
+ spi_hdl->rx_ctrl.state = SPI_STATE_BUSY;
+
+ //Module disable
+ __LL_SPI_Dis(Instance);
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_SPI_MspDeInit(Instance);
+
+ memset((void *)spi_hdl, 0, sizeof(SPI_HandleTypeDef));
+ spi_hdl->tx_ctrl.state = SPI_STATE_RESET;
+ spi_hdl->rx_ctrl.state = SPI_STATE_RESET;
+
+ return LL_OK;
+}
+
+/**
+ * @brief SPI LL Reset
+ * @param Instance Specifies SPI peripheral
+ * @return Status of the Reset
+ */
+LL_StatusETypeDef LL_SPI_Reset(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+ IRQn_Type irq_num;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+
+ if (!IS_SPI_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ irq_num = GET_SPI_IRQ_NUMBER(Instance);
+ if (irq_num < 0) {
+ LOG_E("SPI IRQ does not exist!\n");
+ return LL_ERROR;
+ }
+
+ //Clear pending and interrupt disable
+ __disable_irq();
+ __LL_SPI_Dis(Instance);
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) {
+ CLEAR_BIT(Instance->INTEN, 0xfffUL);
+ SET_BIT(Instance->INT, 0xfffUL);
+ } else {
+ CLEAR_BIT(Instance->INTEN, 0xf3fUL);
+ SET_BIT(Instance->INT, 0xf3fUL);
+ }
+ NVIC_ClearPendingIRQ(irq_num);
+ NVIC_DisableIRQ(irq_num);
+ __enable_irq();
+
+ spi_hdl->tx_ctrl.state = SPI_STATE_BUSY;
+ spi_hdl->rx_ctrl.state = SPI_STATE_BUSY;
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_SPI_MspDeInit(Instance);
+
+ memset((void *)spi_hdl, 0, sizeof(SPI_HandleTypeDef));
+ spi_hdl->tx_ctrl.state = SPI_STATE_RESET;
+ spi_hdl->rx_ctrl.state = SPI_STATE_RESET;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the SPI MSP
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_MspInit(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the SPI MSP
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_MspDeInit(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Register an User SPI Callback
+ * @note User can register callback only in SPI Ready State
+ * @param Instance Specifies SPI peripheral
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_RegisterCallback(SPI_TypeDef *Instance, SPI_UserCallbackIdETypeDef CallbackID, SPI_UserCallback pCallback)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+
+ if (!IS_SPI_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Check callback pointer valid or not
+ if (pCallback == NULL) {
+ LOG_E("The callback pointer which to be registered is NULL!\n");
+ return LL_INVALID;
+ }
+
+ //Register user callback
+ switch (CallbackID) {
+ case SPI_TX_CPLT_CB_ID:
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx isn't in Ready state, can't register Tx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ spi_hdl->user_callback.TxCpltCallback = pCallback;
+ break;
+
+ case SPI_RX_CPLT_CB_ID:
+ if (spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ spi_hdl->user_callback.RxCpltCallback = pCallback;
+ break;
+
+ case SPI_TX_HALF_CPLT_CB_ID:
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx isn't in Ready state, can't register Tx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ spi_hdl->user_callback.TxHalfCpltCallback = pCallback;
+ break;
+
+ case SPI_RX_HALF_CPLT_CB_ID:
+ if (spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Rx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ spi_hdl->user_callback.RxHalfCpltCallback = pCallback;
+ break;
+
+ case SPI_ERROR_CB_ID:
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY || spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx&Rx are both not in Ready state, can't register Error callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ spi_hdl->user_callback.ErrorCallback = pCallback;
+ break;
+
+ default:
+ LOG_E("SPI user callback ID-[%d] is Invalid!\n", CallbackID);
+ return LL_INVALID;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief UnRegister an User SPI Callback
+ * @note User can unregister callback only in SPI Ready State
+ * @param Instance Specifies SPI peripheral
+ * @param CallbackID ID of the callback to be unregistered
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_UnRegisterCallback(SPI_TypeDef *Instance, SPI_UserCallbackIdETypeDef CallbackID)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+
+ if (!IS_SPI_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //UnRegister user callback
+ switch (CallbackID) {
+ case SPI_TX_CPLT_CB_ID:
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx isn't in Ready state, can't unregister Tx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ spi_hdl->user_callback.TxCpltCallback = NULL;
+ break;
+
+ case SPI_RX_CPLT_CB_ID:
+ if (spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ spi_hdl->user_callback.RxCpltCallback = NULL;
+ break;
+
+ case SPI_TX_HALF_CPLT_CB_ID:
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx isn't in Ready state, can't unregister Tx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ spi_hdl->user_callback.TxHalfCpltCallback = NULL;
+ break;
+
+ case SPI_RX_HALF_CPLT_CB_ID:
+ if (spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Rx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ spi_hdl->user_callback.RxHalfCpltCallback = NULL;
+ break;
+
+ case SPI_ERROR_CB_ID:
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY || spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx&Rx are both not in Ready state, can't unregister Error callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ spi_hdl->user_callback.ErrorCallback = NULL;
+ break;
+
+ default:
+ LOG_E("SPI user callback ID-[%d] is Invalid!\n", CallbackID);
+ return LL_INVALID;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_LL_Exported_Functions_Group2 SPI Read Write Functions
+ * @brief SPI Read Write Functions
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in CPU blocking mode
+ * @param Instance Specifies SPI peripheral
+ * @param buf transmit buffer pointer
+ * @param size amount of data to be sent
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_Transmit_CPU(SPI_TypeDef *Instance, uint8_t *buf, uint16_t size, uint32_t timeout)
+{
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ SPI_HandleTypeDef *spi_hdl;
+ SPI_DataWidthETypeDef data_width;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_SPI_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Tx/Rx State check
+ if (spi_hdl->role == SPI_ROLE_MASTER) {
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY || spi_hdl->rx_ctrl.state == SPI_STATE_BUSY_RX) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx isn't in READY state or Rx is Ongoing, can't start transmit!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ } else {
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx isn't in READY state, can't start transmit!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ }
+
+ //Transmit config
+ spi_hdl->tx_ctrl.state = SPI_STATE_BUSY_TX;
+ spi_hdl->tx_ctrl.buf = buf;
+ spi_hdl->tx_ctrl.size = size;
+ spi_hdl->tx_ctrl.cnt = 0;
+ spi_hdl->tx_ctrl.isr = NULL;
+
+ //Tx Enable, Start transmit
+ __LL_SPI_Tx_En(Instance);
+ __LL_SPI_TxFIFO_Reset(Instance);
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ __LL_SPI_Mst_TxRxCnt_Set(Instance, size);
+ __LL_SPI_Mst_TxRx_Start(Instance);
+ data_width = (SPI_DataWidthETypeDef)__LL_SPI_SerialDataLen_Get(Instance);
+ tickstart = LL_GetTick();
+
+ //Transmit loop
+ while (spi_hdl->tx_ctrl.cnt < spi_hdl->tx_ctrl.size) {
+ //if CPU has been broken a long time by Interrupt, the TxDone flag maybe set
+ if (__LL_SPI_IsTxDoneIntPnd(Instance)) {
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ }
+
+ //Wait TxFIFO to be not full
+ while (__LL_SPI_IsTxFIFOFull(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Write data to TxFIFO
+ if (data_width <= SPI_DATA_WIDTH_8BIT) { //Transmit data in 8 Bit mode
+ __LL_SPI_DAT_Write(Instance, *spi_hdl->tx_ctrl.buf);
+ spi_hdl->tx_ctrl.buf++;
+ } else { //Transmit data in 16 Bit mode
+ __LL_SPI_DAT_Write(Instance, *(uint16_t *)spi_hdl->tx_ctrl.buf);
+ spi_hdl->tx_ctrl.buf += 2;
+ }
+
+ spi_hdl->tx_ctrl.cnt++;
+ }
+
+ //Wait for transmit complete
+ while (!__LL_SPI_IsTxDoneIntPnd(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear TX Done Pending
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+
+ ret = LL_OK;
+
+exit:
+ //Stop transmit and Tx Disable
+ __LL_SPI_Mst_TxRx_Stop(Instance);
+ __LL_SPI_Tx_Dis(Instance);
+ spi_hdl->tx_ctrl.state = SPI_STATE_READY;
+
+ return ret;
+}
+
+/**
+ * @brief Receive an amount of data in CPU blocking mode
+ * @param Instance Specifies SPI peripheral
+ * @param buf Receive buffer pointer
+ * @param size amount of data to be received
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_Receive_CPU(SPI_TypeDef *Instance, uint8_t *buf, uint16_t size, uint32_t timeout)
+{
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ SPI_HandleTypeDef *spi_hdl;
+ SPI_DataWidthETypeDef data_width;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_SPI_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Tx/Rx State check
+ if (spi_hdl->role == SPI_ROLE_MASTER) {
+ if (spi_hdl->rx_ctrl.state != SPI_STATE_READY || spi_hdl->tx_ctrl.state == SPI_STATE_BUSY_TX) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Rx isn't in READY state or Tx is Ongoing, can't start receive!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ } else {
+ if (spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Rx isn't in READY state, can't start receive!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ }
+
+ //Receive config
+ spi_hdl->rx_ctrl.state = SPI_STATE_BUSY_RX;
+ spi_hdl->rx_ctrl.buf = buf;
+ spi_hdl->rx_ctrl.size = size;
+ spi_hdl->rx_ctrl.cnt = 0;
+ spi_hdl->rx_ctrl.isr = NULL;
+
+ //Rx Enable and Start receive
+ __LL_SPI_Rx_En(Instance);
+ __LL_SPI_RxFIFO_Reset(Instance);
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+ __LL_SPI_Mst_TxRxCnt_Set(Instance, size);
+ __LL_SPI_Mst_TxRx_Start(Instance);
+ data_width = (SPI_DataWidthETypeDef)__LL_SPI_SerialDataLen_Get(Instance);
+ tickstart = LL_GetTick();
+
+ //Receive loop
+ while (spi_hdl->rx_ctrl.cnt < spi_hdl->rx_ctrl.size) {
+ //Wait RxFIFO to be not empty
+ while (__LL_SPI_IsRxFIFOEmpty(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Read data from RxFIFO
+ if (data_width <= SPI_DATA_WIDTH_8BIT) { //Receive data in 8 Bit mode
+ *spi_hdl->rx_ctrl.buf = (uint8_t)__LL_SPI_DAT_Read(Instance);
+ spi_hdl->rx_ctrl.buf++;
+ } else { //Receive data in 16 Bit mode
+ *(uint16_t *)spi_hdl->rx_ctrl.buf = (uint16_t)__LL_SPI_DAT_Read(Instance);
+ spi_hdl->rx_ctrl.buf += 2;
+ }
+
+ spi_hdl->rx_ctrl.cnt++;
+ }
+
+ //Clear RX Done Pending
+ if (__LL_SPI_IsRxDoneIntPnd(Instance)) {
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+ }
+
+ ret = LL_OK;
+
+exit:
+ //Stop receive and Rx Disable
+ __LL_SPI_Mst_TxRx_Stop(Instance);
+ __LL_SPI_Rx_Dis(Instance);
+ spi_hdl->rx_ctrl.state = SPI_STATE_READY;
+
+ return ret;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in Full Duplex CPU blocking mode
+ * @param Instance Specifies SPI peripheral
+ * @param tx_buf transmit buffer pointer
+ * @param rx_buf receive buffer pointer
+ * @param size amount of data to be sent/received
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_TransmitReceive_CPU(SPI_TypeDef *Instance, uint8_t *tx_buf, uint8_t *rx_buf,
+ uint16_t size, uint32_t timeout)
+{
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ SPI_HandleTypeDef *spi_hdl;
+ SPI_DataWidthETypeDef data_width;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+ assert_param(tx_buf != NULL);
+ assert_param(rx_buf != NULL);
+ assert_param(size);
+
+ if (!IS_SPI_ALL_INSTANCE(Instance) || tx_buf == NULL || rx_buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Tx/Rx State check
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY || spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx/Rx isn't in READY state, can't start transmit/receive!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit/receive config
+ spi_hdl->tx_ctrl.state = SPI_STATE_BUSY_TX;
+ spi_hdl->tx_ctrl.buf = tx_buf;
+ spi_hdl->tx_ctrl.size = size;
+ spi_hdl->tx_ctrl.cnt = 0;
+ spi_hdl->tx_ctrl.isr = NULL;
+
+ spi_hdl->rx_ctrl.state = SPI_STATE_BUSY_RX;
+ spi_hdl->rx_ctrl.buf = rx_buf;
+ spi_hdl->rx_ctrl.size = size;
+ spi_hdl->rx_ctrl.cnt = 0;
+ spi_hdl->rx_ctrl.isr = NULL;
+
+ //Tx/Rx Enable and Start transmit
+ __LL_SPI_Tx_En(Instance);
+ __LL_SPI_Rx_En(Instance);
+ __LL_SPI_TxFIFO_Reset(Instance);
+ __LL_SPI_RxFIFO_Reset(Instance);
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+ __LL_SPI_Mst_TxRxCnt_Set(Instance, size);
+ __LL_SPI_Mst_TxRx_Start(Instance);
+ data_width = (SPI_DataWidthETypeDef)__LL_SPI_SerialDataLen_Get(Instance);
+ tickstart = LL_GetTick();
+
+ //Transmit/receive loop
+ while (spi_hdl->tx_ctrl.cnt < spi_hdl->tx_ctrl.size || spi_hdl->rx_ctrl.cnt < spi_hdl->rx_ctrl.size) {
+ //if CPU has been broken a long time by Interrupt, the TxDone flag maybe set
+ if (__LL_SPI_IsTxDoneIntPnd(Instance)) {
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ }
+
+ //Wait TxFIFO to be not full
+ if (!__LL_SPI_IsTxFIFOFull(Instance) && spi_hdl->tx_ctrl.cnt < spi_hdl->tx_ctrl.size) {
+ if (data_width <= SPI_DATA_WIDTH_8BIT) { //Transmit data in 8 Bit mode
+ __LL_SPI_DAT_Write(Instance, *spi_hdl->tx_ctrl.buf);
+ spi_hdl->tx_ctrl.buf++;
+ } else { //Transmit data in 16 Bit mode
+ __LL_SPI_DAT_Write(Instance, *(uint16_t *)spi_hdl->tx_ctrl.buf);
+ spi_hdl->tx_ctrl.buf += 2;
+ }
+
+ spi_hdl->tx_ctrl.cnt++;
+ }
+
+ //Read data from RxFIFO
+ if (!__LL_SPI_IsRxFIFOEmpty(Instance) && spi_hdl->rx_ctrl.cnt < spi_hdl->rx_ctrl.size) {
+ if (data_width <= SPI_DATA_WIDTH_8BIT) { //Receive data in 8 Bit mode
+ *spi_hdl->rx_ctrl.buf = (uint8_t)__LL_SPI_DAT_Read(Instance);
+ spi_hdl->rx_ctrl.buf++;
+ } else { //Receive data in 16 Bit mode
+ *(uint16_t *)spi_hdl->rx_ctrl.buf = (uint16_t)__LL_SPI_DAT_Read(Instance);
+ spi_hdl->rx_ctrl.buf += 2;
+ }
+
+ spi_hdl->rx_ctrl.cnt++;
+ }
+
+ //Check whether operation timeout or not
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ LOG_E("Can't send or receive Within a predetermined time!\n");
+ LOG_E("It has sent %d numbers data!\n", spi_hdl->tx_ctrl.cnt);
+ LOG_E("It has received %d numbers data!\n", spi_hdl->rx_ctrl.cnt);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear TX Done Pending
+ if (__LL_SPI_IsTxDoneIntPnd(Instance)) {
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ }
+
+ //Clear RX Done Pending
+ if (__LL_SPI_IsRxDoneIntPnd(Instance)) {
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+ }
+
+ ret = LL_OK;
+
+exit:
+ //Stop transmit/receive and Tx/Rx Disable
+ __LL_SPI_Mst_TxRx_Stop(Instance);
+ __LL_SPI_Tx_Dis(Instance);
+ __LL_SPI_Rx_Dis(Instance);
+ spi_hdl->tx_ctrl.state = SPI_STATE_READY;
+ spi_hdl->rx_ctrl.state = SPI_STATE_READY;
+
+ return ret;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies SPI peripheral
+ * @param buf transmit buffer pointer
+ * @param size amount of data to be sent
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_Transmit_IT(SPI_TypeDef *Instance, uint8_t *buf, uint16_t size)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_SPI_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Tx/Rx State check
+ if (spi_hdl->role == SPI_ROLE_MASTER) {
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY || spi_hdl->rx_ctrl.state == SPI_STATE_BUSY_RX) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx isn't in READY state or Rx is Ongoing, can't start transmit!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ } else {
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx isn't in READY state, can't start transmit!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ }
+
+ //Transmit config
+ spi_hdl->tx_ctrl.state = SPI_STATE_BUSY_TX;
+ spi_hdl->tx_ctrl.buf = buf;
+ spi_hdl->tx_ctrl.size = size;
+ spi_hdl->tx_ctrl.cnt = 0;
+
+ if ((SPI_DataWidthETypeDef)__LL_SPI_SerialDataLen_Get(Instance) <= SPI_DATA_WIDTH_8BIT) { //Transmit data in 8 Bit mode
+ spi_hdl->tx_ctrl.isr = SPI_TxISR_8BIT;
+ } else { //Transmit data in 16 Bit mode
+ spi_hdl->tx_ctrl.isr = SPI_TxISR_16BIT;
+ }
+
+ //Tx Enable and Start transmit
+ __LL_SPI_Tx_En(Instance);
+ __LL_SPI_TxFIFO_Reset(Instance);
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ __LL_SPI_Mst_TxRxCnt_Set(Instance, size);
+ __LL_SPI_Mst_TxRx_Start(Instance);
+
+ //Enable TxFIFO Empty interrupt
+ __LL_SPI_TxFIFOEmpty_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies SPI peripheral
+ * @param buf receive buffer pointer
+ * @param size amount of data to be received
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_Receive_IT(SPI_TypeDef *Instance, uint8_t *buf, uint16_t size)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_SPI_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Tx/Rx State check
+ if (spi_hdl->role == SPI_ROLE_MASTER) {
+ if (spi_hdl->rx_ctrl.state != SPI_STATE_READY || spi_hdl->tx_ctrl.state == SPI_STATE_BUSY_TX) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Rx isn't in READY state or Tx is Ongoing, can't start receive!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ } else {
+ if (spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Rx isn't in READY state, can't start receive!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ }
+
+ //Receive config
+ spi_hdl->rx_ctrl.state = SPI_STATE_BUSY_RX;
+ spi_hdl->rx_ctrl.buf = buf;
+ spi_hdl->rx_ctrl.size = size;
+ spi_hdl->rx_ctrl.cnt = 0;
+
+ if ((SPI_DataWidthETypeDef)__LL_SPI_SerialDataLen_Get(Instance) <= SPI_DATA_WIDTH_8BIT) { //Receive data in 8 Bit mode
+ spi_hdl->rx_ctrl.isr = SPI_RxISR_8BIT;
+ } else { //Receive data in 16 Bit mode
+ spi_hdl->rx_ctrl.isr = SPI_RxISR_16BIT;
+ }
+
+ //Rx Enable and Start receive
+ __LL_SPI_Rx_En(Instance);
+ __LL_SPI_RxFIFO_Reset(Instance);
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+ __LL_SPI_Mst_TxRxCnt_Set(Instance, size);
+ __LL_SPI_Mst_TxRx_Start(Instance);
+
+ //Enable RxFIFO Full interrupt
+ __LL_SPI_RxFIFOFull_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in Full Duplex non-blocking mode with Interrupt
+ * @param Instance Specifies SPI peripheral
+ * @param tx_buf transmit buffer pointer
+ * @param rx_buf receive buffer pointer
+ * @param size amount of data to be sent/received
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_TransmitReceive_IT(SPI_TypeDef *Instance, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+ assert_param(tx_buf != NULL);
+ assert_param(rx_buf != NULL);
+ assert_param(size);
+
+ if (!IS_SPI_ALL_INSTANCE(Instance) || tx_buf == NULL || rx_buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Tx/Rx State check
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY || spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx/Rx isn't in READY state, can't start transmit/receive!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit/receive config
+ spi_hdl->tx_ctrl.state = SPI_STATE_BUSY_TX;
+ spi_hdl->tx_ctrl.buf = tx_buf;
+ spi_hdl->tx_ctrl.size = size;
+ spi_hdl->tx_ctrl.cnt = 0;
+
+ spi_hdl->rx_ctrl.state = SPI_STATE_BUSY_RX;
+ spi_hdl->rx_ctrl.buf = rx_buf;
+ spi_hdl->rx_ctrl.size = size;
+ spi_hdl->rx_ctrl.cnt = 0;
+
+ if ((SPI_DataWidthETypeDef)__LL_SPI_SerialDataLen_Get(Instance) <= SPI_DATA_WIDTH_8BIT) { //Transmit/Receive data in 8 Bit mode
+ spi_hdl->tx_ctrl.isr = SPI_TxISR_8BIT;
+ spi_hdl->rx_ctrl.isr = SPI_RxISR_8BIT;
+ } else { //Transmit/Receive data in 16 Bit mode
+ spi_hdl->tx_ctrl.isr = SPI_TxISR_16BIT;
+ spi_hdl->rx_ctrl.isr = SPI_RxISR_16BIT;
+ }
+
+ //Tx/Rx Enable and Start transmit
+ __LL_SPI_Tx_En(Instance);
+ __LL_SPI_Rx_En(Instance);
+ __LL_SPI_TxFIFO_Reset(Instance);
+ __LL_SPI_RxFIFO_Reset(Instance);
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+ __LL_SPI_Mst_TxRxCnt_Set(Instance, size);
+ __LL_SPI_Mst_TxRx_Start(Instance);
+
+ //Enable RxFIFO Full interrupt
+ __LL_SPI_RxFIFOFull_INT_En(Instance);
+
+ //Enable TxFIFO Empty interrupt last
+ __LL_SPI_TxFIFOEmpty_INT_En(Instance);
+
+ return LL_OK;
+}
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies SPI peripheral
+ * @param buf transmit buffer pointer
+ * @param size amount of data to be sent
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_Transmit_DMA(SPI_TypeDef *Instance, uint8_t *buf, uint16_t size)
+{
+ uint32_t dma_size;
+ SPI_HandleTypeDef *spi_hdl;
+ DMA_UserCfgTypeDef dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_SPI_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Tx/Rx State check
+ if (spi_hdl->role == SPI_ROLE_MASTER) {
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY || spi_hdl->rx_ctrl.state == SPI_STATE_BUSY_RX) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx isn't in READY state or Rx is Ongoing, can't start transmit!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ } else {
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx isn't in READY state, can't start transmit!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ }
+
+ //DMA Init
+ memset((void *)&dma_user_cfg, 0x0, sizeof(dma_user_cfg));
+
+ if ((SPI_DataWidthETypeDef)__LL_SPI_SerialDataLen_Get(Instance) <= SPI_DATA_WIDTH_8BIT) { //Transmit data in 8 Bit mode
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_8b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_8b;
+ dma_size = size;
+ } else { //Transmit data in 16 Bit mode
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_16b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_16b;
+ dma_size = size * 2;
+ }
+
+ dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_FIX;
+ dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == SPI0) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_SPI0_TX;
+ } else if (Instance == SPI1) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_SPI1_TX;
+ } else {
+ LOG_E("SPI DMA destination handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Transmit Default Config
+ dma_user_cfg.trans_type = DMA_TRANS_TYPE_M2P;
+ dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_INC;
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ dma_user_cfg.end_callback = (DMA_IRQCallback)SPI_DMATransmitCplt;
+ dma_user_cfg.end_arg = Instance;
+ dma_user_cfg.err_callback = (DMA_IRQCallback)SPI_DMATransmitError;
+ dma_user_cfg.err_arg = Instance;
+ dma_user_cfg.half_callback = (DMA_IRQCallback)SPI_DMAHalfTransmitCplt;
+ dma_user_cfg.half_arg = Instance;
+
+ spi_hdl->tx_ctrl.dma_ch = SPI_DMA_Init(&dma_user_cfg);
+
+ if (spi_hdl->tx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("SPI transmit request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Transmit config
+ spi_hdl->tx_ctrl.state = SPI_STATE_BUSY_TX;
+ spi_hdl->tx_ctrl.buf = buf;
+ spi_hdl->tx_ctrl.size = dma_size;
+ spi_hdl->tx_ctrl.cnt = 0;
+ spi_hdl->tx_ctrl.isr = NULL;
+
+ //Enable Tx DMA Requset
+ __LL_SPI_TxDMA_En(Instance);
+
+ //Tx Enable and Start transmit
+ __LL_SPI_Tx_En(Instance);
+ __LL_SPI_TxFIFO_Reset(Instance);
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ __LL_SPI_Mst_TxRxCnt_Set(Instance, size);
+ __LL_SPI_Mst_TxRx_Start(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, spi_hdl->tx_ctrl.dma_ch, (uint32_t)buf, (uint32_t)&Instance->TDR, dma_size);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies SPI peripheral
+ * @param buf receive buffer pointer
+ * @param size amount of data to be received
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_Receive_DMA(SPI_TypeDef *Instance, uint8_t *buf, uint16_t size)
+{
+ uint32_t dma_size;
+ SPI_HandleTypeDef *spi_hdl;
+ DMA_UserCfgTypeDef dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_SPI_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Tx/Rx State check
+ if (spi_hdl->role == SPI_ROLE_MASTER) {
+ if (spi_hdl->rx_ctrl.state != SPI_STATE_READY || spi_hdl->tx_ctrl.state == SPI_STATE_BUSY_TX) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Rx isn't in READY state or Tx is Ongoing, can't start receive!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ } else {
+ if (spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Rx isn't in READY state, can't start receive!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+ }
+
+ //DMA Init
+ memset((void *)&dma_user_cfg, 0x0, sizeof(dma_user_cfg));
+
+ if ((SPI_DataWidthETypeDef)__LL_SPI_SerialDataLen_Get(Instance) <= SPI_DATA_WIDTH_8BIT) { //Transmit data in 8 Bit mode
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_8b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_8b;
+ dma_size = size;
+ } else { //Transmit data in 16 Bit mode
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_16b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_16b;
+ dma_size = size * 2;
+ }
+
+ dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_FIX;
+ dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == SPI0) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_SPI0_RX;
+ } else if (Instance == SPI1) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_SPI1_RX;
+ } else {
+ LOG_E("SPI DMA source handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Receive Default Config
+ dma_user_cfg.trans_type = DMA_TRANS_TYPE_P2M;
+ dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_INC;
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ dma_user_cfg.end_callback = (DMA_IRQCallback)SPI_DMAReceiveCplt;
+ dma_user_cfg.end_arg = Instance;
+ dma_user_cfg.err_callback = (DMA_IRQCallback)SPI_DMAReceiveError;
+ dma_user_cfg.err_arg = Instance;
+ dma_user_cfg.half_callback = (DMA_IRQCallback)SPI_DMAHalfReceiveCplt;
+ dma_user_cfg.half_arg = Instance;
+
+ spi_hdl->rx_ctrl.dma_ch = SPI_DMA_Init(&dma_user_cfg);
+
+ if (spi_hdl->rx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("SPI receive request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Receive config
+ spi_hdl->rx_ctrl.state = SPI_STATE_BUSY_RX;
+ spi_hdl->rx_ctrl.buf = buf;
+ spi_hdl->rx_ctrl.size = dma_size;
+ spi_hdl->rx_ctrl.cnt = 0;
+ spi_hdl->rx_ctrl.isr = NULL;
+
+ //Enable Rx DMA Requset
+ __LL_SPI_RxDMA_En(Instance);
+
+ //Rx Enable and Start receive
+ __LL_SPI_Rx_En(Instance);
+ __LL_SPI_RxFIFO_Reset(Instance);
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+ __LL_SPI_Mst_TxRxCnt_Set(Instance, size);
+ __LL_SPI_Mst_TxRx_Start(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, spi_hdl->rx_ctrl.dma_ch, (uint32_t)&Instance->RDR, (uint32_t)buf, dma_size);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in Full Duplex non-blocking mode with DMA
+ * @param Instance Specifies SPI peripheral
+ * @param tx_buf transmit buffer pointer
+ * @param rx_buf receive buffer pointer
+ * @param size amount of data to be sent/received
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_SPI_TransmitReceive_DMA(SPI_TypeDef *Instance, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size)
+{
+ uint32_t tx_dma_size, rx_dma_size;
+ SPI_HandleTypeDef *spi_hdl;
+ DMA_UserCfgTypeDef tx_dma_user_cfg, rx_dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+ assert_param(tx_buf != NULL);
+ assert_param(rx_buf != NULL);
+ assert_param(size);
+
+ if (!IS_SPI_ALL_INSTANCE(Instance) || tx_buf == NULL || rx_buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Tx/Rx State check
+ if (spi_hdl->tx_ctrl.state != SPI_STATE_READY || spi_hdl->rx_ctrl.state != SPI_STATE_READY) {
+ LOG_E("This SPI[0x%08" PRIx32 "] Tx/Rx isn't in READY state, can't start transmit/receive!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit/Receive DMA Init
+ memset((void *)&tx_dma_user_cfg, 0x0, sizeof(tx_dma_user_cfg));
+ memset((void *)&rx_dma_user_cfg, 0x0, sizeof(rx_dma_user_cfg));
+
+ if ((SPI_DataWidthETypeDef)__LL_SPI_SerialDataLen_Get(Instance) <= SPI_DATA_WIDTH_8BIT) { //Transmit/Receive data in 8 Bit mode
+ tx_dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_8b;
+ tx_dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_8b;
+ rx_dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_8b;
+ rx_dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_8b;
+ tx_dma_size = size;
+ rx_dma_size = size;
+ } else { //Transmit/Receive data in 16 Bit mode
+ tx_dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_16b;
+ tx_dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_16b;
+ rx_dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_16b;
+ rx_dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_16b;
+ tx_dma_size = size * 2;
+ rx_dma_size = size * 2;
+ }
+
+ tx_dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_FIX;
+ rx_dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_FIX;
+ tx_dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+ rx_dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == SPI0) {
+ tx_dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_SPI0_TX;
+ rx_dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_SPI0_RX;
+ } else if (Instance == SPI1) {
+ tx_dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_SPI1_TX;
+ rx_dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_SPI1_RX;
+ } else {
+ LOG_E("SPI DMA source and destination handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Transmit Default Config
+ tx_dma_user_cfg.trans_type = DMA_TRANS_TYPE_M2P;
+ tx_dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_INC;
+ tx_dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ //DMA Receive Default Config
+ rx_dma_user_cfg.trans_type = DMA_TRANS_TYPE_P2M;
+ rx_dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_INC;
+ rx_dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ tx_dma_user_cfg.end_callback = (DMA_IRQCallback)SPI_DMATransmitCplt;
+ tx_dma_user_cfg.end_arg = Instance;
+ tx_dma_user_cfg.err_callback = (DMA_IRQCallback)SPI_DMATransmitError;
+ tx_dma_user_cfg.err_arg = Instance;
+ tx_dma_user_cfg.half_callback = (DMA_IRQCallback)SPI_DMAHalfTransmitCplt;
+ tx_dma_user_cfg.half_arg = Instance;
+
+ rx_dma_user_cfg.end_callback = (DMA_IRQCallback)SPI_DMAReceiveCplt;
+ rx_dma_user_cfg.end_arg = Instance;
+ rx_dma_user_cfg.err_callback = (DMA_IRQCallback)SPI_DMAReceiveError;
+ rx_dma_user_cfg.err_arg = Instance;
+ rx_dma_user_cfg.half_callback = (DMA_IRQCallback)SPI_DMAHalfReceiveCplt;
+ rx_dma_user_cfg.half_arg = Instance;
+
+ spi_hdl->tx_ctrl.dma_ch = SPI_DMA_Init(&tx_dma_user_cfg);
+
+ if (spi_hdl->tx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("SPI transmit request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ spi_hdl->rx_ctrl.dma_ch = SPI_DMA_Init(&rx_dma_user_cfg);
+
+ if (spi_hdl->rx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ SPI_DMA_DeInit(spi_hdl->tx_ctrl.dma_ch);
+ LOG_E("SPI receive request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Transmit/Receive config
+ spi_hdl->tx_ctrl.state = SPI_STATE_BUSY_TX;
+ spi_hdl->tx_ctrl.buf = tx_buf;
+ spi_hdl->tx_ctrl.size = tx_dma_size;
+ spi_hdl->tx_ctrl.cnt = 0;
+ spi_hdl->tx_ctrl.isr = NULL;
+
+ spi_hdl->rx_ctrl.state = SPI_STATE_BUSY_RX;
+ spi_hdl->rx_ctrl.buf = rx_buf;
+ spi_hdl->rx_ctrl.size = rx_dma_size;
+ spi_hdl->rx_ctrl.cnt = 0;
+ spi_hdl->rx_ctrl.isr = NULL;
+
+ //Enable Tx/Rx DMA Requset
+ __LL_SPI_TxDMA_En(Instance);
+ __LL_SPI_RxDMA_En(Instance);
+
+ //Tx/Rx Enable and Start transmit
+ __LL_SPI_Tx_En(Instance);
+ __LL_SPI_Rx_En(Instance);
+ __LL_SPI_TxFIFO_Reset(Instance);
+ __LL_SPI_RxFIFO_Reset(Instance);
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+ __LL_SPI_Mst_TxRxCnt_Set(Instance, size);
+ __LL_SPI_Mst_TxRx_Start(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, spi_hdl->tx_ctrl.dma_ch, (uint32_t)tx_buf, (uint32_t)&Instance->TDR, tx_dma_size);
+ LL_DMA_Start_IT(DMA, spi_hdl->rx_ctrl.dma_ch, (uint32_t)&Instance->RDR, (uint32_t)rx_buf, rx_dma_size);
+
+ return LL_OK;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_LL_Exported_Functions_Interrupt SPI Interrupt Handler and Callback
+ * @brief SPI Interrupt Handler and Callback
+ * @{
+ */
+
+/**
+ * @brief SPI IRQ Handler
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+void LL_SPI_IRQHandler(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+ uint32_t int_en, int_pending;
+
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+
+ if (!IS_SPI_ALL_INSTANCE(Instance)) {
+ return;
+ }
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ //All Interrupt Enalbe and Pending Get
+ int_en = __LL_SPI_AllIntEn_Get(Instance);
+ int_pending = __LL_SPI_AllIntPnd_Get(Instance);
+
+
+ //RxFIFO Full Interrupt Pending
+ if ((int_en & SPI0_INTEN_RXFIE_Msk) && (int_pending & SPI0_INT_RXFI_Msk)) {
+ //Interrupt Pending auto clear
+
+ if (spi_hdl->rx_ctrl.isr) {
+ spi_hdl->rx_ctrl.isr(Instance);
+ }
+
+ //Callback
+ LL_SPI_RxFullCallback(Instance);
+ }
+
+ //TxFIFO Empty Interrupt Pending
+ if ((int_en & SPI0_INTEN_TXEIE_Msk) && (int_pending & SPI0_INT_TXEI_Msk)) {
+ //Interrupt Pending auto clear
+
+ if (spi_hdl->tx_ctrl.isr) {
+ spi_hdl->tx_ctrl.isr(Instance);
+ }
+
+ //Callback
+ LL_SPI_TxEmptyCallback(Instance);
+ }
+
+ //RxFIFO Overflow Interrupt Pending
+ if ((int_en & SPI0_INTEN_RXOFIE_Msk) && (int_pending & SPI0_INT_RXOFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_SPI_RxOverflowIntPnd_Clr(Instance);
+
+ //Callback
+ LL_SPI_RxOverflowCallback(Instance);
+ }
+
+ //RxFIFO Underflow Interrupt Pending
+ if ((int_en & SPI0_INTEN_RXUFIE_Msk) && (int_pending & SPI0_INT_RXUFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_SPI_RxUnderflowIntPnd_Clr(Instance);
+
+ //Callback
+ LL_SPI_RxUnderflowCallback(Instance);
+ }
+
+ //TxFIFO Overflow Interrupt Pending
+ if ((int_en & SPI0_INTEN_TXOFIE_Msk) && (int_pending & SPI0_INT_TXOFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_SPI_TxOverflowIntPnd_Clr(Instance);
+
+ //Callback
+ LL_SPI_TxOverflowCallback(Instance);
+ }
+
+ //Slave TxFIFO Underflow Interrupt Pending
+ if ((int_en & SPI0_INTEN_TXUFIE_Msk) && (int_pending & SPI0_INT_TXUFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_SPI_Slv_TxUnderflowIntPnd_Clr(Instance);
+
+ //Callback
+ LL_SPI_Slv_TxUnderflowCallback(Instance);
+ }
+
+ //Tx Done Interrupt Pending
+ if ((int_en & SPI0_INTEN_TXDEIE_Msk) && (int_pending & SPI0_INT_TXDEI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+
+ if (spi_hdl->tx_ctrl.cnt >= spi_hdl->tx_ctrl.size && spi_hdl->tx_ctrl.isr) {
+ spi_hdl->tx_ctrl.isr(Instance);
+ }
+
+ //Callback
+ LL_SPI_TxDoneCallback(Instance);
+ }
+
+ //Rx Done Interrupt Pending
+ if ((int_en & SPI0_INTEN_RXDEIE_Msk) && (int_pending & SPI0_INT_RXDEI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+
+ //Callback
+ LL_SPI_RxDoneCallback(Instance);
+ }
+
+ //Tx Complete Interrupt Pending
+ if ((int_en & SPI0_INTEN_TXCIE_Msk) && (int_pending & SPI0_INT_TXCI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_SPI_TxCpltIntPnd_Clr(Instance);
+
+ //Callback
+ LL_SPI_TxCpltCallback(Instance);
+ }
+
+ //Rx Complete Interrupt Pending
+ if ((int_en & SPI0_INTEN_RXCIE_Msk) && (int_pending & SPI0_INT_RXCI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_SPI_RxCpltIntPnd_Clr(Instance);
+
+ //Callback
+ LL_SPI_RxCpltCallback(Instance);
+ }
+
+ //The following features are available for later versions
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ return;
+ }
+
+ //Transmission Mode Fault Interrupt Pending
+ if ((int_en & SPI0_INTEN_MDFIE_Msk) && (int_pending & SPI0_INT_MDFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_SPI_TransModeFaultIntPnd_Clr(Instance);
+
+ //Callback
+ LL_SPI_TransModeFaultCallback(Instance);
+ }
+
+ //Transmission Operation Fault Interrupt Pending
+ if ((int_en & SPI0_INTEN_OPFIE_Msk) && (int_pending & SPI0_INT_OPFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_SPI_TransOptFaultIntPnd_Clr(Instance);
+
+ //Callback
+ LL_SPI_TransOptFaultCallback(Instance);
+ }
+}
+
+/**
+ * @brief SPI Transmission Mode Fault Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_TransModeFaultCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_TransModeFaultCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI Transmission Operation Fault Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_TransOptFaultCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_TransOptFaultCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI RxFIFO Full Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_RxFullCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_RxFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI TxFIFO Empty Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_TxEmptyCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_TxEmptyCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI RxFIFO Overflow Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_RxOverflowCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_RxOverflowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI RxFIFO Underflow Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_RxUnderflowCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_RxUnderflowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI TxFIFO Overflow Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_TxOverflowCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_TxOverflowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI Slave TxFIFO Underflow Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_Slv_TxUnderflowCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_Slv_TxUnderflowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI Tx Done Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_TxDoneCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_TxDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI Rx Done Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_RxDoneCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_RxDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI Tx Complete Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_TxCpltCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI Rx Complete Interrupt Callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+__WEAK void LL_SPI_RxCpltCallback(SPI_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_SPI_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private Functions ---------------------------------------------------------*/
+/** @addtogroup SPI_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief SPI Handle Get
+ * @param Instance Specifies SPI peripheral
+ * @return SPI_HandleTypeDef pointer
+ */
+static SPI_HandleTypeDef *SPI_Handle_Get(SPI_TypeDef *Instance)
+{
+ //Assert param
+ assert_param(IS_SPI_ALL_INSTANCE(Instance));
+
+ if (Instance == SPI0) {
+ return &spi_hdl_global[SPI_INSTANCE_0];
+ } else if (Instance == SPI1) {
+ return &spi_hdl_global[SPI_INSTANCE_1];
+ }
+
+ return NULL;
+}
+
+/**
+ * @brief Handle the data 8-bit transmit in Interrupt mode
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_TxISR_8BIT(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ //Write data to TxFIFO until full according to Slave
+ while (!__LL_SPI_IsTxFIFOFull(Instance) && spi_hdl->tx_ctrl.cnt < spi_hdl->tx_ctrl.size) {
+ //if TxDone flag has been set before write data to TxFIFO, clear it
+ if (__LL_SPI_IsTxDoneIntPnd(Instance)) {
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ }
+
+ __LL_SPI_DAT_Write(Instance, *spi_hdl->tx_ctrl.buf);
+ spi_hdl->tx_ctrl.buf++;
+ spi_hdl->tx_ctrl.cnt++;
+ }
+
+ //Tx Complete
+ if (spi_hdl->tx_ctrl.cnt >= spi_hdl->tx_ctrl.size) {
+ //Disable TxFIFO Empty interrupt
+ __LL_SPI_TxFIFOEmpty_INT_Dis(Instance);
+
+ //Switch isr to TxDone ISR
+ spi_hdl->tx_ctrl.isr = SPI_TxDone_ISR;
+
+ //Enable Tx Done Interrupt
+ __LL_SPI_TxDone_INT_En(Instance);
+ }
+}
+
+/**
+ * @brief Handle the data 16-bit transmit in Interrupt mode
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_TxISR_16BIT(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ //Write data to TxFIFO until full according to Slave
+ while (!__LL_SPI_IsTxFIFOFull(Instance) && spi_hdl->tx_ctrl.cnt < spi_hdl->tx_ctrl.size) {
+ //if TxDone flag has been set before write data to TxFIFO, clear it
+ if (__LL_SPI_IsTxDoneIntPnd(Instance)) {
+ __LL_SPI_TxDoneIntPnd_Clr(Instance);
+ }
+
+ __LL_SPI_DAT_Write(Instance, *(uint16_t *)spi_hdl->tx_ctrl.buf);
+ spi_hdl->tx_ctrl.buf += 2;
+ spi_hdl->tx_ctrl.cnt++;
+ }
+
+ //Tx Complete
+ if (spi_hdl->tx_ctrl.cnt >= spi_hdl->tx_ctrl.size) {
+ //Disable TxFIFO Empty interrupt
+ __LL_SPI_TxFIFOEmpty_INT_Dis(Instance);
+
+ //Switch isr to TxDone ISR
+ spi_hdl->tx_ctrl.isr = SPI_TxDone_ISR;
+
+ //Enable Tx Done Interrupt
+ __LL_SPI_TxDone_INT_En(Instance);
+ }
+}
+
+/**
+ * @brief Handle the data 8-bit receive in Interrupt mode
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_RxISR_8BIT(SPI_TypeDef *Instance)
+{
+ uint8_t rx_fifo_trig_lvl;
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ rx_fifo_trig_lvl = __LL_SPI_RxFIFOFullThres_Get(Instance);
+
+ //Read data from RxFIFO
+ while (rx_fifo_trig_lvl-- && spi_hdl->rx_ctrl.cnt < spi_hdl->rx_ctrl.size) {
+ *spi_hdl->rx_ctrl.buf = (uint8_t)__LL_SPI_DAT_Read(Instance);
+ spi_hdl->rx_ctrl.buf++;
+ spi_hdl->rx_ctrl.cnt++;
+ }
+
+ //Rx Complete
+ if (spi_hdl->rx_ctrl.cnt >= spi_hdl->rx_ctrl.size) {
+ SPI_CloseRx_ISR(Instance);
+ }
+}
+
+/**
+ * @brief Handle the data 16-bit receive in Interrupt mode
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_RxISR_16BIT(SPI_TypeDef *Instance)
+{
+ uint8_t rx_fifo_trig_lvl;
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ rx_fifo_trig_lvl = __LL_SPI_RxFIFOFullThres_Get(Instance);
+
+ //Read data from RxFIFO
+ while (rx_fifo_trig_lvl-- && spi_hdl->rx_ctrl.cnt < spi_hdl->rx_ctrl.size) {
+ *(uint16_t *)spi_hdl->rx_ctrl.buf = (uint16_t)__LL_SPI_DAT_Read(Instance);
+ spi_hdl->rx_ctrl.buf += 2;
+ spi_hdl->rx_ctrl.cnt++;
+ }
+
+ //Rx Complete
+ if (spi_hdl->rx_ctrl.cnt >= spi_hdl->rx_ctrl.size) {
+ SPI_CloseRx_ISR(Instance);
+ }
+}
+
+/**
+ * @brief SPI TxDone Interrupt Service Routine
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_TxDone_ISR(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ if (spi_hdl->tx_ctrl.cnt >= spi_hdl->tx_ctrl.size) {
+ //Disable Tx Done Interrupt
+ __LL_SPI_TxDone_INT_Dis(Instance);
+
+ //Tx Disable
+ __LL_SPI_Tx_Dis(Instance);
+ spi_hdl->tx_ctrl.isr = NULL;
+ spi_hdl->tx_ctrl.state = SPI_STATE_READY;
+
+ //Tx Complete Callback
+ if (spi_hdl->user_callback.TxCpltCallback) {
+ spi_hdl->user_callback.TxCpltCallback();
+ }
+ }
+}
+
+/**
+ * @brief Handle the end of the RX transaction
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_CloseRx_ISR(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ //Disable RxFIFO Full interrupt
+ __LL_SPI_RxFIFOFull_INT_Dis(Instance);
+
+ //Rx Disable
+ __LL_SPI_Rx_Dis(Instance);
+ spi_hdl->rx_ctrl.isr = NULL;
+ spi_hdl->rx_ctrl.state = SPI_STATE_READY;
+
+ //Clear RX Done Pending
+ if (__LL_SPI_IsRxDoneIntPnd(Instance)) {
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+ }
+
+ //Rx Complete Callback
+ if (spi_hdl->user_callback.RxCpltCallback) {
+ spi_hdl->user_callback.RxCpltCallback();
+ }
+}
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief SPI DMA Init
+ * @param dma_user_cfg user dma config pointer
+ * @return DMA_ChannelETypeDef
+ */
+static DMA_ChannelETypeDef SPI_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg)
+{
+ LL_StatusETypeDef ret;
+ DMA_ChannelETypeDef ch;
+
+ if (dma_user_cfg == NULL) {
+ return DMA_CHANNEL_INVALID;
+ }
+
+ //User DMA channel request
+ ch = LL_DMA_ChannelRequest();
+
+ if (ch == DMA_CHANNEL_INVALID) {
+ LOG_E("Requset DMA channel Fail!\n");
+ return DMA_CHANNEL_INVALID;
+ }
+
+ //User DMA init
+ ret = LL_DMA_Init(DMA, ch, dma_user_cfg);
+
+ if (ret != LL_OK) {
+ LOG_E("DMA LL init fail!\n");
+ LL_DMA_ChannelRelease(ch);
+ return DMA_CHANNEL_INVALID;
+ }
+
+ return ch;
+}
+
+/**
+ * @brief SPI DMA DeInit
+ * @param ch DMA channel to Deinit
+ * @return None
+ */
+static void SPI_DMA_DeInit(DMA_ChannelETypeDef ch)
+{
+ if (ch == DMA_CHANNEL_INVALID) {
+ return;
+ }
+
+ LL_DMA_Stop_IT(DMA, ch);
+ LL_DMA_DeInit(DMA, ch);
+ LL_DMA_ChannelRelease(ch);
+}
+
+/**
+ * @brief DMA SPI transmit process complete callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_DMATransmitCplt(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ //Disable Tx DMA Request
+ __LL_SPI_TxDMA_Dis(Instance);
+
+ //DMA DeInit
+ SPI_DMA_DeInit(spi_hdl->tx_ctrl.dma_ch);
+ spi_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ spi_hdl->tx_ctrl.cnt = spi_hdl->tx_ctrl.size;
+
+ //Switch isr to TxDone ISR
+ spi_hdl->tx_ctrl.isr = SPI_TxDone_ISR;
+
+ //Enable Tx Done Interrupt
+ __LL_SPI_TxDone_INT_En(Instance);
+}
+
+/**
+ * @brief DMA SPI receive process complete callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_DMAReceiveCplt(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ //Disable Rx DMA Request
+ __LL_SPI_RxDMA_Dis(Instance);
+
+ //DMA DeInit
+ SPI_DMA_DeInit(spi_hdl->rx_ctrl.dma_ch);
+ spi_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+
+ //Clear RX Done Pending
+ if (__LL_SPI_IsRxDoneIntPnd(Instance)) {
+ __LL_SPI_RxDoneIntPnd_Clr(Instance);
+ }
+
+ //Rx Disable
+ __LL_SPI_Rx_Dis(Instance);
+ spi_hdl->rx_ctrl.cnt = spi_hdl->rx_ctrl.size;
+ spi_hdl->rx_ctrl.state = SPI_STATE_READY;
+
+ //Rx Complete Callback
+ if (spi_hdl->user_callback.RxCpltCallback) {
+ spi_hdl->user_callback.RxCpltCallback();
+ }
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_DMAHalfTransmitCplt(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ //Tx Half Complete Callback
+ if (spi_hdl->user_callback.TxHalfCpltCallback) {
+ spi_hdl->user_callback.TxHalfCpltCallback();
+ }
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_DMAHalfReceiveCplt(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ //Rx Half Complete Callback
+ if (spi_hdl->user_callback.RxHalfCpltCallback) {
+ spi_hdl->user_callback.RxHalfCpltCallback();
+ }
+}
+
+/**
+ * @brief DMA SPI transmit process error callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_DMATransmitError(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ //Disable Tx DMA Request
+ __LL_SPI_TxDMA_Dis(Instance);
+
+ //Stop Tx and Tx Disable
+ __LL_SPI_Mst_TxRx_Stop(Instance);
+ __LL_SPI_Tx_Dis(Instance);
+
+ //DMA DeInit
+ SPI_DMA_DeInit(spi_hdl->tx_ctrl.dma_ch);
+
+ spi_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ spi_hdl->tx_ctrl.state = SPI_STATE_READY;
+
+ if (spi_hdl->user_callback.ErrorCallback) {
+ spi_hdl->user_callback.ErrorCallback();
+ }
+}
+
+/**
+ * @brief DMA SPI receive process error callback
+ * @param Instance Specifies SPI peripheral
+ * @return None
+ */
+static void SPI_DMAReceiveError(SPI_TypeDef *Instance)
+{
+ SPI_HandleTypeDef *spi_hdl;
+
+ //SPI handle get
+ spi_hdl = SPI_Handle_Get(Instance);
+
+ if (spi_hdl == NULL) {
+ LOG_E("Get SPI handle error!\n");
+ return;
+ }
+
+ //Disable Rx DMA Request
+ __LL_SPI_RxDMA_Dis(Instance);
+
+ //Stop Rx and Rx Disable
+ __LL_SPI_Mst_TxRx_Stop(Instance);
+ __LL_SPI_Rx_Dis(Instance);
+
+ //DMA DeInit
+ SPI_DMA_DeInit(spi_hdl->rx_ctrl.dma_ch);
+
+ spi_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ spi_hdl->rx_ctrl.state = SPI_STATE_READY;
+
+ if (spi_hdl->user_callback.ErrorCallback) {
+ spi_hdl->user_callback.ErrorCallback();
+ }
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+
+#endif /* LL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_sysctrl.c b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_sysctrl.c
new file mode 100644
index 0000000000..4de3238914
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_sysctrl.c
@@ -0,0 +1,286 @@
+/**
+ ******************************************************************************
+ * @file tae32g58xx_ll_sysctrl.c
+ * @author MCD Application Team
+ * @brief SYSCTRL LL module driver
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+
+#define DBG_TAG "UART"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae_dbg.h"
+
+
+/** @addtogroup TAE32G58xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup UART_LL UART LL
+ * @brief UART LL module driver
+ * @{
+ */
+
+#ifdef LL_UART_MODULE_ENABLED
+
+/* Private Constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+/* Private Types -------------------------------------------------------------*/
+/* Private Variables ---------------------------------------------------------*/
+/** @defgroup UART_LL_Private_Variables UART LL Private Variables
+ * @brief UART LL Private Variables
+ * @{
+ */
+
+/**
+ * @brief Default UART LL Config
+ */
+static const UART_LLCfgTypeDef uart_ll_cfg_def = {
+ .tx_rx_swap_en = false,
+ .rx_timeout_en = false,
+ .one_wire_en = false,
+ .tx_pol = UART_PIN_POL_INACT_HIGH,
+ .rx_pol = UART_PIN_POL_INACT_HIGH,
+ .bit_order = UART_BIT_ORDER_LSB,
+ .tx_fifo_empty_thres = 0, // 0~15
+ .rx_fifo_full_thres = 1, // 1~16
+ .rx_timeout = 0,
+ .rx_timeout_mode = UART_RTO_MODE_FNE_RXIDEL,
+};
+
+/**
+ * @brief UART Handle global variable
+ */
+static UART_HandleTypeDef uart_hdl_global[UART_INSTANCE_NUMS];
+
+/**
+ * @}
+ */
+
+
+/* Private Function Prototypes -----------------------------------------------*/
+/** @addtogroup UART_LL_Exported_Functions UART LL Exported Functions
+ * @brief UART LL Exported Functions
+ * @{
+ */
+static UART_HandleTypeDef *UART_Handle_Get(UART_TypeDef *Instance);
+
+static void UART_TxISR_8BIT(UART_TypeDef *Instance);
+static void UART_TxISR_16BIT(UART_TypeDef *Instance);
+static void UART_RxISR_8BIT(UART_TypeDef *Instance);
+static void UART_RxISR_16BIT(UART_TypeDef *Instance);
+static void UART_TxDone_ISR(UART_TypeDef *Instance);
+static void UART_RxTimeout_ISR(UART_TypeDef *Instance);
+
+#ifdef LL_DMA_MODULE_ENABLED
+ static DMA_ChannelETypeDef UART_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg);
+ static void UART_DMA_DeInit(DMA_ChannelETypeDef ch);
+
+ static void UART_DMATransmitCplt(UART_TypeDef *Instance);
+ static void UART_DMAReceiveCplt(UART_TypeDef *Instance);
+ static void UART_DMAHalfTransmitCplt(UART_TypeDef *Instance);
+ static void UART_DMAHalfReceiveCplt(UART_TypeDef *Instance);
+ static void UART_DMATransmitError(UART_TypeDef *Instance);
+ static void UART_DMAReceiveError(UART_TypeDef *Instance);
+#endif
+/**
+ * @}
+ */
+
+
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+/** @defgroup UART_LL_Exported_Functions UART LL Exported Functions
+ * @brief UART LL Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_LL_Exported_Functions_Group1 UART Init and DeInit Functions
+ * @brief UART Init and DeInit Functions
+ * @{
+ */
+
+/**
+ * @brief UART LL Init
+ * @param Instance Specifies UART peripheral
+ * @param init UART Init Pointer
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_UART_Init(UART_TypeDef *Instance, UART_InitTypeDef *init)
+{
+ uint32_t baud_rate = 1;
+ UART_LLCfgTypeDef *ll_cfg;
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+ assert_param(init != NULL);
+ assert_param(init->baudrate);
+
+ if (!IS_UART_ALL_INSTANCE(Instance) || init == NULL || !init->baudrate) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->tx_ctrl.state != UART_STATE_RESET || uart_hdl->rx_ctrl.state != UART_STATE_RESET) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't being used\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ //It must disable the UART while configuring certain registers
+ __LL_UART_Dis(Instance);
+
+ uart_hdl->tx_ctrl.state = UART_STATE_BUSY;
+ uart_hdl->rx_ctrl.state = UART_STATE_BUSY;
+
+ //LL config pointer config
+ LL_FUNC_ALTER(init->ll_cfg == NULL, ll_cfg = (UART_LLCfgTypeDef *)&uart_ll_cfg_def, ll_cfg = init->ll_cfg);
+
+ /* init the low level hardware eg. Clock, NVIC */
+ LL_UART_MspInit(Instance);
+
+ /* Reset UART FIFO */
+ __LL_UART_TxFIFO_Reset(Instance);
+ __LL_UART_RxFIFO_Reset(Instance);
+
+ //LL config
+ __LL_UART_TxPinPol_Set(Instance, ll_cfg->tx_pol);
+ __LL_UART_RxPinPol_Set(Instance, ll_cfg->rx_pol);
+ __LL_UART_BitOrder_Set(Instance, ll_cfg->bit_order);
+ __LL_UART_RxFIFOFullThres_Set(Instance, ll_cfg->rx_fifo_full_thres);
+ __LL_UART_TxFIFOEmptyThres_Set(Instance, ll_cfg->tx_fifo_empty_thres);
+ __LL_UART_RxTimeoutTime_Set(Instance, ll_cfg->rx_timeout);
+ LL_FUNC_ALTER(ll_cfg->tx_rx_swap_en, __LL_UART_TxRxPinSwap_En(Instance), __LL_UART_TxRxPinSwap_Dis(Instance));
+ LL_FUNC_ALTER(ll_cfg->one_wire_en, __LL_UART_OneWire_En(Instance), __LL_UART_OneWire_Dis(Instance));
+ LL_FUNC_ALTER(ll_cfg->rx_timeout_en, __LL_UART_RxTimeout_En(Instance), __LL_UART_RxTimeout_Dis(Instance));
+
+ if ((__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) && (LL_IsExtCfgEnGrp(LL_EXT_CFG_GRP_MASK_UART))) {
+ __LL_UART_RTOMode_Set(Instance, ll_cfg->rx_timeout_mode);
+ }
+
+ //User config
+ if (init->parity == UART_PARITY_NO) {
+ __LL_UART_Parity_Dis(Instance);
+ } else {
+ __LL_UART_Parity_En(Instance);
+ __LL_UART_Parity_Set(Instance, init->parity);
+ }
+
+ __LL_UART_StopLen_Set(Instance, init->stop_len);
+ __LL_UART_DatLen_Set(Instance, init->dat_len);
+
+ //Extend Mode Config
+ if (init->ext_bit_en) {
+ __LL_UART_ExtBit_En(Instance);
+
+ __LL_UART_RxExtMode_Set(Instance, init->rx_ext_mode);
+ __LL_UART_RxExtAddr_Set(Instance, init->rx_addr_ext);
+ } else {
+ __LL_UART_ExtBit_Dis(Instance);
+ }
+
+ //Baudrate Config
+ if (Instance == UART0 || Instance == UART1 || Instance == UART2) {
+ baud_rate = (LL_RCU_APB0ClkGet() + init->baudrate / 2) / init->baudrate;
+ } else if (Instance == UART3 || Instance == UART4) {
+ baud_rate = (LL_RCU_APB1ClkGet() + init->baudrate / 2) / init->baudrate;
+ }
+
+ __LL_UART_Baudrate_Set(Instance, baud_rate);
+ __LL_UART_OverSampleMode_Set(Instance, init->over_samp);
+
+ //Transfer State Init
+ uart_hdl->tx_ctrl.state = UART_STATE_READY;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+ uart_hdl->user_callback = init->user_callback;
+
+#ifdef LL_DMA_MODULE_ENABLED
+ uart_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ uart_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+#endif
+
+ //All Interrupt Pending Clear
+ __LL_UART_AllIntPnd_Clr(Instance);
+
+ //TX/RX Enable
+ __LL_UART_Tx_En(Instance);
+ __LL_UART_Rx_En(Instance);
+
+ //UART Enable
+ __LL_UART_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief UART LL DeInit
+ * @param Instance Specifies UART peripheral
+ * @return Status of the DeInitialization
+ */
+LL_StatusETypeDef LL_UART_DeInit(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->tx_ctrl.state == UART_STATE_BUSY_TX || uart_hdl->rx_ctrl.state == UART_STATE_BUSY_RX) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't being used!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ uart_hdl->tx_ctrl.state = UART_STATE_BUSY;
+ uart_hdl->rx_ctrl.state = UART_STATE_BUSY;
+
+ //UART Disable
+ __LL_UART_Dis(Instance);
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_UART_MspDeInit(Instance);
+
+ memset((void *)uart_hdl, 0, sizeof(UART_HandleTypeDef));
+ uart_hdl->tx_ctrl.state = UART_STATE_RESET;
+ uart_hdl->rx_ctrl.state = UART_STATE_RESET;
+
+#ifdef LL_DMA_MODULE_ENABLED
+ uart_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ uart_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+#endif
+
+ return LL_OK;
+}
+
+/**
+ * @brief UART LL Reset
+ * @param Instance Specifies UART peripheral
+ * @return Status of the Reset
+ */
+LL_StatusETypeDef LL_UART_Reset(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+ IRQn_Type irq_num;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ }
+
+ irq_num = GET_UART_IRQ_NUMBER(Instance);
+ if (irq_num < 0) {
+ LOG_E("UART IRQ does not exist!\n");
+ return LL_ERROR;
+ }
+
+ //Clear pending and interrupt disable
+ __disable_irq();
+ NVIC_DisableIRQ(irq_num);
+ (void) CLEAR_BIT(Instance->CR0, 0x7UL);
+ (void) SET_BIT(Instance->CR0, 0x18UL);
+ (void) CLEAR_BIT(Instance->CR0, 0x33FFE0UL);
+ CLEAR_BIT(Instance->INTEN, 0xffffffffUL);
+ NVIC_ClearPendingIRQ(irq_num);
+ __LL_UART_RxFIFO_Reset(Instance);
+ __LL_UART_TxFIFO_Reset(Instance);
+ __enable_irq();
+
+ __LL_UART_AllIntPnd_Clr(Instance);
+
+ uart_hdl->tx_ctrl.state = UART_STATE_BUSY;
+ uart_hdl->rx_ctrl.state = UART_STATE_BUSY;
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_UART_MspDeInit(Instance);
+
+ memset((void *)uart_hdl, 0, sizeof(UART_HandleTypeDef));
+ uart_hdl->tx_ctrl.state = UART_STATE_RESET;
+ uart_hdl->rx_ctrl.state = UART_STATE_RESET;
+
+#ifdef LL_DMA_MODULE_ENABLED
+ uart_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ uart_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+#endif
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the UART MSP
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_MspInit(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the UART MSP
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_MspDeInit(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Register an User UART Callback
+ * @note User can register callback only in UART Ready State
+ * @param Instance Specifies UART peripheral
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_RegisterCallback(UART_TypeDef *Instance, UART_UserCallbackIdETypeDef CallbackID, UART_UserCallback pCallback)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Check callback pointer valid or not
+ if (pCallback == NULL) {
+ LOG_E("The callback pointer which to be registered is NULL!\n");
+ return LL_INVALID;
+ }
+
+ //Register user callback
+ switch (CallbackID) {
+ case UART_TX_CPLT_CB_ID:
+ if (uart_hdl->tx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Tx isn't in Ready state, can't register Tx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ uart_hdl->user_callback.TxCpltCallback = pCallback;
+ break;
+
+ case UART_RX_CPLT_CB_ID:
+ if (uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ uart_hdl->user_callback.RxCpltCallback = pCallback;
+ break;
+
+ case UART_TX_HALF_CPLT_CB_ID:
+ if (uart_hdl->tx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Tx isn't in Ready state, can't register Tx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ uart_hdl->user_callback.TxHalfCpltCallback = pCallback;
+ break;
+
+ case UART_RX_HALF_CPLT_CB_ID:
+ if (uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Rx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ uart_hdl->user_callback.RxHalfCpltCallback = pCallback;
+ break;
+
+ case UART_ERROR_CB_ID:
+ if (uart_hdl->tx_ctrl.state != UART_STATE_READY || uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Tx&Rx are both not in Ready state, can't register Error callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ uart_hdl->user_callback.ErrorCallback = pCallback;
+ break;
+
+ default:
+ LOG_E("UART user callback ID-[%d] is Invalid!\n", CallbackID);
+ return LL_INVALID;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief UnRegister an User UART Callback
+ * @note User can unregister callback only in UART Ready State
+ * @param Instance Specifies UART peripheral
+ * @param CallbackID ID of the callback to be unregistered
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_UnRegisterCallback(UART_TypeDef *Instance, UART_UserCallbackIdETypeDef CallbackID)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ }
+
+ //UnRegister user callback
+ switch (CallbackID) {
+ case UART_TX_CPLT_CB_ID:
+ if (uart_hdl->tx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Tx isn't in Ready state, can't unregister Tx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ uart_hdl->user_callback.TxCpltCallback = NULL;
+ break;
+
+ case UART_RX_CPLT_CB_ID:
+ if (uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ uart_hdl->user_callback.RxCpltCallback = NULL;
+ break;
+
+ case UART_TX_HALF_CPLT_CB_ID:
+ if (uart_hdl->tx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Tx isn't in Ready state, can't unregister Tx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ uart_hdl->user_callback.TxHalfCpltCallback = NULL;
+ break;
+
+ case UART_RX_HALF_CPLT_CB_ID:
+ if (uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Rx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ uart_hdl->user_callback.RxHalfCpltCallback = NULL;
+ break;
+
+ case UART_ERROR_CB_ID:
+ if (uart_hdl->tx_ctrl.state != UART_STATE_READY || uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Tx&Rx are both not in Ready state, can't unregister Error callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ uart_hdl->user_callback.ErrorCallback = NULL;
+ break;
+
+ default:
+ LOG_E("UART user callback ID-[%d] is Invalid!\n", CallbackID);
+ return LL_INVALID;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup UART_LL_Exported_Functions_Group2 UART Transmit and Recieve Function
+ * @brief UART Transmit and Recieve Function
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode
+ * @note When UART parity is not enabled, and Word Length is configured to 9 bits,
+ * the sent data is handled as a set of u16. In this case, size must indicate the number
+ * of u16 provided through buf.
+ * @param Instance Specifies UART peripheral
+ * @param buf Pointer to data buffer (u8 or u16 data elements)
+ * @param size Amount of data elements (u8 or u16) to be sent
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_Transmit_CPU(UART_TypeDef *Instance, uint8_t *buf, uint16_t size, uint32_t timeout)
+{
+ bool tx_9bits_en;
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_UART_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->tx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Tx READY state, can't start Tx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ uart_hdl->tx_ctrl.state = UART_STATE_BUSY_TX;
+ uart_hdl->tx_ctrl.cnt = 0;
+ uart_hdl->tx_ctrl.isr = NULL;
+ uart_hdl->tx_ctrl.buf = buf;
+ uart_hdl->tx_ctrl.size = size;
+ tx_9bits_en = (bool)(__LL_UART_IsExtBitEn(Instance) && !__LL_UART_IsTxExtAddrMatchMode(Instance) &&
+ (UART_DatLenETypeDef)__LL_UART_DatLen_Get(Instance) >= UART_DAT_LEN_8b);
+
+ //Clear TxFIFO and TX Done Pending
+ __LL_UART_TxFIFO_Reset(Instance);
+ __LL_UART_TxDoneIntPnd_Clr(Instance);
+ __LL_UART_Tx_En(Instance);
+ tickstart = LL_GetTick();
+
+ //Transmit data loop
+ while (uart_hdl->tx_ctrl.cnt < uart_hdl->tx_ctrl.size) {
+ //if CPU has been broken a long time by Interrupt, the TxDone flag maybe set
+ if (__LL_UART_IsTxDoneIntPnd(Instance)) {
+ __LL_UART_TxDoneIntPnd_Clr(Instance);
+ }
+
+ //Wait TxFIFO to be not full
+ while (__LL_UART_IsTxFIFOFull(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Write data to TxFIFO
+ if (tx_9bits_en) {
+ __LL_UART_TxDat9bits_Write(Instance, *(uint16_t *)uart_hdl->tx_ctrl.buf);
+ uart_hdl->tx_ctrl.buf += 2;
+ } else {
+ __LL_UART_TxDat8bits_Write(Instance, *uart_hdl->tx_ctrl.buf++);
+ }
+
+ uart_hdl->tx_ctrl.cnt++;
+ }
+
+ //Wait for UART Transmit completed
+ while (!__LL_UART_IsTxDoneIntPnd(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Clear TX Done Pending
+ __LL_UART_TxDoneIntPnd_Clr(Instance);
+
+ ret = LL_OK;
+
+exit:
+ uart_hdl->tx_ctrl.state = UART_STATE_READY;
+ return ret;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode
+ * @note When UART parity is not enabled, and Word Length is configured to 9 bits ,
+ * the received data is handled as a set of u16. In this case, size must indicate the number
+ * of u16 available through buf.
+ * @param Instance Specifies UART peripheral
+ * @param buf Pointer to data buffer (u8 or u16 data elements)
+ * @param size Amount of data elements (u8 or u16) to be sent
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_Receive_CPU(UART_TypeDef *Instance, uint8_t *buf, uint16_t size, uint32_t timeout)
+{
+ bool rx_9bits_en;
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_UART_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Rx READY state, can't start Rx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ uart_hdl->rx_ctrl.state = UART_STATE_BUSY_RX;
+ uart_hdl->rx_ctrl.cnt = 0;
+ uart_hdl->rx_ctrl.isr = NULL;
+ uart_hdl->rx_ctrl.buf = buf;
+ uart_hdl->rx_ctrl.size = size;
+ rx_9bits_en = (bool)(__LL_UART_IsExtBitEn(Instance) && !__LL_UART_IsRxExtAddrMatchMode(Instance) &&
+ (UART_DatLenETypeDef)__LL_UART_DatLen_Get(Instance) >= UART_DAT_LEN_8b);
+
+ //Clear RxFIFO
+ __LL_UART_RxFIFO_Reset(Instance);
+ __LL_UART_Rx_En(Instance);
+ tickstart = LL_GetTick();
+
+ //Receive data loop
+ while (uart_hdl->rx_ctrl.cnt < uart_hdl->rx_ctrl.size) {
+ //Wait RxFIFO to be not empty
+ while (__LL_UART_IsRxFIFOEmpty(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+
+ //Read data from RxFIFO
+ if (rx_9bits_en) {
+ *(uint16_t *)uart_hdl->rx_ctrl.buf = (uint16_t)(__LL_UART_RxDat9bits_Read(Instance));
+ uart_hdl->rx_ctrl.buf += 2;
+ } else {
+ *uart_hdl->rx_ctrl.buf++ = (uint8_t)(__LL_UART_RxDat8bits_Read(Instance));
+ }
+
+ uart_hdl->rx_ctrl.cnt++;
+ }
+
+ ret = LL_OK;
+
+exit:
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+ return ret;
+}
+
+
+/**
+ * @brief Send an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies UART peripheral
+ * @param buf Pointer to data buffer (u8 or u16 data elements)
+ * @param size Amount of data elements (u8 or u16) to be sent
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_Transmit_IT(UART_TypeDef *Instance, uint8_t *buf, uint16_t size)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_UART_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->tx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Tx READY state, can't start Tx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ uart_hdl->tx_ctrl.state = UART_STATE_BUSY_TX;
+ uart_hdl->tx_ctrl.buf = buf;
+ uart_hdl->tx_ctrl.size = size;
+ uart_hdl->tx_ctrl.cnt = 0;
+ LL_FUNC_ALTER(__LL_UART_IsExtBitEn(Instance) && !__LL_UART_IsTxExtAddrMatchMode(Instance) &&
+ (UART_DatLenETypeDef)__LL_UART_DatLen_Get(Instance) >= UART_DAT_LEN_8b,
+ uart_hdl->tx_ctrl.isr = UART_TxISR_16BIT,
+ uart_hdl->tx_ctrl.isr = UART_TxISR_8BIT);
+
+ //Clear TxFIFO and TX Done Pending
+ __LL_UART_TxFIFO_Reset(Instance);
+ __LL_UART_TxDoneIntPnd_Clr(Instance);
+ __LL_UART_Tx_En(Instance);
+
+ //Tx Empty Interrupt Enable
+ __LL_UART_TxEmpty_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies UART peripheral
+ * @param buf Pointer to data buffer (u8 or u16 data elements)
+ * @param size Amount of data elements (u8 or u16) to be sent
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_Receive_IT(UART_TypeDef *Instance, uint8_t *buf, uint16_t size)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_UART_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Rx READY state, can't start Rx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ uart_hdl->rx_ctrl.state = UART_STATE_BUSY_RX;
+ uart_hdl->rx_ctrl.buf = buf;
+ uart_hdl->rx_ctrl.size = size;
+ uart_hdl->rx_ctrl.cnt = 0;
+ LL_FUNC_ALTER(__LL_UART_IsExtBitEn(Instance) && !__LL_UART_IsRxExtAddrMatchMode(Instance) &&
+ (UART_DatLenETypeDef)__LL_UART_DatLen_Get(Instance) >= UART_DAT_LEN_8b,
+ uart_hdl->rx_ctrl.isr = UART_RxISR_16BIT,
+ uart_hdl->rx_ctrl.isr = UART_RxISR_8BIT);
+
+ //Clear RxFIFO
+ __LL_UART_RxFIFO_Reset(Instance);
+ __LL_UART_Rx_En(Instance);
+
+ //Rx TimeOut Interrupt Enable if RxFIFO Full Trigger Level more than 1
+ if (__LL_UART_RxFIFOFullThres_Get(Instance) > 1) {
+ __LL_UART_RxTimeout_INT_En(Instance);
+ }
+
+ //RxFIFO Full Interrupt Enable
+ __LL_UART_RxFull_INT_En(Instance);
+
+ return LL_OK;
+}
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief Send an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies UART peripheral
+ * @param buf Pointer to data buffer (u8 or u16 data elements)
+ * @param size Amount of data elements (u8 or u16) to be sent
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_Transmit_DMA(UART_TypeDef *Instance, uint8_t *buf, uint16_t size)
+{
+ uint32_t dma_size;
+ UART_HandleTypeDef *uart_hdl;
+ DMA_UserCfgTypeDef dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_UART_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->tx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Tx READY state, can't start Tx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //DMA Init
+ memset((void *)&dma_user_cfg, 0, sizeof(dma_user_cfg));
+
+ if (__LL_UART_IsExtBitEn(Instance) && !__LL_UART_IsTxExtAddrMatchMode(Instance) &&
+ (UART_DatLenETypeDef)__LL_UART_DatLen_Get(Instance) >= UART_DAT_LEN_8b) {
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_16b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_16b;
+ dma_size = size * 2;
+ } else {
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_8b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_8b;
+ dma_size = size;
+ }
+
+ dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_FIX;
+ dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == UART0) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_UART0_TX;
+ } else if (Instance == UART1) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_UART1_TX;
+ } else if (Instance == UART2) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_UART2_TX;
+ } else if (Instance == UART3) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_UART3_TX;
+ } else if (Instance == UART4) {
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_UART4_TX;
+ } else {
+ LOG_E("UART DMA destination handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Transmit Default Config
+ dma_user_cfg.trans_type = DMA_TRANS_TYPE_M2P;
+ dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_INC;
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ dma_user_cfg.end_arg = (void *)Instance;
+ dma_user_cfg.end_callback = (DMA_IRQCallback)UART_DMATransmitCplt;
+ dma_user_cfg.err_arg = (void *)Instance;
+ dma_user_cfg.err_callback = (DMA_IRQCallback)UART_DMATransmitError;
+ dma_user_cfg.half_arg = (void *)Instance;
+ dma_user_cfg.half_callback = (DMA_IRQCallback)UART_DMAHalfTransmitCplt;
+
+ uart_hdl->tx_ctrl.dma_ch = UART_DMA_Init(&dma_user_cfg);
+
+ if (uart_hdl->tx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("UART transmit request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Transmit config
+ uart_hdl->tx_ctrl.state = UART_STATE_BUSY_TX;
+ uart_hdl->tx_ctrl.buf = buf;
+ uart_hdl->tx_ctrl.size = dma_size;
+ uart_hdl->tx_ctrl.cnt = 0;
+ uart_hdl->tx_ctrl.isr = NULL;
+
+ //Clear TxFIFO and TX Done Pending
+ __LL_UART_TxFIFO_Reset(Instance);
+ __LL_UART_TxDoneIntPnd_Clr(Instance);
+ __LL_UART_Tx_En(Instance);
+
+ //UART TX DMA Enable
+ __LL_UART_TxDMA_En(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, uart_hdl->tx_ctrl.dma_ch, (uint32_t)uart_hdl->tx_ctrl.buf, (uint32_t)&Instance->TDR, uart_hdl->tx_ctrl.size);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies UART peripheral
+ * @param buf Pointer to data buffer (u8 or u16 data elements)
+ * @param size Amount of data elements (u8 or u16) to be received
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_Receive_DMA(UART_TypeDef *Instance, uint8_t *buf, uint16_t size)
+{
+ uint32_t dma_size;
+ UART_HandleTypeDef *uart_hdl;
+ DMA_UserCfgTypeDef dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_UART_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Rx READY state, can't start Rx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //DMA Init
+ memset((void *)&dma_user_cfg, 0, sizeof(dma_user_cfg));
+
+ if (__LL_UART_IsExtBitEn(Instance) && !__LL_UART_IsRxExtAddrMatchMode(Instance) &&
+ (UART_DatLenETypeDef)__LL_UART_DatLen_Get(Instance) >= UART_DAT_LEN_8b) {
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_16b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_16b;
+ dma_size = size * 2;
+ } else {
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_8b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_8b;
+ dma_size = size;
+ }
+
+ dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_FIX;
+ dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == UART0) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_UART0_RX;
+ } else if (Instance == UART1) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_UART1_RX;
+ } else if (Instance == UART2) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_UART2_RX;
+ } else if (Instance == UART3) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_UART3_RX;
+ } else if (Instance == UART4) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_UART4_RX;
+ } else {
+ LOG_E("UART DMA source handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Receive Default Config
+ dma_user_cfg.trans_type = DMA_TRANS_TYPE_P2M;
+ dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_INC;
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ dma_user_cfg.end_arg = (void *)Instance;
+ dma_user_cfg.end_callback = (DMA_IRQCallback)UART_DMAReceiveCplt;
+ dma_user_cfg.err_arg = (void *)Instance;
+ dma_user_cfg.err_callback = (DMA_IRQCallback)UART_DMAReceiveError;
+ dma_user_cfg.half_arg = (void *)Instance;
+ dma_user_cfg.half_callback = (DMA_IRQCallback)UART_DMAHalfReceiveCplt;
+
+ //Transmit config
+ uart_hdl->rx_ctrl.state = UART_STATE_BUSY_RX;
+ uart_hdl->rx_ctrl.buf = buf;
+ uart_hdl->rx_ctrl.size = dma_size;
+ uart_hdl->rx_ctrl.cnt = 0;
+ uart_hdl->rx_ctrl.isr = NULL;
+
+ uart_hdl->rx_ctrl.dma_ch = UART_DMA_Init(&dma_user_cfg);
+
+ if (uart_hdl->rx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("UART receive request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Clear RxFIFO
+ __LL_UART_RxFIFO_Reset(Instance);
+ __LL_UART_Rx_En(Instance);
+
+ //UART RX DMA Enable
+ __LL_UART_RxDMA_En(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, uart_hdl->rx_ctrl.dma_ch, (uint32_t)&Instance->RDR, (uint32_t)uart_hdl->rx_ctrl.buf, uart_hdl->rx_ctrl.size);
+
+ return LL_OK;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+
+/** @defgroup UART_LL_Exported_Functions_Group3 UART Misc Functions
+ * @brief UART Misc Functions
+ * @{
+ */
+
+/**
+ * @brief Abort ongoing Transmit transfer for CPU blocking mode
+ * @param Instance Specifies UART peripheral
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_AbortTransmit_CPU(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->tx_ctrl.state != UART_STATE_BUSY_TX) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Tx state, can't abort Tx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check UART is in Tx IT state or not
+ if (uart_hdl->tx_ctrl.isr) {
+ LOG_E("This UART[0x%08" PRIx32 "] is in Tx_IT state, can't abort it through CPU interface!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+ //Check UART is in Tx DMA state or not
+ if (uart_hdl->tx_ctrl.dma_ch != DMA_CHANNEL_INVALID) {
+ LOG_E("This UART[0x%08" PRIx32 "] is in Tx_DMA state, can't abort it through CPU interface!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+#endif
+
+ //Clear TxFIFO
+ __LL_UART_TxFIFO_Reset(Instance);
+
+ //Set to complete
+ uart_hdl->tx_ctrl.cnt = uart_hdl->tx_ctrl.size;
+ uart_hdl->tx_ctrl.state = UART_STATE_READY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer for CPU blocking mode
+ * @param Instance Specifies UART peripheral
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_AbortReceive_CPU(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->rx_ctrl.state != UART_STATE_BUSY_RX) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Rx state, can't abort Rx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check UART is in Rx IT state or not
+ if (uart_hdl->rx_ctrl.isr) {
+ LOG_E("This UART[0x%08" PRIx32 "] is in Rx_IT state, can't abort it through CPU interface!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+ //Check UART is in Rx DMA state or not
+ if (uart_hdl->rx_ctrl.dma_ch != DMA_CHANNEL_INVALID) {
+ LOG_E("This UART[0x%08" PRIx32 "] is in Rx_DMA state, can't abort it through CPU interface!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+#endif
+
+ //Clear RxFIFO
+ __LL_UART_RxFIFO_Reset(Instance);
+
+ //Check RxFIFO any error or not
+ if (__LL_UART_IsRxFIFOErr(Instance)) {
+ __LL_UART_RxFIFOErrIntPnd_Clr(Instance);
+ }
+
+ //Set to complete
+ uart_hdl->rx_ctrl.cnt = uart_hdl->rx_ctrl.size;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer for Interrupt mode
+ * @param Instance Specifies UART peripheral
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_AbortTransmit_IT(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->tx_ctrl.state != UART_STATE_BUSY_TX) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Tx state, can't abort Tx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check UART is in Tx IT state or not
+ if (uart_hdl->tx_ctrl.isr == NULL) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Tx_IT state, can't abort it through IT interface!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check has Tx complete or not
+ if (uart_hdl->tx_ctrl.isr == UART_TxDone_ISR) {
+ LOG_E("This UART[0x%08" PRIx32 "] has Tx complete and now is waiting for Tx_Done interrupt flag, can't abort it!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //TxFIFO Empty Interrupt Disable
+ __LL_UART_TxEmpty_INT_Dis(Instance);
+ uart_hdl->tx_ctrl.isr = NULL;
+
+ //Clear TxFIFO
+ __LL_UART_TxFIFO_Reset(Instance);
+
+ //Set to complete
+ uart_hdl->tx_ctrl.cnt = uart_hdl->tx_ctrl.size;
+ uart_hdl->tx_ctrl.state = UART_STATE_READY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer for Interrupt mode
+ * @param Instance Specifies UART peripheral
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_AbortReceive_IT(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->rx_ctrl.state != UART_STATE_BUSY_RX) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Rx state, can't abort Rx!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check UART is in Rx IT state or not
+ if (uart_hdl->rx_ctrl.isr == NULL) {
+ LOG_E("This UART[0x%08" PRIx32 "] isn't in Rx_IT state, can't abort it through IT interface!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //RxFIFO Full Interrupt Disable
+ __LL_UART_RxFull_INT_Dis(Instance);
+ uart_hdl->rx_ctrl.isr = NULL;
+
+ //Rx Timeout Interrupt Disable
+ if (__LL_UART_RxFIFOFullThres_Get(Instance) > 1) {
+ __LL_UART_RxTimeout_INT_Dis(Instance);
+ }
+
+ //Clear RxFIFO
+ __LL_UART_RxFIFO_Reset(Instance);
+
+ //Check RxFIFO any error or not
+ if (__LL_UART_IsRxFIFOErr(Instance)) {
+ __LL_UART_RxFIFOErrIntPnd_Clr(Instance);
+ }
+
+ //Set to complete
+ uart_hdl->rx_ctrl.cnt = uart_hdl->rx_ctrl.size;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+
+ return LL_OK;
+}
+
+/**
+ * @brief UART LL Tx Extend Address Config on runtime
+ * @param Instance Specifies UART peripheral
+ * @param tx_addr_ext tx extend address
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_Uart_TxExtAddrCfg(UART_TypeDef *Instance, uint8_t tx_addr_ext)
+{
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ if (!__LL_UART_IsExtBitEn(Instance)) {
+ LOG_E("Extend Bit feature isn't Enable!\n");
+ return LL_ERROR;
+ }
+
+ //Tx Extend Address Config
+ __LL_UART_TxExtAddr_Set(Instance, tx_addr_ext);
+ __LL_UART_TxExtMode_Set(Instance, UART_EXT_MODE_ADDR_MATCH);
+
+ return LL_OK;
+}
+
+/**
+ * @brief UART LL RS485 Config
+ * @param Instance Specifies UART peripheral
+ * @param cfg RS485 config pointer
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_RS485Cfg(UART_TypeDef *Instance, UART_Rs485CfgTypeDef *cfg)
+{
+ bool uart_en;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+ assert_param(cfg != NULL);
+
+ if (!IS_UART_ALL_INSTANCE(Instance) || cfg == NULL) {
+ return LL_INVALID;
+ }
+
+ //UART Enable state store and set UART Disable to config following params
+ uart_en = __LL_UART_IsEn(Instance);
+ __LL_UART_Dis(Instance);
+
+ if (!cfg->enable) {
+ __LL_UART_RS485_Dis(Instance);
+ goto exit;
+ }
+
+ //RS485 Config
+ __LL_UART_DE_Pol_Set(Instance, cfg->de_pol);
+ __LL_UART_RE_Pol_Set(Instance, cfg->re_pol);
+ __LL_UART_DE_AssertTime_Set(Instance, cfg->de_assert_time);
+ __LL_UART_DE_DeAssertTime_Set(Instance, cfg->de_deassert_time);
+ __LL_UART_DEtoRE_TurnAroundTime_Set(Instance, cfg->de2re_turn_ard_time);
+ __LL_UART_REtoDE_TurnAroundTime_Set(Instance, cfg->re2de_turn_ard_time);
+
+ //RS485 Enable
+ __LL_UART_RS485_En(Instance);
+
+exit:
+ //Recover UART to Enable if need
+ LL_FUNC_ALTER(uart_en, __LL_UART_En(Instance), (void)0U);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Update on the fly the receiver timeout value
+ * @param Instance UART peripheral
+ * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout value must be less or equal to 0xFFFF
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_ReceiverTimeout_Config(UART_TypeDef *Instance, uint16_t TimeoutValue)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->rx_ctrl.state == UART_STATE_RESET) {
+ LOG_E("This UART[0x%08" PRIx32 "] Rx is in Reset state, can't config receiver timeout value!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Set Rx Timeout value
+ __LL_UART_RxTimeoutTime_Set(Instance, TimeoutValue);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Enable the UART receiver timeout feature
+ * @param Instance UART peripheral
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_EnableReceiverTimeout(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Rx isn't in Ready state, can't enable receiver timeout feature!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ __LL_UART_RxTimeout_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Disable the UART receiver timeout feature
+ * @param Instance UART peripheral
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_DisableReceiverTimeout(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if (uart_hdl->rx_ctrl.state != UART_STATE_READY) {
+ LOG_E("This UART[0x%08" PRIx32 "] Rx isn't in Ready state, can't disable receiver timeout feature!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ __LL_UART_RxTimeout_Dis(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief UART LL Auto Baud Rate Config
+ * @note (1) The actual timeout value maybe is 'timeout + 2' if timeout is effected.
+ * (2) This function can be used when Rx & Tx Idle only.
+ * @param Instance Specifies UART peripheral
+ * @param cfg Auto Baud Rate config pointer
+ * @param timeout Timeout for waitting detection
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_UART_AutoBaudRateCfg(UART_TypeDef *Instance, UART_AutoBaudCfgTypeDef *cfg, uint32_t timeout)
+{
+ UART_HandleTypeDef *uart_hdl;
+ uint32_t pre_time, rem_time;
+ volatile uint32_t use_time = 0;
+ uint32_t baud_rate;
+ uint8_t is_uart_en;
+ uint8_t is_over_sample_x8;
+ LL_StatusETypeDef err_status;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+ assert_param(cfg != NULL);
+
+ if (!IS_UART_ALL_INSTANCE(Instance) || cfg == NULL || cfg->default_baud == 0) {
+ return LL_INVALID;
+ }
+
+ if (cfg->detect_at_once && (timeout == 0)) {
+ return LL_INVALID;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return LL_ERROR;
+ } else if ((uart_hdl->rx_ctrl.state != UART_STATE_READY) || (uart_hdl->tx_ctrl.state != UART_STATE_READY)) {
+ LOG_E("This UART[0x%08" PRIx32 "] Rx/Tx isn't in Ready state!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ uart_hdl->rx_ctrl.state = UART_STATE_BUSY;
+ uart_hdl->tx_ctrl.state = UART_STATE_BUSY;
+
+ baud_rate = __LL_UART_Baudrate_Read(Instance);
+ is_uart_en = __LL_UART_IsEn(Instance);
+
+ //Baudrate check
+ if (Instance == UART0 || Instance == UART1 || Instance == UART2) {
+ baud_rate = (LL_RCU_APB0ClkGet() + cfg->default_baud / 2) / cfg->default_baud;
+ } else if (Instance == UART3 || Instance == UART4) {
+ baud_rate = (LL_RCU_APB1ClkGet() + cfg->default_baud / 2) / cfg->default_baud;
+ } else {
+ err_status = LL_INVALID;
+ goto ABNORMAL_EXIT;
+ }
+
+ if (baud_rate == 0) {
+ err_status = LL_INVALID;
+ goto ABNORMAL_EXIT;
+ }
+
+ if (((!is_uart_en) && (cfg->detect_at_once))) {
+ err_status = LL_ERROR;
+ goto ABNORMAL_EXIT;
+ }
+
+ if (cfg->over_samp_refresh == false) {
+ is_over_sample_x8 = __LL_UART_IsOverSampleX8(Instance);
+
+ if (is_over_sample_x8) {
+ if (baud_rate < 0x8) {
+ LOG_E("BAUD value is too small when OverSample is 8X \n");
+ err_status = LL_INVALID;
+ goto ABNORMAL_EXIT;
+ }
+ } else {
+ if (baud_rate < 0x10) {
+ LOG_E("BAUD value is too small when OverSample is 16X \n");
+ err_status = LL_INVALID;
+ goto ABNORMAL_EXIT;
+ }
+ }
+
+ } else {
+ if (cfg->over_samp_reload == UART_OVER_SAMP_16X) {
+ if (baud_rate < 0x10) {
+ LOG_E("BAUD value is too small for UART_OVER_SAMP_16X \n");
+ err_status = LL_INVALID;
+ goto ABNORMAL_EXIT;
+ }
+
+ __LL_UART_Dis(Instance);
+ __LL_UART_OverSampleMode_Set(Instance, cfg->over_samp_reload);
+ } else if (cfg->over_samp_reload == UART_OVER_SAMP_8X) {
+ if (baud_rate < 0x8) {
+ LOG_E("BAUD value is too small for UART_OVER_SAMP_8X \n");
+ err_status = LL_INVALID;
+ goto ABNORMAL_EXIT;
+ }
+
+ __LL_UART_Dis(Instance);
+ __LL_UART_OverSampleMode_Set(Instance, cfg->over_samp_reload);
+ } else {
+ err_status = LL_INVALID;
+ goto ABNORMAL_EXIT;
+ }
+ }
+
+ __LL_UART_Dis(Instance);
+ __LL_UART_Baudrate_Set(Instance, baud_rate);
+ LL_FUNC_ALTER(is_uart_en, __LL_UART_En(Instance), __LL_UART_Dis(Instance));
+
+ //Set Auto-baudrate Mode
+ __LL_UART_AutoBaudRateMode_Set(Instance, cfg->mode);
+
+ //Detect baud rate at once
+ if (!cfg->detect_at_once) {
+ goto NORMAL_END;
+ }
+
+ pre_time = LL_GetTick();
+
+ while (__LL_UART_IsAutoBaudRateEn(Instance)) {
+ use_time = LL_GetTick() - pre_time;
+ if (use_time > timeout) {
+ err_status = LL_TIMEOUT;
+ goto ABNORMAL_EXIT;
+ }
+ }
+
+ //Start once detect
+ __LL_UART_TxFIFO_Reset(Instance);
+ __LL_UART_RxFIFO_Reset(Instance);
+ __LL_UART_AutoBaudRate_En(Instance);
+
+ rem_time = (timeout > use_time) ? (timeout - use_time) : 2;
+ pre_time = LL_GetTick();
+
+ while (__LL_UART_IsAutoBaudRateEn(Instance)) {
+ use_time = LL_GetTick() - pre_time;
+ if (use_time > rem_time) {
+ err_status = LL_TIMEOUT;
+ goto ABNORMAL_EXIT;
+ }
+ }
+
+NORMAL_END:
+ __LL_UART_TxFIFO_Reset(Instance);
+ __LL_UART_RxFIFO_Reset(Instance);
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+ uart_hdl->tx_ctrl.state = UART_STATE_READY;
+ return LL_OK;
+
+ABNORMAL_EXIT:
+ __LL_UART_TxFIFO_Reset(Instance);
+ __LL_UART_RxFIFO_Reset(Instance);
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+ uart_hdl->tx_ctrl.state = UART_STATE_READY;
+ return err_status;
+}
+
+/**
+ * @brief UART LL Handle Get
+ * @param Instance Specifies UART peripheral
+ * @return UART_HandleTypeDef pointer
+ */
+UART_HandleTypeDef *LL_UART_Handle_Get(UART_TypeDef *Instance)
+{
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return NULL;
+ }
+
+ return UART_Handle_Get(Instance);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup UART_LL_Exported_Functions_Interrupt UART Interrupt Handler and Callback
+ * @brief UART Interrupt Handler and Callback
+ * @{
+ */
+
+/**
+ * @brief UART LL IRQ Handler
+ * @param Instance UART peripheral
+ * @return None
+ */
+void LL_UART_IRQHandler(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+ uint32_t int_en, int_pending;
+
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (!IS_UART_ALL_INSTANCE(Instance)) {
+ return;
+ }
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ //All Interrupt Enalbe and Pending Get
+ int_en = __LL_UART_AllIntEn_Get(Instance);
+ int_pending = __LL_UART_AllIntPnd_Get(Instance);
+
+
+ //Rx Address Match Interrupt Handler
+ if ((int_en & UART0_INTEN_AMIE_Msk) && (int_pending & UART0_INT_AMIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_RxAddrMatchIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_RxAddrMatchCallback(Instance);
+ }
+
+ //Tx Idle Done Interrupt Handler
+ if ((int_en & UART0_INTEN_IDLE_Msk) && (int_pending & UART0_INT_IDLF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_TxIdleDoneIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_TxIdleDoneCallback(Instance);
+ }
+
+ //Tx Break Done Interrupt Handler
+ if ((int_en & UART0_INTEN_TBIE_Msk) && (int_pending & UART0_INT_TBIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_TxBreakDoneIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_TxBreakDoneCallback(Instance);
+ }
+
+ //Tx Done Interrupt Handler
+ if ((int_en & UART0_INTEN_TDIE_Msk) && (int_pending & UART0_INT_TDIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_TxDoneIntPnd_Clr(Instance);
+
+ if (uart_hdl->tx_ctrl.cnt >= uart_hdl->tx_ctrl.size && uart_hdl->tx_ctrl.isr) {
+ uart_hdl->tx_ctrl.isr(Instance);
+ }
+
+ //Callback
+ LL_UART_TxDoneCallback(Instance);
+ }
+
+ //Rx Timeout Interrupt Handler
+ if ((int_en & UART0_INTEN_RTIE_Msk) && (int_pending & UART0_INT_RTOI_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_RxTimeoutIntPnd_Clr(Instance);
+
+ if (__LL_UART_RxFIFOFullThres_Get(Instance) > 1) {
+ UART_RxTimeout_ISR(Instance);
+ }
+
+ //Callback
+ LL_UART_RxTimeoutCallback(Instance);
+ }
+
+ //Rx Break Interrupt Handler
+ if ((int_en & UART0_INTEN_BKIE_Msk) && (int_pending & UART0_INT_BKIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_RxBreakIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_RxBreakCallback(Instance);
+ }
+
+ //Frame Error Interrupt Handler
+ if ((int_en & UART0_INTEN_FEIE_Msk) && (int_pending & UART0_INT_FEIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_FrameErrIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_FrameErrCallback(Instance);
+ }
+
+ //Parity Error Interrupt Handler
+ if ((int_en & UART0_INTEN_PEIE_Msk) && (int_pending & UART0_INT_PEIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_ParityErrIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_ParityErrCallback(Instance);
+ }
+
+ //Tx Overflow Interrupt Handler
+ if ((int_en & UART0_INTEN_TOIE_Msk) && (int_pending & UART0_INT_TOIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_TxFIFOOverFlowIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_TxFIFOOverFlowCallback(Instance);
+ }
+
+ //Rx Underflow Interrupt Handler
+ if ((int_en & UART0_INTEN_RUIE_Msk) && (int_pending & UART0_INT_RUIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_RxFIFOUnderFlowIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_RxFIFOUnderFlowCallback(Instance);
+ }
+
+ //Rx Overflow Interrupt Handler
+ if ((int_en & UART0_INTEN_ROIE_Msk) && (int_pending & UART0_INT_ROIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_RxFIFOOverFlowIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_RxFIFOOverFlowCallback(Instance);
+ }
+
+ //Tx Empty Interrupt Handler
+ if ((int_en & UART0_INTEN_TEIE_Msk) && (int_pending & UART0_INT_TXEI_Msk)) {
+ //interrupt pending auto clear
+
+ //Callback
+ if (uart_hdl->tx_ctrl.isr) {
+ uart_hdl->tx_ctrl.isr(Instance);
+ }
+
+ LL_UART_TxFIFOEmptyCallback(Instance);
+ }
+
+ //Rx Full Interrupt Handler
+ if ((int_en & UART0_INTEN_RFIE_Msk) && (int_pending & UART0_INT_RXFI_Msk)) {
+ //interrupt pending auto clear
+
+ //Callback
+ if (uart_hdl->rx_ctrl.isr) {
+ uart_hdl->rx_ctrl.isr(Instance);
+ }
+
+ LL_UART_RxFIFOFullCallback(Instance);
+ }
+
+ //The following features are available for later versions
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ return;
+ }
+
+ //Rx Idle Interrupt Handler
+ if ((int_en & UART0_INTEN_IDIE_Msk) && (int_pending & UART0_INT_IDIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_RxIdleIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_RxIdleDoneCallback(Instance);
+ }
+
+ //Noise Detection Interrupt Handler
+ if ((int_en & UART0_INTEN_NOIE_Msk) && (int_pending & UART0_INT_NOIF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_NoiseDetectIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_NoiseDetectCallback(Instance);
+ }
+
+ //Auto Baud Rate Error Interrupt Handler
+ if ((int_en & UART0_INTEN_ABRE_Msk) && (int_pending & UART0_INT_ABRF_Msk)) {
+ //Interrupt Pending Clear
+ __LL_UART_AutoBaudRateErrIntPnd_Clr(Instance);
+
+ //Callback
+ LL_UART_AutoBaudRateErrCallback(Instance);
+ }
+}
+
+/**
+ * @brief UART LL Auto Baud Rate Error Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_AutoBaudRateErrCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_AutoBaudRateErrCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL Rx Address Match Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_RxAddrMatchCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_RxAddrMatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL Tx Idle Done Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_TxIdleDoneCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_TxIdleDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL Tx Break Done Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_TxBreakDoneCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_TxBreakDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL TX Done Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_TxDoneCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_TxDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL RX Timeout Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_RxTimeoutCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_RxTimeoutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL Rx Break Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_RxBreakCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_RxBreakCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL Frame Error Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_FrameErrCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_FrameErrCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL Parity Error Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_ParityErrCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_ParityErrCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL Noise Detection Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_NoiseDetectCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_NoiseDetectCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL Rx Idle Done Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_RxIdleDoneCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_RxIdleDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL TxFIFO OverFlow Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_TxFIFOOverFlowCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_TxFIFOOverFlowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL RxFIFO UnderFlow Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_RxFIFOUnderFlowCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_RxFIFOUnderFlowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL RxFIFO OverFlow Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_RxFIFOOverFlowCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_RxFIFOOverFlowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL TxFIFO Empty Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_TxFIFOEmptyCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_TxFIFOEmptyCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief UART LL RxFIFO Full Interrupt Callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+__WEAK void LL_UART_RxFIFOFullCallback(UART_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_UART_RxFIFOFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup UART_LL_Private_Functions UART LL Private function
+ * @brief UART LL Private function
+ * @{
+ */
+
+/**
+ * @brief UART Handle Get
+ * @param Instance Specifies UART peripheral
+ * @return UART_HandleTypeDef pointer
+ */
+static UART_HandleTypeDef *UART_Handle_Get(UART_TypeDef *Instance)
+{
+ //Assert param
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+
+ if (Instance == UART0) {
+ return &uart_hdl_global[UART_INSTANCE_0];
+ } else if (Instance == UART1) {
+ return &uart_hdl_global[UART_INSTANCE_1];
+ } else if (Instance == UART2) {
+ return &uart_hdl_global[UART_INSTANCE_2];
+ } else if (Instance == UART3) {
+ return &uart_hdl_global[UART_INSTANCE_3];
+ } else if (Instance == UART4) {
+ return &uart_hdl_global[UART_INSTANCE_4];
+ }
+
+ return NULL;
+}
+
+/**
+ * @brief UART TxDone Interrupt Service Routine
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_TxDone_ISR(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ if (uart_hdl->tx_ctrl.cnt >= uart_hdl->tx_ctrl.size) {
+ //Disable Tx Done Interrupt
+ __LL_UART_TxDone_INT_Dis(Instance);
+ uart_hdl->tx_ctrl.isr = NULL;
+ uart_hdl->tx_ctrl.state = UART_STATE_READY;
+
+ //Tx Complete Callback
+ if (uart_hdl->user_callback.TxCpltCallback) {
+ uart_hdl->user_callback.TxCpltCallback();
+ }
+ }
+}
+
+/**
+ * @brief UART RxTimeout Interrupt Service Routine
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_RxTimeout_ISR(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ if (uart_hdl->rx_ctrl.state == UART_STATE_BUSY_RX) { //In Rx Status
+ //Check is Interrupt Receive mode not, only handle Rx_IT mode, not handle Rx_CPU/Rx_DMA mode
+ if (uart_hdl->rx_ctrl.isr == NULL) {
+ return;
+ }
+
+ //Check buffer pointer to be valid, Check has received complete or not
+ if (uart_hdl->rx_ctrl.buf == NULL || uart_hdl->rx_ctrl.cnt >= uart_hdl->rx_ctrl.size) {
+ //Clear RxFIFO
+ __LL_UART_RxFIFO_Reset(Instance);
+ return;
+ }
+
+ //Check Rx Error or not
+ if (__LL_UART_IsRxFIFOErr(Instance)) {
+ LOG_E("<%s> error!\n", __FUNCTION__);
+
+ //RxFIFO Full Interrupt Disable
+ __LL_UART_RxFull_INT_Dis(Instance);
+ uart_hdl->rx_ctrl.isr = NULL;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+
+ //Error Callback
+ if (uart_hdl->user_callback.ErrorCallback) {
+ uart_hdl->user_callback.ErrorCallback();
+ }
+
+ return;
+ }
+
+ //Get RxFIFO level and Rx 9Bits Enable status
+ uint8_t rx_fifo_lvl = __LL_UART_RxFIFOLvl_Get(Instance);
+ bool rx_9bits_en = (bool)(__LL_UART_IsExtBitEn(Instance) && !__LL_UART_IsRxExtAddrMatchMode(Instance) &&
+ (UART_DatLenETypeDef)__LL_UART_DatLen_Get(Instance) >= UART_DAT_LEN_8b);
+
+ //Read remain data from RxFIFO until receive enough data
+ if (rx_9bits_en) {
+ while (rx_fifo_lvl-- && uart_hdl->rx_ctrl.cnt < uart_hdl->rx_ctrl.size) {
+ *(uint16_t *)uart_hdl->rx_ctrl.buf = (uint16_t)(__LL_UART_RxDat9bits_Read(Instance));
+ uart_hdl->rx_ctrl.buf += 2;
+ uart_hdl->rx_ctrl.cnt++;
+ }
+ } else {
+ while (rx_fifo_lvl-- && uart_hdl->rx_ctrl.cnt < uart_hdl->rx_ctrl.size) {
+ *uart_hdl->rx_ctrl.buf = (uint8_t)__LL_UART_RxDat8bits_Read(Instance);
+ uart_hdl->rx_ctrl.buf++;
+ uart_hdl->rx_ctrl.cnt++;
+ }
+ }
+
+ //RxFIFO Full Interrupt Disable
+ __LL_UART_RxFull_INT_Dis(Instance);
+ uart_hdl->rx_ctrl.isr = NULL;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+
+ //Complete or Error Callback
+ if (uart_hdl->rx_ctrl.cnt >= uart_hdl->rx_ctrl.size) {
+ //Rx Complete Callback
+ if (uart_hdl->user_callback.RxCpltCallback) {
+ uart_hdl->user_callback.RxCpltCallback();
+ }
+ } else {
+ //Error Callback
+ if (uart_hdl->user_callback.ErrorCallback) {
+ uart_hdl->user_callback.ErrorCallback();
+ }
+ }
+
+ //Rx Timeout Interrupt Disable
+ __LL_UART_RxTimeout_INT_Dis(Instance);
+
+ } else { //Not in Rx Status
+
+ //Clear RxFIFO
+ __LL_UART_RxFIFO_Reset(Instance);
+ }
+}
+
+/**
+ * @brief UART write 8bit data handle in Interrupt mode
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_TxISR_8BIT(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ //Write data to TxFIFO
+ if (!__LL_UART_IsTxFIFOFull(Instance) && uart_hdl->tx_ctrl.cnt < uart_hdl->tx_ctrl.size) {
+ //if TxDone flag has been set before write data to TxFIFO, clear it
+ if (__LL_UART_IsTxDoneIntPnd(Instance)) {
+ __LL_UART_TxDoneIntPnd_Clr(Instance);
+ }
+
+ __LL_UART_TxDat8bits_Write(Instance, *uart_hdl->tx_ctrl.buf);
+ uart_hdl->tx_ctrl.buf++;
+ uart_hdl->tx_ctrl.cnt++;
+ }
+
+ //Write Complete
+ if (uart_hdl->tx_ctrl.cnt >= uart_hdl->tx_ctrl.size) {
+ //TxFIFO Empty Interrupt Disable
+ __LL_UART_TxEmpty_INT_Dis(Instance);
+
+ //Switch isr to TxDone ISR
+ uart_hdl->tx_ctrl.isr = UART_TxDone_ISR;
+
+ //Enable Tx Done Interrupt
+ __LL_UART_TxDone_INT_En(Instance);
+ }
+}
+
+/**
+ * @brief UART write 16bit data handle in Interrupt mode
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_TxISR_16BIT(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ //Write data to TxFIFO
+ if (!__LL_UART_IsTxFIFOFull(Instance) && uart_hdl->tx_ctrl.cnt < uart_hdl->tx_ctrl.size) {
+ //if TxDone flag has been set before write data to TxFIFO, clear it
+ if (__LL_UART_IsTxDoneIntPnd(Instance)) {
+ __LL_UART_TxDoneIntPnd_Clr(Instance);
+ }
+
+ __LL_UART_TxDat9bits_Write(Instance, *(uint16_t *)uart_hdl->tx_ctrl.buf);
+ uart_hdl->tx_ctrl.buf += 2;
+ uart_hdl->tx_ctrl.cnt++;
+ }
+
+ //Write Complete
+ if (uart_hdl->tx_ctrl.cnt >= uart_hdl->tx_ctrl.size) {
+ //TxFIFO Empty Interrupt Disable
+ __LL_UART_TxEmpty_INT_Dis(Instance);
+
+ //Switch isr to TxDone ISR
+ uart_hdl->tx_ctrl.isr = UART_TxDone_ISR;
+
+ //Enable Tx Done Interrupt
+ __LL_UART_TxDone_INT_En(Instance);
+ }
+}
+
+/**
+ * @brief UART read 8bit data handle in Interrupt mode
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_RxISR_8BIT(UART_TypeDef *Instance)
+{
+ uint8_t rx_fifo_trig_lvl;
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ rx_fifo_trig_lvl = __LL_UART_RxFIFOFullThres_Get(Instance);
+
+ //Receive data from RxFIFO
+ while (rx_fifo_trig_lvl-- && uart_hdl->rx_ctrl.cnt < uart_hdl->rx_ctrl.size) {
+ //Rx Error
+ if (__LL_UART_IsRxFIFOErr(Instance)) {
+ LOG_E("<%s> error!\n", __FUNCTION__);
+
+ //RxFIFO Full Interrupt Disable
+ __LL_UART_RxFull_INT_Dis(Instance);
+ uart_hdl->rx_ctrl.isr = NULL;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+
+ //Error Callback
+ if (uart_hdl->user_callback.ErrorCallback) {
+ uart_hdl->user_callback.ErrorCallback();
+ }
+
+ return;
+ }
+
+ *uart_hdl->rx_ctrl.buf = (uint8_t)__LL_UART_RxDat8bits_Read(Instance);
+ uart_hdl->rx_ctrl.buf++;
+ uart_hdl->rx_ctrl.cnt++;
+ }
+
+ //Read Complete
+ if (uart_hdl->rx_ctrl.cnt >= uart_hdl->rx_ctrl.size) {
+ //RxFIFO Full Interrupt Disable
+ __LL_UART_RxFull_INT_Dis(Instance);
+ uart_hdl->rx_ctrl.isr = NULL;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+
+ //Rx Complete Callback
+ if (uart_hdl->user_callback.RxCpltCallback) {
+ uart_hdl->user_callback.RxCpltCallback();
+ }
+ }
+}
+
+/**
+ * @brief UART read 16bit data handle in Interrupt mode
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_RxISR_16BIT(UART_TypeDef *Instance)
+{
+ uint8_t rx_fifo_trig_lvl;
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ rx_fifo_trig_lvl = __LL_UART_RxFIFOFullThres_Get(Instance);
+
+ //Receive data from RxFIFO
+ while (rx_fifo_trig_lvl-- && uart_hdl->rx_ctrl.cnt < uart_hdl->rx_ctrl.size) {
+ //Rx Error
+ if (__LL_UART_IsRxFIFOErr(Instance)) {
+ LOG_E("<%s> error!\n", __FUNCTION__);
+
+ //RxFIFO Full Interrupt Disable
+ __LL_UART_RxFull_INT_Dis(Instance);
+ uart_hdl->rx_ctrl.isr = NULL;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+
+ //Error Callback
+ if (uart_hdl->user_callback.ErrorCallback) {
+ uart_hdl->user_callback.ErrorCallback();
+ }
+
+ return;
+ }
+
+ *(uint16_t *)uart_hdl->rx_ctrl.buf = (uint16_t)(__LL_UART_RxDat9bits_Read(Instance));
+ uart_hdl->rx_ctrl.buf += 2;
+ uart_hdl->rx_ctrl.cnt++;
+ }
+
+ //Read Complete
+ if (uart_hdl->rx_ctrl.cnt >= uart_hdl->rx_ctrl.size) {
+ //RxFIFO Full Interrupt Disable
+ __LL_UART_RxFull_INT_Dis(Instance);
+ uart_hdl->rx_ctrl.isr = NULL;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+
+ //Rx Complete Callback
+ if (uart_hdl->user_callback.RxCpltCallback) {
+ uart_hdl->user_callback.RxCpltCallback();
+ }
+ }
+}
+
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief UART LL DMA Init
+ * @param dma_user_cfg user dma config pointer
+ * @return DMA_ChannelETypeDef
+ */
+static DMA_ChannelETypeDef UART_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg)
+{
+ LL_StatusETypeDef ret;
+ DMA_ChannelETypeDef ch;
+
+ if (dma_user_cfg == NULL) {
+ return DMA_CHANNEL_INVALID;
+ }
+
+ //User DMA channel request
+ ch = LL_DMA_ChannelRequest();
+
+ if (ch == DMA_CHANNEL_INVALID) {
+ LOG_E("Requset DMA channel Fail!\n");
+ return DMA_CHANNEL_INVALID;
+ }
+
+ //User DMA init
+ ret = LL_DMA_Init(DMA, ch, dma_user_cfg);
+
+ if (ret != LL_OK) {
+ LOG_E("DMA LL init fail!\n");
+ LL_DMA_ChannelRelease(ch);
+ return DMA_CHANNEL_INVALID;
+ }
+
+ return ch;
+}
+
+/**
+ * @brief UART LL DMA DeInit
+ * @param ch DMA channel to DeInit
+ * @return None
+ */
+static void UART_DMA_DeInit(DMA_ChannelETypeDef ch)
+{
+ if (ch == DMA_CHANNEL_INVALID) {
+ return;
+ }
+
+ LL_DMA_Stop_IT(DMA, ch);
+ LL_DMA_DeInit(DMA, ch);
+ LL_DMA_ChannelRelease(ch);
+}
+
+/**
+ * @brief DMA UART transmit process complete callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_DMATransmitCplt(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ //Disable Tx DMA Request
+ __LL_UART_TxDMA_Dis(Instance);
+
+ //DMA DeInit
+ UART_DMA_DeInit(uart_hdl->tx_ctrl.dma_ch);
+ uart_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ uart_hdl->tx_ctrl.cnt = uart_hdl->tx_ctrl.size;
+
+ //Switch isr to TxDone ISR
+ uart_hdl->tx_ctrl.isr = UART_TxDone_ISR;
+
+ //Enable Tx Done Interrupt
+ __LL_UART_TxDone_INT_En(Instance);
+}
+
+/**
+ * @brief DMA UART receive process complete callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_DMAReceiveCplt(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ //Disable Rx DMA Request
+ __LL_UART_RxDMA_Dis(Instance);
+
+ //DMA DeInit
+ UART_DMA_DeInit(uart_hdl->rx_ctrl.dma_ch);
+ uart_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+
+ uart_hdl->rx_ctrl.cnt = uart_hdl->rx_ctrl.size;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+
+ //Rx Complete Callback
+ if (uart_hdl->user_callback.RxCpltCallback) {
+ uart_hdl->user_callback.RxCpltCallback();
+ }
+}
+
+/**
+ * @brief DMA UART transmit process half complete callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_DMAHalfTransmitCplt(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ //Tx Half Complete Callback
+ if (uart_hdl->user_callback.TxHalfCpltCallback) {
+ uart_hdl->user_callback.TxHalfCpltCallback();
+ }
+}
+
+/**
+ * @brief DMA UART receive process half complete callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_DMAHalfReceiveCplt(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ //Rx Half Complete Callback
+ if (uart_hdl->user_callback.RxHalfCpltCallback) {
+ uart_hdl->user_callback.RxHalfCpltCallback();
+ }
+}
+
+/**
+ * @brief DMA UART transmit process error callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_DMATransmitError(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ //Disable Tx DMA Request
+ __LL_UART_TxDMA_Dis(Instance);
+
+ //DMA DeInit
+ UART_DMA_DeInit(uart_hdl->tx_ctrl.dma_ch);
+
+ uart_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ uart_hdl->tx_ctrl.state = UART_STATE_READY;
+
+ if (uart_hdl->user_callback.ErrorCallback) {
+ uart_hdl->user_callback.ErrorCallback();
+ }
+}
+
+/**
+ * @brief DMA UART receive process error callback
+ * @param Instance Specifies UART peripheral
+ * @return None
+ */
+static void UART_DMAReceiveError(UART_TypeDef *Instance)
+{
+ UART_HandleTypeDef *uart_hdl;
+
+ //UART handle get
+ uart_hdl = UART_Handle_Get(Instance);
+
+ if (uart_hdl == NULL) {
+ LOG_E("Get UART handle error!\n");
+ return;
+ }
+
+ //Disable Rx DMA Request
+ __LL_UART_RxDMA_Dis(Instance);
+
+ //DMA DeInit
+ UART_DMA_DeInit(uart_hdl->rx_ctrl.dma_ch);
+
+ uart_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ uart_hdl->rx_ctrl.state = UART_STATE_READY;
+
+ if (uart_hdl->user_callback.ErrorCallback) {
+ uart_hdl->user_callback.ErrorCallback();
+ }
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+
+#endif /* LL_UART_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_usb.c b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_usb.c
new file mode 100644
index 0000000000..9b385786f0
--- /dev/null
+++ b/bsp/tae32/libraries/TAE32G58xx_Firmware_Library/TAE32G58xx_Driver/Src/tae32g58xx_ll_usb.c
@@ -0,0 +1,1137 @@
+/**
+ ******************************************************************************
+ * @file tae32g58xx_ll_usb.c
+ * @author MCD Application Team
+ * @brief USB LL module driver
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+
+
+#define DBG_TAG "XIF LL"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae_dbg.h"
+
+
+/** @addtogroup TAE32G58xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup XIF_LL XIF LL
+ * @brief XIF LL module driver
+ * @{
+ */
+
+#ifdef LL_XIF_MODULE_ENABLED
+
+/* Private Constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+/* Private Types -------------------------------------------------------------*/
+/** @defgroup XIF_LL_Private_Types XIF LL Private Types
+ * @brief XIF LL Private Types
+ * @{
+ */
+
+/**
+ * @brief XIF IRQ callback function type definition
+ */
+typedef void (*XIF_LLIRQCallback)(XIF_TypeDef *Instance);
+
+/**
+ * @brief XIF Transmission definition
+ */
+typedef struct __XIF_TransTypeDef {
+ uint16_t *buf; /*!< XIF Transmission Buffer Pointer */
+ uint32_t size; /*!< XIF Transmission Buffer Size */
+ uint32_t cnt; /*!< XIF Transmission Counter */
+ XIF_LLIRQCallback isr; /*!< Interrupt Service Routine */
+ XIF_StateETypeDef state; /*!< XIF Transmission State */
+#ifdef LL_DMA_MODULE_ENABLED
+ DMA_ChannelETypeDef dma_ch; /*!< XIF Transmission DMA Channel */
+#endif
+} XIF_TransTypeDef;
+
+/**
+ * @brief XIF handle Structure definition
+ */
+typedef struct __XIF_HandleTypeDef {
+ volatile XIF_TransTypeDef tx_ctrl; /*!< XIF Transmission Tx Control */
+ volatile XIF_TransTypeDef rx_ctrl; /*!< XIF Transmission Rx Control */
+
+ XIF_UserCallbackTypeDef user_callback; /*!< User Callback */
+} XIF_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Private Variables ---------------------------------------------------------*/
+/** @defgroup XIF_LL_Private_Variables XIF LL Private Variables
+ * @brief XIF LL Private Variables
+ * @{
+ */
+
+/**
+ * @brief Default XIF LL Config
+ */
+static const XIF_LLCfgTypeDef xif_ll_cfg_def = {
+ .rx_fifo_full_thres = 1, // 1~8
+ .busy_timeout = 0xffff, // 0~0xffff
+ .dly_chain = XIF_DLY_CHAIN_NONE,
+ .tx_fifo_empty_thres = 1, // 1~8
+};
+
+/**
+ * @brief XIF Handle global variable
+ */
+static XIF_HandleTypeDef xif_hdl_global[XIF_INSTANCE_NUMS];
+
+/**
+ * @}
+ */
+
+
+/* Private Function Prototypes -----------------------------------------------*/
+/** @defgroup XIF_LL_Private_Functions XIF LL Private Functions
+ * @brief XIF LL Private Functions
+ * @{
+ */
+static XIF_HandleTypeDef *XIF_Handle_Get(XIF_TypeDef *Instance);
+
+static void XIF_Tx_ISR(XIF_TypeDef *Instance);
+static void XIF_Rx_ISR(XIF_TypeDef *Instance);
+static void XIF_CloseTx_ISR(XIF_TypeDef *Instance);
+static void XIF_CloseRx_ISR(XIF_TypeDef *Instance);
+void XIF_WaitBusyTimeout_ISR(XIF_TypeDef *Instance);
+
+#ifdef LL_DMA_MODULE_ENABLED
+ static DMA_ChannelETypeDef XIF_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg);
+ static void XIF_DMA_DeInit(DMA_ChannelETypeDef ch);
+ static void XIF_DMAReceiveCplt(XIF_TypeDef *Instance);
+ static void XIF_DMATransmitCplt(XIF_TypeDef *Instance);
+ static void XIF_DMAHalfTransmitCplt(XIF_TypeDef *Instance);
+ static void XIF_DMAHalfReceiveCplt(XIF_TypeDef *Instance);
+ static void XIF_DMATransmitError(XIF_TypeDef *Instance);
+ static void XIF_DMAReceiveError(XIF_TypeDef *Instance);
+#endif
+/**
+ * @}
+ */
+
+
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+/** @defgroup XIF_LL_Exported_Functions XIF LL Exported Functions
+ * @brief XIF LL Exported Functions
+ * @{
+ */
+
+/** @defgroup XIF_LL_Exported_Functions_Group1 XIF Init and DeInit Functions
+ * @brief XIF Init and DeInit Functions
+ * @{
+ */
+
+/**
+ * @brief XIF LL Init
+ * @param Instance Specifies XIF peripheral
+ * @param user_cfg user config pointer
+ * @return Status of the Initialization
+ */
+LL_StatusETypeDef LL_XIF_Init(XIF_TypeDef *Instance, XIF_UserCfgTypeDef *user_cfg)
+{
+ XIF_HandleTypeDef *xif_hdl;
+ XIF_LLCfgTypeDef *ll_cfg;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+ assert_param(user_cfg != NULL);
+
+ if (!IS_XIF_ALL_INSTANCE(Instance) || user_cfg == NULL) {
+ return LL_INVALID;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ } else if ((xif_hdl->tx_ctrl.state != XIF_STATE_RESET) || (xif_hdl->rx_ctrl.state != XIF_STATE_RESET)) {
+ LOG_E("This XIF[0x%08" PRIx32 "] is being used!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ xif_hdl->tx_ctrl.state = XIF_STATE_BUSY;
+ xif_hdl->rx_ctrl.state = XIF_STATE_BUSY;
+
+ //LL config pointer config
+ LL_FUNC_ALTER(user_cfg->ll_cfg == NULL, ll_cfg = (XIF_LLCfgTypeDef *)&xif_ll_cfg_def, ll_cfg = user_cfg->ll_cfg);
+
+ /* Init the low level hardware eg. Clock, NVIC */
+ LL_XIF_MspInit(Instance);
+
+ //Module disable and software reset
+ __LL_XIF_Dis(Instance);
+ __LL_XIF_Sw_Rst(Instance);
+
+ //LL Config
+ __LL_XIF_DlyChain_Set(Instance, ll_cfg->dly_chain);
+ __LL_XIF_RxFIFOFullThres_Set(Instance, ll_cfg->rx_fifo_full_thres);
+ __LL_XIF_BUSY_Timeout_Set(Instance, ll_cfg->busy_timeout);
+
+ if ((__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) && (LL_IsExtCfgEnGrp(LL_EXT_CFG_GRP_MASK_XIF))) {
+ __LL_XIF_TxFIFOEmptyThres_Set(Instance, ll_cfg->tx_fifo_empty_thres);
+ }
+
+ //User Config
+ __LL_XIF_RD_HighTimeLen_Set(Instance, user_cfg->rd_high_len);
+ __LL_XIF_RD_LowTimeLen_Set(Instance, user_cfg->rd_low_len);
+ __LL_XIF_CONVST_LowTimeLen_Set(Instance, user_cfg->convst_low_len);
+ __LL_XIF_RESET_HighTimeLen_Set(Instance, user_cfg->reset_high_len);
+ __LL_XIF_RxDatCnt_Set(Instance, user_cfg->ch_per_frame);
+ LL_FUNC_ALTER(user_cfg->reload_mode_en, __LL_XIF_ReloadMode_En(Instance), __LL_XIF_ReloadMode_Dis(Instance));
+
+ //All Interrupt Pending Clear
+ __LL_XIF_AllIntPnd_Clr(Instance);
+
+ //XIF Handle Init
+ xif_hdl->tx_ctrl.state = XIF_STATE_READY;
+ xif_hdl->rx_ctrl.state = XIF_STATE_READY;
+ xif_hdl->user_callback = user_cfg->user_callback;
+
+#ifdef LL_DMA_MODULE_ENABLED
+ xif_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ xif_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+#endif
+
+ return LL_OK;
+}
+
+/**
+ * @brief XIF LL DeInit
+ * @param Instance Specifies XIF peripheral
+ * @return Status of the DeInitialization
+ */
+LL_StatusETypeDef LL_XIF_DeInit(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+
+ if (!IS_XIF_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ } else if ((xif_hdl->tx_ctrl.state == XIF_STATE_BUSY_WRITE) || (xif_hdl->rx_ctrl.state == XIF_STATE_BUSY_READ)) {
+ LOG_E("This XIF[0x%08" PRIx32 "] is being used!\n", (uint32_t)Instance);
+ return LL_BUSY;
+ }
+
+ xif_hdl->tx_ctrl.state = XIF_STATE_BUSY;
+ xif_hdl->rx_ctrl.state = XIF_STATE_BUSY;
+
+ //XIF Module Disable
+ __LL_XIF_Dis(Instance);
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_XIF_MspDeInit(Instance);
+
+ memset((void *)xif_hdl, 0, sizeof(XIF_HandleTypeDef));
+ xif_hdl->tx_ctrl.state = XIF_STATE_RESET;
+ xif_hdl->rx_ctrl.state = XIF_STATE_RESET;
+
+#ifdef LL_DMA_MODULE_ENABLED
+ xif_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ xif_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+#endif
+
+ return LL_OK;
+}
+
+/**
+ * @brief XIF LL Reset
+ * @param Instance Specifies XIF peripheral
+ * @return Status of the Reset
+ */
+LL_StatusETypeDef LL_XIF_Reset(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+ IRQn_Type irq_num;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+
+ if (!IS_XIF_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ }
+
+ irq_num = GET_XIF_IRQ_NUMBER(Instance);
+ if (irq_num < 0) {
+ LOG_E("XIF IRQ does not exist!\n");
+ return LL_ERROR;
+ }
+
+ //Clear pending and interrupt disable
+ __disable_irq();
+ CLEAR_BIT(Instance->ENABLE, 0x13UL);
+ CLEAR_BIT(Instance->CTRL, 0x700F000UL);
+ SET_BIT(Instance->ISR, 0x6000EUL);
+ SET_BIT(Instance->ENABLE, 0x4UL);
+ NVIC_ClearPendingIRQ(irq_num);
+ NVIC_DisableIRQ(irq_num);
+ __enable_irq();
+
+ xif_hdl->tx_ctrl.state = XIF_STATE_BUSY;
+ xif_hdl->rx_ctrl.state = XIF_STATE_BUSY;
+
+ /* DeInit the low level hardware eg. Clock, NVIC */
+ LL_XIF_MspDeInit(Instance);
+
+ memset((void *)xif_hdl, 0, sizeof(XIF_HandleTypeDef));
+ xif_hdl->tx_ctrl.state = XIF_STATE_RESET;
+ xif_hdl->rx_ctrl.state = XIF_STATE_RESET;
+
+#ifdef LL_DMA_MODULE_ENABLED
+ xif_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+ xif_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+#endif
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initializes the XIF MSP
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+__WEAK void LL_XIF_MspInit(XIF_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_XIF_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the XIF MSP
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+__WEAK void LL_XIF_MspDeInit(XIF_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_XIF_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Register an User XIF Callback
+ * @note User can register callback only in XIF Ready State
+ * @param Instance Specifies XIF peripheral
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_XIF_RegisterCallback(XIF_TypeDef *Instance, XIF_UserCallbackIdETypeDef CallbackID, XIF_UserCallback pCallback)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+
+ if (!IS_XIF_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ }
+
+ //Check callback pointer valid or not
+ if (pCallback == NULL) {
+ LOG_E("The callback pointer which to be registered is NULL!\n");
+ return LL_INVALID;
+ }
+
+ //Register user callback
+ switch (CallbackID) {
+ case XIF_TX_CPLT_CB_ID:
+ if (xif_hdl->tx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Tx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ xif_hdl->user_callback.TxCpltCallback = pCallback;
+ break;
+
+ case XIF_RX_CPLT_CB_ID:
+ if (xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ xif_hdl->user_callback.RxCpltCallback = pCallback;
+ break;
+
+ case XIF_TX_HALF_CPLT_CB_ID:
+ if (xif_hdl->tx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Tx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ xif_hdl->user_callback.TxHalfCpltCallback = pCallback;
+ break;
+
+ case XIF_RX_HALF_CPLT_CB_ID:
+ if (xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Rx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ xif_hdl->user_callback.RxHalfCpltCallback = pCallback;
+ break;
+
+ case XIF_ERROR_CB_ID:
+ if (xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] Rx isn't in Ready state, can't register Error callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ xif_hdl->user_callback.ErrorCallback = pCallback;
+ break;
+
+ default:
+ LOG_E("XIF user callback ID-[%d] is Invalid!\n", CallbackID);
+ return LL_INVALID;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief UnRegister an User XIF Callback
+ * @note User can unregister callback only in XIF Ready State
+ * @param Instance Specifies XIF peripheral
+ * @param CallbackID ID of the callback to be unregistered
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_XIF_UnRegisterCallback(XIF_TypeDef *Instance, XIF_UserCallbackIdETypeDef CallbackID)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+
+ if (!IS_XIF_ALL_INSTANCE(Instance)) {
+ return LL_INVALID;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ }
+
+ //UnRegister user callback
+ switch (CallbackID) {
+ case XIF_TX_CPLT_CB_ID:
+ if (xif_hdl->tx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Tx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ xif_hdl->user_callback.TxCpltCallback = NULL;
+ break;
+
+ case XIF_RX_CPLT_CB_ID:
+ if (xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Rx Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ xif_hdl->user_callback.RxCpltCallback = NULL;
+ break;
+
+ case XIF_TX_HALF_CPLT_CB_ID:
+ if (xif_hdl->tx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Tx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ xif_hdl->user_callback.TxHalfCpltCallback = NULL;
+ break;
+
+ case XIF_RX_HALF_CPLT_CB_ID:
+ if (xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Rx Half Complete callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ xif_hdl->user_callback.RxHalfCpltCallback = NULL;
+ break;
+
+ case XIF_ERROR_CB_ID:
+ if (xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] Rx isn't in Ready state, can't unregister Error callback!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ xif_hdl->user_callback.ErrorCallback = NULL;
+ break;
+
+ default:
+ LOG_E("XIF user callback ID-[%d] is Invalid!\n", CallbackID);
+ return LL_INVALID;
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup XIF_LL_Exported_Functions_Group2 XIF Operation Functions
+ * @brief XIF Operation Functions
+ * @{
+ */
+
+/**
+ * @brief XIF Transmit an amount of data in CPU blocking mode
+ * @param Instance Specifies XIF peripheral
+ * @param buf Transmit buffer pointer
+ * @param size amount of data to be transmitted in uint16_t unit
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_XIF_Transmit_CPU(XIF_TypeDef *Instance, uint16_t *buf, uint32_t size, uint32_t timeout)
+{
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ XIF_HandleTypeDef *xif_hdl;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_XIF_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //Check whether this function is supported
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ LOG_E("The chip not support XIF Blocking Transmit!\n");
+ return LL_FAILED;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ } else if (xif_hdl->tx_ctrl.state != XIF_STATE_READY || xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] isn't in READY state, can't start operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ xif_hdl->tx_ctrl.state = XIF_STATE_BUSY_WRITE;
+ xif_hdl->tx_ctrl.cnt = 0;
+ xif_hdl->tx_ctrl.isr = NULL;
+ xif_hdl->tx_ctrl.buf = buf;
+ xif_hdl->tx_ctrl.size = size;
+
+ __LL_XIF_TsfDir_Set(Instance, XIF_TSF_DIR_TX);
+
+ //Clear TxFIFO and TX Done Pending
+ __LL_XIF_TxDoneIntPnd_Clr(Instance);
+ __LL_XIF_WaitBUSYTimeoutIntPnd_Clr(Instance);
+ __LL_XIF_En(Instance);
+ tickstart = LL_GetTick();
+
+ //Transmit data loop
+ while (xif_hdl->tx_ctrl.cnt < xif_hdl->tx_ctrl.size) {
+ //if CPU has been broken a long time by Interrupt, the TxDone flag maybe set
+ if (__LL_XIF_IsTxDoneIntPnd(Instance)) {
+ __LL_XIF_TxDoneIntPnd_Clr(Instance);
+ }
+
+ //Wait TxFIFO to be not full
+ while (__LL_XIF_IsTxFIFOFull(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+
+ //Check Error State (Wait BUSY Timeout)
+ if (xif_hdl->tx_ctrl.state == XIF_STATE_ERROR || __LL_XIF_IsWaitBUSYTimeoutIntPnd(Instance)) {
+ __LL_XIF_WaitBUSYTimeoutIntPnd_Clr(Instance);
+ LOG_E("Wait BUSY signal timeout!\n");
+ ret = LL_ERROR;
+ goto exit;
+ }
+ }
+
+ //Write data to TxFIFO
+ __LL_XIF_TxFIFODat_Write(Instance, *xif_hdl->tx_ctrl.buf++);
+
+ xif_hdl->tx_ctrl.cnt++;
+ }
+
+ //Wait for XIF Transmit completed
+ if (!__LL_XIF_IsReloadModeEn(Instance)) {
+ while (!__LL_XIF_IsTxDoneIntPnd(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+ }
+ }
+
+ //Clear TX Done Pending
+ if (__LL_XIF_IsTxDoneIntPnd(Instance)) {
+ __LL_XIF_TxDoneIntPnd_Clr(Instance);
+ }
+
+ ret = LL_OK;
+
+exit:
+ //Disable XIF to stop transmit
+ __LL_XIF_Dis(Instance);
+
+ xif_hdl->tx_ctrl.state = XIF_STATE_READY;
+ return ret;
+}
+
+/**
+ * @brief XIF Receive an amount of data in CPU blocking mode
+ * @param Instance Specifies XIF peripheral
+ * @param buf Receive buffer pointer
+ * @param size amount of data to be received in uint16_t unit
+ * @param timeout timeout duration
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_XIF_Receive_CPU(XIF_TypeDef *Instance, uint16_t *buf, uint32_t size, uint32_t timeout)
+{
+ uint32_t tickstart;
+ LL_StatusETypeDef ret;
+ XIF_HandleTypeDef *xif_hdl;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_XIF_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ } else if (xif_hdl->tx_ctrl.state != XIF_STATE_READY || xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] isn't in READY state, can't start operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ xif_hdl->rx_ctrl.state = XIF_STATE_BUSY_READ;
+ xif_hdl->rx_ctrl.buf = buf;
+ xif_hdl->rx_ctrl.size = size;
+ xif_hdl->rx_ctrl.cnt = 0;
+ xif_hdl->rx_ctrl.isr = NULL;
+
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) {
+ __LL_XIF_TsfDir_Set(Instance, XIF_TSF_DIR_RX);
+ }
+
+ //Enable XIF to start transmit
+ __LL_XIF_RxDoneIntPnd_Clr(Instance);
+ __LL_XIF_WaitBUSYTimeoutIntPnd_Clr(Instance);
+ __LL_XIF_En(Instance);
+ tickstart = LL_GetTick();
+
+ //Receive loop
+ while (xif_hdl->rx_ctrl.cnt < xif_hdl->rx_ctrl.size) {
+ //Wait RxFIFO to be not empty
+ while (__LL_XIF_IsRxFIFOEmpty(Instance)) {
+ if (timeout != LL_WAIT_FOREVER && (LL_GetTick() - tickstart) > timeout) {
+ LOG_E("<%s> timeout!\n", __FUNCTION__);
+ ret = LL_TIMEOUT;
+ goto exit;
+ }
+
+ //Check Error State (Wait BUSY Timeout)
+ if (xif_hdl->rx_ctrl.state == XIF_STATE_ERROR || __LL_XIF_IsWaitBUSYTimeoutIntPnd(Instance)) {
+ __LL_XIF_WaitBUSYTimeoutIntPnd_Clr(Instance);
+ LOG_E("Wait BUSY signal timeout!\n");
+ ret = LL_ERROR;
+ goto exit;
+ }
+ }
+
+ *xif_hdl->rx_ctrl.buf++ = __LL_XIF_Dat_Read(Instance);
+ xif_hdl->rx_ctrl.cnt++;
+ }
+
+ //Clear RX Done Pending
+ if (__LL_XIF_IsRxDoneIntPnd(Instance)) {
+ __LL_XIF_RxDoneIntPnd_Clr(Instance);
+ }
+
+ ret = LL_OK;
+
+exit:
+ //Disable XIF to stop transmit
+ __LL_XIF_Dis(Instance);
+
+ xif_hdl->rx_ctrl.state = XIF_STATE_READY;
+ return ret;
+}
+
+/**
+ * @brief XIF Transmit an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies XIF peripheral
+ * @param buf Transmit buffer pointer
+ * @param size amount of data to be transmitted in uint16_t unit
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_XIF_Transmit_IT(XIF_TypeDef *Instance, uint16_t *buf, uint32_t size)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_XIF_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ } else if (xif_hdl->tx_ctrl.state != XIF_STATE_READY || xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] isn't in READY state, can't start operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check whether this function is supported
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ LOG_E("The chip not support XIF Interrupt Transmit!\n");
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ xif_hdl->tx_ctrl.state = XIF_STATE_BUSY_WRITE;
+ xif_hdl->tx_ctrl.buf = buf;
+ xif_hdl->tx_ctrl.size = size;
+ xif_hdl->tx_ctrl.cnt = 0;
+ xif_hdl->tx_ctrl.isr = XIF_Tx_ISR;
+
+ __LL_XIF_TsfDir_Set(Instance, XIF_TSF_DIR_TX);
+
+ //Clear TxFIFO and TX Done Pending
+ __LL_XIF_TxDoneIntPnd_Clr(Instance);
+ __LL_XIF_WaitBUSYTimeoutIntPnd_Clr(Instance);
+ __LL_XIF_En(Instance);
+
+ //Enable TxFIFO Empty interrupt
+ __LL_XIF_TxFIFOEmpty_INT_En(Instance);
+
+ //Enable Wait BUSY Timeout interrupt
+ __LL_XIF_WaitBusyTimeout_INT_En(Instance);
+
+ return LL_OK;
+}
+
+/**
+ * @brief XIF Receive an amount of data in non-blocking mode with Interrupt
+ * @param Instance Specifies XIF peripheral
+ * @param buf Receive buffer pointer
+ * @param size amount of data to be received in uint16_t unit
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_XIF_Receive_IT(XIF_TypeDef *Instance, uint16_t *buf, uint32_t size)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_XIF_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ } else if (xif_hdl->tx_ctrl.state != XIF_STATE_READY || xif_hdl->rx_ctrl.state != XIF_STATE_READY){
+ LOG_E("This XIF[0x%08" PRIx32 "] isn't in READY state, can't start operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Transmit config
+ xif_hdl->rx_ctrl.state = XIF_STATE_BUSY_READ;
+ xif_hdl->rx_ctrl.buf = buf;
+ xif_hdl->rx_ctrl.size = size;
+ xif_hdl->rx_ctrl.cnt = 0;
+ xif_hdl->rx_ctrl.isr = XIF_Rx_ISR;
+
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) {
+ __LL_XIF_TsfDir_Set(Instance, XIF_TSF_DIR_RX);
+ }
+
+ //Enable XIF to start transmit
+ __LL_XIF_RxDoneIntPnd_Clr(Instance);
+ __LL_XIF_WaitBUSYTimeoutIntPnd_Clr(Instance);
+ __LL_XIF_En(Instance);
+
+ //Enable RxFIFO Full interrupt
+ __LL_XIF_RxFIFOFull_INT_En(Instance);
+
+ //Enable Wait BUSY Timeout interrupt
+ __LL_XIF_WaitBusyTimeout_INT_En(Instance);
+
+ return LL_OK;
+}
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief XIF Transmit an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies XIF peripheral
+ * @param buf Transmit buffer pointer
+ * @param size amount of data to be transmitted in uint16_t unit
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_XIF_Transmit_DMA(XIF_TypeDef *Instance, uint16_t *buf, uint32_t size)
+{
+ XIF_HandleTypeDef *xif_hdl;
+ DMA_UserCfgTypeDef dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_XIF_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ } else if (xif_hdl->tx_ctrl.state != XIF_STATE_READY || xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] isn't in READY state, can't start operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //Check whether this function is supported
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ LOG_E("The chip not support XIF DMA Transmit!\n");
+ return LL_FAILED;
+ }
+
+ //DMA Init
+ memset((void *)&dma_user_cfg, 0x0, sizeof(dma_user_cfg));
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_16b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_16b;
+
+ dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_FIX;
+ dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == XIF) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_XIF_TX;
+ } else {
+ LOG_E("XIF DMA source handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Transmit Default Config
+ dma_user_cfg.trans_type = DMA_TRANS_TYPE_P2M;
+ dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_INC;
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ dma_user_cfg.end_callback = (DMA_IRQCallback)XIF_DMATransmitCplt;
+ dma_user_cfg.end_arg = Instance;
+ dma_user_cfg.err_callback = (DMA_IRQCallback)XIF_DMATransmitError;
+ dma_user_cfg.err_arg = Instance;
+ dma_user_cfg.half_callback = (DMA_IRQCallback)XIF_DMAHalfTransmitCplt;
+ dma_user_cfg.half_arg = Instance;
+
+ xif_hdl->tx_ctrl.dma_ch = XIF_DMA_Init(&dma_user_cfg);
+
+ if (xif_hdl->tx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("XIF receive request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Transmit config
+ xif_hdl->tx_ctrl.state = XIF_STATE_BUSY_WRITE;
+ xif_hdl->tx_ctrl.buf = buf;
+ xif_hdl->tx_ctrl.size = size;
+ xif_hdl->tx_ctrl.cnt = 0;
+ xif_hdl->tx_ctrl.isr = NULL;
+
+ __LL_XIF_TsfDir_Set(Instance, XIF_TSF_DIR_TX);
+
+ //Enable Tx DMA Requset
+ __LL_XIF_TxDMA_En(Instance);
+
+ //Enable XIF to start transmit
+ __LL_XIF_TxDoneIntPnd_Clr(Instance);
+ __LL_XIF_WaitBUSYTimeoutIntPnd_Clr(Instance);
+ __LL_XIF_En(Instance);
+
+ //Enable Wait BUSY Timeout interrupt
+ __LL_XIF_WaitBusyTimeout_INT_En(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, xif_hdl->tx_ctrl.dma_ch, (uint32_t)&Instance->DATA, (uint32_t)buf, xif_hdl->tx_ctrl.size * 2);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA
+ * @param Instance Specifies XIF peripheral
+ * @param buf Receive buffer pointer
+ * @param size amount of data to be received in uint16_t unit
+ * @return LL Status
+ */
+LL_StatusETypeDef LL_XIF_Receive_DMA(XIF_TypeDef *Instance, uint16_t *buf, uint32_t size)
+{
+ XIF_HandleTypeDef *xif_hdl;
+ DMA_UserCfgTypeDef dma_user_cfg;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+ assert_param(buf != NULL);
+ assert_param(size);
+
+ if (!IS_XIF_ALL_INSTANCE(Instance) || buf == NULL || !size) {
+ return LL_INVALID;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return LL_ERROR;
+ } else if (xif_hdl->tx_ctrl.state != XIF_STATE_READY || xif_hdl->rx_ctrl.state != XIF_STATE_READY) {
+ LOG_E("This XIF[0x%08" PRIx32 "] isn't in READY state, can't start operation!\n", (uint32_t)Instance);
+ return LL_FAILED;
+ }
+
+ //DMA Init
+ memset((void *)&dma_user_cfg, 0x0, sizeof(dma_user_cfg));
+ dma_user_cfg.src_data_width = DMA_TRANS_WIDTH_16b;
+ dma_user_cfg.dst_data_width = DMA_TRANS_WIDTH_16b;
+
+ dma_user_cfg.src_addr_mode = DMA_ADDR_MODE_FIX;
+ dma_user_cfg.trans_mode = DMA_TRANS_MODE_SINGLE;
+
+ if (Instance == XIF) {
+ dma_user_cfg.src_hs_ifc = DMA_HANDSHAKE_IFC_XIF_RX;
+ } else {
+ LOG_E("XIF DMA source handshake interface auto config error!\n");
+ return LL_ERROR;
+ }
+
+ //DMA Receive Default Config
+ dma_user_cfg.trans_type = DMA_TRANS_TYPE_P2M;
+ dma_user_cfg.dst_addr_mode = DMA_ADDR_MODE_INC;
+ dma_user_cfg.dst_hs_ifc = DMA_HANDSHAKE_IFC_MEMORY;
+
+ dma_user_cfg.end_callback = (DMA_IRQCallback)XIF_DMAReceiveCplt;
+ dma_user_cfg.end_arg = Instance;
+ dma_user_cfg.err_callback = (DMA_IRQCallback)XIF_DMAReceiveError;
+ dma_user_cfg.err_arg = Instance;
+ dma_user_cfg.half_callback = (DMA_IRQCallback)XIF_DMAHalfReceiveCplt;
+ dma_user_cfg.half_arg = Instance;
+
+ xif_hdl->rx_ctrl.dma_ch = XIF_DMA_Init(&dma_user_cfg);
+
+ if (xif_hdl->rx_ctrl.dma_ch == DMA_CHANNEL_INVALID) {
+ LOG_E("XIF receive request DMA channel Failed!\n");
+ return LL_ERROR;
+ }
+
+ //Transmit config
+ xif_hdl->rx_ctrl.state = XIF_STATE_BUSY_READ;
+ xif_hdl->rx_ctrl.buf = buf;
+ xif_hdl->rx_ctrl.size = size;
+ xif_hdl->rx_ctrl.cnt = 0;
+ xif_hdl->rx_ctrl.isr = NULL;
+
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) {
+ __LL_XIF_TsfDir_Set(Instance, XIF_TSF_DIR_RX);
+ }
+
+ //Enable Rx DMA Requset
+ __LL_XIF_RxDMA_En(Instance);
+
+ //Enable XIF to start transmit
+ __LL_XIF_RxDoneIntPnd_Clr(Instance);
+ __LL_XIF_WaitBUSYTimeoutIntPnd_Clr(Instance);
+ __LL_XIF_En(Instance);
+
+ //Enable Wait BUSY Timeout interrupt
+ __LL_XIF_WaitBusyTimeout_INT_En(Instance);
+
+ //Start DMA Transmission in Interrupt mode
+ LL_DMA_Start_IT(DMA, xif_hdl->rx_ctrl.dma_ch, (uint32_t)&Instance->DATA, (uint32_t)buf, xif_hdl->rx_ctrl.size * 2);
+
+ return LL_OK;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+
+/** @defgroup XIF_LL_Exported_Functions_Interrupt XIF Interrupt Handler and Callback
+ * @brief XIF Interrupt Handler and Callback
+ * @{
+ */
+
+/**
+ * @brief XIF IRQ Handler
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+void LL_XIF_IRQHandler(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+ uint32_t int_en, int_pending;
+
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+
+ if (!IS_XIF_ALL_INSTANCE(Instance)) {
+ return;
+ }
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //All Interrupt Enalbe and Pending Get
+ int_en = __LL_XIF_AllIntEn_Get(Instance);
+ int_pending = __LL_XIF_AllIntPnd_Get(Instance);
+
+
+ //RxFIFO Full Interrupt Handler
+ if ((int_en & XIF_CTRL_RXFIE_Msk) && (int_pending & XIF_ISR_RXFI_Msk)) {
+ //Interrupt Pending auto clear
+
+ if (xif_hdl->rx_ctrl.isr) {
+ xif_hdl->rx_ctrl.isr(Instance);
+ }
+
+ //Callback
+ LL_XIF_RxFullCallback(Instance);
+ }
+
+ //RxFIFO Overflow Interrupt Handler
+ if ((int_en & XIF_CTRL_RXOFIE_Msk) && (int_pending & XIF_ISR_RXOFI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_XIF_RxFIFOOverflowIntPnd_Clr(Instance);
+
+ //Callback
+ LL_XIF_RxOverflowCallback(Instance);
+ }
+
+ //Rx Done Interrupt Handler
+ if ((int_en & XIF_CTRL_RXDIE_Msk) && (int_pending & XIF_ISR_RXDI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_XIF_RxDoneIntPnd_Clr(Instance);
+
+ //Callback
+ LL_XIF_RxDoneCallback(Instance);
+ }
+
+ //Wait BUSY Timeout Interrupt Handler
+ if ((int_en & XIF_CTRL_BTOIE_Msk) && (int_pending & XIF_ISR_BTOI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_XIF_WaitBUSYTimeoutIntPnd_Clr(Instance);
+
+ XIF_WaitBusyTimeout_ISR(Instance);
+
+ //Callback
+ LL_XIF_WaitBusyTimeoutCallback(Instance);
+ }
+
+ //The following features are available for later versions
+ if (__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) < 3) {
+ return;
+ }
+
+ //TxFIFO Empty Interrupt Handler
+ if ((int_en & XIF_CTRL_TXEIE_Msk) && (int_pending & XIF_ISR_TXEI_Msk)) {
+ //Interrupt Pending auto clear
+
+ if (xif_hdl->tx_ctrl.isr) {
+ xif_hdl->tx_ctrl.isr(Instance);
+ }
+
+ //Callback
+ LL_XIF_TxEmptyCallback(Instance);
+ }
+
+ //Tx Done Interrupt Handler
+ if ((int_en & XIF_CTRL_TXDIE_Msk) && (int_pending & XIF_ISR_TXDI_Msk)) {
+ //Clear Interrupt Pending
+ __LL_XIF_TxDoneIntPnd_Clr(Instance);
+
+ //Callback
+ LL_XIF_TxDoneCallback(Instance);
+ }
+
+}
+
+/**
+ * @brief XIF TxFIFO Empty Interrupt Callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+__WEAK void LL_XIF_TxEmptyCallback(XIF_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_XIF_TxEmptyCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief XIF Tx Done Interrupt Callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+__WEAK void LL_XIF_TxDoneCallback(XIF_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_XIF_TxDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief XIF RxFIFO Full Interrupt Callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+__WEAK void LL_XIF_RxFullCallback(XIF_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_XIF_RxFullCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief XIF RxFIFO Overflow Interrupt Callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+__WEAK void LL_XIF_RxOverflowCallback(XIF_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_XIF_RxOverflowCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief XIF Rx Done Interrupt Callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+__WEAK void LL_XIF_RxDoneCallback(XIF_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_XIF_RxDoneCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief XIF Wait BUSY Timeout Interrupt Callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+__WEAK void LL_XIF_WaitBusyTimeoutCallback(XIF_TypeDef *Instance)
+{
+ /* Prevent unused argument(s) compilation warning */
+ LL_UNUSED(Instance);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the LL_XIF_WaitBusyTimeoutCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private Functions ---------------------------------------------------------*/
+/** @addtogroup XIF_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief XIF Handle Get
+ * @param Instance Specifies XIF peripheral
+ * @return XIF_HandleTypeDef pointer
+ */
+static XIF_HandleTypeDef *XIF_Handle_Get(XIF_TypeDef *Instance)
+{
+ //Assert param
+ assert_param(IS_XIF_ALL_INSTANCE(Instance));
+
+ if (Instance == XIF) {
+ return &xif_hdl_global[XIF_INSTANCE_0];
+ }
+
+ return NULL;
+}
+
+/**
+ * @brief Handle the end of the TX transaction
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+static void XIF_CloseTx_ISR(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //Disable Wait BUSY Timeout interrupt
+ __LL_XIF_WaitBusyTimeout_INT_Dis(Instance);
+
+ //Disable TxFIFO Full interrupt
+ __LL_XIF_TxFIFOEmpty_INT_Dis(Instance);
+ xif_hdl->tx_ctrl.isr = NULL;
+
+ //Clear TX Done Pending
+ if (__LL_XIF_IsTxDoneIntPnd(Instance)) {
+ __LL_XIF_TxDoneIntPnd_Clr(Instance);
+ }
+
+ //Disable XIF to stop transmit
+ __LL_XIF_Dis(Instance);
+
+ xif_hdl->tx_ctrl.state = XIF_STATE_READY;
+}
+
+/**
+ * @brief Handle the end of the RX transaction
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+static void XIF_CloseRx_ISR(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //Disable Wait BUSY Timeout interrupt
+ __LL_XIF_WaitBusyTimeout_INT_Dis(Instance);
+
+ //Disable RxFIFO Full interrupt
+ __LL_XIF_RxFIFOFull_INT_Dis(Instance);
+ xif_hdl->rx_ctrl.isr = NULL;
+
+ //Clear RX Done Pending
+ if (__LL_XIF_IsRxDoneIntPnd(Instance)) {
+ __LL_XIF_RxDoneIntPnd_Clr(Instance);
+ }
+
+ //Disable XIF to stop transmit
+ __LL_XIF_Dis(Instance);
+
+ xif_hdl->rx_ctrl.state = XIF_STATE_READY;
+}
+
+/**
+ * @brief Handle the data transmit in Interrupt mode
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+static void XIF_Tx_ISR(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //Write data to TxFIFO
+ if ((!__LL_XIF_IsTxFIFOFull(Instance)) && (xif_hdl->tx_ctrl.cnt < xif_hdl->tx_ctrl.size)) {
+ //if TxDone flag has been set before write data to TxFIFO, clear it
+ if (__LL_XIF_IsTxDoneIntPnd(Instance)) {
+ __LL_XIF_TxDoneIntPnd_Clr(Instance);
+ }
+
+ __LL_XIF_TxFIFODat_Write(Instance, *xif_hdl->tx_ctrl.buf);
+ xif_hdl->tx_ctrl.buf++;
+ xif_hdl->tx_ctrl.cnt++;
+ }
+
+ //Write Complete
+ if (xif_hdl->tx_ctrl.cnt >= xif_hdl->tx_ctrl.size) {
+ //Close Tx Communication
+ XIF_CloseTx_ISR(Instance);
+
+ //Tx Complete Callback
+ if (xif_hdl->user_callback.TxCpltCallback) {
+ xif_hdl->user_callback.TxCpltCallback();
+ }
+ }
+}
+
+/**
+ * @brief Handle the data receive in Interrupt mode
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+static void XIF_Rx_ISR(XIF_TypeDef *Instance)
+{
+ //uint8_t rx_fifo_trig_lvl;
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //rx_fifo_trig_lvl = __LL_XIF_RxFIFOFullThres_Get(Instance);
+
+ //Read data from RxFIFO
+ while (!__LL_XIF_IsRxFIFOEmpty(Instance) && xif_hdl->rx_ctrl.cnt < xif_hdl->rx_ctrl.size) { //rx_fifo_trig_lvl--
+ *xif_hdl->rx_ctrl.buf++ = __LL_XIF_Dat_Read(Instance);
+ xif_hdl->rx_ctrl.cnt++;
+ }
+
+ //Rx Complete
+ if (xif_hdl->rx_ctrl.cnt >= xif_hdl->rx_ctrl.size) {
+ //Close Rx Communication
+ XIF_CloseRx_ISR(Instance);
+
+ //Rx Complete Callback
+ if (xif_hdl->user_callback.RxCpltCallback) {
+ xif_hdl->user_callback.RxCpltCallback();
+ }
+ }
+}
+
+/**
+ * @brief XIF Wait BUSY Timeout Interrupt Callback
+ * @note User must invoking LL_XIF_DeInit before reinitializing XIF when BUSY Timeout occured
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+void XIF_WaitBusyTimeout_ISR(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //Set Error State
+ xif_hdl->tx_ctrl.state = XIF_STATE_ERROR;
+ xif_hdl->rx_ctrl.state = XIF_STATE_ERROR;
+
+ if (xif_hdl->tx_ctrl.isr != NULL) { //Interrupt Transmit on going
+ //Abort Tx Communication
+ XIF_CloseTx_ISR(Instance);
+
+ if (xif_hdl->user_callback.ErrorCallback) {
+ xif_hdl->user_callback.ErrorCallback();
+ }
+ }
+
+ if (xif_hdl->rx_ctrl.isr != NULL) { //Interrupt Transmit on going
+ //Abort Rx Communication
+ XIF_CloseRx_ISR(Instance);
+
+ if (xif_hdl->user_callback.ErrorCallback) {
+ xif_hdl->user_callback.ErrorCallback();
+ }
+ }
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+ if (xif_hdl->tx_ctrl.dma_ch != DMA_CHANNEL_INVALID) { //DMA Transmit on going
+ XIF_DMATransmitError(Instance);
+ }
+
+ if (xif_hdl->rx_ctrl.dma_ch != DMA_CHANNEL_INVALID) { //DMA Transmit on going
+ XIF_DMAReceiveError(Instance);
+ }
+
+#endif
+}
+
+#ifdef LL_DMA_MODULE_ENABLED
+
+/**
+ * @brief XIF DMA Init
+ * @param dma_user_cfg user dma config pointer
+ * @return DMA_ChannelETypeDef
+ */
+static DMA_ChannelETypeDef XIF_DMA_Init(DMA_UserCfgTypeDef *dma_user_cfg)
+{
+ LL_StatusETypeDef ret;
+ DMA_ChannelETypeDef ch;
+
+ if (dma_user_cfg == NULL) {
+ return DMA_CHANNEL_INVALID;
+ }
+
+ //User DMA channel request
+ ch = LL_DMA_ChannelRequest();
+
+ if (ch == DMA_CHANNEL_INVALID) {
+ LOG_E("Requset DMA channel Fail!\n");
+ return DMA_CHANNEL_INVALID;
+ }
+
+ //User DMA init
+ ret = LL_DMA_Init(DMA, ch, dma_user_cfg);
+
+ if (ret != LL_OK) {
+ LOG_E("DMA LL init fail!\n");
+ LL_DMA_ChannelRelease(ch);
+ return DMA_CHANNEL_INVALID;
+ }
+
+ return ch;
+}
+
+/**
+ * @brief XIF DMA DeInit
+ * @param ch DMA channel to Deinit
+ * @return None
+ */
+static void XIF_DMA_DeInit(DMA_ChannelETypeDef ch)
+{
+ if (ch == DMA_CHANNEL_INVALID) {
+ return;
+ }
+
+ LL_DMA_Stop_IT(DMA, ch);
+ LL_DMA_DeInit(DMA, ch);
+ LL_DMA_ChannelRelease(ch);
+}
+
+/**
+ * @brief DMA XIF transmit process complete callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+static void XIF_DMATransmitCplt(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //Disable Wait BUSY Timeout interrupt
+ __LL_XIF_WaitBusyTimeout_INT_Dis(Instance);
+
+ //Disable Tx DMA Request
+ __LL_XIF_TxDMA_Dis(Instance);
+
+ //DMA DeInit
+ XIF_DMA_DeInit(xif_hdl->tx_ctrl.dma_ch);
+ xif_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+
+ //Clear RX Done Pending
+ if (__LL_XIF_IsTxDoneIntPnd(Instance)) {
+ __LL_XIF_TxDoneIntPnd_Clr(Instance);
+ }
+
+ //Disable XIF to stop transmit
+ __LL_XIF_Dis(Instance);
+
+ xif_hdl->tx_ctrl.cnt = xif_hdl->tx_ctrl.size;
+ xif_hdl->tx_ctrl.state = XIF_STATE_READY;
+
+ //Rx Complete Callback
+ if (xif_hdl->user_callback.TxCpltCallback) {
+ xif_hdl->user_callback.TxCpltCallback();
+ }
+}
+
+/**
+ * @brief DMA XIF receive process complete callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+static void XIF_DMAReceiveCplt(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //Disable Wait BUSY Timeout interrupt
+ __LL_XIF_WaitBusyTimeout_INT_Dis(Instance);
+
+ //Disable Rx DMA Request
+ __LL_XIF_RxDMA_Dis(Instance);
+
+ //DMA DeInit
+ XIF_DMA_DeInit(xif_hdl->rx_ctrl.dma_ch);
+ xif_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+
+ //Clear RX Done Pending
+ if (__LL_XIF_IsRxDoneIntPnd(Instance)) {
+ __LL_XIF_RxDoneIntPnd_Clr(Instance);
+ }
+
+ //Disable XIF to stop transmit
+ __LL_XIF_Dis(Instance);
+
+ xif_hdl->rx_ctrl.cnt = xif_hdl->rx_ctrl.size;
+ xif_hdl->rx_ctrl.state = XIF_STATE_READY;
+
+ //Rx Complete Callback
+ if (xif_hdl->user_callback.RxCpltCallback) {
+ xif_hdl->user_callback.RxCpltCallback();
+ }
+}
+
+/**
+ * @brief DMA XIF half transmit process complete callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+static void XIF_DMAHalfTransmitCplt(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //Tx Half Complete Callback
+ if (xif_hdl->user_callback.TxHalfCpltCallback) {
+ xif_hdl->user_callback.TxHalfCpltCallback();
+ }
+}
+
+/**
+ * @brief DMA XIF half receive process complete callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+static void XIF_DMAHalfReceiveCplt(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //Rx Half Complete Callback
+ if (xif_hdl->user_callback.RxHalfCpltCallback) {
+ xif_hdl->user_callback.RxHalfCpltCallback();
+ }
+}
+
+/**
+ * @brief DMA XIF transmit process error callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+static void XIF_DMATransmitError(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //Disable Wait BUSY Timeout interrupt
+ __LL_XIF_WaitBusyTimeout_INT_Dis(Instance);
+
+ //Disable Tx DMA Request
+ __LL_XIF_TxDMA_Dis(Instance);
+
+ //DMA DeInit
+ XIF_DMA_DeInit(xif_hdl->tx_ctrl.dma_ch);
+ xif_hdl->tx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+
+ //Disable XIF to stop transmit
+ __LL_XIF_Dis(Instance);
+
+ xif_hdl->tx_ctrl.state = XIF_STATE_READY;
+
+ if (xif_hdl->user_callback.ErrorCallback) {
+ xif_hdl->user_callback.ErrorCallback();
+ }
+}
+
+/**
+ * @brief DMA XIF receive process error callback
+ * @param Instance Specifies XIF peripheral
+ * @return None
+ */
+static void XIF_DMAReceiveError(XIF_TypeDef *Instance)
+{
+ XIF_HandleTypeDef *xif_hdl;
+
+ //XIF handle get
+ xif_hdl = XIF_Handle_Get(Instance);
+
+ if (xif_hdl == NULL) {
+ LOG_E("Get XIF handle error!\n");
+ return;
+ }
+
+ //Disable Wait BUSY Timeout interrupt
+ __LL_XIF_WaitBusyTimeout_INT_Dis(Instance);
+
+ //Disable Rx DMA Request
+ __LL_XIF_RxDMA_Dis(Instance);
+
+ //DMA DeInit
+ XIF_DMA_DeInit(xif_hdl->rx_ctrl.dma_ch);
+ xif_hdl->rx_ctrl.dma_ch = DMA_CHANNEL_INVALID;
+
+ //Disable XIF to stop transmit
+ __LL_XIF_Dis(Instance);
+
+ xif_hdl->rx_ctrl.state = XIF_STATE_READY;
+
+ if (xif_hdl->user_callback.ErrorCallback) {
+ xif_hdl->user_callback.ErrorCallback();
+ }
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+
+#endif /* LL_XIF_MODULE_ENABLED */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/tae32_drivers/SConscript b/bsp/tae32/libraries/tae32_drivers/SConscript
new file mode 100644
index 0000000000..d759f0561e
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/SConscript
@@ -0,0 +1,43 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+# add pin drivers.
+if GetDepend('RT_USING_PIN'):
+ src += ['drv_gpio.c']
+
+# add usart drivers.
+if GetDepend(['RT_USING_SERIAL']):
+ if GetDepend(['RT_USING_SERIAL_V2']):
+ src += ['drv_uart_v2.c']
+ else:
+ src += ['drv_uart.c']
+
+# add wdt drivers.
+if GetDepend(['RT_USING_WDT']):
+ src += ['drv_wdt.c']
+
+# add can drivers.
+if GetDepend(['RT_USING_CAN']):
+ src += ['drv_can.c']
+
+# add flash drivers.
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_TAE32G58xx']):
+ src += [os.path.join('drv_flash', 'drv_flash_g58xx.c')]
+
+path = [cwd]
+
+path += [os.path.join(cwd, 'config')]
+
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+ path += [os.path.join(cwd, 'drv_flash')]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/tae32/libraries/tae32_drivers/config/g58xx/can_config.h b/bsp/tae32/libraries/tae32_drivers/config/g58xx/can_config.h
new file mode 100644
index 0000000000..9479474e9d
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/config/g58xx/can_config.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-27 yeml first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define TAE32_CAN_FD_ISO 1
+#define TAE32_CAN_FD_NON_ISO 0
+
+
+#define CAN_CLOCK (60000000U)
+
+#ifdef BSP_USING_CAN0
+#ifdef RT_CAN_USING_CANFD
+#define CAN0_CAN_FD_MODE TAE32_CAN_FD_NON_ISO
+#endif
+#endif
+
+#ifdef BSP_USING_CAN1
+#ifdef RT_CAN_USING_CANFD
+#define CAN1_CAN_FD_MODE TAE32_CAN_FD_NON_ISO
+#endif
+#endif
+
+
+/* Bit time config
+ Restrictions: num_seg1 >= (num_seg2 + 1), (num_seg2 + 1) >= (num_sjw + 1).
+
+ Baudrate = CANClock/(perescaler*((num_seg1 + 2) + (num_seg2 + 1)))
+ TQ = perescaler / CANClock.
+
+
+ | SYNC | PROP | PHASE1 | PHASE2 |
+TQ: | 1 | 1 | um_seg1 + 2 | num_seg2 + 1 |
+
+ Bit time = ((num_seg1 + 2) + (num_seg2 + 1) )
+
+ Sample point = (num_seg1 + 2) / ( (num_seg1 + 2) + (num_seg2 + 1) )
+
+ Users need to calculate the values under different baud rates based on the actual CAN clock.
+
+ The following bit time configures are based on CAN Clock 60M,Sample point is 80%
+*/
+#define CAN_BIT_TIME_CONFIG_1M_BAUD \
+ { \
+ .prescaler = 4, \
+ .num_seg1 = 10, \
+ .num_seg2 = 2, \
+ .num_sjw = 2 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_800K_BAUD \
+ { \
+ .prescaler = 5, \
+ .num_seg1 = 10, \
+ .num_seg2 = 2, \
+ .num_sjw = 2 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_500K_BAUD \
+ { \
+ .prescaler = 8, \
+ .num_seg1 = 10, \
+ .num_seg2 = 2, \
+ .num_sjw = 2 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_250K_BAUD \
+ { \
+ .prescaler = 16, \
+ .num_seg1 = 10, \
+ .num_seg2 = 2, \
+ .num_sjw = 2 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_125K_BAUD \
+ { \
+ .prescaler = 32, \
+ .num_seg1 = 10, \
+ .num_seg2 = 2, \
+ .num_sjw = 2 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_100K_BAUD \
+ { \
+ .prescaler = 40, \
+ .num_seg1 = 10, \
+ .num_seg2 = 2, \
+ .num_sjw = 2 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_50K_BAUD \
+ { \
+ .prescaler = 80, \
+ .num_seg1 = 10, \
+ .num_seg2 = 2, \
+ .num_sjw = 2 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_20K_BAUD \
+ { \
+ .prescaler = 200, \
+ .num_seg1 = 10, \
+ .num_seg2 = 2, \
+ .num_sjw = 2 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_10K_BAUD \
+ { \
+ .prescaler = 240, \
+ .num_seg1 = 18, \
+ .num_seg2 = 4, \
+ .num_sjw = 2 \
+ }
+
+#ifdef __cplusplus
+extern "C"
+}
+#endif
+#endif
+
diff --git a/bsp/tae32/libraries/tae32_drivers/config/g58xx/uart_config.h b/bsp/tae32/libraries/tae32_drivers/config/g58xx/uart_config.h
new file mode 100644
index 0000000000..669756a67e
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/config/g58xx/uart_config.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-17 yeml first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(BSP_USING_UART0)
+#ifndef UART0_CONFIG
+#define UART0_CONFIG \
+ { \
+ .name = "uart0", \
+ .irq_type = UART0_IRQn, \
+ }
+#endif /* UART0_CONFIG */
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG \
+ { \
+ .name = "uart1", \
+ .irq_type = UART1_IRQn, \
+ }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG \
+ { \
+ .name = "uart2", \
+ .irq_type = UART2_IRQn, \
+ }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG \
+ { \
+ .name = "uart3", \
+ .irq_type = UART3_IRQn, \
+ }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG \
+ { \
+ .name = "uart4", \
+ .irq_type = UART4_IRQn, \
+ }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/tae32/libraries/tae32_drivers/drv_can.c b/bsp/tae32/libraries/tae32_drivers/drv_can.c
new file mode 100644
index 0000000000..23e5e2c5eb
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/drv_can.c
@@ -0,0 +1,765 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-27 yeml the first version
+ */
+
+#define RT_USING_CAN
+#ifdef RT_USING_CAN
+
+#include "drv_can.h"
+
+enum
+{
+#ifdef BSP_USING_CAN0
+ CAN0_INDEX,
+#endif
+#ifdef BSP_USING_CAN1
+ CAN1_INDEX,
+#endif
+ CAN_INDEX_MAX
+};
+
+
+#define BSP_USING_CAN0
+static struct tae32_can can_obj[CAN_INDEX_MAX] =
+{
+#ifdef BSP_USING_CAN0
+ {
+ .name = "can0",
+ .Instance = CAN0,
+ }
+#endif
+
+#ifdef BSP_USING_CAN1
+ {
+ .name = "can1",
+ .Instance = CAN1,
+ }
+#endif
+};
+
+
+#define CAN_FILTER_COUNT (CAN_ACCEPT_FILT_SLOT_NUMS)
+
+struct tae32_can_bit_timing
+{
+ rt_uint8_t prescaler;
+ rt_uint8_t num_seg1;
+ rt_uint8_t num_seg2;
+ rt_uint8_t num_sjw;
+};
+
+struct tae32_baud_rate_tab
+{
+ rt_uint32_t baud_rate;
+ struct tae32_can_bit_timing bit_timing;
+};
+
+static const struct tae32_baud_rate_tab can_baud_rate_tab[] =
+{
+ {CAN1MBaud, CAN_BIT_TIME_CONFIG_1M_BAUD },
+ {CAN800kBaud, CAN_BIT_TIME_CONFIG_800K_BAUD},
+ {CAN500kBaud, CAN_BIT_TIME_CONFIG_500K_BAUD},
+ {CAN250kBaud, CAN_BIT_TIME_CONFIG_250K_BAUD},
+ {CAN125kBaud, CAN_BIT_TIME_CONFIG_125K_BAUD},
+ {CAN100kBaud, CAN_BIT_TIME_CONFIG_100K_BAUD},
+ {CAN50kBaud, CAN_BIT_TIME_CONFIG_50K_BAUD },
+ {CAN20kBaud, CAN_BIT_TIME_CONFIG_20K_BAUD },
+ {CAN10kBaud, CAN_BIT_TIME_CONFIG_10K_BAUD },
+};
+
+static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
+{
+ rt_uint32_t len, index;
+
+ len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
+ for (index = 0; index < len; index++)
+ {
+ if (can_baud_rate_tab[index].baud_rate == baud)
+ return index;
+ }
+
+ return 0; /* default baud is CAN1MBaud */
+}
+
+static rt_err_t tae32_can_filter_reset(struct rt_can_device *can)
+{
+ struct tae32_can *pCanObj;
+ pCanObj = rt_container_of(can, struct tae32_can, rt_can);
+
+ for (rt_uint8_t i = 0; i < CAN_FILTER_COUNT; i++)
+ {
+ /* CAN acceptance filter Code and Mask config */
+ __LL_CAN_AcceptFilAddr_Set(pCanObj->Instance, i);
+ __LL_CAN_AcceptFilContentSel_Mask(pCanObj->Instance);
+ __LL_CAN_AcceptFilCodeOrMaskVal_Set(pCanObj->Instance, 0);
+ __LL_CAN_AcceptFilRxFrm_Set(pCanObj->Instance, CAN_ACCEPT_FILT_FRM_STD_EXT);
+ __LL_CAN_AcceptFilContentSel_Code(pCanObj->Instance);
+ __LL_CAN_AcceptFilCodeOrMaskVal_Set(pCanObj->Instance, 0);
+
+ __LL_CAN_AcceptMode_Set(pCanObj->Instance, CAN_ACCEPT_MODE_AND);
+ __LL_CAN_AcceptCtrl_Set(pCanObj->Instance, CAN_ACCEPT_CTRL_STORE_PRB);
+
+ /* CAN acceptance filter disable */
+ __LL_CAN_AcceptFil_Dis(pCanObj->Instance, ((uint8_t)i));
+ }
+}
+
+static rt_err_t tae32_can_filter_cfg(struct rt_can_device *can)
+{
+ struct tae32_can *pCanObj;
+ pCanObj = rt_container_of(can, struct tae32_can, rt_can);
+ for (rt_uint8_t i = 0; i < pCanObj->config.accept_fil_cfg_num; i++)
+ {
+ /* CAN acceptance filter Code and Mask config */
+ __LL_CAN_AcceptFilAddr_Set(pCanObj->Instance, pCanObj->config.accept_fil_cfg_ptr[i].slot);
+ __LL_CAN_AcceptFilContentSel_Mask(pCanObj->Instance);
+ __LL_CAN_AcceptFilCodeOrMaskVal_Set(pCanObj->Instance, pCanObj->config.accept_fil_cfg_ptr[i].mask_val);
+ __LL_CAN_AcceptFilRxFrm_Set(pCanObj->Instance, pCanObj->config.accept_fil_cfg_ptr[i].rx_frm);
+ __LL_CAN_AcceptFilContentSel_Code(pCanObj->Instance);
+ __LL_CAN_AcceptFilCodeOrMaskVal_Set(pCanObj->Instance, pCanObj->config.accept_fil_cfg_ptr[i].code_val);
+
+ __LL_CAN_AcceptMode_Set(pCanObj->Instance, CAN_ACCEPT_MODE_AND);
+ __LL_CAN_AcceptCtrl_Set(pCanObj->Instance, CAN_ACCEPT_CTRL_STORE_PRB);
+
+ /* CAN acceptance filter enable */
+ __LL_CAN_AcceptFil_En(pCanObj->Instance, ((uint8_t)pCanObj->config.accept_fil_cfg_ptr[i].slot));
+ }
+}
+
+
+static LL_StatusETypeDef ll_can_transmitPTB(CAN_TypeDef *Instance, CAN_TxBufFormatTypeDef *buf_fmt, uint32_t *buf)
+{
+ uint8_t dat_len;
+
+ assert_param(IS_CAN_ALL_INSTANCE(Instance));
+ assert_param(buf_fmt != NULL);
+
+ /* Check last frame transmit complete or not */
+ if (__LL_CAN_TxPriEn_Get(Instance))
+ {
+ return LL_ERROR;
+ }
+
+ /* TX buffer select PTB*/
+ __LL_CAN_TxBufSel_PTB(Instance);
+
+ /* Write buffer format data */
+ __LL_CAN_TxBufReg_ID_Write(Instance, *((uint32_t *)buf_fmt));
+ __LL_CAN_TxBufReg_Ctrl_Write(Instance, *(((uint32_t *)buf_fmt) + 1));
+
+ /* Write data to TX buffer */
+ if (buf != NULL)
+ {
+ dat_len = LL_CAN_DatLen_Get(Instance, buf_fmt->data_len_code);
+
+ for (uint32_t i = 0; i < (dat_len + 3) / 4; i++)
+ {
+ __LL_CAN_TxBufReg_Data_Write(Instance, i, *buf++);
+ }
+ }
+ /* TX primary enable */
+ __LL_CAN_TxPriEn_Set(Instance);
+
+ return LL_OK;
+}
+
+static rt_err_t tae32_can_configure(struct rt_can_device *can, struct can_configure *cfg)
+{
+ struct tae32_can *pCanObj;
+ rt_uint32_t baud_ss_index;
+ rt_uint32_t baud_fs_index;
+ RT_ASSERT(can != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+ CAN_UserCfgTypeDef can_init;
+ rt_memset(&can_init, 0, sizeof(can_init));
+
+ pCanObj = rt_container_of(can, struct tae32_can, rt_can);
+
+ LL_CAN_MspInit(pCanObj->Instance);
+ __LL_CAN_Reset_Set(pCanObj->Instance);
+ __LL_CAN_AllIntLine_Clr(pCanObj->Instance);
+
+ baud_ss_index = get_can_baud_index(cfg->baud_rate);
+
+ pCanObj->config.func_clk_freq = CAN_CLOCK;
+ pCanObj->config.baudrate_ss = can_baud_rate_tab[baud_ss_index].baud_rate;
+ pCanObj->config.bit_timing_seg1_ss = can_baud_rate_tab[baud_ss_index].bit_timing.num_seg1;
+ pCanObj->config.bit_timing_seg2_ss = can_baud_rate_tab[baud_ss_index].bit_timing.num_seg2;
+ pCanObj->config.bit_timing_sjw_ss = can_baud_rate_tab[baud_ss_index].bit_timing.num_sjw;
+
+ baud_ss_index = get_can_baud_index(cfg->baud_rate);
+ __LL_CAN_SS_Prescaler_Set(pCanObj->Instance, can_baud_rate_tab[baud_ss_index].bit_timing.prescaler - 1);
+ __LL_CAN_SS_BitTimingSeg1_Set(pCanObj->Instance, pCanObj->config.bit_timing_seg1_ss);
+ __LL_CAN_SS_BitTimingSeg2_Set(pCanObj->Instance, pCanObj->config.bit_timing_seg2_ss);
+ __LL_CAN_SS_SyncJumpWidth_Set(pCanObj->Instance, pCanObj->config.bit_timing_sjw_ss);
+
+ pCanObj->config.fd_en = 0;
+ can_init.fd_iso_en = 0;
+ __LL_CAN_FD_Dis(pCanObj->Instance);
+ __LL_CAN_FD_ISO_Dis(pCanObj->Instance);
+
+#ifdef RT_CAN_USING_CANFD
+
+ if (cfg->enable_canfd)
+ {
+ pCanObj->config.fd_en = 1;
+ __LL_CAN_FD_En(pCanObj->Instance);
+
+#ifdef BSP_USING_CAN0
+ if ((CAN0_CAN_FD_MODE) && (pCanObj->Instance == CAN0))
+ {
+ pCanObj->config.fd_iso_en = 1;
+ __LL_CAN_FD_ISO_En(pCanObj->Instance);
+ }
+#endif
+#ifdef BSP_USING_CAN1
+ if ((CAN1_CAN_FD_MODE) && (pCanObj->Instance == CAN1))
+ {
+ pCanObj->config.fd_iso_en = 1;
+ __LL_CAN_FD_ISO_En(pCanObj->Instance);
+ }
+#endif
+ if (pCanObj->rt_can.config.use_bit_timing)
+ {
+ pCanObj->config.baudrate_ss = cfg->baud_rate;
+ pCanObj->config.bit_timing_seg1_ss = cfg->can_timing.num_seg1;
+ pCanObj->config.bit_timing_seg2_ss = cfg->can_timing.num_seg2;
+ pCanObj->config.bit_timing_sjw_ss = cfg->can_timing.num_sjw;
+
+ pCanObj->config.baudrate_fs = cfg->baud_rate_fd;
+ pCanObj->config.bit_timing_seg1_fs = cfg->canfd_timing.num_seg1;
+ pCanObj->config.bit_timing_seg2_fs = cfg->canfd_timing.num_seg2;
+ pCanObj->config.bit_timing_sjw_fs = cfg->canfd_timing.num_sjw;
+
+ __LL_CAN_SS_Prescaler_Set(pCanObj->Instance, cfg->can_timing.prescaler - 1);
+ __LL_CAN_FS_Prescaler_Set(pCanObj->Instance, cfg->canfd_timing.prescaler - 1);
+ }
+ else
+ {
+ baud_ss_index = get_can_baud_index(cfg->baud_rate);
+ pCanObj->config.baudrate_ss = can_baud_rate_tab[baud_ss_index].baud_rate;
+ pCanObj->config.bit_timing_seg1_ss = can_baud_rate_tab[baud_ss_index].bit_timing.num_seg1;
+ pCanObj->config.bit_timing_seg2_ss = can_baud_rate_tab[baud_ss_index].bit_timing.num_seg2;
+ pCanObj->config.bit_timing_sjw_ss = can_baud_rate_tab[baud_ss_index].bit_timing.num_sjw;
+ __LL_CAN_SS_Prescaler_Set(pCanObj->Instance, can_baud_rate_tab[baud_ss_index].bit_timing.prescaler - 1);
+
+ baud_fs_index = get_can_baud_index(cfg->baud_rate_fd);
+ pCanObj->config.baudrate_fs = can_baud_rate_tab[baud_fs_index].baud_rate;
+ pCanObj->config.bit_timing_seg1_fs = can_baud_rate_tab[baud_fs_index].bit_timing.num_seg1;
+ pCanObj->config.bit_timing_seg2_fs = can_baud_rate_tab[baud_fs_index].bit_timing.num_seg2;
+ pCanObj->config.bit_timing_sjw_fs = can_baud_rate_tab[baud_fs_index].bit_timing.num_sjw;
+ __LL_CAN_FS_Prescaler_Set(pCanObj->Instance, can_baud_rate_tab[baud_fs_index].bit_timing.prescaler - 1);
+ }
+ __LL_CAN_SS_BitTimingSeg1_Set(pCanObj->Instance, pCanObj->config.bit_timing_seg1_ss);
+ __LL_CAN_SS_BitTimingSeg2_Set(pCanObj->Instance, pCanObj->config.bit_timing_seg2_ss);
+ __LL_CAN_SS_SyncJumpWidth_Set(pCanObj->Instance, pCanObj->config.bit_timing_sjw_ss);
+ __LL_CAN_FS_BitTimingSeg1_Set(pCanObj->Instance, pCanObj->config.bit_timing_seg1_fs);
+ __LL_CAN_FS_BitTimingSeg2_Set(pCanObj->Instance, pCanObj->config.bit_timing_seg2_fs);
+ __LL_CAN_FS_SyncJumpWidth_Set(pCanObj->Instance, pCanObj->config.bit_timing_sjw_fs);
+
+#endif
+ switch (cfg->mode)
+ {
+ case RT_CAN_MODE_NORMAL:
+ __LL_CAN_ListenOnlyMode_Dis(pCanObj->Instance);
+ __LL_CAN_LoopBackModeInternal_Dis(pCanObj->Instance);
+ __LL_CAN_LoopBackModeExt_Dis(pCanObj->Instance);
+ break;
+
+ case RT_CAN_MODE_LISTEN:
+ __LL_CAN_ListenOnlyMode_En(pCanObj->Instance);
+ __LL_CAN_LoopBackModeInternal_Dis(pCanObj->Instance);
+ __LL_CAN_LoopBackModeExt_Dis(pCanObj->Instance);
+
+ break;
+ case RT_CAN_MODE_LOOPBACK:
+ __LL_CAN_LoopBackModeInternal_En(pCanObj->Instance);
+ __LL_CAN_ListenOnlyMode_Dis(pCanObj->Instance);
+ __LL_CAN_LoopBackModeExt_Dis(pCanObj->Instance);
+ break;
+
+ case RT_CAN_MODE_LOOPBACKANLISTEN:
+ __LL_CAN_LoopBackModeExt_En(pCanObj->Instance);
+ __LL_CAN_ListenOnlyMode_Dis(pCanObj->Instance);
+ __LL_CAN_LoopBackModeInternal_Dis(pCanObj->Instance);
+ break;
+ }
+ }
+ __LL_CAN_Reset_Clr(pCanObj->Instance);
+ return RT_EOK;
+}
+
+rt_err_t tae32_can_control(struct rt_can_device * can, int cmd, void *arg)
+{
+ rt_uint32_t argval;
+ struct tae32_can *pCanObj;
+ struct rt_can_filter_config *pFilterCfg = (struct rt_can_filter_config *)arg;
+ struct rt_can_bit_timing_config *timing_configs = (struct rt_can_bit_timing_config*)argval;
+
+ CAN_AcceptFilCfgTypeDef can_acpt_fil_cfg[CAN_FILTER_COUNT];
+
+ RT_ASSERT(can != RT_NULL);
+ pCanObj = rt_container_of(can, struct tae32_can, rt_can);
+ RT_ASSERT(pCanObj != RT_NULL);
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_CLR_INT:
+ argval = (rt_uint32_t) arg;
+ if (0 == pCanObj->intOpenCnt)
+ {
+ if (pCanObj->Instance == CAN0)
+ {
+ LL_NVIC_DisableIRQ(CAN0_IRQn);
+ }
+#ifdef BSP_USING_CAN1
+ if (pCanObj->Instance == CAN1)
+ {
+ LL_NVIC_DisableIRQ(CAN1_IRQn);
+ }
+#endif
+ }
+
+ if (argval == RT_DEVICE_FLAG_INT_RX)
+ {
+ pCanObj->intOpenCnt &= ~(1 << 0);
+ __LL_CAN_Rx_INT_Dis(pCanObj->Instance);
+ __LL_CAN_RxBufOver_INT_Dis(pCanObj->Instance);
+ __LL_CAN_RxBufFull_INT_Dis(pCanObj->Instance);
+ }
+ else if (argval == RT_DEVICE_FLAG_INT_TX)
+ {
+ pCanObj->intOpenCnt &= ~(1 << 1);
+ __LL_CAN_TxPri_INT_En(pCanObj->Instance);
+ }
+
+ else if (argval == RT_DEVICE_CAN_INT_ERR)
+ {
+ pCanObj->intOpenCnt &= ~(1 << 2);
+ __LL_CAN_Err_INT_Dis(pCanObj->Instance);
+ __LL_CAN_ArbLost_INT_Dis(pCanObj->Instance);
+ __LL_CAN_ErrPassive_INT_Dis(pCanObj->Instance);
+ __LL_CAN_BusErr_INT_Dis(pCanObj->Instance);
+ }
+ break;
+ case RT_DEVICE_CTRL_SET_INT:
+ argval = (rt_uint32_t) arg;
+
+ if (0 == pCanObj->intOpenCnt)
+ {
+ if (pCanObj->Instance == CAN0)
+ {
+ pCanObj->Instance->INTRLS = 0;
+ LL_NVIC_EnableIRQ(CAN0_IRQn);
+ }
+#ifdef BSP_USING_CAN1
+ if (pCanObj->Instance == CAN1)
+ {
+ pCanObj->Instance->INTRLS = 0;
+ LL_NVIC_EnableIRQ(CAN1_IRQn);
+ }
+#endif
+ }
+
+ if (argval == RT_DEVICE_FLAG_INT_RX)
+ {
+ pCanObj->intOpenCnt |= (1 << 0);
+ __LL_CAN_Rx_INT_En(pCanObj->Instance);
+ __LL_CAN_RxBufOver_INT_En(pCanObj->Instance);
+ }
+ else if (argval == RT_DEVICE_FLAG_INT_TX)
+ {
+ pCanObj->intOpenCnt |= (1 << 1);
+ __LL_CAN_TxPri_INT_En(pCanObj->Instance); /* PTB */
+ }
+ else if (argval == RT_DEVICE_CAN_INT_ERR)
+ {
+ pCanObj->intOpenCnt |= (1 << 2);
+ __LL_CAN_Err_INT_En(pCanObj->Instance);
+ __LL_CAN_ArbLost_INT_En(pCanObj->Instance);
+ __LL_CAN_ErrPassive_INT_En(pCanObj->Instance);
+ __LL_CAN_BusErr_INT_En(pCanObj->Instance);
+ }
+ break;
+
+ case RT_CAN_CMD_SET_FILTER:
+ rt_memset(can_acpt_fil_cfg, 0, sizeof(can_acpt_fil_cfg));
+ if (pFilterCfg->count > CAN_FILTER_COUNT)
+ {
+ return RT_FALSE;
+ }
+
+ for (rt_size_t i = 0; i < pFilterCfg->count; i++)
+ {
+ if (pFilterCfg->items[i].hdr_bank != -1)
+ {
+ can_acpt_fil_cfg[i].slot = pFilterCfg->items[i].hdr_bank;
+ }
+ else
+ {
+ can_acpt_fil_cfg[i].slot = i;
+
+ }
+ can_acpt_fil_cfg[i].code_val = pFilterCfg->items[i].id;
+
+ /* tae32 CAN mask, 0 mean filter, 1 mean ignore. */
+ if (pFilterCfg->items[i].mode)
+ {
+ /* rtt can device filter list mode */
+ can_acpt_fil_cfg[i].mask_val = 0;
+ }
+ else
+ {
+ /* rtt can device filter mask mode，mask=0 mean ignore, mask=1 mean filter */
+ can_acpt_fil_cfg[i].mask_val = (~pFilterCfg->items[i].mask) & 0x1FFFFFFF;
+ }
+
+ switch (pFilterCfg->items[i].ide)
+ {
+ case RT_CAN_STDID:
+ can_acpt_fil_cfg[i].rx_frm = CAN_ACCEPT_FILT_FRM_STD;
+ break;
+ case RT_CAN_EXTID:
+ can_acpt_fil_cfg[i].rx_frm = CAN_ACCEPT_FILT_FRM_EXT;
+ break;
+ }
+ }
+ pCanObj->config.accept_fil_cfg_ptr = can_acpt_fil_cfg;
+ pCanObj->config.accept_fil_cfg_num = pFilterCfg->count;
+
+ tae32_can_filter_reset(can);
+ tae32_can_filter_cfg(can);
+ break;
+
+ case RT_CAN_CMD_SET_MODE:
+ argval = (rt_uint32_t) arg;
+ if (argval != RT_CAN_MODE_NORMAL &&
+ argval != RT_CAN_MODE_LISTEN &&
+ argval != RT_CAN_MODE_LOOPBACK &&
+ argval != RT_CAN_MODE_LOOPBACKANLISTEN)
+ {
+ return -RT_ERROR;
+ }
+ if (argval != pCanObj->rt_can.config.mode)
+ {
+ pCanObj->rt_can.config.mode = argval;
+ return tae32_can_configure(&pCanObj->rt_can, &pCanObj->rt_can.config);
+ }
+ break;
+ case RT_CAN_CMD_SET_BAUD:
+ argval = (rt_uint32_t) arg;
+ if (argval != CAN1MBaud &&
+ argval != CAN800kBaud &&
+ argval != CAN500kBaud &&
+ argval != CAN250kBaud &&
+ argval != CAN125kBaud &&
+ argval != CAN100kBaud &&
+ argval != CAN50kBaud &&
+ argval != CAN20kBaud &&
+ argval != CAN10kBaud)
+ {
+ return -RT_ERROR;
+ }
+ if (argval != pCanObj->rt_can.config.baud_rate)
+ {
+ pCanObj->rt_can.config.baud_rate = argval;
+ return tae32_can_configure(&pCanObj->rt_can, &pCanObj->rt_can.config);
+ }
+ break;
+
+#ifdef RT_CAN_USING_CANFD
+ case RT_CAN_CMD_SET_CANFD:
+ argval = (uint32_t) arg;
+ if (argval != pCanObj->rt_can.config.enable_canfd)
+ {
+ pCanObj->rt_can.config.enable_canfd = argval;
+ tae32_can_configure(can, &pCanObj->rt_can.config);
+ }
+ break;
+ case RT_CAN_CMD_SET_BAUD_FD:
+ argval = (uint32_t) arg;
+ if (argval != pCanObj->rt_can.config.baud_rate_fd)
+ {
+ pCanObj->rt_can.config.baud_rate_fd = argval;
+ tae32_can_configure(can, &pCanObj->rt_can.config);
+ }
+ break;
+ case RT_CAN_CMD_SET_BITTIMING:
+
+ if ((timing_configs == RT_NULL) || (timing_configs->count < 1) || (timing_configs->count > 2))
+ {
+ return -RT_ERROR;
+ }
+ if (timing_configs->count != 0U)
+ {
+ pCanObj->rt_can.config.can_timing = timing_configs->items[0];
+ }
+ if (timing_configs->count == 2)
+ {
+ pCanObj->rt_can.config.canfd_timing = timing_configs->items[1];
+ }
+ tae32_can_configure(can, &pCanObj->rt_can.config);
+ break;
+#endif
+ case RT_CAN_CMD_SET_PRIV:
+ pCanObj->rt_can.config.privmode = argval;
+ break;
+ case RT_CAN_CMD_GET_STATUS:
+ pCanObj->rt_can.status.rcverrcnt = __LL_CAN_RxErrCnt_Get(pCanObj->Instance);
+ pCanObj->rt_can.status.snderrcnt = __LL_CAN_TxErrCnt_Get(pCanObj->Instance);
+ pCanObj->rt_can.status.lasterrtype = __LL_CAN_ErrCode_Get(pCanObj->Instance);
+ pCanObj->rt_can.status.errcode = 0;
+ if (__LL_CAN_IsErrWarnLimitReached(pCanObj->Instance))
+ {
+ pCanObj->rt_can.status.errcode |= ERRWARNING;
+ }
+ if (__LL_CAN_IsErrPassiveModeActive(pCanObj->Instance))
+ {
+ pCanObj->rt_can.status.errcode |= ERRPASSIVE;
+ }
+ if (__LL_CAN_IsBusOff(pCanObj->Instance))
+ {
+ pCanObj->rt_can.status.errcode |= BUSOFF;
+ }
+ rt_memcpy(arg, &pCanObj->rt_can.status, sizeof(pCanObj->rt_can.status));
+ break;
+
+ /* case RT_CAN_CMD_START:break; */
+ }
+ return RT_EOK;
+}
+
+static rt_ssize_t tae32_can_sendmsg(struct rt_can_device * can, const void *buf, rt_uint32_t boxno)
+{
+ struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+ struct tae32_can *pCanObj;
+
+ CAN_TxBufFormatTypeDef buf_fmt;
+
+ RT_ASSERT(can != RT_NULL);
+ pCanObj = rt_container_of(can, struct tae32_can, rt_can);
+ RT_ASSERT(pCanObj != RT_NULL);
+
+ rt_memset((void *)(&buf_fmt), 0, sizeof(buf_fmt));
+
+ /* Set up the Id */
+ buf_fmt.id = pmsg->id;
+
+ /* Set up the IDE */
+ buf_fmt.id_extension = pmsg->ide;
+
+ buf_fmt.remote_tx_req = pmsg->rtr;
+
+#ifdef RT_CAN_USING_CANFD
+ if (pmsg->fd_frame != 0)
+ {
+ RT_ASSERT(pmsg->len <= 64);
+ }
+ else
+ {
+ RT_ASSERT(pmsg->len <= 8);
+ }
+
+ buf_fmt.bit_rate_switch = pmsg->brs;
+ buf_fmt.extended_data_len = pmsg->fd_frame;
+
+#endif
+ /* Set up the DLC */
+ buf_fmt.data_len_code = LL_CAN_DatLenCode_Get(pCanObj->Instance, pmsg->len);
+
+ /* Request transmission */
+ if (ll_can_transmitPTB(pCanObj->Instance, &buf_fmt, (rt_uint32_t *)pmsg->data) != LL_OK)
+ {
+ return RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+
+static rt_ssize_t tae32_can_recvmsg(struct rt_can_device * can, void *buf, rt_uint32_t fifo)
+{
+ struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+ struct tae32_can *pCanObj;
+
+ CAN_RxBufFormatTypeDef buf_fmt;
+
+ RT_ASSERT(can != RT_NULL);
+ pCanObj = rt_container_of(can, struct tae32_can, rt_can);
+ RT_ASSERT(pCanObj != RT_NULL);
+
+ *((uint32_t *)(&buf_fmt) + 0) = __LL_CAN_RxBufReg_ID_Read(pCanObj->Instance);
+ *((uint32_t *)(&buf_fmt) + 1) = __LL_CAN_RxBufReg_Ctrl_Read(pCanObj->Instance);
+
+ if (&(pmsg->data) != NULL)
+ {
+ rt_memcpy((void *)pmsg->data, (void *)pCanObj->Instance->RBUFDT, LL_CAN_DatLen_Get(pCanObj->Instance, buf_fmt.data_len_code));
+ }
+ /* RxFIFO Release(Clear) */
+ __LL_CAN_RxBufRelease(pCanObj->Instance);
+
+ /* get id */
+ if (0 == buf_fmt.id_extension)
+ {
+ pmsg->ide = RT_CAN_STDID;
+ }
+ else
+ {
+ pmsg->ide = RT_CAN_EXTID;
+ }
+ pmsg->id = buf_fmt.id;
+
+ /* get type */
+ if (0 == buf_fmt.remote_tx_req)
+ {
+ pmsg->rtr = RT_CAN_DTR;
+ }
+ else
+ {
+ pmsg->rtr = RT_CAN_RTR;
+ }
+
+#ifdef RT_CAN_USING_CANFD
+ pmsg->fd_frame = buf_fmt.extended_data_len;
+ pmsg->brs = buf_fmt.bit_rate_switch;
+#endif
+ /* get len */
+ pmsg->len = LL_CAN_DatLen_Get(pCanObj->Instance, buf_fmt.data_len_code);
+
+ /* get hdr_index */
+ pmsg->hdr_index = buf_fmt.acceptance_data;
+ pCanObj->rt_can.hdr[pmsg->hdr_index].connected = 1;
+
+ return RT_EOK;
+}
+
+static void tae32_can_isr(struct rt_can_device * can)
+{
+ struct tae32_can *pCanObj;
+ uint32_t int_en, int_pending;
+
+ RT_ASSERT(can != RT_NULL);
+
+ pCanObj = rt_container_of(can, struct tae32_can, rt_can);
+ RT_ASSERT(pCanObj != RT_NULL);
+
+ /* All Interrupt Enalbe and Pending Get */
+ int_en = __LL_CAN_AllIntEn_Get(pCanObj->Instance);
+ int_pending = __LL_CAN_AllIntPnd_Get(pCanObj->Instance);
+
+
+ /* Rx Interrupt Handler */
+ if ((int_en & CAN0_INTREN_RIE_Msk) && (int_pending & CAN0_INTRST_RIF_Msk))
+ {
+ __LL_CAN_RxIntPnd_Clr(pCanObj->Instance);
+ rt_hw_can_isr(&pCanObj->rt_can, RT_CAN_EVENT_RX_IND | (0UL << 8));
+ }
+
+ /* Rx Overrun Interrupt Handler */
+ if ((int_en & CAN0_INTREN_ROIE_Msk) && (int_pending & CAN0_INTRST_ROIF_Msk))
+ {
+ __LL_CAN_RxOverIntPnd_Clr(pCanObj->Instance);
+ rt_hw_can_isr(&pCanObj->rt_can, RT_CAN_EVENT_RXOF_IND | (0UL << 8));
+ }
+
+ /* Transmission Primary Interrupt Handler */
+ if ((int_en & CAN0_INTREN_TPIE_Msk) && (int_pending & CAN0_INTRST_TPIF_Msk))
+ {
+ __LL_CAN_TxPriIntPnd_Clr(pCanObj->Instance);
+ rt_hw_can_isr(&pCanObj->rt_can, RT_CAN_EVENT_TX_DONE | (0UL << 8));
+ }
+
+ /* Error Passive Interrupt Handler */
+ if ((int_en & CAN0_INTREN_EPIE_Msk) && (int_pending & CAN0_INTRST_EPIF_Msk))
+ {
+ __LL_CAN_ErrPassiveIntPnd_Clr(pCanObj->Instance);
+ }
+
+ /* Arbitration Lost Interrupt Handler */
+ if ((int_en & CAN0_INTREN_ALIE_Msk) && (int_pending & CAN0_INTRST_ALIF_Msk))
+ {
+ rt_hw_can_isr(&pCanObj->rt_can, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+ __LL_CAN_ArbLostIntPnd_Clr(pCanObj->Instance);
+ }
+
+ /* Bus Error Interrupt Handler */
+ if ((int_en & CAN0_INTREN_BEIE_Msk) && (int_pending & CAN0_INTRST_BEIF_Msk))
+ {
+ rt_hw_can_isr(&pCanObj->rt_can, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+ __LL_CAN_BusErrIntPnd_Clr(pCanObj->Instance);
+ }
+
+ /* Error Interrupt Handler */
+ if ((int_en & CAN0_INTREN_EIE_Msk) && (int_pending & CAN0_INTRST_EIF_Msk))
+ {
+ __LL_CAN_ErrIntPnd_Clr(pCanObj->Instance);
+ rt_hw_can_isr(&pCanObj->rt_can, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+ }
+}
+
+#ifdef BSP_USING_CAN0
+void CAN0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ tae32_can_isr(&can_obj[CAN0_INDEX].rt_can);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_CAN1
+void CAN1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ tae32_can_isr(&can_obj[CAN1_INDEX].rt_can);
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+
+static const struct rt_can_ops tae32_can_ops =
+{
+ tae32_can_configure,
+ tae32_can_control,
+ tae32_can_sendmsg,
+ tae32_can_recvmsg,
+};
+
+
+int rt_hw_can_init(void)
+{
+ int result = RT_EOK;
+ struct can_configure config = CANDEFAULTCONFIG;
+ config.privmode = RT_CAN_MODE_NOPRIV;
+ config.ticks = 50;
+#ifdef RT_CAN_USING_HDR
+ config.maxhdr = CAN_FILTER_COUNT;
+#endif
+
+ for (rt_uint32_t i = 0; i < CAN_INDEX_MAX; i++)
+ {
+ can_obj[i].rt_can.config = config;
+ rt_memset(&can_obj[i].config, 0, sizeof(can_obj[i].config));
+ /* register CAN device */
+ result = rt_hw_can_register(&can_obj[i].rt_can,
+ can_obj[i].name,
+ &tae32_can_ops,
+ NULL);
+ }
+ return result;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_can_init);
+
+#endif /* RT_USING_CAN */
diff --git a/bsp/tae32/libraries/tae32_drivers/drv_can.h b/bsp/tae32/libraries/tae32_drivers/drv_can.h
new file mode 100644
index 0000000000..dba9eb413a
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/drv_can.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-27 yeml the first version
+ */
+
+#ifndef __DRV_CAN_H__
+#define __DRV_CAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "board.h"
+#include
+#include
+
+#ifdef SOC_SERIES_TAE32G58xx
+#include "tae32g58xx_ll_can.h"
+#include "config/g58xx/can_config.h"
+#endif
+
+/* tae32 can device */
+struct tae32_can
+{
+ struct rt_can_device rt_can; /* inherit from can device */
+
+ char *name;
+ CAN_TypeDef *Instance;
+ CAN_UserCfgTypeDef config;
+
+ rt_int8_t intOpenCnt;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DRV_CAN_H__ */
diff --git a/bsp/tae32/libraries/tae32_drivers/drv_flash/drv_flash.h b/bsp/tae32/libraries/tae32_drivers/drv_flash/drv_flash.h
new file mode 100644
index 0000000000..ebce6ebb1d
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/drv_flash/drv_flash.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-22 yeml first version
+ *
+ */
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include
+#include "rtdevice.h"
+#include
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined SOC_SERIES_TAE32G58xx
+#include "tae32g58xx_ll_eflash.h"
+#endif
+
+int tae32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
+int tae32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
+int tae32_flash_erase(rt_uint32_t addr, size_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_FLASH_H__ */
diff --git a/bsp/tae32/libraries/tae32_drivers/drv_flash/drv_flash_g58xx.c b/bsp/tae32/libraries/tae32_drivers/drv_flash/drv_flash_g58xx.c
new file mode 100644
index 0000000000..edebaebf54
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/drv_flash/drv_flash_g58xx.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-22 yeml first version
+ *
+ */
+#include
+#include
+
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_flash.h"
+#include "board.h"
+
+#if defined(RT_USING_FAL)
+ #include "fal.h"
+#endif
+
+#define DBG_TAG "FLASH"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae_dbg.h"
+int tae32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
+{
+ size_t i;
+
+ if ((addr + size) > TAE32_FLASH_END_ADDRESS)
+ {
+ LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+ return -RT_EINVAL;
+ }
+ for (i = 0; i < size; i++)
+ {
+ *buf = *((rt_uint8_t *)addr);
+ addr++;
+ buf++;
+ }
+ return i;
+}
+
+int tae32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
+{
+ rt_err_t result = RT_EOK;
+ rt_uint32_t end_addr = addr + size;
+
+ if (addr % 4 != 0)
+ {
+ LOG_E("write addr must be 4-byte alignment");
+ return -RT_EINVAL;
+ }
+
+ if ((end_addr) > TAE32_FLASH_END_ADDRESS)
+ {
+ LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
+ return -RT_EINVAL;
+ }
+
+ LL_EFLASH_ProgErase_Unlock(EFLASH);
+
+ if (0 == LL_EFLASH_Program(EFLASH, addr, (rt_uint8_t *)buf, size))
+ {
+ LOG_E("write size must be 8-byte alignment");
+ result = -RT_ERROR;
+ }
+
+ LL_EFLASH_ProgErase_Lock(EFLASH);
+
+ if (result != RT_EOK)
+ {
+ return result;
+ }
+ else
+ {
+ return size;
+ }
+}
+
+int tae32_flash_erase(rt_uint32_t addr, size_t size)
+{
+ rt_err_t result = RT_EOK;
+
+ rt_uint32_t sector_num = 0;
+ rt_uint32_t sector_cnt = 0;
+ rt_uint32_t sector_size = 0;
+ rt_uint32_t flash_sec_nums = 0;
+ size_t i = 0;
+
+ if ((addr + size) > TAE32_FLASH_END_ADDRESS)
+ {
+ LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+ return -RT_EINVAL;
+ }
+
+ if (size < 1)
+ {
+ return -RT_EINVAL;
+ }
+
+ flash_sec_nums = LL_EFLASH_SectorNums_Get(EFLASH);
+ if (flash_sec_nums == EFLASH_SECTOR_NUM_256_S)
+ {
+ sector_size = EFLASH_SECTOR_SIZE_256_S;
+ }
+ else
+ {
+ sector_size = EFLASH_SECTOR_SIZE_256_D;
+ }
+
+ sector_cnt = size / sector_size;
+ if(size % sector_size)
+ {
+ sector_cnt++;
+ }
+ sector_num = (addr - 0x08000000) / sector_size;
+
+ LL_EFLASH_ProgErase_Unlock(EFLASH);
+ for (i = 0; i < sector_cnt; i++)
+ {
+ if (LL_EFLASH_EraseSector(EFLASH, sector_num) != LL_OK)
+ {
+ result = -RT_ERROR;
+ break;
+ }
+ sector_num++;
+ }
+ LL_EFLASH_ProgErase_Lock(EFLASH);
+
+ if (result != RT_EOK)
+ {
+ return result;
+ }
+ else
+ {
+ return size;
+ }
+}
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_erase(long offset, size_t size);
+
+const struct fal_flash_dev tae32_onchip_flash =
+{
+ "onchip_flash",
+ ((uint32_t)0x08000000),
+#ifdef BSP_USING_FLASH_SBANK
+ (EFLASH_SECTOR_NUM_256_S * EFLASH_SECTOR_SIZE_256_S),
+ EFLASH_SECTOR_SIZE_256_S,
+#else
+ (EFLASH_SECTOR_NUM_256_D * EFLASH_SECTOR_SIZE_256_D),
+ EFLASH_SECTOR_SIZE_256_D,
+#endif
+ {
+ NULL,
+ fal_flash_read,
+ fal_flash_write,
+ fal_flash_erase
+ }
+};
+
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
+{
+ return tae32_flash_read(tae32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+ return tae32_flash_write(tae32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_erase(long offset, size_t size)
+{
+ return tae32_flash_erase(tae32_onchip_flash.addr + offset, size);
+}
+
+
+#endif /* BSP_USING_ON_CHIP_FLASH */
\ No newline at end of file
diff --git a/bsp/tae32/libraries/tae32_drivers/drv_gpio.c b/bsp/tae32/libraries/tae32_drivers/drv_gpio.c
new file mode 100644
index 0000000000..087eacac30
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/drv_gpio.c
@@ -0,0 +1,602 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-20 yeml the first version
+ */
+
+#include
+#include
+#include
+
+#include "drv_gpio.h"
+
+#ifdef RT_USING_PIN
+
+#define PIN_NUM_CALC(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
+
+#define PIN_PORT_GET(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
+#define PIN_NO_GET(pin) ((uint8_t)((pin) & 0xFu))
+
+#define TAE32_PORT_GET(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT_GET(pin))))
+#define TAE32_PIN_GET(pin) ((uint16_t)(1u << PIN_NO_GET(pin)))
+
+#if defined(GPIOZ)
+ #define __TAE32_PORT_MAX 12u
+#elif defined(GPIOK)
+ #define __TAE32_PORT_MAX 11u
+#elif defined(GPIOJ)
+ #define __TAE32_PORT_MAX 10u
+#elif defined(GPIOI)
+ #define __TAE32_PORT_MAX 9u
+#elif defined(GPIOH)
+ #define __TAE32_PORT_MAX 8u
+#elif defined(GPIOG)
+ #define __TAE32_PORT_MAX 7u
+#elif defined(GPIOF)
+ #define __TAE32_PORT_MAX 6u
+#elif defined(GPIOE)
+ #define __TAE32_PORT_MAX 5u
+#elif defined(GPIOD)
+ #define __TAE32_PORT_MAX 4u
+#elif defined(GPIOC)
+ #define __TAE32_PORT_MAX 3u
+#elif defined(GPIOB)
+ #define __TAE32_PORT_MAX 2u
+#elif defined(GPIOA)
+ #define __TAE32_PORT_MAX 1u
+#else
+ #define __TAE32_PORT_MAX 0u
+ #error Unsupported TAE32 GPIO peripheral.
+#endif
+
+#define PIN_TAEPORT_MAX __TAE32_PORT_MAX
+
+struct tea32_pin_irq_hdr
+{
+ IRQn_Type irq_port;
+ struct rt_pin_irq_hdr hdr_pin[16];
+};
+
+struct tea32_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+ {
+ GPIOA_IRQn,
+ {
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ }
+ },
+ {
+ GPIOB_IRQn,
+ {
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ }
+ },
+ {
+ GPIOC_IRQn,
+ {
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ }
+ },
+ {
+ GPIOD_IRQn,
+ {
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ }
+ },
+ {
+ GPIOE_IRQn,
+ {
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ }
+ },
+ {
+ GPIOF_IRQn,
+ {
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ {-1, 0, RT_NULL, RT_NULL},
+ }
+ }
+};
+
+static uint32_t irq_enable_mask[PIN_TAEPORT_MAX][16] = {0};
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+
+static rt_base_t tae32_pin_get(const char *name)
+{
+ rt_base_t pin = 0;
+ int hw_port_num, hw_pin_num = 0;
+ int i, name_len;
+
+ name_len = rt_strlen(name);
+
+ if ((name_len < 4) || (name_len >= 6))
+ {
+ goto out;
+ }
+ if ((name[0] != 'P') || (name[2] != '.'))
+ {
+ goto out;
+ }
+
+ if ((name[1] >= 'A') && (name[1] <= 'Z'))
+ {
+ hw_port_num = (int)(name[1] - 'A');
+ }
+ else
+ {
+ goto out;
+ }
+
+ for (i = 3; i < name_len; i++)
+ {
+ hw_pin_num *= 10;
+ hw_pin_num += name[i] - '0';
+ }
+
+ pin = PIN_NUM_CALC(hw_port_num, hw_pin_num);
+
+ return pin;
+
+out:
+ rt_kprintf("Px.y x:A~Z y:0-15, e.g. PA.0\n");
+ return -RT_EINVAL;
+}
+
+static void tae32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
+{
+ GPIO_TypeDef *gpio_port;
+ uint16_t gpio_pin;
+
+ if (PIN_PORT_GET(pin) < PIN_TAEPORT_MAX)
+ {
+ gpio_port = TAE32_PORT_GET(pin);
+ gpio_pin = TAE32_PIN_GET(pin);
+
+ LL_GPIO_WritePin(gpio_port, gpio_pin, (GPIO_PinStateETypeDef)value);
+ }
+}
+
+static rt_size_t tae32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+ GPIO_TypeDef *gpio_port;
+ uint16_t gpio_pin;
+ GPIO_PinStateETypeDef state = GPIO_PIN_RESET;
+
+ if (PIN_PORT_GET(pin) < PIN_TAEPORT_MAX)
+ {
+ gpio_port = TAE32_PORT_GET(pin);
+ gpio_pin = TAE32_PIN_GET(pin);
+ state = LL_GPIO_ReadPin(gpio_port, gpio_pin);
+ }
+ else
+ {
+ return -RT_EINVAL;
+ }
+
+ return (state == GPIO_PIN_RESET) ? PIN_LOW : PIN_HIGH;
+}
+
+static void tae32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
+{
+ GPIO_InitTypeDef GPIO_InitStruct;
+
+ if (PIN_PORT_GET(pin) >= PIN_TAEPORT_MAX)
+ {
+ return;
+ }
+
+ /* Configure GPIO_InitStructure */
+ GPIO_InitStruct.Pin = (uint32_t)TAE32_PIN_GET(pin);
+ GPIO_InitStruct.OType = GPIO_OTYPE_PP;
+ GPIO_InitStruct.Alternate = GPIO_AF1_OUTPUT;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+
+ switch (mode)
+ {
+ case PIN_MODE_OUTPUT:
+ /* output setting */
+ GPIO_InitStruct.Alternate = GPIO_AF1_OUTPUT;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ break;
+ case PIN_MODE_INPUT:
+ /* input setting: not pull. */
+ GPIO_InitStruct.Alternate = GPIO_AF0_INPUT;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ break;
+ case PIN_MODE_INPUT_PULLUP:
+ /* input setting: pull up. */
+ GPIO_InitStruct.Alternate = GPIO_AF0_INPUT;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ break;
+ case PIN_MODE_INPUT_PULLDOWN:
+ /* input setting: pull down. */
+ GPIO_InitStruct.Alternate = GPIO_AF0_INPUT;
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ break;
+ case PIN_MODE_OUTPUT_OD:
+ /* output setting: od. */
+ GPIO_InitStruct.OType = GPIO_OTYPE_OD;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ break;
+
+ default:
+ break;
+ }
+ LL_GPIO_Init(TAE32_PORT_GET(pin), &GPIO_InitStruct);
+}
+
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+ rt_int32_t i;
+ for (i = 0; i < 32; i++)
+ {
+ if (((rt_uint32_t)0x01 << i) == bit)
+ {
+ return i;
+ }
+ }
+ return -1;
+}
+
+rt_inline rt_int32_t gpio_port_index(GPIO_TypeDef *port)
+{
+ rt_uint32_t gpio_port;
+ gpio_port = (rt_uint32_t)port;
+ switch (gpio_port)
+ {
+ case GPIOA_BASE:
+ return 0;
+ case GPIOB_BASE:
+ return 1;
+ case GPIOC_BASE:
+ return 2;
+ case GPIOD_BASE:
+ return 3;
+ case GPIOE_BASE:
+ return 4;
+ case GPIOF_BASE:
+ return 5;
+ }
+ return -1;
+}
+
+static rt_err_t tae32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+ rt_uint8_t mode, void (*hdr)(void *args), void *args)
+{
+ rt_base_t level;
+ rt_int32_t irqPinIndex = -1;
+ rt_int32_t irqPortIndex = -1;
+
+ irqPinIndex = bit2bitno(TAE32_PIN_GET(pin));
+ irqPortIndex = gpio_port_index(TAE32_PORT_GET(pin));
+
+ if (irqPortIndex < 0 || irqPortIndex > PIN_TAEPORT_MAX)
+ {
+ return -RT_ENOSYS;
+ }
+ if (irqPinIndex < 0 || irqPinIndex >= (rt_int32_t)ITEM_NUM(pin_irq_hdr_tab[irqPortIndex].hdr_pin))
+ {
+ return -RT_ENOSYS;
+ }
+
+ level = rt_hw_interrupt_disable();
+ if (pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].pin == pin &&
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].hdr == hdr &&
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].mode == mode &&
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].args == args)
+ {
+ rt_hw_interrupt_enable(level);
+ return RT_EOK;
+ }
+
+ if (pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].pin != -1)
+ {
+ rt_hw_interrupt_enable(level);
+ return -RT_EBUSY;
+ }
+
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].pin = pin;
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].hdr = hdr;
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].mode = mode;
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].args = args;
+ rt_hw_interrupt_enable(level);
+
+ return RT_EOK;
+}
+
+static rt_err_t tae32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
+{
+ rt_base_t level;
+ rt_int32_t irqPinIndex = -1;
+ rt_int32_t irqPortIndex = -1;
+
+ irqPinIndex = bit2bitno(TAE32_PIN_GET(pin));
+ irqPortIndex = gpio_port_index(TAE32_PORT_GET(pin));
+
+ if (irqPortIndex < 0 || irqPortIndex > PIN_TAEPORT_MAX)
+ {
+ return -RT_ENOSYS;
+ }
+ if (irqPinIndex < 0 || irqPinIndex >= (rt_int32_t)ITEM_NUM(pin_irq_hdr_tab[irqPortIndex].hdr_pin))
+ {
+ return -RT_ENOSYS;
+ }
+
+ level = rt_hw_interrupt_disable();
+ if (pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].pin == -1)
+ {
+ rt_hw_interrupt_enable(level);
+ return RT_EOK;
+ }
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].pin = -1;
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].hdr = RT_NULL;
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].mode = 0;
+ pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].args = RT_NULL;
+ rt_hw_interrupt_enable(level);
+
+ return RT_EOK;
+}
+
+static rt_err_t tae32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+ rt_uint8_t enabled)
+{
+ rt_base_t level;
+ rt_uint8_t i;
+ rt_int32_t irqPinIndex = -1;
+ rt_int32_t irqPortIndex = -1;
+
+ GPIO_InitTypeDef GPIO_InitStruct;
+
+ irqPinIndex = bit2bitno(TAE32_PIN_GET(pin));
+ irqPortIndex = gpio_port_index(TAE32_PORT_GET(pin));
+
+ if (PIN_PORT_GET(pin) >= PIN_TAEPORT_MAX)
+ {
+ return -RT_ENOSYS;
+ }
+
+ if (irqPortIndex < 0 || irqPortIndex > (rt_int32_t)ITEM_NUM(pin_irq_hdr_tab))
+ {
+ return -RT_ENOSYS;
+ }
+ if (irqPinIndex < 0 || irqPinIndex >= (rt_int32_t)ITEM_NUM(pin_irq_hdr_tab[irqPortIndex].hdr_pin))
+ {
+ return -RT_ENOSYS;
+ }
+
+
+ if (enabled == PIN_IRQ_ENABLE)
+ {
+
+ level = rt_hw_interrupt_disable();
+
+ if (pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].pin == -1)
+ {
+ rt_hw_interrupt_enable(level);
+ return -RT_ENOSYS;
+ }
+
+ GPIO_InitStruct.Pin = TAE32_PIN_GET(pin);
+ GPIO_InitStruct.Alternate = GPIO_AF0_INPUT;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+ switch (pin_irq_hdr_tab[irqPortIndex].hdr_pin[irqPinIndex].mode)
+ {
+ case PIN_IRQ_MODE_RISING:
+ GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+ GPIO_InitStruct.IntMode = GPIO_INT_MODE_RISING;
+ break;
+ case PIN_IRQ_MODE_FALLING:
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.IntMode = GPIO_INT_MODE_FALLING;
+ break;
+ case PIN_IRQ_MODE_RISING_FALLING:
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.IntMode = GPIO_INT_MODE_RISING_FALLING;
+ break;
+ }
+ LL_GPIO_Init(TAE32_PORT_GET(pin), &GPIO_InitStruct);
+ LL_NVIC_EnableIRQ(pin_irq_hdr_tab[irqPortIndex].irq_port);
+
+ irq_enable_mask[irqPortIndex][irqPinIndex] = RT_TRUE;
+
+ rt_hw_interrupt_enable(level);
+ }
+ else if (enabled == PIN_IRQ_DISABLE)
+ {
+ level = rt_hw_interrupt_disable();
+ LL_GPIO_DeInit(TAE32_PORT_GET(pin), TAE32_PIN_GET(pin));
+
+ irq_enable_mask[irqPortIndex][irqPinIndex] = RT_FALSE;
+ for (i = 0; i < 16; i++)
+ {
+ if (irq_enable_mask[irqPortIndex][i])
+ {
+ break;
+ }
+ }
+ if (i >= 16)
+ {
+ LL_NVIC_DisableIRQ(pin_irq_hdr_tab[irqPortIndex].irq_port);
+ }
+ rt_hw_interrupt_enable(level);
+ }
+ else
+ {
+ return -RT_ENOSYS;
+ }
+
+ return RT_EOK;
+}
+
+static const struct rt_pin_ops tae32_pin_ops =
+{
+ tae32_pin_mode,
+ tae32_pin_write,
+ tae32_pin_read,
+ tae32_pin_attach_irq,
+ tae32_pin_dettach_irq,
+ tae32_pin_irq_enable,
+ tae32_pin_get,
+};
+
+rt_inline void pin_irq_hdr(rt_int32_t irq_port_index, rt_int32_t irq_pin_index)
+{
+ if (pin_irq_hdr_tab[irq_port_index].hdr_pin[irq_pin_index].hdr)
+ {
+ pin_irq_hdr_tab[irq_port_index].hdr_pin[irq_pin_index].hdr(pin_irq_hdr_tab[irq_port_index].hdr_pin[irq_pin_index].args);
+ }
+}
+
+void LL_GPIO_ExtTrigCallback(GPIO_TypeDef *Instance, uint32_t pin)
+{
+ pin_irq_hdr(gpio_port_index(Instance), bit2bitno(pin));
+}
+
+void GPIOA_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ LL_GPIO_IRQHandler(GPIOA);
+ rt_interrupt_leave();
+}
+
+void GPIOB_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ LL_GPIO_IRQHandler(GPIOB);
+ rt_interrupt_leave();
+}
+
+void GPIOC_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ LL_GPIO_IRQHandler(GPIOC);
+ rt_interrupt_leave();
+}
+
+void GPIOD_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ LL_GPIO_IRQHandler(GPIOD);
+ rt_interrupt_leave();
+}
+
+void GPIOE_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ LL_GPIO_IRQHandler(GPIOE);
+ rt_interrupt_leave();
+}
+
+void GPIOF_IRQHandler(void)
+{
+ rt_interrupt_enter();
+ LL_GPIO_IRQHandler(GPIOF);
+ rt_interrupt_leave();
+}
+
+int rt_hw_pin_init(void)
+{
+ int result;
+
+ result = rt_device_pin_register("pin", &tae32_pin_ops, RT_NULL);
+
+ return result;
+}
+
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+#endif /* RT_USING_PIN */
\ No newline at end of file
diff --git a/bsp/tae32/libraries/tae32_drivers/drv_gpio.h b/bsp/tae32/libraries/tae32_drivers/drv_gpio.h
new file mode 100644
index 0000000000..79b7261ae7
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/drv_gpio.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-20 yeml the first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pin_irq_map
+{
+ rt_uint16_t pinbit;
+ IRQn_Type irq_port;
+};
+
+#define __TAE32_PORT(port) GPIO##port##_BASE
+
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__TAE32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x1000UL) )) + PIN)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
diff --git a/bsp/tae32/libraries/tae32_drivers/drv_uart_v2.c b/bsp/tae32/libraries/tae32_drivers/drv_uart_v2.c
new file mode 100644
index 0000000000..980bc7f701
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/drv_uart_v2.c
@@ -0,0 +1,586 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-17 yeml the first version
+ */
+
+#include "drv_uart_v2.h"
+#ifdef RT_USING_SERIAL_V2
+
+#if !defined(BSP_USING_UART0) && \
+ !defined(BSP_USING_UART1) && \
+ !defined(BSP_USING_UART2) && \
+ !defined(BSP_USING_UART3) && \
+ !defined(BSP_USING_UART4)
+ #error "Please define at least one UARTx"
+#endif
+
+enum
+{
+#ifdef BSP_USING_UART0
+ UART0_INDEX,
+#endif
+#ifdef BSP_USING_UART1
+ UART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+ UART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+ UART3_INDEX,
+#endif
+#ifdef BSP_USING_UART4
+ UART4_INDEX,
+#endif
+};
+
+static struct tae32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART0
+ UART0_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART1
+ UART1_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART2
+ UART2_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART3
+ UART3_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART4
+ UART4_CONFIG,
+#endif
+};
+
+static struct tae32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+static void uart_isr(struct rt_serial_device *serial)
+{
+ struct tae32_uart *uart;
+ uint32_t int_en, int_pending;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct tae32_uart, serial);
+
+ // All Interrupt Enalbe and Pending Get
+ int_en = __LL_UART_AllIntEn_Get(uart->Instance);
+ int_pending = __LL_UART_AllIntPnd_Get(uart->Instance);
+ bool rx_9bits_en;
+ // Rx Full Interrupt Handler
+ if ((int_en & UART0_INTEN_RFIE_Msk) && (int_pending & UART0_INT_RXFI_Msk))
+ {
+ // interrupt pending auto clear
+ struct rt_serial_rx_fifo *rx_fifo;
+ rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+ RT_ASSERT(rx_fifo != RT_NULL);
+
+ rx_9bits_en = (bool)(__LL_UART_IsExtBitEn(uart->Instance) && !__LL_UART_IsRxExtAddrMatchMode(uart->Instance) &&
+ (UART_DatLenETypeDef)__LL_UART_DatLen_Get(uart->Instance) >= UART_DAT_LEN_8b);
+
+ if (rx_9bits_en)
+ {
+ rt_ringbuffer_putchar(&(rx_fifo->rb), __LL_UART_RxDat9bits_Read(uart->Instance));
+ }
+ else
+ {
+ rt_ringbuffer_putchar(&(rx_fifo->rb), __LL_UART_RxDat8bits_Read(uart->Instance));
+ }
+
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+ }
+ // Tx Empty Interrupt Handler
+ else if ((int_en & UART0_INTEN_TEIE_Msk) && (int_pending & UART0_INT_TXEI_Msk))
+ {
+ struct rt_serial_tx_fifo *tx_fifo;
+ tx_fifo = (struct rt_serial_tx_fifo *)serial->serial_tx;
+ RT_ASSERT(tx_fifo != RT_NULL);
+
+ rt_uint8_t put_char = 0;
+ if (rt_ringbuffer_getchar(&(tx_fifo->rb), &put_char))
+ {
+ __LL_UART_TxDat9bits_Write(uart->Instance, put_char);
+ }
+ else
+ {
+ __LL_UART_TxEmpty_INT_Dis(uart->Instance);
+ __LL_UART_TxDone_INT_En(uart->Instance);
+ }
+ }
+ // Tx Done Interrupt Handler
+ else if ((int_en & UART0_INTEN_TDIE_Msk) && (int_pending & UART0_INT_TDIF_Msk))
+ {
+
+ __LL_UART_TxDone_INT_Dis(uart->Instance);
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
+ __LL_UART_TxDoneIntPnd_Clr(uart->Instance);
+ }
+}
+
+#if defined(BSP_USING_UART0)
+
+void UART0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART0_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UART1)
+void UART1_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART1_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UART2)
+void UART2_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART2_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UART3)
+void UART3_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART3_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UART4)
+void UART4_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ uart_isr(&(uart_obj[UART4_INDEX].serial));
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif
+
+static const UART_LLCfgTypeDef uart_ll_cfg_def = {
+ .tx_rx_swap_en = false,
+ .rx_timeout_en = false,
+ .one_wire_en = false,
+ .tx_pol = UART_PIN_POL_INACT_HIGH,
+ .rx_pol = UART_PIN_POL_INACT_HIGH,
+ .bit_order = UART_BIT_ORDER_LSB,
+ .tx_fifo_empty_thres = 0, // 0~15
+ .rx_fifo_full_thres = 1, // 1~16
+ .rx_timeout = 0,
+ .rx_timeout_mode = UART_RTO_MODE_FNE_RXIDEL,
+};
+
+
+LL_StatusETypeDef ll_uart_Init(UART_TypeDef *Instance, UART_InitTypeDef *init)
+{
+ uint32_t baud_rate = 1;
+ UART_LLCfgTypeDef *ll_cfg;
+ UART_HandleTypeDef *uart_hdl;
+
+ assert_param(IS_UART_ALL_INSTANCE(Instance));
+ assert_param(init != NULL);
+ assert_param(init->baudrate);
+
+ if (!IS_UART_ALL_INSTANCE(Instance) || init == NULL || !init->baudrate) {
+ return LL_INVALID;
+ }
+
+ /* It must disable the UART while configuring certain registers */
+ __LL_UART_Dis(Instance);
+
+ LL_FUNC_ALTER(init->ll_cfg == NULL, ll_cfg = (UART_LLCfgTypeDef *)&uart_ll_cfg_def, ll_cfg = init->ll_cfg);
+
+ /* init the low level hardware eg. Clock, NVIC */
+ LL_UART_MspInit(Instance);
+
+ /* Reset UART FIFO */
+ __LL_UART_TxFIFO_Reset(Instance);
+ __LL_UART_RxFIFO_Reset(Instance);
+
+ __LL_UART_TxPinPol_Set(Instance, ll_cfg->tx_pol);
+ __LL_UART_RxPinPol_Set(Instance, ll_cfg->rx_pol);
+ __LL_UART_BitOrder_Set(Instance, ll_cfg->bit_order);
+ __LL_UART_RxFIFOFullThres_Set(Instance, ll_cfg->rx_fifo_full_thres);
+ __LL_UART_TxFIFOEmptyThres_Set(Instance, ll_cfg->tx_fifo_empty_thres);
+ __LL_UART_RxTimeoutTime_Set(Instance, ll_cfg->rx_timeout);
+ LL_FUNC_ALTER(ll_cfg->tx_rx_swap_en, __LL_UART_TxRxPinSwap_En(Instance), __LL_UART_TxRxPinSwap_Dis(Instance));
+ LL_FUNC_ALTER(ll_cfg->one_wire_en, __LL_UART_OneWire_En(Instance), __LL_UART_OneWire_Dis(Instance));
+ LL_FUNC_ALTER(ll_cfg->rx_timeout_en, __LL_UART_RxTimeout_En(Instance), __LL_UART_RxTimeout_Dis(Instance));
+
+ if ((__LL_SYSCTRL_ChipDCN_Get(SYSCTRL) >= 3) && (LL_IsExtCfgEnGrp(LL_EXT_CFG_GRP_MASK_UART))) {
+ __LL_UART_RTOMode_Set(Instance, ll_cfg->rx_timeout_mode);
+ }
+
+ if (init->parity == UART_PARITY_NO) {
+ __LL_UART_Parity_Dis(Instance);
+ } else {
+ __LL_UART_Parity_En(Instance);
+ __LL_UART_Parity_Set(Instance, init->parity);
+ }
+
+ __LL_UART_StopLen_Set(Instance, init->stop_len);
+ __LL_UART_DatLen_Set(Instance, init->dat_len);
+
+ if (init->ext_bit_en) {
+ __LL_UART_ExtBit_En(Instance);
+
+ __LL_UART_RxExtMode_Set(Instance, init->rx_ext_mode);
+ __LL_UART_RxExtAddr_Set(Instance, init->rx_addr_ext);
+ } else {
+ __LL_UART_ExtBit_Dis(Instance);
+ }
+
+ /* Baudrate Config */
+ if (Instance == UART0 || Instance == UART1 || Instance == UART2) {
+ baud_rate = (LL_RCU_APB0ClkGet() + init->baudrate / 2) / init->baudrate;
+ } else if (Instance == UART3 || Instance == UART4) {
+ baud_rate = (LL_RCU_APB1ClkGet() + init->baudrate / 2) / init->baudrate;
+ }
+
+ __LL_UART_Baudrate_Set(Instance, baud_rate);
+ __LL_UART_OverSampleMode_Set(Instance, init->over_samp);
+
+ __LL_UART_AllIntPnd_Clr(Instance);
+
+ __LL_UART_Tx_En(Instance);
+ __LL_UART_Rx_En(Instance);
+
+ __LL_UART_En(Instance);
+
+ return LL_OK;
+}
+
+
+static rt_err_t tae32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+ struct tae32_uart *uart;
+ UART_InitTypeDef uart_init;
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(cfg != RT_NULL);
+
+ rt_memset(&uart_init, 0, sizeof(uart_init));
+
+ uart = rt_container_of(serial, struct tae32_uart, serial);
+ uart_init.baudrate = cfg->baud_rate;
+
+#ifdef BSP_UART_USING_OVER_SAMP16X
+ uart_init.over_samp = UART_OVER_SAMP_16X;
+#else
+ uart_init.over_samp = UART_OVER_SAMP_8X;
+#endif
+ switch (cfg->data_bits)
+ {
+ case DATA_BITS_5:
+ uart_init.dat_len = UART_DAT_LEN_5b;
+ break;
+ case DATA_BITS_6:
+ uart_init.dat_len = UART_DAT_LEN_6b;
+ break;
+ case DATA_BITS_7:
+ uart_init.dat_len = UART_DAT_LEN_7b;
+ break;
+ case DATA_BITS_8:
+ uart_init.dat_len = UART_DAT_LEN_8b;
+ break;
+ default:
+ uart_init.dat_len = UART_DAT_LEN_8b;
+ break;
+ }
+ switch (cfg->stop_bits)
+ {
+ case STOP_BITS_1:
+ uart_init.stop_len = UART_STOP_LEN_1b;
+ break;
+ case STOP_BITS_2:
+ uart_init.stop_len = UART_STOP_LEN_2b;
+ break;
+ default:
+ uart_init.stop_len = UART_STOP_LEN_1b;
+ break;
+ }
+
+ switch (cfg->parity)
+ {
+ case PARITY_NONE:
+ uart_init.parity = UART_PARITY_NO;
+ break;
+ case PARITY_ODD:
+ uart_init.parity = UART_PARITY_ODD;
+ break;
+ case PARITY_EVEN:
+ uart_init.parity = UART_PARITY_EVEN;
+ break;
+ default:
+ uart_init.parity = UART_PARITY_NO;
+ break;
+ }
+ if (ll_uart_Init(uart->Instance, &uart_init) != LL_OK)
+ {
+ return -RT_ERROR;
+ }
+ return RT_EOK;
+}
+
+
+static rt_err_t tae32_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+ struct tae32_uart *uart;
+ rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct tae32_uart, serial);
+
+ if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
+ {
+ if (uart->dma_flag & RT_DEVICE_FLAG_DMA_RX)
+ ctrl_arg = RT_DEVICE_FLAG_DMA_RX;
+ else
+ ctrl_arg = RT_DEVICE_FLAG_INT_RX;
+ }
+ else if (ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
+ {
+ if (uart->dma_flag & RT_DEVICE_FLAG_DMA_TX)
+ ctrl_arg = RT_DEVICE_FLAG_DMA_TX;
+ else
+ ctrl_arg = RT_DEVICE_FLAG_INT_TX;
+ }
+
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_CLR_INT:
+ /* disable rx irq */
+ NVIC_DisableIRQ(uart->config->irq_type);
+
+ /* disable interrupt */
+ if (ctrl_arg == RT_DEVICE_FLAG_INT_RX)
+ {
+ __LL_UART_RxFull_INT_Dis(uart->Instance);
+ }
+ else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX)
+ {
+ __LL_UART_TxEmpty_INT_Dis(uart->Instance);
+ }
+ break;
+
+ case RT_DEVICE_CTRL_SET_INT:
+ /* enable rx irq */
+ NVIC_EnableIRQ(uart->config->irq_type);
+
+ /* enable interrupt */
+ if (ctrl_arg == RT_DEVICE_FLAG_INT_RX)
+ {
+ __LL_UART_RxFIFO_Reset(uart->Instance);
+ __LL_UART_RxFull_INT_En(uart->Instance);
+ }
+ else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX)
+ {
+ __LL_UART_TxFIFO_Reset(uart->Instance);
+ __LL_UART_TxDoneIntPnd_Clr(uart->Instance);
+ __LL_UART_TxEmpty_INT_En(uart->Instance);
+ __LL_UART_TxDone_INT_En(uart->Instance);
+ }
+ break;
+
+ case RT_DEVICE_CTRL_CONFIG:
+ if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX))
+ {
+#ifdef RT_SERIAL_USING_DMA
+ ;
+#endif
+ }
+ else
+ {
+ tae32_uart_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg);
+ }
+ break;
+
+ case RT_DEVICE_CHECK_OPTMODE:
+ if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX)
+ return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
+ else
+ return RT_SERIAL_TX_BLOCKING_BUFFER;
+
+ case RT_DEVICE_CTRL_CLOSE:
+ LL_UART_DeInit(uart->Instance);
+ break;
+ }
+
+ return RT_EOK;
+}
+
+int tae32_uart_putc(struct rt_serial_device *serial, char ch)
+{
+ struct tae32_uart *uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct tae32_uart, serial);
+ __LL_UART_TxDoneIntPnd_Clr(uart->Instance);
+ __LL_UART_TxDat9bits_Write(uart->Instance, ch);
+ while (!__LL_UART_IsTxDoneIntPnd(uart->Instance))
+ ;
+ return RT_EOK;
+}
+
+int tae32_uart_getc(struct rt_serial_device *serial)
+{
+ int ch;
+ struct tae32_uart *uart;
+ bool rx_9bits_en;
+ RT_ASSERT(serial != RT_NULL);
+ uart = rt_container_of(serial, struct tae32_uart, serial);
+
+ ch = -1;
+ rx_9bits_en = (bool)(__LL_UART_IsExtBitEn(uart->Instance) && !__LL_UART_IsRxExtAddrMatchMode(uart->Instance) &&
+ (UART_DatLenETypeDef)__LL_UART_DatLen_Get(uart->Instance) >= UART_DAT_LEN_8b);
+
+ if (!(__LL_UART_IsRxFIFOEmpty(uart->Instance)))
+ {
+ if (rx_9bits_en)
+ {
+ ch = (uint16_t)(__LL_UART_RxDat9bits_Read(uart->Instance));
+ }
+ else
+ {
+ ch = (uint8_t)(__LL_UART_RxDat8bits_Read(uart->Instance));
+ }
+ }
+ return ch;
+}
+
+rt_ssize_t tae32_uart_transmit(struct rt_serial_device *serial,
+ rt_uint8_t *buf,
+ rt_size_t size,
+ rt_uint32_t tx_flag)
+{
+ struct tae32_uart *uart;
+
+ RT_ASSERT(serial != RT_NULL);
+ RT_ASSERT(buf != RT_NULL);
+ uart = rt_container_of(serial, struct tae32_uart, serial);
+#ifdef RT_SERIAL_USING_DMA
+ if (uart->dma_flag & RT_DEVICE_FLAG_DMA_TX)
+ {
+ /*DMA设置发送*/
+ return size;
+ }
+#endif
+ tae32_uart_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)tx_flag);
+
+ return size;
+}
+
+static void tae32_uart_get_config(void)
+{
+ struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+#ifdef BSP_USING_UART0
+ uart_obj[UART0_INDEX].Instance = UART0;
+ uart_obj[UART0_INDEX].serial.config = config;
+
+ uart_obj[UART0_INDEX].serial.config.rx_bufsz = BSP_UART0_RX_BUFSIZE;
+ uart_obj[UART0_INDEX].serial.config.tx_bufsz = BSP_UART0_TX_BUFSIZE;
+
+#endif
+
+#ifdef BSP_USING_UART1
+ uart_obj[UART1_INDEX].Instance = UART1;
+ uart_obj[UART1_INDEX].serial.config = config;
+
+ uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE;
+ uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE;
+
+#endif
+
+#ifdef BSP_USING_UART2
+ uart_obj[UART2_INDEX].Instance = UART2;
+ uart_obj[UART2_INDEX].serial.config = config;
+
+ uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE;
+ uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE;
+
+#endif
+
+#ifdef BSP_USING_UART3
+ uart_obj[UART3_INDEX].Instance = UART3;
+ uart_obj[UART3_INDEX].serial.config = config;
+
+ uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
+ uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
+
+#endif
+
+#ifdef BSP_USING_UART4
+ uart_obj[UART4_INDEX].Instance = UART4;
+ uart_obj[UART4_INDEX].serial.config = config;
+
+ uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
+ uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
+
+#endif
+}
+
+static const struct rt_uart_ops tae32_uart_ops =
+{
+ .configure = tae32_uart_configure,
+ .control = tae32_uart_control,
+ .putc = tae32_uart_putc,
+ .getc = tae32_uart_getc,
+ .transmit = tae32_uart_transmit
+};
+
+int rt_hw_usart_init(void)
+{
+ rt_err_t result = 0;
+ rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct tae32_uart);
+
+ tae32_uart_get_config();
+ for (int i = 0; i < obj_num; i++)
+ {
+ /* init UART object */
+ uart_obj[i].config = &uart_config[i];
+ uart_obj[i].serial.ops = &tae32_uart_ops;
+ /* register UART device */
+ result = rt_hw_serial_register(&uart_obj[i].serial,
+ uart_obj[i].config->name,
+ RT_DEVICE_FLAG_RDWR,
+ NULL);
+ RT_ASSERT(result == RT_EOK);
+ }
+
+ return result;
+}
+
+#endif
diff --git a/bsp/tae32/libraries/tae32_drivers/drv_uart_v2.h b/bsp/tae32/libraries/tae32_drivers/drv_uart_v2.h
new file mode 100644
index 0000000000..a9f48a6d97
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/drv_uart_v2.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-17 yeml the first version
+ */
+
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+
+#include
+#include
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#ifdef SOC_SERIES_TAE32G58xx
+#include "tae32g58xx_ll_uart.h"
+#include "config/g58xx/uart_config.h"
+#endif
+
+/*tae32_uart_config*/
+struct tae32_uart_config
+{
+ const char *name;
+ IRQn_Type irq_type;
+};
+
+/* tae32 uart dirver class */
+struct tae32_uart
+{
+ struct rt_serial_device serial;
+
+ UART_TypeDef *Instance;
+ struct tae32_uart_config *config;
+ rt_uint16_t dma_flag;
+};
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
diff --git a/bsp/tae32/libraries/tae32_drivers/drv_wdt.c b/bsp/tae32/libraries/tae32_drivers/drv_wdt.c
new file mode 100644
index 0000000000..3d91a6f7b0
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/drv_wdt.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-22 yeml the first version
+ */
+
+#include "drv_wdt.h"
+
+#ifdef RT_USING_WDT
+
+#define DBG_TAG "WDT"
+#define DBG_LVL DBG_ERROR
+#include "dbg/tae_dbg.h"
+
+static struct tae32_wdt tae32_wdt_obj;
+
+static rt_err_t tae32_wdt_init(rt_watchdog_t *wdt)
+{
+ tae32_wdt_obj.Instance = IWDG;
+ tae32_wdt_obj.is_start = RT_FALSE;
+
+ tae32_wdt_obj.config.reload_val = 0x1FFF;
+ tae32_wdt_obj.config.mode = IWDG_MODE_RESET;
+ tae32_wdt_obj.config.pre_div = IWDG_PRE_DIV_256;
+
+ if (LL_IWDG_Init(tae32_wdt_obj.Instance, &tae32_wdt_obj.config) == LL_OK)
+ {
+ return RT_EOK;
+ }
+ else
+ {
+ return RT_ERROR;
+ }
+}
+
+static rt_err_t tae32_wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+ struct tae32_wdt *ptr_tae32_wdt;
+ float f_temp = 0;
+ ptr_tae32_wdt = rt_container_of(wdt, struct tae32_wdt, watchdog);
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+#if defined(LSI_VALUE)
+ f_temp = (float)tae32_wdt_obj.config.reload_val * 256 / LSI_VALUE;
+ /*Rounding*/
+ if(f_temp + 0.5 > (rt_uint32_t)f_temp + 1)
+ {
+ (*((rt_uint32_t*)arg)) = (rt_uint32_t)f_temp + 1;
+ }
+ else
+ {
+ (*((rt_uint32_t*)arg)) = (rt_uint32_t)f_temp;
+ }
+
+#else
+#error "Please define the value of LSI_VALUE!"
+#endif
+ break;
+
+ case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+#if defined(LSI_VALUE)
+ tae32_wdt_obj.config.reload_val = (*((rt_uint32_t*)arg)) * LSI_VALUE / 256;
+ if (tae32_wdt_obj.config.reload_val > 0x1FFF)
+ {
+ LOG_E("wdg set timeout parameter too large, please less than %ds", 0x1FFF * 256 / LSI_VALUE);
+ return -RT_EINVAL;
+ }
+#else
+#error "Please define the value of LSI_VALUE!"
+#endif
+ if (tae32_wdt_obj.is_start)
+ {
+ if (LL_IWDG_Init(tae32_wdt_obj.Instance, &tae32_wdt_obj.config) != LL_OK)
+ {
+ LOG_E("wdg set timeout failed.");
+ return -RT_ERROR;
+ }
+ }
+ break;
+
+ case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+ LL_IWDG_Refresh(ptr_tae32_wdt->Instance);
+ break;
+
+ case RT_DEVICE_CTRL_WDT_START:
+ if ((LL_IWDG_Init(tae32_wdt_obj.Instance, &tae32_wdt_obj.config) == LL_OK) && \
+ (LL_IWDG_Start(ptr_tae32_wdt->Instance) == LL_OK))
+ {
+ tae32_wdt_obj.is_start = RT_TRUE;
+ }
+ else
+ {
+ LOG_E("wdg start failed.");
+ return -RT_ERROR;
+ }
+ break;
+
+ case RT_DEVICE_CTRL_WDT_STOP:
+ LL_IWDG_Stop(ptr_tae32_wdt->Instance);
+ tae32_wdt_obj.is_start = RT_FALSE;
+ break;
+
+ default:
+ LOG_W("This command is not supported.");
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+
+static const struct rt_watchdog_ops tae32_wdt_ops =
+{
+ .init = tae32_wdt_init,
+ .control = tae32_wdt_control
+};
+
+int rt_hw_wdt_init(void)
+{
+ rt_err_t result = 0;
+
+ tae32_wdt_obj.watchdog.ops = &tae32_wdt_ops;
+ result = rt_hw_watchdog_register(&tae32_wdt_obj.watchdog,
+ "wdt", RT_DEVICE_FLAG_DEACTIVATE,
+ RT_NULL);
+
+ RT_ASSERT(result == RT_EOK);
+ return result;
+}
+INIT_BOARD_EXPORT(rt_hw_wdt_init);
+
+#endif /* RT_USING_WDT */
diff --git a/bsp/tae32/libraries/tae32_drivers/drv_wdt.h b/bsp/tae32/libraries/tae32_drivers/drv_wdt.h
new file mode 100644
index 0000000000..0644ce4a8b
--- /dev/null
+++ b/bsp/tae32/libraries/tae32_drivers/drv_wdt.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-22 yeml the first version
+ */
+
+#ifndef __DRV_WDT_H__
+#define __DRV_WDT_H__
+
+#include
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined SOC_SERIES_TAE32G58xx
+#include "tae32g58xx_ll_iwdg.h"
+#endif
+
+struct tae32_wdt
+{
+ rt_watchdog_t watchdog;
+
+ IWDG_TypeDef *Instance;
+ IWDG_InitTypeDef config;
+ rt_uint16_t is_start;
+};
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/.config b/bsp/tae32/libraries/templates/tae32g58xx/.config
new file mode 100644
index 0000000000..f3cdbb6e38
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/.config
@@ -0,0 +1,1265 @@
+CONFIG_SOC_TAE325800=y
+CONFIG_BOARD_TAE32G5800_EVAL=y
+
+#
+# RT-Thread Kernel
+#
+
+#
+# klibc options
+#
+
+#
+# rt_vsnprintf options
+#
+# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set
+# end of rt_vsnprintf options
+
+#
+# rt_vsscanf options
+#
+# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set
+# end of rt_vsscanf options
+
+#
+# rt_memset options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set
+# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set
+# end of rt_memset options
+
+#
+# rt_memcpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set
+# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set
+# end of rt_memcpy options
+
+#
+# rt_memmove options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set
+# end of rt_memmove options
+
+#
+# rt_memcmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set
+# end of rt_memcmp options
+
+#
+# rt_strstr options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set
+# end of rt_strstr options
+
+#
+# rt_strcasecmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set
+# end of rt_strcasecmp options
+
+#
+# rt_strncpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set
+# end of rt_strncpy options
+
+#
+# rt_strcpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set
+# end of rt_strcpy options
+
+#
+# rt_strncmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set
+# end of rt_strncmp options
+
+#
+# rt_strcmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set
+# end of rt_strcmp options
+
+#
+# rt_strlen options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set
+# end of rt_strlen options
+
+#
+# rt_strnlen options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
+# end of rt_strnlen options
+
+# CONFIG_RT_UTEST_TC_USING_KLIBC is not set
+# end of klibc options
+
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
+
+#
+# kservice options
+#
+# CONFIG_RT_USING_TINY_FFS is not set
+# end of kservice options
+
+CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_ASSERT=y
+CONFIG_RT_DEBUGING_COLOR=y
+CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
+# CONFIG_RT_USING_CI_ACTION is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
+
+#
+# Memory Management
+#
+# CONFIG_RT_USING_MEMPOOL is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+# CONFIG_RT_USING_CONSOLE is not set
+CONFIG_RT_VER_NUM=0x50200
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# end of RT-Thread Kernel
+
+CONFIG_RT_USING_HW_ATOMIC=y
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M4=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+
+#
+# DFS: device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# end of DFS: device virtual file system
+
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+# CONFIG_RT_USING_SERIAL_BYPASS is not set
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PHY_V2 is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_BLK is not set
+# CONFIG_RT_USING_VIRTIO is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_KTIME is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CHERRYUSB is not set
+# end of Device Drivers
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+# end of Timezone and Daylight Saving Time
+# end of ISO-ANSI C layer
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
+# CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+# end of Network
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+# end of Memory protection
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Using USB legacy version
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB legacy version
+
+# CONFIG_RT_USING_FDT is not set
+# end of RT-Thread Components
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# end of CYW43012 WiFi
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+# end of BL808 WiFi
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# end of CYW43439 WiFi
+# end of Wi-Fi
+
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
+# CONFIG_PKG_USING_QMODBUS is not set
+# end of IoT - internet of things
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+# end of multimedia packages
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_RT_TRACE is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+# end of tools packages
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+# end of enhanced kernel services
+
+# CONFIG_PKG_USING_AUNITY is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
+# end of system packages
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# end of STM32 HAL & SDK Drivers
+
+#
+# Infineon HAL Packages
+#
+# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
+# CONFIG_PKG_USING_INFINEON_CMSIS is not set
+# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
+# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
+# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
+# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
+# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
+# CONFIG_PKG_USING_INFINEON_USBDEV is not set
+# end of Infineon HAL Packages
+
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# end of HAL & SDK Drivers
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+# end of sensors drivers
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# end of touch drivers
+
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+# end of peripheral libraries and drivers
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
+# end of AI packages
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_APID is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+# end of Signal Processing and Control Algorithm Packages
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+# end of project laboratory
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
+# end of entertainment: terminal games and other interesting software packages
+
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+# end of miscellaneous packages
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects and Demos
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
+# end of Sensors
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+# end of Display
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+# end of Timing
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
+# end of Data Processing
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# end of Device Control
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# end of Other
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
+
+#
+# Uncategorized
+#
+# end of Arduino libraries
+# end of RT-Thread online packages
+
+CONFIG_SOC_FAMILY_TAE32=y
+CONFIG_SOC_SERIES_TAE32G58xx=y
+
+#
+# Hardware Drivers Config
+#
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_UART_USING_OVER_SAMP16X is not set
+CONFIG_BSP_UART0_RX_BUFSIZE=64
+CONFIG_BSP_UART0_TX_BUFSIZE=0
+# end of On-chip Peripheral Drivers
+
+#
+# Board extended module Drivers
+#
+# end of Hardware Drivers Config
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/.gitignore b/bsp/tae32/libraries/templates/tae32g58xx/.gitignore
new file mode 100644
index 0000000000..7221bde019
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/.gitignore
@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/Kconfig b/bsp/tae32/libraries/templates/tae32g58xx/Kconfig
new file mode 100644
index 0000000000..a167cc71c2
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/Kconfig
@@ -0,0 +1,27 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../..
+
+PKGS_DIR := packages
+
+config SOC_TAE325800
+ bool
+ select SOC_SERIES_TAE32G58xx
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+config BOARD_TAE32G5800_EVAL
+ bool
+ select BOARD_SERIES_TAE32_AE32G5800_EVAL_100
+ default y
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+
+if !RT_USING_NANO
+rsource "board/Kconfig"
+endif
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/README.md b/bsp/tae32/libraries/templates/tae32g58xx/README.md
new file mode 100644
index 0000000000..59fb59d3dd
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/README.md
@@ -0,0 +1,124 @@
+# BSP README 模板
+
+## 简介
+
+本文档为 xxx 开发板的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+【此处简单介绍一下开发板】
+
+开发板外观如下图所示：
+
+
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：STM32xxx，主频 xxxMHz，xxxKB FLASH ，xxxKB RAM
+- 外部 RAM：型号，xMB
+- 外部 FLASH：型号，xMB
+- 常用外设
+ - LED：x个，DS0（红色，PB1），DS1（绿色，PB0）
+ - 按键：x个，K0（兼具唤醒功能，PA0），K1（PC13）
+- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口等
+- 调试接口，标准 JTAG/SWD
+
+开发板更多详细信息请参考【厂商名】 [xxx开发板介绍](https://xxx)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设** | **支持情况** | **备注** |
+| :----------------- | :----------: | :------------------------------------- |
+| USB 转串口 | 支持 | |
+| SPI Flash | 支持 | |
+| 以太网 | 支持 | |
+| SD卡 | 暂不支持 | |
+| CAN | 暂不支持 | |
+| **片上外设** | **支持情况** | **备注** |
+| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
+| UART | 支持 | UART1/x/x |
+| SPI | 支持 | SPI1/x/x |
+| I2C | 支持 | 软件 I2C |
+| SDIO | 暂不支持 | 即将支持 |
+| RTC | 暂不支持 | 即将支持 |
+| PWM | 暂不支持 | 即将支持 |
+| USB Device | 暂不支持 | 即将支持 |
+| USB Host | 暂不支持 | 即将支持 |
+| IWG | 暂不支持 | 即将支持 |
+| xxx | 暂不支持 | 即将支持 |
+| **扩展模块** | **支持情况** | **备注** |
+| xxx 模块 | 支持 | |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 xxx 仿真器下载程序，在通过 xxx 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，【这里写开发板运行起来之后的现象，如：LED 闪烁等】。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 3.1.1 build Nov 19 2018
+ 2006 - 2018 Copyright by rt-thread team
+msh >
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+- xxx
+
+## 联系人信息
+
+维护人:
+
+- [xxx](https://个人主页), 邮箱：
\ No newline at end of file
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/SConscript b/bsp/tae32/libraries/templates/tae32g58xx/SConscript
new file mode 100644
index 0000000000..20f7689c53
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/SConstruct b/bsp/tae32/libraries/templates/tae32g58xx/SConstruct
new file mode 100644
index 0000000000..638b826656
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/SConstruct
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+ env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+tae32_library = 'TAE32G58xx_Firmware_Library'
+tae32_drivers = 'tae32_drivers'
+rtconfig.BSP_LIBRARY_TYPE = tae32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, tae32_library, 'SConscript')))
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, tae32_drivers, 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/applications/SConscript b/bsp/tae32/libraries/templates/tae32g58xx/applications/SConscript
new file mode 100644
index 0000000000..9bb9abae89
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/applications/SConscript
@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+ if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+ group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/applications/main.c b/bsp/tae32/libraries/templates/tae32g58xx/applications/main.c
new file mode 100644
index 0000000000..48b2d19afa
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/applications/main.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-13 yeml first version
+ */
+
+#include
+#include
+#include
+
+/* defined the LED0 pin: PB1 */
+//#define LED0_PIN GET_PIN(B, 1)
+
+int main(void)
+{
+ LL_GPIO_AF_Config(GPIOB, GPIO_PIN_4, GPIO_AF1_OUTPUT);
+ while (1)
+ {
+ LL_GPIO_TogglePin(GPIOB,GPIO_PIN_4);
+ rt_thread_mdelay(50);
+ }
+
+ return RT_EOK;
+}
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/applications/main.h b/bsp/tae32/libraries/templates/tae32g58xx/applications/main.h
new file mode 100644
index 0000000000..7a5f5f2d48
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/applications/main.h
@@ -0,0 +1,69 @@
+/**
+ ******************************************************************************
+ * @file main.h
+ * @author MCD Application Team
+ * @brief Header for main.c module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+
+
+/** @addtogroup TAE32G58xx_Examples
+ * @{
+ */
+
+/** @addtogroup TAE32G58xx_Template
+ * @{
+ */
+
+
+/* Exported Constants --------------------------------------------------------*/
+/* Exported Macros -----------------------------------------------------------*/
+/* Exported Types ------------------------------------------------------------*/
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _MAIN_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/board/Kconfig b/bsp/tae32/libraries/templates/tae32g58xx/board/Kconfig
new file mode 100644
index 0000000000..02bdefa97e
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/board/Kconfig
@@ -0,0 +1,40 @@
+menu "Hardware Drivers Config"
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default y
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_UART0
+ bool "Enable UART0"
+ default y
+
+ config BSP_UART_USING_OVER_SAMP16X
+ bool "Enable UART0 OVER_SAMP16X"
+ depends on BSP_USING_UART0
+ default n
+
+ config BSP_UART0_RX_BUFSIZE
+ int "Set UART0 RX buffer size"
+ range 64 65535
+ depends on BSP_USING_UART0 && RT_USING_SERIAL_V2
+ default 64
+
+ config BSP_UART0_TX_BUFSIZE
+ int "Set UART0 TX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART0 && RT_USING_SERIAL_V2
+ default 0
+ endif
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/board/SConscript b/bsp/tae32/libraries/templates/tae32g58xx/board/SConscript
new file mode 100644
index 0000000000..8ba9ed64d1
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/board/SConscript
@@ -0,0 +1,29 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+tae32g58xx_ll_msp.c
+''')
+
+path = [cwd]
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['gcc']:
+ src += [startup_path_prefix + '/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/startup_tae32g58xx.c']
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+ src += [startup_path_prefix + '/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/startup_tae32g58xx.c']
+elif rtconfig.PLATFORM in ['iccarm']:
+ src += [startup_path_prefix + '/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/startup_tae32g58xx.c']
+
+CPPDEFINES = ['TAE32G5800']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/board/board.c b/bsp/tae32/libraries/templates/tae32g58xx/board/board.c
new file mode 100644
index 0000000000..c9f7437434
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/board/board.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-12 yeml first version
+ */
+
+ #include "board.h"
+
+ void SystemClock_Config(void)
+ {
+ LL_StatusETypeDef ret;
+ RCU_SysclkUserCfgTypeDef sysclk_cfg;
+
+ //SYSCLK Clock Config
+ sysclk_cfg.sysclk_src = SYSCLK_SRC_PLL0DivClk;
+ sysclk_cfg.sysclk_freq = 180000000UL;
+ sysclk_cfg.pll0clk_src = PLLCLK_SRC_HSE;
+ sysclk_cfg.pll0clk_src_freq = HSE_VALUE;
+ sysclk_cfg.apb0_clk_div = RCU_CLK_DIV_2;
+ sysclk_cfg.apb1_clk_div = RCU_CLK_DIV_2;
+ sysclk_cfg.ahb_clk_div = RCU_CLK_DIV_1;
+ ret = LL_RCU_SysclkInit(RCU, &sysclk_cfg);
+
+ if (ret == LL_OK) {
+ SystemCoreClockUpdate(sysclk_cfg.sysclk_freq);
+ }
+
+ if (ret == LL_OK) {
+ LL_RCU_USB_ClkCfg(RCU_CLK_SRC_PLL0, RCU_CLK_DIV_6);
+ }
+ }
+
+ /**
+ * This is the timer interrupt service routine.
+ *
+ */
+ void SysTick_Handler(void)
+ {
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+ }
+
+ /**
+ * This function will initial TAE32 board.
+ */
+void rt_hw_board_init()
+{
+ #ifdef BSP_SCB_ENABLE_I_CACHE
+ /* Enable I-Cache---------------------------------------------------------*/
+ SCB_EnableICache();
+ #endif
+
+ #ifdef BSP_SCB_ENABLE_D_CACHE
+ /* Enable D-Cache---------------------------------------------------------*/
+ SCB_EnableDCache();
+ #endif
+ /* System Clock Update */
+ SystemClock_Config();
+
+ /* System Tick Configuration */
+ LL_Init();
+ #if defined(RT_USING_HEAP)
+ /* Heap initialization */
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+ #endif
+
+ #ifdef RT_USING_PIN
+ rt_hw_pin_init();
+ #endif
+
+ #ifdef RT_USING_SERIAL
+ rt_hw_usart_init();
+ #endif
+
+ #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+ /* Set the shell console output device */
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+ #endif
+
+ #if defined(RT_USING_CONSOLE) && defined(RT_USING_NANO)
+ extern void rt_hw_console_init(void);
+ rt_hw_console_init();
+ #endif
+
+ #ifdef RT_USING_COMPONENTS_INIT
+ /* Board underlying hardware initialization */
+ rt_components_board_init();
+ #endif
+ }
\ No newline at end of file
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/board/board.h b/bsp/tae32/libraries/templates/tae32g58xx/board/board.h
new file mode 100644
index 0000000000..bd5e1bc90a
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/board/board.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-12 yeml first version
+ */
+
+ #ifndef __BOARD_H__
+ #define __BOARD_H__
+
+ #include
+ #include "tae32g58xx_ll.h"
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+#define TAE32_FLASH_START_ADRESS ((uint32_t)0x08000000)
+#define TAE32_FLASH_SIZE (EFLASH_SECTOR_NUM_256_S * EFLASH_SECTOR_SIZE_256_S)
+#define TAE32_FLASH_END_ADDRESS ((uint32_t)(TAE32_FLASH_START_ADRESS + TAE32_FLASH_SIZE))
+
+#define TAE32_SRAM_SIZE 128
+#define TAE32_SRAM_END (0x20000000 + TAE32_SRAM_SIZE * 1024)
+
+#if defined(__ARMCC_VERSION)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN (&__bss_end)
+#endif
+
+#define HEAP_END TAE32_SRAM_END
+
+ void SystemClock_Config(void);
+ int rt_hw_usart_init(void);
+ #ifdef __cplusplus
+ }
+ #endif
+
+ #endif
+
+
\ No newline at end of file
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/board/dbg/tae_dbg.h b/bsp/tae32/libraries/templates/tae32g58xx/board/dbg/tae_dbg.h
new file mode 100644
index 0000000000..c95941acc2
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/board/dbg/tae_dbg.h
@@ -0,0 +1,254 @@
+/**
+ ******************************************************************************
+ * @file tae_dbg.h
+ * @author MCD Application Team
+ * @brief The macro definitions for dbg
+ *
+ ==============================================================================
+ ##### How to use #####
+ ==============================================================================
+ *
+ * If you want to use debug macro, you can use as following steps:
+ *
+ * Step 1: Macros in "tae_dbg_conf.h"
+ * a. Define the TAE_USING_DBG to enable the feature
+ * #define TAE_USING_DBG
+ *
+ * b. Define the print interface for dbg
+ * #define TAE_DBG_PRINT(...) printf(__VA_ARGS__)
+ *
+ * c. Other optional macros define, such as TAE_USING_DBG_COLOR
+ *
+ * Step 2: Macros in your C/C++ file
+ * a. Define the debug tag and level for dbg. If you did not define this,
+ default definition will be used.
+ * #define DBG_TAG "TAG" // must be string
+ * #define DBG_LVL DBG_INFO // others DBG_ERROR, DBG_WARNING, DBG_LOG.
+ * DBG_LOG > DBG_INFO > DBG_WARNING > DBG_ERROR
+ *
+ * b. Include this header file
+ * #include "tae_dbg.h" // this must after of DBG_LVL, DBG_TAG or other options
+ *
+ * Step 3: LOG_X macro to print out logs in your C/C++ file
+ * PLEASE NOTE: LOG_X is related to the DBG_LVL that defined in Step 2. Using LOG_X
+ * witch higher then DBG_LVL will be ignored.
+ * LOG_D("this is a debug log!");
+ * LOG_I("this is a info log!")
+ * LOG_W("this is a warning log!")
+ * LOG_E("this is a error log!");
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+
+
+/** @addtogroup TAE_Utilities
+ * @{
+ */
+
+/** @defgroup TAE_Debug_Template TAE Debug Template
+ * @brief TAE Debug Template
+ * @{
+ */
+
+
+/* Exported Types ------------------------------------------------------------*/
+/* Exported Constants --------------------------------------------------------*/
+/** @defgroup TAE_Debug_Template_Exported_Constants TAE Debug Template Exported Constants
+ * @brief TAE Debug Template Exported Constants
+ * @{
+ */
+
+/**
+ * @brief Define TAE_USING_DBG to enable dbg
+ */
+#define TAE_USING_DBG
+
+/**
+ * @brief Define TAE_USING_DBG_COLOR to enable dbg color mode
+ */
+#define TAE_USING_DBG_COLOR
+
+/**
+ * @}
+ */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup TAE_Debug_Template_Exported_Macros TAE Debug Template Exported Macros
+ * @brief TAE Debug Template Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Define your own print interface here
+ */
+#ifdef TAE_USING_DBG
+#define TAE_DBG_PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define TAE_DBG_PRINT(fmt, ...)
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE_DBG_CONF_TEMPLATE_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/board/dbg/user_debug.c b/bsp/tae32/libraries/templates/tae32g58xx/board/dbg/user_debug.c
new file mode 100644
index 0000000000..7f3a270a82
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/board/dbg/user_debug.c
@@ -0,0 +1,464 @@
+/**
+ ******************************************************************************
+ * @file user_debug.c
+ * @author MCD Application Team
+ * @brief This file provides the Debug User Config Method.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+#include
+#include "dbg/user_debug.h"
+
+
+/** @defgroup TAE_Utilities TAE Utilities
+ * @brief TAE Utilities
+ * @{
+ */
+
+/** @defgroup User_Debug User Debug
+ * @brief User Debug
+ * @{
+ */
+
+
+/* Private Constants ---------------------------------------------------------*/
+/** @defgroup User_Debug_Private_Constants User Debug Private Constants
+ * @brief User Debug Private Constants
+ * @{
+ */
+
+/**
+ * @brief C lib stdio.h putchar/getchar interface retarget
+ * @note With GCC/RAISONANCE, small DBG_NOR (option LD Linker->Libraries->Small DBG_NOR set to 'Yes') calls these functions
+ */
+#if defined (__CC_ARM) /*!< AC5 Compiler */
+
+ #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
+ #define GETCHAR_PROTOTYPE int fgetc(FILE *f)
+
+#elif defined (__ICCARM__) /*!< IAR Compiler */
+
+ #define PUTCHAR_PROTOTYPE int putchar(int ch)
+ #define GETCHAR_PROTOTYPE int getchar(void)
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /*!< AC6 Compiler */
+
+ #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
+ #define GETCHAR_PROTOTYPE int fgetc(FILE *f)
+
+#elif defined (__GNUC__) /*!< GCC Compiler */
+
+ #define PUTCHAR_PROTOTYPE int _write(int fd, char *pBuffer, int size)
+ #define GETCHAR_PROTOTYPE int _read(int fd, char *pBuffer, int size)
+
+#else
+
+ #error "Not supported compiler type"
+
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Private Types -------------------------------------------------------------*/
+/** @defgroup User_Debug_Private_Types User Debug Private Types
+ * @brief User Debug Private Types
+ * @{
+ */
+
+/**
+ * @brief C lib stdio.h __FILE struct definition for KEIL Compiler
+ */
+#if defined(__CC_ARM)
+#pragma import(__use_no_semihosting_swi)
+struct __FILE {
+ int handle;
+ /* Add whatever you need here */
+};
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Private Variables ---------------------------------------------------------*/
+/** @defgroup User_Debug_Private_Variables User Debug Private Variables
+ * @brief User Debug Private Variables
+ * @{
+ */
+
+#if defined(__CC_ARM) || defined(__ICCARM__) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ /**
+ * @brief C lib stdio.h __stdout FILE stream definition
+ */
+ FILE __stdout;
+
+ /**
+ * @brief C lib stdio.h __stdin FILE stream definition
+ */
+ FILE __stdin;
+
+ /**
+ * @brief C lib stdio.h __stderr FILE stream definition
+ */
+ //FILE __stderr;
+#endif
+
+/**
+ * @brief user debug interface
+ */
+USER_DBG_IfcETypeDef user_dbg_ifc;
+
+/**
+ * @brief user debug ITM Rx buffer
+ */
+volatile int32_t ITM_RxBuffer;
+
+#ifdef LL_UART_MODULE_ENABLED
+ /**
+ * @brief user debug uart instance
+ */
+ UART_TypeDef *user_dbg_uart_ins;
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------*/
+/* Private Function Prototypes -----------------------------------------------*/
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+/** @defgroup User_Debug_Exported_Functions User Debug Exported Functions
+ * @brief User Debug Exported Functions
+ * @{
+ */
+
+/**
+ * @brief User Debug Init
+ * @note Remember to implement the LL_UART_MspInit interface in the user file if use UART as debug interface
+ * @param ifc User debug interface
+ * @return LL Status
+ */
+LL_StatusETypeDef User_Debug_Init(USER_DBG_IfcETypeDef ifc)
+{
+ LL_StatusETypeDef ret = LL_FAILED;
+
+ //Check ifc to be Valid
+ if (ifc == USER_DBG_IFC_NO) {
+ user_dbg_ifc = USER_DBG_IFC_NO;
+ user_dbg_uart_ins = NULL;
+ return LL_OK;
+ }
+
+ //User Debug Interface Init
+ if (ifc == USER_DBG_IFC_ITM) {
+#ifdef LL_GPIO_MODULE_ENABLED
+ //SWO GPIO Init: PB3
+ GPIO_InitTypeDef swo_init;
+ swo_init.Pin = GPIO_PIN_3;
+ swo_init.IntMode = GPIO_INT_MODE_CLOSE;
+ swo_init.OType = GPIO_OTYPE_PP;
+ swo_init.Pull = GPIO_NOPULL;
+ swo_init.Speed = GPIO_SPEED_FREQ_LOW;
+ swo_init.Alternate = GPIO_AF2_SWO;
+ ret = LL_GPIO_Init(GPIOB, &swo_init);
+
+ if (ret == LL_OK) {
+ user_dbg_ifc = ifc;
+ }
+
+#endif
+
+ } else {
+
+#ifdef LL_UART_MODULE_ENABLED
+
+ UART_TypeDef *uart_ins_temp;
+
+ if (ifc == USER_DBG_IFC_UART0) {
+ uart_ins_temp = UART0;
+ } else if (ifc == USER_DBG_IFC_UART1) {
+ uart_ins_temp = UART1;
+ } else if (ifc == USER_DBG_IFC_UART2) {
+ uart_ins_temp = UART2;
+ } else if (ifc == USER_DBG_IFC_UART3) {
+ uart_ins_temp = UART3;
+ } else if (ifc == USER_DBG_IFC_UART4) {
+ uart_ins_temp = UART4;
+ } else {
+ return LL_INVALID;
+ }
+
+ //UART Init
+ UART_InitTypeDef uart_init;
+ memset((void *)&uart_init, 0x00, sizeof(uart_init));
+ uart_init.baudrate = 115200;
+ uart_init.dat_len = UART_DAT_LEN_8b;
+ uart_init.stop_len = UART_STOP_LEN_1b;
+ uart_init.parity = UART_PARITY_NO;
+ ret = LL_UART_Init(uart_ins_temp, &uart_init);
+
+ if (ret == LL_OK) {
+ user_dbg_ifc = ifc;
+ user_dbg_uart_ins = uart_ins_temp;
+ }
+
+#endif
+ }
+
+ return ret;
+}
+
+/**
+ * @brief User Debug DeInit
+ * @note Remember to implement the LL_UART_MspDeInit interface in the user file if use UART as debug interface
+ * @return LL Status
+ */
+LL_StatusETypeDef User_Debug_DeInit(void)
+{
+ LL_StatusETypeDef ret = LL_FAILED;
+
+ //Check current user debug interface to be Valid
+ if (user_dbg_ifc == USER_DBG_IFC_NO) {
+ user_dbg_uart_ins = NULL;
+ return LL_OK;
+ }
+
+ if (user_dbg_ifc == USER_DBG_IFC_ITM) {
+#ifdef LL_GPIO_MODULE_ENABLED
+ //SWO GPIO DeInit: PB3
+ ret = LL_GPIO_DeInit(GPIOB, GPIO_PIN_3);
+
+ if (ret == LL_OK) {
+ user_dbg_ifc = USER_DBG_IFC_NO;
+ }
+
+#endif
+
+ } else {
+
+#ifdef LL_UART_MODULE_ENABLED
+
+ if (user_dbg_uart_ins == NULL) {
+ return LL_INVALID;
+ }
+
+ //UART DeInit
+ ret = LL_UART_DeInit(user_dbg_uart_ins);
+
+ if (ret == LL_OK) {
+ user_dbg_ifc = USER_DBG_IFC_NO;
+ user_dbg_uart_ins = NULL;
+ }
+
+#endif
+ }
+
+ return ret;
+}
+
+/**
+ * @brief User Debug Get Char
+ * @param None
+ * @return get char value
+ */
+int User_Debug_GetChar(void)
+{
+ int val = 0;
+
+ //Check user debug interface to be Valid
+ if (user_dbg_ifc == USER_DBG_IFC_NO) {
+ return 0;
+ }
+
+ if (user_dbg_ifc == USER_DBG_IFC_ITM) {
+ while (!ITM_CheckChar()) {
+ __NOP();
+ }
+
+ val = ITM_ReceiveChar();
+ } else {
+#ifdef LL_UART_MODULE_ENABLED
+
+ if (user_dbg_uart_ins == NULL) {
+ return 0;
+ }
+
+ //Wait RX data to be ready
+ while (__LL_UART_IsRxFIFOEmpty(user_dbg_uart_ins));
+
+ //Read data from UART
+ val = __LL_UART_RxDat9bits_Read(user_dbg_uart_ins);
+#endif
+ }
+
+ return val;
+}
+
+/**
+ * @brief User Debug Put Char
+ * @param Data put data
+ * @return None
+ */
+void User_Debug_PutChar(uint16_t Data)
+{
+ //Check user debug interface to be Valid
+ if (user_dbg_ifc == USER_DBG_IFC_NO) {
+ return;
+ }
+
+ if (user_dbg_ifc == USER_DBG_IFC_ITM) {
+ ITM_SendChar(Data);
+ } else {
+#ifdef LL_UART_MODULE_ENABLED
+
+ if (user_dbg_uart_ins == NULL) {
+ return;
+ }
+
+ //Wait TXFIFO to be no full
+ while (__LL_UART_IsTxFIFOFull(user_dbg_uart_ins));
+
+ //Send data to UART
+ __LL_UART_TxDat9bits_Write(user_dbg_uart_ins, Data);
+#endif
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup User_Debug_Private_Functions User Debug Private Functions
+ * @brief User Debug Private Functions
+ * @{
+ */
+
+
+#if defined(__CC_ARM) || defined(__ICCARM__) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/**
+ * @brief Get char, Retargets the C library DBG_NOR function to the UART or ITM.
+ * @param f file pointer
+ * @retval get char value
+ */
+GETCHAR_PROTOTYPE {
+ int val = 0;
+
+ val = User_Debug_GetChar();
+
+ return val;
+}
+
+/**
+ * @brief Put char, Retargets the C library DBG_NOR function to the UART or ITM.
+ * @param ch put data
+ * @param f file pointer
+ * @retval ch
+ */
+PUTCHAR_PROTOTYPE {
+ User_Debug_PutChar(ch);
+
+ return ch;
+}
+
+/**
+ * @brief ferror
+ * @param f: Printed entry pointer
+ * @retval Return result
+ */
+int ferror(FILE *f)
+{
+ /* Your implementation of ferror */
+ return EOF;
+}
+
+/**
+ * @brief _ttywrch
+ * @param ch: The value of the string to print
+ * @retval None
+ */
+void _ttywrch(int ch)
+{
+ int file = 0;
+ fputc(ch, (FILE *)file);
+}
+
+/**
+ * @brief _sys_exit
+ * @param return_code: Return wrong information
+ * @retval None
+ */
+void _sys_exit(int return_code)
+{
+ while (1); /* endless loop */
+}
+
+/**
+ * @brief backspace
+ * @param None
+ * @return 0
+ */
+int __backspace()
+{
+ return 0;
+}
+
+#else
+
+PUTCHAR_PROTOTYPE {
+ for (int i = 0; i < size; i++)
+ {
+ User_Debug_PutChar(pBuffer[i]);
+ }
+
+ return size;
+}
+
+GETCHAR_PROTOTYPE {
+ for (int i = 0; i < size; i++)
+ {
+ pBuffer[i] = User_Debug_GetChar();
+ }
+
+ return size;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/board/dbg/user_debug.h b/bsp/tae32/libraries/templates/tae32g58xx/board/dbg/user_debug.h
new file mode 100644
index 0000000000..63c075f4bc
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/board/dbg/user_debug.h
@@ -0,0 +1,101 @@
+/**
+ ******************************************************************************
+ * @file user_debug.h
+ * @author MCD Application Team
+ * @brief Header file for user debug.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. Flash Configuration
+ Flash Base Address <0x0-0xFFFFFFFF:8>
+ Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x08000000;
+__ROM_SIZE = 0x00040000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+ RAM Configuration
+ RAM Base Address <0x0-0xFFFFFFFF:8>
+ RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__RAMA_BASE = 0x20000000;
+__RAMA_SIZE = 0x00020000;
+
+__RAMB_BASE = 0x20010000;
+__RAMB_SIZE = 0x00000000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+ Stack / Heap Configuration
+ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE = 0x00000000;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+ RAMA (rwx) : ORIGIN = __RAMA_BASE, LENGTH = __RAMA_SIZE
+ RAMB (rwx) : ORIGIN = __RAMB_BASE, LENGTH = __RAMB_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ /* ---< text sections Config >--- */
+ .text :
+ {
+ KEEP(*(.vectors))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+
+ /*
+ * SG veneers:
+ * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ * must be set, either with the command line option �--section-start� or in a linker script,
+ * to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+*/
+
+ /* ---< Copy&Zero table sections Config >--- */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG ((__data_end__ - __data_start__) / 4)
+
+ /* Add each additional data section here */
+/*
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG ((__data2_end__ - __data2_start__) / 4)
+*/
+
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+
+ LONG (__bss_start__)
+ LONG ((__bss_end__ - __bss_start__) / 4)
+
+ /* Add each additional bss section here */
+/*
+ LONG (__bss2_start__)
+ LONG ((__bss2_end__ - __bss2_start__) / 4)
+*/
+
+ __zero_table_end__ = .;
+ } > FLASH
+
+
+ /**
+ * Location counter can end up 2byte aligned with narrow Thumb code but
+ * __etext is assumed by startup code to be the LMA of a section in RAM
+ * which must be 4byte aligned
+ */
+ __etext = ALIGN (4);
+
+
+ /* ---< data sections Config >--- */
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data)
+ *(.data.*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAMA
+
+ /*
+ * Secondary data section, optional
+ *
+ * Remember to add each additional data section
+ * to the .copy.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ __etext2 = ALIGN (4);
+
+ .data2 : AT (__etext2)
+ {
+ . = ALIGN(4);
+ __data2_start__ = .;
+ *(.data2)
+ *(.data2.*)
+ . = ALIGN(4);
+ __data2_end__ = .;
+
+ } > RAMB
+*/
+
+
+ /* ---< bss sections Config >--- */
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAMA AT > RAMA
+
+ /*
+ * Secondary bss section, optional
+ *
+ * Remember to add each additional bss section
+ * to the .zero.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ .bss2 :
+ {
+ . = ALIGN(4);
+ __bss2_start__ = .;
+ *(.bss2)
+ *(.bss2.*)
+ . = ALIGN(4);
+ __bss2_end__ = .;
+ } > RAMB AT > RAMB
+*/
+
+
+ /* ---< Heap and Stack Config >--- */
+ .heap (COPY) :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ . = . + __HEAP_SIZE;
+ . = ALIGN(8);
+ __HeapLimit = .;
+ } > RAMA
+
+ .stack (ORIGIN(RAMA) + LENGTH(RAMA) - __STACK_SIZE) (COPY) :
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ . = . + __STACK_SIZE;
+ . = ALIGN(8);
+ __StackTop = .;
+ } > RAMA
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/board/linker_scripts/link.sct b/bsp/tae32/libraries/templates/tae32g58xx/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..5328833a72
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/board/linker_scripts/link.sct
@@ -0,0 +1,19 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 0x20000000 0x00020000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_STACK AlignExpr(0x20020000, 16) EMPTY - 0x800{ ; Reserve empty region for stack
+ }
+}
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/board/tae32g58xx_ll_conf.h b/bsp/tae32/libraries/templates/tae32g58xx/board/tae32g58xx_ll_conf.h
new file mode 100644
index 0000000000..e92f8930d0
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/board/tae32g58xx_ll_conf.h
@@ -0,0 +1,282 @@
+/**
+ ******************************************************************************
+ * @file tae32g58xx_ll_conf.h
+ * @author MCD Application Team
+ * @brief LL configuration file.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+#include
+
+
+/** @addtogroup TAE32G58xx_Examples
+ * @{
+ */
+
+/** @addtogroup TAE32G58xx_GPIO_Flow_LED_Example
+ * @{
+ */
+
+
+/* Exported Types ------------------------------------------------------------*/
+/* Exported Constants --------------------------------------------------------*/
+/** @defgroup GPIO_Flow_LED_Debug_Conf_Exported_Constants GPIO_Flow_LED Debug Conf Exported Constants
+ * @brief GPIO_Flow_LED Debug Conf Exported Constants
+ * @{
+ */
+
+/**
+ * @brief Define TAE_USING_DBG to enable dbg
+ */
+#define TAE_USING_DBG
+
+/**
+ * @brief Define TAE_USING_DBG_COLOR to enable dbg color mode
+ */
+//#define TAE_USING_DBG_COLOR
+
+/**
+ * @}
+ */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup GPIO_Flow_LED_Debug_Conf_Exported_Macros GPIO_Flow_LED Debug Conf Exported Macros
+ * @brief GPIO_Flow_LED Debug Conf Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Define your own print interface here
+ */
+#ifdef TAE_USING_DBG
+#define TAE_DBG_PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define TAE_DBG_PRINT(fmt, ...)
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE_DBG_CONF_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/project.ewd b/bsp/tae32/libraries/templates/tae32g58xx/project.ewd
new file mode 100644
index 0000000000..e94c83ed06
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/project.ewd
@@ -0,0 +1,2834 @@
+
+
+ 3
+
+ rt-thread
+
+ ARM
+
+ 1
+
+ C-SPY
+ 2
+
+ 29
+ 1
+ 1
+
+ CInput
+ 1
+
+
+ CEndian
+ 1
+
+
+ CProcessor
+ 1
+
+
+ OCVariant
+ 0
+
+
+ MacOverride
+ 0
+
+
+ MacFile
+
+
+ MemOverride
+ 0
+
+
+ MemFile
+ $TOOLKIT_DIR$\CONFIG\debugger\ST\STM32F407ZG.ddf
+
+
+ RunToEnable
+ 1
+
+
+ RunToName
+ main
+
+
+ CExtraOptionsCheck
+ 0
+
+
+ CExtraOptions
+
+
+ CFpuProcessor
+ 1
+
+
+ OCDDFArgumentProducer
+
+
+ OCDownloadSuppressDownload
+ 0
+
+
+ OCDownloadVerifyAll
+ 0
+
+
+ OCProductVersion
+ 8.11.3.13977
+
+
+ OCDynDriverList
+ JLINK_ID
+
+
+ OCLastSavedByProductVersion
+ 8.11.3.13977
+
+
+ UseFlashLoader
+ 1
+
+
+ CLowLevel
+ 1
+
+
+ OCBE8Slave
+ 1
+
+
+ MacFile2
+
+
+ CDevice
+ 1
+
+
+ FlashLoadersV3
+ $TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32F4xxx.board
+
+
+ OCImagesSuppressCheck1
+ 0
+
+
+ OCImagesPath1
+
+
+ OCImagesSuppressCheck2
+ 0
+
+
+ OCImagesPath2
+
+
+ OCImagesSuppressCheck3
+ 0
+
+
+ OCImagesPath3
+
+
+ OverrideDefFlashBoard
+ 0
+
+
+ OCImagesOffset1
+
+
+ OCImagesOffset2
+
+
+ OCImagesOffset3
+
+
+ OCImagesUse1
+ 0
+
+
+ OCImagesUse2
+ 0
+
+
+ OCImagesUse3
+ 0
+
+
+ OCDeviceConfigMacroFile
+ 1
+
+
+ OCDebuggerExtraOption
+ 1
+
+
+ OCAllMTBOptions
+ 1
+
+
+ OCMulticoreNrOfCores
+ 1
+
+
+ OCMulticoreMaster
+ 0
+
+
+ OCMulticorePort
+ 53461
+
+
+ OCMulticoreWorkspace
+
+
+ OCMulticoreSlaveProject
+
+
+ OCMulticoreSlaveConfiguration
+
+
+ OCDownloadExtraImage
+ 1
+
+
+ OCAttachSlave
+ 0
+
+
+ MassEraseBeforeFlashing
+ 0
+
+
+
+
+ ARMSIM_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ OCSimDriverInfo
+ 1
+
+
+ OCSimEnablePSP
+ 0
+
+
+ OCSimPspOverrideConfig
+ 0
+
+
+ OCSimPspConfigFile
+
+
+
+
+ CADI_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CCadiMemory
+ 1
+
+
+ Fast Model
+
+
+ CCADILogFileCheck
+ 0
+
+
+ CCADILogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ CMSISDAP_ID
+ 2
+
+ 4
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ CMSISDAPResetList
+ 1
+ 10
+
+
+ CMSISDAPHWResetDuration
+ 300
+
+
+ CMSISDAPHWResetDelay
+ 200
+
+
+ CMSISDAPDoLogfile
+ 0
+
+
+ CMSISDAPLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CMSISDAPInterfaceRadio
+ 0
+
+
+ CMSISDAPInterfaceCmdLine
+ 0
+
+
+ CMSISDAPMultiTargetEnable
+ 0
+
+
+ CMSISDAPMultiTarget
+ 0
+
+
+ CMSISDAPJtagSpeedList
+ 0
+ 0
+
+
+ CMSISDAPBreakpointRadio
+ 0
+
+
+ CMSISDAPRestoreBreakpointsCheck
+ 0
+
+
+ CMSISDAPUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ CMSISDAPMultiCPUEnable
+ 0
+
+
+ CMSISDAPMultiCPUNumber
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+ CMSISDAPProbeConfigRadio
+ 0
+
+
+ CMSISDAPSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+ OCJetEmuParams
+ 1
+
+
+ CCCMSISDAPUsbSerialNo
+
+
+ CCCMSISDAPUsbSerialNoSelect
+ 0
+
+
+
+
+ GDBSERVER_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ TCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJTagBreakpointRadio
+ 0
+
+
+ CCJTagDoUpdateBreakpoints
+ 0
+
+
+ CCJTagUpdateBreakpoints
+ _call_main
+
+
+
+
+ IJET_ID
+ 2
+
+ 8
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ IjetResetList
+ 1
+ 10
+
+
+ IjetHWResetDuration
+ 300
+
+
+ IjetHWResetDelay
+ 200
+
+
+ IjetPowerFromProbe
+ 1
+
+
+ IjetPowerRadio
+ 0
+
+
+ IjetDoLogfile
+ 0
+
+
+ IjetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ IjetInterfaceRadio
+ 0
+
+
+ IjetInterfaceCmdLine
+ 0
+
+
+ IjetMultiTargetEnable
+ 0
+
+
+ IjetMultiTarget
+ 0
+
+
+ IjetScanChainNonARMDevices
+ 0
+
+
+ IjetIRLength
+ 0
+
+
+ IjetJtagSpeedList
+ 0
+ 0
+
+
+ IjetProtocolRadio
+ 0
+
+
+ IjetSwoPin
+ 0
+
+
+ IjetCpuClockEdit
+
+
+ IjetSwoPrescalerList
+ 1
+ 0
+
+
+ IjetBreakpointRadio
+ 0
+
+
+ IjetRestoreBreakpointsCheck
+ 0
+
+
+ IjetUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+ IjetProbeConfigRadio
+ 0
+
+
+ IjetMultiCPUEnable
+ 0
+
+
+ IjetMultiCPUNumber
+ 0
+
+
+ IjetSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+ OCJetEmuParams
+ 1
+
+
+ IjetPreferETB
+ 1
+
+
+ IjetTraceSettingsList
+ 0
+ 0
+
+
+ IjetTraceSizeList
+ 0
+ 4
+
+
+ FlashBoardPathSlave
+ 0
+
+
+ CCIjetUsbSerialNo
+
+
+ CCIjetUsbSerialNoSelect
+ 0
+
+
+
+
+ JLINK_ID
+ 2
+
+ 16
+ 1
+ 1
+
+ JLinkSpeed
+ 1000
+
+
+ CCJLinkDoLogfile
+ 0
+
+
+ CCJLinkLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJLinkHWResetDelay
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+ JLinkInitialSpeed
+ 1000
+
+
+ CCDoJlinkMultiTarget
+ 0
+
+
+ CCScanChainNonARMDevices
+ 0
+
+
+ CCJLinkMultiTarget
+ 0
+
+
+ CCJLinkIRLength
+ 0
+
+
+ CCJLinkCommRadio
+ 0
+
+
+ CCJLinkTCPIP
+ aaa.bbb.ccc.ddd
+
+
+ CCJLinkSpeedRadioV2
+ 0
+
+
+ CCUSBDevice
+ 1
+ 1
+
+
+ CCRDICatchReset
+ 0
+
+
+ CCRDICatchUndef
+ 0
+
+
+ CCRDICatchSWI
+ 0
+
+
+ CCRDICatchData
+ 0
+
+
+ CCRDICatchPrefetch
+ 0
+
+
+ CCRDICatchIRQ
+ 0
+
+
+ CCRDICatchFIQ
+ 0
+
+
+ CCJLinkBreakpointRadio
+ 0
+
+
+ CCJLinkDoUpdateBreakpoints
+ 0
+
+
+ CCJLinkUpdateBreakpoints
+ _call_main
+
+
+ CCJLinkInterfaceRadio
+ 1
+
+
+ CCJLinkResetList
+ 6
+ 7
+
+
+ CCJLinkInterfaceCmdLine
+ 0
+
+
+ CCCatchCORERESET
+ 0
+
+
+ CCCatchMMERR
+ 0
+
+
+ CCCatchNOCPERR
+ 0
+
+
+ CCCatchCHRERR
+ 0
+
+
+ CCCatchSTATERR
+ 0
+
+
+ CCCatchBUSERR
+ 0
+
+
+ CCCatchINTERR
+ 0
+
+
+ CCCatchSFERR
+ 0
+
+
+ CCCatchHARDERR
+ 0
+
+
+ CCCatchDummy
+ 0
+
+
+ OCJLinkScriptFile
+ 1
+
+
+ CCJLinkUsbSerialNo
+
+
+ CCTcpIpAlt
+ 0
+ 0
+
+
+ CCJLinkTcpIpSerialNo
+
+
+ CCCpuClockEdit
+ 168.0
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ OCJLinkTraceSource
+ 0
+
+
+ OCJLinkTraceSourceDummy
+ 0
+
+
+ OCJLinkDeviceName
+ 1
+
+
+
+
+ LMIFTDI_ID
+ 2
+
+ 2
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ LmiftdiSpeed
+ 500
+
+
+ CCLmiftdiDoLogfile
+ 0
+
+
+ CCLmiftdiLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCLmiFtdiInterfaceRadio
+ 0
+
+
+ CCLmiFtdiInterfaceCmdLine
+ 0
+
+
+
+
+ PEMICRO_ID
+ 2
+
+ 3
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCJPEMicroShowSettings
+ 0
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ STLINK_ID
+ 2
+
+ 4
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCSTLinkInterfaceRadio
+ 0
+
+
+ CCSTLinkInterfaceCmdLine
+ 0
+
+
+ CCSTLinkResetList
+ 3
+ 0
+
+
+ CCCpuClockEdit
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCSTLinkDoUpdateBreakpoints
+ 0
+
+
+ CCSTLinkUpdateBreakpoints
+ _call_main
+
+
+ CCSTLinkCatchCORERESET
+ 0
+
+
+ CCSTLinkCatchMMERR
+ 0
+
+
+ CCSTLinkCatchNOCPERR
+ 0
+
+
+ CCSTLinkCatchCHRERR
+ 0
+
+
+ CCSTLinkCatchSTATERR
+ 0
+
+
+ CCSTLinkCatchBUSERR
+ 0
+
+
+ CCSTLinkCatchINTERR
+ 0
+
+
+ CCSTLinkCatchSFERR
+ 0
+
+
+ CCSTLinkCatchHARDERR
+ 0
+
+
+ CCSTLinkCatchDummy
+ 0
+
+
+ CCSTLinkUsbSerialNo
+
+
+ CCSTLinkUsbSerialNoSelect
+ 0
+
+
+ CCSTLinkJtagSpeedList
+ 0
+ 0
+
+
+ CCSTLinkDAPNumber
+
+
+ CCSTLinkDebugAccessPortRadio
+ 0
+
+
+
+
+ THIRDPARTY_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CThirdPartyDriverDll
+ ###Uninitialized###
+
+
+ CThirdPartyLogFileCheck
+ 0
+
+
+ CThirdPartyLogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ TIFET_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCMSPFetResetList
+ 0
+ 0
+
+
+ CCMSPFetInterfaceRadio
+ 0
+
+
+ CCMSPFetInterfaceCmdLine
+ 0
+
+
+ CCMSPFetTargetVccTypeDefault
+ 0
+
+
+ CCMSPFetTargetVoltage
+ ###Uninitialized###
+
+
+ CCMSPFetVCCDefault
+ 1
+
+
+ CCMSPFetTargetSettlingtime
+ 0
+
+
+ CCMSPFetRadioJtagSpeedType
+ 1
+
+
+ CCMSPFetConnection
+ 0
+ 0
+
+
+ CCMSPFetUsbComPort
+ Automatic
+
+
+ CCMSPFetAllowAccessToBSL
+ 0
+
+
+ CCMSPFetDoLogfile
+ 0
+
+
+ CCMSPFetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCMSPFetRadioEraseFlash
+ 1
+
+
+
+
+ XDS100_ID
+ 2
+
+ 6
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ TIPackageOverride
+ 0
+
+
+ TIPackage
+
+
+ BoardFile
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCXds100BreakpointRadio
+ 0
+
+
+ CCXds100DoUpdateBreakpoints
+ 0
+
+
+ CCXds100UpdateBreakpoints
+ _call_main
+
+
+ CCXds100CatchReset
+ 0
+
+
+ CCXds100CatchUndef
+ 0
+
+
+ CCXds100CatchSWI
+ 0
+
+
+ CCXds100CatchData
+ 0
+
+
+ CCXds100CatchPrefetch
+ 0
+
+
+ CCXds100CatchIRQ
+ 0
+
+
+ CCXds100CatchFIQ
+ 0
+
+
+ CCXds100CatchCORERESET
+ 0
+
+
+ CCXds100CatchMMERR
+ 0
+
+
+ CCXds100CatchNOCPERR
+ 0
+
+
+ CCXds100CatchCHRERR
+ 0
+
+
+ CCXds100CatchSTATERR
+ 0
+
+
+ CCXds100CatchBUSERR
+ 0
+
+
+ CCXds100CatchINTERR
+ 0
+
+
+ CCXds100CatchSFERR
+ 0
+
+
+ CCXds100CatchHARDERR
+ 0
+
+
+ CCXds100CatchDummy
+ 0
+
+
+ CCXds100CpuClockEdit
+
+
+ CCXds100SwoClockAuto
+ 0
+
+
+ CCXds100SwoClockEdit
+ 1000
+
+
+ CCXds100HWResetDelay
+ 0
+
+
+ CCXds100ResetList
+ 0
+ 0
+
+
+ CCXds100UsbSerialNo
+
+
+ CCXds100UsbSerialNoSelect
+ 0
+
+
+ CCXds100JtagSpeedList
+ 0
+ 0
+
+
+ CCXds100InterfaceRadio
+ 2
+
+
+ CCXds100InterfaceCmdLine
+ 0
+
+
+ CCXds100ProbeList
+ 0
+ 2
+
+
+ CCXds100SWOPortRadio
+ 0
+
+
+ CCXds100SWOPort
+ 1
+
+
+
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+ 1
+
+
+ $EW_DIR$\common\plugins\IARProbe\IarProbePlugin.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+ 0
+
+
+
+
+ Release
+
+ ARM
+
+ 0
+
+ C-SPY
+ 2
+
+ 29
+ 1
+ 0
+
+ CInput
+ 1
+
+
+ CEndian
+ 1
+
+
+ CProcessor
+ 1
+
+
+ OCVariant
+ 0
+
+
+ MacOverride
+ 0
+
+
+ MacFile
+
+
+ MemOverride
+ 0
+
+
+ MemFile
+
+
+ RunToEnable
+ 1
+
+
+ RunToName
+ main
+
+
+ CExtraOptionsCheck
+ 0
+
+
+ CExtraOptions
+
+
+ CFpuProcessor
+ 1
+
+
+ OCDDFArgumentProducer
+
+
+ OCDownloadSuppressDownload
+ 0
+
+
+ OCDownloadVerifyAll
+ 0
+
+
+ OCProductVersion
+ 8.11.3.13977
+
+
+ OCDynDriverList
+ ARMSIM_ID
+
+
+ OCLastSavedByProductVersion
+
+
+ UseFlashLoader
+ 1
+
+
+ CLowLevel
+ 1
+
+
+ OCBE8Slave
+ 1
+
+
+ MacFile2
+
+
+ CDevice
+ 1
+
+
+ FlashLoadersV3
+
+
+ OCImagesSuppressCheck1
+ 0
+
+
+ OCImagesPath1
+
+
+ OCImagesSuppressCheck2
+ 0
+
+
+ OCImagesPath2
+
+
+ OCImagesSuppressCheck3
+ 0
+
+
+ OCImagesPath3
+
+
+ OverrideDefFlashBoard
+ 0
+
+
+ OCImagesOffset1
+
+
+ OCImagesOffset2
+
+
+ OCImagesOffset3
+
+
+ OCImagesUse1
+ 0
+
+
+ OCImagesUse2
+ 0
+
+
+ OCImagesUse3
+ 0
+
+
+ OCDeviceConfigMacroFile
+ 1
+
+
+ OCDebuggerExtraOption
+ 1
+
+
+ OCAllMTBOptions
+ 1
+
+
+ OCMulticoreNrOfCores
+
+
+ OCMulticoreMaster
+ 0
+
+
+ OCMulticorePort
+ 53461
+
+
+ OCMulticoreWorkspace
+
+
+ OCMulticoreSlaveProject
+
+
+ OCMulticoreSlaveConfiguration
+
+
+ OCDownloadExtraImage
+ 1
+
+
+ OCAttachSlave
+ 0
+
+
+ MassEraseBeforeFlashing
+ 0
+
+
+
+
+ ARMSIM_ID
+ 2
+
+ 1
+ 1
+ 0
+
+ OCSimDriverInfo
+ 1
+
+
+ OCSimEnablePSP
+ 0
+
+
+ OCSimPspOverrideConfig
+ 0
+
+
+ OCSimPspConfigFile
+
+
+
+
+ CADI_ID
+ 2
+
+ 0
+ 1
+ 0
+
+ CCadiMemory
+ 1
+
+
+ Fast Model
+
+
+ CCADILogFileCheck
+ 0
+
+
+ CCADILogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ CMSISDAP_ID
+ 2
+
+ 4
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ CMSISDAPResetList
+ 1
+ 10
+
+
+ CMSISDAPHWResetDuration
+ 300
+
+
+ CMSISDAPHWResetDelay
+ 200
+
+
+ CMSISDAPDoLogfile
+ 0
+
+
+ CMSISDAPLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CMSISDAPInterfaceRadio
+ 0
+
+
+ CMSISDAPInterfaceCmdLine
+ 0
+
+
+ CMSISDAPMultiTargetEnable
+ 0
+
+
+ CMSISDAPMultiTarget
+ 0
+
+
+ CMSISDAPJtagSpeedList
+ 0
+ 0
+
+
+ CMSISDAPBreakpointRadio
+ 0
+
+
+ CMSISDAPRestoreBreakpointsCheck
+ 0
+
+
+ CMSISDAPUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ CMSISDAPMultiCPUEnable
+ 0
+
+
+ CMSISDAPMultiCPUNumber
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+ CMSISDAPProbeConfigRadio
+ 0
+
+
+ CMSISDAPSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+ OCJetEmuParams
+ 1
+
+
+ CCCMSISDAPUsbSerialNo
+
+
+ CCCMSISDAPUsbSerialNoSelect
+ 0
+
+
+
+
+ GDBSERVER_ID
+ 2
+
+ 0
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ TCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJTagBreakpointRadio
+ 0
+
+
+ CCJTagDoUpdateBreakpoints
+ 0
+
+
+ CCJTagUpdateBreakpoints
+ _call_main
+
+
+
+
+ IJET_ID
+ 2
+
+ 8
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ IjetResetList
+ 1
+ 10
+
+
+ IjetHWResetDuration
+ 300
+
+
+ IjetHWResetDelay
+ 200
+
+
+ IjetPowerFromProbe
+ 1
+
+
+ IjetPowerRadio
+ 0
+
+
+ IjetDoLogfile
+ 0
+
+
+ IjetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ IjetInterfaceRadio
+ 0
+
+
+ IjetInterfaceCmdLine
+ 0
+
+
+ IjetMultiTargetEnable
+ 0
+
+
+ IjetMultiTarget
+ 0
+
+
+ IjetScanChainNonARMDevices
+ 0
+
+
+ IjetIRLength
+ 0
+
+
+ IjetJtagSpeedList
+ 0
+ 0
+
+
+ IjetProtocolRadio
+ 0
+
+
+ IjetSwoPin
+ 0
+
+
+ IjetCpuClockEdit
+
+
+ IjetSwoPrescalerList
+ 1
+ 0
+
+
+ IjetBreakpointRadio
+ 0
+
+
+ IjetRestoreBreakpointsCheck
+ 0
+
+
+ IjetUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+ IjetProbeConfigRadio
+ 0
+
+
+ IjetMultiCPUEnable
+ 0
+
+
+ IjetMultiCPUNumber
+ 0
+
+
+ IjetSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+ OCJetEmuParams
+ 1
+
+
+ IjetPreferETB
+ 1
+
+
+ IjetTraceSettingsList
+ 0
+ 0
+
+
+ IjetTraceSizeList
+ 0
+ 4
+
+
+ FlashBoardPathSlave
+ 0
+
+
+ CCIjetUsbSerialNo
+
+
+ CCIjetUsbSerialNoSelect
+ 0
+
+
+
+
+ JLINK_ID
+ 2
+
+ 16
+ 1
+ 0
+
+ JLinkSpeed
+ 1000
+
+
+ CCJLinkDoLogfile
+ 0
+
+
+ CCJLinkLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJLinkHWResetDelay
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+ JLinkInitialSpeed
+ 1000
+
+
+ CCDoJlinkMultiTarget
+ 0
+
+
+ CCScanChainNonARMDevices
+ 0
+
+
+ CCJLinkMultiTarget
+ 0
+
+
+ CCJLinkIRLength
+ 0
+
+
+ CCJLinkCommRadio
+ 0
+
+
+ CCJLinkTCPIP
+ aaa.bbb.ccc.ddd
+
+
+ CCJLinkSpeedRadioV2
+ 0
+
+
+ CCUSBDevice
+ 1
+ 1
+
+
+ CCRDICatchReset
+ 0
+
+
+ CCRDICatchUndef
+ 0
+
+
+ CCRDICatchSWI
+ 0
+
+
+ CCRDICatchData
+ 0
+
+
+ CCRDICatchPrefetch
+ 0
+
+
+ CCRDICatchIRQ
+ 0
+
+
+ CCRDICatchFIQ
+ 0
+
+
+ CCJLinkBreakpointRadio
+ 0
+
+
+ CCJLinkDoUpdateBreakpoints
+ 0
+
+
+ CCJLinkUpdateBreakpoints
+ _call_main
+
+
+ CCJLinkInterfaceRadio
+ 0
+
+
+ CCJLinkResetList
+ 6
+ 5
+
+
+ CCJLinkInterfaceCmdLine
+ 0
+
+
+ CCCatchCORERESET
+ 0
+
+
+ CCCatchMMERR
+ 0
+
+
+ CCCatchNOCPERR
+ 0
+
+
+ CCCatchCHRERR
+ 0
+
+
+ CCCatchSTATERR
+ 0
+
+
+ CCCatchBUSERR
+ 0
+
+
+ CCCatchINTERR
+ 0
+
+
+ CCCatchSFERR
+ 0
+
+
+ CCCatchHARDERR
+ 0
+
+
+ CCCatchDummy
+ 0
+
+
+ OCJLinkScriptFile
+ 1
+
+
+ CCJLinkUsbSerialNo
+
+
+ CCTcpIpAlt
+ 0
+ 0
+
+
+ CCJLinkTcpIpSerialNo
+
+
+ CCCpuClockEdit
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ OCJLinkTraceSource
+ 0
+
+
+ OCJLinkTraceSourceDummy
+ 0
+
+
+ OCJLinkDeviceName
+ 1
+
+
+
+
+ LMIFTDI_ID
+ 2
+
+ 2
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ LmiftdiSpeed
+ 500
+
+
+ CCLmiftdiDoLogfile
+ 0
+
+
+ CCLmiftdiLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCLmiFtdiInterfaceRadio
+ 0
+
+
+ CCLmiFtdiInterfaceCmdLine
+ 0
+
+
+
+
+ PEMICRO_ID
+ 2
+
+ 3
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ CCJPEMicroShowSettings
+ 0
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ STLINK_ID
+ 2
+
+ 4
+ 1
+ 0
+
+ OCDriverInfo
+ 1
+
+
+ CCSTLinkInterfaceRadio
+ 0
+
+
+ CCSTLinkInterfaceCmdLine
+ 0
+
+
+ CCSTLinkResetList
+ 3
+ 0
+
+
+ CCCpuClockEdit
+
+
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+ 0
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+
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+ 0
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+ 0
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+
+ $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+ 1
+
+
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+ 0
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+
+
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/project.ewp b/bsp/tae32/libraries/templates/tae32g58xx/project.ewp
new file mode 100644
index 0000000000..db4161a4b3
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/project.ewp
@@ -0,0 +1,2410 @@
+
+ 3
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+ rt-thread
+
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+ 1
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+ 1
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+ build\iar\Exe
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+ Automatic choice of formatter, without multibyte support.
+
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+ Automatic choice of formatter, without multibyte support.
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+ 1
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+ RTDescription
+ Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+
+
+ OGProductVersion
+ 6.30.6.53380
+
+
+ OGLastSavedByProductVersion
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+
+
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+ OGChipSelectEditMenu
+ STM32F407ZG ST STM32F407ZG
+
+
+ GenLowLevelInterface
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+ 25
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+ STM32F407ZG ST STM32F407ZG
+
+
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+
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+ NEON
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+ GenLocaleDisplayOnly
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+ OutputFile
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+ $PROJ_DIR$\board\CubeMX_Config\Inc
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+ $PROJ_DIR$\..\..\..\include
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+ CCStdIncCheck
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+ $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c
+
+
+ $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c
+
+
+ $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c
+
+
+ $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c
+
+
+ $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c
+
+
+ $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c
+
+
+ $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c
+
+
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/project.eww b/bsp/tae32/libraries/templates/tae32g58xx/project.eww
new file mode 100644
index 0000000000..c2cb02eb1e
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/project.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\project.ewp
+
+
+
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/project.uvopt b/bsp/tae32/libraries/templates/tae32g58xx/project.uvopt
new file mode 100644
index 0000000000..b53d69d5df
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/project.uvopt
@@ -0,0 +1,162 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 25000000
+
+ 1
+ 1
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\keil\List\
+
+
+ 1
+ 1
+ 1
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+ 1
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+
+
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+ 6
+ Segger\JL2CM3.dll
+
+
+
+ 0
+ JL2CM3
+ -U30000299 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000
+
+
+ 0
+ UL2CM3
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000)
+
+
+
+ 0
+
+
+ 0
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+
+
+
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/project.uvoptx b/bsp/tae32/libraries/templates/tae32g58xx/project.uvoptx
new file mode 100644
index 0000000000..fdf222da0a
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/project.uvoptx
@@ -0,0 +1,185 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+ 0
+
+
+
+ 0
+ 0
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\build\keil\List\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
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+
+ 0
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+
+ 255
+
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+ 0
+ 0
+ 4
+ Segger\JL2CM3.dll
+
+
+
+ 0
+ UL2CM3
+ UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0TAE32G58xx_256kB -FL040000 -FS08000000 -FP0($$Device:TAE32G5800$Flash\TAE32G58xx_256kB.FLM)
+
+
+ 0
+ JL2CM3
+ -U601012352 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8006 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC2000 -FN1 -FF0TAE32G58xx_256kB -FS08000000 -FL040000
+
+
+
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+
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+
+ 0
+ 0
+ 0
+
+
+
+
+ Source Group 1
+ 0
+ 0
+ 0
+ 0
+
+
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/project.uvproj b/bsp/tae32/libraries/templates/tae32g58xx/project.uvproj
new file mode 100644
index 0000000000..a2c80e0594
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/project.uvproj
@@ -0,0 +1,1189 @@
+
+
+ 1.1
+ ### uVision Project, (C) Keil Software
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+
+ STM32F407ZG
+ STMicroelectronics
+ IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2
+ "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000)
+ 6105
+ stm32f4xx.h
+ -DSTM32F40_41xxx
+ SFD\ST\STM32F4xx\STM32F40x.sfr
+ 0
+ 0
+ ST\STM32F4xx\
+ ST\STM32F4xx\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\build\keil\Obj\
+ rt-thread
+ 1
+ 0
+ 0
+ 1
+ 0
+ .\build\keil\List\
+ 1
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+
+ 0
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+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
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+
+
+ 1
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+ fromelf --bin !L --output rtthread.bin
+ 0
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+
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+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+ 1
+
+
+ SARMCM3.DLL
+ -MPU -REMAP
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 0
+ 1
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+
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+
+ 0
+ 6
+
+
+
+ Segger\JL2CM3.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
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+ 1
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+ 1
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+ 1
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+ "Cortex-M4"
+ 0
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+
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+ 0x20000
+
+
+ 0
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+ 0x10000
+
+
+
+
+ 1
+ 1
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+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+ USE_HAL_DRIVER, STM32F407xx
+ applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include
+
+
+
+ 1
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+ 0
+ 0
+ 0
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+ .\board\linker_scripts\link.sct
+ --keep *.o(.rti_fn.*) --keep *.o(FSymTab)
+
+
+
+
+
+ Applications
+
+
+ main.c
+ 1
+ applications\main.c
+
+
+
+
+ Drivers
+
+
+ board.c
+ 1
+ board\board.c
+
+
+
+
+ stm32f4xx_hal_msp.c
+ 1
+ board\CubeMX_Config\Src\stm32f4xx_hal_msp.c
+
+
+
+
+ startup_stm32f407xx.s
+ 2
+ ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f407xx.s
+
+
+
+
+ drv_gpio.c
+ 1
+ ..\libraries\HAL_Drivers\drv_gpio.c
+
+
+
+
+ drv_usart.c
+ 1
+ ..\libraries\HAL_Drivers\drv_usart.c
+
+
+
+
+ drv_common.c
+ 1
+ ..\libraries\HAL_Drivers\drv_common.c
+
+
+
+
+ Kernel
+
+
+ clock.c
+ 1
+ ..\..\..\src\clock.c
+
+
+
+
+ components.c
+ 1
+ ..\..\..\src\components.c
+
+
+
+
+ device.c
+ 1
+ ..\..\..\src\device.c
+
+
+
+
+ idle.c
+ 1
+ ..\..\..\src\idle.c
+
+
+
+
+ ipc.c
+ 1
+ ..\..\..\src\ipc.c
+
+
+
+
+ irq.c
+ 1
+ ..\..\..\src\irq.c
+
+
+
+
+ kservice.c
+ 1
+ ..\..\..\src\kservice.c
+
+
+
+
+ mem.c
+ 1
+ ..\..\..\src\mem.c
+
+
+
+
+ mempool.c
+ 1
+ ..\..\..\src\mempool.c
+
+
+
+
+ object.c
+ 1
+ ..\..\..\src\object.c
+
+
+
+
+ scheduler.c
+ 1
+ ..\..\..\src\scheduler.c
+
+
+
+
+ signal.c
+ 1
+ ..\..\..\src\signal.c
+
+
+
+
+ thread.c
+ 1
+ ..\..\..\src\thread.c
+
+
+
+
+ timer.c
+ 1
+ ..\..\..\src\timer.c
+
+
+
+
+ CORTEX-M4
+
+
+ cpuport.c
+ 1
+ ..\..\..\libcpu\arm\cortex-m4\cpuport.c
+
+
+
+
+ context_rvds.S
+ 2
+ ..\..\..\libcpu\arm\cortex-m4\context_rvds.S
+
+
+
+
+ backtrace.c
+ 1
+ ..\..\..\libcpu\arm\common\backtrace.c
+
+
+
+
+ div0.c
+ 1
+ ..\..\..\libcpu\arm\common\div0.c
+
+
+
+
+ showmem.c
+ 1
+ ..\..\..\libcpu\arm\common\showmem.c
+
+
+
+
+ DeviceDrivers
+
+
+ pin.c
+ 1
+ ..\..\..\components\drivers\misc\pin.c
+
+
+
+
+ serial.c
+ 1
+ ..\..\..\components\drivers\serial\serial.c
+
+
+
+
+ completion.c
+ 1
+ ..\..\..\components\drivers\src\completion.c
+
+
+
+
+ dataqueue.c
+ 1
+ ..\..\..\components\drivers\src\dataqueue.c
+
+
+
+
+ pipe.c
+ 1
+ ..\..\..\components\drivers\src\pipe.c
+
+
+
+
+ ringblk_buf.c
+ 1
+ ..\..\..\components\drivers\src\ringblk_buf.c
+
+
+
+
+ ringbuffer.c
+ 1
+ ..\..\..\components\drivers\src\ringbuffer.c
+
+
+
+
+ waitqueue.c
+ 1
+ ..\..\..\components\drivers\src\waitqueue.c
+
+
+
+
+ workqueue.c
+ 1
+ ..\..\..\components\drivers\src\workqueue.c
+
+
+
+
+ finsh
+
+
+ shell.c
+ 1
+ ..\..\..\components\finsh\shell.c
+
+
+
+
+ symbol.c
+ 1
+ ..\..\..\components\finsh\symbol.c
+
+
+
+
+ cmd.c
+ 1
+ ..\..\..\components\finsh\cmd.c
+
+
+
+
+ msh.c
+ 1
+ ..\..\..\components\finsh\msh.c
+
+
+
+
+ msh_cmd.c
+ 1
+ ..\..\..\components\finsh\msh_cmd.c
+
+
+
+
+ msh_file.c
+ 1
+ ..\..\..\components\finsh\msh_file.c
+
+
+
+
+ STM32_HAL
+
+
+ system_stm32f4xx.c
+ 1
+ ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c
+
+
+
+
+ stm32f4xx_hal.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c
+
+
+
+
+ stm32f4xx_hal_adc.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c
+
+
+
+
+ stm32f4xx_hal_adc_ex.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c
+
+
+
+
+ stm32f4xx_hal_can.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c
+
+
+
+
+ stm32f4xx_hal_cec.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c
+
+
+
+
+ stm32f4xx_hal_cortex.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c
+
+
+
+
+ stm32f4xx_hal_crc.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c
+
+
+
+
+ stm32f4xx_hal_cryp.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c
+
+
+
+
+ stm32f4xx_hal_cryp_ex.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c
+
+
+
+
+ stm32f4xx_hal_dac.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac.c
+
+
+
+
+ stm32f4xx_hal_dac_ex.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dac_ex.c
+
+
+
+
+ stm32f4xx_hal_dcmi.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi.c
+
+
+
+
+ stm32f4xx_hal_dcmi_ex.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dcmi_ex.c
+
+
+
+
+ stm32f4xx_hal_dfsdm.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dfsdm.c
+
+
+
+
+ stm32f4xx_hal_dma.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c
+
+
+
+
+ stm32f4xx_hal_dma2d.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c
+
+
+
+
+ stm32f4xx_hal_dma_ex.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c
+
+
+
+
+ stm32f4xx_hal_dsi.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c
+
+
+
+
+ stm32f4xx_hal_eth.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_eth.c
+
+
+
+
+ stm32f4xx_hal_flash.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c
+
+
+
+
+ stm32f4xx_hal_flash_ex.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c
+
+
+
+
+ stm32f4xx_hal_flash_ramfunc.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c
+
+
+
+
+ stm32f4xx_hal_fmpi2c.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c.c
+
+
+
+
+ stm32f4xx_hal_fmpi2c_ex.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_fmpi2c_ex.c
+
+
+
+
+ stm32f4xx_hal_gpio.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c
+
+
+
+
+ stm32f4xx_hal_hash.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_hash.c
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+ stm32f4xx_hal_pcd.c
+ 1
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+ 1
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+
+
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+
+ stm32f4xx_hal_rng.c
+ 1
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+
+
+
+
+ stm32f4xx_hal_rtc.c
+ 1
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+ stm32f4xx_hal_rtc_ex.c
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+
+
+
+
+ stm32f4xx_hal_sdram.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c
+
+
+
+
+ stm32f4xx_hal_smartcard.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_smartcard.c
+
+
+
+
+ stm32f4xx_hal_spdifrx.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spdifrx.c
+
+
+
+
+ stm32f4xx_hal_spi.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c
+
+
+
+
+ stm32f4xx_hal_sram.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c
+
+
+
+
+ stm32f4xx_hal_tim.c
+ 1
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+
+
+
+
+ stm32f4xx_hal_tim_ex.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c
+
+
+
+
+ stm32f4xx_hal_uart.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c
+
+
+
+
+ stm32f4xx_hal_usart.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c
+
+
+
+
+ stm32f4xx_hal_wwdg.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c
+
+
+
+
+ stm32f4xx_ll_fmc.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c
+
+
+
+
+ stm32f4xx_ll_fsmc.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c
+
+
+
+
+ stm32f4xx_ll_sdmmc.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c
+
+
+
+
+ stm32f4xx_ll_usb.c
+ 1
+ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c
+
+
+
+
+
+
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/project.uvprojx b/bsp/tae32/libraries/templates/tae32g58xx/project.uvprojx
new file mode 100644
index 0000000000..0b8acf58cc
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/project.uvprojx
@@ -0,0 +1,895 @@
+
+
+ 2.1
+ ### uVision Project, (C) Keil Software
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::ARMCC
+ 0
+
+
+ TAE32G5800
+ Tai-Action
+ Tai-Action.TAE32G58xx_DFP.1.3.0
+ https://www.keil.com/pack/
+ IRAM(0x20000000,0x10000) IRAM2(0x20010000,0x10000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TAE32G58xx_256kB -FS08000000 -FL040000 -FP0($$Device:TAE32G5800$Flash\TAE32G58xx_256kB.FLM))
+ 0
+ $$Device:TAE32G5800$SVD\TAE32G58xx.svd
+ 0
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+
+ 0
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+ .\build\keil\Obj\
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+ fromelf --bin !L --output rtthread.bin
+ 0
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+
+ SARMCM3.DLL
+ -REMAP
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ TCM.DLL
+ -pCM4
+
+
+
+ 1
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+ __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, __RTTHREAD__, RT_USING_ARMLIBC, TAE32G5800, USE_STDPERIPH_DRIVER
+ ..\..\..\include;.;..\libraries\TAE32G58xx_Firmware_Library\TAE32G58xx_Device\Inc;..\..\..\components\libc\posix\io\eventfd;..\libraries\TAE32G58xx_Firmware_Library\TAE32G58xx_Driver\Inc;..\libraries\tae32_drivers;..\..\..\components\drivers\include;..\..\..\components\drivers\phy;..\..\..\components\drivers\smp_call;..\..\..\components\libc\posix\ipc;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\compilers\common\extension;..\libraries\tae32_drivers\config;board;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\arm\cortex-m4;applications;..\libraries\TAE32G58xx_Firmware_Library\CMSIS\Include
+
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+ .\board\linker_scripts\link.sct
+
+
+
+
+
+ Applications
+
+
+ main.c
+ 1
+ applications\main.c
+
+
+
+
+ Compiler
+
+
+ syscall_mem.c
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+
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+
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+
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+
+
+
+
+ cwchar.c
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+
+
+
+
+ DeviceDrivers
+
+
+ device.c
+ 1
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+
+
+
+
+ Drivers
+
+
+ startup_tae32g58xx.c
+ 1
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+
+
+
+
+ board.c
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+
+
+
+
+ tae32g58xx_ll_msp.c
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+
+
+
+ Kernel
+
+
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+ 1
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+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
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+
+
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+
+ components.c
+ 1
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+
+
+
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+
+ cpu_up.c
+ 1
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+
+
+
+
+
+ __RT_KERNEL_SOURCE__
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+
+
+
+
+
+
+
+
+
+ defunct.c
+ 1
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+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ idle.c
+ 1
+ ..\..\..\src\idle.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ ipc.c
+ 1
+ ..\..\..\src\ipc.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
+
+
+
+
+
+
+
+ irq.c
+ 1
+ ..\..\..\src\irq.c
+
+
+
+
+
+ __RT_KERNEL_SOURCE__
+
+
+
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+
+
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+
+ kservice.c
+ 1
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+
+
+
+
+
+ __RT_KERNEL_SOURCE__
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+
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+
+ mem.c
+ 1
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+
+ scheduler_comm.c
+ 1
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+
+
+
+
+
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+
+
+ scheduler_up.c
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+
+
+
+
+ __RT_KERNEL_SOURCE__
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+
+
+
+
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+
+
+
+
+ thread.c
+ 1
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+
+
+
+
+
+ __RT_KERNEL_SOURCE__
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+
+ timer.c
+ 1
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+
+
+
+
+ __RT_KERNEL_SOURCE__
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+
+
+
+
+
+
+
+
+
+ klibc
+
+
+ kerrno.c
+ 1
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+
+
+
+
+ rt_vsscanf.c
+ 1
+ ..\..\..\src\klibc\rt_vsscanf.c
+
+
+
+
+ rt_vsnprintf_tiny.c
+ 1
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+
+
+
+
+ kstring.c
+ 1
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+
+
+
+
+ kstdio.c
+ 1
+ ..\..\..\src\klibc\kstdio.c
+
+
+
+
+ libcpu
+
+
+ atomic_arm.c
+ 1
+ ..\..\..\libcpu\arm\common\atomic_arm.c
+
+
+
+
+ div0.c
+ 1
+ ..\..\..\libcpu\arm\common\div0.c
+
+
+
+
+ showmem.c
+ 1
+ ..\..\..\libcpu\arm\common\showmem.c
+
+
+
+
+ context_rvds.S
+ 2
+ ..\..\..\libcpu\arm\cortex-m4\context_rvds.S
+
+
+
+
+ cpuport.c
+ 1
+ ..\..\..\libcpu\arm\cortex-m4\cpuport.c
+
+
+
+
+ Libraries
+
+
+ system_tae32g58xx.c
+ 1
+ ..\libraries\TAE32G58xx_Firmware_Library\TAE32G58xx_Device\Src\system_tae32g58xx.c
+
+
+
+
+ tae32g58xx_ll_rcu.c
+ 1
+ ..\libraries\TAE32G58xx_Firmware_Library\TAE32G58xx_Driver\Src\tae32g58xx_ll_rcu.c
+
+
+
+
+ tae32g58xx_ll_gpio.c
+ 1
+ ..\libraries\TAE32G58xx_Firmware_Library\TAE32G58xx_Driver\Src\tae32g58xx_ll_gpio.c
+
+
+
+
+ tae32g58xx_ll.c
+ 1
+ ..\libraries\TAE32G58xx_Firmware_Library\TAE32G58xx_Driver\Src\tae32g58xx_ll.c
+
+
+
+
+ tae32g58xx_ll_cortex.c
+ 1
+ ..\libraries\TAE32G58xx_Firmware_Library\TAE32G58xx_Driver\Src\tae32g58xx_ll_cortex.c
+
+
+
+
+ tae32g58xx_ll_sysctrl.c
+ 1
+ ..\libraries\TAE32G58xx_Firmware_Library\TAE32G58xx_Driver\Src\tae32g58xx_ll_sysctrl.c
+
+
+
+
+
+
+
+
+
+
+
+ <Project Info>
+ 0
+ 1
+
+
+
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/rtconfig.h b/bsp/tae32/libraries/templates/tae32g58xx/rtconfig.h
new file mode 100644
index 0000000000..291f07b8f0
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/rtconfig.h
@@ -0,0 +1,5 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+
+#endif
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/rtconfig.py b/bsp/tae32/libraries/templates/tae32g58xx/rtconfig.py
new file mode 100644
index 0000000000..5e5bc02064
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/rtconfig.py
@@ -0,0 +1,184 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+ PLATFORM = 'iccarm'
+ EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ CXX = PREFIX + 'g++'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+ CFLAGS = DEVICE + ' -Dgcc'
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2 -g'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ CXX = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --cpu Cortex-M4.fp '
+ CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+ AFLAGS = DEVICE + ' --apcs=interwork '
+ LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+ LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+ CFLAGS += ' -D__MICROLIB '
+ AFLAGS += ' --pd "__MICROLIB SETA 1" '
+ LFLAGS += ' --library_type=microlib '
+ EXEC_PATH += '/ARM/ARMCC/bin/'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+ CFLAGS += ' -std=c99'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'armclang':
+ # toolchains
+ CC = 'armclang'
+ CXX = 'armclang'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --cpu Cortex-M4.fp '
+ CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 '
+ CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 '
+ CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
+ CFLAGS += ' -gdwarf-3 -ffunction-sections '
+ AFLAGS = DEVICE + ' --apcs=interwork '
+ LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
+ LFLAGS += ' --list rt-thread.map '
+ LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
+ LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
+
+ EXEC_PATH += '/ARM/ARMCLANG/bin/'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O1' # armclang recommend
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ CXXFLAGS = CFLAGS
+ CFLAGS += ' -std=c99'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iccarm':
+ # toolchains
+ CC = 'iccarm'
+ CXX = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = '-Dewarm'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M4'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=VFPv4_sp'
+ CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' --silent'
+
+ AFLAGS = DEVICE
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M4'
+ AFLAGS += ' --fpu VFPv4_sp'
+ AFLAGS += ' -S'
+
+ if BUILD == 'debug':
+ CFLAGS += ' --debug'
+ CFLAGS += ' -On'
+ else:
+ CFLAGS += ' -Oh'
+
+ LFLAGS = ' --config "board/linker_scripts/link.icf"'
+ LFLAGS += ' --entry __iar_program_start'
+
+ CXXFLAGS = CFLAGS
+
+ EXEC_PATH = EXEC_PATH + '/arm/bin/'
+ POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+ import sys
+ cwd_path = os.getcwd()
+ sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+ from sdk_dist import dist_do_building
+ dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/template.ewp b/bsp/tae32/libraries/templates/tae32g58xx/template.ewp
new file mode 100644
index 0000000000..21c66ca0d0
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/template.ewp
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diff --git a/bsp/tae32/libraries/templates/tae32g58xx/template.eww b/bsp/tae32/libraries/templates/tae32g58xx/template.eww
new file mode 100644
index 0000000000..bd036bb4c9
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/template.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\template.ewp
+
+
+
+
diff --git a/bsp/tae32/libraries/templates/tae32g58xx/template.uvopt b/bsp/tae32/libraries/templates/tae32g58xx/template.uvopt
new file mode 100644
index 0000000000..b53d69d5df
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/template.uvopt
@@ -0,0 +1,162 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+
+
+
+ 0
+ 0
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+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
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+ 1
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+
+
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diff --git a/bsp/tae32/libraries/templates/tae32g58xx/template.uvoptx b/bsp/tae32/libraries/templates/tae32g58xx/template.uvoptx
new file mode 100644
index 0000000000..fdf222da0a
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/template.uvoptx
@@ -0,0 +1,185 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj; *.o
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
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+
+
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+ ARM-ADS
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+
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diff --git a/bsp/tae32/libraries/templates/tae32g58xx/template.uvproj b/bsp/tae32/libraries/templates/tae32g58xx/template.uvproj
new file mode 100644
index 0000000000..6ca2a92953
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/template.uvproj
@@ -0,0 +1,407 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+
+
+ STM32F407ZG
+ STMicroelectronics
+ IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2
+ "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code")
+ UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000)
+ 6105
+ stm32f4xx.h
+ -DSTM32F40_41xxx
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+ rt-thread
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+
+ SARMCM3.DLL
+ -MPU -REMAP
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
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+ "" ()
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+
+
+
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diff --git a/bsp/tae32/libraries/templates/tae32g58xx/template.uvprojx b/bsp/tae32/libraries/templates/tae32g58xx/template.uvprojx
new file mode 100644
index 0000000000..29e314c3fb
--- /dev/null
+++ b/bsp/tae32/libraries/templates/tae32g58xx/template.uvprojx
@@ -0,0 +1,411 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ rt-thread
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::ARMCC
+ 0
+
+
+ TAE32G5800
+ Tai-Action
+ Tai-Action.TAE32G58xx_DFP.1.3.0
+ https://www.keil.com/pack/
+ IRAM(0x20000000,0x10000) IRAM2(0x20010000,0x10000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TAE32G58xx_256kB -FS08000000 -FL040000 -FP0($$Device:TAE32G5800$Flash\TAE32G58xx_256kB.FLM))
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+ $$Device:TAE32G5800$SVD\TAE32G58xx.svd
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+
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+ -REMAP
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ TCM.DLL
+ -pCM4
+
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+
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diff --git a/bsp/tae32/tae32g5800_eval_board/.config b/bsp/tae32/tae32g5800_eval_board/.config
new file mode 100644
index 0000000000..88d8f3ad40
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/.config
@@ -0,0 +1,1313 @@
+CONFIG_SOC_TAE325800=y
+CONFIG_BOARD_TAE32G5800_EVAL=y
+
+#
+# RT-Thread Kernel
+#
+
+#
+# klibc options
+#
+
+#
+# rt_vsnprintf options
+#
+# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set
+# end of rt_vsnprintf options
+
+#
+# rt_vsscanf options
+#
+# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set
+# end of rt_vsscanf options
+
+#
+# rt_memset options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set
+# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set
+# end of rt_memset options
+
+#
+# rt_memcpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set
+# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set
+# end of rt_memcpy options
+
+#
+# rt_memmove options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set
+# end of rt_memmove options
+
+#
+# rt_memcmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set
+# end of rt_memcmp options
+
+#
+# rt_strstr options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set
+# end of rt_strstr options
+
+#
+# rt_strcasecmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set
+# end of rt_strcasecmp options
+
+#
+# rt_strncpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set
+# end of rt_strncpy options
+
+#
+# rt_strcpy options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set
+# end of rt_strcpy options
+
+#
+# rt_strncmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set
+# end of rt_strncmp options
+
+#
+# rt_strcmp options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set
+# end of rt_strcmp options
+
+#
+# rt_strlen options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set
+# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set
+# end of rt_strlen options
+
+#
+# rt_strnlen options
+#
+# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set
+# end of rt_strnlen options
+# end of klibc options
+
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
+
+#
+# kservice options
+#
+# CONFIG_RT_USING_TINY_FFS is not set
+# end of kservice options
+
+CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_ASSERT=y
+CONFIG_RT_DEBUGING_COLOR=y
+CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
+# CONFIG_RT_USING_CI_ACTION is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
+
+#
+# Memory Management
+#
+# CONFIG_RT_USING_MEMPOOL is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50201
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# end of RT-Thread Kernel
+
+CONFIG_RT_USING_HW_ATOMIC=y
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M4=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+# CONFIG_FINSH_USING_WORD_OPERATION is not set
+# CONFIG_FINSH_USING_FUNC_EXT is not set
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=128
+CONFIG_FINSH_USING_OPTION_COMPLETION=y
+
+#
+# DFS: device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# end of DFS: device virtual file system
+
+CONFIG_RT_USING_FAL=y
+CONFIG_FAL_USING_DEBUG=y
+CONFIG_FAL_PART_HAS_TABLE_CFG=y
+# CONFIG_FAL_USING_SFUD_PORT is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set
+CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+# CONFIG_RT_USING_SERIAL_BYPASS is not set
+CONFIG_RT_USING_CAN=y
+CONFIG_RT_CAN_USING_HDR=y
+CONFIG_RT_CAN_USING_CANFD=y
+CONFIG_RT_CANMSG_BOX_SZ=16
+CONFIG_RT_CANSND_BOX_NUM=1
+CONFIG_RT_CANSND_MSG_TIMEOUT=100
+CONFIG_RT_CAN_NB_TX_FIFO_SIZE=256
+# CONFIG_RT_CAN_MALLOC_NB_TX_BUFFER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PHY_V2 is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_WDT=y
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_BLK is not set
+# CONFIG_RT_USING_VIRTIO is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_KTIME is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CHERRYUSB is not set
+# end of Device Drivers
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+# end of Timezone and Daylight Saving Time
+# end of ISO-ANSI C layer
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
+# CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+# end of Network
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+# end of Memory protection
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Using USB legacy version
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB legacy version
+
+# CONFIG_RT_USING_FDT is not set
+# end of RT-Thread Components
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+# end of RT-Thread Utestcases
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# end of CYW43012 WiFi
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+# end of BL808 WiFi
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
+# end of CYW43439 WiFi
+# end of Wi-Fi
+
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
+# CONFIG_PKG_USING_QMODBUS is not set
+# end of IoT - internet of things
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+# end of multimedia packages
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_RT_TRACE is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+# end of tools packages
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+# end of enhanced kernel services
+
+# CONFIG_PKG_USING_AUNITY is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_CORE is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+# CONFIG_PKG_USING_CMSIS_NN is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FILEX is not set
+# CONFIG_PKG_USING_LEVELX is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
+# end of system packages
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# HAL & SDK Drivers
+#
+
+#
+# STM32 HAL & SDK Drivers
+#
+# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# end of STM32 HAL & SDK Drivers
+
+#
+# Infineon HAL Packages
+#
+# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
+# CONFIG_PKG_USING_INFINEON_CMSIS is not set
+# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
+# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
+# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
+# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
+# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
+# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
+# CONFIG_PKG_USING_INFINEON_USBDEV is not set
+# end of Infineon HAL Packages
+
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# end of HAL & SDK Drivers
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+# end of sensors drivers
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_CST812T is not set
+# end of touch drivers
+
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
+# CONFIG_PKG_USING_RGPOWER is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+# end of peripheral libraries and drivers
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
+# end of AI packages
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_APID is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+# end of Signal Processing and Control Algorithm Packages
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+# end of project laboratory
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
+# end of entertainment: terminal games and other interesting software packages
+
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+# end of miscellaneous packages
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects and Demos
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set
+# end of Sensors
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+# end of Display
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+# end of Timing
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set
+# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set
+# end of Data Processing
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# end of Device Control
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# end of Other
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
+
+#
+# Uncategorized
+#
+# end of Arduino libraries
+# end of RT-Thread online packages
+
+CONFIG_SOC_FAMILY_TAE32=y
+CONFIG_SOC_SERIES_TAE32G58xx=y
+
+#
+# Hardware Drivers Config
+#
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_WDT=y
+CONFIG_BSP_USING_CAN=y
+CONFIG_BSP_USING_CAN0=y
+# CONFIG_BSP_USING_CAN1 is not set
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+CONFIG_BSP_UART0_USING_OVER_SAMP16X=y
+CONFIG_BSP_UART0_RX_BUFSIZE=512
+CONFIG_BSP_UART0_TX_BUFSIZE=0
+CONFIG_BSP_USING_UART1=y
+CONFIG_BSP_UART1_USING_OVER_SAMP16X=y
+CONFIG_BSP_UART1_RX_BUFSIZE=1024
+CONFIG_BSP_UART1_TX_BUFSIZE=0
+CONFIG_BSP_USING_UART2=y
+CONFIG_BSP_UART2_USING_OVER_SAMP16X=y
+CONFIG_BSP_UART2_RX_BUFSIZE=64
+CONFIG_BSP_UART2_TX_BUFSIZE=0
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+CONFIG_BSP_USING_ON_CHIP_FLASH=y
+# CONFIG_BSP_USING_FLASH_SBANK is not set
+CONFIG_BSP_USING_FLASH_DBANK=y
+# end of On-chip Peripheral Drivers
+
+#
+# Board extended module Drivers
+#
+# end of Hardware Drivers Config
diff --git a/bsp/tae32/tae32g5800_eval_board/.gitignore b/bsp/tae32/tae32g5800_eval_board/.gitignore
new file mode 100644
index 0000000000..7221bde019
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/.gitignore
@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h
diff --git a/bsp/tae32/tae32g5800_eval_board/EventRecorderStub.scvd b/bsp/tae32/tae32g5800_eval_board/EventRecorderStub.scvd
new file mode 100644
index 0000000000..2956b29683
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+
+
+
+
+
+
+
+
diff --git a/bsp/tae32/tae32g5800_eval_board/Kconfig b/bsp/tae32/tae32g5800_eval_board/Kconfig
new file mode 100644
index 0000000000..5eb7fd54ac
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/Kconfig
@@ -0,0 +1,34 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../../.."
+
+config PKGS_DIR
+ string
+
+config SOC_TAE325800
+ bool
+ select SOC_SERIES_TAE32G58xx
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+config BOARD_TAE32G5800_EVAL
+ bool
+ select BOARD_SERIES_TAE32_AE32G5800_EVAL_100
+ default y
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+
+if !RT_USING_NANO
+rsource "board/Kconfig"
+endif
diff --git a/bsp/tae32/tae32g5800_eval_board/README.md b/bsp/tae32/tae32g5800_eval_board/README.md
new file mode 100644
index 0000000000..fa95da1987
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/README.md
@@ -0,0 +1,100 @@
+# BSP README 模板
+
+## 简介
+
+本文档为 tae32g5800 开发板的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+开发板外观如下图所示：
+
+
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：TAE32G5800，主频 200MHz，256KB FLASH(支持双BANK)，128KB RAM
+- 常用外设
+ - LED：2个
+ - 按键：2个
+- 调试接口，标准 SWD/板载DAPLINK
+
+更多详细信息请参考【珠海泰为电子】 [TAE32G5800系列](https://www.tai-action.com/tae32g5800#%E8%8A%AF%E7%89%87%E6%A6%82%E8%BF%B0)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注** |
+| :----------------- | :----------: | :------------------------------------- |
+| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
+| UART | 支持 | UART1/UART2/UART3/UART4 |
+| FAL | 支持 |片内FLASH |
+| IWDG | 支持 | |
+| CAN | 支持 |CAN/FDCAN |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 xxx 仿真器下载程序，在通过 xxx 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行。
+
+连接开发板对应串口0(TX:PC4 RX:PC5)到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT - Thread Operating System
+ / | \ 5.2.2 build Nov 17 2025 14:43:07
+ 2006 - 2024 Copyright by RT-Thread team
+msh >
+```
+### 进阶使用
+
+此 BSP 默认开启了 GPIO/串口1/串口2/IWDG/CAN 的功能，根据实际需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包(当前未使用到任何的pkgs，此步为非必需步骤)。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+## 联系人信息
+
+维护人:
+
+- [yeml], 邮箱：<125309610@qq.com>
\ No newline at end of file
diff --git a/bsp/tae32/tae32g5800_eval_board/SConscript b/bsp/tae32/tae32g5800_eval_board/SConscript
new file mode 100644
index 0000000000..20f7689c53
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/tae32/tae32g5800_eval_board/SConstruct b/bsp/tae32/tae32g5800_eval_board/SConstruct
new file mode 100644
index 0000000000..638b826656
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/SConstruct
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+ env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+tae32_library = 'TAE32G58xx_Firmware_Library'
+tae32_drivers = 'tae32_drivers'
+rtconfig.BSP_LIBRARY_TYPE = tae32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, tae32_library, 'SConscript')))
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, tae32_drivers, 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/tae32/tae32g5800_eval_board/applications/SConscript b/bsp/tae32/tae32g5800_eval_board/applications/SConscript
new file mode 100644
index 0000000000..9bb9abae89
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/applications/SConscript
@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+ if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+ group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')
diff --git a/bsp/tae32/tae32g5800_eval_board/applications/main.c b/bsp/tae32/tae32g5800_eval_board/applications/main.c
new file mode 100644
index 0000000000..c5f4eb9552
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/applications/main.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-03-04 yeml first version
+ */
+
+#include
+#include
+#include
+
+int main(void)
+{
+ rt_base_t LED1_PIN = 0;
+ LED1_PIN = rt_pin_get("PB.6");
+ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
+ while (1)
+ {
+ rt_pin_write(LED1_PIN, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED1_PIN, PIN_LOW);
+ rt_thread_mdelay(500);
+ }
+}
+
+
+
+
\ No newline at end of file
diff --git a/bsp/tae32/tae32g5800_eval_board/applications/main.h b/bsp/tae32/tae32g5800_eval_board/applications/main.h
new file mode 100644
index 0000000000..7a5f5f2d48
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/applications/main.h
@@ -0,0 +1,69 @@
+/**
+ ******************************************************************************
+ * @file main.h
+ * @author MCD Application Team
+ * @brief Header for main.c module
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+
+
+/** @addtogroup TAE32G58xx_Examples
+ * @{
+ */
+
+/** @addtogroup TAE32G58xx_Template
+ * @{
+ */
+
+
+/* Exported Constants --------------------------------------------------------*/
+/* Exported Macros -----------------------------------------------------------*/
+/* Exported Types ------------------------------------------------------------*/
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _MAIN_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/tae32g5800_eval_board/board/Kconfig b/bsp/tae32/tae32g5800_eval_board/board/Kconfig
new file mode 100644
index 0000000000..0edc785387
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/board/Kconfig
@@ -0,0 +1,167 @@
+menu "Hardware Drivers Config"
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default y
+
+ config BSP_USING_WDT
+ bool "Enable Independent Watch Dog Timer"
+ select RT_USING_WDT
+ default n
+
+ menuconfig BSP_USING_CAN
+ bool "Enable CAN"
+ default n
+ select RT_USING_CAN
+ select RT_CAN_USING_HDR
+ if BSP_USING_CAN
+ config BSP_USING_CAN0
+ bool "Enable can0"
+ default n
+
+ config BSP_USING_CAN1
+ bool "Enable can1"
+ default n
+ endif
+
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default y
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ config BSP_USING_UART0
+ bool "Enable UART0"
+ default y
+
+ config BSP_UART0_USING_OVER_SAMP16X
+ bool " Enable UART0 OVER SAMP16X"
+ depends on BSP_USING_UART0
+ default n
+
+ config BSP_UART0_RX_BUFSIZE
+ int " Set UART0 RX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART0 && RT_USING_SERIAL_V2
+ default 64
+
+ config BSP_UART0_TX_BUFSIZE
+ int " Set UART0 TX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART0 && RT_USING_SERIAL_V2
+ default 0
+
+ config BSP_USING_UART1
+ bool "Enable UART1"
+ default y
+
+ config BSP_UART1_USING_OVER_SAMP16X
+ bool " Enable UART1 OVER_SAMP16X"
+ depends on BSP_USING_UART1
+ default n
+
+ config BSP_UART1_RX_BUFSIZE
+ int " Set UART1 RX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART1 && RT_USING_SERIAL_V2
+ default 64
+
+ config BSP_UART1_TX_BUFSIZE
+ int " Set UART1 TX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART1 && RT_USING_SERIAL_V2
+ default 0
+
+ config BSP_USING_UART2
+ bool "Enable UART2"
+ default y
+
+ config BSP_UART2_USING_OVER_SAMP16X
+ bool " Enable UART2 OVER_SAMP16X"
+ depends on BSP_USING_UART2
+ default n
+
+ config BSP_UART2_RX_BUFSIZE
+ int " Set UART2 RX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART2 && RT_USING_SERIAL_V2
+ default 64
+
+ config BSP_UART2_TX_BUFSIZE
+ int " Set UART2 TX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART2 && RT_USING_SERIAL_V2
+ default 0
+
+ config BSP_USING_UART3
+ bool "Enable UART3"
+ default y
+
+ config BSP_UART3_USING_OVER_SAMP16X
+ bool " Enable UART3 OVER_SAMP16X"
+ depends on BSP_USING_UART3
+ default n
+
+ config BSP_UART3_RX_BUFSIZE
+ int " Set UART3 RX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART3 && RT_USING_SERIAL_V2
+ default 64
+
+ config BSP_UART3_TX_BUFSIZE
+ int " Set UART3 TX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART3 && RT_USING_SERIAL_V2
+ default 0
+
+ config BSP_USING_UART4
+ bool "Enable UART4"
+ default y
+
+ config BSP_UART4_USING_OVER_SAMP16X
+ bool " Enable UART4 OVER_SAMP16X"
+ depends on BSP_USING_UART4
+ default n
+
+ config BSP_UART4_RX_BUFSIZE
+ int " Set UART4 RX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART4 && RT_USING_SERIAL_V2
+ default 64
+
+ config BSP_UART4_TX_BUFSIZE
+ int " Set UART4 TX buffer size"
+ range 0 65535
+ depends on BSP_USING_UART4 && RT_USING_SERIAL_V2
+ default 0
+ endif
+
+ menuconfig BSP_USING_ON_CHIP_FLASH
+ bool "Enable on-chip FLASH"
+ default n
+ if BSP_USING_ON_CHIP_FLASH
+ choice
+ prompt "Select based on the actual bank mode of the chip"
+ default BSP_USING_FLASH_SBANK
+
+ config BSP_USING_FLASH_SBANK
+ bool "Single Bank Flash"
+
+ config BSP_USING_FLASH_DBANK
+ bool "Dual Bank Flash"
+ endchoice
+ endif
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/tae32/tae32g5800_eval_board/board/SConscript b/bsp/tae32/tae32g5800_eval_board/board/SConscript
new file mode 100644
index 0000000000..8507a860a8
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/board/SConscript
@@ -0,0 +1,30 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+tae32g58xx_ll_msp.c
+''')
+
+path = [cwd]
+path += [cwd + '/ports']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['gcc']:
+ src += [startup_path_prefix + '/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/startup_tae32g58xx.c']
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+ src += [startup_path_prefix + '/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/startup_tae32g58xx.c']
+elif rtconfig.PLATFORM in ['iccarm']:
+ src += [startup_path_prefix + '/TAE32G58xx_Firmware_Library/TAE32G58xx_Device/Src/startup_tae32g58xx.c']
+
+CPPDEFINES = ['TAE32G5800']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/tae32/tae32g5800_eval_board/board/board.c b/bsp/tae32/tae32g5800_eval_board/board/board.c
new file mode 100644
index 0000000000..8102745aea
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/board/board.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-12 yeml first version
+ */
+
+ #include "board.h"
+
+ void SystemClock_Config(void)
+ {
+ LL_StatusETypeDef ret;
+ RCU_SysclkUserCfgTypeDef sysclk_cfg;
+
+ //SYSCLK Clock Config
+ sysclk_cfg.sysclk_src = SYSCLK_SRC_PLL0DivClk;
+ sysclk_cfg.sysclk_freq = 180000000UL;
+ sysclk_cfg.pll0clk_src = PLLCLK_SRC_HSE;
+ sysclk_cfg.pll0clk_src_freq = HSE_VALUE;
+ sysclk_cfg.apb0_clk_div = RCU_CLK_DIV_2;
+ sysclk_cfg.apb1_clk_div = RCU_CLK_DIV_2;
+ sysclk_cfg.ahb_clk_div = RCU_CLK_DIV_1;
+ ret = LL_RCU_SysclkInit(RCU, &sysclk_cfg);
+
+ if (ret == LL_OK) {
+ SystemCoreClockUpdate(sysclk_cfg.sysclk_freq);
+ }
+
+ if (ret == LL_OK) {
+ LL_RCU_USB_ClkCfg(RCU_CLK_SRC_PLL0, RCU_CLK_DIV_6);
+ }
+ if (ret == LL_OK) {
+ LL_RCU_CAN_ClkCfg(RCU_CLK_SRC_PLL0, RCU_CLK_DIV_6);
+ }
+ }
+
+ /**
+ * This is the timer interrupt service routine.
+ *
+ */
+ void SysTick_Handler(void)
+ {
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ LL_IncTick();
+ /* leave interrupt */
+ rt_interrupt_leave();
+ }
+
+ /**
+ * This function will initial TAE32 board.
+ */
+void rt_hw_board_init()
+{
+ /* System Clock Update */
+ SystemClock_Config();
+
+ /* System Tick Configuration */
+ LL_Init();
+
+ #if defined(RT_USING_HEAP)
+ /* Heap initialization */
+ rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+ #endif
+
+ #ifdef RT_USING_SERIAL
+ rt_hw_usart_init();
+ #endif
+
+ #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+ /* Set the shell console output device */
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+ #endif
+
+ #if defined(RT_USING_CONSOLE) && defined(RT_USING_NANO)
+ extern void rt_hw_console_init(void);
+ rt_hw_console_init();
+ #endif
+
+ #ifdef RT_USING_COMPONENTS_INIT
+ /* Board underlying hardware initialization */
+ rt_components_board_init();
+ #endif
+ }
\ No newline at end of file
diff --git a/bsp/tae32/tae32g5800_eval_board/board/board.h b/bsp/tae32/tae32g5800_eval_board/board/board.h
new file mode 100644
index 0000000000..9d01c90bb1
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/board/board.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-12 yeml first version
+ */
+
+ #ifndef __BOARD_H__
+ #define __BOARD_H__
+
+ #include
+ #include "tae32g58xx_ll.h"
+
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+
+#define TAE32_FLASH_START_ADRESS ((uint32_t)0x08000000)
+#define TAE32_FLASH_SIZE (32 * 8192)
+#define TAE32_FLASH_END_ADDRESS ((uint32_t)(TAE32_FLASH_START_ADRESS + TAE32_FLASH_SIZE))
+
+#define TAE32_SRAM_SIZE 128
+#define TAE32_SRAM_END (0x20000000 + TAE32_SRAM_SIZE * 1024)
+
+#if defined(__ARMCC_VERSION)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN (&__bss_end)
+#endif
+
+#define HEAP_END (TAE32_SRAM_END - 0x800)
+
+ void SystemClock_Config(void);
+ int rt_hw_usart_init(void);
+ #ifdef __cplusplus
+ }
+ #endif
+
+ #endif
+
+
\ No newline at end of file
diff --git a/bsp/tae32/tae32g5800_eval_board/board/dbg/tae_dbg.h b/bsp/tae32/tae32g5800_eval_board/board/dbg/tae_dbg.h
new file mode 100644
index 0000000000..c95941acc2
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/board/dbg/tae_dbg.h
@@ -0,0 +1,254 @@
+/**
+ ******************************************************************************
+ * @file tae_dbg.h
+ * @author MCD Application Team
+ * @brief The macro definitions for dbg
+ *
+ ==============================================================================
+ ##### How to use #####
+ ==============================================================================
+ *
+ * If you want to use debug macro, you can use as following steps:
+ *
+ * Step 1: Macros in "tae_dbg_conf.h"
+ * a. Define the TAE_USING_DBG to enable the feature
+ * #define TAE_USING_DBG
+ *
+ * b. Define the print interface for dbg
+ * #define TAE_DBG_PRINT(...) printf(__VA_ARGS__)
+ *
+ * c. Other optional macros define, such as TAE_USING_DBG_COLOR
+ *
+ * Step 2: Macros in your C/C++ file
+ * a. Define the debug tag and level for dbg. If you did not define this,
+ default definition will be used.
+ * #define DBG_TAG "TAG" // must be string
+ * #define DBG_LVL DBG_INFO // others DBG_ERROR, DBG_WARNING, DBG_LOG.
+ * DBG_LOG > DBG_INFO > DBG_WARNING > DBG_ERROR
+ *
+ * b. Include this header file
+ * #include "tae_dbg.h" // this must after of DBG_LVL, DBG_TAG or other options
+ *
+ * Step 3: LOG_X macro to print out logs in your C/C++ file
+ * PLEASE NOTE: LOG_X is related to the DBG_LVL that defined in Step 2. Using LOG_X
+ * witch higher then DBG_LVL will be ignored.
+ * LOG_D("this is a debug log!");
+ * LOG_I("this is a info log!")
+ * LOG_W("this is a warning log!")
+ * LOG_E("this is a error log!");
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+
+
+/** @addtogroup TAE_Utilities
+ * @{
+ */
+
+/** @defgroup TAE_Debug_Template TAE Debug Template
+ * @brief TAE Debug Template
+ * @{
+ */
+
+
+/* Exported Types ------------------------------------------------------------*/
+/* Exported Constants --------------------------------------------------------*/
+/** @defgroup TAE_Debug_Template_Exported_Constants TAE Debug Template Exported Constants
+ * @brief TAE Debug Template Exported Constants
+ * @{
+ */
+
+/**
+ * @brief Define TAE_USING_DBG to enable dbg
+ */
+#define TAE_USING_DBG
+
+/**
+ * @brief Define TAE_USING_DBG_COLOR to enable dbg color mode
+ */
+#define TAE_USING_DBG_COLOR
+
+/**
+ * @}
+ */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup TAE_Debug_Template_Exported_Macros TAE Debug Template Exported Macros
+ * @brief TAE Debug Template Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Define your own print interface here
+ */
+#ifdef TAE_USING_DBG
+#define TAE_DBG_PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define TAE_DBG_PRINT(fmt, ...)
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE_DBG_CONF_TEMPLATE_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/tae32g5800_eval_board/board/dbg/user_debug.c b/bsp/tae32/tae32g5800_eval_board/board/dbg/user_debug.c
new file mode 100644
index 0000000000..7f3a270a82
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/board/dbg/user_debug.c
@@ -0,0 +1,464 @@
+/**
+ ******************************************************************************
+ * @file user_debug.c
+ * @author MCD Application Team
+ * @brief This file provides the Debug User Config Method.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+#include
+#include "dbg/user_debug.h"
+
+
+/** @defgroup TAE_Utilities TAE Utilities
+ * @brief TAE Utilities
+ * @{
+ */
+
+/** @defgroup User_Debug User Debug
+ * @brief User Debug
+ * @{
+ */
+
+
+/* Private Constants ---------------------------------------------------------*/
+/** @defgroup User_Debug_Private_Constants User Debug Private Constants
+ * @brief User Debug Private Constants
+ * @{
+ */
+
+/**
+ * @brief C lib stdio.h putchar/getchar interface retarget
+ * @note With GCC/RAISONANCE, small DBG_NOR (option LD Linker->Libraries->Small DBG_NOR set to 'Yes') calls these functions
+ */
+#if defined (__CC_ARM) /*!< AC5 Compiler */
+
+ #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
+ #define GETCHAR_PROTOTYPE int fgetc(FILE *f)
+
+#elif defined (__ICCARM__) /*!< IAR Compiler */
+
+ #define PUTCHAR_PROTOTYPE int putchar(int ch)
+ #define GETCHAR_PROTOTYPE int getchar(void)
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /*!< AC6 Compiler */
+
+ #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
+ #define GETCHAR_PROTOTYPE int fgetc(FILE *f)
+
+#elif defined (__GNUC__) /*!< GCC Compiler */
+
+ #define PUTCHAR_PROTOTYPE int _write(int fd, char *pBuffer, int size)
+ #define GETCHAR_PROTOTYPE int _read(int fd, char *pBuffer, int size)
+
+#else
+
+ #error "Not supported compiler type"
+
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Private Types -------------------------------------------------------------*/
+/** @defgroup User_Debug_Private_Types User Debug Private Types
+ * @brief User Debug Private Types
+ * @{
+ */
+
+/**
+ * @brief C lib stdio.h __FILE struct definition for KEIL Compiler
+ */
+#if defined(__CC_ARM)
+#pragma import(__use_no_semihosting_swi)
+struct __FILE {
+ int handle;
+ /* Add whatever you need here */
+};
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Private Variables ---------------------------------------------------------*/
+/** @defgroup User_Debug_Private_Variables User Debug Private Variables
+ * @brief User Debug Private Variables
+ * @{
+ */
+
+#if defined(__CC_ARM) || defined(__ICCARM__) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ /**
+ * @brief C lib stdio.h __stdout FILE stream definition
+ */
+ FILE __stdout;
+
+ /**
+ * @brief C lib stdio.h __stdin FILE stream definition
+ */
+ FILE __stdin;
+
+ /**
+ * @brief C lib stdio.h __stderr FILE stream definition
+ */
+ //FILE __stderr;
+#endif
+
+/**
+ * @brief user debug interface
+ */
+USER_DBG_IfcETypeDef user_dbg_ifc;
+
+/**
+ * @brief user debug ITM Rx buffer
+ */
+volatile int32_t ITM_RxBuffer;
+
+#ifdef LL_UART_MODULE_ENABLED
+ /**
+ * @brief user debug uart instance
+ */
+ UART_TypeDef *user_dbg_uart_ins;
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------*/
+/* Private Function Prototypes -----------------------------------------------*/
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+/** @defgroup User_Debug_Exported_Functions User Debug Exported Functions
+ * @brief User Debug Exported Functions
+ * @{
+ */
+
+/**
+ * @brief User Debug Init
+ * @note Remember to implement the LL_UART_MspInit interface in the user file if use UART as debug interface
+ * @param ifc User debug interface
+ * @return LL Status
+ */
+LL_StatusETypeDef User_Debug_Init(USER_DBG_IfcETypeDef ifc)
+{
+ LL_StatusETypeDef ret = LL_FAILED;
+
+ //Check ifc to be Valid
+ if (ifc == USER_DBG_IFC_NO) {
+ user_dbg_ifc = USER_DBG_IFC_NO;
+ user_dbg_uart_ins = NULL;
+ return LL_OK;
+ }
+
+ //User Debug Interface Init
+ if (ifc == USER_DBG_IFC_ITM) {
+#ifdef LL_GPIO_MODULE_ENABLED
+ //SWO GPIO Init: PB3
+ GPIO_InitTypeDef swo_init;
+ swo_init.Pin = GPIO_PIN_3;
+ swo_init.IntMode = GPIO_INT_MODE_CLOSE;
+ swo_init.OType = GPIO_OTYPE_PP;
+ swo_init.Pull = GPIO_NOPULL;
+ swo_init.Speed = GPIO_SPEED_FREQ_LOW;
+ swo_init.Alternate = GPIO_AF2_SWO;
+ ret = LL_GPIO_Init(GPIOB, &swo_init);
+
+ if (ret == LL_OK) {
+ user_dbg_ifc = ifc;
+ }
+
+#endif
+
+ } else {
+
+#ifdef LL_UART_MODULE_ENABLED
+
+ UART_TypeDef *uart_ins_temp;
+
+ if (ifc == USER_DBG_IFC_UART0) {
+ uart_ins_temp = UART0;
+ } else if (ifc == USER_DBG_IFC_UART1) {
+ uart_ins_temp = UART1;
+ } else if (ifc == USER_DBG_IFC_UART2) {
+ uart_ins_temp = UART2;
+ } else if (ifc == USER_DBG_IFC_UART3) {
+ uart_ins_temp = UART3;
+ } else if (ifc == USER_DBG_IFC_UART4) {
+ uart_ins_temp = UART4;
+ } else {
+ return LL_INVALID;
+ }
+
+ //UART Init
+ UART_InitTypeDef uart_init;
+ memset((void *)&uart_init, 0x00, sizeof(uart_init));
+ uart_init.baudrate = 115200;
+ uart_init.dat_len = UART_DAT_LEN_8b;
+ uart_init.stop_len = UART_STOP_LEN_1b;
+ uart_init.parity = UART_PARITY_NO;
+ ret = LL_UART_Init(uart_ins_temp, &uart_init);
+
+ if (ret == LL_OK) {
+ user_dbg_ifc = ifc;
+ user_dbg_uart_ins = uart_ins_temp;
+ }
+
+#endif
+ }
+
+ return ret;
+}
+
+/**
+ * @brief User Debug DeInit
+ * @note Remember to implement the LL_UART_MspDeInit interface in the user file if use UART as debug interface
+ * @return LL Status
+ */
+LL_StatusETypeDef User_Debug_DeInit(void)
+{
+ LL_StatusETypeDef ret = LL_FAILED;
+
+ //Check current user debug interface to be Valid
+ if (user_dbg_ifc == USER_DBG_IFC_NO) {
+ user_dbg_uart_ins = NULL;
+ return LL_OK;
+ }
+
+ if (user_dbg_ifc == USER_DBG_IFC_ITM) {
+#ifdef LL_GPIO_MODULE_ENABLED
+ //SWO GPIO DeInit: PB3
+ ret = LL_GPIO_DeInit(GPIOB, GPIO_PIN_3);
+
+ if (ret == LL_OK) {
+ user_dbg_ifc = USER_DBG_IFC_NO;
+ }
+
+#endif
+
+ } else {
+
+#ifdef LL_UART_MODULE_ENABLED
+
+ if (user_dbg_uart_ins == NULL) {
+ return LL_INVALID;
+ }
+
+ //UART DeInit
+ ret = LL_UART_DeInit(user_dbg_uart_ins);
+
+ if (ret == LL_OK) {
+ user_dbg_ifc = USER_DBG_IFC_NO;
+ user_dbg_uart_ins = NULL;
+ }
+
+#endif
+ }
+
+ return ret;
+}
+
+/**
+ * @brief User Debug Get Char
+ * @param None
+ * @return get char value
+ */
+int User_Debug_GetChar(void)
+{
+ int val = 0;
+
+ //Check user debug interface to be Valid
+ if (user_dbg_ifc == USER_DBG_IFC_NO) {
+ return 0;
+ }
+
+ if (user_dbg_ifc == USER_DBG_IFC_ITM) {
+ while (!ITM_CheckChar()) {
+ __NOP();
+ }
+
+ val = ITM_ReceiveChar();
+ } else {
+#ifdef LL_UART_MODULE_ENABLED
+
+ if (user_dbg_uart_ins == NULL) {
+ return 0;
+ }
+
+ //Wait RX data to be ready
+ while (__LL_UART_IsRxFIFOEmpty(user_dbg_uart_ins));
+
+ //Read data from UART
+ val = __LL_UART_RxDat9bits_Read(user_dbg_uart_ins);
+#endif
+ }
+
+ return val;
+}
+
+/**
+ * @brief User Debug Put Char
+ * @param Data put data
+ * @return None
+ */
+void User_Debug_PutChar(uint16_t Data)
+{
+ //Check user debug interface to be Valid
+ if (user_dbg_ifc == USER_DBG_IFC_NO) {
+ return;
+ }
+
+ if (user_dbg_ifc == USER_DBG_IFC_ITM) {
+ ITM_SendChar(Data);
+ } else {
+#ifdef LL_UART_MODULE_ENABLED
+
+ if (user_dbg_uart_ins == NULL) {
+ return;
+ }
+
+ //Wait TXFIFO to be no full
+ while (__LL_UART_IsTxFIFOFull(user_dbg_uart_ins));
+
+ //Send data to UART
+ __LL_UART_TxDat9bits_Write(user_dbg_uart_ins, Data);
+#endif
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup User_Debug_Private_Functions User Debug Private Functions
+ * @brief User Debug Private Functions
+ * @{
+ */
+
+
+#if defined(__CC_ARM) || defined(__ICCARM__) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/**
+ * @brief Get char, Retargets the C library DBG_NOR function to the UART or ITM.
+ * @param f file pointer
+ * @retval get char value
+ */
+GETCHAR_PROTOTYPE {
+ int val = 0;
+
+ val = User_Debug_GetChar();
+
+ return val;
+}
+
+/**
+ * @brief Put char, Retargets the C library DBG_NOR function to the UART or ITM.
+ * @param ch put data
+ * @param f file pointer
+ * @retval ch
+ */
+PUTCHAR_PROTOTYPE {
+ User_Debug_PutChar(ch);
+
+ return ch;
+}
+
+/**
+ * @brief ferror
+ * @param f: Printed entry pointer
+ * @retval Return result
+ */
+int ferror(FILE *f)
+{
+ /* Your implementation of ferror */
+ return EOF;
+}
+
+/**
+ * @brief _ttywrch
+ * @param ch: The value of the string to print
+ * @retval None
+ */
+void _ttywrch(int ch)
+{
+ int file = 0;
+ fputc(ch, (FILE *)file);
+}
+
+/**
+ * @brief _sys_exit
+ * @param return_code: Return wrong information
+ * @retval None
+ */
+void _sys_exit(int return_code)
+{
+ while (1); /* endless loop */
+}
+
+/**
+ * @brief backspace
+ * @param None
+ * @return 0
+ */
+int __backspace()
+{
+ return 0;
+}
+
+#else
+
+PUTCHAR_PROTOTYPE {
+ for (int i = 0; i < size; i++)
+ {
+ User_Debug_PutChar(pBuffer[i]);
+ }
+
+ return size;
+}
+
+GETCHAR_PROTOTYPE {
+ for (int i = 0; i < size; i++)
+ {
+ pBuffer[i] = User_Debug_GetChar();
+ }
+
+ return size;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/tae32g5800_eval_board/board/dbg/user_debug.h b/bsp/tae32/tae32g5800_eval_board/board/dbg/user_debug.h
new file mode 100644
index 0000000000..63c075f4bc
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/board/dbg/user_debug.h
@@ -0,0 +1,101 @@
+/**
+ ******************************************************************************
+ * @file user_debug.h
+ * @author MCD Application Team
+ * @brief Header file for user debug.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. Flash Configuration
+ Flash Base Address <0x0-0xFFFFFFFF:8>
+ Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x08000000;
+__ROM_SIZE = 0x00040000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+ RAM Configuration
+ RAM Base Address <0x0-0xFFFFFFFF:8>
+ RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__RAMA_BASE = 0x20000000;
+__RAMA_SIZE = 0x00020000;
+
+__RAMB_BASE = 0x20010000;
+__RAMB_SIZE = 0x00000000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+ Stack / Heap Configuration
+ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+ -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE = 0x00000000;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+ RAMA (rwx) : ORIGIN = __RAMA_BASE, LENGTH = __RAMA_SIZE
+ RAMB (rwx) : ORIGIN = __RAMB_BASE, LENGTH = __RAMB_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ /* ---< text sections Config >--- */
+ .text :
+ {
+ KEEP(*(.vectors))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+
+ /*
+ * SG veneers:
+ * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ * must be set, either with the command line option �--section-start� or in a linker script,
+ * to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+*/
+
+ /* ---< Copy&Zero table sections Config >--- */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG ((__data_end__ - __data_start__) / 4)
+
+ /* Add each additional data section here */
+/*
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG ((__data2_end__ - __data2_start__) / 4)
+*/
+
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+
+ LONG (__bss_start__)
+ LONG ((__bss_end__ - __bss_start__) / 4)
+
+ /* Add each additional bss section here */
+/*
+ LONG (__bss2_start__)
+ LONG ((__bss2_end__ - __bss2_start__) / 4)
+*/
+
+ __zero_table_end__ = .;
+ } > FLASH
+
+
+ /**
+ * Location counter can end up 2byte aligned with narrow Thumb code but
+ * __etext is assumed by startup code to be the LMA of a section in RAM
+ * which must be 4byte aligned
+ */
+ __etext = ALIGN (4);
+
+
+ /* ---< data sections Config >--- */
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data)
+ *(.data.*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAMA
+
+ /*
+ * Secondary data section, optional
+ *
+ * Remember to add each additional data section
+ * to the .copy.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ __etext2 = ALIGN (4);
+
+ .data2 : AT (__etext2)
+ {
+ . = ALIGN(4);
+ __data2_start__ = .;
+ *(.data2)
+ *(.data2.*)
+ . = ALIGN(4);
+ __data2_end__ = .;
+
+ } > RAMB
+*/
+
+
+ /* ---< bss sections Config >--- */
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAMA AT > RAMA
+
+ /*
+ * Secondary bss section, optional
+ *
+ * Remember to add each additional bss section
+ * to the .zero.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ .bss2 :
+ {
+ . = ALIGN(4);
+ __bss2_start__ = .;
+ *(.bss2)
+ *(.bss2.*)
+ . = ALIGN(4);
+ __bss2_end__ = .;
+ } > RAMB AT > RAMB
+*/
+
+
+ /* ---< Heap and Stack Config >--- */
+ .heap (COPY) :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ . = . + __HEAP_SIZE;
+ . = ALIGN(8);
+ __HeapLimit = .;
+ } > RAMA
+
+ .stack (ORIGIN(RAMA) + LENGTH(RAMA) - __STACK_SIZE) (COPY) :
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ . = . + __STACK_SIZE;
+ . = ALIGN(8);
+ __StackTop = .;
+ } > RAMA
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/bsp/tae32/tae32g5800_eval_board/board/linker_scripts/link.sct b/bsp/tae32/tae32g5800_eval_board/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..5328833a72
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/board/linker_scripts/link.sct
@@ -0,0 +1,19 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 0x20000000 0x00020000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_STACK AlignExpr(0x20020000, 16) EMPTY - 0x800{ ; Reserve empty region for stack
+ }
+}
+
diff --git a/bsp/tae32/tae32g5800_eval_board/board/ports/fal_cfg.h b/bsp/tae32/tae32g5800_eval_board/board/ports/fal_cfg.h
new file mode 100644
index 0000000000..1a5aca68ed
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/board/ports/fal_cfg.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2025-02-22 yeml first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include
+#include "board.h"
+
+/* ===================== Flash device Configuration ========================= */
+extern const struct fal_flash_dev tae32_onchip_flash;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE \
+{ \
+ &tae32_onchip_flash, \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table */
+#define FAL_PART_TABLE \
+{ \
+ {FAL_PART_MAGIC_WROD, "section1", "onchip_flash", 100*1024, 20 * 1024, 0}, \
+ {FAL_PART_MAGIC_WROD, "section2", "onchip_flash", 156*1024 , 50 * 1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */
+
\ No newline at end of file
diff --git a/bsp/tae32/tae32g5800_eval_board/board/tae32g58xx_ll_conf.h b/bsp/tae32/tae32g5800_eval_board/board/tae32g58xx_ll_conf.h
new file mode 100644
index 0000000000..e92f8930d0
--- /dev/null
+++ b/bsp/tae32/tae32g5800_eval_board/board/tae32g58xx_ll_conf.h
@@ -0,0 +1,282 @@
+/**
+ ******************************************************************************
+ * @file tae32g58xx_ll_conf.h
+ * @author MCD Application Team
+ * @brief LL configuration file.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved. © Copyright (c) 2020 Tai-Action.
+ * All rights reserved.
+#include
+
+
+/** @addtogroup TAE32G58xx_Examples
+ * @{
+ */
+
+/** @addtogroup TAE32G58xx_GPIO_Flow_LED_Example
+ * @{
+ */
+
+
+/* Exported Types ------------------------------------------------------------*/
+/* Exported Constants --------------------------------------------------------*/
+/** @defgroup GPIO_Flow_LED_Debug_Conf_Exported_Constants GPIO_Flow_LED Debug Conf Exported Constants
+ * @brief GPIO_Flow_LED Debug Conf Exported Constants
+ * @{
+ */
+
+/**
+ * @brief Define TAE_USING_DBG to enable dbg
+ */
+#define TAE_USING_DBG
+
+/**
+ * @brief Define TAE_USING_DBG_COLOR to enable dbg color mode
+ */
+//#define TAE_USING_DBG_COLOR
+
+/**
+ * @}
+ */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup GPIO_Flow_LED_Debug_Conf_Exported_Macros GPIO_Flow_LED Debug Conf Exported Macros
+ * @brief GPIO_Flow_LED Debug Conf Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Define your own print interface here
+ */
+#ifdef TAE_USING_DBG
+#define TAE_DBG_PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define TAE_DBG_PRINT(fmt, ...)
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Exported Variables --------------------------------------------------------*/
+/* Exported Functions --------------------------------------------------------*/
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _TAE_DBG_CONF_H_ */
+
+
+/************************* (C) COPYRIGHT Tai-Action *****END OF FILE***********/
+
diff --git a/bsp/tae32/tae32g5800_eval_board/figures/board.png b/bsp/tae32/tae32g5800_eval_board/figures/board.png
new file mode 100644
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