# SysVCoder

**Repository Path**: sdu-aes-lab/sysvcoder

## Basic Information

- **Project Name**: SysVCoder
- **Description**: An LLM-Driven Framework for Systematic Generation of System-Level Verilog Code
- **Primary Language**: Unknown
- **License**: MIT
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2026-06-16
- **Last Updated**: 2026-06-16

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Verilog Code

![Overview of SysVCoder Framework](./image/fig-overview-v4.png)

## Installation

Install dependencies:
   ```bash
   pip install -r requirements.txt
   ```

## Fine-Tuning

SysVCoder uses the Qwen2.5 models (7B and 14B) as the base for fine-tuning to generate high-quality Verilog code.

### Base and Fine-Tuned Models


## 📚 Fine-Tuned Model Zoo

### 🔍 NL specification -> GIR
| Base Model | Fine-Tuned Model |
|----------|------------------|
| [Qwen/Qwen2.5-7B-Instruct](https://huggingface.co/Qwen/Qwen2.5-7B-Instruct) | [SysVcoder/SysVCoder-7B-IR](https://huggingface.co/sysvz/SysVCoder-7B-IR) |
| [Qwen/Qwen2.5-14B-Instruct](https://huggingface.co/Qwen/Qwen2.5-14B-Instruct) | [SysVcoder/SysVCoder-14B-IR](https://huggingface.co/sysvz/SysVCoder-14B-IR) |


### 💻 GIR -> Code
| Base Model | Fine-Tuned Model |
|----------|------------------|
| [Qwen/Qwen2.5-7B-Instruct](https://huggingface.co/Qwen/Qwen2.5-7B-Instruct) | [SysVcoder/SysVCoder-7B-Code](https://huggingface.co/sysvz/SysVCoder-7B-Code) |
| [Qwen/Qwen2.5-14B-Instruct](https://huggingface.co/Qwen/Qwen2.5-14B-Instruct) | [SysVcoder/SysVCoder-14B-Code](https://huggingface.co/sysvz/SysVCoder-14B-Code) |

The complete dataset and model will be released once the paper is accepted

### Fine-Tuning Instructions

1. Navigate to the fine-tuning directory:
   ```bash
   cd Finetune/Qwen_model
   ```

2. Run the training script:
   ```bash
   python train.py
   ```

## Testing

SysVCoder provides a robust testing framework to evaluate the generated Verilog code using testbenches and performance metrics.

### Testbench Dataset Structure
The testbench dataset should be organized as follows:
```
./instance
├── PromptIR.txt  # Input prompt for intermediate representation
├── testbench.v   # Verilog testbench file
└── code.v        # Generated Verilog code
```

### Running Tests with Intermediate Representation (IR)
To generate Verilog code using the IR-based approach, use the following command:
```bash
python main.py ds 5 --temperature 0.4
```

#### Command Arguments
**api_type**: Specifies the API type for code generation. Options: gpt, ds, qwen, mg, codev, claude, RTLcoder.
**num**: Number of code samples to generate. Options: 1, 3, 5.
**--temperature**: Sampling temperature for text generation. Options: 0, 0.4, 0.8.

### Running Tests without IR
To generate Verilog code without using intermediate representation, use:
```bash
python withoutIR.py ds 5 --temperature 0.4
```

### Evaluating Performance with pass@k
To compute the pass@k metric for evaluating the quality of generated code:
```bash
python passk.py
```

## License
This project is licensed under the [MIT License](LICENSE). See the [LICENSE](LICENSE) file for details.