# mem-opt7

**Repository Path**: speedz/mem-opt7

## Basic Information

- **Project Name**: mem-opt7
- **Description**: DRAM Sub-System Optimization using Platform Architect [2025]
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2024-12-17
- **Last Updated**: 2025-12-31

## Categories & Tags

**Categories**: Uncategorized

**Tags**: dev

## README

# SoC On-chip Bus and Memory Sub-system Optimization

The Goal: Try to identify the performance degradation caused within memory subsystems, interconnects, and peripherals of a typical SoC.


### 🦑 NoC and DRAM Subsystem Performance Statistic and Analysis (SystemC Simulation)


-   [2025.03] Memo: **[Intro: PA for DRAM-NoC OPT.](https://gitee.com/speedz/mem-opt7/tree/master/Platform_Architect/PA_25.03.pdf)**

-   [2025.04] Memo: **[PA DDRx Sim Tutorial](https://gitee.com/speedz/mem-opt7/tree/master/Platform_Architect/PA-DDRsim-Part1_25.04.pdf)**

-   [2025.05] Memo: **[PA FlexNoC Sim Tutorial](https://gitee.com/speedz/mem-opt7/tree/master/Platform_Architect/PA-FlexNoCsim-Part1_25.05.pdf)**

-   [2025.06] Project: **[PA FlexNoC + DDR4 uMCTL2 Sim Tutorial Project](https://gitee.com/speedz/mem-opt7/tree/master/Platform_Architect/PA_NoC_uMCTL2sim_25.06.tgz)**

-   [2025.06] Project Doc: **[PA FlexNoC + DDR4 uMCTL2 Sim Tutorial](https://gitee.com/speedz/mem-opt7/tree/master/Platform_Architect/PA_NoC_uMCTL2sim_25.06.pdf)**

-   [2025.09] Memo: **[uMCTL2 DDR4 Address Mapping Optimization](https://gitee.com/speedz/mem-opt7/tree/master/DDR4_Addr_Remap/DDR4-Address-Remap_25.09.pdf)**

-   [2025.09] Project: **[uMCTL2 DDR4 Address Remap PA Project](https://gitee.com/speedz/mem-opt7/tree/master/DDR4_Addr_Remap/uMCTL2_DDR4_Remap_25.09.zip)**

-   [2025.11~12] Final Project: **[Trace Driven SoC DRAM-Subsystem Design using Platform Architect](https://gitee.com/speedz/mem-opt7/tree/master/Final/4K_Video_Transcoding_PA.tgz.zip)**

-   [2025.11~12] Final Project Trace Preparation: **[Video Transcoding Trace Capture & Post-processing](https://gitee.com/speedz/mem-opt7/tree/master/Final/Trace_Processing.7z.zip)**

-   [2025.11~12] Final Project Doc: **[Trace Driven SoC DRAM-Subsystem Design using Platform Architect](https://gitee.com/speedz/mem-opt7/tree/master/Final/Trace_Driven_SoC_DRAM-Subsystem_Design_using_PA.pdf)**


### 🦀 Workload Trace

-   [2025.03] Memo: **[Intro: STL Trace](https://gitee.com/speedz/mem-opt7/tree/master/Platform_Architect/PA_STL_25.03.pdf)**

-   [2025.06] Memo: **[Howto: STL Trace Capture](https://gitee.com/speedz/mem-opt7/tree/master/Platform_Architect/PA_STL_25.06.pdf)**

-   [2025.07~10] Code: **[AXI STL Logger module](https://gitee.com/speedz/mem-opt7/tree/master/STL/axi_stl_logger.sv.zip)**

-   [2025.10] Code Doc: **[AXI STL Logger module readme](https://gitee.com/speedz/mem-opt7/tree/master/STL/STL_Logger_Readme.pdf)**

-   [2025.07~10] Project: **[AXI STL Logger RTLSim Demo](https://gitee.com/speedz/mem-opt7/tree/master/STL/STL_GEN_RTLSim_Demo.zip)**

-   [2025.08] Memo: **[Video Decoder/Encoder IP Workload Trace Capture](https://gitee.com/speedz/mem-opt7/tree/master/STL/Video_Decoder_Encoder_Workload_Trace_Capture.pdf)**


### 🏄 Performance Signoff