From 3843bfc58534e576851745fa28989eebdd7f1690 Mon Sep 17 00:00:00 2001 From: wxiat Date: Thu, 29 Jun 2023 14:50:46 +0800 Subject: [PATCH] cherry-pick `add sw patch #ff50ad5468b46ef4b285a5f2e2e507730d9b0e5c`. Signed-off-by: wxiat Signed-off-by: Weisson --- nspr-4.34-sw.patch | 401 +++++++++++++++++++++++++++++++++++++++++++++ nspr.spec | 7 +- 2 files changed, 407 insertions(+), 1 deletion(-) create mode 100644 nspr-4.34-sw.patch diff --git a/nspr-4.34-sw.patch b/nspr-4.34-sw.patch new file mode 100644 index 0000000..25ebeb7 --- /dev/null +++ b/nspr-4.34-sw.patch @@ -0,0 +1,401 @@ +diff -Naur nspr-4.34.org/nspr/configure nspr-4.34.sw/nspr/configure +--- nspr-4.34.org/nspr/configure 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/configure 2023-05-16 10:40:27.966463673 +0800 +@@ -6808,6 +6808,14 @@ + fi + CPU_ARCH_TAG=_${CPU_ARCH} + case "${target_cpu}" in ++ sw_64) ++ $as_echo "#define _SW_64_ 1" >>confdefs.h ++ ++ $as_echo "#define __sw_64 1" >>confdefs.h ++ ++ CFLAGS="$CFLAGS -mieee" ++ CXXFLAGS="$CXXFLAGS -mieee" ++ ;; + alpha) + $as_echo "#define _ALPHA_ 1" >>confdefs.h + +diff -Naur nspr-4.34.org/nspr/configure.in nspr-4.34.sw/nspr/configure.in +--- nspr-4.34.org/nspr/configure.in 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/configure.in 2023-05-16 10:41:03.864728526 +0800 +@@ -1675,6 +1675,12 @@ + fi + CPU_ARCH_TAG=_${CPU_ARCH} + case "${target_cpu}" in ++ sw_64) ++ AC_DEFINE(_SW_64_) ++ AC_DEFINE(__sw_64) ++ CFLAGS="$CFLAGS -mieee" ++ CXXFLAGS="$CXXFLAGS -mieee" ++ ;; + alpha) + AC_DEFINE(_ALPHA_) + AC_DEFINE(__alpha) +diff -Naur nspr-4.34.org/nspr/pr/include/gencfg.c nspr-4.34.sw/nspr/pr/include/gencfg.c +--- nspr-4.34.org/nspr/pr/include/gencfg.c 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/pr/include/gencfg.c 2023-05-16 10:41:26.932541303 +0800 +@@ -17,7 +17,7 @@ + #endif + #endif + +-#if defined(__alpha) ++#if defined(__alpha) || defined(__sw_64) + #if !(defined(_WIN32)) && !(defined(__linux)) && !(defined(__FreeBSD__)) + error - None of _WIN32, __linux, or __FreeBSD__ is defined + #endif +diff -Naur nspr-4.34.org/nspr/pr/include/md/_freebsd.cfg nspr-4.34.sw/nspr/pr/include/md/_freebsd.cfg +--- nspr-4.34.org/nspr/pr/include/md/_freebsd.cfg 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/pr/include/md/_freebsd.cfg 2023-05-16 10:41:59.590691998 +0800 +@@ -65,7 +65,7 @@ + #define PR_ALIGN_OF_DOUBLE 4 + #define PR_ALIGN_OF_POINTER 4 + +-#elif defined(__alpha__) ++#elif defined(__alpha__) || defined(__sw_64__) + + #define IS_LITTLE_ENDIAN 1 + #undef IS_BIG_ENDIAN +diff -Naur nspr-4.34.org/nspr/pr/include/md/_freebsd.h nspr-4.34.sw/nspr/pr/include/md/_freebsd.h +--- nspr-4.34.org/nspr/pr/include/md/_freebsd.h 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/pr/include/md/_freebsd.h 2023-05-16 10:42:32.676857761 +0800 +@@ -17,6 +17,8 @@ + #define _PR_SI_SYSNAME "FREEBSD" + #if defined(__i386__) + #define _PR_SI_ARCHITECTURE "x86" ++#elif defined(__sw_64__) ++#define _PR_SI_ARCHITECTURE "sw_64" + #elif defined(__alpha__) + #define _PR_SI_ARCHITECTURE "alpha" + #elif defined(__sparc__) +diff -Naur nspr-4.34.org/nspr/pr/include/md/_linux.cfg nspr-4.34.sw/nspr/pr/include/md/_linux.cfg +--- nspr-4.34.org/nspr/pr/include/md/_linux.cfg 2023-05-16 10:38:50.426026906 +0800 ++++ nspr-4.34.sw/nspr/pr/include/md/_linux.cfg 2023-05-16 10:42:53.091577055 +0800 +@@ -128,7 +128,7 @@ + #define PR_BYTES_PER_WORD_LOG2 2 + #define PR_BYTES_PER_DWORD_LOG2 3 + +-#elif defined(__alpha) ++#elif defined(__alpha) || defined(__sw_64) + + #define IS_LITTLE_ENDIAN 1 + #undef IS_BIG_ENDIAN +diff -Naur nspr-4.34.org/nspr/pr/include/md/_linux.h nspr-4.34.sw/nspr/pr/include/md/_linux.h +--- nspr-4.34.org/nspr/pr/include/md/_linux.h 2023-05-16 10:38:50.427026941 +0800 ++++ nspr-4.34.sw/nspr/pr/include/md/_linux.h 2023-05-16 10:46:34.516378810 +0800 +@@ -23,6 +23,8 @@ + #define _PR_SI_ARCHITECTURE "ppc64" + #elif defined(__powerpc__) + #define _PR_SI_ARCHITECTURE "ppc" ++#elif defined(__sw_64) ++#define _PR_SI_ARCHITECTURE "sw_64" + #elif defined(__alpha) + #define _PR_SI_ARCHITECTURE "alpha" + #elif defined(__ia64__) +@@ -210,6 +212,83 @@ + #define _MD_ATOMIC_SET(ptr, nv) __sync_lock_test_and_set(ptr, nv) + #endif + ++#if defined(__sw_64) ++#define _PR_HAVE_ATOMIC_OPS ++#define _MD_INIT_ATOMIC() ++#define _MD_ATOMIC_ADD(ptr, i) ({ \ ++ PRInt32 __atomic_tmp, __atomic_ret; \ ++ PRInt32 __atomic_tmp1, __atomic_tmp2; \ ++ __asm__ __volatile__( \ ++ "1: ldi %[tmp1],%[val] \n" \ ++ " ldi %[tmp2],1 \n" \ ++ " lldw %[ret], 0(%[tmp1]) \n" \ ++ " wr_f %[tmp2] \n" \ ++ " addw %[ret], %[inc], %[tmp] \n" \ ++ " addw %[ret], %[inc], %[ret] \n" \ ++ " lstw %[tmp], 0(%[tmp1]) \n" \ ++ " rd_f %[tmp] \n" \ ++ " beq %[tmp], 2f \n" \ ++ ".subsection 2 \n" \ ++ "2: br 1b \n" \ ++ ".previous" \ ++ : [ret] "=&r" (__atomic_ret), \ ++ [tmp] "=&r" (__atomic_tmp), \ ++ [tmp1] "=&r" (__atomic_tmp1), \ ++ [tmp2] "=&r" (__atomic_tmp2), \ ++ [val] "=m" (*ptr) \ ++ : [inc] "Ir" (i), "m" (*ptr)); \ ++ __atomic_ret; \ ++}) ++#define _MD_ATOMIC_INCREMENT(ptr) _MD_ATOMIC_ADD(ptr, 1) ++#define _MD_ATOMIC_DECREMENT(ptr) ({ \ ++ PRInt32 __atomic_tmp, __atomic_ret; \ ++ PRInt32 __atomic_tmp1, __atomic_tmp2; \ ++ __asm__ __volatile__( \ ++ "1: ldi %[tmp1],%[val] \n" \ ++ " ldi %[tmp2],1 \n" \ ++ " lldw %[ret], 0(%[tmp1]) \n" \ ++ " wr_f %[tmp2] \n" \ ++ " subw %[ret], 1, %[tmp] \n" \ ++ " subw %[ret], 1, %[ret] \n" \ ++ " lstw %[tmp], 0(%[tmp1]) \n" \ ++ " rd_f %[tmp] \n" \ ++ " beq %[tmp], 2f \n" \ ++ ".subsection 2 \n" \ ++ "2: br 1b \n" \ ++ ".previous" \ ++ : [ret] "=&r" (__atomic_ret), \ ++ [tmp] "=&r" (__atomic_tmp), \ ++ [tmp1] "=&r" (__atomic_tmp1), \ ++ [tmp2] "=&r" (__atomic_tmp2), \ ++ [val] "=m" (*ptr) \ ++ : "m" (*ptr)); \ ++ __atomic_ret; \ ++}) ++#define _MD_ATOMIC_SET(ptr, n) ({ \ ++ PRInt32 __atomic_tmp, __atomic_ret; \ ++ PRInt32 __atomic_tmp1, __atomic_tmp2; \ ++ __asm__ __volatile__( \ ++ "1: ldi %[tmp1],%[val] \n" \ ++ " ldi %[tmp2],1 \n" \ ++ " lldw %[ret], 0(%[tmp1]) \n" \ ++ " wr_f %[tmp2] \n" \ ++ " mov %[newval], %[tmp] \n" \ ++ " lstw %[tmp], 0(%[tmp1]) \n" \ ++ " rd_f %[tmp] \n" \ ++ " beq %[tmp], 2f \n" \ ++ ".subsection 2 \n" \ ++ "2: br 1b \n" \ ++ ".previous" \ ++ : [ret] "=&r" (__atomic_ret), \ ++ [tmp] "=&r"(__atomic_tmp), \ ++ [tmp1] "=&r" (__atomic_tmp1), \ ++ [tmp2] "=&r" (__atomic_tmp2), \ ++ [val] "=m" (*ptr) \ ++ : [newval] "Ir" (n), "m" (*ptr)); \ ++ __atomic_ret; \ ++}) ++#endif ++ + #if defined(__alpha) + #define _PR_HAVE_ATOMIC_OPS + #define _MD_INIT_ATOMIC() +@@ -328,7 +407,7 @@ + #endif + #undef _PR_USE_POLL + #define _PR_STAT_HAS_ONLY_ST_ATIME +-#if defined(__alpha) || defined(__ia64__) ++#if defined(__alpha) || defined(__ia64__) || defined(__sw_64) + #define _PR_HAVE_LARGE_OFF_T + #elif (__GLIBC__ > 2) || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 1) \ + || defined(ANDROID) +@@ -385,7 +464,7 @@ + /* aix = 64, macos = 70 */ + #define PR_NUM_GCREGS 64 + +-#elif defined(__alpha) ++#elif defined(__alpha) || defined(__sw_64) + /* Alpha based Linux */ + + #if defined(__GLIBC__) && __GLIBC__ >= 2 +diff -Naur nspr-4.34.org/nspr/pr/include/md/_linux.h.gcc-atomics nspr-4.34.sw/nspr/pr/include/md/_linux.h.gcc-atomics +--- nspr-4.34.org/nspr/pr/include/md/_linux.h.gcc-atomics 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/pr/include/md/_linux.h.gcc-atomics 2023-05-16 10:49:04.333657529 +0800 +@@ -23,6 +23,8 @@ + #define _PR_SI_ARCHITECTURE "ppc64" + #elif defined(__powerpc__) + #define _PR_SI_ARCHITECTURE "ppc" ++#elif defined(__sw_64) ++#define _PR_SI_ARCHITECTURE "sw_64" + #elif defined(__alpha) + #define _PR_SI_ARCHITECTURE "alpha" + #elif defined(__ia64__) +@@ -188,6 +190,84 @@ + #define _MD_ATOMIC_SET(ptr, nv) __sync_lock_test_and_set(ptr, nv) + #endif + ++#if defined(__sw_64) ++#define _PR_HAVE_ATOMIC_OPS ++#define _MD_INIT_ATOMIC() ++#define _MD_ATOMIC_ADD(ptr, i) ({ \ ++ PRInt32 __atomic_tmp, __atomic_ret; \ ++ PRInt32 __atomic_tmp1, __atomic_tmp2; \ ++ __asm__ __volatile__( \ ++ "1: ldi %[tmp1],%[val] \n" \ ++ " ldi %[tmp2],1 \n" \ ++ " lldw %[ret], 0(%[tmp1]) \n" \ ++ " wr_f %[tmp2] \n" \ ++ " addw %[ret], %[inc], %[tmp] \n" \ ++ " addw %[ret], %[inc], %[ret] \n" \ ++ " lstw %[tmp], 0(%[tmp1]) \n" \ ++ " rd_f %[tmp] \n" \ ++ " beq %[tmp], 2f \n" \ ++ ".subsection 2 \n" \ ++ "2: br 1b \n" \ ++ ".previous" \ ++ : [ret] "=&r" (__atomic_ret), \ ++ [tmp] "=&r" (__atomic_tmp), \ ++ [tmp1] "=&r" (__atomic_tmp1), \ ++ [tmp2] "=&r" (__atomic_tmp2), \ ++ [val] "=m" (*ptr) \ ++ : [inc] "Ir" (i), "m" (*ptr)); \ ++ __atomic_ret; \ ++}) ++#define _MD_ATOMIC_INCREMENT(ptr) _MD_ATOMIC_ADD(ptr, 1) ++#define _MD_ATOMIC_DECREMENT(ptr) ({ \ ++ PRInt32 __atomic_tmp, __atomic_ret; \ ++ PRInt32 __atomic_tmp1, __atomic_tmp2; \ ++ __asm__ __volatile__( \ ++ "1: ldi %[tmp1],%[val] \n" \ ++ " ldi %[tmp2],1 \n" \ ++ " lldw %[ret], 0(%[tmp1]) \n" \ ++ " wr_f %[tmp2] \n" \ ++ " subw %[ret], 1, %[tmp] \n" \ ++ " subw %[ret], 1, %[ret] \n" \ ++ " lstw %[tmp], 0(%[tmp1]) \n" \ ++ " rd_f %[tmp] \n" \ ++ " beq %[tmp], 2f \n" \ ++ ".subsection 2 \n" \ ++ "2: br 1b \n" \ ++ ".previous" \ ++ : [ret] "=&r" (__atomic_ret), \ ++ [tmp] "=&r" (__atomic_tmp), \ ++ [tmp1] "=&r" (__atomic_tmp1), \ ++ [tmp2] "=&r" (__atomic_tmp2), \ ++ [val] "=m" (*ptr) \ ++ : "m" (*ptr)); \ ++ __atomic_ret; \ ++}) ++#define _MD_ATOMIC_SET(ptr, n) ({ \ ++ PRInt32 __atomic_tmp, __atomic_ret; \ ++ PRInt32 __atomic_tmp1, __atomic_tmp2; \ ++ __asm__ __volatile__( \ ++ "1: ldi %[tmp1],%[val] \n" \ ++ " ldi %[tmp2],1 \n" \ ++ " lldw %[ret], 0(%[tmp1]) \n" \ ++ " wr_f %[tmp2] \n" \ ++ " mov %[newval], %[tmp] \n" \ ++ " lstw %[tmp], 0(%[tmp1]) \n" \ ++ " rd_f %[tmp] \n" \ ++ " beq %[tmp], 2f \n" \ ++ ".subsection 2 \n" \ ++ "2: br 1b \n" \ ++ ".previous" \ ++ : [ret] "=&r" (__atomic_ret), \ ++ [tmp] "=&r"(__atomic_tmp), \ ++ [tmp1] "=&r" (__atomic_tmp1), \ ++ [tmp2] "=&r" (__atomic_tmp2), \ ++ [val] "=m" (*ptr) \ ++ : [newval] "Ir" (n), "m" (*ptr)); \ ++ __atomic_ret; \ ++}) ++#endif ++ ++ + #if defined(__alpha) + #define _PR_HAVE_ATOMIC_OPS + #define _MD_INIT_ATOMIC() +@@ -306,7 +386,7 @@ + #endif + #undef _PR_USE_POLL + #define _PR_STAT_HAS_ONLY_ST_ATIME +-#if defined(__alpha) || defined(__ia64__) ++#if defined(__alpha) || defined(__ia64__) || defined(__sw_64) + #define _PR_HAVE_LARGE_OFF_T + #elif (__GLIBC__ > 2) || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 1) \ + || defined(ANDROID) +@@ -363,7 +443,7 @@ + /* aix = 64, macos = 70 */ + #define PR_NUM_GCREGS 64 + +-#elif defined(__alpha) ++#elif defined(__alpha) || defined(__sw_64) + /* Alpha based Linux */ + + #if defined(__GLIBC__) && __GLIBC__ >= 2 +diff -Naur nspr-4.34.org/nspr/pr/include/md/_netbsd.cfg nspr-4.34.sw/nspr/pr/include/md/_netbsd.cfg +--- nspr-4.34.org/nspr/pr/include/md/_netbsd.cfg 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/pr/include/md/_netbsd.cfg 2023-05-16 10:49:35.964772021 +0800 +@@ -157,7 +157,7 @@ + #define PR_ALIGN_OF_DOUBLE 8 + #define PR_ALIGN_OF_POINTER 4 + +-#elif defined(__alpha__) ++#elif defined(__alpha__) || defined(__sw_64__) + #define IS_LITTLE_ENDIAN 1 + #undef IS_BIG_ENDIAN + #define HAVE_ALIGNED_DOUBLES +diff -Naur nspr-4.34.org/nspr/pr/include/md/_netbsd.h nspr-4.34.sw/nspr/pr/include/md/_netbsd.h +--- nspr-4.34.org/nspr/pr/include/md/_netbsd.h 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/pr/include/md/_netbsd.h 2023-05-16 10:50:15.493164778 +0800 +@@ -13,6 +13,8 @@ + #define _PR_SI_SYSNAME "NetBSD" + #if defined(__i386__) + #define _PR_SI_ARCHITECTURE "x86" ++#elif defined(__sw_64__) ++#define _PR_SI_ARCHITECTURE "sw_64" + #elif defined(__alpha__) + #define _PR_SI_ARCHITECTURE "alpha" + #elif defined(__amd64__) +@@ -75,7 +77,7 @@ + #define JB_SP_INDEX 2 + #elif defined(__mips__) + #define JB_SP_INDEX 4 +-#elif defined(__alpha__) ++#elif defined(__alpha__) || defined(__sw_64__) + #define JB_SP_INDEX 34 + #elif defined(__arm32__) + /* +diff -Naur nspr-4.34.org/nspr/pr/include/md/_openbsd.cfg nspr-4.34.sw/nspr/pr/include/md/_openbsd.cfg +--- nspr-4.34.org/nspr/pr/include/md/_openbsd.cfg 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/pr/include/md/_openbsd.cfg 2023-05-16 10:50:50.695405107 +0800 +@@ -206,7 +206,7 @@ + #define PR_ALIGN_OF_DOUBLE 8 + #define PR_ALIGN_OF_POINTER 4 + +-#elif defined(__alpha__) ++#elif defined(__alpha__) || defined(__sw_64__) + #define IS_LITTLE_ENDIAN 1 + #undef IS_BIG_ENDIAN + #define HAVE_ALIGNED_DOUBLES +diff -Naur nspr-4.34.org/nspr/pr/include/md/_openbsd.h nspr-4.34.sw/nspr/pr/include/md/_openbsd.h +--- nspr-4.34.org/nspr/pr/include/md/_openbsd.h 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/pr/include/md/_openbsd.h 2023-05-16 10:51:30.412804521 +0800 +@@ -12,6 +12,8 @@ + #define _PR_SI_SYSNAME "OPENBSD" + #if defined(__i386__) + #define _PR_SI_ARCHITECTURE "x86" ++#elif defined(__sw_64__) ++#define _PR_SI_ARCHITECTURE "sw_64" + #elif defined(__alpha__) + #define _PR_SI_ARCHITECTURE "alpha" + #elif defined(__amd64__) +@@ -65,7 +67,7 @@ + #define JB_SP_INDEX 2 + #elif defined(__powerpc__) + #define JB_SP_INDEX 1 +-#elif defined(__alpha__) ++#elif defined(__alpha__) || defined(__sw_64__) + #define JB_SP_INDEX 34 + #elif defined(__amd64__) + #define JB_SP_INDEX 6 +diff -Naur nspr-4.34.org/nspr/pr/include/pratom.h nspr-4.34.sw/nspr/pr/include/pratom.h +--- nspr-4.34.org/nspr/pr/include/pratom.h 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/pr/include/pratom.h 2023-05-16 10:52:07.521112011 +0800 +@@ -107,7 +107,7 @@ + defined(__powerpc__) || \ + (defined(__arm__) && \ + defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4)) || \ +- defined(__aarch64__) || defined(__alpha) || \ ++ defined(__aarch64__) || defined(__alpha) || defined(__sw_64) || \ + (defined(__mips__) && \ + defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4))))) + +diff -Naur nspr-4.34.org/nspr/pr/src/md/unix/unix.c nspr-4.34.sw/nspr/pr/src/md/unix/unix.c +--- nspr-4.34.org/nspr/pr/src/md/unix/unix.c 2022-05-26 05:34:56.000000000 +0800 ++++ nspr-4.34.sw/nspr/pr/src/md/unix/unix.c 2023-05-16 10:52:58.574910851 +0800 +@@ -2901,7 +2901,7 @@ + * to be made executable because longjmp/signal seem + * to put machine instructions on the stack. + */ +-#if defined(LINUX) && defined(__alpha) ++#if defined(LINUX) && (defined(__alpha) || defined(__sw_64)) + prot |= PROT_EXEC; + #endif + rv = mmap((vaddr != 0) ? vaddr : lastaddr, size, prot, diff --git a/nspr.spec b/nspr.spec index 37ff31b..21b71ae 100644 --- a/nspr.spec +++ b/nspr.spec @@ -1,5 +1,5 @@ %global nspr_version 4.35.0 -%define anolis_release .0.1 +%define anolis_release .0.2 # The upstream omits the trailing ".0", while we need it for # consistency with the pkg-config version: @@ -31,6 +31,7 @@ Patch1000: 1000-nspr-anolis-support-loongarch64-build.patch Patch10: nspr-4.34-fix-coverity-loop-issue.patch Patch11: nspr-4.34-server-passive.patch +Patch1001: nspr-4.34-sw.patch %description NSPR provides platform independence for non-GUI operating system @@ -68,6 +69,7 @@ pushd nspr %patch11 -p1 -b .passive popd %patch1000 -p1 +%patch1001 -p1 %build %define _configure ./nspr/configure %configure \ @@ -159,6 +161,9 @@ done %{_mandir}/man*/* %changelog +* Thu Mar 21 2024 wxiat - 4.35.0-1.0.2 +- cherry-pick `add sw patch #ff50ad5468b46ef4b285a5f2e2e507730d9b0e5c`. + * Fri Sep 22 2023 Liwei Ge - 4.35.0-1.0.1 - Support loongarch64 platform -- Gitee