diff --git a/RISC-V-1-Support-Zabha-extension.patch b/RISC-V-1-Support-Zabha-extension.patch new file mode 100644 index 0000000000000000000000000000000000000000..51c6fecb9e1f9641237ab2b70ae546d00bdad243 --- /dev/null +++ b/RISC-V-1-Support-Zabha-extension.patch @@ -0,0 +1,547 @@ +From a3b373fdc5da47390b58fbb902d904ac917f0015 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Wed, 28 Feb 2024 16:27:17 +0800 +Subject: [PATCH] RISC-V: Support Zabha extension. + +The Zabha extension[1] supports for byte and halfword +atomic memory operations. This patch add all instructions +include in Zabha. Further work is waiting Zacas[2] merge. + +[1] https://github.com/riscv/riscv-zabha/tags +[2] https://sourceware.org/pipermail/binutils/2023-May/127700.html + +Version log: +Add new imply relation that Zabha extension implies A extension. + +bfd/ChangeLog: + + * elfxx-riscv.c (riscv_implicit_subsets): New imply. + (riscv_multi_subset_supports): New extension. + (riscv_multi_subset_supports_ext): Ditto. + +gas/ChangeLog: + + * testsuite/gas/riscv/zabha-32.d: New test. + * testsuite/gas/riscv/zabha.d: New test. + * testsuite/gas/riscv/zabha.s: New test. + +include/ChangeLog: + + * opcode/riscv-opc.h (MATCH_AMOADD_B): New opcodes. + (MASK_AMOADD_B): Ditto. + (MATCH_AMOXOR_B): Ditto. + (MASK_AMOXOR_B): Ditto. + (MATCH_AMOOR_B): Ditto. + (MASK_AMOOR_B): Ditto. + (MATCH_AMOAND_B): Ditto. + (MASK_AMOAND_B): Ditto. + (MATCH_AMOMIN_B): Ditto. + (MASK_AMOMIN_B): Ditto. + (MATCH_AMOMAX_B): Ditto. + (MASK_AMOMAX_B): Ditto. + (MATCH_AMOMINU_B): Ditto. + (MASK_AMOMINU_B): Ditto. + (MATCH_AMOMAXU_B): Ditto. + (MASK_AMOMAXU_B): Ditto. + (MATCH_AMOSWAP_B): Ditto. + (MASK_AMOSWAP_B): Ditto. + (MATCH_AMOADD_H): Ditto. + (MASK_AMOADD_H): Ditto. + (MATCH_AMOXOR_H): Ditto. + (MASK_AMOXOR_H): Ditto. + (MATCH_AMOOR_H): Ditto. + (MASK_AMOOR_H): Ditto. + (MATCH_AMOAND_H): Ditto. + (MASK_AMOAND_H): Ditto. + (MATCH_AMOMIN_H): Ditto. + (MASK_AMOMIN_H): Ditto. + (MATCH_AMOMAX_H): Ditto. + (MASK_AMOMAX_H): Ditto. + (MATCH_AMOMINU_H): Ditto. + (MASK_AMOMINU_H): Ditto. + (MATCH_AMOMAXU_H): Ditto. + (MASK_AMOMAXU_H): Ditto. + (MATCH_AMOSWAP_H): Ditto. + (MASK_AMOSWAP_H): Ditto. + (DECLARE_INSN): New declare. + * opcode/riscv.h (enum riscv_insn_class): New class. + +opcodes/ChangeLog: + + * riscv-opc.c: New instructions. +--- + bfd/elfxx-riscv.c | 6 +++ + gas/testsuite/gas/riscv/zabha-32.d | 81 ++++++++++++++++++++++++++++++ + gas/testsuite/gas/riscv/zabha.d | 81 ++++++++++++++++++++++++++++++ + gas/testsuite/gas/riscv/zabha.s | 73 +++++++++++++++++++++++++++ + include/opcode/riscv-opc.h | 54 ++++++++++++++++++++ + include/opcode/riscv.h | 1 + + opcodes/riscv-opc.c | 74 +++++++++++++++++++++++++++ + 7 files changed, 370 insertions(+) + create mode 100644 gas/testsuite/gas/riscv/zabha-32.d + create mode 100644 gas/testsuite/gas/riscv/zabha.d + create mode 100644 gas/testsuite/gas/riscv/zabha.s + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index a32374c65f3..be996167960 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1118,6 +1118,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"v", "d", check_implicit_always}, + {"v", "zve64d", check_implicit_always}, + {"v", "zvl128b", check_implicit_always}, ++ {"zabha", "a", check_implicit_always}, + {"zvfbfmin", "zve32f", check_implicit_always}, + {"zvfbfwma", "zve32f", check_implicit_always}, + {"zvfbfwma", "zfbfmin", check_implicit_always}, +@@ -1278,6 +1279,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2444,6 +2446,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + return riscv_subset_supports (rps, "zmmul"); + case INSN_CLASS_A: + return riscv_subset_supports (rps, "a"); ++ case INSN_CLASS_ZABHA: ++ return riscv_subset_supports (rps, "zabha"); + case INSN_CLASS_ZAWRS: + return riscv_subset_supports (rps, "zawrs"); + case INSN_CLASS_F: +@@ -2672,6 +2676,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, + return _ ("m' or `zmmul"); + case INSN_CLASS_A: + return "a"; ++ case INSN_CLASS_ZABHA: ++ return "zabha"; + case INSN_CLASS_ZAWRS: + return "zawrs"; + case INSN_CLASS_F: +diff --git a/gas/testsuite/gas/riscv/zabha-32.d b/gas/testsuite/gas/riscv/zabha-32.d +new file mode 100644 +index 00000000000..1e6427ea752 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zabha-32.d +@@ -0,0 +1,81 @@ ++#as: -march=rv32i_zabha ++#source: zabha.s ++#objdump: -d -Mno-aliases ++ ++.*:[ ]+file format .* ++ ++Disassembly of section .text: ++ ++0+000 : ++[ ]+[0-9a-f]+:[ ]+00a5052f[ ]+amoadd.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+08a5052f[ ]+amoswap.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+60a5052f[ ]+amoand.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+40a5052f[ ]+amoor.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+20a5052f[ ]+amoxor.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+a0a5052f[ ]+amomax.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+e0a5052f[ ]+amomaxu.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+80a5052f[ ]+amomin.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+c0a5052f[ ]+amominu.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+04a5052f[ ]+amoadd.b.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+0ca5052f[ ]+amoswap.b.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+64a5052f[ ]+amoand.b.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+44a5052f[ ]+amoor.b.aq[ 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]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+02a5052f[ ]+amoadd.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+0aa5052f[ ]+amoswap.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+62a5052f[ ]+amoand.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+42a5052f[ ]+amoor.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+22a5052f[ ]+amoxor.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+a2a5052f[ ]+amomax.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+e2a5052f[ ]+amomaxu.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+82a5052f[ ]+amomin.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+c2a5052f[ ]+amominu.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+06a5052f[ ]+amoadd.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+0ea5052f[ ]+amoswap.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+66a5052f[ ]+amoand.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+46a5052f[ ]+amoor.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+26a5052f[ ]+amoxor.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+a6a5052f[ ]+amomax.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+e6a5052f[ ]+amomaxu.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+86a5052f[ ]+amomin.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+c6a5052f[ ]+amominu.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+00a5152f[ ]+amoadd.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+08a5152f[ ]+amoswap.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+60a5152f[ ]+amoand.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+40a5152f[ ]+amoor.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+20a5152f[ ]+amoxor.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+a0a5152f[ ]+amomax.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+e0a5152f[ ]+amomaxu.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+80a5152f[ ]+amomin.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+c0a5152f[ ]+amominu.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+04a5152f[ ]+amoadd.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+0ca5152f[ ]+amoswap.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+64a5152f[ ]+amoand.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+44a5152f[ ]+amoor.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+24a5152f[ ]+amoxor.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+a4a5152f[ ]+amomax.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+e4a5152f[ ]+amomaxu.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+84a5152f[ ]+amomin.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+c4a5152f[ ]+amominu.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+02a5152f[ ]+amoadd.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+0aa5152f[ ]+amoswap.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+62a5152f[ ]+amoand.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+42a5152f[ ]+amoor.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+22a5152f[ ]+amoxor.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+a2a5152f[ ]+amomax.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+e2a5152f[ ]+amomaxu.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+82a5152f[ ]+amomin.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+c2a5152f[ ]+amominu.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+06a5152f[ ]+amoadd.h.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+0ea5152f[ ]+amoswap.h.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+66a5152f[ ]+amoand.h.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+46a5152f[ ]+amoor.h.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+26a5152f[ ]+amoxor.h.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+a6a5152f[ ]+amomax.h.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+e6a5152f[ ]+amomaxu.h.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+86a5152f[ ]+amomin.h.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+c6a5152f[ ]+amominu.h.aqrl[ ]+a0,a0,\(a0\) +diff --git a/gas/testsuite/gas/riscv/zabha.s b/gas/testsuite/gas/riscv/zabha.s +new file mode 100644 +index 00000000000..82b811a44e7 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zabha.s +@@ -0,0 +1,73 @@ ++target: ++ amoadd.b a0, a0, 0(a0) ++ amoswap.b a0, a0, 0(a0) ++ amoand.b a0, a0, 0(a0) ++ amoor.b a0, a0, 0(a0) ++ amoxor.b a0, a0, 0(a0) ++ amomax.b a0, a0, 0(a0) ++ amomaxu.b a0, a0, 0(a0) ++ amomin.b a0, a0, 0(a0) ++ amominu.b a0, a0, 0(a0) ++ amoadd.b.aq a0, a0, 0(a0) ++ amoswap.b.aq a0, a0, 0(a0) ++ amoand.b.aq a0, a0, 0(a0) ++ amoor.b.aq a0, a0, 0(a0) ++ amoxor.b.aq a0, a0, 0(a0) ++ amomax.b.aq a0, a0, 0(a0) ++ amomaxu.b.aq a0, a0, 0(a0) ++ amomin.b.aq a0, a0, 0(a0) ++ amominu.b.aq a0, a0, 0(a0) ++ amoadd.b.rl a0, a0, 0(a0) ++ amoswap.b.rl a0, a0, 0(a0) ++ amoand.b.rl a0, a0, 0(a0) ++ amoor.b.rl a0, a0, 0(a0) ++ amoxor.b.rl a0, a0, 0(a0) ++ amomax.b.rl a0, a0, 0(a0) ++ amomaxu.b.rl a0, a0, 0(a0) ++ amomin.b.rl a0, a0, 0(a0) ++ amominu.b.rl a0, a0, 0(a0) ++ amoadd.b.aqrl a0, a0, 0(a0) ++ amoswap.b.aqrl a0, a0, 0(a0) ++ amoand.b.aqrl a0, a0, 0(a0) ++ amoor.b.aqrl a0, a0, 0(a0) ++ amoxor.b.aqrl a0, a0, 0(a0) ++ amomax.b.aqrl a0, a0, 0(a0) ++ amomaxu.b.aqrl a0, a0, 0(a0) ++ amomin.b.aqrl a0, a0, 0(a0) ++ amominu.b.aqrl a0, a0, 0(a0) ++ amoadd.h a0, a0, 0(a0) ++ amoswap.h a0, a0, 0(a0) ++ amoand.h a0, a0, 0(a0) ++ amoor.h a0, a0, 0(a0) ++ amoxor.h a0, a0, 0(a0) ++ amomax.h a0, a0, 0(a0) ++ amomaxu.h a0, a0, 0(a0) ++ amomin.h a0, a0, 0(a0) ++ amominu.h a0, a0, 0(a0) ++ amoadd.h.aq a0, a0, 0(a0) ++ amoswap.h.aq a0, a0, 0(a0) ++ amoand.h.aq a0, a0, 0(a0) ++ amoor.h.aq a0, a0, 0(a0) ++ amoxor.h.aq a0, a0, 0(a0) ++ amomax.h.aq a0, a0, 0(a0) ++ amomaxu.h.aq a0, a0, 0(a0) ++ amomin.h.aq a0, a0, 0(a0) ++ amominu.h.aq a0, a0, 0(a0) ++ amoadd.h.rl a0, a0, 0(a0) ++ amoswap.h.rl a0, a0, 0(a0) ++ amoand.h.rl a0, a0, 0(a0) ++ amoor.h.rl a0, a0, 0(a0) ++ amoxor.h.rl a0, a0, 0(a0) ++ amomax.h.rl a0, a0, 0(a0) ++ amomaxu.h.rl a0, a0, 0(a0) ++ amomin.h.rl a0, a0, 0(a0) ++ amominu.h.rl a0, a0, 0(a0) ++ amoadd.h.aqrl a0, a0, 0(a0) ++ amoswap.h.aqrl a0, a0, 0(a0) ++ amoand.h.aqrl a0, a0, 0(a0) ++ amoor.h.aqrl a0, a0, 0(a0) ++ amoxor.h.aqrl a0, a0, 0(a0) ++ amomax.h.aqrl a0, a0, 0(a0) ++ amomaxu.h.aqrl a0, a0, 0(a0) ++ amomin.h.aqrl a0, a0, 0(a0) ++ amominu.h.aqrl a0, a0, 0(a0) +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index fe5b5630b7b..c0b17b7031e 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -235,6 +235,42 @@ + #define MASK_LR_D 0xf9f0707f + #define MATCH_SC_D 0x1800302f + #define MASK_SC_D 0xf800707f ++#define MATCH_AMOADD_B 0x02f ++#define MASK_AMOADD_B 0xf800707f ++#define MATCH_AMOXOR_B 0x2000002f ++#define MASK_AMOXOR_B 0xf800707f ++#define MATCH_AMOOR_B 0x4000002f ++#define MASK_AMOOR_B 0xf800707f ++#define MATCH_AMOAND_B 0x6000002f ++#define MASK_AMOAND_B 0xf800707f ++#define MATCH_AMOMIN_B 0x8000002f ++#define MASK_AMOMIN_B 0xf800707f ++#define MATCH_AMOMAX_B 0xa000002f ++#define MASK_AMOMAX_B 0xf800707f ++#define MATCH_AMOMINU_B 0xc000002f ++#define MASK_AMOMINU_B 0xf800707f ++#define MATCH_AMOMAXU_B 0xe000002f ++#define MASK_AMOMAXU_B 0xf800707f ++#define MATCH_AMOSWAP_B 0x800002f ++#define MASK_AMOSWAP_B 0xf800707f ++#define MATCH_AMOADD_H 0x102f ++#define MASK_AMOADD_H 0xf800707f ++#define MATCH_AMOXOR_H 0x2000102f ++#define MASK_AMOXOR_H 0xf800707f ++#define MATCH_AMOOR_H 0x4000102f ++#define MASK_AMOOR_H 0xf800707f ++#define MATCH_AMOAND_H 0x6000102f ++#define MASK_AMOAND_H 0xf800707f ++#define MATCH_AMOMIN_H 0x8000102f ++#define MASK_AMOMIN_H 0xf800707f ++#define MATCH_AMOMAX_H 0xa000102f ++#define MASK_AMOMAX_H 0xf800707f ++#define MATCH_AMOMINU_H 0xc000102f ++#define MASK_AMOMINU_H 0xf800707f ++#define MATCH_AMOMAXU_H 0xe000102f ++#define MASK_AMOMAXU_H 0xf800707f ++#define MATCH_AMOSWAP_H 0x800102f ++#define MASK_AMOSWAP_H 0xf800707f + #define MATCH_ECALL 0x73 + #define MASK_ECALL 0xffffffff + #define MATCH_EBREAK 0x100073 +@@ -3590,6 +3626,24 @@ DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) + DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) + DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) + DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) ++DECLARE_INSN(amoadd_b, MATCH_AMOADD_B, MASK_AMOADD_B) ++DECLARE_INSN(amoxor_b, MATCH_AMOXOR_B, MASK_AMOXOR_B) ++DECLARE_INSN(amoor_b, MATCH_AMOOR_B, MASK_AMOOR_B) ++DECLARE_INSN(amoand_b, MATCH_AMOAND_B, MASK_AMOAND_B) ++DECLARE_INSN(amomin_b, MATCH_AMOMIN_B, MASK_AMOMIN_B) ++DECLARE_INSN(amomax_b, MATCH_AMOMAX_B, MASK_AMOMAX_B) ++DECLARE_INSN(amominu_b, MATCH_AMOMINU_B, MASK_AMOMINU_B) ++DECLARE_INSN(amomaxu_b, MATCH_AMOMAXU_B, MASK_AMOMAXU_B) ++DECLARE_INSN(amoswap_b, MATCH_AMOSWAP_B, MASK_AMOSWAP_B) ++DECLARE_INSN(amoadd_h, MATCH_AMOADD_H, MASK_AMOADD_H) ++DECLARE_INSN(amoxor_h, MATCH_AMOXOR_H, MASK_AMOXOR_H) ++DECLARE_INSN(amoor_h, MATCH_AMOOR_H, MASK_AMOOR_H) ++DECLARE_INSN(amoand_h, MATCH_AMOAND_H, MASK_AMOAND_H) ++DECLARE_INSN(amomin_h, MATCH_AMOMIN_H, MASK_AMOMIN_H) ++DECLARE_INSN(amomax_h, MATCH_AMOMAX_H, MASK_AMOMAX_H) ++DECLARE_INSN(amominu_h, MATCH_AMOMINU_H, MASK_AMOMINU_H) ++DECLARE_INSN(amomaxu_h, MATCH_AMOMAXU_H, MASK_AMOMAXU_H) ++DECLARE_INSN(amoswap_h, MATCH_AMOSWAP_H, MASK_AMOSWAP_H) + DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) + DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) + DECLARE_INSN(uret, MATCH_URET, MASK_URET) +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index 8f2b7fdf061..1e5adbf5abf 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -471,6 +471,7 @@ enum riscv_insn_class + INSN_CLASS_ZICBOM, + INSN_CLASS_ZICBOP, + INSN_CLASS_ZICBOZ, ++ INSN_CLASS_ZABHA, + INSN_CLASS_H, + INSN_CLASS_XCVMAC, + INSN_CLASS_XCVALU, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index dec2f41e30c..a61ebfc74e5 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -659,6 +659,80 @@ const struct riscv_opcode riscv_opcodes[] = + {"amomin.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, + {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, + ++/* Byte and Halfword Atomic Memory Operations instruction subset. */ ++{"amoadd.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoswap.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoand.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoor.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoxor.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomax.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomaxu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomin.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amominu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoadd.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQ, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoswap.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQ, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoand.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQ, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoor.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_AQ, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoxor.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_AQ, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomax.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_AQ, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomaxu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQ, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomin.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQ, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amominu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQ, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoadd.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_RL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoswap.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_RL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoand.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_RL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoor.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_RL, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoxor.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_RL, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomax.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_RL, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomaxu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_RL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomin.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_RL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amominu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_RL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoadd.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQRL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoswap.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQRL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoand.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQRL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoor.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_B|MASK_AQRL, MASK_AMOOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoxor.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_B|MASK_AQRL, MASK_AMOXOR_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomax.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_B|MASK_AQRL, MASK_AMOMAX_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomaxu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQRL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amomin.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQRL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amominu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQRL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amoadd.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoswap.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoand.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoor.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoxor.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomax.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomaxu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomin.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amominu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoadd.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQ, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoswap.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQ, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoand.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQ, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoor.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_AQ, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoxor.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_AQ, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomax.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_AQ, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomaxu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQ, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomin.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQ, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amominu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQ, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoadd.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_RL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoswap.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_RL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoand.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_RL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoor.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_RL, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoxor.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_RL, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomax.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_RL, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomaxu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_RL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomin.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_RL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amominu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_RL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoadd.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQRL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoswap.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQRL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoand.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQRL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoor.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOOR_H|MASK_AQRL, MASK_AMOOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amoxor.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOXOR_H|MASK_AQRL, MASK_AMOXOR_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomax.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAX_H|MASK_AQRL, MASK_AMOMAX_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomaxu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQRL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amomin.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQRL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amominu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQRL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++ + /* Multiply/Divide instruction subset. */ + {"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS }, + {"mul", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, +-- +2.27.0 + diff --git a/RISC-V-2-Support-Zabha-extension.patch b/RISC-V-2-Support-Zabha-extension.patch new file mode 100644 index 0000000000000000000000000000000000000000..545b489d30d6a3540fdcb2ee3e0978cda51f85b6 --- /dev/null +++ b/RISC-V-2-Support-Zabha-extension.patch @@ -0,0 +1,90 @@ +From c45078f6868391b0fd661c7d8b449a909bce5d50 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Wed, 28 Feb 2024 16:27:17 +0800 +Subject: [PATCH] RISC-V: Support Zabha extension. + +The Zabha extension[1] supports for byte and halfword +atomic memory operations. This patch add all instructions +include in Zabha. Further work is waiting Zacas[2] merge. + +[1] https://github.com/riscv/riscv-zabha/tags +[2] https://sourceware.org/pipermail/binutils/2023-May/127700.html + +Version log: +Add new imply relation that Zabha extension implies A extension. + +bfd/ChangeLog: + + * elfxx-riscv.c (riscv_implicit_subsets): New imply. + (riscv_multi_subset_supports): New extension. + (riscv_multi_subset_supports_ext): Ditto. + +gas/ChangeLog: + + * testsuite/gas/riscv/zabha-32.d: New test. + * testsuite/gas/riscv/zabha.d: New test. + * testsuite/gas/riscv/zabha.s: New test. + +include/ChangeLog: + + * opcode/riscv-opc.h (MATCH_AMOADD_B): New opcodes. + (MASK_AMOADD_B): Ditto. + (MATCH_AMOXOR_B): Ditto. + (MASK_AMOXOR_B): Ditto. + (MATCH_AMOOR_B): Ditto. + (MASK_AMOOR_B): Ditto. + (MATCH_AMOAND_B): Ditto. + (MASK_AMOAND_B): Ditto. + (MATCH_AMOMIN_B): Ditto. + (MASK_AMOMIN_B): Ditto. + (MATCH_AMOMAX_B): Ditto. + (MASK_AMOMAX_B): Ditto. + (MATCH_AMOMINU_B): Ditto. + (MASK_AMOMINU_B): Ditto. + (MATCH_AMOMAXU_B): Ditto. + (MASK_AMOMAXU_B): Ditto. + (MATCH_AMOSWAP_B): Ditto. + (MASK_AMOSWAP_B): Ditto. + (MATCH_AMOADD_H): Ditto. + (MASK_AMOADD_H): Ditto. + (MATCH_AMOXOR_H): Ditto. + (MASK_AMOXOR_H): Ditto. + (MATCH_AMOOR_H): Ditto. + (MASK_AMOOR_H): Ditto. + (MATCH_AMOAND_H): Ditto. + (MASK_AMOAND_H): Ditto. + (MATCH_AMOMIN_H): Ditto. + (MASK_AMOMIN_H): Ditto. + (MATCH_AMOMAX_H): Ditto. + (MASK_AMOMAX_H): Ditto. + (MATCH_AMOMINU_H): Ditto. + (MASK_AMOMINU_H): Ditto. + (MATCH_AMOMAXU_H): Ditto. + (MASK_AMOMAXU_H): Ditto. + (MATCH_AMOSWAP_H): Ditto. + (MASK_AMOSWAP_H): Ditto. + (DECLARE_INSN): New declare. + * opcode/riscv.h (enum riscv_insn_class): New class. + +opcodes/ChangeLog: + + * riscv-opc.c: New instructions. +--- + bfd/elfxx-riscv.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index be996167960..b4a0139196b 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1122,6 +1122,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"zvfbfmin", "zve32f", check_implicit_always}, + {"zvfbfwma", "zve32f", check_implicit_always}, + {"zvfbfwma", "zfbfmin", check_implicit_always}, ++ {"zabha", "a", check_implicit_always}, + {"zvfh", "zvfhmin", check_implicit_always}, + {"zvfh", "zfhmin", check_implicit_always}, + {"zvfhmin", "zve32f", check_implicit_always}, +-- +2.27.0 + diff --git a/RISC-V-Add-Smrnmi-extension-csrs.patch b/RISC-V-Add-Smrnmi-extension-csrs.patch new file mode 100644 index 0000000000000000000000000000000000000000..494e6c872a4c677f11e1ca4bac831c97552991cd --- /dev/null +++ b/RISC-V-Add-Smrnmi-extension-csrs.patch @@ -0,0 +1,283 @@ +From 2a8bfd92a81ba12a24f0fef32df38d8488d8d969 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Tue, 24 Sep 2024 19:16:25 +0800 +Subject: [PATCH] RISC-V: Add Smrnmi extension csrs. + +This patch support Smrnmi extension[1], +The csrs address can be find in[2]. + +[1] https://github.com/riscv/riscv-isa-manual/commit/35eb3948bf0b87c83fab5a7238bd68b6211faf62 +[2] https://github.com/riscv/riscv-isa-manual/blob/smrnmi-1.0/src/priv-csrs.adoc + +bfd/ChangeLog: + + * elfxx-riscv.c: New extension. + +gas/ChangeLog: + + * NEWS: Add Smrnmi extension support. + * config/tc-riscv.c (enum riscv_csr_class): New extension class. + (riscv_csr_address): Ditto. + * testsuite/gas/riscv/csr-version-1p10.d: New csrs. + * testsuite/gas/riscv/csr-version-1p10.l: Ditto. + * testsuite/gas/riscv/csr-version-1p11.d: Ditto. + * testsuite/gas/riscv/csr-version-1p11.l: Ditto. + * testsuite/gas/riscv/csr-version-1p12.d: Ditto. + * testsuite/gas/riscv/csr-version-1p12.l: Ditto. + * testsuite/gas/riscv/csr.s: Ditto. + * testsuite/gas/riscv/march-help.l: New extension. + +include/ChangeLog: + + * opcode/riscv-opc.h (CSR_MNSCRATCH): New csr. + (CSR_MNEPC): Ditto. + (CSR_MNCAUSE): Ditto. + (CSR_MNSTATUS): Ditto. + (DECLARE_CSR): New csr declarations. +--- + bfd/elfxx-riscv.c | 1 + + gas/NEWS | 21 +++++++++++++++++++++ + gas/config/tc-riscv.c | 4 ++++ + gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++ + gas/testsuite/gas/riscv/csr-version-1p10.l | 16 ++++++++++++++++ + gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++ + gas/testsuite/gas/riscv/csr-version-1p11.l | 16 ++++++++++++++++ + gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++ + gas/testsuite/gas/riscv/csr-version-1p12.l | 16 ++++++++++++++++ + gas/testsuite/gas/riscv/csr.s | 6 ++++++ + gas/testsuite/gas/riscv/march-help.l | 1 + + include/opcode/riscv-opc.h | 10 ++++++++++ + 12 files changed, 115 insertions(+) + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 212d83728df..08758faf728 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1393,6 +1393,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = + {"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smctr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"smrnmi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssccfg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c +index 869837e7964..289c20bf3dc 100644 +--- a/gas/config/tc-riscv.c ++++ b/gas/config/tc-riscv.c +@@ -81,6 +81,7 @@ enum riscv_csr_class + CSR_CLASS_SMCSRIND, /* Smcsrind */ + CSR_CLASS_SMCNTRPMF, /* Smcntrpmf */ + CSR_CLASS_SMCNTRPMF_32, /* Smcntrpmf, rv32 only */ ++ CSR_CLASS_SMRNMI, /* Smrnmi */ + CSR_CLASS_SMSTATEEN, /* Smstateen only */ + CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */ + CSR_CLASS_SMCTR, /* Smctr */ +@@ -1081,6 +1082,9 @@ riscv_csr_address (const char *csr_name, + need_check_version = true; + extension = "smcntrpmf"; + break; ++ case CSR_CLASS_SMRNMI: ++ extension = "smrnmi"; ++ break; + case CSR_CLASS_SMSTATEEN_32: + is_rv32_only = true; + /* Fall through. */ +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d +index 57e6b27e32c..e74da2d0b59 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.d +@@ -645,6 +645,14 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1 + [ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh + [ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1 ++[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc ++[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 ++[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause ++[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 ++[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch ++[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 ++[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus ++[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 + [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 + [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 + [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l +index 1d1299183e7..d1d2a9f6adc 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.l +@@ -941,6 +941,22 @@ + .*Info: macro .* + .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension + .*Info: macro .* ++.*Warning: invalid CSR `mnepc', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnepc', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mncause', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mncause', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension ++.*Info: macro .* + .*Warning: invalid CSR `mstateen0', needs `smstateen' extension + .*Info: macro .* + .*Warning: invalid CSR `mstateen0', needs `smstateen' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d +index e948481d72d..a9d4276a7d8 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.d +@@ -645,6 +645,14 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1 + [ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh + [ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1 ++[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc ++[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 ++[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause ++[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 ++[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch ++[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 ++[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus ++[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 + [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 + [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 + [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l +index aa649eb51b9..8888854e61e 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.l +@@ -937,6 +937,22 @@ + .*Info: macro .* + .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension + .*Info: macro .* ++.*Warning: invalid CSR `mnepc', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnepc', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mncause', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mncause', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension ++.*Info: macro .* + .*Warning: invalid CSR `mstateen0', needs `smstateen' extension + .*Info: macro .* + .*Warning: invalid CSR `mstateen0', needs `smstateen' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d +index 5075ef3bfba..4b90845aa0f 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.d +@@ -645,6 +645,14 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1 + [ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh + [ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1 ++[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc ++[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1 ++[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause ++[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1 ++[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch ++[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1 ++[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus ++[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1 + [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0 + [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1 + [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1 +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l +index a88c88cb760..ce262703cc8 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.l +@@ -661,6 +661,22 @@ + .*Info: macro .* + .*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension + .*Info: macro .* ++.*Warning: invalid CSR `mnepc', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnepc', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mncause', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mncause', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension ++.*Info: macro .* + .*Warning: invalid CSR `mstateen0', needs `smstateen' extension + .*Info: macro .* + .*Warning: invalid CSR `mstateen0', needs `smstateen' extension +diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s +index 79c7758111c..ad071839bb0 100644 +--- a/gas/testsuite/gas/riscv/csr.s ++++ b/gas/testsuite/gas/riscv/csr.s +@@ -365,6 +365,12 @@ + csr mcyclecfgh + csr minstretcfgh + ++ # smrnmi ++ csr mnepc ++ csr mncause ++ csr mnscratch ++ csr mnstatus ++ + # Smstateen/Ssstateen extensions + csr mstateen0 + csr mstateen1 +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index 5d940249e2b..4a9bac5c7f0 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -100,6 +100,7 @@ All available -march extensions for RISC-V: + smcntrpmf 1.0 + smctr 1.0 + smepmp 1.0 ++ smrnmi 1.0 + smstateen 1.0 + ssaia 1.0 + ssccfg 1.0 +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index 506ddd492d7..b9ea042cc1a 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -3417,6 +3417,11 @@ + #define CSR_MINSTRETCFG 0x322 + #define CSR_MCYCLECFGH 0x721 + #define CSR_MINSTRETCFGH 0x722 ++/* Smrnmi extension. */ ++#define CSR_MNSCRATCH 0x740 ++#define CSR_MNEPC 0x741 ++#define CSR_MNCAUSE 0x742 ++#define CSR_MNSTATUS 0x744 + /* Smstateen extension */ + #define CSR_MSTATEEN0 0x30c + #define CSR_MSTATEEN1 0x30d +@@ -4461,6 +4466,11 @@ DECLARE_CSR(mcyclecfg, CSR_MCYCLECFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, + DECLARE_CSR(minstretcfg, CSR_MINSTRETCFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mcyclecfgh, CSR_MCYCLECFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(minstretcfgh, CSR_MINSTRETCFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++/* Smrnmi extensions. */ ++DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + /* Smstateen/Ssstateen extensions. */ + DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +-- +2.27.0 + diff --git a/RISC-V-Add-Zabha-extension-CAS-instructions.patch b/RISC-V-Add-Zabha-extension-CAS-instructions.patch new file mode 100644 index 0000000000000000000000000000000000000000..277f31eb8fb482691456a0fe595c10c3f99a72fd --- /dev/null +++ b/RISC-V-Add-Zabha-extension-CAS-instructions.patch @@ -0,0 +1,384 @@ +From 3184210ab70ec9400efae5a98c84fb3b4dd7600c Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Fri, 28 Jun 2024 00:13:54 +0800 +Subject: [PATCH] RISC-V: Add Zabha extension CAS instructions. + +This patch update the cas instruction in Zabha extension [1], +when both Zabha and Zacas extension enabled. + +[1] https://github.com/riscv/riscv-zabha/tags + +bfd/ChangeLog: + + * elfxx-riscv.c (riscv_multi_subset_supports): New extension case. + +gas/ChangeLog: + + * testsuite/gas/riscv/zabha-32.d: New instructions. + * testsuite/gas/riscv/zabha.d: Ditto. + * testsuite/gas/riscv/zabha.s: Ditto. + +include/ChangeLog: + + * opcode/riscv-opc.h (MATCH_AMOCAS_B): New opcodes. + (MASK_AMOCAS_B): Ditto. + (MATCH_AMOCAS_H): Ditto. + (MASK_AMOCAS_H): Ditto. + (DECLARE_INSN): New instructions. + * opcode/riscv.h (enum riscv_insn_class): New class case. + +opcodes/ChangeLog: + + * riscv-opc.c: New instructions. +--- + bfd/elfxx-riscv.c | 3 +++ + gas/testsuite/gas/riscv/zabha-32.d | 10 +++++++++- + gas/testsuite/gas/riscv/zabha.d | 10 +++++++++- + gas/testsuite/gas/riscv/zabha.s | 8 ++++++++ + include/opcode/riscv-opc.h | 6 ++++++ + include/opcode/riscv.h | 1 + + opcodes/riscv-opc.c | 8 ++++++++ + 7 files changed, 44 insertions(+), 2 deletions(-) + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 1ea65463985..0b3e7f8cd67 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -2523,6 +2523,9 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + return riscv_subset_supports (rps, "zabha"); + case INSN_CLASS_ZACAS: + return riscv_subset_supports (rps, "zacas"); ++ case INSN_CLASS_ZABHA_AND_ZACAS: ++ return (riscv_subset_supports (rps, "zabha") ++ && riscv_subset_supports (rps, "zacas")); + case INSN_CLASS_ZALRSC: + return riscv_subset_supports (rps, "zalrsc"); + case INSN_CLASS_ZAWRS: +diff --git a/gas/testsuite/gas/riscv/zabha-32.d b/gas/testsuite/gas/riscv/zabha-32.d +index 1e6427ea752..7836ae9acc6 100644 +--- a/gas/testsuite/gas/riscv/zabha-32.d ++++ b/gas/testsuite/gas/riscv/zabha-32.d +@@ -1,4 +1,4 @@ +-#as: -march=rv32i_zabha ++#as: -march=rv32i_zabha_zacas + #source: zabha.s + #objdump: -d -Mno-aliases + +@@ -16,6 +16,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e0a5052f[ ]+amomaxu.b[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+80a5052f[ ]+amomin.b[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c0a5052f[ ]+amominu.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5052f[ ]+amocas.b[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+04a5052f[ ]+amoadd.b.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0ca5052f[ ]+amoswap.b.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+64a5052f[ ]+amoand.b.aq[ ]+a0,a0,\(a0\) +@@ -25,6 +26,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e4a5052f[ ]+amomaxu.b.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+84a5052f[ ]+amomin.b.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c4a5052f[ ]+amominu.b.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5052f[ ]+amocas.b.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+02a5052f[ ]+amoadd.b.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0aa5052f[ ]+amoswap.b.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+62a5052f[ ]+amoand.b.rl[ ]+a0,a0,\(a0\) +@@ -34,6 +36,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e2a5052f[ ]+amomaxu.b.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+82a5052f[ ]+amomin.b.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c2a5052f[ ]+amominu.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5052f[ ]+amocas.b.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+06a5052f[ ]+amoadd.b.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0ea5052f[ ]+amoswap.b.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+66a5052f[ ]+amoand.b.aqrl[ ]+a0,a0,\(a0\) +@@ -43,6 +46,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e6a5052f[ ]+amomaxu.b.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+86a5052f[ ]+amomin.b.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c6a5052f[ ]+amominu.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5052f[ ]+amocas.b.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+00a5152f[ ]+amoadd.h[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+08a5152f[ ]+amoswap.h[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+60a5152f[ ]+amoand.h[ ]+a0,a0,\(a0\) +@@ -52,6 +56,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e0a5152f[ ]+amomaxu.h[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+80a5152f[ ]+amomin.h[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c0a5152f[ ]+amominu.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5152f[ ]+amocas.h[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+04a5152f[ ]+amoadd.h.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0ca5152f[ ]+amoswap.h.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+64a5152f[ ]+amoand.h.aq[ ]+a0,a0,\(a0\) +@@ -61,6 +66,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e4a5152f[ ]+amomaxu.h.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+84a5152f[ ]+amomin.h.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c4a5152f[ ]+amominu.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5152f[ ]+amocas.h.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+02a5152f[ ]+amoadd.h.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0aa5152f[ ]+amoswap.h.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+62a5152f[ ]+amoand.h.rl[ ]+a0,a0,\(a0\) +@@ -70,6 +76,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e2a5152f[ ]+amomaxu.h.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+82a5152f[ ]+amomin.h.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c2a5152f[ ]+amominu.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5152f[ ]+amocas.h.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+06a5152f[ ]+amoadd.h.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0ea5152f[ ]+amoswap.h.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+66a5152f[ ]+amoand.h.aqrl[ ]+a0,a0,\(a0\) +@@ -79,3 +86,4 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e6a5152f[ ]+amomaxu.h.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+86a5152f[ ]+amomin.h.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c6a5152f[ ]+amominu.h.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5152f[ ]+amocas.h.aqrl[ ]+a0,a0,\(a0\) +diff --git a/gas/testsuite/gas/riscv/zabha.d b/gas/testsuite/gas/riscv/zabha.d +index 7000452b6d1..86e2eb29f34 100644 +--- a/gas/testsuite/gas/riscv/zabha.d ++++ b/gas/testsuite/gas/riscv/zabha.d +@@ -1,4 +1,4 @@ +-#as: -march=rv64i_zabha ++#as: -march=rv64i_zabha_zacas + #source: zabha.s + #objdump: -d -Mno-aliases + +@@ -16,6 +16,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e0a5052f[ ]+amomaxu.b[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+80a5052f[ ]+amomin.b[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c0a5052f[ ]+amominu.b[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5052f[ ]+amocas.b[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+04a5052f[ ]+amoadd.b.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0ca5052f[ ]+amoswap.b.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+64a5052f[ ]+amoand.b.aq[ ]+a0,a0,\(a0\) +@@ -25,6 +26,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e4a5052f[ ]+amomaxu.b.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+84a5052f[ ]+amomin.b.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c4a5052f[ ]+amominu.b.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5052f[ ]+amocas.b.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+02a5052f[ ]+amoadd.b.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0aa5052f[ ]+amoswap.b.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+62a5052f[ ]+amoand.b.rl[ ]+a0,a0,\(a0\) +@@ -34,6 +36,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e2a5052f[ ]+amomaxu.b.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+82a5052f[ ]+amomin.b.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c2a5052f[ ]+amominu.b.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5052f[ ]+amocas.b.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+06a5052f[ ]+amoadd.b.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0ea5052f[ ]+amoswap.b.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+66a5052f[ ]+amoand.b.aqrl[ ]+a0,a0,\(a0\) +@@ -43,6 +46,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e6a5052f[ ]+amomaxu.b.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+86a5052f[ ]+amomin.b.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c6a5052f[ ]+amominu.b.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5052f[ ]+amocas.b.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+00a5152f[ ]+amoadd.h[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+08a5152f[ ]+amoswap.h[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+60a5152f[ ]+amoand.h[ ]+a0,a0,\(a0\) +@@ -52,6 +56,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e0a5152f[ ]+amomaxu.h[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+80a5152f[ ]+amomin.h[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c0a5152f[ ]+amominu.h[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5152f[ ]+amocas.h[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+04a5152f[ ]+amoadd.h.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0ca5152f[ ]+amoswap.h.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+64a5152f[ ]+amoand.h.aq[ ]+a0,a0,\(a0\) +@@ -61,6 +66,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e4a5152f[ ]+amomaxu.h.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+84a5152f[ ]+amomin.h.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c4a5152f[ ]+amominu.h.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5152f[ ]+amocas.h.aq[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+02a5152f[ ]+amoadd.h.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0aa5152f[ ]+amoswap.h.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+62a5152f[ ]+amoand.h.rl[ ]+a0,a0,\(a0\) +@@ -70,6 +76,7 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e2a5152f[ ]+amomaxu.h.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+82a5152f[ ]+amomin.h.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c2a5152f[ ]+amominu.h.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5152f[ ]+amocas.h.rl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+06a5152f[ ]+amoadd.h.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+0ea5152f[ ]+amoswap.h.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+66a5152f[ ]+amoand.h.aqrl[ ]+a0,a0,\(a0\) +@@ -79,3 +86,4 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+e6a5152f[ ]+amomaxu.h.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+86a5152f[ ]+amomin.h.aqrl[ ]+a0,a0,\(a0\) + [ ]+[0-9a-f]+:[ ]+c6a5152f[ ]+amominu.h.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5152f[ ]+amocas.h.aqrl[ ]+a0,a0,\(a0\) +diff --git a/gas/testsuite/gas/riscv/zabha.s b/gas/testsuite/gas/riscv/zabha.s +index 82b811a44e7..4c4fd17cf5d 100644 +--- a/gas/testsuite/gas/riscv/zabha.s ++++ b/gas/testsuite/gas/riscv/zabha.s +@@ -8,6 +8,7 @@ target: + amomaxu.b a0, a0, 0(a0) + amomin.b a0, a0, 0(a0) + amominu.b a0, a0, 0(a0) ++ amocas.b a0, a0, 0(a0) + amoadd.b.aq a0, a0, 0(a0) + amoswap.b.aq a0, a0, 0(a0) + amoand.b.aq a0, a0, 0(a0) +@@ -17,6 +18,7 @@ target: + amomaxu.b.aq a0, a0, 0(a0) + amomin.b.aq a0, a0, 0(a0) + amominu.b.aq a0, a0, 0(a0) ++ amocas.b.aq a0, a0, 0(a0) + amoadd.b.rl a0, a0, 0(a0) + amoswap.b.rl a0, a0, 0(a0) + amoand.b.rl a0, a0, 0(a0) +@@ -26,6 +28,7 @@ target: + amomaxu.b.rl a0, a0, 0(a0) + amomin.b.rl a0, a0, 0(a0) + amominu.b.rl a0, a0, 0(a0) ++ amocas.b.rl a0, a0, 0(a0) + amoadd.b.aqrl a0, a0, 0(a0) + amoswap.b.aqrl a0, a0, 0(a0) + amoand.b.aqrl a0, a0, 0(a0) +@@ -35,6 +38,7 @@ target: + amomaxu.b.aqrl a0, a0, 0(a0) + amomin.b.aqrl a0, a0, 0(a0) + amominu.b.aqrl a0, a0, 0(a0) ++ amocas.b.aqrl a0, a0, 0(a0) + amoadd.h a0, a0, 0(a0) + amoswap.h a0, a0, 0(a0) + amoand.h a0, a0, 0(a0) +@@ -44,6 +48,7 @@ target: + amomaxu.h a0, a0, 0(a0) + amomin.h a0, a0, 0(a0) + amominu.h a0, a0, 0(a0) ++ amocas.h a0, a0, 0(a0) + amoadd.h.aq a0, a0, 0(a0) + amoswap.h.aq a0, a0, 0(a0) + amoand.h.aq a0, a0, 0(a0) +@@ -53,6 +58,7 @@ target: + amomaxu.h.aq a0, a0, 0(a0) + amomin.h.aq a0, a0, 0(a0) + amominu.h.aq a0, a0, 0(a0) ++ amocas.h.aq a0, a0, 0(a0) + amoadd.h.rl a0, a0, 0(a0) + amoswap.h.rl a0, a0, 0(a0) + amoand.h.rl a0, a0, 0(a0) +@@ -62,6 +68,7 @@ target: + amomaxu.h.rl a0, a0, 0(a0) + amomin.h.rl a0, a0, 0(a0) + amominu.h.rl a0, a0, 0(a0) ++ amocas.h.rl a0, a0, 0(a0) + amoadd.h.aqrl a0, a0, 0(a0) + amoswap.h.aqrl a0, a0, 0(a0) + amoand.h.aqrl a0, a0, 0(a0) +@@ -71,3 +78,4 @@ target: + amomaxu.h.aqrl a0, a0, 0(a0) + amomin.h.aqrl a0, a0, 0(a0) + amominu.h.aqrl a0, a0, 0(a0) ++ amocas.h.aqrl a0, a0, 0(a0) +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index 381cfe08b3d..24b7d3a67f4 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -253,6 +253,8 @@ + #define MASK_AMOMAXU_B 0xf800707f + #define MATCH_AMOSWAP_B 0x800002f + #define MASK_AMOSWAP_B 0xf800707f ++#define MATCH_AMOCAS_B 0x2800002f ++#define MASK_AMOCAS_B 0xf800707f + #define MATCH_AMOADD_H 0x102f + #define MASK_AMOADD_H 0xf800707f + #define MATCH_AMOXOR_H 0x2000102f +@@ -271,6 +273,8 @@ + #define MASK_AMOMAXU_H 0xf800707f + #define MATCH_AMOSWAP_H 0x800102f + #define MASK_AMOSWAP_H 0xf800707f ++#define MATCH_AMOCAS_H 0x2800102f ++#define MASK_AMOCAS_H 0xf800707f + #define MATCH_ECALL 0x73 + #define MASK_ECALL 0xffffffff + #define MATCH_EBREAK 0x100073 +@@ -3774,6 +3778,7 @@ DECLARE_INSN(amomax_b, MATCH_AMOMAX_B, MASK_AMOMAX_B) + DECLARE_INSN(amominu_b, MATCH_AMOMINU_B, MASK_AMOMINU_B) + DECLARE_INSN(amomaxu_b, MATCH_AMOMAXU_B, MASK_AMOMAXU_B) + DECLARE_INSN(amoswap_b, MATCH_AMOSWAP_B, MASK_AMOSWAP_B) ++DECLARE_INSN(amocas_b, MATCH_AMOCAS_B, MASK_AMOCAS_B) + DECLARE_INSN(amoadd_h, MATCH_AMOADD_H, MASK_AMOADD_H) + DECLARE_INSN(amoxor_h, MATCH_AMOXOR_H, MASK_AMOXOR_H) + DECLARE_INSN(amoor_h, MATCH_AMOOR_H, MASK_AMOOR_H) +@@ -3783,6 +3788,7 @@ DECLARE_INSN(amomax_h, MATCH_AMOMAX_H, MASK_AMOMAX_H) + DECLARE_INSN(amominu_h, MATCH_AMOMINU_H, MASK_AMOMINU_H) + DECLARE_INSN(amomaxu_h, MATCH_AMOMAXU_H, MASK_AMOMAXU_H) + DECLARE_INSN(amoswap_h, MATCH_AMOSWAP_H, MASK_AMOSWAP_H) ++DECLARE_INSN(amocas_h, MATCH_AMOCAS_H, MASK_AMOCAS_H) + DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) + DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) + DECLARE_INSN(uret, MATCH_URET, MASK_URET) +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index bcea456efd0..13803584153 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -479,6 +479,7 @@ enum riscv_insn_class + INSN_CLASS_ZICBOZ, + INSN_CLASS_ZABHA, + INSN_CLASS_ZACAS, ++ INSN_CLASS_ZABHA_AND_ZACAS, + INSN_CLASS_H, + INSN_CLASS_XCVMAC, + INSN_CLASS_XCVALU, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index 9f42f283011..8c785e104d6 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -705,6 +705,7 @@ const struct riscv_opcode riscv_opcodes[] = + {"amomaxu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amomin.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amominu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amocas.b", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amoadd.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQ, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amoswap.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQ, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amoand.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQ, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +@@ -714,6 +715,7 @@ const struct riscv_opcode riscv_opcodes[] = + {"amomaxu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQ, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amomin.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQ, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amominu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQ, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amocas.b.aq", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_AQ, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amoadd.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_RL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amoswap.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_RL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amoand.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_RL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +@@ -723,6 +725,7 @@ const struct riscv_opcode riscv_opcodes[] = + {"amomaxu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_RL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amomin.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_RL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amominu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_RL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amocas.b.rl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_RL, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amoadd.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQRL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amoswap.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQRL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amoand.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQRL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +@@ -732,6 +735,7 @@ const struct riscv_opcode riscv_opcodes[] = + {"amomaxu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQRL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amomin.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQRL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amominu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQRL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, ++{"amocas.b.aqrl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_AQRL, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, + {"amoadd.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoswap.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoand.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +@@ -741,6 +745,7 @@ const struct riscv_opcode riscv_opcodes[] = + {"amomaxu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amomin.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amominu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amocas.h", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoadd.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQ, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoswap.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQ, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoand.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQ, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +@@ -750,6 +755,7 @@ const struct riscv_opcode riscv_opcodes[] = + {"amomaxu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQ, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amomin.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQ, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amominu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQ, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amocas.h.aq", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_AQ, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoadd.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_RL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoswap.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_RL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoand.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_RL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +@@ -759,6 +765,7 @@ const struct riscv_opcode riscv_opcodes[] = + {"amomaxu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_RL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amomin.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_RL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amominu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_RL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amocas.h.rl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_RL, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoadd.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQRL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoswap.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQRL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amoand.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQRL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, +@@ -768,6 +775,7 @@ const struct riscv_opcode riscv_opcodes[] = + {"amomaxu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQRL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amomin.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQRL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amominu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQRL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, ++{"amocas.h.aqrl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_AQRL, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + + /* Zacas instruction subset. */ + {"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-- +2.27.0 + diff --git a/RISC-V-Add-platform-property-capability-extensions.patch b/RISC-V-Add-platform-property-capability-extensions.patch new file mode 100644 index 0000000000000000000000000000000000000000..e16d1ec10614e97e2a56cdfcb4eebf2d3b7ec184 --- /dev/null +++ b/RISC-V-Add-platform-property-capability-extensions.patch @@ -0,0 +1,216 @@ +From 985f79e843539bb687068c1a4bcc7ca9557a995c Mon Sep 17 00:00:00 2001 +From: Tsukasa OI +Date: Tue, 18 Jun 2024 19:50:17 +0800 +Subject: [PATCH] RISC-V: Add platform property/capability extensions + +RISC-V Profiles document defines number of "extensions" that indicate +certain platform properties/capabilities just like 'Zkt' extension from the +RISC-V cryptography extensions. + +This commit defines 20 platform property/capability extensions as defined +in the RISC-V Profiles documentation. + +The only exception: 'Ssstateen' extension is defined separately because it +defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension. + +This is based on the ratified version of RISC-V Profiles: + + +[Definition] + +"Main memory regions": + Main memory regions (in contrast to I/O or vacant memory regions) with + both the cacheability and coherence PMAs. + +[New Unprivileged Extensions] + +1. 'Ziccif' + "Main memory regions" support instruction fetch and any instruction + fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN) + are atomic. +2. 'Ziccrse' + "Main memory regions" provide the eventual success guarantee for + LR/SC sequence (RsrvEventual). +3. 'Ziccamoa' + "Main memory regions" support all currently-defined AMO operations + including swap, logical and arithmetic operations (AMOArithmetic). +4. 'Za64rs' + For LR/SC instructions, reservation sets are contiguous, naturally + aligned and at most 64-bytes in size. +5. 'Za128rs' + Likewise, but reservation sets are at most 128-bytes in size. +6. 'Zicclsm' + Misaligned loads / stores to "main memory regions" are supported. + Those include both regular scalar and vector accesses but does not + include AMOs and other specialized forms of memory accesses. +7. 'Zic64b' + Cache blocks are (exactly) 64-bytes in size and naturally aligned. + +[New Privileged Extensions] + +1. 'Svbare' + "satp" mode Bare is supported. +2. 'Svade' + Page-fault exceptions are raised when a page is accessed when A bit is + clear, or written when D bit is clear. +3. 'Ssccptr' + "Main memory regions" support hardware page-table reads. +4. 'Sstvecd' + "stvec" mode Direct is supported. When "stvec" mode is Direct, + "stvec.BASE" is capable of holding any valid 4-byte aligned address. +5. 'Sstvala' + "stval" is always written with a nonzero value whenever possible as + specified in the Privileged Architecture documentation + (version 20211203: see section 4.1.9). +6. 'Sscounterenw' + For any "hpmcounter" that is not read-only zero, the corresponding bit + in "scounteren" is writable. +7. 'Ssu64xl' + "sstatus.UXL" is capable of holding the value 0b10 + (UXLEN==64 is supported). +8. 'Shcounterenw' + Similar to 'Sscounterenw' but the same rule applies to "hcounteren". +9. 'Shvstvala' + Similar to 'Sstvala' but the same rule applies to "vstval". +10. 'Shtvala' + "htval" is written with the faulting guest physical address as long as + permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala'). +11. 'Shvstvecd' + Similar to 'Sstvecd' but the same rule applies to "vstvec". +12. 'Shvsatpa' + All translation modes supported in "satp" are also supported in "vsatp". +13. 'Shgatpa' + For each supported virtual memory scheme SvNN supported in "satp", the + corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare + is also supported. + +[Implications] + +(Due to reservation set size constraints) +- 'Za64rs' -> 'Za128rs' + +(Due to the fact that a privileged "extension" directly refers a CSR) +- 'Svbare' -> 'Zicsr' +- 'Sstvecd' -> 'Zicsr' +- 'Sstvala' -> 'Zicsr' +- 'Sscounterenw' -> 'Zicsr' +- 'Ssu64xl' -> 'Zicsr' + +(Due to the fact that a privileged "extension" indirectly depends on CSRs) +- 'Svade' -> 'Zicsr' + +(Due to the fact that a privileged "extension" is a hypervisor property) +- 'Shcounterenw' -> 'H' +- 'Shvstvala' -> 'H' +- 'Shtvala' -> 'H' +- 'Shvstvecd' -> 'H' +- 'Shvsatpa' -> 'H' +- 'Shgatpa' -> 'H' + +bfd/ChangeLog: + + * elfxx-riscv.c + (riscv_implicit_subsets): Add 13 implication rules. + Reorder 'H' for new 'Sh*' extensions. + (riscv_supported_std_z_ext) Add 7 property/capability extensions. + (riscv_supported_std_s_ext) Add 13 property/capability extensions. +--- + bfd/elfxx-riscv.c | 35 ++++++++++++++++++++++++++++++++++- + 1 file changed, 34 insertions(+), 1 deletion(-) + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index b4a0139196b..36a525018e7 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1113,7 +1113,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"g", "zicsr", check_implicit_always}, + {"g", "zifencei", check_implicit_always}, + {"m", "zmmul", check_implicit_always}, +- {"h", "zicsr", check_implicit_always}, + {"q", "d", check_implicit_always}, + {"v", "d", check_implicit_always}, + {"v", "zve64d", check_implicit_always}, +@@ -1164,6 +1163,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"zhinx", "zhinxmin", check_implicit_always}, + {"zhinxmin", "zfinx", check_implicit_always}, + {"zfinx", "zicsr", check_implicit_always}, ++ {"za64rs", "za128rs", check_implicit_always}, + {"zk", "zkn", check_implicit_always}, + {"zk", "zkr", check_implicit_always}, + {"zk", "zkt", check_implicit_always}, +@@ -1203,10 +1203,23 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"smcntrpmf", "zicsr", check_implicit_always}, + {"smstateen", "ssstateen", check_implicit_always}, + {"smepmp", "zicsr", check_implicit_always}, ++ {"shcounterenw", "h", check_implicit_always}, ++ {"shgatpa", "h", check_implicit_always}, ++ {"shtvala", "h", check_implicit_always}, ++ {"shvsatpa", "h", check_implicit_always}, ++ {"shvstvala", "h", check_implicit_always}, ++ {"shvstvecd", "h", check_implicit_always}, ++ {"h", "zicsr", check_implicit_always}, + {"ssaia", "zicsr", check_implicit_always}, + {"sscofpmf", "zicsr", check_implicit_always}, ++ {"sscounterenw", "zicsr", check_implicit_always}, + {"ssstateen", "zicsr", check_implicit_always}, + {"sstc", "zicsr", check_implicit_always}, ++ {"sstvala", "zicsr", check_implicit_always}, ++ {"sstvecd", "zicsr", check_implicit_always}, ++ {"ssu64xl", "zicsr", check_implicit_always}, ++ {"svade", "zicsr", check_implicit_always}, ++ {"svbare", "zicsr", check_implicit_always}, + {"svadu", "zicsr", check_implicit_always}, + + {"xsfvcp", "zve32x", check_implicit_always}, +@@ -1267,6 +1280,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] = + + static struct riscv_supported_ext riscv_supported_std_z_ext[] = + { ++ {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -1280,6 +1298,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -1355,14 +1375,27 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + + static struct riscv_supported_ext riscv_supported_std_s_ext[] = + { ++ {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +-- +2.27.0 + diff --git a/RISC-V-Add-support-for-Zfbfmin-extension.patch b/RISC-V-Add-support-for-Zfbfmin-extension.patch new file mode 100644 index 0000000000000000000000000000000000000000..edf27ebb9ab0b76b958eab2adb4e252af0d94c33 --- /dev/null +++ b/RISC-V-Add-support-for-Zfbfmin-extension.patch @@ -0,0 +1,323 @@ +From 4479abf7a0a3c362bd7eca81a4442a0651784106 Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Thu, 6 Jun 2024 15:59:51 +0800 +Subject: [PATCH] RISC-V: Add support for Zfbfmin extension + +This implements the Zfbfmin extension, as of version 1.0. + +View detailed information in: + + +1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and + FMV.H.X instructions as defined in the Zfh extension. + +2 The Zfhmin extension includes the following instructions from the Zfh + extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in: + + +3 Zfhmin extension depend on 'F'. + +4 Simply put, just make Zfbfmin dependent on Zfhmin. + +Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and +FMV.H.X instructions an independent extension to achieve precise dependency +relationships for the Zfbfmin. + +5 For relevant information in gcc, please refer to: + + +bfd/ChangeLog: + + * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin. + (riscv_multi_subset_supports_ext): Ditto. + +gas/ChangeLog: + + * NEWS: Updated. + * testsuite/gas/riscv/march-help.l: Ditto. + * testsuite/gas/riscv/zfbfmin.d: New test. + * testsuite/gas/riscv/zfbfmin.s: New test. + +include/ChangeLog: + + * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define. + (MASK_FCVT_BF16_S): Ditto. + (MATCH_FCVT_S_BF16): Ditto. + (MASK_FCVT_S_BF16): Ditto. + (DECLARE_INSN): New declarations for Zfbfmin. + * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN. + +opcodes/ChangeLog: + + * riscv-opc.c: Add Zfbfmin instructions. +--- + bfd/elfxx-riscv.c | 6 ++ + gas/NEWS | 25 +++++- + gas/testsuite/gas/riscv/march-help.l | 127 +++++++++++++++++++++++++++ + gas/testsuite/gas/riscv/zfbfmin.d | 11 +++ + gas/testsuite/gas/riscv/zfbfmin.s | 6 ++ + include/opcode/riscv-opc.h | 8 ++ + include/opcode/riscv.h | 1 + + opcodes/riscv-opc.c | 5 ++ + 8 files changed, 186 insertions(+), 3 deletions(-) + create mode 100644 gas/testsuite/gas/riscv/march-help.l + create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d + create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 9a121b47121..31858cb8d12 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1148,6 +1148,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"zihpm", "zicsr", check_implicit_always}, + {"zcd", "d", check_implicit_always}, + {"zcf", "f", check_implicit_always}, ++ {"zfbfmin", "zfhmin", check_implicit_always}, + {"zfa", "f", check_implicit_always}, + {"d", "f", check_implicit_always}, + {"zfh", "zfhmin", check_implicit_always}, +@@ -1275,6 +1276,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2483,6 +2485,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + && riscv_subset_supports (rps, "q")) + || (riscv_subset_supports (rps, "zhinxmin") + && riscv_subset_supports (rps, "zqinx"))); ++ case INSN_CLASS_ZFBFMIN: ++ return riscv_subset_supports (rps, "zfbfmin"); + case INSN_CLASS_ZFA: + return riscv_subset_supports (rps, "zfa"); + case INSN_CLASS_D_AND_ZFA: +@@ -2725,6 +2729,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, + return "zhinxmin"; + else + return _("zfhmin' and `q', or `zhinxmin' and `zqinx"); ++ case INSN_CLASS_ZFBFMIN: ++ return "zfbfmin"; + case INSN_CLASS_ZFA: + return "zfa"; + case INSN_CLASS_D_AND_ZFA: +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +new file mode 100644 +index 00000000000..57c73b3074e +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -0,0 +1,127 @@ ++All available -march extensions for RISC-V: ++ e 1.9 ++ i 2.1, 2.0 ++ m 2.0 ++ a 2.1, 2.0 ++ f 2.2, 2.0 ++ d 2.2, 2.0 ++ q 2.2, 2.0 ++ c 2.0 ++ b 1.0 ++ v 1.0 ++ h 1.0 ++ zicbom 1.0 ++ zicbop 1.0 ++ zicboz 1.0 ++ zicond 1.0 ++ zicntr 2.0 ++ zicsr 2.0 ++ zifencei 2.0 ++ zihintntl 1.0 ++ zihintpause 2.0 ++ zihpm 2.0 ++ zmmul 1.0 ++ zaamo 1.0 ++ zabha 1.0 ++ zalrsc 1.0 ++ zawrs 1.0 ++ zfbfmin 1.0 ++ zfa 1.0 ++ zfh 1.0 ++ zfhmin 1.0 ++ zfinx 1.0 ++ zdinx 1.0 ++ zqinx 1.0 ++ zhinx 1.0 ++ zhinxmin 1.0 ++ zbb 1.0 ++ zba 1.0 ++ zbc 1.0 ++ zbs 1.0 ++ zbkb 1.0 ++ zbkc 1.0 ++ zbkx 1.0 ++ zk 1.0 ++ zkn 1.0 ++ zknd 1.0 ++ zkne 1.0 ++ zknh 1.0 ++ zkr 1.0 ++ zks 1.0 ++ zksed 1.0 ++ zksh 1.0 ++ zkt 1.0 ++ zve32x 1.0 ++ zve32f 1.0 ++ zve64x 1.0 ++ zve64f 1.0 ++ zve64d 1.0 ++ zvbb 1.0 ++ zvbc 1.0 ++ zvfh 1.0 ++ zvfhmin 1.0 ++ zvkb 1.0 ++ zvkg 1.0 ++ zvkn 1.0 ++ zvkng 1.0 ++ zvknc 1.0 ++ zvkned 1.0 ++ zvknha 1.0 ++ zvknhb 1.0 ++ zvksed 1.0 ++ zvksh 1.0 ++ zvks 1.0 ++ zvksg 1.0 ++ zvksc 1.0 ++ zvkt 1.0 ++ zvl32b 1.0 ++ zvl64b 1.0 ++ zvl128b 1.0 ++ zvl256b 1.0 ++ zvl512b 1.0 ++ zvl1024b 1.0 ++ zvl2048b 1.0 ++ zvl4096b 1.0 ++ zvl8192b 1.0 ++ zvl16384b 1.0 ++ zvl32768b 1.0 ++ zvl65536b 1.0 ++ ztso 1.0 ++ zca 1.0 ++ zcb 1.0 ++ zcf 1.0 ++ zcd 1.0 ++ zcmp 1.0 ++ smaia 1.0 ++ smcntrpmf 1.0 ++ smepmp 1.0 ++ smstateen 1.0 ++ ssaia 1.0 ++ sscofpmf 1.0 ++ ssstateen 1.0 ++ sstc 1.0 ++ svadu 1.0 ++ svinval 1.0 ++ svnapot 1.0 ++ svpbmt 1.0 ++ xcvmac 1.0 ++ xcvalu 1.0 ++ xcvelw 1.0 ++ xcvbi 1.0 ++ xcvmem 1.0 ++ xtheadba 1.0 ++ xtheadbb 1.0 ++ xtheadbs 1.0 ++ xtheadcmo 1.0 ++ xtheadcondmov 1.0 ++ xtheadfmemidx 1.0 ++ xtheadfmv 1.0 ++ xtheadint 1.0 ++ xtheadmac 1.0 ++ xtheadmemidx 1.0 ++ xtheadmempair 1.0 ++ xtheadsync 1.0 ++ xtheadvector 1.0 ++ xtheadzvamo 1.0 ++ xventanacondops 1.0 ++ xsfvcp 1.0 +diff --git a/gas/testsuite/gas/riscv/zfbfmin.d b/gas/testsuite/gas/riscv/zfbfmin.d +new file mode 100644 +index 00000000000..7cacc0bd684 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zfbfmin.d +@@ -0,0 +1,11 @@ ++#as: -march=rv64i_zfbfmin ++#objdump: -d ++ ++.*:[ ]+file format .* ++ ++Disassembly of section .text: ++ ++0+000 : ++[ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt.bf16.s[ ]+fa0,fa1 ++[ ]+[0-9a-f]+:[ ]+44858553[ ]+fcvt.bf16.s[ ]+fa0,fa1,rne ++[ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt.s.bf16[ ]+fa0,fa1 +diff --git a/gas/testsuite/gas/riscv/zfbfmin.s b/gas/testsuite/gas/riscv/zfbfmin.s +new file mode 100644 +index 00000000000..c9a9af3e394 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zfbfmin.s +@@ -0,0 +1,6 @@ ++target: ++ # fcvt.bf16.s ++ fcvt.bf16.s fa0, fa1 ++ fcvt.bf16.s fa0, fa1, rne ++ # fcvt.s.bf16 ++ fcvt.s.bf16 fa0, fa1 +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index a24e59cf310..c8340517117 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -2320,6 +2320,11 @@ + #define MASK_WRS_NTO 0xffffffff + #define MATCH_WRS_STO 0x01d00073 + #define MASK_WRS_STO 0xffffffff ++/* Zfbfmin intructions. */ ++#define MATCH_FCVT_BF16_S 0x44800053 ++#define MASK_FCVT_BF16_S 0xfff0007f ++#define MATCH_FCVT_S_BF16 0x40600053 ++#define MASK_FCVT_S_BF16 0xfff0007f + /* Vendor-specific (CORE-V) Xcvmac instructions. */ + #define MATCH_CV_MAC 0x9000302b + #define MASK_CV_MAC 0xfe00707f +@@ -3849,6 +3854,9 @@ DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) + /* Zawrs instructions. */ + DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) + DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) ++/* Zfbfmin instructions. */ ++DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S) ++DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) + /* Zvbb/Zvkb instructions. */ + DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) + DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index adea7dbc794..93830dfa5f2 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -430,6 +430,7 @@ enum riscv_insn_class + INSN_CLASS_ZFHMIN_INX, + INSN_CLASS_ZFHMIN_AND_D_INX, + INSN_CLASS_ZFHMIN_AND_Q_INX, ++ INSN_CLASS_ZFBFMIN, + INSN_CLASS_ZFA, + INSN_CLASS_D_AND_ZFA, + INSN_CLASS_Q_AND_ZFA, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index fdd05ac75dc..0041419641f 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -740,6 +740,11 @@ const struct riscv_opcode riscv_opcodes[] = + {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 }, + {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, + ++/* Zfbfmin instructions. */ ++{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 }, ++{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 }, ++{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 }, ++ + /* Single-precision floating-point instruction subset. */ + {"frcsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, + {"frsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, +-- +2.27.0 + diff --git a/binutils-2.44-backport-RISC-V-Add-support-for-Zimop-extension.patch b/RISC-V-Add-support-for-Zimop-extension.patch similarity index 56% rename from binutils-2.44-backport-RISC-V-Add-support-for-Zimop-extension.patch rename to RISC-V-Add-support-for-Zimop-extension.patch index 83d49b0c52293f098cc80affd6f10bc81497e6e9..a43cd1c0cf590062cf36f4eb7015888a9817f541 100644 --- a/binutils-2.44-backport-RISC-V-Add-support-for-Zimop-extension.patch +++ b/RISC-V-Add-support-for-Zimop-extension.patch @@ -1,7 +1,71 @@ -diff -rup binutils.orig/bfd/elfxx-riscv.c binutils-2.42/bfd/elfxx-riscv.c ---- binutils.orig/bfd/elfxx-riscv.c 2025-07-01 10:21:19.489412455 +0800 -+++ binutils-2.42/bfd/elfxx-riscv.c 2025-07-01 10:21:39.880067385 +0800 -@@ -1291,6 +1291,7 @@ static struct riscv_supported_ext riscv_ +From fb522c72f4742dbf354f5692075c4095b3ba2968 Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Wed, 12 Jun 2024 09:28:17 +0800 +Subject: [PATCH] RISC-V: Add support for Zimop extension + +This implements the Zimop (May-Be-Operations) extension, as of version 1.0. + +View detailed information in: + + +bfd/ChangeLog: + + * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zimop + (riscv_multi_subset_supports_ext): Ditto. + +gas/ChangeLog: + + * NEWS: Updated. + * testsuite/gas/riscv/march-help.l: Ditto. + * testsuite/gas/riscv/zimop.d: New test. + * testsuite/gas/riscv/zimop.s: New test. + +include/ChangeLog: + + * opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zimop. + (MATCH_MOP_R_0, MATCH_MOP_R_1, MATCH_MOP_R_2, MATCH_MOP_R_3, + MATCH_MOP_R_4, MATCH_MOP_R_5, MATCH_MOP_R_6, MATCH_MOP_R_7, + MATCH_MOP_R_8, MATCH_MOP_R_9, MATCH_MOP_R_10, MATCH_MOP_R_11, + MATCH_MOP_R_12, MATCH_MOP_R_13, MATCH_MOP_R_14, MATCH_MOP_R_15, + MATCH_MOP_R_16, MATCH_MOP_R_17, MATCH_MOP_R_18, MATCH_MOP_R_19, + MATCH_MOP_R_20, MATCH_MOP_R_21, MATCH_MOP_R_22, MATCH_MOP_R_23, + MATCH_MOP_R_24, MATCH_MOP_R_25, MATCH_MOP_R_26, MATCH_MOP_R_27, + MATCH_MOP_R_28, MATCH_MOP_R_29, MATCH_MOP_R_30, MATCH_MOP_R_31, + MATCH_MOP_RR_0, MATCH_MOP_RR_1, MATCH_MOP_RR_2, MATCH_MOP_RR_3, + MATCH_MOP_RR_4, MATCH_MOP_RR_5, MATCH_MOP_RR_6, MATCH_MOP_RR_7): Define. + (MASK_MOP_R_0, MASK_MOP_R_1, MASK_MOP_R_2, MASK_MOP_R_3, MASK_MOP_R_4, + MASK_MOP_R_5, MASK_MOP_R_6, MASK_MOP_R_7, MASK_MOP_R_8, MASK_MOP_R_9, + MASK_MOP_R_10, MASK_MOP_R_11, MASK_MOP_R_12, MASK_MOP_R_13, + MASK_MOP_R_14, MASK_MOP_R_15, MASK_MOP_R_16, MASK_MOP_R_17, + MASK_MOP_R_18, MASK_MOP_R_19, MASK_MOP_R_20, MASK_MOP_R_21, + MASK_MOP_R_22, MASK_MOP_R_23, MASK_MOP_R_24, MASK_MOP_R_25, + MASK_MOP_R_26, MASK_MOP_R_27, MASK_MOP_R_28, MASK_MOP_R_29, + MASK_MOP_R_30, MASK_MOP_R_31, MASK_MOP_RR_0, MASK_MOP_RR_1, + MASK_MOP_RR_2, MASK_MOP_RR_3, MASK_MOP_RR_4, MASK_MOP_RR_5, + MASK_MOP_RR_6, MASK_MOP_RR_7): Ditto. + * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZIMOP. + +opcodes/ChangeLog: + + * riscv-opc.c: Add Zimop instructions. +--- + bfd/elfxx-riscv.c | 5 ++ + gas/NEWS | 1 + + gas/testsuite/gas/riscv/march-help.l | 1 + + gas/testsuite/gas/riscv/zimop.d | 48 +++++++++++ + gas/testsuite/gas/riscv/zimop.s | 43 ++++++++++ + include/opcode/riscv-opc.h | 122 +++++++++++++++++++++++++++ + include/opcode/riscv.h | 1 + + opcodes/riscv-opc.c | 42 +++++++++ + 8 files changed, 263 insertions(+) + create mode 100644 gas/testsuite/gas/riscv/zimop.d + create mode 100644 gas/testsuite/gas/riscv/zimop.s + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 17179a3c637..ec4651ad942 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1310,6 +1310,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, @@ -9,7 +73,7 @@ diff -rup binutils.orig/bfd/elfxx-riscv.c binutils-2.42/bfd/elfxx-riscv.c {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -@@ -2464,6 +2465,8 @@ riscv_multi_subset_supports (riscv_parse +@@ -2497,6 +2498,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zca"))); case INSN_CLASS_ZIHINTPAUSE: return riscv_subset_supports (rps, "zihintpause"); @@ -18,7 +82,7 @@ diff -rup binutils.orig/bfd/elfxx-riscv.c binutils-2.42/bfd/elfxx-riscv.c case INSN_CLASS_M: return riscv_subset_supports (rps, "m"); case INSN_CLASS_ZMMUL: -@@ -2686,6 +2689,8 @@ riscv_multi_subset_supports_ext (riscv_p +@@ -2734,6 +2737,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("c' or `zca"); case INSN_CLASS_ZIHINTPAUSE: return "zihintpause"; @@ -27,21 +91,126 @@ diff -rup binutils.orig/bfd/elfxx-riscv.c binutils-2.42/bfd/elfxx-riscv.c case INSN_CLASS_M: return "m"; case INSN_CLASS_ZMMUL: -diff -rup binutils.orig/include/opcode/riscv.h binutils-2.42/include/opcode/riscv.h ---- binutils.orig/include/opcode/riscv.h 2025-07-01 10:21:21.698591754 +0800 -+++ binutils-2.42/include/opcode/riscv.h 2025-07-01 10:21:39.882067547 +0800 -@@ -420,6 +420,7 @@ enum riscv_insn_class - INSN_CLASS_ZIHINTNTL, - INSN_CLASS_ZIHINTNTL_AND_C, - INSN_CLASS_ZIHINTPAUSE, -+ INSN_CLASS_ZIMOP, - INSN_CLASS_ZMMUL, - INSN_CLASS_ZAWRS, - INSN_CLASS_F_INX, -diff -rup binutils.orig/include/opcode/riscv-opc.h binutils-2.42/include/opcode/riscv-opc.h ---- binutils.orig/include/opcode/riscv-opc.h 2025-07-01 10:21:21.698591754 +0800 -+++ binutils-2.42/include/opcode/riscv-opc.h 2025-07-01 10:21:39.882067547 +0800 -@@ -2315,6 +2315,87 @@ +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index 439a7514cbf..212bdc429d6 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -20,6 +20,7 @@ All available -march extensions for RISC-V: + zihintntl 1.0 + zihintpause 2.0 + zihpm 2.0 ++ zimop 1.0 + zmmul 1.0 + zaamo 1.0 + zabha 1.0 +diff --git a/gas/testsuite/gas/riscv/zimop.d b/gas/testsuite/gas/riscv/zimop.d +new file mode 100644 +index 00000000000..becb72ca650 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zimop.d +@@ -0,0 +1,48 @@ ++#as: -march=rv64i_zimop ++#objdump: -d ++ ++.*:[ ]+file format .* ++ ++Disassembly of section .text: ++ ++0+000 : ++[ ]+[0-9a-f]+:[ ]+81c5c573[ ]+mop.r.0[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+81d5c573[ ]+mop.r.1[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+81e5c573[ ]+mop.r.2[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+81f5c573[ ]+mop.r.3[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+85c5c573[ ]+mop.r.4[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+85d5c573[ ]+mop.r.5[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+85e5c573[ ]+mop.r.6[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+85f5c573[ ]+mop.r.7[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+89c5c573[ ]+mop.r.8[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+89d5c573[ ]+mop.r.9[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+89e5c573[ ]+mop.r.10[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+89f5c573[ ]+mop.r.11[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+8dc5c573[ ]+mop.r.12[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+8dd5c573[ ]+mop.r.13[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+8de5c573[ ]+mop.r.14[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+8df5c573[ ]+mop.r.15[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c1c5c573[ ]+mop.r.16[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c1d5c573[ ]+mop.r.17[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c1e5c573[ ]+mop.r.18[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c1f5c573[ ]+mop.r.19[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c5c5c573[ ]+mop.r.20[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c5d5c573[ ]+mop.r.21[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c5e5c573[ ]+mop.r.22[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c5f5c573[ ]+mop.r.23[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c9c5c573[ ]+mop.r.24[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c9d5c573[ ]+mop.r.25[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c9e5c573[ ]+mop.r.26[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+c9f5c573[ ]+mop.r.27[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+cdc5c573[ ]+mop.r.28[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+cdd5c573[ ]+mop.r.29[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+cde5c573[ ]+mop.r.30[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+cdf5c573[ ]+mop.r.31[ ]+a0,a1 ++[ ]+[0-9a-f]+:[ ]+82c5c573[ ]+mop.rr.0[ ]+a0,a1,a2 ++[ ]+[0-9a-f]+:[ ]+86c5c573[ ]+mop.rr.1[ ]+a0,a1,a2 ++[ ]+[0-9a-f]+:[ ]+8ac5c573[ ]+mop.rr.2[ ]+a0,a1,a2 ++[ ]+[0-9a-f]+:[ ]+8ec5c573[ ]+mop.rr.3[ ]+a0,a1,a2 ++[ ]+[0-9a-f]+:[ ]+c2c5c573[ ]+mop.rr.4[ ]+a0,a1,a2 ++[ ]+[0-9a-f]+:[ ]+c6c5c573[ ]+mop.rr.5[ ]+a0,a1,a2 ++[ ]+[0-9a-f]+:[ ]+cac5c573[ ]+mop.rr.6[ ]+a0,a1,a2 ++[ ]+[0-9a-f]+:[ ]+cec5c573[ ]+mop.rr.7[ ]+a0,a1,a2 +diff --git a/gas/testsuite/gas/riscv/zimop.s b/gas/testsuite/gas/riscv/zimop.s +new file mode 100644 +index 00000000000..d244c1fb0fb +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zimop.s +@@ -0,0 +1,43 @@ ++target: ++ # mop.r.n ++ mop.r.0 a0, a1 ++ mop.r.1 a0, a1 ++ mop.r.2 a0, a1 ++ mop.r.3 a0, a1 ++ mop.r.4 a0, a1 ++ mop.r.5 a0, a1 ++ mop.r.6 a0, a1 ++ mop.r.7 a0, a1 ++ mop.r.8 a0, a1 ++ mop.r.9 a0, a1 ++ mop.r.10 a0, a1 ++ mop.r.11 a0, a1 ++ mop.r.12 a0, a1 ++ mop.r.13 a0, a1 ++ mop.r.14 a0, a1 ++ mop.r.15 a0, a1 ++ mop.r.16 a0, a1 ++ mop.r.17 a0, a1 ++ mop.r.18 a0, a1 ++ mop.r.19 a0, a1 ++ mop.r.20 a0, a1 ++ mop.r.21 a0, a1 ++ mop.r.22 a0, a1 ++ mop.r.23 a0, a1 ++ mop.r.24 a0, a1 ++ mop.r.25 a0, a1 ++ mop.r.26 a0, a1 ++ mop.r.27 a0, a1 ++ mop.r.28 a0, a1 ++ mop.r.29 a0, a1 ++ mop.r.30 a0, a1 ++ mop.r.31 a0, a1 ++ # mop.rr.n ++ mop.rr.0 a0, a1, a2 ++ mop.rr.1 a0, a1, a2 ++ mop.rr.2 a0, a1, a2 ++ mop.rr.3 a0, a1, a2 ++ mop.rr.4 a0, a1, a2 ++ mop.rr.5 a0, a1, a2 ++ mop.rr.6 a0, a1, a2 ++ mop.rr.7 a0, a1, a2 +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index 415d1fb8343..8bf71c729aa 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -2352,6 +2352,87 @@ #define MASK_C_NTL_S1 0xffff #define MATCH_C_NTL_ALL 0x9016 #define MASK_C_NTL_ALL 0xffff @@ -126,10 +295,10 @@ diff -rup binutils.orig/include/opcode/riscv-opc.h binutils-2.42/include/opcode/ +#define MASK_MOP_RR_6 0xfe00707f +#define MATCH_MOP_RR_7 0xce004073 +#define MASK_MOP_RR_7 0xfe00707f - /* Zawrs instructions. */ - #define MATCH_WRS_NTO 0x00d00073 - #define MASK_WRS_NTO 0xffffffff -@@ -3852,6 +3933,47 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, M + /* Zacas instructions. */ + #define MATCH_AMOCAS_W 0x2800202f + #define MASK_AMOCAS_W 0xf800707f +@@ -3952,6 +4033,47 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) @@ -174,13 +343,26 @@ diff -rup binutils.orig/include/opcode/riscv-opc.h binutils-2.42/include/opcode/ +DECLARE_INSN(MOP_RR_5, MATCH_MOP_RR_5, MASK_MOP_RR_5) +DECLARE_INSN(MOP_RR_6, MATCH_MOP_RR_6, MASK_MOP_RR_6) +DECLARE_INSN(MOP_RR_7, MATCH_MOP_RR_7, MASK_MOP_RR_7) - /* Zawrs instructions. */ - DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) - DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) -diff -rup binutils.orig/opcodes/riscv-opc.c binutils-2.42/opcodes/riscv-opc.c ---- binutils.orig/opcodes/riscv-opc.c 2025-07-01 10:21:23.053701737 +0800 -+++ binutils-2.42/opcodes/riscv-opc.c 2025-07-01 10:21:39.884067709 +0800 -@@ -996,6 +996,48 @@ const struct riscv_opcode riscv_opcodes[ + /* Zacas instructions. */ + DECLARE_INSN(amocas_w, MATCH_AMOCAS_W, MASK_AMOCAS_W) + DECLARE_INSN(amocas_d, MATCH_AMOCAS_D, MASK_AMOCAS_D) +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index 92884e4d24d..1de200ce393 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -419,6 +419,7 @@ enum riscv_insn_class + INSN_CLASS_ZIHINTNTL, + INSN_CLASS_ZIHINTNTL_AND_C, + INSN_CLASS_ZIHINTPAUSE, ++ INSN_CLASS_ZIMOP, + INSN_CLASS_ZMMUL, + INSN_CLASS_ZAAMO, + INSN_CLASS_ZALRSC, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index bfea2921a3d..49d2888ff66 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -1101,6 +1101,48 @@ const struct riscv_opcode riscv_opcodes[] = {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, @@ -229,3 +411,6 @@ diff -rup binutils.orig/opcodes/riscv-opc.c binutils-2.42/opcodes/riscv-opc.c /* Zawrs instructions. */ {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, +-- +2.27.0 + diff --git a/RISC-V-Add-support-for-Zvfbfmin-extension.patch b/RISC-V-Add-support-for-Zvfbfmin-extension.patch new file mode 100644 index 0000000000000000000000000000000000000000..85ad67ed39052c4e093e4b1e00b1a6c6696fe637 --- /dev/null +++ b/RISC-V-Add-support-for-Zvfbfmin-extension.patch @@ -0,0 +1,193 @@ +From b4dde2f46b036fcdf638069c1ef8560d7c5d0012 Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Thu, 6 Jun 2024 15:59:52 +0800 +Subject: [PATCH] RISC-V: Add support for Zvfbfmin extension + +This implements the Zvfbfmin extension, as of version 1.0. +View detailed information in: + + +Depending on different usage scenarios, the Zvfbfmin extension may +depend on 'V' or 'Zve32f'. This patch only implements dependencies +in scenario of Embedded Processor. In scenario of Application +Processor, it is necessary to explicitly indicate the dependent +'V' extension. + +For relevant information in gcc, please refer to: + + +bfd/ChangeLog: + + * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin. + (riscv_multi_subset_supports_ext): Ditto. + +gas/ChangeLog: + + * NEWS: Updated. + * testsuite/gas/riscv/march-help.l: Ditto. + * testsuite/gas/riscv/zvfbfmin.d: New test. + * testsuite/gas/riscv/zvfbfmin.s: New test. + +include/ChangeLog: + + * opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define. + (MASK_VFNCVTBF16_F_F_W): Ditto. + (MATCH_VFWCVTBF16_F_F_V): Ditto. + (MASK_VFWCVTBF16_F_F_V): Ditto. + (DECLARE_INSN): New declarations for Zvfbfmin. + * opcode/riscv.h (enum riscv_insn_class): Add + INSN_CLASS_ZVFBFMIN + +opcodes/ChangeLog: + + * riscv-opc.c: Add Zvfbfmin instructions. +--- + bfd/elfxx-riscv.c | 6 ++++++ + gas/NEWS | 2 ++ + gas/testsuite/gas/riscv/march-help.l | 1 + + gas/testsuite/gas/riscv/zvfbfmin.d | 12 ++++++++++++ + gas/testsuite/gas/riscv/zvfbfmin.s | 7 +++++++ + include/opcode/riscv-opc.h | 8 ++++++++ + include/opcode/riscv.h | 1 + + opcodes/riscv-opc.c | 4 ++++ + 8 files changed, 41 insertions(+) + create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.d + create mode 100644 gas/testsuite/gas/riscv/zvfbfmin.s + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 31858cb8d12..81d280c0c8e 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1118,6 +1118,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"v", "d", check_implicit_always}, + {"v", "zve64d", check_implicit_always}, + {"v", "zvl128b", check_implicit_always}, ++ {"zvfbfmin", "zve32f", check_implicit_always}, + {"zvfh", "zvfhmin", check_implicit_always}, + {"zvfh", "zfhmin", check_implicit_always}, + {"zvfhmin", "zve32f", check_implicit_always}, +@@ -1309,6 +1310,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2548,6 +2550,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + return riscv_subset_supports (rps, "zvbb"); + case INSN_CLASS_ZVBC: + return riscv_subset_supports (rps, "zvbc"); ++ case INSN_CLASS_ZVFBFMIN: ++ return riscv_subset_supports (rps, "zvfbfmin"); + case INSN_CLASS_ZVKB: + return riscv_subset_supports (rps, "zvkb"); + case INSN_CLASS_ZVKG: +@@ -2806,6 +2810,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, + return _("zvbb"); + case INSN_CLASS_ZVBC: + return _("zvbc"); ++ case INSN_CLASS_ZVFBFMIN: ++ return "zvfbfmin"; + case INSN_CLASS_ZVKB: + return _("zvkb"); + case INSN_CLASS_ZVKG: +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index 57c73b3074e..38c70e269bf 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -58,6 +58,7 @@ All available -march extensions for RISC-V: + zve64d 1.0 + zvbb 1.0 + zvbc 1.0 ++ zvfbfmin 1.0 + zvfh 1.0 + zvfhmin 1.0 + zvkb 1.0 +diff --git a/gas/testsuite/gas/riscv/zvfbfmin.d b/gas/testsuite/gas/riscv/zvfbfmin.d +new file mode 100644 +index 00000000000..ce973812fe1 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zvfbfmin.d +@@ -0,0 +1,12 @@ ++#as: -march=rv64iv_zvfbfmin ++#objdump: -d ++ ++.*:[ ]+file format .* ++ ++Disassembly of section .text: ++ ++0+000 : ++[ ]+[0-9a-f]+:[ ]+4a8e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8 ++[ ]+[0-9a-f]+:[ ]+488e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8,v0.t ++[ ]+[0-9a-f]+:[ ]+4a869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8 ++[ ]+[0-9a-f]+:[ ]+48869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8,v0.t +diff --git a/gas/testsuite/gas/riscv/zvfbfmin.s b/gas/testsuite/gas/riscv/zvfbfmin.s +new file mode 100644 +index 00000000000..9a4493d84d1 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zvfbfmin.s +@@ -0,0 +1,7 @@ ++target: ++ # vfncvtbf16.f.f.w ++ vfncvtbf16.f.f.w v4, v8 ++ vfncvtbf16.f.f.w v4, v8, v0.t ++ # vfwcvtbf16.f.f.v ++ vfwcvtbf16.f.f.v v4, v8 ++ vfwcvtbf16.f.f.v v4, v8, v0.t +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index c8340517117..316c84ab02c 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -2325,6 +2325,11 @@ + #define MASK_FCVT_BF16_S 0xfff0007f + #define MATCH_FCVT_S_BF16 0x40600053 + #define MASK_FCVT_S_BF16 0xfff0007f ++/* Zvfbfmin intructions. */ ++#define MATCH_VFNCVTBF16_F_F_W 0x480e9057 ++#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f ++#define MATCH_VFWCVTBF16_F_F_V 0x48069057 ++#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f + /* Vendor-specific (CORE-V) Xcvmac instructions. */ + #define MATCH_CV_MAC 0x9000302b + #define MASK_CV_MAC 0xfe00707f +@@ -3857,6 +3862,9 @@ DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) + /* Zfbfmin instructions. */ + DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S) + DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) ++/* Zvfbfmin instructions. */ ++DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W) ++DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V) + /* Zvbb/Zvkb instructions. */ + DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) + DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index 93830dfa5f2..677276b5d76 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -455,6 +455,7 @@ enum riscv_insn_class + INSN_CLASS_ZVEF, + INSN_CLASS_ZVBB, + INSN_CLASS_ZVBC, ++ INSN_CLASS_ZVFBFMIN, + INSN_CLASS_ZVKB, + INSN_CLASS_ZVKG, + INSN_CLASS_ZVKNED, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index 0041419641f..bcca1289566 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -1928,6 +1928,10 @@ const struct riscv_opcode riscv_opcodes[] = + {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0}, + {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0}, + ++/* Zvfbfmin instructions. */ ++{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0}, ++{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0}, ++ + /* Zvbb/Zvkb instructions. */ + {"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0}, + {"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0}, +-- +2.27.0 + diff --git a/RISC-V-Add-support-for-Zvfbfwma-extension.patch b/RISC-V-Add-support-for-Zvfbfwma-extension.patch new file mode 100644 index 0000000000000000000000000000000000000000..559a18ae8a18aeb41b7fc0bd2bc0dbb1e2f65ff0 --- /dev/null +++ b/RISC-V-Add-support-for-Zvfbfwma-extension.patch @@ -0,0 +1,199 @@ +From 5b8ca47cdb4da87a1f11e07b3d04085b47a3582f Mon Sep 17 00:00:00 2001 +From: Xiao Zeng +Date: Thu, 6 Jun 2024 15:59:53 +0800 +Subject: [PATCH] RISC-V: Add support for Zvfbfwma extension + +This implements the Zvfbfwma extension, as of version 1.0. +View detailed information in: + + +1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension." + 1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f + 1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V + 1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin + +2 Depending on different usage scenarios, the Zvfbfwma extension may +depend on 'V' or 'Zve32f'. This patch only implements dependencies in +scenario of Embedded Processor. This is consistent with the processing +strategy in Zvfbfmin. In scenario of Application Processor, it is +necessary to explicitly indicate the dependent 'V' extension. + +For relevant information in gcc, please refer to: + + +bfd/ChangeLog: + + * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma. + (riscv_multi_subset_supports_ext): Ditto. + +gas/ChangeLog: + + * NEWS: Updated. + * testsuite/gas/riscv/march-help.l: Ditto. + * testsuite/gas/riscv/zvfbfwma.d: New test. + * testsuite/gas/riscv/zvfbfwma.s: New test. + +include/ChangeLog: + + * opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define. + (MASK_VFWMACCBF16_VF): Ditto. + (MATCH_VFWMACCBF16_VV): Ditto. + (MASK_VFWMACCBF16_VV): Ditto. + (DECLARE_INSN): New declarations for Zvfbfwma. + * opcode/riscv.h (enum riscv_insn_class): Add + INSN_CLASS_ZVFBFWMA + +opcodes/ChangeLog: + + * riscv-opc.c: Add Zvfbfwma instructions. +--- + bfd/elfxx-riscv.c | 7 +++++++ + gas/NEWS | 2 ++ + gas/testsuite/gas/riscv/march-help.l | 1 + + gas/testsuite/gas/riscv/zvfbfwma.d | 12 ++++++++++++ + gas/testsuite/gas/riscv/zvfbfwma.s | 7 +++++++ + include/opcode/riscv-opc.h | 8 ++++++++ + include/opcode/riscv.h | 1 + + opcodes/riscv-opc.c | 4 ++++ + 8 files changed, 42 insertions(+) + create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.d + create mode 100644 gas/testsuite/gas/riscv/zvfbfwma.s + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 81d280c0c8e..a32374c65f3 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1119,6 +1119,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"v", "zve64d", check_implicit_always}, + {"v", "zvl128b", check_implicit_always}, + {"zvfbfmin", "zve32f", check_implicit_always}, ++ {"zvfbfwma", "zve32f", check_implicit_always}, ++ {"zvfbfwma", "zfbfmin", check_implicit_always}, + {"zvfh", "zvfhmin", check_implicit_always}, + {"zvfh", "zfhmin", check_implicit_always}, + {"zvfhmin", "zve32f", check_implicit_always}, +@@ -1311,6 +1313,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zvfbfwma", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2552,6 +2555,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + return riscv_subset_supports (rps, "zvbc"); + case INSN_CLASS_ZVFBFMIN: + return riscv_subset_supports (rps, "zvfbfmin"); ++ case INSN_CLASS_ZVFBFWMA: ++ return riscv_subset_supports (rps, "zvfbfwma"); + case INSN_CLASS_ZVKB: + return riscv_subset_supports (rps, "zvkb"); + case INSN_CLASS_ZVKG: +@@ -2812,6 +2817,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, + return _("zvbc"); + case INSN_CLASS_ZVFBFMIN: + return "zvfbfmin"; ++ case INSN_CLASS_ZVFBFWMA: ++ return "zvfbfwma"; + case INSN_CLASS_ZVKB: + return _("zvkb"); + case INSN_CLASS_ZVKG: +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index 38c70e269bf..dd82752cd30 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -59,6 +59,7 @@ All available -march extensions for RISC-V: + zvbb 1.0 + zvbc 1.0 + zvfbfmin 1.0 ++ zvfbfwma 1.0 + zvfh 1.0 + zvfhmin 1.0 + zvkb 1.0 +diff --git a/gas/testsuite/gas/riscv/zvfbfwma.d b/gas/testsuite/gas/riscv/zvfbfwma.d +new file mode 100644 +index 00000000000..05da1328eea +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zvfbfwma.d +@@ -0,0 +1,12 @@ ++#as: -march=rv64iv_zvfbfwma ++#objdump: -d ++ ++.*:[ ]+file format .* ++ ++Disassembly of section .text: ++ ++0+000 : ++[ ]+[0-9a-f]+:[ ]+ee865257[ ]+vfwmaccbf16.vf[ ]+v4,fa2,v8 ++[ ]+[0-9a-f]+:[ ]+ec865257[ ]+vfwmaccbf16.vf[ ]+v4,fa2,v8,v0.t ++[ ]+[0-9a-f]+:[ ]+ee861257[ ]+vfwmaccbf16.vv[ ]+v4,v12,v8 ++[ ]+[0-9a-f]+:[ ]+ec861257[ ]+vfwmaccbf16.vv[ ]+v4,v12,v8,v0.t +diff --git a/gas/testsuite/gas/riscv/zvfbfwma.s b/gas/testsuite/gas/riscv/zvfbfwma.s +new file mode 100644 +index 00000000000..f824af98361 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zvfbfwma.s +@@ -0,0 +1,7 @@ ++target: ++ # vfwmaccbf16.vf ++ vfwmaccbf16.vf v4, fa2, v8 ++ vfwmaccbf16.vf v4, fa2, v8, v0.t ++ # vfwmaccbf16.vv ++ vfwmaccbf16.vv v4, v12, v8 ++ vfwmaccbf16.vv v4, v12, v8, v0.t +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index 316c84ab02c..fe5b5630b7b 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -2330,6 +2330,11 @@ + #define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f + #define MATCH_VFWCVTBF16_F_F_V 0x48069057 + #define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f ++/* Zvfbfwma intructions. */ ++#define MATCH_VFWMACCBF16_VF 0xec005057 ++#define MASK_VFWMACCBF16_VF 0xfc00707f ++#define MATCH_VFWMACCBF16_VV 0xec001057 ++#define MASK_VFWMACCBF16_VV 0xfc00707f + /* Vendor-specific (CORE-V) Xcvmac instructions. */ + #define MATCH_CV_MAC 0x9000302b + #define MASK_CV_MAC 0xfe00707f +@@ -3865,6 +3870,9 @@ DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16) + /* Zvfbfmin instructions. */ + DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W) + DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V) ++/* Zvfbfwma instructions. */ ++DECLARE_INSN(VFWMACCBF16_VF, MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF) ++DECLARE_INSN(VFWMACCBF16_VV, MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV) + /* Zvbb/Zvkb instructions. */ + DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) + DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index 677276b5d76..8f2b7fdf061 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -456,6 +456,7 @@ enum riscv_insn_class + INSN_CLASS_ZVBB, + INSN_CLASS_ZVBC, + INSN_CLASS_ZVFBFMIN, ++ INSN_CLASS_ZVFBFWMA, + INSN_CLASS_ZVKB, + INSN_CLASS_ZVKG, + INSN_CLASS_ZVKNED, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index bcca1289566..dec2f41e30c 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -1932,6 +1932,10 @@ const struct riscv_opcode riscv_opcodes[] = + {"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0}, + {"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0}, + ++/* Zvfbfwma instructions. */ ++{"vfwmaccbf16.vf", 0, INSN_CLASS_ZVFBFWMA, "Vd,S,VtVm", MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF, match_opcode, 0}, ++{"vfwmaccbf16.vv", 0, INSN_CLASS_ZVFBFWMA, "Vd,Vs,VtVm", MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV, match_opcode, 0}, ++ + /* Zvbb/Zvkb instructions. */ + {"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0}, + {"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0}, +-- +2.27.0 + diff --git a/RISC-V-Fixed-typo-from-smscrind-to-smcsrind-in-riscv.patch b/RISC-V-Fixed-typo-from-smscrind-to-smcsrind-in-riscv.patch new file mode 100644 index 0000000000000000000000000000000000000000..d2790e2562e23c122b402bb417bc68a2b4748293 --- /dev/null +++ b/RISC-V-Fixed-typo-from-smscrind-to-smcsrind-in-riscv.patch @@ -0,0 +1,46 @@ +From 627d163f283953c288a596df899d728fc3a888ce Mon Sep 17 00:00:00 2001 +From: Nelson Chu +Date: Tue, 18 Jun 2024 16:15:45 +0800 +Subject: [PATCH] RISC-V: Fixed typo from smscrind to smcsrind in + riscv_implicit_subsets. + +bfd/ + * elfxx-riscv.c (riscv_implicit_subsets): Fixed type from smscrind to + smcsrind. +gas/ + * testsuite/gas/riscv/march-imply-smcsrind.d: New testcase. It fails + without applying this patch. +--- + bfd/elfxx-riscv.c | 2 +- + gas/testsuite/gas/riscv/march-imply-smcsrind.d | 6 ++++++ + 2 files changed, 7 insertions(+), 1 deletion(-) + create mode 100644 gas/testsuite/gas/riscv/march-imply-smcsrind.d + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index db7c133f92d..5427b7a12ce 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1200,7 +1200,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"zcd", "zca", check_implicit_always}, + {"zcb", "zca", check_implicit_always}, + {"smaia", "ssaia", check_implicit_always}, +- {"smscrind", "sscsrind", check_implicit_always}, ++ {"smcsrind", "sscsrind", check_implicit_always}, + {"smcntrpmf", "zicsr", check_implicit_always}, + {"smstateen", "ssstateen", check_implicit_always}, + {"smepmp", "zicsr", check_implicit_always}, +diff --git a/gas/testsuite/gas/riscv/march-imply-smcsrind.d b/gas/testsuite/gas/riscv/march-imply-smcsrind.d +new file mode 100644 +index 00000000000..e028a067a43 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-imply-smcsrind.d +@@ -0,0 +1,6 @@ ++#as: -march=rv32i_smcsrind -march-attr -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0" +-- +2.27.0 + diff --git a/RISC-V-Removed-privileged-spec-1.9.1-support-in-asse.patch b/RISC-V-Removed-privileged-spec-1.9.1-support-in-asse.patch new file mode 100644 index 0000000000000000000000000000000000000000..6a7bd1c72a20881d910fd4008d25a2efac01200a --- /dev/null +++ b/RISC-V-Removed-privileged-spec-1.9.1-support-in-asse.patch @@ -0,0 +1,3722 @@ +From 290b8dbe63514053d858fe3dedc22cdcbbcf1a18 Mon Sep 17 00:00:00 2001 +From: Nelson Chu +Date: Fri, 22 Mar 2024 15:21:27 +0800 +Subject: [PATCH] RISC-V: Removed privileged spec 1.9.1 support in assembler. + +Removed since it's may have lots of conflicts with the newer extensions, but +still keep linker recognizes it in case of linking old objects. + +gas/ + * NEWS: Updated. + * config/tc-riscv.c (riscv_set_default_priv_spec): Regard 1.9.1 as + an unknown version. + (md_show_usage): Removed privileged spec 1.9.1 information. + * testsuite/gas/riscv/attribute-05.s: Updated since privileged spec + 1.9.1 is unsupported. + * testsuite/gas/riscv/attribute-05.d: Likewise. + * testsuite/gas/riscv/attribute-12.d: Likewise. + * testsuite/gas/riscv/attribute-13.d: Likewise. + * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. + * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. + * testsuite/gas/riscv/csr.s: Likewise. + * testsuite/gas/riscv/csr-version-1p10.d: Likewise. + * testsuite/gas/riscv/csr-version-1p10.l: Likewise. + * testsuite/gas/riscv/csr-version-1p11.d: Likewise. + * testsuite/gas/riscv/csr-version-1p11.l: Likewise. + * testsuite/gas/riscv/csr-version-1p12.d: Likewise. + * testsuite/gas/riscv/csr-version-1p12.l: Likewise. + * testsuite/gas/riscv/csr-version-1p9p1.d: Removed. + * testsuite/gas/riscv/csr-version-1p9p1.l: Removed. +include/ + * opcode/riscv-opc.h: Updated since privileged spec 1.9.1 is + unsupported. +ld/ + * testsuite/ld-riscv-elf/attr-merge-priv-spec-01.d: Updated since + privileged spec 1.9.1 is unsupported. + * testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. + * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. + * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise. +--- + gas/NEWS | 3 + + gas/config/tc-riscv.c | 5 +- + gas/testsuite/gas/riscv/attribute-05.d | 3 +- + gas/testsuite/gas/riscv/attribute-05.s | 4 +- + gas/testsuite/gas/riscv/attribute-12.d | 5 +- + gas/testsuite/gas/riscv/attribute-13.d | 2 +- + gas/testsuite/gas/riscv/csr-dw-regnums.d | 13 - + gas/testsuite/gas/riscv/csr-dw-regnums.s | 13 - + gas/testsuite/gas/riscv/csr-version-1p10.d | 26 - + gas/testsuite/gas/riscv/csr-version-1p10.l | 52 - + gas/testsuite/gas/riscv/csr-version-1p11.d | 26 - + gas/testsuite/gas/riscv/csr-version-1p11.l | 52 - + gas/testsuite/gas/riscv/csr-version-1p12.d | 26 - + gas/testsuite/gas/riscv/csr-version-1p12.l | 52 - + gas/testsuite/gas/riscv/csr-version-1p9p1.d | 897 --------- + gas/testsuite/gas/riscv/csr-version-1p9p1.l | 1683 ----------------- + gas/testsuite/gas/riscv/csr.s | 33 +- + include/opcode/riscv-opc.h | 389 ++-- + .../ld-riscv-elf/attr-merge-priv-spec-01.d | 3 +- + .../ld-riscv-elf/attr-merge-priv-spec-02.d | 3 +- + .../ld-riscv-elf/attr-merge-priv-spec-03.d | 3 +- + .../ld-riscv-elf/attr-merge-priv-spec-a.s | 3 +- + .../ld-riscv-elf/attr-merge-priv-spec-b.s | 3 +- + .../attr-merge-priv-spec-failed-01.d | 3 +- + .../attr-merge-priv-spec-failed-02.d | 3 +- + .../attr-merge-priv-spec-failed-03.d | 3 +- + .../attr-merge-priv-spec-failed-04.d | 3 +- + .../attr-merge-priv-spec-failed-05.d | 3 +- + .../attr-merge-priv-spec-failed-06.d | 3 +- + 29 files changed, 218 insertions(+), 3099 deletions(-) + delete mode 100644 gas/testsuite/gas/riscv/csr-version-1p9p1.d + delete mode 100644 gas/testsuite/gas/riscv/csr-version-1p9p1.l + +diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c +index a4161420128..1980c62ea01 100644 +--- a/gas/config/tc-riscv.c ++++ b/gas/config/tc-riscv.c +@@ -210,7 +210,8 @@ riscv_set_default_priv_spec (const char *s) + obj_attribute *attr; + + RISCV_GET_PRIV_SPEC_CLASS (s, class); +- if (class != PRIV_SPEC_CLASS_NONE) ++ if (class != PRIV_SPEC_CLASS_NONE ++ && class != PRIV_SPEC_CLASS_1P9P1) + { + default_priv_spec = class; + return 1; +@@ -4987,7 +4988,7 @@ RISC-V options:\n\ + -fno-pic don't generate position-independent code (default)\n\ + -march=ISA set the RISC-V architecture\n\ + -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\ +- -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\ ++ -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.10, 1.11, 1.12)\n\ + -mabi=ABI set the RISC-V ABI\n\ + -mrelax enable relax (default)\n\ + -mno-relax disable relax\n\ +diff --git a/gas/testsuite/gas/riscv/attribute-05.d b/gas/testsuite/gas/riscv/attribute-05.d +index 9507b43976d..7d90612e0ae 100644 +--- a/gas/testsuite/gas/riscv/attribute-05.d ++++ b/gas/testsuite/gas/riscv/attribute-05.d +@@ -7,5 +7,4 @@ File Attributes + Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" + Tag_RISCV_unaligned_access: Unaligned access + Tag_RISCV_priv_spec: 1 +- Tag_RISCV_priv_spec_minor: 9 +- Tag_RISCV_priv_spec_revision: 1 ++ Tag_RISCV_priv_spec_minor: 12 +diff --git a/gas/testsuite/gas/riscv/attribute-05.s b/gas/testsuite/gas/riscv/attribute-05.s +index 49203097994..7cda21823d0 100644 +--- a/gas/testsuite/gas/riscv/attribute-05.s ++++ b/gas/testsuite/gas/riscv/attribute-05.s +@@ -1,6 +1,6 @@ + .attribute arch, "rv32g" + .attribute priv_spec, 1 +- .attribute priv_spec_minor, 9 +- .attribute priv_spec_revision, 1 ++ .attribute priv_spec_minor, 12 ++ #.attribute priv_spec_revision, version + .attribute unaligned_access, 1 + .attribute stack_align, 16 +diff --git a/gas/testsuite/gas/riscv/attribute-12.d b/gas/testsuite/gas/riscv/attribute-12.d +index 980b36cada6..1441df41cf1 100644 +--- a/gas/testsuite/gas/riscv/attribute-12.d ++++ b/gas/testsuite/gas/riscv/attribute-12.d +@@ -1,9 +1,8 @@ +-#as: -march-attr -mpriv-spec=1.9.1 ++#as: -march-attr -mpriv-spec=1.12 + #readelf: -A + #source: attribute-11.s + Attribute Section: riscv + File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: 1 +- Tag_RISCV_priv_spec_minor: 9 +- Tag_RISCV_priv_spec_revision: 1 ++ Tag_RISCV_priv_spec_minor: 12 +diff --git a/gas/testsuite/gas/riscv/attribute-13.d b/gas/testsuite/gas/riscv/attribute-13.d +index b8dfe3a7dee..b6a160c4596 100644 +--- a/gas/testsuite/gas/riscv/attribute-13.d ++++ b/gas/testsuite/gas/riscv/attribute-13.d +@@ -1,4 +1,4 @@ +-#as: -march-attr -mpriv-spec=1.9.1 ++#as: -march-attr -mpriv-spec=1.12 + #readelf: -A + #source: empty.s + Attribute Section: riscv +diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d +index cabb7c71918..2d85996ad5c 100644 +--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d ++++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d +@@ -403,19 +403,6 @@ Contents of the .* section: + DW_CFA_offset_extended_sf: r4445 \(stimecmph\) at cfa\+1396 + DW_CFA_offset_extended_sf: r4685 \(vstimecmp\) at cfa\+2356 + DW_CFA_offset_extended_sf: r4701 \(vstimecmph\) at cfa\+2420 +- DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268 +- DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292 +- DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536 +- DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340 +- DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200 +- DW_CFA_offset_extended_sf: r4897 \(mcyclecfg\) at cfa\+3204 +- DW_CFA_offset_extended_sf: r4898 \(minstretcfg\) at cfa\+3208 +- DW_CFA_offset_extended_sf: r4992 \(mbase\) at cfa\+3584 +- DW_CFA_offset_extended_sf: r4993 \(mbound\) at cfa\+3588 +- DW_CFA_offset_extended_sf: r4994 \(mibase\) at cfa\+3592 +- DW_CFA_offset_extended_sf: r4995 \(mibound\) at cfa\+3596 +- DW_CFA_offset_extended_sf: r4996 \(mdbase\) at cfa\+3600 +- DW_CFA_offset_extended_sf: r4997 \(mdbound\) at cfa\+3604 + DW_CFA_offset_extended: r4096 \(ustatus\) at cfa\+0 + DW_CFA_offset_extended_sf: r4100 \(uie\) at cfa\+16 + DW_CFA_offset_extended_sf: r4101 \(utvec\) at cfa\+20 +diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s +index 428d0770779..a4cf56dd799 100644 +--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s ++++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s +@@ -406,19 +406,6 @@ _start: + .cfi_offset vstimecmp, 2356 + .cfi_offset vstimecmph, 2420 + # dropped +- .cfi_offset ubadaddr, 268 # aliases +- .cfi_offset sbadaddr, 1292 # aliases +- .cfi_offset sptbr, 1536 # aliases +- .cfi_offset mbadaddr, 3340 # aliases +- .cfi_offset mucounteren, 3200 # aliases +- .cfi_offset mscounteren, 3204 # aliases +- .cfi_offset mhcounteren, 3208 # aliases +- .cfi_offset mbase, 3584 +- .cfi_offset mbound, 3588 +- .cfi_offset mibase, 3592 +- .cfi_offset mibound, 3596 +- .cfi_offset mdbase, 3600 +- .cfi_offset mdbound, 3604 + .cfi_offset ustatus, 0 + .cfi_offset uie, 16 + .cfi_offset utvec, 20 +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d +index dbdc077adac..2ee4ee55ecd 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.d +@@ -781,32 +781,6 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 + [ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph + [ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 +-[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval +-[ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+utval,a1 +-[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval +-[ ]+[0-9a-f]+:[ ]+14359073[ ]+csrw[ ]+stval,a1 +-[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp +-[ ]+[0-9a-f]+:[ ]+18059073[ ]+csrw[ ]+satp,a1 +-[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval +-[ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mtval,a1 +-[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,0x320 +-[ ]+[0-9a-f]+:[ ]+32059073[ ]+csrw[ ]+0x320,a1 +-[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mcyclecfg +-[ ]+[0-9a-f]+:[ ]+32159073[ ]+csrw[ ]+mcyclecfg,a1 +-[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,minstretcfg +-[ ]+[0-9a-f]+:[ ]+32259073[ ]+csrw[ ]+minstretcfg,a1 +-[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380 +-[ ]+[0-9a-f]+:[ ]+38059073[ ]+csrw[ ]+0x380,a1 +-[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381 +-[ ]+[0-9a-f]+:[ ]+38159073[ ]+csrw[ ]+0x381,a1 +-[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382 +-[ ]+[0-9a-f]+:[ ]+38259073[ ]+csrw[ ]+0x382,a1 +-[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,0x383 +-[ ]+[0-9a-f]+:[ ]+38359073[ ]+csrw[ ]+0x383,a1 +-[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,0x384 +-[ ]+[0-9a-f]+:[ ]+38459073[ ]+csrw[ ]+0x384,a1 +-[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,0x385 +-[ ]+[0-9a-f]+:[ ]+38559073[ ]+csrw[ ]+0x385,a1 + [ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus + [ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+ustatus,a1 + [ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l +index 054179a416d..63991d5023c 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.l +@@ -1511,58 +1511,6 @@ + .*Info: macro .* + .*Warning: invalid CSR `vstimecmph', needs `sstc' extension + .*Info: macro .* +-.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `sptbr' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `sptbr' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mucounteren' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mucounteren' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mscounteren' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mscounteren' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mbase' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mbase' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mbound' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mbound' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mibase' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mibase' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mibound' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mibound' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbase' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbase' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbound' for the privileged spec `1.10' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbound' for the privileged spec `1.10' +-.*Info: macro .* + .*Warning: invalid CSR `fflags', needs `f' extension + .*Info: macro .* + .*Warning: invalid CSR `fflags', needs `f' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d +index 7ba88b6d1d5..836dedef86a 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.d +@@ -781,32 +781,6 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 + [ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph + [ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 +-[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval +-[ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+utval,a1 +-[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval +-[ ]+[0-9a-f]+:[ ]+14359073[ ]+csrw[ ]+stval,a1 +-[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp +-[ ]+[0-9a-f]+:[ ]+18059073[ ]+csrw[ ]+satp,a1 +-[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval +-[ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mtval,a1 +-[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit +-[ ]+[0-9a-f]+:[ ]+32059073[ ]+csrw[ ]+mcountinhibit,a1 +-[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mcyclecfg +-[ ]+[0-9a-f]+:[ ]+32159073[ ]+csrw[ ]+mcyclecfg,a1 +-[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,minstretcfg +-[ ]+[0-9a-f]+:[ ]+32259073[ ]+csrw[ ]+minstretcfg,a1 +-[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380 +-[ ]+[0-9a-f]+:[ ]+38059073[ ]+csrw[ ]+0x380,a1 +-[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381 +-[ ]+[0-9a-f]+:[ ]+38159073[ ]+csrw[ ]+0x381,a1 +-[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382 +-[ ]+[0-9a-f]+:[ ]+38259073[ ]+csrw[ ]+0x382,a1 +-[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,0x383 +-[ ]+[0-9a-f]+:[ ]+38359073[ ]+csrw[ ]+0x383,a1 +-[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,0x384 +-[ ]+[0-9a-f]+:[ ]+38459073[ ]+csrw[ ]+0x384,a1 +-[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,0x385 +-[ ]+[0-9a-f]+:[ ]+38559073[ ]+csrw[ ]+0x385,a1 + [ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus + [ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+ustatus,a1 + [ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l +index cc365f1df41..6caec9f63a5 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.l +@@ -1507,58 +1507,6 @@ + .*Info: macro .* + .*Warning: invalid CSR `vstimecmph', needs `sstc' extension + .*Info: macro .* +-.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `sptbr' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `sptbr' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mucounteren' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mucounteren' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mscounteren' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mscounteren' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mbase' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mbase' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mbound' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mbound' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mibase' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mibase' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mibound' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mibound' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbase' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbase' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbound' for the privileged spec `1.11' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbound' for the privileged spec `1.11' +-.*Info: macro .* + .*Warning: invalid CSR `fflags', needs `f' extension + .*Info: macro .* + .*Warning: invalid CSR `fflags', needs `f' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d +index 677820b9526..beeec9a580f 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.d +@@ -781,32 +781,6 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 + [ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph + [ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 +-[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,0x43 +-[ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+0x43,a1 +-[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval +-[ ]+[0-9a-f]+:[ ]+14359073[ ]+csrw[ ]+stval,a1 +-[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp +-[ ]+[0-9a-f]+:[ ]+18059073[ ]+csrw[ ]+satp,a1 +-[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval +-[ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mtval,a1 +-[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit +-[ ]+[0-9a-f]+:[ ]+32059073[ ]+csrw[ ]+mcountinhibit,a1 +-[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mcyclecfg +-[ ]+[0-9a-f]+:[ ]+32159073[ ]+csrw[ ]+mcyclecfg,a1 +-[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,minstretcfg +-[ ]+[0-9a-f]+:[ ]+32259073[ ]+csrw[ ]+minstretcfg,a1 +-[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,0x380 +-[ ]+[0-9a-f]+:[ ]+38059073[ ]+csrw[ ]+0x380,a1 +-[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,0x381 +-[ ]+[0-9a-f]+:[ ]+38159073[ ]+csrw[ ]+0x381,a1 +-[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,0x382 +-[ ]+[0-9a-f]+:[ ]+38259073[ ]+csrw[ ]+0x382,a1 +-[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,0x383 +-[ ]+[0-9a-f]+:[ ]+38359073[ ]+csrw[ ]+0x383,a1 +-[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,0x384 +-[ ]+[0-9a-f]+:[ ]+38459073[ ]+csrw[ ]+0x384,a1 +-[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,0x385 +-[ ]+[0-9a-f]+:[ ]+38559073[ ]+csrw[ ]+0x385,a1 + [ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,0x0 + [ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+0x0,a1 + [ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,0x4 +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l +index 7a7f5f717c5..b83a0012004 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.l +@@ -1231,58 +1231,6 @@ + .*Info: macro .* + .*Warning: invalid CSR `vstimecmph', needs `sstc' extension + .*Info: macro .* +-.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `sptbr' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `sptbr' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mucounteren' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mucounteren' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mscounteren' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mscounteren' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mbase' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mbase' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mbound' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mbound' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mibase' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mibase' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mibound' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mibound' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbase' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbase' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbound' for the privileged spec `1.12' +-.*Info: macro .* +-.*Warning: invalid CSR `mdbound' for the privileged spec `1.12' +-.*Info: macro .* + .*Warning: invalid CSR `ustatus' for the privileged spec `1.12' + .*Info: macro .* + .*Warning: invalid CSR `ustatus' for the privileged spec `1.12' +diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d +deleted file mode 100644 +index f4d2b04ca6a..00000000000 +--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d ++++ /dev/null +@@ -1,897 +0,0 @@ +-#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.9.1 +-#source: csr.s +-#warning_output: csr-version-1p9p1.l +-#objdump: -dr -Mpriv-spec=1.9.1 +- +-.*:[ ]+file format .* +- +- +-Disassembly of section .text: +- +-0+000 <.text>: +-[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0 +-[ ]+[0-9a-f]+:[ ]+c0059073[ ]+csrw[ ]+cycle,a1 +-[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0 +-[ ]+[0-9a-f]+:[ ]+c0159073[ ]+csrw[ ]+time,a1 +-[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0 +-[ ]+[0-9a-f]+:[ ]+c0259073[ ]+csrw[ ]+instret,a1 +-[ ]+[0-9a-f]+:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3 +-[ ]+[0-9a-f]+:[ ]+c0359073[ ]+csrw[ ]+hpmcounter3,a1 +-[ ]+[0-9a-f]+:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4 +-[ ]+[0-9a-f]+:[ ]+c0459073[ ]+csrw[ ]+hpmcounter4,a1 +-[ ]+[0-9a-f]+:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5 +-[ ]+[0-9a-f]+:[ ]+c0559073[ ]+csrw[ ]+hpmcounter5,a1 +-[ ]+[0-9a-f]+:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6 +-[ ]+[0-9a-f]+:[ ]+c0659073[ ]+csrw[ ]+hpmcounter6,a1 +-[ ]+[0-9a-f]+:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7 +-[ ]+[0-9a-f]+:[ ]+c0759073[ ]+csrw[ ]+hpmcounter7,a1 +-[ ]+[0-9a-f]+:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8 +-[ ]+[0-9a-f]+:[ ]+c0859073[ ]+csrw[ ]+hpmcounter8,a1 +-[ ]+[0-9a-f]+:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9 +-[ ]+[0-9a-f]+:[ ]+c0959073[ ]+csrw[ ]+hpmcounter9,a1 +-[ ]+[0-9a-f]+:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10 +-[ ]+[0-9a-f]+:[ ]+c0a59073[ ]+csrw[ ]+hpmcounter10,a1 +-[ ]+[0-9a-f]+:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11 +-[ ]+[0-9a-f]+:[ ]+c0b59073[ ]+csrw[ ]+hpmcounter11,a1 +-[ ]+[0-9a-f]+:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12 +-[ ]+[0-9a-f]+:[ ]+c0c59073[ ]+csrw[ ]+hpmcounter12,a1 +-[ ]+[0-9a-f]+:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13 +-[ ]+[0-9a-f]+:[ ]+c0d59073[ ]+csrw[ ]+hpmcounter13,a1 +-[ ]+[0-9a-f]+:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14 +-[ ]+[0-9a-f]+:[ ]+c0e59073[ ]+csrw[ ]+hpmcounter14,a1 +-[ ]+[0-9a-f]+:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15 +-[ ]+[0-9a-f]+:[ ]+c0f59073[ ]+csrw[ ]+hpmcounter15,a1 +-[ ]+[0-9a-f]+:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16 +-[ ]+[0-9a-f]+:[ ]+c1059073[ ]+csrw[ ]+hpmcounter16,a1 +-[ ]+[0-9a-f]+:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17 +-[ ]+[0-9a-f]+:[ ]+c1159073[ ]+csrw[ ]+hpmcounter17,a1 +-[ ]+[0-9a-f]+:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18 +-[ ]+[0-9a-f]+:[ ]+c1259073[ ]+csrw[ ]+hpmcounter18,a1 +-[ ]+[0-9a-f]+:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19 +-[ ]+[0-9a-f]+:[ ]+c1359073[ ]+csrw[ ]+hpmcounter19,a1 +-[ ]+[0-9a-f]+:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20 +-[ ]+[0-9a-f]+:[ ]+c1459073[ ]+csrw[ ]+hpmcounter20,a1 +-[ ]+[0-9a-f]+:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21 +-[ ]+[0-9a-f]+:[ ]+c1559073[ ]+csrw[ ]+hpmcounter21,a1 +-[ ]+[0-9a-f]+:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22 +-[ ]+[0-9a-f]+:[ ]+c1659073[ ]+csrw[ ]+hpmcounter22,a1 +-[ ]+[0-9a-f]+:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23 +-[ ]+[0-9a-f]+:[ ]+c1759073[ ]+csrw[ ]+hpmcounter23,a1 +-[ ]+[0-9a-f]+:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24 +-[ ]+[0-9a-f]+:[ ]+c1859073[ ]+csrw[ ]+hpmcounter24,a1 +-[ ]+[0-9a-f]+:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25 +-[ ]+[0-9a-f]+:[ ]+c1959073[ ]+csrw[ ]+hpmcounter25,a1 +-[ ]+[0-9a-f]+:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26 +-[ ]+[0-9a-f]+:[ ]+c1a59073[ ]+csrw[ ]+hpmcounter26,a1 +-[ ]+[0-9a-f]+:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27 +-[ ]+[0-9a-f]+:[ ]+c1b59073[ ]+csrw[ ]+hpmcounter27,a1 +-[ ]+[0-9a-f]+:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28 +-[ ]+[0-9a-f]+:[ ]+c1c59073[ ]+csrw[ ]+hpmcounter28,a1 +-[ ]+[0-9a-f]+:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29 +-[ ]+[0-9a-f]+:[ ]+c1d59073[ ]+csrw[ ]+hpmcounter29,a1 +-[ ]+[0-9a-f]+:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30 +-[ ]+[0-9a-f]+:[ ]+c1e59073[ ]+csrw[ ]+hpmcounter30,a1 +-[ ]+[0-9a-f]+:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31 +-[ ]+[0-9a-f]+:[ ]+c1f59073[ ]+csrw[ ]+hpmcounter31,a1 +-[ ]+[0-9a-f]+:[ ]+c8002573[ ]+csrr[ ]+a0,cycleh +-[ ]+[0-9a-f]+:[ ]+c8059073[ ]+csrw[ ]+cycleh,a1 +-[ ]+[0-9a-f]+:[ ]+c8102573[ ]+csrr[ ]+a0,timeh +-[ ]+[0-9a-f]+:[ ]+c8159073[ ]+csrw[ ]+timeh,a1 +-[ ]+[0-9a-f]+:[ ]+c8202573[ ]+csrr[ ]+a0,instreth +-[ ]+[0-9a-f]+:[ ]+c8259073[ ]+csrw[ ]+instreth,a1 +-[ ]+[0-9a-f]+:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h +-[ ]+[0-9a-f]+:[ ]+c8359073[ ]+csrw[ ]+hpmcounter3h,a1 +-[ ]+[0-9a-f]+:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h +-[ ]+[0-9a-f]+:[ ]+c8459073[ ]+csrw[ ]+hpmcounter4h,a1 +-[ ]+[0-9a-f]+:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h +-[ ]+[0-9a-f]+:[ ]+c8559073[ ]+csrw[ ]+hpmcounter5h,a1 +-[ ]+[0-9a-f]+:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h +-[ ]+[0-9a-f]+:[ ]+c8659073[ ]+csrw[ ]+hpmcounter6h,a1 +-[ ]+[0-9a-f]+:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h +-[ ]+[0-9a-f]+:[ ]+c8759073[ ]+csrw[ ]+hpmcounter7h,a1 +-[ ]+[0-9a-f]+:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h +-[ ]+[0-9a-f]+:[ ]+c8859073[ ]+csrw[ ]+hpmcounter8h,a1 +-[ ]+[0-9a-f]+:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h +-[ ]+[0-9a-f]+:[ ]+c8959073[ ]+csrw[ ]+hpmcounter9h,a1 +-[ ]+[0-9a-f]+:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h +-[ ]+[0-9a-f]+:[ ]+c8a59073[ ]+csrw[ ]+hpmcounter10h,a1 +-[ ]+[0-9a-f]+:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h +-[ ]+[0-9a-f]+:[ ]+c8b59073[ ]+csrw[ ]+hpmcounter11h,a1 +-[ ]+[0-9a-f]+:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h +-[ ]+[0-9a-f]+:[ ]+c8c59073[ ]+csrw[ ]+hpmcounter12h,a1 +-[ ]+[0-9a-f]+:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h +-[ ]+[0-9a-f]+:[ ]+c8d59073[ ]+csrw[ ]+hpmcounter13h,a1 +-[ ]+[0-9a-f]+:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h +-[ ]+[0-9a-f]+:[ ]+c8e59073[ ]+csrw[ ]+hpmcounter14h,a1 +-[ ]+[0-9a-f]+:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h +-[ ]+[0-9a-f]+:[ ]+c8f59073[ ]+csrw[ ]+hpmcounter15h,a1 +-[ ]+[0-9a-f]+:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h +-[ ]+[0-9a-f]+:[ ]+c9059073[ ]+csrw[ ]+hpmcounter16h,a1 +-[ ]+[0-9a-f]+:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h +-[ ]+[0-9a-f]+:[ ]+c9159073[ ]+csrw[ ]+hpmcounter17h,a1 +-[ ]+[0-9a-f]+:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h +-[ ]+[0-9a-f]+:[ ]+c9259073[ ]+csrw[ ]+hpmcounter18h,a1 +-[ ]+[0-9a-f]+:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h +-[ ]+[0-9a-f]+:[ ]+c9359073[ ]+csrw[ ]+hpmcounter19h,a1 +-[ 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]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 +-[ ]+[0-9a-f]+:[ ]+7a359073[ ]+csrw[ ]+tdata3,a1 +-[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 +-[ ]+[0-9a-f]+:[ ]+7a359073[ ]+csrw[ ]+tdata3,a1 +-[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed +-[ ]+[0-9a-f]+:[ ]+01559073[ ]+csrw[ ]+seed,a1 +-[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +-[ ]+[0-9a-f]+:[ ]+00859073[ ]+csrw[ ]+vstart,a1 +-[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +-[ ]+[0-9a-f]+:[ ]+00959073[ ]+csrw[ ]+vxsat,a1 +-[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +-[ ]+[0-9a-f]+:[ ]+00a59073[ ]+csrw[ ]+vxrm,a1 +-[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +-[ ]+[0-9a-f]+:[ ]+00f59073[ ]+csrw[ ]+vcsr,a1 +-[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +-[ ]+[0-9a-f]+:[ ]+c2059073[ ]+csrw[ ]+vl,a1 +-[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +-[ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1 +-[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb +-[ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1 +diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l +deleted file mode 100644 +index 7fcd73ab7dd..00000000000 +--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l ++++ /dev/null +@@ -1,1683 +0,0 @@ +-.*Assembler messages: +-.*Warning: read-only CSR is written `csrw cycle,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw time,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw instret,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter3,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter4,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter5,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter6,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter7,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter8,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter9,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter10,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter11,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter12,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter13,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter14,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter15,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter16,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter17,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter18,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter19,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter20,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter21,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter22,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter23,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter24,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter25,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter26,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter27,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter28,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter29,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter30,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter31,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `cycleh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `cycleh', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw cycleh,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `timeh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `timeh', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw timeh,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `instreth', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `instreth', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw instreth,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter3h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter4h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter5h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter6h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter7h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter8h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter9h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter10h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter11h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter12h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter13h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter14h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter15h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter16h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter17h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter18h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter19h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter20h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter21h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter22h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter23h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter24h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter25h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter26h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter27h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter28h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter29h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter30h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hpmcounter31h,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `scounteren' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `scounteren' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `senvcfg' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `senvcfg' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `stval' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `stval' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `satp' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `satp' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw mvendorid,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw marchid,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw mimpid,a1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw mhartid,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `mconfigptr' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mconfigptr' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw mconfigptr,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `mcounteren' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mcounteren' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mstatush', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstatush' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mstatush', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstatush' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mtval' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mtval' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mtinst' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mtinst' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mtval2' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mtval2' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `menvcfg' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `menvcfg' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `menvcfgh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `menvcfgh' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `menvcfgh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `menvcfgh' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mseccfg' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mseccfg' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mseccfgh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mseccfgh' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mseccfgh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mseccfgh' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg0' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg0' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg1', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg1' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg1', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg1' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg2' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg2' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg3', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg3' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg3', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg3' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg4' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg4' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg5', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg5' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg5', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg5' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg6' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg6' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg7', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg7' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg7', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg7' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg8' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg8' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg9', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg9' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg9', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg9' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg10' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg10' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg11', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg11' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg11', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg11' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg12' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg12' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg13', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg13' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg13', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg13' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg14' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg14' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg15', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg15' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg15', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `pmpcfg15' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr0' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr0' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr1' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr1' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr2' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr2' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr3' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr3' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr4' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr4' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr5' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr5' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr6' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr6' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr7' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr7' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr8' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr8' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr9' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr9' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr10' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr10' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr11' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr11' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr12' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr12' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr13' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr13' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr14' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr14' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr15' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr15' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr16' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr16' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr17' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr17' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr18' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr18' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr19' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr19' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr20' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr20' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr21' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr21' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr22' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr22' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr23' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr23' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr24' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr24' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr25' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr25' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr26' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr26' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr27' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr27' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr28' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr28' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr29' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr29' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr30' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr30' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr31' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr31' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr32' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr32' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr33' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr33' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr34' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr34' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr35' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr35' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr36' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr36' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr37' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr37' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr38' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr38' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr39' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr39' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr40' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr40' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr41' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr41' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr42' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr42' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr43' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr43' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr44' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr44' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr45' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr45' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr46' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr46' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr47' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr47' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr48' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr48' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr49' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr49' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr50' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr50' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr51' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr51' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr52' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr52' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr53' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr53' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr54' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr54' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr55' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr55' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr56' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr56' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr57' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr57' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr58' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr58' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr59' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr59' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr60' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr60' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr61' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr61' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr62' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr62' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr63' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `pmpaddr63' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mcycleh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mcycleh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `minstreth', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `minstreth', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mcountinhibit' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mcountinhibit' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `hstatus', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstatus', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hedeleg', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hedeleg', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hideleg', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hideleg', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hie', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hie', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hcounteren', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hcounteren', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hgeie', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hgeie', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `htval', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `htval', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hip', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hip', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvip', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvip', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `htinst', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `htinst', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hgeip', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hgeip', needs `h' extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw hgeip,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `henvcfg', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `henvcfg', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `henvcfgh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `henvcfgh', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `henvcfgh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `henvcfgh', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hgatp', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hgatp', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `htimedelta', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `htimedelta', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `htimedeltah', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `htimedeltah', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `htimedeltah', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `htimedeltah', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsstatus', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsstatus', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsie', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsie', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstvec', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstvec', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsscratch', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsscratch', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsepc', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsepc', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vscause', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vscause', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstval', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstval', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsip', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsip', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsatp', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsatp', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `miselect', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `miselect', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mireg', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mireg', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mtopei', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mtopei', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mtopi', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mtopi', needs `smaia' extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw mtopi,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `mvien', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mvien', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mvip', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mvip', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `midelegh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `midelegh', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `midelegh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `midelegh', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mieh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mieh', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mieh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mieh', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mvienh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mvienh', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mvienh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mvienh', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mviph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mviph', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mviph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mviph', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `miph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `miph', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `miph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `miph', needs `smaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mcyclecfg', needs `smcntrpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mcyclecfg' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mcyclecfg', needs `smcntrpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mcyclecfg' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `minstretcfg', needs `smcntrpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `minstretcfg' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `minstretcfg', needs `smcntrpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `minstretcfg' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mcyclecfgh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mcyclecfgh', needs `smcntrpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mcyclecfgh' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mcyclecfgh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mcyclecfgh', needs `smcntrpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mcyclecfgh' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `minstretcfgh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `minstretcfgh' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `minstretcfgh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `minstretcfgh' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen0', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen0', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen1', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen1', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen2', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen2', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen3', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen3', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen0', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen0', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen1', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen1', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen2', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen2', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen3', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen3', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen0h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen0h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen1h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen1h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen2h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen2h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen3h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen3h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen0h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen0h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen0h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen0h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen1h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen1h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen1h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen1h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen2h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen2h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen2h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen2h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen3h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen3h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen3h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen3h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension +-.*Info: macro .* +-.*Warning: invalid CSR `siselect', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `siselect', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sireg', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sireg', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `stopei', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `stopei', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `stopi', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `stopi', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw stopi,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `sieh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `sieh', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `sieh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `sieh', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `siph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `siph', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `siph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `siph', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvien', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvien', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvien', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvien', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvictl', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvictl', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvictl', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvictl', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio1', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio1', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio1', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio1', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio2', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio2', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio2', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio2', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsiselect', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsiselect', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsireg', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsireg', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsireg', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsireg', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstopei', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstopei', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstopei', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstopei', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstopi', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstopi', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstopi', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstopi', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw vstopi,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `hidelegh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hidelegh', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hidelegh', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hidelegh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hidelegh', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hidelegh', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvienh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvienh', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvienh', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvienh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvienh', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hvienh', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviph', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviph', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviph', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviph', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio1h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio1h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio1h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio1h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio2h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio2h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio2h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio2h', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsieh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsieh', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsieh', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsieh', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsieh', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsieh', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsiph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsiph', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsiph', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsiph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsiph', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vsiph', needs `ssaia' extension +-.*Info: macro .* +-.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw scountovf,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension +-.*Info: macro .* +-.*Warning: invalid CSR `stimecmp', needs `sstc' extension +-.*Info: macro .* +-.*Warning: invalid CSR `stimecmp', needs `sstc' extension +-.*Info: macro .* +-.*Warning: invalid CSR `stimecmph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `stimecmph', needs `sstc' extension +-.*Info: macro .* +-.*Warning: invalid CSR `stimecmph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `stimecmph', needs `sstc' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstimecmp', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstimecmp', needs `sstc' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstimecmp', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstimecmp', needs `sstc' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstimecmph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstimecmph', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstimecmph', needs `sstc' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstimecmph', needs rv32i extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstimecmph', needs `h' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstimecmph', needs `sstc' extension +-.*Info: macro .* +-.*Warning: invalid CSR `utval' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `utval' for the privileged spec `1.9.1' +-.*Info: macro .* +-.*Warning: invalid CSR `fflags', needs `f' extension +-.*Info: macro .* +-.*Warning: invalid CSR `fflags', needs `f' extension +-.*Info: macro .* +-.*Warning: invalid CSR `frm', needs `f' extension +-.*Info: macro .* +-.*Warning: invalid CSR `frm', needs `f' extension +-.*Info: macro .* +-.*Warning: invalid CSR `fcsr', needs `f' extension +-.*Info: macro .* +-.*Warning: invalid CSR `fcsr', needs `f' extension +-.*Info: macro .* +-.*Warning: invalid CSR `seed', needs `zkr' extension +-.*Info: macro .* +-.*Warning: invalid CSR `seed', needs `zkr' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstart', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vstart', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vxsat', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vxsat', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vxrm', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vxrm', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vcsr', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vcsr', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vl', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vl', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw vl,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `vtype', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vtype', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw vtype,a1' +-.*Info: macro .* +-.*Warning: invalid CSR `vlenb', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: invalid CSR `vlenb', needs `zve32x' extension +-.*Info: macro .* +-.*Warning: read-only CSR is written `csrw vlenb,a1' +-.*Info: macro .* +diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s +index 3d8da5488a0..42bb158547b 100644 +--- a/gas/testsuite/gas/riscv/csr.s ++++ b/gas/testsuite/gas/riscv/csr.s +@@ -3,7 +3,7 @@ + csrw \val, a1 + .endm + +- # Supported privileged specs, 1.9.1, 1.10, 1.11 and 1.12. ++ # Supported privileged specs, 1.10, 1.11 and 1.12. + + # User Counter/Timers + csr cycle +@@ -441,29 +441,16 @@ + + # Supported in previous priv spec, but dropped now + +- csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10 +- csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10 +- csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10 +- csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10 +- csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11 +- csr mscounteren # 0x321 in 1.9.1, dropped in 1.10, but the value is mcyclecfg for Smcntrpmf extension +- csr mhcounteren # 0x322 in 1.9.1, dropped in 1.10, but the value is minstretcfg for Smcntrpmf extension +- csr mbase # 0x380 in 1.9.1, dropped in 1.10 +- csr mbound # 0x381 in 1.9.1, dropped in 1.10 +- csr mibase # 0x382 in 1.9.1, dropped in 1.10 +- csr mibound # 0x383 in 1.9.1, dropped in 1.10 +- csr mdbase # 0x384 in 1.9.1, dropped in 1.10 +- csr mdbound # 0x385 in 1.9.1, dropped in 1.10 +- csr ustatus # 0x0 in 1.9.1, dropped in 1.12 +- csr uie # 0x4 in 1.9.1, dropped in 1.12 +- csr utvec # 0x5 in 1.9.1, dropped in 1.12 +- csr uscratch # 0x40 in 1.9.1, dropped in 1.12 +- csr uepc # 0x41 in 1.9.1, dropped in 1.12 +- csr ucause # 0x42 in 1.9.1, dropped in 1.12 ++ csr ustatus # 0x0 in 1.10, dropped in 1.12 ++ csr uie # 0x4 in 1.10, dropped in 1.12 ++ csr utvec # 0x5 in 1.10, dropped in 1.12 ++ csr uscratch # 0x40 in 1.10, dropped in 1.12 ++ csr uepc # 0x41 in 1.10, dropped in 1.12 ++ csr ucause # 0x42 in 1.10, dropped in 1.12 + csr utval # 0x43 in 1.10, dropped in 1.12 +- csr uip # 0x44 in 1.9.1, dropped in 1.12 +- csr sedeleg # 0x102 in 1.9.1, dropped in 1.12 +- csr sideleg # 0x103 in 1.9.1, dropped in 1.12 ++ csr uip # 0x44 in 1.10, dropped in 1.12 ++ csr sedeleg # 0x102 in 1.10, dropped in 1.12 ++ csr sideleg # 0x103 in 1.10, dropped in 1.12 + + # Unprivileged CSR which are not controlled by privilege spec + +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index e77b49a6298..a24e59cf310 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -3332,12 +3332,6 @@ + #define CSR_VSIP 0x244 + #define CSR_VSATP 0x280 + /* Droppped CSR addresses. */ +-#define CSR_MBASE 0x380 +-#define CSR_MBOUND 0x381 +-#define CSR_MIBASE 0x382 +-#define CSR_MIBOUND 0x383 +-#define CSR_MDBASE 0x384 +-#define CSR_MDBOUND 0x385 + #define CSR_USTATUS 0x0 + #define CSR_UIE 0x4 + #define CSR_UTVEC 0x5 +@@ -4040,101 +4034,101 @@ DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN) + #endif /* DECLARE_INSN */ + #ifdef DECLARE_CSR + /* Unprivileged Counter/Timers CSRs. */ +-DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + /* Privileged Supervisor CSRs. */ +-DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(senvcfg, CSR_SENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + /* Privileged Machine CSRs. */ +-DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mstatush, CSR_MSTATUSH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mtinst, CSR_MTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mtval2, CSR_MTVAL2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(menvcfg, CSR_MENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +@@ -4221,98 +4215,98 @@ DECLARE_CSR(pmpaddr60, CSR_PMPADDR60, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SP + DECLARE_CSR(pmpaddr61, CSR_PMPADDR61, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(pmpaddr62, CSR_PMPADDR62, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(pmpaddr63, CSR_PMPADDR63, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + /* Privileged Hypervisor CSRs. */ + DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +@@ -4436,22 +4430,16 @@ DECLARE_CSR(stimecmph, CSR_STIMECMPH, CSR_CLASS_SSTC_32, PRIV_SPEC_CLASS_NONE, P + DECLARE_CSR(vstimecmp, CSR_VSTIMECMP, CSR_CLASS_SSTC_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH, CSR_CLASS_SSTC_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + /* Dropped CSRs. */ +-DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) +-DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) +-DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) +-DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) +-DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) +-DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) ++DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) ++DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) ++DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) ++DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) ++DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) ++DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) + DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) +-DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) +-DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) +-DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) ++DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) ++DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) ++DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) + /* Unprivileged Floating-Point CSRs. */ + DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +@@ -4483,13 +4471,6 @@ DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS + DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + #endif /* DECLARE_CSR */ + #ifdef DECLARE_CSR_ALIAS +-DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR_ALIAS(mscounteren, CSR_MCYCLECFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) +-DECLARE_CSR_ALIAS(mhcounteren, CSR_MINSTRETCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) + DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR_ALIAS(mcontrol, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR_ALIAS(mcontrol6, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-01.d +index 0aa6fe0701b..122161d7025 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-01.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-01.d +@@ -8,5 +8,4 @@ Attribute Section: riscv + File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: 1 +- Tag_RISCV_priv_spec_minor: 9 +- Tag_RISCV_priv_spec_revision: 1 ++ Tag_RISCV_priv_spec_minor: 10 +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d +index 0ac4ca7c045..f13010c9d41 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d +@@ -8,5 +8,4 @@ Attribute Section: riscv + File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: 1 +- Tag_RISCV_priv_spec_minor: 9 +- Tag_RISCV_priv_spec_revision: 1 ++ Tag_RISCV_priv_spec_minor: 10 +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d +index 69504839d72..ca004c8c107 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d +@@ -8,5 +8,4 @@ Attribute Section: riscv + File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].* + Tag_RISCV_priv_spec: 1 +- Tag_RISCV_priv_spec_minor: 9 +- Tag_RISCV_priv_spec_revision: 1 ++ Tag_RISCV_priv_spec_minor: 10 +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s +index 0b7ffea1fc2..12df9fffd87 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s +@@ -1,3 +1,2 @@ + .attribute priv_spec, 1 +- .attribute priv_spec_minor, 9 +- .attribute priv_spec_revision, 1 ++ .attribute priv_spec_minor, 10 +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s +index 0b7ffea1fc2..12df9fffd87 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s +@@ -1,3 +1,2 @@ + .attribute priv_spec, 1 +- .attribute priv_spec_minor, 9 +- .attribute priv_spec_revision, 1 ++ .attribute priv_spec_minor, 10 +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d +index 3509caeed58..7f987070ea0 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d +@@ -2,8 +2,7 @@ + #source: attr-merge-priv-spec-c.s + #as: + #ld: -r +-#warning: .*use privileged spec version 1.11.0 but the output use version 1.9.1 +-#warning: .*privileged spec version 1.9.1 can not be linked with other spec versions ++#warning: .*use privileged spec version 1.11.0 but the output use version 1.10.0 + #readelf: -A + + Attribute Section: riscv +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d +index 88defe1dced..f86ef10b6bc 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d +@@ -2,8 +2,7 @@ + #source: attr-merge-priv-spec-a.s + #as: + #ld: -r +-#warning: .*use privileged spec version 1.9.1 but the output use version 1.11.0 +-#warning: .*privileged spec version 1.9.1 can not be linked with other spec versions ++#warning: .*use privileged spec version 1.10.0 but the output use version 1.11.0 + #readelf: -A + + Attribute Section: riscv +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d +index 7a1b977bbcf..cfbb23328a6 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d +@@ -3,8 +3,7 @@ + #source: attr-merge-priv-spec-c.s + #as: + #ld: -r +-#warning: .*use privileged spec version 1.11.0 but the output use version 1.9.1 +-#warning: .*privileged spec version 1.9.1 can not be linked with other spec versions ++#warning: .*use privileged spec version 1.11.0 but the output use version 1.10.0 + #readelf: -A + + Attribute Section: riscv +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d +index 37b8afcff6f..4332597daa4 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d +@@ -3,8 +3,7 @@ + #source: attr-merge-priv-spec-c.s + #as: + #ld: -r +-#warning: .*use privileged spec version 1.11.0 but the output use version 1.9.1 +-#warning: .*privileged spec version 1.9.1 can not be linked with other spec versions ++#warning: .*use privileged spec version 1.11.0 but the output use version 1.10.0 + #readelf: -A + + Attribute Section: riscv +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d +index 30446c9dd3e..bb6573df51f 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d +@@ -3,8 +3,7 @@ + #source: attr-merge-priv-spec-a.s + #as: + #ld: -r +-#warning: .*use privileged spec version 1.9.1 but the output use version 1.11.0 +-#warning: .*privileged spec version 1.9.1 can not be linked with other spec versions ++#warning: .*use privileged spec version 1.10.0 but the output use version 1.11.0 + #readelf: -A + + Attribute Section: riscv +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d +index 8c7624c8daa..9d97ff99a7b 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d +@@ -3,8 +3,7 @@ + #source: attr-merge-priv-spec-a.s + #as: + #ld: -r +-#warning: .*use privileged spec version 1.9.1 but the output use version 1.11.0 +-#warning: .*privileged spec version 1.9.1 can not be linked with other spec versions ++#warning: .*use privileged spec version 1.10.0 but the output use version 1.11.0 + #readelf: -A + + Attribute Section: riscv +-- +2.27.0 + diff --git a/RISC-V-Support-B-Zaamo-and-Zalrsc-extensions.patch b/RISC-V-Support-B-Zaamo-and-Zalrsc-extensions.patch new file mode 100644 index 0000000000000000000000000000000000000000..19a0846c4d73a0633d40e09563c216e16ea985f2 --- /dev/null +++ b/RISC-V-Support-B-Zaamo-and-Zalrsc-extensions.patch @@ -0,0 +1,516 @@ +From 12f78b803c951df4cfb0280dd1efa6d70943624d Mon Sep 17 00:00:00 2001 +From: Nelson Chu +Date: Mon, 5 Feb 2024 09:39:37 +0800 +Subject: [PATCH] RISC-V: Support B, Zaamo and Zalrsc extensions. + +* https://github.com/riscv/riscv-b/tags +Added standard B extension back, which implies Zba, Zbb and Zbs extensions. + +* https://github.com/riscv/riscv-zaamo-zalrsc/tags +Splited standard A extension into two new extensions, Zaamo and Zalrsc. +The A extension implies Zaamo and Zalrsc extensions. + +Not sure if we need to do the similar check as i and zicsr/zifencei. + +Passed riscv[32|64]-[elf/linux] binutils testcases. + +bfd/ + * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules + for A and B extensions. The A implies Zaamo and Zalrsc, the + B implies Zba, Zbb and Zbs. + (riscv_supported_std_ext): Supported B extension with v1.0. + (riscv_supported_std_z_ext): Supported Zaamo and Zalrsc with v1.0. + (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Updated. +include/ + * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_A, Added + INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC. +opcodes/ + * riscv-opc.c (riscv_opcodes): Splited standard A extension into two + new extensions, Zaamo and Zalrsc. +gas/ + * testsuite/gas/riscv/march-imply-a.d: New testcase. + * testsuite/gas/riscv/march-imply-b.d: New testcase. + * testsuite/gas/riscv/attribute-01.d: Updated. + * testsuite/gas/riscv/attribute-02.d: Updated. + * testsuite/gas/riscv/attribute-03.d: Updated. + * testsuite/gas/riscv/attribute-04.d: Updated. + * testsuite/gas/riscv/attribute-05.d: Updated. + * testsuite/gas/riscv/attribute-10.d: Updated. + * testsuite/gas/riscv/mapping-symbols.d: Updated. + * testsuite/gas/riscv/march-imply-g.d: Updated. + * testsuite/gas/riscv/march-imply-unsupported.d: Updated. + * testsuite/gas/riscv/march-ok-reorder.d: Updated. +ld/ + * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated. + * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Updated. + * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Updated. + * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Updated. +--- + bfd/elfxx-riscv.c | 20 +- + gas/testsuite/gas/riscv/attribute-01.d | 2 +- + gas/testsuite/gas/riscv/attribute-02.d | 2 +- + gas/testsuite/gas/riscv/attribute-03.d | 2 +- + gas/testsuite/gas/riscv/attribute-04.d | 2 +- + gas/testsuite/gas/riscv/attribute-05.d | 2 +- + gas/testsuite/gas/riscv/attribute-10.d | 2 +- + gas/testsuite/gas/riscv/mapping-symbols.d | 2 +- + gas/testsuite/gas/riscv/march-imply-a.d | 6 + + gas/testsuite/gas/riscv/march-imply-b.d | 6 + + gas/testsuite/gas/riscv/march-imply-g.d | 2 +- + .../gas/riscv/march-imply-unsupported.d | 2 +- + gas/testsuite/gas/riscv/march-ok-reorder.d | 2 +- + include/opcode/riscv.h | 3 +- + .../ld-riscv-elf/attr-merge-arch-01.d | 2 +- + .../ld-riscv-elf/attr-merge-arch-02.d | 2 +- + .../ld-riscv-elf/attr-merge-arch-03.d | 2 +- + .../ld-riscv-elf/attr-merge-user-ext-01.d | 2 +- + opcodes/riscv-opc.c | 176 +++++++++--------- + 19 files changed, 132 insertions(+), 107 deletions(-) + create mode 100644 gas/testsuite/gas/riscv/march-imply-a.d + create mode 100644 gas/testsuite/gas/riscv/march-imply-b.d + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 08758faf728..0cfab116c32 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1227,6 +1227,11 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"svadu", "zicsr", check_implicit_always}, + {"smctr", "zicsr", check_implicit_always}, + {"ssctr", "zicsr", check_implicit_always}, ++ {"b", "zba", check_implicit_always}, ++ {"b", "zbb", check_implicit_always}, ++ {"b", "zbs", check_implicit_always}, ++ {"a", "zaamo", check_implicit_always}, ++ {"a", "zalrsc", check_implicit_always}, + + {"xsfvcp", "zve32x", check_implicit_always}, + {NULL, NULL, NULL} +@@ -1279,6 +1284,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] = + {"c", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, + {"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, + {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 }, ++ {"b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"v", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"h", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {NULL, 0, 0, 0, 0} +@@ -1306,7 +1312,9 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2491,10 +2499,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + return riscv_subset_supports (rps, "m"); + case INSN_CLASS_ZMMUL: + return riscv_subset_supports (rps, "zmmul"); +- case INSN_CLASS_A: +- return riscv_subset_supports (rps, "a"); ++ case INSN_CLASS_ZAAMO: ++ return riscv_subset_supports (rps, "zaamo"); + case INSN_CLASS_ZABHA: + return riscv_subset_supports (rps, "zabha"); ++ case INSN_CLASS_ZALRSC: ++ return riscv_subset_supports (rps, "zalrsc"); + case INSN_CLASS_ZAWRS: + return riscv_subset_supports (rps, "zawrs"); + case INSN_CLASS_F: +@@ -2724,10 +2734,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, + return "m"; + case INSN_CLASS_ZMMUL: + return _ ("m' or `zmmul"); +- case INSN_CLASS_A: +- return "a"; ++ case INSN_CLASS_ZAAMO: ++ return "zaamo"; + case INSN_CLASS_ZABHA: + return "zabha"; ++ case INSN_CLASS_ZALRSC: ++ return "zalrsc"; + case INSN_CLASS_ZAWRS: + return "zawrs"; + case INSN_CLASS_F: +diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d +index 612305765ab..5615d590866 100644 +--- a/gas/testsuite/gas/riscv/attribute-01.d ++++ b/gas/testsuite/gas/riscv/attribute-01.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d +index 324fd9f2171..134cc41b825 100644 +--- a/gas/testsuite/gas/riscv/attribute-02.d ++++ b/gas/testsuite/gas/riscv/attribute-02.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_xargle2p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0_xargle2p0" +diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d +index 6e1c2fbc592..70e07e3b55c 100644 +--- a/gas/testsuite/gas/riscv/attribute-03.d ++++ b/gas/testsuite/gas/riscv/attribute-03.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_xargle2p0_xfoo3p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0_xargle2p0_xfoo3p0" +diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d +index f64494a798d..21575b4a632 100644 +--- a/gas/testsuite/gas/riscv/attribute-04.d ++++ b/gas/testsuite/gas/riscv/attribute-04.d +@@ -3,4 +3,4 @@ + #source: attribute-04.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/attribute-05.d b/gas/testsuite/gas/riscv/attribute-05.d +index 7d90612e0ae..5cd63b953d9 100644 +--- a/gas/testsuite/gas/riscv/attribute-05.d ++++ b/gas/testsuite/gas/riscv/attribute-05.d +@@ -4,7 +4,7 @@ + Attribute Section: riscv + File Attributes + Tag_RISCV_stack_align: 16-bytes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" + Tag_RISCV_unaligned_access: Unaligned access + Tag_RISCV_priv_spec: 1 + Tag_RISCV_priv_spec_minor: 12 +diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d +index f46692275f1..04c322ab1dd 100644 +--- a/gas/testsuite/gas/riscv/attribute-10.d ++++ b/gas/testsuite/gas/riscv/attribute-10.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d b/gas/testsuite/gas/riscv/mapping-symbols.d +index 40df3409736..6af825d8ad3 100644 +--- a/gas/testsuite/gas/riscv/mapping-symbols.d ++++ b/gas/testsuite/gas/riscv/mapping-symbols.d +@@ -37,7 +37,7 @@ SYMBOL TABLE: + 0+04 l .text.last.section 0+00 \$d + 0+00 l d .text.section.padding 0+00 .text.section.padding + 0+00 l .text.section.padding 0+00 \$xrv32i2p1_c2p0 +-0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0 ++0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0_zaamo1p0_zalrsc1p0 + 0+06 l .text.section.padding 0+00 \$d + 0+00 l d .text.relax.align 0+00 .text.relax.align + 0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0 +diff --git a/gas/testsuite/gas/riscv/march-imply-a.d b/gas/testsuite/gas/riscv/march-imply-a.d +new file mode 100644 +index 00000000000..b2cbfcf8376 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-imply-a.d +@@ -0,0 +1,6 @@ ++#as: -march=rv32ia -march-attr -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/march-imply-b.d b/gas/testsuite/gas/riscv/march-imply-b.d +new file mode 100644 +index 00000000000..82506c9a3e1 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-imply-b.d +@@ -0,0 +1,6 @@ ++#as: -march=rv32ib -march-attr -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0" +diff --git a/gas/testsuite/gas/riscv/march-imply-g.d b/gas/testsuite/gas/riscv/march-imply-g.d +index 239b717fd7f..7e7a96785bf 100644 +--- a/gas/testsuite/gas/riscv/march-imply-g.d ++++ b/gas/testsuite/gas/riscv/march-imply-g.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/march-imply-unsupported.d b/gas/testsuite/gas/riscv/march-imply-unsupported.d +index 612305765ab..5615d590866 100644 +--- a/gas/testsuite/gas/riscv/march-imply-unsupported.d ++++ b/gas/testsuite/gas/riscv/march-imply-unsupported.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/march-ok-reorder.d b/gas/testsuite/gas/riscv/march-ok-reorder.d +index 030f8b15018..712c1bdff4d 100644 +--- a/gas/testsuite/gas/riscv/march-ok-reorder.d ++++ b/gas/testsuite/gas/riscv/march-ok-reorder.d +@@ -4,4 +4,4 @@ + + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zba1p0_xbar2p0_xfoo2p0" ++ Tag_RISCV_arch: "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zba1p0_xbar2p0_xfoo2p0" +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index c1a0f9982eb..c8baa557bb7 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -407,7 +407,6 @@ enum riscv_insn_class + + INSN_CLASS_I, + INSN_CLASS_C, +- INSN_CLASS_A, + INSN_CLASS_M, + INSN_CLASS_F, + INSN_CLASS_D, +@@ -421,6 +420,8 @@ enum riscv_insn_class + INSN_CLASS_ZIHINTNTL_AND_C, + INSN_CLASS_ZIHINTPAUSE, + INSN_CLASS_ZMMUL, ++ INSN_CLASS_ZAAMO, ++ INSN_CLASS_ZALRSC, + INSN_CLASS_ZAWRS, + INSN_CLASS_F_INX, + INSN_CLASS_D_INX, +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d +index de87f600387..0fb655c7239 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d +@@ -6,4 +6,4 @@ + + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_a2p0" ++ Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0" +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d +index 381ef850d97..10d01b1b7be 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d +@@ -6,4 +6,4 @@ + + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_a2p0" ++ Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0" +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d +index 6419fe89791..9649931d937 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d +@@ -6,4 +6,4 @@ + + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_a2p0_xbar2p0_xfoo2p0" ++ Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0_xbar2p0_xfoo2p0" +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d +index f4012dcf90d..d71dd56820e 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d +@@ -6,4 +6,4 @@ + + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_a2p1" ++ Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0" +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index 4d9deaaca64..f60525cf089 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -570,94 +570,94 @@ const struct riscv_opcode riscv_opcodes[] = + {"subw", 64, INSN_CLASS_I, "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 }, + + /* Atomic memory operation instruction subset. */ +-{"lr.w", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"sc.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoadd.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoswap.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoand.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoxor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomax.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomaxu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomin.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amominu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"lr.w.aq", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQ, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"sc.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQ, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoadd.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQ, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoswap.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoand.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQ, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQ, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoxor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQ, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomax.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQ, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomaxu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomin.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQ, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amominu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"lr.w.rl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_RL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"sc.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_RL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoadd.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_RL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoswap.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_RL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoand.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_RL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_RL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoxor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_RL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomax.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_RL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomaxu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_RL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomin.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_RL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amominu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_RL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"lr.w.aqrl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQRL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"sc.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQRL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoadd.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoswap.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoand.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQRL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoxor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomax.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomaxu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomin.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amominu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"lr.d", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"sc.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoadd.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoswap.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoand.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoxor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomax.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomaxu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomin.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amominu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"lr.d.aq", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQ, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"sc.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQ, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoadd.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQ, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoswap.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoand.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQ, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQ, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoxor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQ, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomax.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQ, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomaxu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomin.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQ, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amominu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"lr.d.rl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_RL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"sc.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_RL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoadd.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_RL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoswap.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_RL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoand.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_RL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_RL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoxor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_RL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomax.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_RL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomaxu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_RL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomin.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_RL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amominu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_RL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"lr.d.aqrl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQRL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"sc.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQRL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoadd.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoswap.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoand.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQRL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoxor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomax.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomaxu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomin.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"lr.w", 0, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_W, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"sc.w", 0, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_W, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoadd.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoswap.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoand.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoor.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoxor.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomax.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomaxu.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomin.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amominu.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"lr.w.aq", 0, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_W|MASK_AQ, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"sc.w.aq", 0, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_W|MASK_AQ, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoadd.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQ, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoswap.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoand.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQ, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoor.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQ, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoxor.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQ, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomax.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQ, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomaxu.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomin.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQ, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amominu.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"lr.w.rl", 0, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_W|MASK_RL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"sc.w.rl", 0, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_W|MASK_RL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoadd.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W|MASK_RL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoswap.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_RL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoand.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W|MASK_RL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoor.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W|MASK_RL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoxor.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W|MASK_RL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomax.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W|MASK_RL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomaxu.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_RL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomin.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W|MASK_RL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amominu.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W|MASK_RL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"lr.w.aqrl", 0, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_W|MASK_AQRL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"sc.w.aqrl", 0, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_W|MASK_AQRL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoadd.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoswap.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoand.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoor.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQRL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoxor.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomax.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomaxu.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomin.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amominu.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"lr.d", 64, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_D, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"sc.d", 64, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_D, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoadd.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoswap.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoand.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoor.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoxor.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomax.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomaxu.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomin.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amominu.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"lr.d.aq", 64, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_D|MASK_AQ, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"sc.d.aq", 64, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_D|MASK_AQ, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoadd.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQ, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoswap.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoand.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQ, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoor.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQ, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoxor.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQ, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomax.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQ, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomaxu.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomin.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQ, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amominu.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"lr.d.rl", 64, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_D|MASK_RL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"sc.d.rl", 64, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_D|MASK_RL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoadd.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D|MASK_RL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoswap.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_RL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoand.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D|MASK_RL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoor.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D|MASK_RL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoxor.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D|MASK_RL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomax.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D|MASK_RL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomaxu.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_RL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomin.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D|MASK_RL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amominu.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D|MASK_RL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"lr.d.aqrl", 64, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_D|MASK_AQRL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"sc.d.aqrl", 64, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_D|MASK_AQRL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoadd.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoswap.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoand.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoor.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQRL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoxor.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomax.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomaxu.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomin.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amominu.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, + + /* Byte and Halfword Atomic Memory Operations instruction subset. */ + {"amoadd.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE }, +-- +2.27.0 + diff --git a/RISC-V-Support-CFI-Zicfiss-and-Zicfilp-instructions-.patch b/RISC-V-Support-CFI-Zicfiss-and-Zicfilp-instructions-.patch new file mode 100644 index 0000000000000000000000000000000000000000..2373b3c8883dbd761e9adf43fc083f4cfc1c0445 --- /dev/null +++ b/RISC-V-Support-CFI-Zicfiss-and-Zicfilp-instructions-.patch @@ -0,0 +1,518 @@ +From 706cf5099a550168e606fad3f1c73615e2dd62b9 Mon Sep 17 00:00:00 2001 +From: Monk Chiang +Date: Fri, 17 Jan 2025 09:53:00 +0800 +Subject: [PATCH] RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR. + +https://github.com/riscv/riscv-cfi/releases/tag/v1.0 + +This patch only support the CFI instructions and CSR in assembler. +--- + bfd/elfxx-riscv.c | 26 +++++++++++++ + gas/config/tc-riscv.c | 4 ++ + gas/testsuite/gas/riscv/csr-dw-regnums.d | 1 + + gas/testsuite/gas/riscv/csr-dw-regnums.s | 2 + + gas/testsuite/gas/riscv/csr-version-1p10.d | 2 + + gas/testsuite/gas/riscv/csr-version-1p10.l | 4 ++ + gas/testsuite/gas/riscv/csr-version-1p11.d | 2 + + gas/testsuite/gas/riscv/csr-version-1p11.l | 4 ++ + gas/testsuite/gas/riscv/csr-version-1p12.d | 2 + + gas/testsuite/gas/riscv/csr-version-1p12.l | 4 ++ + gas/testsuite/gas/riscv/csr.s | 3 ++ + gas/testsuite/gas/riscv/march-help.l | 2 + + gas/testsuite/gas/riscv/zicfisslp-32.d | 23 +++++++++++ + gas/testsuite/gas/riscv/zicfisslp-32.s | 23 +++++++++++ + gas/testsuite/gas/riscv/zicfisslp-64.d | 23 +++++++++++ + gas/testsuite/gas/riscv/zicfisslp-64.s | 23 +++++++++++ + include/opcode/riscv-opc.h | 33 ++++++++++++++++ + include/opcode/riscv.h | 3 ++ + opcodes/riscv-opc.c | 45 ++++++++++++++++++++++ + 19 files changed, 229 insertions(+) + create mode 100644 gas/testsuite/gas/riscv/zicfisslp-32.d + create mode 100644 gas/testsuite/gas/riscv/zicfisslp-32.s + create mode 100644 gas/testsuite/gas/riscv/zicfisslp-64.d + create mode 100644 gas/testsuite/gas/riscv/zicfisslp-64.s + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index ec4651ad942..1ea65463985 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1155,6 +1155,10 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"zcf", "f", check_implicit_always}, + {"zfbfmin", "zfhmin", check_implicit_always}, + {"zfa", "f", check_implicit_always}, ++ ++ {"zicfilp", "zicsr", check_implicit_always}, ++ {"zicfiss", "zimop", check_implicit_always}, ++ {"zicfiss", "zicsr", check_implicit_always}, + {"d", "f", check_implicit_always}, + {"zfh", "zfhmin", check_implicit_always}, + {"zfhmin", "f", check_implicit_always}, +@@ -1311,6 +1315,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zimop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zicfiss", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zicfilp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2500,6 +2506,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + return riscv_subset_supports (rps, "zihintpause"); + case INSN_CLASS_ZIMOP: + return riscv_subset_supports (rps, "zimop"); ++ case INSN_CLASS_ZICFISS: ++ return riscv_subset_supports (rps, "zicfiss"); ++ case INSN_CLASS_ZICFISS_AND_ZCMOP: ++ return riscv_subset_supports (rps, "zicfiss") ++ && riscv_subset_supports (rps, "zcmop"); ++ case INSN_CLASS_ZICFILP: ++ return riscv_subset_supports (rps, "zicfilp"); + case INSN_CLASS_M: + return riscv_subset_supports (rps, "m"); + case INSN_CLASS_ZMMUL: +@@ -2722,6 +2735,19 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, + return "zicsr"; + case INSN_CLASS_ZIFENCEI: + return "zifencei"; ++ case INSN_CLASS_ZICFISS: ++ return "zicfiss"; ++ case INSN_CLASS_ZICFISS_AND_ZCMOP: ++ if (!riscv_subset_supports (rps, "zicfiss")) ++ { ++ if (!riscv_subset_supports (rps, "zcmop")) ++ return _("zicfiss' and `zcmop"); ++ else ++ return "zicfiss"; ++ } ++ return "zcmop"; ++ case INSN_CLASS_ZICFILP: ++ return "zicfilp"; + case INSN_CLASS_ZIHINTNTL: + return "zihintntl"; + case INSN_CLASS_ZIHINTNTL_AND_C: +diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c +index 289c20bf3dc..62d0290720a 100644 +--- a/gas/config/tc-riscv.c ++++ b/gas/config/tc-riscv.c +@@ -71,6 +71,7 @@ enum riscv_csr_class + CSR_CLASS_I_32, /* rv32 only */ + CSR_CLASS_F, /* f-ext only */ + CSR_CLASS_ZKR, /* zkr only */ ++ CSR_CLASS_ZICFISS, /* Zicfiss */ + CSR_CLASS_V, /* rvv only */ + CSR_CLASS_DEBUG, /* debug CSR */ + CSR_CLASS_H, /* hypervisor */ +@@ -1060,6 +1061,9 @@ riscv_csr_address (const char *csr_name, + case CSR_CLASS_ZKR: + extension = "zkr"; + break; ++ case CSR_CLASS_ZICFISS: ++ extension = "zicfiss"; ++ break; + case CSR_CLASS_V: + extension = "zve32x"; + break; +diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d +index a1d1147188d..572f76c5cf1 100644 +--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d ++++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d +@@ -408,6 +408,7 @@ Contents of the .* section: + DW_CFA_offset_extended_sf: r4447 \(sctrdepth\) at cfa\+1404 + DW_CFA_offset_extended_sf: r4686 \(vsctrctl\) at cfa\+2360 + DW_CFA_offset_extended_sf: r4942 \(mctrctl\) at cfa\+3384 ++ DW_CFA_offset_extended_sf: r4113 \(ssp\) at cfa\+324 + DW_CFA_offset_extended: r4096 \(ustatus\) at cfa\+0 + DW_CFA_offset_extended_sf: r4100 \(uie\) at cfa\+16 + DW_CFA_offset_extended_sf: r4101 \(utvec\) at cfa\+20 +diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s +index d4be4f14669..66ee9a5a149 100644 +--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s ++++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s +@@ -412,6 +412,8 @@ _start: + .cfi_offset sctrdepth, 1404 + .cfi_offset vsctrctl, 2360 + .cfi_offset mctrctl, 3384 ++ # Zicfiss extension ++ .cfi_offset ssp, 324 + + # dropped + .cfi_offset ustatus, 0 +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d +index e74da2d0b59..aaa55051804 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.d +@@ -737,6 +737,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+25459073[ ]+csrw[ ]+vsiph,a1 + [ ]+[0-9a-f]+:[ ]+12002573[ ]+csrr[ ]+a0,scountinhibit + [ ]+[0-9a-f]+:[ ]+12059073[ ]+csrw[ ]+scountinhibit,a1 ++[ ]+[0-9a-f]+:[ ]+01102573[ ]+csrr[ ]+a0,ssp ++[ ]+[0-9a-f]+:[ ]+01159073[ ]+csrw[ ]+ssp,a1 + [ ]+[0-9a-f]+:[ ]+15002573[ ]+csrr[ ]+a0,siselect + [ ]+[0-9a-f]+:[ ]+15059073[ ]+csrw[ ]+siselect,a1 + [ ]+[0-9a-f]+:[ ]+15102573[ ]+csrr[ ]+a0,sireg +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l +index d1d2a9f6adc..82d3dbbdd44 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.l +@@ -1289,6 +1289,10 @@ + .*Info: macro .* + .*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension + .*Info: macro .* ++.*Warning: invalid CSR `ssp', needs `zicfiss' extension ++.*Info: macro .* ++.*Warning: invalid CSR `ssp', needs `zicfiss' extension ++.*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d +index a9d4276a7d8..1507982afb8 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.d +@@ -737,6 +737,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+25459073[ ]+csrw[ ]+vsiph,a1 + [ ]+[0-9a-f]+:[ ]+12002573[ ]+csrr[ ]+a0,scountinhibit + [ ]+[0-9a-f]+:[ ]+12059073[ ]+csrw[ ]+scountinhibit,a1 ++[ ]+[0-9a-f]+:[ ]+01102573[ ]+csrr[ ]+a0,ssp ++[ ]+[0-9a-f]+:[ ]+01159073[ ]+csrw[ ]+ssp,a1 + [ ]+[0-9a-f]+:[ ]+15002573[ ]+csrr[ ]+a0,siselect + [ ]+[0-9a-f]+:[ ]+15059073[ ]+csrw[ ]+siselect,a1 + [ ]+[0-9a-f]+:[ ]+15102573[ ]+csrr[ ]+a0,sireg +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l +index 8888854e61e..2af63ca3211 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.l +@@ -1285,6 +1285,10 @@ + .*Info: macro .* + .*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension + .*Info: macro .* ++.*Warning: invalid CSR `ssp', needs `zicfiss' extension ++.*Info: macro .* ++.*Warning: invalid CSR `ssp', needs `zicfiss' extension ++.*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d +index 4b90845aa0f..03d4c85506f 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.d +@@ -737,6 +737,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+25459073[ ]+csrw[ ]+vsiph,a1 + [ ]+[0-9a-f]+:[ ]+12002573[ ]+csrr[ ]+a0,scountinhibit + [ ]+[0-9a-f]+:[ ]+12059073[ ]+csrw[ ]+scountinhibit,a1 ++[ ]+[0-9a-f]+:[ ]+01102573[ ]+csrr[ ]+a0,ssp ++[ ]+[0-9a-f]+:[ ]+01159073[ ]+csrw[ ]+ssp,a1 + [ ]+[0-9a-f]+:[ ]+15002573[ ]+csrr[ ]+a0,siselect + [ ]+[0-9a-f]+:[ ]+15059073[ ]+csrw[ ]+siselect,a1 + [ ]+[0-9a-f]+:[ ]+15102573[ ]+csrr[ ]+a0,sireg +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l +index ce262703cc8..ee1823ecc23 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.l +@@ -1009,6 +1009,10 @@ + .*Info: macro .* + .*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension + .*Info: macro .* ++.*Warning: invalid CSR `ssp', needs `zicfiss' extension ++.*Info: macro .* ++.*Warning: invalid CSR `ssp', needs `zicfiss' extension ++.*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension +diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s +index ad071839bb0..62394b437df 100644 +--- a/gas/testsuite/gas/riscv/csr.s ++++ b/gas/testsuite/gas/riscv/csr.s +@@ -419,6 +419,9 @@ + # Ssccfg + csr scountinhibit + ++ # Zicfiss ++ csr ssp ++ + # Sscsrind + csr siselect + csr sireg +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index 212bdc429d6..cfe5c2d86b9 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -21,6 +21,8 @@ All available -march extensions for RISC-V: + zihintpause 2.0 + zihpm 2.0 + zimop 1.0 ++ zicfiss 1.0 ++ zicfilp 1.0 + zmmul 1.0 + zaamo 1.0 + zabha 1.0 +diff --git a/gas/testsuite/gas/riscv/zicfisslp-32.d b/gas/testsuite/gas/riscv/zicfisslp-32.d +new file mode 100644 +index 00000000000..3eb22e23423 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zicfisslp-32.d +@@ -0,0 +1,23 @@ ++#as: -march=rv32gc_zicfiss_zicfilp ++#objdump: -dr ++ ++.*:[ ]+file format .* ++ ++ ++Disassembly of section .text: ++ ++0+000 <.text>: ++[ ]+[0-9a-f]+:[ ]+ce104073[ ]+sspush[ ]+ra ++[ ]+[0-9a-f]+:[ ]+ce504073[ ]+sspush[ ]+t0 ++[ ]+[0-9a-f]+:[ ]+cdc0c073[ ]+sspopchk[ ]+ra ++[ ]+[0-9a-f]+:[ ]+cdc2c073[ ]+sspopchk[ ]+t0 ++[ ]+[0-9a-f]+:[ ]+cdc04573[ ]+ssrdp[ ]+a0 ++[ ]+[0-9a-f]+:[ ]+48a5252f[ ]+ssamoswap.w[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+48a5252f[ ]+ssamoswap.w[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4ca5252f[ ]+ssamoswap.w.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4ca5252f[ ]+ssamoswap.w.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4aa5252f[ ]+ssamoswap.w.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4aa5252f[ ]+ssamoswap.w.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4ea5252f[ ]+ssamoswap.w.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4ea5252f[ ]+ssamoswap.w.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+00111017[ ]+lpad[ ]+0x111 +diff --git a/gas/testsuite/gas/riscv/zicfisslp-32.s b/gas/testsuite/gas/riscv/zicfisslp-32.s +new file mode 100644 +index 00000000000..99a7b238460 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zicfisslp-32.s +@@ -0,0 +1,23 @@ ++ # Zicfiss ++.option push ++.option arch, rv32i_zicfiss ++ sspush x1 ++ sspush x5 ++ sspopchk x1 ++ sspopchk x5 ++ ssrdp a0 ++ ssamoswap.w a0,a0,(a0) ++ ssamoswap.w a0,a0,0(a0) ++ ssamoswap.w.aq a0,a0,(a0) ++ ssamoswap.w.aq a0,a0,0(a0) ++ ssamoswap.w.rl a0,a0,(a0) ++ ssamoswap.w.rl a0,a0,0(a0) ++ ssamoswap.w.aqrl a0,a0,(a0) ++ ssamoswap.w.aqrl a0,a0,0(a0) ++.option pop ++ ++ # Zicfilp ++.option push ++.option arch, rv32ic_zicfilp ++ lpad 0x111 ++.option pop +diff --git a/gas/testsuite/gas/riscv/zicfisslp-64.d b/gas/testsuite/gas/riscv/zicfisslp-64.d +new file mode 100644 +index 00000000000..b892747343f +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zicfisslp-64.d +@@ -0,0 +1,23 @@ ++#as: -march=rv64gc_zicfiss_zicfilp ++#objdump: -dr ++ ++.*:[ ]+file format .* ++ ++ ++Disassembly of section .text: ++ ++0+000 <.text>: ++[ ]+[0-9a-f]+:[ ]+ce104073[ ]+sspush[ ]+ra ++[ ]+[0-9a-f]+:[ ]+ce504073[ ]+sspush[ ]+t0 ++[ ]+[0-9a-f]+:[ ]+cdc0c073[ ]+sspopchk[ ]+ra ++[ ]+[0-9a-f]+:[ ]+cdc2c073[ ]+sspopchk[ ]+t0 ++[ ]+[0-9a-f]+:[ ]+cdc04573[ ]+ssrdp[ ]+a0 ++[ ]+[0-9a-f]+:[ ]+48a5352f[ ]+ssamoswap.d[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+48a5352f[ ]+ssamoswap.d[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4ca5352f[ ]+ssamoswap.d.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4ca5352f[ ]+ssamoswap.d.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4aa5352f[ ]+ssamoswap.d.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4aa5352f[ ]+ssamoswap.d.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4ea5352f[ ]+ssamoswap.d.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+4ea5352f[ ]+ssamoswap.d.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+00111017[ ]+lpad[ ]+0x111 +diff --git a/gas/testsuite/gas/riscv/zicfisslp-64.s b/gas/testsuite/gas/riscv/zicfisslp-64.s +new file mode 100644 +index 00000000000..7561fa1bc40 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zicfisslp-64.s +@@ -0,0 +1,23 @@ ++ # Zicfiss ++.option push ++.option arch, rv64i_zicfiss ++ sspush x1 ++ sspush x5 ++ sspopchk x1 ++ sspopchk x5 ++ ssrdp a0 ++ ssamoswap.d a0, a0, 0(a0) ++ ssamoswap.d a0, a0, (a0) ++ ssamoswap.d.aq a0, a0, 0(a0) ++ ssamoswap.d.aq a0, a0, (a0) ++ ssamoswap.d.rl a0, a0, 0(a0) ++ ssamoswap.d.rl a0, a0, (a0) ++ ssamoswap.d.aqrl a0, a0, 0(a0) ++ ssamoswap.d.aqrl a0, a0, (a0) ++.option pop ++ ++ # Zicfilp ++.option push ++.option arch, rv64ic_zicfilp ++ lpad 0x111 ++.option pop +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index 8bf71c729aa..381cfe08b3d 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -2314,6 +2314,24 @@ + #define MASK_HSV_W 0xfe007fff + #define MATCH_HSV_D 0x6e004073 + #define MASK_HSV_D 0xfe007fff ++/* Zicfiss instructions. */ ++#define MATCH_SSPUSH 0xce004073 ++#define MASK_SSPUSH 0xfe0fffff ++#define MATCH_SSPOPCHK 0xcdc04073 ++#define MASK_SSPOPCHK 0xfff07fff ++#define MATCH_SSRDP 0xcdc04073 ++#define MASK_SSRDP 0xfffff07f ++#define MATCH_SSAMOSWAP_W 0x4800202f ++#define MASK_SSAMOSWAP_W 0xf800707f ++#define MATCH_SSAMOSWAP_D 0x4800302f ++#define MASK_SSAMOSWAP_D 0xf800707f ++#define MATCH_C_SSPUSH 0x6081 ++#define MASK_C_SSPUSH 0xffff ++#define MATCH_C_SSPOPCHK 0x6281 ++#define MASK_C_SSPOPCHK 0xffff ++/* Zicfilp instructions. */ ++#define MATCH_LPAD 0x17 ++#define MASK_LPAD 0xfff + /* Zicbop hint instructions. */ + #define MATCH_PREFETCH_I 0x6013 + #define MASK_PREFETCH_I 0x1f07fff +@@ -3608,6 +3626,8 @@ + #define CSR_SCTRDEPTH 0x15f + #define CSR_VSCTRCTL 0x24e + #define CSR_MCTRCTL 0x34e ++/* Zicfissp CSR addresses. */ ++#define CSR_SSP 0x11 + /* Unprivileged Floating-Point CSR addresses. */ + #define CSR_FFLAGS 0x1 + #define CSR_FRM 0x2 +@@ -4274,6 +4294,17 @@ DECLARE_INSN(th_sync_s, MATCH_TH_SYNC_S, MASK_TH_SYNC_S) + /* XVentanaCondOps instructions. */ + DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC) + DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN) ++ ++/* Zicfiss instructions. */ ++DECLARE_INSN(sspush, MATCH_SSPUSH, MASK_SSPUSH) ++DECLARE_INSN(sspopchk, MATCH_SSPOPCHK, MASK_SSPOPCHK) ++DECLARE_INSN(c_sspush, MATCH_C_SSPUSH, MASK_C_SSPUSH) ++DECLARE_INSN(c_sspopchk, MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK) ++DECLARE_INSN(ssrdp, MATCH_SSRDP, MASK_SSRDP) ++DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W) ++DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D) ++/* Zicfilp instructions. */ ++DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD) + #endif /* DECLARE_INSN */ + #ifdef DECLARE_CSR + /* Unprivileged Counter/Timers CSRs. */ +@@ -4702,6 +4733,8 @@ DECLARE_CSR(sctrstatus, CSR_SCTRSTATUS, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, P + DECLARE_CSR(sctrdepth, CSR_SCTRDEPTH, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vsctrctl, CSR_VSCTRCTL, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(mctrctl, CSR_MCTRCTL, CSR_CLASS_SMCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++/* Zicfiss CSRs. */ ++DECLARE_CSR(ssp, CSR_SSP, CSR_CLASS_ZICFISS, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + /* Dropped CSRs. */ + DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) + DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index 1de200ce393..bcea456efd0 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -465,6 +465,9 @@ enum riscv_insn_class + INSN_CLASS_ZVKNHA_OR_ZVKNHB, + INSN_CLASS_ZVKSED, + INSN_CLASS_ZVKSH, ++ INSN_CLASS_ZICFISS, ++ INSN_CLASS_ZICFISS_AND_ZCMOP, ++ INSN_CLASS_ZICFILP, + INSN_CLASS_ZCB, + INSN_CLASS_ZCB_AND_ZBA, + INSN_CLASS_ZCB_AND_ZBB, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index 49d2888ff66..9f42f283011 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -351,6 +351,30 @@ match_th_load_pair(const struct riscv_opcode *op, + Because of the lookup algorithm used, entries with the same opcode + name must be contiguous. */ + ++static int ++match_rs1_x1x5_opcode (const struct riscv_opcode *op, ++ insn_t insn) ++{ ++ int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; ++ return match_opcode (op, insn) && (rs1 == 1 || rs1 == 5); ++} ++ ++static int ++match_rs2_x1x5_opcode (const struct riscv_opcode *op, ++ insn_t insn) ++{ ++ int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; ++ return match_opcode (op, insn) && (rs2 == 1 || rs2 == 5); ++} ++ ++static int ++match_rd_x1x5_opcode (const struct riscv_opcode *op, ++ insn_t insn) ++{ ++ int rd = (insn & MASK_RD) >> OP_SH_RD; ++ return match_opcode (op, insn) && (rd == 1 || rd == 5); ++} ++ + const struct riscv_opcode riscv_opcodes[] = + { + /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ +@@ -505,6 +529,10 @@ const struct riscv_opcode riscv_opcodes[] = + {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, + {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, + {"or", 0, INSN_CLASS_I, "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 }, ++ ++/* Zicfilp instructions. */ ++{"lpad", 0, INSN_CLASS_ZICFILP, "u", MATCH_LPAD, MASK_LPAD, match_opcode, 0 }, ++ + {"auipc", 0, INSN_CLASS_I, "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 }, + {"seqz", 0, INSN_CLASS_I, "d,s", MATCH_SLTIU|ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS }, + {"snez", 0, INSN_CLASS_I, "d,t", MATCH_SLTU, MASK_SLTU|MASK_RS1, match_opcode, INSN_ALIAS }, +@@ -1101,6 +1129,23 @@ const struct riscv_opcode riscv_opcodes[] = + {"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 }, + {"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 }, + ++/* Zicfiss instructions. */ ++{"sspush", 0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPUSH, MASK_C_SSPUSH, match_rd_x1x5_opcode, INSN_ALIAS }, ++{"sspush", 0, INSN_CLASS_ZICFISS, "t", MATCH_SSPUSH, MASK_SSPUSH, match_rs2_x1x5_opcode, 0 }, ++{"sspopchk", 0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK, match_rd_x1x5_opcode, INSN_ALIAS }, ++{"sspopchk", 0, INSN_CLASS_ZICFISS, "s", MATCH_SSPOPCHK, MASK_SSPOPCHK, match_rs1_x1x5_opcode, 0 }, ++{"c.sspush", 0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPUSH, MASK_C_SSPUSH, match_rd_x1x5_opcode, 0 }, ++{"c.sspopchk", 0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK, match_rd_x1x5_opcode, 0 }, ++{"ssrdp", 0, INSN_CLASS_ZICFISS, "d", MATCH_SSRDP, MASK_SSRDP, match_opcode, 0 }, ++{"ssamoswap.w", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"ssamoswap.w.aq", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQ, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"ssamoswap.w.rl", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_RL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"ssamoswap.w.aqrl", 32, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQRL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"ssamoswap.d", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"ssamoswap.d.aq", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_AQ, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"ssamoswap.d.rl", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_RL, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"ssamoswap.d.aqrl", 64, INSN_CLASS_ZICFISS, "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_AQRL, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++ + /* Zimop instructions. */ + {"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R_0, match_opcode, 0 }, + {"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R_1, match_opcode, 0 }, +-- +2.27.0 + diff --git a/RISC-V-Support-S-sm-csrind-extension-csrs.patch b/RISC-V-Support-S-sm-csrind-extension-csrs.patch new file mode 100644 index 0000000000000000000000000000000000000000..d57553063147965220fa917f67f8032f760fabf9 --- /dev/null +++ b/RISC-V-Support-S-sm-csrind-extension-csrs.patch @@ -0,0 +1,1062 @@ +From 70720e1a9659f4f333eb5f5b6b475743cfea1136 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Tue, 11 Jun 2024 21:59:00 +0800 +Subject: [PATCH] RISC-V: Support S[sm]csrind extension csrs. + +This patch supports RISC-V Smcsrind/Sscsrind privilege extension csrs. +Reuse csr 'smselect/siselect', 'mireg/sireg' and 'vsiselect,vsireg' csrs +in Smaia/Ssaia extension. + +bfd/ChangeLog: + + * elfxx-riscv.c: New extensions. + +gas/ChangeLog: + + * NEWS: Updated. + * config/tc-riscv.c (enum riscv_csr_class): New extensions. + (riscv_csr_address): Ditto. + * testsuite/gas/riscv/csr-version-1p10.d: New csrs. + * testsuite/gas/riscv/csr-version-1p10.l: Ditto. + * testsuite/gas/riscv/csr-version-1p11.d: Ditto. + * testsuite/gas/riscv/csr-version-1p11.l: Ditto. + * testsuite/gas/riscv/csr-version-1p12.d: Ditto. + * testsuite/gas/riscv/csr-version-1p12.l: Ditto. + * testsuite/gas/riscv/csr.s: Ditto. + * testsuite/gas/riscv/march-help.l: New extensions. + +include/ChangeLog: + + * opcode/riscv-opc.h (CSR_MIREG2): New csr. + (CSR_MIREG3): Ditto. + (CSR_MIREG4): Ditto. + (CSR_MIREG5): Ditto. + (CSR_MIREG6): Ditto. + (CSR_SIREG2): Ditto. + (CSR_SIREG3): Ditto. + (CSR_SIREG4): Ditto. + (CSR_SIREG5): Ditto. + (CSR_SIREG6): Ditto. + (CSR_VSIREG2): Ditto. + (CSR_VSIREG3): Ditto. + (CSR_VSIREG4): Ditto. + (CSR_VSIREG5): Ditto. + (CSR_VSIREG6): Ditto. + (DECLARE_CSR): Ditto. +--- + bfd/elfxx-riscv.c | 4 + + gas/NEWS | 10 ++ + gas/config/tc-riscv.c | 22 ++++ + gas/testsuite/gas/riscv/csr-version-1p10.d | 42 +++++++ + gas/testsuite/gas/riscv/csr-version-1p10.l | 136 +++++++++++++++++++-- + gas/testsuite/gas/riscv/csr-version-1p11.d | 42 +++++++ + gas/testsuite/gas/riscv/csr-version-1p11.l | 136 +++++++++++++++++++-- + gas/testsuite/gas/riscv/csr-version-1p12.d | 42 +++++++ + gas/testsuite/gas/riscv/csr-version-1p12.l | 136 +++++++++++++++++++-- + gas/testsuite/gas/riscv/csr.s | 25 ++++ + gas/testsuite/gas/riscv/march-help.l | 2 + + include/opcode/riscv-opc.h | 46 ++++++- + 12 files changed, 601 insertions(+), 42 deletions(-) + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 0c3e23a59c2..db7c133f92d 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1200,6 +1200,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"zcd", "zca", check_implicit_always}, + {"zcb", "zca", check_implicit_always}, + {"smaia", "ssaia", check_implicit_always}, ++ {"smscrind", "sscsrind", check_implicit_always}, + {"smcntrpmf", "zicsr", check_implicit_always}, + {"smstateen", "ssstateen", check_implicit_always}, + {"smepmp", "zicsr", check_implicit_always}, +@@ -1211,6 +1212,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"shvstvecd", "h", check_implicit_always}, + {"h", "zicsr", check_implicit_always}, + {"ssaia", "zicsr", check_implicit_always}, ++ {"sscsrind", "zicsr", check_implicit_always}, + {"sscofpmf", "zicsr", check_implicit_always}, + {"sscounterenw", "zicsr", check_implicit_always}, + {"ssstateen", "zicsr", check_implicit_always}, +@@ -1384,12 +1386,14 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"smcsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smctr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"sscsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssctr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c +index 3077a33e747..5f31715df4f 100644 +--- a/gas/config/tc-riscv.c ++++ b/gas/config/tc-riscv.c +@@ -77,6 +77,8 @@ enum riscv_csr_class + CSR_CLASS_H_32, /* hypervisor, rv32 only */ + CSR_CLASS_SMAIA, /* Smaia */ + CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */ ++ CSR_CLASS_SMAIA_OR_SMCSRIND, /* Smaia/Smcsrind */ ++ CSR_CLASS_SMCSRIND, /* Smcsrind */ + CSR_CLASS_SMCNTRPMF, /* Smcntrpmf */ + CSR_CLASS_SMCNTRPMF_32, /* Smcntrpmf, rv32 only */ + CSR_CLASS_SMSTATEEN, /* Smstateen only */ +@@ -86,6 +88,10 @@ enum riscv_csr_class + CSR_CLASS_SSAIA_AND_H, /* Ssaia with H */ + CSR_CLASS_SSAIA_32, /* Ssaia, rv32 only */ + CSR_CLASS_SSAIA_AND_H_32, /* Ssaia with H, rv32 only */ ++ CSR_CLASS_SSAIA_OR_SSCSRIND, /* Ssaia/Smcsrind */ ++ CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H, /* Ssaia/Smcsrind with H */ ++ CSR_CLASS_SSCSRIND, /* Sscsrind */ ++ CSR_CLASS_SSCSRIND_AND_H, /* Sscsrind with H */ + CSR_CLASS_SSSTATEEN, /* S[ms]stateen only */ + CSR_CLASS_SSSTATEEN_AND_H, /* S[ms]stateen only (with H) */ + CSR_CLASS_SSSTATEEN_AND_H_32, /* S[ms]stateen RV32 only (with H) */ +@@ -1061,6 +1067,12 @@ riscv_csr_address (const char *csr_name, + case CSR_CLASS_SMAIA: + extension = "smaia"; + break; ++ case CSR_CLASS_SMAIA_OR_SMCSRIND: ++ extension = "smaia or smcsrind"; ++ break; ++ case CSR_CLASS_SMCSRIND: ++ extension = "smcsrind"; ++ break; + case CSR_CLASS_SMCNTRPMF_32: + is_rv32_only = true; + /* Fall through. */ +@@ -1085,6 +1097,16 @@ riscv_csr_address (const char *csr_name, + || csr_class == CSR_CLASS_SSAIA_AND_H_32); + extension = "ssaia"; + break; ++ case CSR_CLASS_SSAIA_OR_SSCSRIND: ++ case CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H: ++ is_h_required = (csr_class == CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H); ++ extension = "ssaia or sscsrind"; ++ break; ++ case CSR_CLASS_SSCSRIND: ++ case CSR_CLASS_SSCSRIND_AND_H: ++ is_h_required = (csr_class == CSR_CLASS_SSCSRIND_AND_H); ++ extension = "sscsrind"; ++ break; + case CSR_CLASS_SSSTATEEN_AND_H_32: + is_rv32_only = true; + /* Fall through. */ +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d +index 9b6cd27178b..0121e7b9240 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.d +@@ -623,6 +623,20 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 + [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph + [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 ++[ ]+[0-9a-f]+:[ ]+35002573[ ]+csrr[ ]+a0,miselect ++[ ]+[0-9a-f]+:[ ]+35059073[ ]+csrw[ ]+miselect,a1 ++[ ]+[0-9a-f]+:[ ]+35102573[ ]+csrr[ ]+a0,mireg ++[ ]+[0-9a-f]+:[ ]+35159073[ ]+csrw[ ]+mireg,a1 ++[ ]+[0-9a-f]+:[ ]+35202573[ ]+csrr[ ]+a0,mireg2 ++[ ]+[0-9a-f]+:[ ]+35259073[ ]+csrw[ ]+mireg2,a1 ++[ ]+[0-9a-f]+:[ ]+35302573[ ]+csrr[ ]+a0,mireg3 ++[ ]+[0-9a-f]+:[ ]+35359073[ ]+csrw[ ]+mireg3,a1 ++[ ]+[0-9a-f]+:[ ]+35502573[ ]+csrr[ ]+a0,mireg4 ++[ ]+[0-9a-f]+:[ ]+35559073[ ]+csrw[ ]+mireg4,a1 ++[ ]+[0-9a-f]+:[ ]+35602573[ ]+csrr[ ]+a0,mireg5 ++[ ]+[0-9a-f]+:[ ]+35659073[ ]+csrw[ ]+mireg5,a1 ++[ ]+[0-9a-f]+:[ ]+35702573[ ]+csrr[ ]+a0,mireg6 ++[ ]+[0-9a-f]+:[ ]+35759073[ ]+csrw[ ]+mireg6,a1 + [ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mcyclecfg + [ ]+[0-9a-f]+:[ ]+32159073[ ]+csrw[ ]+mcyclecfg,a1 + [ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,minstretcfg +@@ -713,6 +727,34 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+21459073[ ]+csrw[ ]+vsieh,a1 + [ ]+[0-9a-f]+:[ ]+25402573[ ]+csrr[ ]+a0,vsiph + [ ]+[0-9a-f]+:[ ]+25459073[ ]+csrw[ ]+vsiph,a1 ++[ ]+[0-9a-f]+:[ ]+15002573[ ]+csrr[ ]+a0,siselect ++[ ]+[0-9a-f]+:[ ]+15059073[ ]+csrw[ ]+siselect,a1 ++[ ]+[0-9a-f]+:[ ]+15102573[ ]+csrr[ ]+a0,sireg ++[ ]+[0-9a-f]+:[ ]+15159073[ ]+csrw[ ]+sireg,a1 ++[ ]+[0-9a-f]+:[ ]+15202573[ ]+csrr[ ]+a0,sireg2 ++[ ]+[0-9a-f]+:[ ]+15259073[ ]+csrw[ ]+sireg2,a1 ++[ ]+[0-9a-f]+:[ ]+15302573[ ]+csrr[ ]+a0,sireg3 ++[ ]+[0-9a-f]+:[ ]+15359073[ ]+csrw[ ]+sireg3,a1 ++[ ]+[0-9a-f]+:[ ]+15502573[ ]+csrr[ ]+a0,sireg4 ++[ ]+[0-9a-f]+:[ ]+15559073[ ]+csrw[ ]+sireg4,a1 ++[ ]+[0-9a-f]+:[ ]+15602573[ ]+csrr[ ]+a0,sireg5 ++[ ]+[0-9a-f]+:[ ]+15659073[ ]+csrw[ ]+sireg5,a1 ++[ ]+[0-9a-f]+:[ ]+15702573[ ]+csrr[ ]+a0,sireg6 ++[ ]+[0-9a-f]+:[ ]+15759073[ ]+csrw[ ]+sireg6,a1 ++[ ]+[0-9a-f]+:[ ]+25002573[ ]+csrr[ ]+a0,vsiselect ++[ ]+[0-9a-f]+:[ ]+25059073[ ]+csrw[ ]+vsiselect,a1 ++[ ]+[0-9a-f]+:[ ]+25102573[ ]+csrr[ ]+a0,vsireg ++[ ]+[0-9a-f]+:[ ]+25159073[ ]+csrw[ ]+vsireg,a1 ++[ ]+[0-9a-f]+:[ ]+25202573[ ]+csrr[ ]+a0,vsireg2 ++[ ]+[0-9a-f]+:[ ]+25259073[ ]+csrw[ ]+vsireg2,a1 ++[ ]+[0-9a-f]+:[ ]+25302573[ ]+csrr[ ]+a0,vsireg3 ++[ ]+[0-9a-f]+:[ ]+25359073[ ]+csrw[ ]+vsireg3,a1 ++[ ]+[0-9a-f]+:[ ]+25502573[ ]+csrr[ ]+a0,vsireg4 ++[ ]+[0-9a-f]+:[ ]+25559073[ ]+csrw[ ]+vsireg4,a1 ++[ ]+[0-9a-f]+:[ ]+25602573[ ]+csrr[ ]+a0,vsireg5 ++[ ]+[0-9a-f]+:[ ]+25659073[ ]+csrw[ ]+vsireg5,a1 ++[ ]+[0-9a-f]+:[ ]+25702573[ ]+csrr[ ]+a0,vsireg6 ++[ ]+[0-9a-f]+:[ ]+25759073[ ]+csrw[ ]+vsireg6,a1 + [ ]+[0-9a-f]+:[ ]+da002573[ ]+csrr[ ]+a0,scountovf + [ ]+[0-9a-f]+:[ ]+da059073[ ]+csrw[ ]+scountovf,a1 + [ ]+[0-9a-f]+:[ ]+72302573[ ]+csrr[ ]+a0,mhpmevent3h +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l +index 6ba3f350eb6..f36dc10b3d4 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.l +@@ -823,13 +823,13 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsatp', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `miselect', needs `smaia' extension ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `miselect', needs `smaia' extension ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `mireg', needs `smaia' extension ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `mireg', needs `smaia' extension ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `mtopei', needs `smaia' extension + .*Info: macro .* +@@ -889,6 +889,34 @@ + .*Info: macro .* + .*Warning: invalid CSR `miph', needs `smaia' extension + .*Info: macro .* ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg2', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg2', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg3', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg3', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg4', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg4', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg5', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg5', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg6', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg6', needs `smcsrind' extension ++.*Info: macro .* + .*Warning: invalid CSR `mcyclecfg', needs `smcntrpmf' extension + .*Info: macro .* + .*Warning: invalid CSR `mcyclecfg', needs `smcntrpmf' extension +@@ -1057,13 +1085,13 @@ + .*Info: macro .* + .*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension + .*Info: macro .* +-.*Warning: invalid CSR `siselect', needs `ssaia' extension ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `siselect', needs `ssaia' extension ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `sireg', needs `ssaia' extension ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `sireg', needs `ssaia' extension ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `stopei', needs `ssaia' extension + .*Info: macro .* +@@ -1125,19 +1153,19 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsiselect', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vsiselect', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vsireg', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsireg', needs `ssaia' extension ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vsireg', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsireg', needs `ssaia' extension ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vstopei', needs `h' extension + .*Info: macro .* +@@ -1241,6 +1269,90 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsiph', needs `ssaia' extension + .*Info: macro .* ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension ++.*Info: macro .* + .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension + .*Info: macro .* + .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d +index ebfa9e1ded3..5e3ed10c5a5 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.d +@@ -623,6 +623,20 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 + [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph + [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 ++[ ]+[0-9a-f]+:[ ]+35002573[ ]+csrr[ ]+a0,miselect ++[ ]+[0-9a-f]+:[ ]+35059073[ ]+csrw[ ]+miselect,a1 ++[ ]+[0-9a-f]+:[ ]+35102573[ ]+csrr[ ]+a0,mireg ++[ ]+[0-9a-f]+:[ ]+35159073[ ]+csrw[ ]+mireg,a1 ++[ ]+[0-9a-f]+:[ ]+35202573[ ]+csrr[ ]+a0,mireg2 ++[ ]+[0-9a-f]+:[ ]+35259073[ ]+csrw[ ]+mireg2,a1 ++[ ]+[0-9a-f]+:[ ]+35302573[ ]+csrr[ ]+a0,mireg3 ++[ ]+[0-9a-f]+:[ ]+35359073[ ]+csrw[ ]+mireg3,a1 ++[ ]+[0-9a-f]+:[ ]+35502573[ ]+csrr[ ]+a0,mireg4 ++[ ]+[0-9a-f]+:[ ]+35559073[ ]+csrw[ ]+mireg4,a1 ++[ ]+[0-9a-f]+:[ ]+35602573[ ]+csrr[ ]+a0,mireg5 ++[ ]+[0-9a-f]+:[ ]+35659073[ ]+csrw[ ]+mireg5,a1 ++[ ]+[0-9a-f]+:[ ]+35702573[ ]+csrr[ ]+a0,mireg6 ++[ ]+[0-9a-f]+:[ ]+35759073[ ]+csrw[ ]+mireg6,a1 + [ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mcyclecfg + [ ]+[0-9a-f]+:[ ]+32159073[ ]+csrw[ ]+mcyclecfg,a1 + [ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,minstretcfg +@@ -713,6 +727,34 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+21459073[ ]+csrw[ ]+vsieh,a1 + [ ]+[0-9a-f]+:[ ]+25402573[ ]+csrr[ ]+a0,vsiph + [ ]+[0-9a-f]+:[ ]+25459073[ ]+csrw[ ]+vsiph,a1 ++[ ]+[0-9a-f]+:[ ]+15002573[ ]+csrr[ ]+a0,siselect ++[ ]+[0-9a-f]+:[ ]+15059073[ ]+csrw[ ]+siselect,a1 ++[ ]+[0-9a-f]+:[ ]+15102573[ ]+csrr[ ]+a0,sireg ++[ ]+[0-9a-f]+:[ ]+15159073[ ]+csrw[ ]+sireg,a1 ++[ ]+[0-9a-f]+:[ ]+15202573[ ]+csrr[ ]+a0,sireg2 ++[ ]+[0-9a-f]+:[ ]+15259073[ ]+csrw[ ]+sireg2,a1 ++[ ]+[0-9a-f]+:[ ]+15302573[ ]+csrr[ ]+a0,sireg3 ++[ ]+[0-9a-f]+:[ ]+15359073[ ]+csrw[ ]+sireg3,a1 ++[ ]+[0-9a-f]+:[ ]+15502573[ ]+csrr[ ]+a0,sireg4 ++[ ]+[0-9a-f]+:[ ]+15559073[ ]+csrw[ ]+sireg4,a1 ++[ ]+[0-9a-f]+:[ ]+15602573[ ]+csrr[ ]+a0,sireg5 ++[ ]+[0-9a-f]+:[ ]+15659073[ ]+csrw[ ]+sireg5,a1 ++[ ]+[0-9a-f]+:[ ]+15702573[ ]+csrr[ ]+a0,sireg6 ++[ ]+[0-9a-f]+:[ ]+15759073[ ]+csrw[ ]+sireg6,a1 ++[ ]+[0-9a-f]+:[ ]+25002573[ ]+csrr[ ]+a0,vsiselect ++[ ]+[0-9a-f]+:[ ]+25059073[ ]+csrw[ ]+vsiselect,a1 ++[ ]+[0-9a-f]+:[ ]+25102573[ ]+csrr[ ]+a0,vsireg ++[ ]+[0-9a-f]+:[ ]+25159073[ ]+csrw[ ]+vsireg,a1 ++[ ]+[0-9a-f]+:[ ]+25202573[ ]+csrr[ ]+a0,vsireg2 ++[ ]+[0-9a-f]+:[ ]+25259073[ ]+csrw[ ]+vsireg2,a1 ++[ ]+[0-9a-f]+:[ ]+25302573[ ]+csrr[ ]+a0,vsireg3 ++[ ]+[0-9a-f]+:[ ]+25359073[ ]+csrw[ ]+vsireg3,a1 ++[ ]+[0-9a-f]+:[ ]+25502573[ ]+csrr[ ]+a0,vsireg4 ++[ ]+[0-9a-f]+:[ ]+25559073[ ]+csrw[ ]+vsireg4,a1 ++[ ]+[0-9a-f]+:[ ]+25602573[ ]+csrr[ ]+a0,vsireg5 ++[ ]+[0-9a-f]+:[ ]+25659073[ ]+csrw[ ]+vsireg5,a1 ++[ ]+[0-9a-f]+:[ ]+25702573[ ]+csrr[ ]+a0,vsireg6 ++[ ]+[0-9a-f]+:[ ]+25759073[ ]+csrw[ ]+vsireg6,a1 + [ ]+[0-9a-f]+:[ ]+da002573[ ]+csrr[ ]+a0,scountovf + [ ]+[0-9a-f]+:[ ]+da059073[ ]+csrw[ ]+scountovf,a1 + [ ]+[0-9a-f]+:[ ]+72302573[ ]+csrr[ ]+a0,mhpmevent3h +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l +index f766244ce62..511c7722f13 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.l +@@ -819,13 +819,13 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsatp', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `miselect', needs `smaia' extension ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `miselect', needs `smaia' extension ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `mireg', needs `smaia' extension ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `mireg', needs `smaia' extension ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `mtopei', needs `smaia' extension + .*Info: macro .* +@@ -885,6 +885,34 @@ + .*Info: macro .* + .*Warning: invalid CSR `miph', needs `smaia' extension + .*Info: macro .* ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg2', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg2', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg3', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg3', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg4', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg4', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg5', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg5', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg6', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg6', needs `smcsrind' extension ++.*Info: macro .* + .*Warning: invalid CSR `mcyclecfg', needs `smcntrpmf' extension + .*Info: macro .* + .*Warning: invalid CSR `mcyclecfg', needs `smcntrpmf' extension +@@ -1053,13 +1081,13 @@ + .*Info: macro .* + .*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension + .*Info: macro .* +-.*Warning: invalid CSR `siselect', needs `ssaia' extension ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `siselect', needs `ssaia' extension ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `sireg', needs `ssaia' extension ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `sireg', needs `ssaia' extension ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `stopei', needs `ssaia' extension + .*Info: macro .* +@@ -1121,19 +1149,19 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsiselect', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vsiselect', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vsireg', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsireg', needs `ssaia' extension ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vsireg', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsireg', needs `ssaia' extension ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vstopei', needs `h' extension + .*Info: macro .* +@@ -1237,6 +1265,90 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsiph', needs `ssaia' extension + .*Info: macro .* ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension ++.*Info: macro .* + .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension + .*Info: macro .* + .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d +index 4413969208c..5136e6d01f7 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.d +@@ -623,6 +623,20 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1 + [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph + [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1 ++[ ]+[0-9a-f]+:[ ]+35002573[ ]+csrr[ ]+a0,miselect ++[ ]+[0-9a-f]+:[ ]+35059073[ ]+csrw[ ]+miselect,a1 ++[ ]+[0-9a-f]+:[ ]+35102573[ ]+csrr[ ]+a0,mireg ++[ ]+[0-9a-f]+:[ ]+35159073[ ]+csrw[ ]+mireg,a1 ++[ ]+[0-9a-f]+:[ ]+35202573[ ]+csrr[ ]+a0,mireg2 ++[ ]+[0-9a-f]+:[ ]+35259073[ ]+csrw[ ]+mireg2,a1 ++[ ]+[0-9a-f]+:[ ]+35302573[ ]+csrr[ ]+a0,mireg3 ++[ ]+[0-9a-f]+:[ ]+35359073[ ]+csrw[ ]+mireg3,a1 ++[ ]+[0-9a-f]+:[ ]+35502573[ ]+csrr[ ]+a0,mireg4 ++[ ]+[0-9a-f]+:[ ]+35559073[ ]+csrw[ ]+mireg4,a1 ++[ ]+[0-9a-f]+:[ ]+35602573[ ]+csrr[ ]+a0,mireg5 ++[ ]+[0-9a-f]+:[ ]+35659073[ ]+csrw[ ]+mireg5,a1 ++[ ]+[0-9a-f]+:[ ]+35702573[ ]+csrr[ ]+a0,mireg6 ++[ ]+[0-9a-f]+:[ ]+35759073[ ]+csrw[ ]+mireg6,a1 + [ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mcyclecfg + [ ]+[0-9a-f]+:[ ]+32159073[ ]+csrw[ ]+mcyclecfg,a1 + [ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,minstretcfg +@@ -713,6 +727,34 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+21459073[ ]+csrw[ ]+vsieh,a1 + [ ]+[0-9a-f]+:[ ]+25402573[ ]+csrr[ ]+a0,vsiph + [ ]+[0-9a-f]+:[ ]+25459073[ ]+csrw[ ]+vsiph,a1 ++[ ]+[0-9a-f]+:[ ]+15002573[ ]+csrr[ ]+a0,siselect ++[ ]+[0-9a-f]+:[ ]+15059073[ ]+csrw[ ]+siselect,a1 ++[ ]+[0-9a-f]+:[ ]+15102573[ ]+csrr[ ]+a0,sireg ++[ ]+[0-9a-f]+:[ ]+15159073[ ]+csrw[ ]+sireg,a1 ++[ ]+[0-9a-f]+:[ ]+15202573[ ]+csrr[ ]+a0,sireg2 ++[ ]+[0-9a-f]+:[ ]+15259073[ ]+csrw[ ]+sireg2,a1 ++[ ]+[0-9a-f]+:[ ]+15302573[ ]+csrr[ ]+a0,sireg3 ++[ ]+[0-9a-f]+:[ ]+15359073[ ]+csrw[ ]+sireg3,a1 ++[ ]+[0-9a-f]+:[ ]+15502573[ ]+csrr[ ]+a0,sireg4 ++[ ]+[0-9a-f]+:[ ]+15559073[ ]+csrw[ ]+sireg4,a1 ++[ ]+[0-9a-f]+:[ ]+15602573[ ]+csrr[ ]+a0,sireg5 ++[ ]+[0-9a-f]+:[ ]+15659073[ ]+csrw[ ]+sireg5,a1 ++[ ]+[0-9a-f]+:[ ]+15702573[ ]+csrr[ ]+a0,sireg6 ++[ ]+[0-9a-f]+:[ ]+15759073[ ]+csrw[ ]+sireg6,a1 ++[ ]+[0-9a-f]+:[ ]+25002573[ ]+csrr[ ]+a0,vsiselect ++[ ]+[0-9a-f]+:[ ]+25059073[ ]+csrw[ ]+vsiselect,a1 ++[ ]+[0-9a-f]+:[ ]+25102573[ ]+csrr[ ]+a0,vsireg ++[ ]+[0-9a-f]+:[ ]+25159073[ ]+csrw[ ]+vsireg,a1 ++[ ]+[0-9a-f]+:[ ]+25202573[ ]+csrr[ ]+a0,vsireg2 ++[ ]+[0-9a-f]+:[ ]+25259073[ ]+csrw[ ]+vsireg2,a1 ++[ ]+[0-9a-f]+:[ ]+25302573[ ]+csrr[ ]+a0,vsireg3 ++[ ]+[0-9a-f]+:[ ]+25359073[ ]+csrw[ ]+vsireg3,a1 ++[ ]+[0-9a-f]+:[ ]+25502573[ ]+csrr[ ]+a0,vsireg4 ++[ ]+[0-9a-f]+:[ ]+25559073[ ]+csrw[ ]+vsireg4,a1 ++[ ]+[0-9a-f]+:[ ]+25602573[ ]+csrr[ ]+a0,vsireg5 ++[ ]+[0-9a-f]+:[ ]+25659073[ ]+csrw[ ]+vsireg5,a1 ++[ ]+[0-9a-f]+:[ ]+25702573[ ]+csrr[ ]+a0,vsireg6 ++[ ]+[0-9a-f]+:[ ]+25759073[ ]+csrw[ ]+vsireg6,a1 + [ ]+[0-9a-f]+:[ ]+da002573[ ]+csrr[ ]+a0,scountovf + [ ]+[0-9a-f]+:[ ]+da059073[ ]+csrw[ ]+scountovf,a1 + [ ]+[0-9a-f]+:[ ]+72302573[ ]+csrr[ ]+a0,mhpmevent3h +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l +index a7bdfddae6d..64c1976a5c0 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.l +@@ -543,13 +543,13 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsatp', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `miselect', needs `smaia' extension ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `miselect', needs `smaia' extension ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `mireg', needs `smaia' extension ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `mireg', needs `smaia' extension ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `mtopei', needs `smaia' extension + .*Info: macro .* +@@ -609,6 +609,34 @@ + .*Info: macro .* + .*Warning: invalid CSR `miph', needs `smaia' extension + .*Info: macro .* ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg2', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg2', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg3', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg3', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg4', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg4', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg5', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg5', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg6', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg6', needs `smcsrind' extension ++.*Info: macro .* + .*Warning: invalid CSR `mcyclecfg', needs `smcntrpmf' extension + .*Info: macro .* + .*Warning: invalid CSR `mcyclecfg', needs `smcntrpmf' extension +@@ -777,13 +805,13 @@ + .*Info: macro .* + .*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension + .*Info: macro .* +-.*Warning: invalid CSR `siselect', needs `ssaia' extension ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `siselect', needs `ssaia' extension ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `sireg', needs `ssaia' extension ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension + .*Info: macro .* +-.*Warning: invalid CSR `sireg', needs `ssaia' extension ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `stopei', needs `ssaia' extension + .*Info: macro .* +@@ -845,19 +873,19 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsiselect', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vsiselect', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsiselect', needs `ssaia' extension ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vsireg', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsireg', needs `ssaia' extension ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vsireg', needs `h' extension + .*Info: macro .* +-.*Warning: invalid CSR `vsireg', needs `ssaia' extension ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `vstopei', needs `h' extension + .*Info: macro .* +@@ -961,6 +989,90 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsiph', needs `ssaia' extension + .*Info: macro .* ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension ++.*Info: macro .* + .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension + .*Info: macro .* + .*Warning: invalid CSR `scountovf', needs `sscofpmf' extension +diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s +index 97ce2a2ce59..8b5e4d1cbbd 100644 +--- a/gas/testsuite/gas/riscv/csr.s ++++ b/gas/testsuite/gas/riscv/csr.s +@@ -350,6 +350,15 @@ + csr mviph + csr miph + ++ # Smcsrind ++ csr miselect ++ csr mireg ++ csr mireg2 ++ csr mireg3 ++ csr mireg4 ++ csr mireg5 ++ csr mireg6 ++ + # Smcntrpmf extension + csr mcyclecfg + csr minstretcfg +@@ -401,6 +410,22 @@ + csr vsieh + csr vsiph + ++ # Sscsrind ++ csr siselect ++ csr sireg ++ csr sireg2 ++ csr sireg3 ++ csr sireg4 ++ csr sireg5 ++ csr sireg6 ++ csr vsiselect ++ csr vsireg ++ csr vsireg2 ++ csr vsireg3 ++ csr vsireg4 ++ csr vsireg5 ++ csr vsireg6 ++ + # Sscofpmf extension + csr scountovf + csr mhpmevent3h +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index 68277a000a4..cb6cbac2da3 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -95,11 +95,13 @@ All available -march extensions for RISC-V: + zcd 1.0 + zcmp 1.0 + smaia 1.0 ++ smcsrind 1.0 + smcntrpmf 1.0 + smctr 1.0 + smepmp 1.0 + smstateen 1.0 + ssaia 1.0 ++ sscsrind 1.0 + sscofpmf 1.0 + ssctr 1.0 + ssstateen 1.0 +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index 3add95398a8..affc6b0acd7 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -3406,6 +3406,12 @@ + #define CSR_MVIENH 0x318 + #define CSR_MVIPH 0x319 + #define CSR_MIPH 0x354 ++/*Smcsrind extension */ ++#define CSR_MIREG2 0x352 ++#define CSR_MIREG3 0x353 ++#define CSR_MIREG4 0x355 ++#define CSR_MIREG5 0x356 ++#define CSR_MIREG6 0x357 + /* Smcntrpmf extension. */ + #define CSR_MCYCLECFG 0x321 + #define CSR_MINSTRETCFG 0x322 +@@ -3454,6 +3460,17 @@ + #define CSR_HVIPRIO2H 0x657 + #define CSR_VSIEH 0x214 + #define CSR_VSIPH 0x254 ++/* Sscsrind extension */ ++#define CSR_SIREG2 0x152 ++#define CSR_SIREG3 0x153 ++#define CSR_SIREG4 0x155 ++#define CSR_SIREG5 0x156 ++#define CSR_SIREG6 0x157 ++#define CSR_VSIREG2 0x252 ++#define CSR_VSIREG3 0x253 ++#define CSR_VSIREG4 0x255 ++#define CSR_VSIREG5 0x256 ++#define CSR_VSIREG6 0x257 + /* Sscofpmf extension */ + #define CSR_SCOUNTOVF 0xda0 + #define CSR_MHPMEVENT3H 0x723 +@@ -4420,8 +4437,8 @@ DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLA + DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + /* Smaia extension */ +-DECLARE_CSR(miselect, CSR_MISELECT, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +-DECLARE_CSR(mireg, CSR_MIREG, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(miselect, CSR_MISELECT, CSR_CLASS_SMAIA_OR_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(mireg, CSR_MIREG, CSR_CLASS_SMAIA_OR_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(mtopei, CSR_MTOPEI, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(mtopi, CSR_MTOPI, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(mvien, CSR_MVIEN, CSR_CLASS_SMAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +@@ -4431,6 +4448,12 @@ DECLARE_CSR(mieh, CSR_MIEH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_ + DECLARE_CSR(mvienh, CSR_MVIENH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(mviph, CSR_MVIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(miph, CSR_MIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++/* Smcsrind extension */ ++DECLARE_CSR(mireg2, CSR_MIREG2, CSR_CLASS_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(mireg3, CSR_MIREG3, CSR_CLASS_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(mireg4, CSR_MIREG4, CSR_CLASS_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(mireg5, CSR_MIREG5, CSR_CLASS_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(mireg6, CSR_MIREG6, CSR_CLASS_SMCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + /* Smcntrpmf extension (incompatible with the privileged spec v1.9.1). */ + DECLARE_CSR(mcyclecfg, CSR_MCYCLECFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(minstretcfg, CSR_MINSTRETCFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) +@@ -4458,8 +4481,8 @@ DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_ + DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H, CSR_CLASS_SSSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + /* Ssaia extension */ +-DECLARE_CSR(siselect, CSR_SISELECT, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +-DECLARE_CSR(sireg, CSR_SIREG, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(siselect, CSR_SISELECT, CSR_CLASS_SSAIA_OR_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(sireg, CSR_SIREG, CSR_CLASS_SSAIA_OR_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(stopei, CSR_STOPEI, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(stopi, CSR_STOPI, CSR_CLASS_SSAIA, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(sieh, CSR_SIEH, CSR_CLASS_SSAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +@@ -4468,8 +4491,8 @@ DECLARE_CSR(hvien, CSR_HVIEN, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_ + DECLARE_CSR(hvictl, CSR_HVICTL, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(hviprio1, CSR_HVIPRIO1, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(hviprio2, CSR_HVIPRIO2, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +-DECLARE_CSR(vsiselect, CSR_VSISELECT, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +-DECLARE_CSR(vsireg, CSR_VSIREG, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(vsiselect, CSR_VSISELECT, CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(vsireg, CSR_VSIREG, CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vstopei, CSR_VSTOPEI, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vstopi, CSR_VSTOPI, CSR_CLASS_SSAIA_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(hidelegh, CSR_HIDELEGH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +@@ -4479,6 +4502,17 @@ DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_ + DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vsieh, CSR_VSIEH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vsiph, CSR_VSIPH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++/* Sscsrind extension */ ++DECLARE_CSR(sireg2, CSR_SIREG2, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(sireg3, CSR_SIREG3, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(sireg4, CSR_SIREG4, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(sireg5, CSR_SIREG5, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(sireg6, CSR_SIREG6, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(vsireg2, CSR_VSIREG2, CSR_CLASS_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(vsireg3, CSR_VSIREG3, CSR_CLASS_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(vsireg4, CSR_VSIREG4, CSR_CLASS_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(vsireg5, CSR_VSIREG5, CSR_CLASS_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(vsireg6, CSR_VSIREG6, CSR_CLASS_SSCSRIND_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + /* Sscofpmf extension */ + DECLARE_CSR(scountovf, CSR_SCOUNTOVF, CSR_CLASS_SSCOFPMF, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +-- +2.27.0 + diff --git a/RISC-V-Support-Smcdeleg-and-Ssccfg-extensions.patch b/RISC-V-Support-Smcdeleg-and-Ssccfg-extensions.patch new file mode 100644 index 0000000000000000000000000000000000000000..5fa12dffcdbd8113b430211ce285c81d212fc0ca --- /dev/null +++ b/RISC-V-Support-Smcdeleg-and-Ssccfg-extensions.patch @@ -0,0 +1,240 @@ +From 17bbcc5656baaf0f61ee1d09e5e02f3443583269 Mon Sep 17 00:00:00 2001 +From: Nelson Chu +Date: Thu, 20 Jun 2024 12:53:59 +0800 +Subject: [PATCH] RISC-V: Support Smcdeleg and Ssccfg extensions. + +https://github.com/riscv/riscv-smcdeleg-ssccfg/blob/v1.0.0/readme.adoc + +Added a new CSR, scountinhibit (0x120), for supervisor counter setup, should +be controlled by Ssccfg. + +Simialr to Smcsrind imply Sscsrind, all added CSRs should be avaiable for +machine-level environment, Smcdeleg seems should imply Ssccfg. + +Besides, spec said - These extensions depend on the Zicntr and/or Zihpm +extensions, and on the Sscsrind extension. Since Zicntr and Zihpm are +enabled by i-ext for now, that means they are always enabled, Smcsrind and +Ssccfg only imply Sscsrind should be enough. + +bfd/ + * elfxx-riscv.c (riscv_implicit_subsets): Added smcdeleg imply ssccfg, + and ssccfg imply sscsrind. + (riscv_supported_std_z_ext): Added smcdeleg and ssccfg with v1.0. +gas/ + * config/tc-riscv.c (riscv_csr_address): Handle CSR_CLASS_SSCCFG. + * testsuite/gas/riscv/csr-version-1p10.d: Updated. + * testsuite/gas/riscv/csr-version-1p10.l: Updated. + * testsuite/gas/riscv/csr-version-1p11.d: Updated. + * testsuite/gas/riscv/csr-version-1p11.l: Updated. + * testsuite/gas/riscv/csr-version-1p12.d: Updated. + * testsuite/gas/riscv/csr-version-1p12.l: Updated. + * testsuite/gas/riscv/csr.s: Updated. + * testsuite/gas/riscv/march-help.l: Updated. +include/ + * opcode/riscv-opc.h: Added support for scountinhibit CSR. +--- + bfd/elfxx-riscv.c | 4 ++++ + gas/config/tc-riscv.c | 4 ++++ + gas/testsuite/gas/riscv/csr-version-1p10.d | 2 ++ + gas/testsuite/gas/riscv/csr-version-1p10.l | 4 ++++ + gas/testsuite/gas/riscv/csr-version-1p11.d | 2 ++ + gas/testsuite/gas/riscv/csr-version-1p11.l | 4 ++++ + gas/testsuite/gas/riscv/csr-version-1p12.d | 2 ++ + gas/testsuite/gas/riscv/csr-version-1p12.l | 4 ++++ + gas/testsuite/gas/riscv/csr.s | 3 +++ + gas/testsuite/gas/riscv/march-help.l | 2 ++ + include/opcode/riscv-opc.h | 4 ++++ + 11 files changed, 35 insertions(+) + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 5427b7a12ce..212d83728df 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1200,6 +1200,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"zcd", "zca", check_implicit_always}, + {"zcb", "zca", check_implicit_always}, + {"smaia", "ssaia", check_implicit_always}, ++ {"smcdeleg", "ssccfg", check_implicit_always}, ++ {"ssccfg", "sscsrind", check_implicit_always}, + {"smcsrind", "sscsrind", check_implicit_always}, + {"smcntrpmf", "zicsr", check_implicit_always}, + {"smstateen", "ssstateen", check_implicit_always}, +@@ -1386,12 +1388,14 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"smcdeleg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smcsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smctr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ssccfg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c +index 5f31715df4f..869837e7964 100644 +--- a/gas/config/tc-riscv.c ++++ b/gas/config/tc-riscv.c +@@ -90,6 +90,7 @@ enum riscv_csr_class + CSR_CLASS_SSAIA_AND_H_32, /* Ssaia with H, rv32 only */ + CSR_CLASS_SSAIA_OR_SSCSRIND, /* Ssaia/Smcsrind */ + CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H, /* Ssaia/Smcsrind with H */ ++ CSR_CLASS_SSCCFG, /* Ssccfg */ + CSR_CLASS_SSCSRIND, /* Sscsrind */ + CSR_CLASS_SSCSRIND_AND_H, /* Sscsrind with H */ + CSR_CLASS_SSSTATEEN, /* S[ms]stateen only */ +@@ -1102,6 +1103,9 @@ riscv_csr_address (const char *csr_name, + is_h_required = (csr_class == CSR_CLASS_SSAIA_OR_SSCSRIND_AND_H); + extension = "ssaia or sscsrind"; + break; ++ case CSR_CLASS_SSCCFG: ++ extension = "ssccfg"; ++ break; + case CSR_CLASS_SSCSRIND: + case CSR_CLASS_SSCSRIND_AND_H: + is_h_required = (csr_class == CSR_CLASS_SSCSRIND_AND_H); +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d +index 0121e7b9240..57e6b27e32c 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.d +@@ -727,6 +727,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+21459073[ ]+csrw[ ]+vsieh,a1 + [ ]+[0-9a-f]+:[ ]+25402573[ ]+csrr[ ]+a0,vsiph + [ ]+[0-9a-f]+:[ ]+25459073[ ]+csrw[ ]+vsiph,a1 ++[ ]+[0-9a-f]+:[ ]+12002573[ ]+csrr[ ]+a0,scountinhibit ++[ ]+[0-9a-f]+:[ ]+12059073[ ]+csrw[ ]+scountinhibit,a1 + [ ]+[0-9a-f]+:[ ]+15002573[ ]+csrr[ ]+a0,siselect + [ ]+[0-9a-f]+:[ ]+15059073[ ]+csrw[ ]+siselect,a1 + [ ]+[0-9a-f]+:[ ]+15102573[ ]+csrr[ ]+a0,sireg +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l +index f36dc10b3d4..1d1299183e7 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.l +@@ -1269,6 +1269,10 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsiph', needs `ssaia' extension + .*Info: macro .* ++.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension ++.*Info: macro .* ++.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension ++.*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d +index 5e3ed10c5a5..e948481d72d 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.d +@@ -727,6 +727,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+21459073[ ]+csrw[ ]+vsieh,a1 + [ ]+[0-9a-f]+:[ ]+25402573[ ]+csrr[ ]+a0,vsiph + [ ]+[0-9a-f]+:[ ]+25459073[ ]+csrw[ ]+vsiph,a1 ++[ ]+[0-9a-f]+:[ ]+12002573[ ]+csrr[ ]+a0,scountinhibit ++[ ]+[0-9a-f]+:[ ]+12059073[ ]+csrw[ ]+scountinhibit,a1 + [ ]+[0-9a-f]+:[ ]+15002573[ ]+csrr[ ]+a0,siselect + [ ]+[0-9a-f]+:[ ]+15059073[ ]+csrw[ ]+siselect,a1 + [ ]+[0-9a-f]+:[ ]+15102573[ ]+csrr[ ]+a0,sireg +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l +index 511c7722f13..aa649eb51b9 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.l +@@ -1265,6 +1265,10 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsiph', needs `ssaia' extension + .*Info: macro .* ++.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension ++.*Info: macro .* ++.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension ++.*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d +index 5136e6d01f7..5075ef3bfba 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.d +@@ -727,6 +727,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+21459073[ ]+csrw[ ]+vsieh,a1 + [ ]+[0-9a-f]+:[ ]+25402573[ ]+csrr[ ]+a0,vsiph + [ ]+[0-9a-f]+:[ ]+25459073[ ]+csrw[ ]+vsiph,a1 ++[ ]+[0-9a-f]+:[ ]+12002573[ ]+csrr[ ]+a0,scountinhibit ++[ ]+[0-9a-f]+:[ ]+12059073[ ]+csrw[ ]+scountinhibit,a1 + [ ]+[0-9a-f]+:[ ]+15002573[ ]+csrr[ ]+a0,siselect + [ ]+[0-9a-f]+:[ ]+15059073[ ]+csrw[ ]+siselect,a1 + [ ]+[0-9a-f]+:[ ]+15102573[ ]+csrr[ ]+a0,sireg +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l +index 64c1976a5c0..a88c88cb760 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.l +@@ -989,6 +989,10 @@ + .*Info: macro .* + .*Warning: invalid CSR `vsiph', needs `ssaia' extension + .*Info: macro .* ++.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension ++.*Info: macro .* ++.*Warning: invalid CSR `scountinhibit', needs `ssccfg' extension ++.*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension + .*Info: macro .* + .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension +diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s +index 8b5e4d1cbbd..79c7758111c 100644 +--- a/gas/testsuite/gas/riscv/csr.s ++++ b/gas/testsuite/gas/riscv/csr.s +@@ -410,6 +410,9 @@ + csr vsieh + csr vsiph + ++ # Ssccfg ++ csr scountinhibit ++ + # Sscsrind + csr siselect + csr sireg +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index cb6cbac2da3..5d940249e2b 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -95,12 +95,14 @@ All available -march extensions for RISC-V: + zcd 1.0 + zcmp 1.0 + smaia 1.0 ++ smcdeleg 1.0 + smcsrind 1.0 + smcntrpmf 1.0 + smctr 1.0 + smepmp 1.0 + smstateen 1.0 + ssaia 1.0 ++ ssccfg 1.0 + sscsrind 1.0 + sscofpmf 1.0 + ssctr 1.0 +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index affc6b0acd7..506ddd492d7 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -3460,6 +3460,8 @@ + #define CSR_HVIPRIO2H 0x657 + #define CSR_VSIEH 0x214 + #define CSR_VSIPH 0x254 ++/* Ssccfg CSR address. */ ++#define CSR_SCOUNTINHIBIT 0x120 + /* Sscsrind extension */ + #define CSR_SIREG2 0x152 + #define CSR_SIREG3 0x153 +@@ -4502,6 +4504,8 @@ DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_ + DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vsieh, CSR_VSIEH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vsiph, CSR_VSIPH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++/* Ssccfg CSR. */ ++DECLARE_CSR(scountinhibit, CSR_SCOUNTINHIBIT, CSR_CLASS_SSCCFG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + /* Sscsrind extension */ + DECLARE_CSR(sireg2, CSR_SIREG2, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(sireg3, CSR_SIREG3, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +-- +2.27.0 + diff --git a/RISC-V-Support-Zacas-extension.patch b/RISC-V-Support-Zacas-extension.patch new file mode 100644 index 0000000000000000000000000000000000000000..c40eb0be3ec9c028291cdb8867dac77ecf29f07b --- /dev/null +++ b/RISC-V-Support-Zacas-extension.patch @@ -0,0 +1,401 @@ +From 18e7cb42a2c209af2acf569252671eb82c363fff Mon Sep 17 00:00:00 2001 +From: Gianluca Guida +Date: Wed, 31 May 2023 17:28:56 +0100 +Subject: [PATCH] RISC-V: Support Zacas extension. + +https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0 + +The Zacas extension introduce compare-and-swap instructions to operate +on 32-bit, 64-bit and 128-bit (RV64 only) data values. + +It introduces three new instructions: + - amocas.w (32-bit CAS) + - amocas.d (64-bit CAS) + - amocas.q (128-bit CAS, RV64 only) + +Like other AMOs in the A extension, Zacas instructions have '.aq', +'.rl' and '.aqrl' variations. + +bfd/ChangeLog: + + * elfxx-riscv.c (riscv_implicit_subsets): 'A' implied by 'Zacas'. + (riscv_supported_std_z_ext): Add 'Zacas' extension. + (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): + Handle INSN_CLASS_ZACAS case. + +gas/ChangeLog: + + * NEWS: Updated. + * testsuite/gas/riscv/march-help.l: Updated. + * testsuite/gas/riscv/zacas-32.d: New test (RV32). + * testsuite/gas/riscv/zacas-fail-32.d: Likewise. + * testsuite/gas/riscv/zacas-64.d: New test (RV64). + * testsuite/gas/riscv/zacas-fail-64.d: Likewise. + * testsuite/gas/riscv/zacas.s: New test source. + * testsuite/gas/riscv/zacas-fail.s: Likewise. + * testsuite/gas/riscv/zacas-fail-32.l: New file. + * testsuite/gas/riscv/zacas-fail-64.l: Likewise. + +include/ChangeLog: + + * include/opcode/riscv.h (INSN_CLASS_ZACAS): New definition. + * include/opcode/riscv-opc.h (MATCH_AMOCAS_W, MASK_AMOCAS_W) + (MATCH_AMOCAS_D, MASK_AMOCAS_D, MATCH_AMOCAS_Q, MASK_AMOCAS_Q): + Likewise. + (amocas_w, amocas_d, amocas_q): Declare instructions. + +opcodes/ChangeLog: + + * riscv-opc.c (match_rs2_rd_even): New function. + (amocas_w, amocas_d, amocas_q, amocas_w.aq) + (amocas_d.aq, amocas_q.aq, amocas_w.rl, amocas_d.rl, amocas_q.rl) + (amocas_w.aqrl, amocas_d.aqrl, amocas_q.aqrl): Add instructions. +--- + bfd/elfxx-riscv.c | 6 +++++ + gas/NEWS | 2 ++ + gas/testsuite/gas/riscv/march-help.l | 1 + + gas/testsuite/gas/riscv/zacas-32.d | 26 +++++++++++++++++++ + gas/testsuite/gas/riscv/zacas-64.d | 34 +++++++++++++++++++++++++ + gas/testsuite/gas/riscv/zacas-fail-32.d | 3 +++ + gas/testsuite/gas/riscv/zacas-fail-32.l | 17 +++++++++++++ + gas/testsuite/gas/riscv/zacas-fail-64.d | 3 +++ + gas/testsuite/gas/riscv/zacas-fail-64.l | 9 +++++++ + gas/testsuite/gas/riscv/zacas-fail.s | 17 +++++++++++++ + gas/testsuite/gas/riscv/zacas.s | 27 ++++++++++++++++++++ + include/opcode/riscv-opc.h | 11 ++++++++ + include/opcode/riscv.h | 1 + + opcodes/riscv-opc.c | 26 +++++++++++++++++++ + 14 files changed, 183 insertions(+) + create mode 100644 gas/testsuite/gas/riscv/zacas-32.d + create mode 100644 gas/testsuite/gas/riscv/zacas-64.d + create mode 100644 gas/testsuite/gas/riscv/zacas-fail-32.d + create mode 100644 gas/testsuite/gas/riscv/zacas-fail-32.l + create mode 100644 gas/testsuite/gas/riscv/zacas-fail-64.d + create mode 100644 gas/testsuite/gas/riscv/zacas-fail-64.l + create mode 100644 gas/testsuite/gas/riscv/zacas-fail.s + create mode 100644 gas/testsuite/gas/riscv/zacas.s + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 0cfab116c32..17179a3c637 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1118,6 +1118,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"v", "zve64d", check_implicit_always}, + {"v", "zvl128b", check_implicit_always}, + {"zabha", "a", check_implicit_always}, ++ {"zacas", "a", check_implicit_always}, + {"zvfbfmin", "zve32f", check_implicit_always}, + {"zvfbfwma", "zve32f", check_implicit_always}, + {"zvfbfwma", "zfbfmin", check_implicit_always}, +@@ -1314,6 +1315,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2503,6 +2505,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + return riscv_subset_supports (rps, "zaamo"); + case INSN_CLASS_ZABHA: + return riscv_subset_supports (rps, "zabha"); ++ case INSN_CLASS_ZACAS: ++ return riscv_subset_supports (rps, "zacas"); + case INSN_CLASS_ZALRSC: + return riscv_subset_supports (rps, "zalrsc"); + case INSN_CLASS_ZAWRS: +@@ -2738,6 +2742,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, + return "zaamo"; + case INSN_CLASS_ZABHA: + return "zabha"; ++ case INSN_CLASS_ZACAS: ++ return "zacas"; + case INSN_CLASS_ZALRSC: + return "zalrsc"; + case INSN_CLASS_ZAWRS: +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index 4a9bac5c7f0..439a7514cbf 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -23,6 +23,7 @@ All available -march extensions for RISC-V: + zmmul 1.0 + zaamo 1.0 + zabha 1.0 ++ zacas 1.0 + zalrsc 1.0 + zawrs 1.0 + zfbfmin 1.0 +diff --git a/gas/testsuite/gas/riscv/zacas-32.d b/gas/testsuite/gas/riscv/zacas-32.d +new file mode 100644 +index 00000000000..9f7fabb8d00 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zacas-32.d +@@ -0,0 +1,26 @@ ++#as: -march=rv32ia_zacas ++#source: zacas.s ++#objdump: -d ++ ++.*:[ ]+file format .* ++ ++ ++Disassembly of section .text: ++ ++0+000 : ++[ ]+[0-9a-f]+:[ ]+28a5252f[ ]+amocas.w[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5252f[ ]+amocas.w[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5252f[ ]+amocas.w.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5252f[ ]+amocas.w.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5252f[ ]+amocas.w.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5252f[ ]+amocas.w.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5252f[ ]+amocas.w.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5252f[ ]+amocas.w.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5352f[ ]+amocas.d[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5352f[ ]+amocas.d[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5352f[ ]+amocas.d.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5352f[ ]+amocas.d.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5352f[ ]+amocas.d.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5352f[ ]+amocas.d.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5352f[ ]+amocas.d.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5352f[ ]+amocas.d.aqrl[ ]+a0,a0,\(a0\) +diff --git a/gas/testsuite/gas/riscv/zacas-64.d b/gas/testsuite/gas/riscv/zacas-64.d +new file mode 100644 +index 00000000000..3f9113b3b34 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zacas-64.d +@@ -0,0 +1,34 @@ ++#as: -march=rv64ia_zacas -defsym rv64=1 ++#source: zacas.s ++#objdump: -d ++ ++.*:[ ]+file format .* ++ ++ ++Disassembly of section .text: ++ ++0+000 : ++[ ]+[0-9a-f]+:[ ]+28a5252f[ ]+amocas.w[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5252f[ ]+amocas.w[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5252f[ ]+amocas.w.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5252f[ ]+amocas.w.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5252f[ ]+amocas.w.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5252f[ ]+amocas.w.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5252f[ ]+amocas.w.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5252f[ ]+amocas.w.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5352f[ ]+amocas.d[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5352f[ ]+amocas.d[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5352f[ ]+amocas.d.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5352f[ ]+amocas.d.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5352f[ ]+amocas.d.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5352f[ ]+amocas.d.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5352f[ ]+amocas.d.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5352f[ ]+amocas.d.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5452f[ ]+amocas.q[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+28a5452f[ ]+amocas.q[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5452f[ ]+amocas.q.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ca5452f[ ]+amocas.q.aq[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5452f[ ]+amocas.q.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2aa5452f[ ]+amocas.q.rl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5452f[ ]+amocas.q.aqrl[ ]+a0,a0,\(a0\) ++[ ]+[0-9a-f]+:[ ]+2ea5452f[ ]+amocas.q.aqrl[ ]+a0,a0,\(a0\) +diff --git a/gas/testsuite/gas/riscv/zacas-fail-32.d b/gas/testsuite/gas/riscv/zacas-fail-32.d +new file mode 100644 +index 00000000000..f9cee1cdae7 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zacas-fail-32.d +@@ -0,0 +1,3 @@ ++#as: -march=rv32ia_zacas ++#source: zacas-fail.s ++#error_output: zacas-fail-32.l +\ No newline at end of file +diff --git a/gas/testsuite/gas/riscv/zacas-fail-32.l b/gas/testsuite/gas/riscv/zacas-fail-32.l +new file mode 100644 +index 00000000000..ff12bd3253d +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zacas-fail-32.l +@@ -0,0 +1,17 @@ ++.*: Assembler messages: ++.*: Error: illegal operands `amocas.d a1,a0,\(a0\)' ++.*: Error: illegal operands `amocas.d a0,a1,\(a0\)' ++.*: Error: illegal operands `amocas.d.aq a1,a0,\(a0\)' ++.*: Error: illegal operands `amocas.d.aq a0,a1,\(a0\)' ++.*: Error: illegal operands `amocas.d.rl a1,a0,\(a0\)' ++.*: Error: illegal operands `amocas.d.rl a0,a1,\(a0\)' ++.*: Error: illegal operands `amocas.d.aqrl a1,a0,\(a0\)' ++.*: Error: illegal operands `amocas.d.aqrl a0,a1,\(a0\)' ++.*: Error: unrecognized opcode `amocas.q a1,a0,\(a0\)' ++.*: Error: unrecognized opcode `amocas.q a0,a1,\(a0\)' ++.*: Error: unrecognized opcode `amocas.q.aq a1,a0,\(a0\)' ++.*: Error: unrecognized opcode `amocas.q.aq a0,a1,\(a0\)' ++.*: Error: unrecognized opcode `amocas.q.rl a1,a0,\(a0\)' ++.*: Error: unrecognized opcode `amocas.q.rl a0,a1,\(a0\)' ++.*: Error: unrecognized opcode `amocas.q.aqrl a1,a0,\(a0\)' ++.*: Error: unrecognized opcode `amocas.q.aqrl a0,a1,\(a0\)' +diff --git a/gas/testsuite/gas/riscv/zacas-fail-64.d b/gas/testsuite/gas/riscv/zacas-fail-64.d +new file mode 100644 +index 00000000000..d8413e0a457 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zacas-fail-64.d +@@ -0,0 +1,3 @@ ++#as: -march=rv64ia_zacas ++#source: zacas-fail.s ++#error_output: zacas-fail-64.l +\ No newline at end of file +diff --git a/gas/testsuite/gas/riscv/zacas-fail-64.l b/gas/testsuite/gas/riscv/zacas-fail-64.l +new file mode 100644 +index 00000000000..9ac263d6b56 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zacas-fail-64.l +@@ -0,0 +1,9 @@ ++.*: Assembler messages: ++.*: Error: illegal operands `amocas.q a1,a0,\(a0\)' ++.*: Error: illegal operands `amocas.q a0,a1,\(a0\)' ++.*: Error: illegal operands `amocas.q.aq a1,a0,\(a0\)' ++.*: Error: illegal operands `amocas.q.aq a0,a1,\(a0\)' ++.*: Error: illegal operands `amocas.q.rl a1,a0,\(a0\)' ++.*: Error: illegal operands `amocas.q.rl a0,a1,\(a0\)' ++.*: Error: illegal operands `amocas.q.aqrl a1,a0,\(a0\)' ++.*: Error: illegal operands `amocas.q.aqrl a0,a1,\(a0\)' +diff --git a/gas/testsuite/gas/riscv/zacas-fail.s b/gas/testsuite/gas/riscv/zacas-fail.s +new file mode 100644 +index 00000000000..b1b4ddfc198 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zacas-fail.s +@@ -0,0 +1,17 @@ ++ # rd and rs2 must be even ++ amocas.d a1, a0, (a0) ++ amocas.d a0, a1, (a0) ++ amocas.d.aq a1, a0, (a0) ++ amocas.d.aq a0, a1, (a0) ++ amocas.d.rl a1, a0, (a0) ++ amocas.d.rl a0, a1, (a0) ++ amocas.d.aqrl a1, a0, (a0) ++ amocas.d.aqrl a0, a1, (a0) ++ amocas.q a1, a0, (a0) ++ amocas.q a0, a1, (a0) ++ amocas.q.aq a1, a0, (a0) ++ amocas.q.aq a0, a1, (a0) ++ amocas.q.rl a1, a0, (a0) ++ amocas.q.rl a0, a1, (a0) ++ amocas.q.aqrl a1, a0, (a0) ++ amocas.q.aqrl a0, a1, (a0) +diff --git a/gas/testsuite/gas/riscv/zacas.s b/gas/testsuite/gas/riscv/zacas.s +new file mode 100644 +index 00000000000..c374ba149d1 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/zacas.s +@@ -0,0 +1,27 @@ ++target: ++ amocas.w a0, a0, 0(a0) ++ amocas.w a0, a0, (a0) ++ amocas.w.aq a0, a0, 0(a0) ++ amocas.w.aq a0, a0, (a0) ++ amocas.w.rl a0, a0, 0(a0) ++ amocas.w.rl a0, a0, (a0) ++ amocas.w.aqrl a0, a0, 0(a0) ++ amocas.w.aqrl a0, a0, (a0) ++ amocas.d a0, a0, 0(a0) ++ amocas.d a0, a0, (a0) ++ amocas.d.aq a0, a0, 0(a0) ++ amocas.d.aq a0, a0, (a0) ++ amocas.d.rl a0, a0, 0(a0) ++ amocas.d.rl a0, a0, (a0) ++ amocas.d.aqrl a0, a0, 0(a0) ++ amocas.d.aqrl a0, a0, (a0) ++.ifdef rv64 ++ amocas.q a0, a0, 0(a0) ++ amocas.q a0, a0, (a0) ++ amocas.q.aq a0, a0, 0(a0) ++ amocas.q.aq a0, a0, (a0) ++ amocas.q.rl a0, a0, 0(a0) ++ amocas.q.rl a0, a0, (a0) ++ amocas.q.aqrl a0, a0, 0(a0) ++ amocas.q.aqrl a0, a0, (a0) ++.endif +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index b9ea042cc1a..415d1fb8343 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -2352,6 +2352,13 @@ + #define MASK_C_NTL_S1 0xffff + #define MATCH_C_NTL_ALL 0x9016 + #define MASK_C_NTL_ALL 0xffff ++/* Zacas instructions. */ ++#define MATCH_AMOCAS_W 0x2800202f ++#define MASK_AMOCAS_W 0xf800707f ++#define MATCH_AMOCAS_D 0x2800302f ++#define MASK_AMOCAS_D 0xf800707f ++#define MATCH_AMOCAS_Q 0x2800402f ++#define MASK_AMOCAS_Q 0xf800707f + /* Zawrs instructions. */ + #define MATCH_WRS_NTO 0x00d00073 + #define MASK_WRS_NTO 0xffffffff +@@ -3945,6 +3952,10 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) + DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) + DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) + DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) ++/* Zacas instructions. */ ++DECLARE_INSN(amocas_w, MATCH_AMOCAS_W, MASK_AMOCAS_W) ++DECLARE_INSN(amocas_d, MATCH_AMOCAS_D, MASK_AMOCAS_D) ++DECLARE_INSN(amocas_q, MATCH_AMOCAS_Q, MASK_AMOCAS_Q) + /* Zawrs instructions. */ + DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) + DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index c8baa557bb7..92884e4d24d 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -474,6 +474,7 @@ enum riscv_insn_class + INSN_CLASS_ZICBOP, + INSN_CLASS_ZICBOZ, + INSN_CLASS_ZABHA, ++ INSN_CLASS_ZACAS, + INSN_CLASS_H, + INSN_CLASS_XCVMAC, + INSN_CLASS_XCVALU, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index f60525cf089..bfea2921a3d 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -183,6 +183,14 @@ match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn) + return match_opcode (op, insn) && rs1 == rs2; + } + ++static int ++match_rs2_rd_even (const struct riscv_opcode *op, insn_t insn) ++{ ++ int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; ++ int rd = (insn & MASK_RD) >> OP_SH_RD; ++ return ((rs2 & 1) == 0) && ((rd & 1) == 0) && match_opcode (op, insn); ++} ++ + static int + match_rd_nonzero (const struct riscv_opcode *op, insn_t insn) + { +@@ -733,6 +741,24 @@ const struct riscv_opcode riscv_opcodes[] = + {"amomin.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQRL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + {"amominu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQRL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE }, + ++/* Zacas instruction subset. */ ++{"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amocas.d", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE }, ++{"amocas.d", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amocas.q", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE }, ++{"amocas.w.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_AQ, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amocas.d.aq", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQ, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE }, ++{"amocas.d.aq", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQ, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amocas.q.aq", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_AQ, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE }, ++{"amocas.w.rl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_RL, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amocas.d.rl", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_RL, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE }, ++{"amocas.d.rl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_RL, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amocas.q.rl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_RL, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE }, ++{"amocas.w.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_AQRL, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amocas.d.aqrl", 32, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQRL, MASK_AMOCAS_D|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_8_BYTE }, ++{"amocas.d.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQRL, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_AQRL, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE }, ++ + /* Multiply/Divide instruction subset. */ + {"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS }, + {"mul", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, +-- +2.27.0 + diff --git a/RISC-V-Support-ssctr-smctr-extensions-with-frozen-ve.patch b/RISC-V-Support-ssctr-smctr-extensions-with-frozen-ve.patch new file mode 100644 index 0000000000000000000000000000000000000000..982b56aaf1c021f2d822fccfc8b577a13d2c9fbe --- /dev/null +++ b/RISC-V-Support-ssctr-smctr-extensions-with-frozen-ve.patch @@ -0,0 +1,545 @@ +From 838ff2fb505c91367d8bea6850d3c2cfe57de662 Mon Sep 17 00:00:00 2001 +From: Nelson Chu +Date: Tue, 18 Jun 2024 12:48:26 +0800 +Subject: [PATCH] RISC-V: Support ssctr/smctr extensions with frozen version + 1.0. + +https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0.0_rc2 + +The privileged spec v1.10 already removed the sfence.vm instruction, and the +encoding of sfence.vm instruction is overlapped with the sctrclr instruction +of ssctr/smctr. But since the privileged spec v1.10 already removed the +sfence.vm, and we no longer support the privileged spec v1.9.1 for now, we +had to remove the sfence.vm. + +bfd/ + * elfxx-riscv.c (riscv_implicit_subsets): Imply zicsr for ssctr/smctr. + (riscv_supported_std_s_ext): Added ssctr/smctr with version 1.0. + (riscv_multi_subset_supports): Handle INSN_CLASS for ssctr/smctr. + (riscv_multi_subset_supports_ext): Likewise. +gas/ + * config/tc-riscv.c (enum riscv_csr_class, riscv_csr_address): + Added and handle CSR_CLASS_SSCTR and CSR_CLASS_SMCTR. + (riscv_is_priv_insn): Removed SFENCE_VM check. + * testsuite/gas/riscv/attribute-14e.d: Removed since sfence.vm is no + longer supported since privileged spec v1.10. + * testsuite/gas/riscv/attribute-14.s: Likewise. + * testsuite/gas/riscv/csr-version-1p10.d: Updated for ssctr/smctr CSRs. + * testsuite/gas/riscv/csr-version-1p10.l: Likewise. + * testsuite/gas/riscv/csr-version-1p11.d: Likewise. + * testsuite/gas/riscv/csr-version-1p11.l: Likewise. + * testsuite/gas/riscv/csr-version-1p12.d: Likewise. + * testsuite/gas/riscv/csr-version-1p12.l: Likewise. + * testsuite/gas/riscv/csr.s: Likewise. + * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. + * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. + * testsuite/gas/riscv/march-help.l: Updated for ssctr/smctr. + * testsuite/gas/riscv/smctr-ssctr.d: New testcase for sctr instruction. + * testsuite/gas/riscv/smctr-ssctr.s: Likewise. +include/ + * opcode/riscv-opc.h: Added encoding macro for sctrclr, but removed + encoding macro for sfence.vm since encoding conflict. Added CSR + numbers for ssctr/smctr CSRs. + * opcode/riscv.h (enum riscv_insn_class): Added + INSN_CLASS_SMCTR_OR_SSCTR for sctrclr. +opcodes/ + * riscv-opc.c (riscv_opcodes): Added sctrclr, but removed sfence.vm + since encoding conflict. +--- + bfd/elfxx-riscv.c | 9 +++++++++ + gas/config/tc-riscv.c | 9 +++++---- + gas/testsuite/gas/riscv/attribute-14.s | 5 ----- + gas/testsuite/gas/riscv/attribute-14e.d | 8 -------- + gas/testsuite/gas/riscv/csr-dw-regnums.d | 5 +++++ + gas/testsuite/gas/riscv/csr-dw-regnums.s | 8 ++++++++ + gas/testsuite/gas/riscv/csr-version-1p10.d | 10 ++++++++++ + gas/testsuite/gas/riscv/csr-version-1p10.l | 20 ++++++++++++++++++++ + gas/testsuite/gas/riscv/csr-version-1p11.d | 10 ++++++++++ + gas/testsuite/gas/riscv/csr-version-1p11.l | 20 ++++++++++++++++++++ + gas/testsuite/gas/riscv/csr-version-1p12.d | 10 ++++++++++ + gas/testsuite/gas/riscv/csr-version-1p12.l | 20 ++++++++++++++++++++ + gas/testsuite/gas/riscv/csr.s | 7 +++++++ + gas/testsuite/gas/riscv/march-help.l | 2 ++ + gas/testsuite/gas/riscv/smctr-ssctr.d | 11 +++++++++++ + gas/testsuite/gas/riscv/smctr-ssctr.s | 1 + + include/opcode/riscv-opc.h | 20 +++++++++++++++++--- + include/opcode/riscv.h | 1 + + opcodes/riscv-opc.c | 5 +++-- + 19 files changed, 159 insertions(+), 22 deletions(-) + delete mode 100644 gas/testsuite/gas/riscv/attribute-14e.d + create mode 100644 gas/testsuite/gas/riscv/smctr-ssctr.d + create mode 100644 gas/testsuite/gas/riscv/smctr-ssctr.s + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 36a525018e7..0c3e23a59c2 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1221,6 +1221,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"svade", "zicsr", check_implicit_always}, + {"svbare", "zicsr", check_implicit_always}, + {"svadu", "zicsr", check_implicit_always}, ++ {"smctr", "zicsr", check_implicit_always}, ++ {"ssctr", "zicsr", check_implicit_always}, + + {"xsfvcp", "zve32x", check_implicit_always}, + {NULL, NULL, NULL} +@@ -1383,11 +1385,13 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"smctr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ssctr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2619,6 +2623,9 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + case INSN_CLASS_ZCB_AND_ZMMUL: + return (riscv_subset_supports (rps, "zcb") + && riscv_subset_supports (rps, "zmmul")); ++ case INSN_CLASS_SMCTR_OR_SSCTR: ++ return (riscv_subset_supports (rps, "smctr") ++ || riscv_subset_supports (rps, "ssctr")); + case INSN_CLASS_SVINVAL: + return riscv_subset_supports (rps, "svinval"); + case INSN_CLASS_H: +@@ -2879,6 +2886,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, + return _("zcb' and `zbb"); + case INSN_CLASS_ZCB_AND_ZMMUL: + return _("zcb' and `zmmul', or `zcb' and `m"); ++ case INSN_CLASS_SMCTR_OR_SSCTR: ++ return _("smctr' or `ssctr"); + case INSN_CLASS_SVINVAL: + return "svinval"; + case INSN_CLASS_H: +diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c +index 1980c62ea01..3077a33e747 100644 +--- a/gas/config/tc-riscv.c ++++ b/gas/config/tc-riscv.c +@@ -81,6 +81,7 @@ enum riscv_csr_class + CSR_CLASS_SMCNTRPMF_32, /* Smcntrpmf, rv32 only */ + CSR_CLASS_SMSTATEEN, /* Smstateen only */ + CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */ ++ CSR_CLASS_SMCTR, /* Smctr */ + CSR_CLASS_SSAIA, /* Ssaia */ + CSR_CLASS_SSAIA_AND_H, /* Ssaia with H */ + CSR_CLASS_SSAIA_32, /* Ssaia, rv32 only */ +@@ -94,6 +95,7 @@ enum riscv_csr_class + CSR_CLASS_SSTC_AND_H, /* Sstc only (with H) */ + CSR_CLASS_SSTC_32, /* Sstc RV32 only */ + CSR_CLASS_SSTC_AND_H_32, /* Sstc RV32 only (with H) */ ++ CSR_CLASS_SSCTR, /* Ssctr */ + CSR_CLASS_XTHEADVECTOR, /* xtheadvector only */ + }; + +@@ -1072,6 +1074,7 @@ riscv_csr_address (const char *csr_name, + case CSR_CLASS_SMSTATEEN: + extension = "smstateen"; + break; ++ case CSR_CLASS_SMCTR: extension = "smctr"; break; + case CSR_CLASS_SSAIA: + case CSR_CLASS_SSAIA_AND_H: + case CSR_CLASS_SSAIA_32: +@@ -1107,6 +1110,7 @@ riscv_csr_address (const char *csr_name, + || csr_class == CSR_CLASS_SSTC_AND_H_32); + extension = "sstc"; + break; ++ case CSR_CLASS_SSCTR: extension = "ssctr"; break; + case CSR_CLASS_DEBUG: + break; + case CSR_CLASS_XTHEADVECTOR: +@@ -2573,10 +2577,7 @@ riscv_is_priv_insn (insn_t insn) + return (((insn ^ MATCH_SRET) & MASK_SRET) == 0 + || ((insn ^ MATCH_MRET) & MASK_MRET) == 0 + || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0 +- || ((insn ^ MATCH_WFI) & MASK_WFI) == 0 +- /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to +- check it here to keep the compatible. */ +- || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0); ++ || ((insn ^ MATCH_WFI) & MASK_WFI) == 0); + } + + static symbolS *deferred_sym_rootP; +diff --git a/gas/testsuite/gas/riscv/attribute-14.s b/gas/testsuite/gas/riscv/attribute-14.s +index ddda6b996f8..dcca2d8671d 100644 +--- a/gas/testsuite/gas/riscv/attribute-14.s ++++ b/gas/testsuite/gas/riscv/attribute-14.s +@@ -12,8 +12,3 @@ + .ifdef priv_insn_d + sfence.vma + .endif +- +- # Obselete priv instruction. +-.ifdef priv_insn_e +- sfence.vm +-.endif +diff --git a/gas/testsuite/gas/riscv/attribute-14e.d b/gas/testsuite/gas/riscv/attribute-14e.d +deleted file mode 100644 +index 47fdc2e2df9..00000000000 +--- a/gas/testsuite/gas/riscv/attribute-14e.d ++++ /dev/null +@@ -1,8 +0,0 @@ +-#as: -march-attr --defsym priv_insn_e=1 +-#readelf: -A +-#source: attribute-14.s +-Attribute Section: riscv +-File Attributes +- Tag_RISCV_arch: [a-zA-Z0-9_\"].* +- Tag_RISCV_priv_spec: [0-9_\"].* +-#... +diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d +index 2d85996ad5c..a1d1147188d 100644 +--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d ++++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d +@@ -403,6 +403,11 @@ Contents of the .* section: + DW_CFA_offset_extended_sf: r4445 \(stimecmph\) at cfa\+1396 + DW_CFA_offset_extended_sf: r4685 \(vstimecmp\) at cfa\+2356 + DW_CFA_offset_extended_sf: r4701 \(vstimecmph\) at cfa\+2420 ++ DW_CFA_offset_extended_sf: r4430 \(sctrctl\) at cfa\+1336 ++ DW_CFA_offset_extended_sf: r4431 \(sctrstatus\) at cfa\+1340 ++ DW_CFA_offset_extended_sf: r4447 \(sctrdepth\) at cfa\+1404 ++ DW_CFA_offset_extended_sf: r4686 \(vsctrctl\) at cfa\+2360 ++ DW_CFA_offset_extended_sf: r4942 \(mctrctl\) at cfa\+3384 + DW_CFA_offset_extended: r4096 \(ustatus\) at cfa\+0 + DW_CFA_offset_extended_sf: r4100 \(uie\) at cfa\+16 + DW_CFA_offset_extended_sf: r4101 \(utvec\) at cfa\+20 +diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s +index a4cf56dd799..d4be4f14669 100644 +--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s ++++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s +@@ -405,6 +405,14 @@ _start: + .cfi_offset stimecmph, 1396 + .cfi_offset vstimecmp, 2356 + .cfi_offset vstimecmph, 2420 ++ ++ # Ssctr/Smctr extension ++ .cfi_offset sctrctl, 1336 ++ .cfi_offset sctrstatus, 1340 ++ .cfi_offset sctrdepth, 1404 ++ .cfi_offset vsctrctl, 2360 ++ .cfi_offset mctrctl, 3384 ++ + # dropped + .cfi_offset ustatus, 0 + .cfi_offset uie, 16 +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d +index 2ee4ee55ecd..9b6cd27178b 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.d +@@ -781,6 +781,16 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 + [ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph + [ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 ++[ ]+[0-9a-f]+:[ ]+14e02573[ ]+csrr[ ]+a0,sctrctl ++[ ]+[0-9a-f]+:[ ]+14e59073[ ]+csrw[ ]+sctrctl,a1 ++[ ]+[0-9a-f]+:[ ]+14f02573[ ]+csrr[ ]+a0,sctrstatus ++[ ]+[0-9a-f]+:[ ]+14f59073[ ]+csrw[ ]+sctrstatus,a1 ++[ ]+[0-9a-f]+:[ ]+15f02573[ ]+csrr[ ]+a0,sctrdepth ++[ ]+[0-9a-f]+:[ ]+15f59073[ ]+csrw[ ]+sctrdepth,a1 ++[ ]+[0-9a-f]+:[ ]+24e02573[ ]+csrr[ ]+a0,vsctrctl ++[ ]+[0-9a-f]+:[ ]+24e59073[ ]+csrw[ ]+vsctrctl,a1 ++[ ]+[0-9a-f]+:[ ]+34e02573[ ]+csrr[ ]+a0,mctrctl ++[ ]+[0-9a-f]+:[ ]+34e59073[ ]+csrw[ ]+mctrctl,a1 + [ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus + [ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+ustatus,a1 + [ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l +index 63991d5023c..6ba3f350eb6 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.l +@@ -1511,6 +1511,26 @@ + .*Info: macro .* + .*Warning: invalid CSR `vstimecmph', needs `sstc' extension + .*Info: macro .* ++.*Warning: invalid CSR `sctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mctrctl', needs `smctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mctrctl', needs `smctr' extension ++.*Info: macro .* + .*Warning: invalid CSR `fflags', needs `f' extension + .*Info: macro .* + .*Warning: invalid CSR `fflags', needs `f' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d +index 836dedef86a..ebfa9e1ded3 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.d +@@ -781,6 +781,16 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 + [ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph + [ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 ++[ ]+[0-9a-f]+:[ ]+14e02573[ ]+csrr[ ]+a0,sctrctl ++[ ]+[0-9a-f]+:[ ]+14e59073[ ]+csrw[ ]+sctrctl,a1 ++[ ]+[0-9a-f]+:[ ]+14f02573[ ]+csrr[ ]+a0,sctrstatus ++[ ]+[0-9a-f]+:[ ]+14f59073[ ]+csrw[ ]+sctrstatus,a1 ++[ ]+[0-9a-f]+:[ ]+15f02573[ ]+csrr[ ]+a0,sctrdepth ++[ ]+[0-9a-f]+:[ ]+15f59073[ ]+csrw[ ]+sctrdepth,a1 ++[ ]+[0-9a-f]+:[ ]+24e02573[ ]+csrr[ ]+a0,vsctrctl ++[ ]+[0-9a-f]+:[ ]+24e59073[ ]+csrw[ ]+vsctrctl,a1 ++[ ]+[0-9a-f]+:[ ]+34e02573[ ]+csrr[ ]+a0,mctrctl ++[ ]+[0-9a-f]+:[ ]+34e59073[ ]+csrw[ ]+mctrctl,a1 + [ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus + [ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+ustatus,a1 + [ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l +index 6caec9f63a5..f766244ce62 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.l +@@ -1507,6 +1507,26 @@ + .*Info: macro .* + .*Warning: invalid CSR `vstimecmph', needs `sstc' extension + .*Info: macro .* ++.*Warning: invalid CSR `sctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mctrctl', needs `smctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mctrctl', needs `smctr' extension ++.*Info: macro .* + .*Warning: invalid CSR `fflags', needs `f' extension + .*Info: macro .* + .*Warning: invalid CSR `fflags', needs `f' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d +index beeec9a580f..4413969208c 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.d +@@ -781,6 +781,16 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 + [ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph + [ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 ++[ ]+[0-9a-f]+:[ ]+14e02573[ ]+csrr[ ]+a0,sctrctl ++[ ]+[0-9a-f]+:[ ]+14e59073[ ]+csrw[ ]+sctrctl,a1 ++[ ]+[0-9a-f]+:[ ]+14f02573[ ]+csrr[ ]+a0,sctrstatus ++[ ]+[0-9a-f]+:[ ]+14f59073[ ]+csrw[ ]+sctrstatus,a1 ++[ ]+[0-9a-f]+:[ ]+15f02573[ ]+csrr[ ]+a0,sctrdepth ++[ ]+[0-9a-f]+:[ ]+15f59073[ ]+csrw[ ]+sctrdepth,a1 ++[ ]+[0-9a-f]+:[ ]+24e02573[ ]+csrr[ ]+a0,vsctrctl ++[ ]+[0-9a-f]+:[ ]+24e59073[ ]+csrw[ ]+vsctrctl,a1 ++[ ]+[0-9a-f]+:[ ]+34e02573[ ]+csrr[ ]+a0,mctrctl ++[ ]+[0-9a-f]+:[ ]+34e59073[ ]+csrw[ ]+mctrctl,a1 + [ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,0x0 + [ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+0x0,a1 + [ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,0x4 +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l +index b83a0012004..a7bdfddae6d 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.l +@@ -1231,6 +1231,26 @@ + .*Info: macro .* + .*Warning: invalid CSR `vstimecmph', needs `sstc' extension + .*Info: macro .* ++.*Warning: invalid CSR `sctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mctrctl', needs `smctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mctrctl', needs `smctr' extension ++.*Info: macro .* + .*Warning: invalid CSR `ustatus' for the privileged spec `1.12' + .*Info: macro .* + .*Warning: invalid CSR `ustatus' for the privileged spec `1.12' +diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s +index 42bb158547b..97ce2a2ce59 100644 +--- a/gas/testsuite/gas/riscv/csr.s ++++ b/gas/testsuite/gas/riscv/csr.s +@@ -439,6 +439,13 @@ + csr vstimecmp + csr vstimecmph + ++ # Smctr/Ssctr ++ csr sctrctl ++ csr sctrstatus ++ csr sctrdepth ++ csr vsctrctl ++ csr mctrctl ++ + # Supported in previous priv spec, but dropped now + + csr ustatus # 0x0 in 1.10, dropped in 1.12 +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index dd82752cd30..68277a000a4 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -96,10 +96,12 @@ All available -march extensions for RISC-V: + zcmp 1.0 + smaia 1.0 + smcntrpmf 1.0 ++ smctr 1.0 + smepmp 1.0 + smstateen 1.0 + ssaia 1.0 + sscofpmf 1.0 ++ ssctr 1.0 + ssstateen 1.0 + sstc 1.0 + svadu 1.0 +diff --git a/gas/testsuite/gas/riscv/smctr-ssctr.d b/gas/testsuite/gas/riscv/smctr-ssctr.d +new file mode 100644 +index 00000000000..ead1f2337b8 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/smctr-ssctr.d +@@ -0,0 +1,11 @@ ++#as: -march=rv32i_smctr_ssctr ++#source: smctr-ssctr.s ++#objdump: -d ++ ++.*:[ ]+file format .* ++ ++ ++Disassembly of section .text: ++ ++0+000 <.text>: ++[ ]+0:[ ]+10400073[ ]+sctrclr +diff --git a/gas/testsuite/gas/riscv/smctr-ssctr.s b/gas/testsuite/gas/riscv/smctr-ssctr.s +new file mode 100644 +index 00000000000..08cfab4ac8d +--- /dev/null ++++ b/gas/testsuite/gas/riscv/smctr-ssctr.s +@@ -0,0 +1 @@ ++ sctrclr +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index c0b17b7031e..3add95398a8 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -285,8 +285,6 @@ + #define MASK_MRET 0xffffffff + #define MATCH_DRET 0x7b200073 + #define MASK_DRET 0xffffffff +-#define MATCH_SFENCE_VM 0x10400073 +-#define MASK_SFENCE_VM 0xfff07fff + #define MATCH_SFENCE_VMA 0x12000073 + #define MASK_SFENCE_VMA 0xfe007fff + #define MATCH_WFI 0x10500073 +@@ -2271,6 +2269,9 @@ + #define MASK_C_NOT 0xfc7f + #define MATCH_C_MUL 0x9c41 + #define MASK_C_MUL 0xfc63 ++/* Smctr/Ssctr instruction. */ ++#define MATCH_SCTRCLR 0x10400073 ++#define MASK_SCTRCLR 0xffffffff + /* Svinval instruction. */ + #define MATCH_SINVAL_VMA 0x16000073 + #define MASK_SINVAL_VMA 0xfe007fff +@@ -3489,6 +3490,12 @@ + #define CSR_STIMECMPH 0x15d + #define CSR_VSTIMECMP 0x24d + #define CSR_VSTIMECMPH 0x25d ++/* Smctr/Ssctr CSR addresses. */ ++#define CSR_SCTRCTL 0x14e ++#define CSR_SCTRSTATUS 0x14f ++#define CSR_SCTRDEPTH 0x15f ++#define CSR_VSCTRCTL 0x24e ++#define CSR_MCTRCTL 0x34e + /* Unprivileged Floating-Point CSR addresses. */ + #define CSR_FFLAGS 0x1 + #define CSR_FRM 0x2 +@@ -3651,7 +3658,6 @@ DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) + DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) + DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) + DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +-DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) + DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) + DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) + DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +@@ -3988,6 +3994,8 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) + DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) + DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) + DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) ++/* Smctr/Ssctr instruction. */ ++DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR) + /* Vendor-specific (T-Head) XTheadBa instructions. */ + DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) + /* Vendor-specific (T-Head) XTheadBb instructions. */ +@@ -4507,6 +4515,12 @@ DECLARE_CSR(stimecmp, CSR_STIMECMP, CSR_CLASS_SSTC, PRIV_SPEC_CLASS_NONE, PRIV_S + DECLARE_CSR(stimecmph, CSR_STIMECMPH, CSR_CLASS_SSTC_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vstimecmp, CSR_VSTIMECMP, CSR_CLASS_SSTC_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH, CSR_CLASS_SSTC_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++/* Smctr/Ssctr CSRs. */ ++DECLARE_CSR(sctrctl, CSR_SCTRCTL, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(sctrstatus, CSR_SCTRSTATUS, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(sctrdepth, CSR_SCTRDEPTH, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(vsctrctl, CSR_VSCTRCTL, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(mctrctl, CSR_MCTRCTL, CSR_CLASS_SMCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + /* Dropped CSRs. */ + DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) + DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index 1e5adbf5abf..c1a0f9982eb 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -467,6 +467,7 @@ enum riscv_insn_class + INSN_CLASS_ZCB_AND_ZBA, + INSN_CLASS_ZCB_AND_ZBB, + INSN_CLASS_ZCB_AND_ZMMUL, ++ INSN_CLASS_SMCTR_OR_SSCTR, + INSN_CLASS_SVINVAL, + INSN_CLASS_ZICBOM, + INSN_CLASS_ZICBOP, +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index a61ebfc74e5..4d9deaaca64 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -2105,13 +2105,14 @@ const struct riscv_opcode riscv_opcodes[] = + {"hret", 0, INSN_CLASS_I, "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, + {"mret", 0, INSN_CLASS_I, "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, + {"dret", 0, INSN_CLASS_I, "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, +-{"sfence.vm", 0, INSN_CLASS_I, "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, +-{"sfence.vm", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, + {"sfence.vma", 0, INSN_CLASS_I, "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS }, + {"sfence.vma", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS2, match_opcode, INSN_ALIAS }, + {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, + {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, + ++/* Smctr/Ssctr instruction. */ ++{"sctrclr", 0, INSN_CLASS_SMCTR_OR_SSCTR, "", MATCH_SCTRCLR, MASK_SCTRCLR, match_opcode, 0 }, ++ + /* Svinval instructions. */ + {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, + {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 }, +-- +2.27.0 + diff --git a/binutils-2.42.spec b/binutils-2.42.spec index 8fae807f51891f1e1e823a4d288dbed9aa411c05..ee8aec7fb1d761dbf3c65ff34d6d6a52fa42a6a3 100644 --- a/binutils-2.42.spec +++ b/binutils-2.42.spec @@ -15,7 +15,7 @@ Summary: A GNU collection of binary utilities Name: %{?_scl_prefix}binutils%{binutils_ver} Version: 2.42 -Release: 3 +Release: 4 License: GPLv3+ URL: https://sourceware.org/binutils ExcludeArch: loongarch64 @@ -182,9 +182,28 @@ Source2: binutils-2.19.50.0.1-output-format.sed # 25f05199bb7e35820c23e802424484accb7936b1 # 3ba06284d2cada7a4798f7849da113661aff07dd # 8a3ffa71945816b941d3dea9ebc7013d5be7a1a4 -Patch3001: binutils-2.44-backport-RISC-V-Add-platform-property-capability-extensions.patch -Patch3002: binutils-2.44-backport-RISC-V-Add-support-for-Zimop-extension.patch -Patch3003: binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch + +# Purpose: Add support for more RVA32 extensions and several other important extensions. +# Lifetime: Backport from branch binutils-2_42-branch of +# https://code.risc-verse.isrc.ac.cn/risc-verse/toolchain/binutils-gdb +Patch3001: RISC-V-Removed-privileged-spec-1.9.1-support-in-asse.patch +Patch3002: RISC-V-Add-support-for-Zfbfmin-extension.patch +Patch3003: RISC-V-Add-support-for-Zvfbfmin-extension.patch +Patch3004: RISC-V-Add-support-for-Zvfbfwma-extension.patch +Patch3005: RISC-V-1-Support-Zabha-extension.patch +Patch3006: RISC-V-2-Support-Zabha-extension.patch +Patch3007: RISC-V-Add-platform-property-capability-extensions.patch +Patch3008: RISC-V-Support-ssctr-smctr-extensions-with-frozen-ve.patch +Patch3009: RISC-V-Support-S-sm-csrind-extension-csrs.patch +Patch3010: RISC-V-Fixed-typo-from-smscrind-to-smcsrind-in-riscv.patch +Patch3011: RISC-V-Support-Smcdeleg-and-Ssccfg-extensions.patch +Patch3012: RISC-V-Add-Smrnmi-extension-csrs.patch +Patch3013: RISC-V-Support-B-Zaamo-and-Zalrsc-extensions.patch +Patch3014: RISC-V-Support-Zacas-extension.patch +Patch3015: RISC-V-Add-support-for-Zimop-extension.patch +Patch3016: RISC-V-Support-CFI-Zicfiss-and-Zicfilp-instructions-.patch +Patch3017: RISC-V-Add-Zabha-extension-CAS-instructions.patch +Patch3018: binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch # Part 5000 - # Purpose: Use /lib64 and /usr/lib64 instead of /lib and /usr/lib in the @@ -1280,6 +1299,9 @@ exit 0 #---------------------------------------------------------------------------- %changelog +* Tue Sep 02 2025 dangyuan - 2.42-4 +- Add support for more RVA32 extensions and several other important extensions. + * Wed Jul 02 2025 zhangenpei - 2.42-3 - Backport RVA23U64 mandatory extensions. diff --git a/binutils-2.44-backport-RISC-V-Add-platform-property-capability-extensions.patch b/binutils-2.44-backport-RISC-V-Add-platform-property-capability-extensions.patch deleted file mode 100644 index 4976c6e8562a5db15305c9489d4f27690c3e2799..0000000000000000000000000000000000000000 --- a/binutils-2.44-backport-RISC-V-Add-platform-property-capability-extensions.patch +++ /dev/null @@ -1,83 +0,0 @@ -diff -rup binutils.orig/bfd/elfxx-riscv.c binutils-2.42/bfd/elfxx-riscv.c ---- binutils.orig/bfd/elfxx-riscv.c 2025-07-01 10:16:05.889931463 +0800 -+++ binutils-2.42/bfd/elfxx-riscv.c 2025-07-01 10:16:55.803095052 +0800 -@@ -1113,6 +1113,12 @@ static struct riscv_implicit_subset risc - {"g", "zicsr", check_implicit_always}, - {"g", "zifencei", check_implicit_always}, - {"m", "zmmul", check_implicit_always}, -+ {"shcounterenw", "h", check_implicit_always}, -+ {"shgatpa", "h", check_implicit_always}, -+ {"shtvala", "h", check_implicit_always}, -+ {"shvsatpa", "h", check_implicit_always}, -+ {"shvstvala", "h", check_implicit_always}, -+ {"shvstvecd", "h", check_implicit_always}, - {"h", "zicsr", check_implicit_always}, - {"q", "d", check_implicit_always}, - {"v", "d", check_implicit_always}, -@@ -1199,9 +1205,16 @@ static struct riscv_implicit_subset risc - {"smepmp", "zicsr", check_implicit_always}, - {"ssaia", "zicsr", check_implicit_always}, - {"sscofpmf", "zicsr", check_implicit_always}, -+ {"sscounterenw", "zicsr", check_implicit_always}, - {"ssstateen", "zicsr", check_implicit_always}, - {"sstc", "zicsr", check_implicit_always}, -+ {"sstvala", "zicsr", check_implicit_always}, -+ {"sstvecd", "zicsr", check_implicit_always}, -+ {"ssu64xl", "zicsr", check_implicit_always}, -+ -+ {"svade", "zicsr", check_implicit_always}, - {"svadu", "zicsr", check_implicit_always}, -+ {"svbare", "zicsr", check_implicit_always}, - - {"xsfvcp", "zve32x", check_implicit_always}, - {NULL, NULL, NULL} -@@ -1261,6 +1274,11 @@ static struct riscv_supported_ext riscv_ - - static struct riscv_supported_ext riscv_supported_std_z_ext[] = - { -+ {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -@@ -1274,6 +1292,8 @@ static struct riscv_supported_ext riscv_ - {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, - {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, - {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -@@ -1345,15 +1365,28 @@ static struct riscv_supported_ext riscv_ - - static struct riscv_supported_ext riscv_supported_std_s_ext[] = - { -+ {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch b/binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch index 5a405d2af8c23b5846711b837e1979ecc55591ea..4a73ae06214ce3724ea23fd463e2e7816c70f633 100644 --- a/binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch +++ b/binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch @@ -1,56 +1,55 @@ -diff -rup binutils.orig/bfd/elfxx-riscv.c binutils-2.42/bfd/elfxx-riscv.c ---- binutils.orig/bfd/elfxx-riscv.c 2025-07-01 10:28:57.536983487 +0800 -+++ binutils-2.42/bfd/elfxx-riscv.c 2025-07-01 10:29:16.665474728 +0800 -@@ -1113,6 +1113,8 @@ static struct riscv_implicit_subset risc - {"g", "zicsr", check_implicit_always}, - {"g", "zifencei", check_implicit_always}, - {"m", "zmmul", check_implicit_always}, -+ {"zcmop", "zca", check_implicit_always}, -+ - {"shcounterenw", "h", check_implicit_always}, - {"shgatpa", "h", check_implicit_always}, - {"shtvala", "h", check_implicit_always}, -@@ -1361,6 +1363,7 @@ static struct riscv_supported_ext riscv_ +diff -rup binutils-2.42.orig/bfd/elfxx-riscv.c binutils-2.42/bfd/elfxx-riscv.c +--- binutils-2.42.orig/bfd/elfxx-riscv.c 2025-09-02 09:59:47.738603826 +0800 ++++ binutils-2.42/bfd/elfxx-riscv.c 2025-09-02 10:36:58.215760046 +0800 +@@ -1204,6 +1204,7 @@ static struct riscv_implicit_subset risc + {"zcf", "zca", check_implicit_always}, + {"zcd", "zca", check_implicit_always}, + {"zcb", "zca", check_implicit_always}, ++ {"zcmop", "zca", check_implicit_always}, + {"smaia", "ssaia", check_implicit_always}, + {"smcdeleg", "ssccfg", check_implicit_always}, + {"ssccfg", "sscsrind", check_implicit_always}, +@@ -1393,6 +1394,7 @@ static struct riscv_supported_ext riscv_ {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, -+ {"zcmop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zcmop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; -@@ -2604,6 +2607,8 @@ riscv_multi_subset_supports (riscv_parse +@@ -2665,6 +2667,8 @@ riscv_multi_subset_supports (riscv_parse case INSN_CLASS_ZCB_AND_ZMMUL: return (riscv_subset_supports (rps, "zcb") && riscv_subset_supports (rps, "zmmul")); + case INSN_CLASS_ZCMOP: + return riscv_subset_supports (rps, "zcmop"); - case INSN_CLASS_SVINVAL: - return riscv_subset_supports (rps, "svinval"); - case INSN_CLASS_H: -@@ -2858,6 +2863,8 @@ riscv_multi_subset_supports_ext (riscv_p + case INSN_CLASS_SMCTR_OR_SSCTR: + return (riscv_subset_supports (rps, "smctr") + || riscv_subset_supports (rps, "ssctr")); +@@ -2947,6 +2951,8 @@ riscv_multi_subset_supports_ext (riscv_p return _("zcb' and `zbb"); case INSN_CLASS_ZCB_AND_ZMMUL: return _("zcb' and `zmmul', or `zcb' and `m"); + case INSN_CLASS_ZCMOP: + return "zcmop"; + case INSN_CLASS_SMCTR_OR_SSCTR: + return _("smctr' or `ssctr"); case INSN_CLASS_SVINVAL: - return "svinval"; - case INSN_CLASS_H: -diff -rup binutils.orig/include/opcode/riscv.h binutils-2.42/include/opcode/riscv.h ---- binutils.orig/include/opcode/riscv.h 2025-07-01 10:29:00.552376203 +0800 -+++ binutils-2.42/include/opcode/riscv.h 2025-07-01 10:29:16.669475249 +0800 -@@ -465,6 +465,7 @@ enum riscv_insn_class +diff -rup binutils-2.42.orig/include/opcode/riscv.h binutils-2.42/include/opcode/riscv.h +--- binutils-2.42.orig/include/opcode/riscv.h 2025-09-02 09:59:51.233833762 +0800 ++++ binutils-2.42/include/opcode/riscv.h 2025-09-02 10:26:58.858146507 +0800 +@@ -472,6 +472,7 @@ enum riscv_insn_class INSN_CLASS_ZCB_AND_ZBA, INSN_CLASS_ZCB_AND_ZBB, INSN_CLASS_ZCB_AND_ZMMUL, + INSN_CLASS_ZCMOP, + INSN_CLASS_SMCTR_OR_SSCTR, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, - INSN_CLASS_ZICBOP, -diff -rup binutils.orig/include/opcode/riscv-opc.h binutils-2.42/include/opcode/riscv-opc.h ---- binutils.orig/include/opcode/riscv-opc.h 2025-07-01 10:29:00.551376073 +0800 -+++ binutils-2.42/include/opcode/riscv-opc.h 2025-07-01 10:29:16.668475119 +0800 -@@ -2235,6 +2235,23 @@ +diff -rup binutils-2.42.orig/include/opcode/riscv-opc.h binutils-2.42/include/opcode/riscv-opc.h +--- binutils-2.42.orig/include/opcode/riscv-opc.h 2025-09-02 09:59:51.233833762 +0800 ++++ binutils-2.42/include/opcode/riscv-opc.h 2025-09-02 10:26:25.419942256 +0800 +@@ -2273,6 +2273,23 @@ #define MASK_C_NOT 0xfc7f #define MATCH_C_MUL 0x9c41 #define MASK_C_MUL 0xfc63 @@ -71,10 +70,10 @@ diff -rup binutils.orig/include/opcode/riscv-opc.h binutils-2.42/include/opcode/ +#define MASK_C_MOP_13 0xffff +#define MATCH_C_MOP_15 0x6781 +#define MASK_C_MOP_15 0xffff - /* Svinval instruction. */ - #define MATCH_SINVAL_VMA 0x16000073 - #define MASK_SINVAL_VMA 0xfe007fff -@@ -4038,6 +4055,15 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_ + /* Smctr/Ssctr instruction. */ + #define MATCH_SCTRCLR 0x10400073 + #define MASK_SCTRCLR 0xffffffff +@@ -4177,6 +4194,15 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_ DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) @@ -87,13 +86,13 @@ diff -rup binutils.orig/include/opcode/riscv-opc.h binutils-2.42/include/opcode/ +DECLARE_INSN(c_mop_11, MATCH_C_MOP_11, MASK_C_MOP_11) +DECLARE_INSN(c_mop_13, MATCH_C_MOP_13, MASK_C_MOP_13) +DECLARE_INSN(c_mop_15, MATCH_C_MOP_15, MASK_C_MOP_15) + /* Smctr/Ssctr instruction. */ + DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR) /* Vendor-specific (T-Head) XTheadBa instructions. */ - DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) - /* Vendor-specific (T-Head) XTheadBb instructions. */ -diff -rup binutils.orig/opcodes/riscv-opc.c binutils-2.42/opcodes/riscv-opc.c ---- binutils.orig/opcodes/riscv-opc.c 2025-07-01 10:29:02.563638145 +0800 -+++ binutils-2.42/opcodes/riscv-opc.c 2025-07-01 10:29:16.669475249 +0800 -@@ -2035,6 +2035,16 @@ const struct riscv_opcode riscv_opcodes[ +diff -rup binutils-2.42.orig/opcodes/riscv-opc.c binutils-2.42/opcodes/riscv-opc.c +--- binutils-2.42.orig/opcodes/riscv-opc.c 2025-09-02 09:59:53.407976789 +0800 ++++ binutils-2.42/opcodes/riscv-opc.c 2025-09-02 10:28:21.675605805 +0800 +@@ -2201,6 +2201,16 @@ const struct riscv_opcode riscv_opcodes[ {"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 }, {"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },