From 6f9877cbbcea6a3edcf6ef9380bc154f66e66222 Mon Sep 17 00:00:00 2001 From: jchzhou Date: Sat, 20 Sep 2025 23:44:19 +0800 Subject: [PATCH] add some backported RISC-V patches for RVA23 profiles and extensions --- binutils-2.42.spec | 14 +- ...upport-B-Zaamo-and-Zalrsc-extensions.patch | 644 ++++ ...dd-Privileged-Architecture-1.13-CSRs.patch | 2850 +++++++++++++++++ ...SC-V-Add-Profiles-RVA-B23S64-support.patch | 89 + ...nted-hypervisor-extension-sha-suppor.patch | 315 ++ ...dd-support-for-RISC-V-Profiles-20-22.patch | 282 ++ ...V-Add-support-for-RISC-V-Profiles-23.patch | 81 + ...-V-Ssnpm-smnpm-and-smmpm-imply-zicsr.patch | 42 + ...upport-pointer-masking-extension-1.0.patch | 115 + ...ISC-V-Update-Profiles-string-in-RV23.patch | 73 + 10 files changed, 4504 insertions(+), 1 deletion(-) create mode 100644 binutils-2.43-backport-RISC-V-Support-B-Zaamo-and-Zalrsc-extensions.patch create mode 100644 binutils-2.45-backport-RISC-V-Add-Privileged-Architecture-1.13-CSRs.patch create mode 100644 binutils-2.45-backport-RISC-V-Add-Profiles-RVA-B23S64-support.patch create mode 100644 binutils-2.45-backport-RISC-V-Add-augmented-hypervisor-extension-sha-suppor.patch create mode 100644 binutils-2.45-backport-RISC-V-Add-support-for-RISC-V-Profiles-20-22.patch create mode 100644 binutils-2.45-backport-RISC-V-Add-support-for-RISC-V-Profiles-23.patch create mode 100644 binutils-2.45-backport-RISC-V-Ssnpm-smnpm-and-smmpm-imply-zicsr.patch create mode 100644 binutils-2.45-backport-RISC-V-Support-pointer-masking-extension-1.0.patch create mode 100644 binutils-2.45-backport-RISC-V-Update-Profiles-string-in-RV23.patch diff --git a/binutils-2.42.spec b/binutils-2.42.spec index 8fae807..1089087 100644 --- a/binutils-2.42.spec +++ b/binutils-2.42.spec @@ -15,7 +15,7 @@ Summary: A GNU collection of binary utilities Name: %{?_scl_prefix}binutils%{binutils_ver} Version: 2.42 -Release: 3 +Release: 4 License: GPLv3+ URL: https://sourceware.org/binutils ExcludeArch: loongarch64 @@ -185,6 +185,15 @@ Source2: binutils-2.19.50.0.1-output-format.sed Patch3001: binutils-2.44-backport-RISC-V-Add-platform-property-capability-extensions.patch Patch3002: binutils-2.44-backport-RISC-V-Add-support-for-Zimop-extension.patch Patch3003: binutils-2.44-backport-RISC-V-Add-support-for-Zcmop-extension.patch +Patch3004: binutils-2.43-backport-RISC-V-Support-B-Zaamo-and-Zalrsc-extensions.patch +Patch3005: binutils-2.45-backport-RISC-V-Support-pointer-masking-extension-1.0.patch +Patch3006: binutils-2.45-backport-RISC-V-Ssnpm-smnpm-and-smmpm-imply-zicsr.patch +Patch3007: binutils-2.45-backport-RISC-V-Add-Privileged-Architecture-1.13-CSRs.patch +Patch3008: binutils-2.45-backport-RISC-V-Add-augmented-hypervisor-extension-sha-suppor.patch +Patch3009: binutils-2.45-backport-RISC-V-Add-support-for-RISC-V-Profiles-20-22.patch +Patch3010: binutils-2.45-backport-RISC-V-Add-support-for-RISC-V-Profiles-23.patch +Patch3011: binutils-2.45-backport-RISC-V-Update-Profiles-string-in-RV23.patch +Patch3012: binutils-2.45-backport-RISC-V-Add-Profiles-RVA-B23S64-support.patch # Part 5000 - # Purpose: Use /lib64 and /usr/lib64 instead of /lib and /usr/lib in the @@ -1280,6 +1289,9 @@ exit 0 #---------------------------------------------------------------------------- %changelog +* Fri Sep 19 2025 jchzhou - 2.42-4 +- Add some backported RISC-V patches for RVA23 profiles and extensions + * Wed Jul 02 2025 zhangenpei - 2.42-3 - Backport RVA23U64 mandatory extensions. diff --git a/binutils-2.43-backport-RISC-V-Support-B-Zaamo-and-Zalrsc-extensions.patch b/binutils-2.43-backport-RISC-V-Support-B-Zaamo-and-Zalrsc-extensions.patch new file mode 100644 index 0000000..036cd3d --- /dev/null +++ b/binutils-2.43-backport-RISC-V-Support-B-Zaamo-and-Zalrsc-extensions.patch @@ -0,0 +1,644 @@ +From 2de7f5a504ae08dd8956ace743d669d3d29cd9f4 Mon Sep 17 00:00:00 2001 +From: Nelson Chu +Date: Mon, 5 Feb 2024 09:39:37 +0800 +Subject: [PATCH 1/9] RISC-V: Support B, Zaamo and Zalrsc extensions. + +* https://github.com/riscv/riscv-b/tags +Added standard B extension back, which implies Zba, Zbb and Zbs extensions. + +* https://github.com/riscv/riscv-zaamo-zalrsc/tags +Splited standard A extension into two new extensions, Zaamo and Zalrsc. +The A extension implies Zaamo and Zalrsc extensions. + +Not sure if we need to do the similar check as i and zicsr/zifencei. + +Passed riscv[32|64]-[elf/linux] binutils testcases. + +bfd/ + * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules + for A and B extensions. The A implies Zaamo and Zalrsc, the + B implies Zba, Zbb and Zbs. + (riscv_supported_std_ext): Supported B extension with v1.0. + (riscv_supported_std_z_ext): Supported Zaamo and Zalrsc with v1.0. + (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Updated. +include/ + * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_A, Added + INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC. +opcodes/ + * riscv-opc.c (riscv_opcodes): Splited standard A extension into two + new extensions, Zaamo and Zalrsc. +gas/ + * testsuite/gas/riscv/march-imply-a.d: New testcase. + * testsuite/gas/riscv/march-imply-b.d: New testcase. + * testsuite/gas/riscv/attribute-01.d: Updated. + * testsuite/gas/riscv/attribute-02.d: Updated. + * testsuite/gas/riscv/attribute-03.d: Updated. + * testsuite/gas/riscv/attribute-04.d: Updated. + * testsuite/gas/riscv/attribute-05.d: Updated. + * testsuite/gas/riscv/attribute-10.d: Updated. + * testsuite/gas/riscv/mapping-symbols.d: Updated. + * testsuite/gas/riscv/march-imply-g.d: Updated. + * testsuite/gas/riscv/march-imply-unsupported.d: Updated. + * testsuite/gas/riscv/march-ok-reorder.d: Updated. +ld/ + * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated. + * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Updated. + * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Updated. + * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Updated. + +(backported from commit c144f638337) +--- + bfd/elfxx-riscv.c | 20 +- + gas/testsuite/gas/riscv/attribute-01.d | 2 +- + gas/testsuite/gas/riscv/attribute-02.d | 2 +- + gas/testsuite/gas/riscv/attribute-03.d | 2 +- + gas/testsuite/gas/riscv/attribute-04.d | 2 +- + gas/testsuite/gas/riscv/attribute-05.d | 2 +- + gas/testsuite/gas/riscv/attribute-10.d | 2 +- + gas/testsuite/gas/riscv/mapping-symbols.d | 2 +- + gas/testsuite/gas/riscv/march-help.l | 123 ++++++++++++ + gas/testsuite/gas/riscv/march-imply-a.d | 6 + + gas/testsuite/gas/riscv/march-imply-b.d | 6 + + gas/testsuite/gas/riscv/march-imply-g.d | 2 +- + .../gas/riscv/march-imply-unsupported.d | 2 +- + gas/testsuite/gas/riscv/march-ok-reorder.d | 2 +- + include/opcode/riscv.h | 3 +- + .../ld-riscv-elf/attr-merge-arch-01.d | 2 +- + .../ld-riscv-elf/attr-merge-arch-02.d | 2 +- + .../ld-riscv-elf/attr-merge-arch-03.d | 2 +- + .../ld-riscv-elf/attr-merge-user-ext-01.d | 2 +- + opcodes/riscv-opc.c | 176 +++++++++--------- + 20 files changed, 255 insertions(+), 107 deletions(-) + create mode 100644 gas/testsuite/gas/riscv/march-help.l + create mode 100644 gas/testsuite/gas/riscv/march-imply-a.d + create mode 100644 gas/testsuite/gas/riscv/march-imply-b.d + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index a36b889dd25..3336de7f168 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1217,6 +1217,11 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"svade", "zicsr", check_implicit_always}, + {"svadu", "zicsr", check_implicit_always}, + {"svbare", "zicsr", check_implicit_always}, ++ {"b", "zba", check_implicit_always}, ++ {"b", "zbb", check_implicit_always}, ++ {"b", "zbs", check_implicit_always}, ++ {"a", "zaamo", check_implicit_always}, ++ {"a", "zalrsc", check_implicit_always}, + + {"xsfvcp", "zve32x", check_implicit_always}, + {NULL, NULL, NULL} +@@ -1269,6 +1274,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] = + {"c", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, + {"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, + {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 }, ++ {"b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"v", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"h", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {NULL, 0, 0, 0, 0} +@@ -1297,6 +1303,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +@@ -2474,8 +2482,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, + return riscv_subset_supports (rps, "m"); + case INSN_CLASS_ZMMUL: + return riscv_subset_supports (rps, "zmmul"); +- case INSN_CLASS_A: +- return riscv_subset_supports (rps, "a"); ++ case INSN_CLASS_ZAAMO: ++ return riscv_subset_supports (rps, "zaamo"); ++ case INSN_CLASS_ZALRSC: ++ return riscv_subset_supports (rps, "zalrsc"); + case INSN_CLASS_ZAWRS: + return riscv_subset_supports (rps, "zawrs"); + case INSN_CLASS_F: +@@ -2700,8 +2710,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, + return "m"; + case INSN_CLASS_ZMMUL: + return _ ("m' or `zmmul"); +- case INSN_CLASS_A: +- return "a"; ++ case INSN_CLASS_ZAAMO: ++ return "zaamo"; ++ case INSN_CLASS_ZALRSC: ++ return "zalrsc"; + case INSN_CLASS_ZAWRS: + return "zawrs"; + case INSN_CLASS_F: +diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d +index 612305765ab..5615d590866 100644 +--- a/gas/testsuite/gas/riscv/attribute-01.d ++++ b/gas/testsuite/gas/riscv/attribute-01.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d +index 324fd9f2171..134cc41b825 100644 +--- a/gas/testsuite/gas/riscv/attribute-02.d ++++ b/gas/testsuite/gas/riscv/attribute-02.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_xargle2p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0_xargle2p0" +diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d +index 6e1c2fbc592..70e07e3b55c 100644 +--- a/gas/testsuite/gas/riscv/attribute-03.d ++++ b/gas/testsuite/gas/riscv/attribute-03.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_xargle2p0_xfoo3p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0_xargle2p0_xfoo3p0" +diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d +index f64494a798d..21575b4a632 100644 +--- a/gas/testsuite/gas/riscv/attribute-04.d ++++ b/gas/testsuite/gas/riscv/attribute-04.d +@@ -3,4 +3,4 @@ + #source: attribute-04.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/attribute-05.d b/gas/testsuite/gas/riscv/attribute-05.d +index 9507b43976d..4a2d6ca8c9e 100644 +--- a/gas/testsuite/gas/riscv/attribute-05.d ++++ b/gas/testsuite/gas/riscv/attribute-05.d +@@ -4,7 +4,7 @@ + Attribute Section: riscv + File Attributes + Tag_RISCV_stack_align: 16-bytes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" + Tag_RISCV_unaligned_access: Unaligned access + Tag_RISCV_priv_spec: 1 + Tag_RISCV_priv_spec_minor: 9 +diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d +index f46692275f1..04c322ab1dd 100644 +--- a/gas/testsuite/gas/riscv/attribute-10.d ++++ b/gas/testsuite/gas/riscv/attribute-10.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d b/gas/testsuite/gas/riscv/mapping-symbols.d +index 40df3409736..6af825d8ad3 100644 +--- a/gas/testsuite/gas/riscv/mapping-symbols.d ++++ b/gas/testsuite/gas/riscv/mapping-symbols.d +@@ -37,7 +37,7 @@ SYMBOL TABLE: + 0+04 l .text.last.section 0+00 \$d + 0+00 l d .text.section.padding 0+00 .text.section.padding + 0+00 l .text.section.padding 0+00 \$xrv32i2p1_c2p0 +-0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0 ++0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0_zaamo1p0_zalrsc1p0 + 0+06 l .text.section.padding 0+00 \$d + 0+00 l d .text.relax.align 0+00 .text.relax.align + 0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0 +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +new file mode 100644 +index 00000000000..c5754837e05 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -0,0 +1,123 @@ ++All available -march extensions for RISC-V: ++ e 1.9 ++ i 2.1, 2.0 ++ m 2.0 ++ a 2.1, 2.0 ++ f 2.2, 2.0 ++ d 2.2, 2.0 ++ q 2.2, 2.0 ++ c 2.0 ++ b 1.0 ++ v 1.0 ++ h 1.0 ++ zicbom 1.0 ++ zicbop 1.0 ++ zicboz 1.0 ++ zicond 1.0 ++ zicntr 2.0 ++ zicsr 2.0 ++ zifencei 2.0 ++ zihintntl 1.0 ++ zihintpause 2.0 ++ zihpm 2.0 ++ zmmul 1.0 ++ zaamo 1.0 ++ zabha 1.0 ++ zalrsc 1.0 ++ zawrs 1.0 ++ zfa 1.0 ++ zfh 1.0 ++ zfhmin 1.0 ++ zfinx 1.0 ++ zdinx 1.0 ++ zqinx 1.0 ++ zhinx 1.0 ++ zhinxmin 1.0 ++ zbb 1.0 ++ zba 1.0 ++ zbc 1.0 ++ zbs 1.0 ++ zbkb 1.0 ++ zbkc 1.0 ++ zbkx 1.0 ++ zk 1.0 ++ zkn 1.0 ++ zknd 1.0 ++ zkne 1.0 ++ zknh 1.0 ++ zkr 1.0 ++ zks 1.0 ++ zksed 1.0 ++ zksh 1.0 ++ zkt 1.0 ++ zve32x 1.0 ++ zve32f 1.0 ++ zve64x 1.0 ++ zve64f 1.0 ++ zve64d 1.0 ++ zvbb 1.0 ++ zvbc 1.0 ++ zvfh 1.0 ++ zvfhmin 1.0 ++ zvkb 1.0 ++ zvkg 1.0 ++ zvkn 1.0 ++ zvkng 1.0 ++ zvknc 1.0 ++ zvkned 1.0 ++ zvknha 1.0 ++ zvknhb 1.0 ++ zvksed 1.0 ++ zvksh 1.0 ++ zvks 1.0 ++ zvksg 1.0 ++ zvksc 1.0 ++ zvkt 1.0 ++ zvl32b 1.0 ++ zvl64b 1.0 ++ zvl128b 1.0 ++ zvl256b 1.0 ++ zvl512b 1.0 ++ zvl1024b 1.0 ++ zvl2048b 1.0 ++ zvl4096b 1.0 ++ zvl8192b 1.0 ++ zvl16384b 1.0 ++ zvl32768b 1.0 ++ zvl65536b 1.0 ++ ztso 1.0 ++ zca 1.0 ++ zcb 1.0 ++ zcf 1.0 ++ zcd 1.0 ++ zcmp 1.0 ++ smaia 1.0 ++ smcntrpmf 1.0 ++ smepmp 1.0 ++ smstateen 1.0 ++ ssaia 1.0 ++ sscofpmf 1.0 ++ ssstateen 1.0 ++ sstc 1.0 ++ svadu 1.0 ++ svinval 1.0 ++ svnapot 1.0 ++ svpbmt 1.0 ++ xcvmac 1.0 ++ xcvalu 1.0 ++ xtheadba 1.0 ++ xtheadbb 1.0 ++ xtheadbs 1.0 ++ xtheadcmo 1.0 ++ xtheadcondmov 1.0 ++ xtheadfmemidx 1.0 ++ xtheadfmv 1.0 ++ xtheadint 1.0 ++ xtheadmac 1.0 ++ xtheadmemidx 1.0 ++ xtheadmempair 1.0 ++ xtheadsync 1.0 ++ xtheadvector 1.0 ++ xtheadzvamo 1.0 ++ xventanacondops 1.0 ++ xsfvcp 1.0 +diff --git a/gas/testsuite/gas/riscv/march-imply-a.d b/gas/testsuite/gas/riscv/march-imply-a.d +new file mode 100644 +index 00000000000..b2cbfcf8376 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-imply-a.d +@@ -0,0 +1,6 @@ ++#as: -march=rv32ia -march-attr -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/march-imply-b.d b/gas/testsuite/gas/riscv/march-imply-b.d +new file mode 100644 +index 00000000000..82506c9a3e1 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-imply-b.d +@@ -0,0 +1,6 @@ ++#as: -march=rv32ib -march-attr -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0" +diff --git a/gas/testsuite/gas/riscv/march-imply-g.d b/gas/testsuite/gas/riscv/march-imply-g.d +index 239b717fd7f..7e7a96785bf 100644 +--- a/gas/testsuite/gas/riscv/march-imply-g.d ++++ b/gas/testsuite/gas/riscv/march-imply-g.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/march-imply-unsupported.d b/gas/testsuite/gas/riscv/march-imply-unsupported.d +index 612305765ab..5615d590866 100644 +--- a/gas/testsuite/gas/riscv/march-imply-unsupported.d ++++ b/gas/testsuite/gas/riscv/march-imply-unsupported.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0" ++ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/march-ok-reorder.d b/gas/testsuite/gas/riscv/march-ok-reorder.d +index 030f8b15018..712c1bdff4d 100644 +--- a/gas/testsuite/gas/riscv/march-ok-reorder.d ++++ b/gas/testsuite/gas/riscv/march-ok-reorder.d +@@ -4,4 +4,4 @@ + + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zba1p0_xbar2p0_xfoo2p0" ++ Tag_RISCV_arch: "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zba1p0_xbar2p0_xfoo2p0" +diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h +index 714a02f48ac..2c59283a7ee 100644 +--- a/include/opcode/riscv.h ++++ b/include/opcode/riscv.h +@@ -407,7 +407,6 @@ enum riscv_insn_class + + INSN_CLASS_I, + INSN_CLASS_C, +- INSN_CLASS_A, + INSN_CLASS_M, + INSN_CLASS_F, + INSN_CLASS_D, +@@ -422,6 +421,8 @@ enum riscv_insn_class + INSN_CLASS_ZIHINTPAUSE, + INSN_CLASS_ZIMOP, + INSN_CLASS_ZMMUL, ++ INSN_CLASS_ZAAMO, ++ INSN_CLASS_ZALRSC, + INSN_CLASS_ZAWRS, + INSN_CLASS_F_INX, + INSN_CLASS_D_INX, +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d +index de87f600387..0fb655c7239 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d +@@ -6,4 +6,4 @@ + + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_a2p0" ++ Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0" +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d +index 381ef850d97..10d01b1b7be 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d +@@ -6,4 +6,4 @@ + + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_a2p0" ++ Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0" +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d +index 6419fe89791..9649931d937 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d +@@ -6,4 +6,4 @@ + + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_a2p0_xbar2p0_xfoo2p0" ++ Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0_xbar2p0_xfoo2p0" +diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d +index f4012dcf90d..d71dd56820e 100644 +--- a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d ++++ b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d +@@ -6,4 +6,4 @@ + + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv32i2p1_a2p1" ++ Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0" +diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c +index b577029d479..f885fb26350 100644 +--- a/opcodes/riscv-opc.c ++++ b/opcodes/riscv-opc.c +@@ -570,94 +570,94 @@ const struct riscv_opcode riscv_opcodes[] = + {"subw", 64, INSN_CLASS_I, "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 }, + + /* Atomic memory operation instruction subset. */ +-{"lr.w", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"sc.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoadd.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoswap.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoand.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoxor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomax.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomaxu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomin.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amominu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"lr.w.aq", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQ, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"sc.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQ, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoadd.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQ, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoswap.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoand.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQ, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQ, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoxor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQ, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomax.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQ, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomaxu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomin.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQ, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amominu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"lr.w.rl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_RL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"sc.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_RL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoadd.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_RL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoswap.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_RL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoand.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_RL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_RL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoxor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_RL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomax.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_RL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomaxu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_RL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomin.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_RL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amominu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_RL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"lr.w.aqrl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQRL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"sc.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQRL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoadd.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoswap.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoand.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQRL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amoxor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomax.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomaxu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amomin.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"amominu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +-{"lr.d", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"sc.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoadd.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoswap.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoand.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoxor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomax.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomaxu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomin.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amominu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"lr.d.aq", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQ, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"sc.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQ, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoadd.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQ, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoswap.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoand.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQ, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQ, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoxor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQ, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomax.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQ, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomaxu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomin.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQ, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amominu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"lr.d.rl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_RL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"sc.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_RL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoadd.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_RL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoswap.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_RL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoand.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_RL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_RL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoxor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_RL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomax.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_RL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomaxu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_RL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomin.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_RL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amominu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_RL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"lr.d.aqrl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQRL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"sc.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQRL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoadd.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoswap.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoand.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQRL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amoxor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomax.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomaxu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amomin.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +-{"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"lr.w", 0, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_W, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"sc.w", 0, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_W, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoadd.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoswap.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoand.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoor.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoxor.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomax.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomaxu.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomin.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amominu.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"lr.w.aq", 0, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_W|MASK_AQ, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"sc.w.aq", 0, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_W|MASK_AQ, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoadd.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQ, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoswap.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoand.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQ, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoor.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQ, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoxor.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQ, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomax.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQ, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomaxu.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomin.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQ, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amominu.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"lr.w.rl", 0, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_W|MASK_RL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"sc.w.rl", 0, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_W|MASK_RL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoadd.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W|MASK_RL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoswap.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_RL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoand.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W|MASK_RL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoor.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W|MASK_RL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoxor.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W|MASK_RL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomax.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W|MASK_RL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomaxu.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_RL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomin.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W|MASK_RL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amominu.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W|MASK_RL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"lr.w.aqrl", 0, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_W|MASK_AQRL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"sc.w.aqrl", 0, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_W|MASK_AQRL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoadd.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoswap.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoand.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoor.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQRL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amoxor.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomax.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomaxu.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amomin.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"amominu.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, ++{"lr.d", 64, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_D, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"sc.d", 64, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_D, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoadd.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoswap.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoand.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoor.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoxor.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomax.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomaxu.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomin.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amominu.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"lr.d.aq", 64, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_D|MASK_AQ, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"sc.d.aq", 64, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_D|MASK_AQ, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoadd.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQ, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoswap.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoand.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQ, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoor.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQ, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoxor.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQ, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomax.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQ, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomaxu.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomin.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQ, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amominu.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"lr.d.rl", 64, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_D|MASK_RL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"sc.d.rl", 64, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_D|MASK_RL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoadd.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D|MASK_RL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoswap.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_RL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoand.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D|MASK_RL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoor.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D|MASK_RL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoxor.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D|MASK_RL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomax.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D|MASK_RL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomaxu.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_RL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomin.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D|MASK_RL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amominu.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D|MASK_RL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"lr.d.aqrl", 64, INSN_CLASS_ZALRSC, "d,0(s)", MATCH_LR_D|MASK_AQRL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"sc.d.aqrl", 64, INSN_CLASS_ZALRSC, "d,t,0(s)", MATCH_SC_D|MASK_AQRL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoadd.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoswap.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoand.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoor.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQRL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amoxor.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomax.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomaxu.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amomin.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, ++{"amominu.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, + + /* Multiply/Divide instruction subset. */ + {"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS }, +-- +2.51.0 + diff --git a/binutils-2.45-backport-RISC-V-Add-Privileged-Architecture-1.13-CSRs.patch b/binutils-2.45-backport-RISC-V-Add-Privileged-Architecture-1.13-CSRs.patch new file mode 100644 index 0000000..b97dece --- /dev/null +++ b/binutils-2.45-backport-RISC-V-Add-Privileged-Architecture-1.13-CSRs.patch @@ -0,0 +1,2850 @@ +From 6f9feb05a22ccc0d5a412e79cff63fbef270d885 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Fri, 9 May 2025 10:22:45 +0800 +Subject: [PATCH 4/9] RISC-V: Add Privileged Architecture 1.13 CSRs. + +This patch support RISC-V Privileged Architecture 1.13 CSRs 'medelegh' and +'hedelegh'. More details between 1.12 and 1.13 see [1]. + +[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv-preface.adoc + +Version log: Remove gas/po changes. + +bfd/ChangeLog: + + * cpu-riscv.c: New option. + * cpu-riscv.h (enum riscv_spec_class): Ditto. + +gas/ChangeLog: + + * config/tc-riscv.c: New option. + * configure: Ditto. + * configure.ac: Ditto. + * testsuite/gas/riscv/csr-version-1p10.d: New CSR. + * testsuite/gas/riscv/csr-version-1p10.l: New warning. + * testsuite/gas/riscv/csr-version-1p11.d: New CSR. + * testsuite/gas/riscv/csr-version-1p11.l: New warning. + * testsuite/gas/riscv/csr-version-1p12.d: New CSR. + * testsuite/gas/riscv/csr-version-1p12.l: New warning. + * testsuite/gas/riscv/csr.s: New CSR. + * testsuite/gas/riscv/attribute-15.d: New test. + * testsuite/gas/riscv/attribute-16.d: New test. + * testsuite/gas/riscv/csr-version-1p13.d: New test. + * testsuite/gas/riscv/csr-version-1p13.l: New test. + +include/ChangeLog: + + * opcode/riscv-opc.h (CSR_MEDELEGH): New CSR. + (CSR_HEDELEGH): Ditto. + (DECLARE_CSR): Ditto. + +(backported from 433372af698) +--- + bfd/cpu-riscv.c | 1 + + bfd/cpu-riscv.h | 1 + + gas/config/tc-riscv.c | 2 +- + gas/configure | 2 +- + gas/configure.ac | 2 +- + gas/testsuite/gas/riscv/attribute-15.d | 8 + + gas/testsuite/gas/riscv/attribute-16.d | 6 + + gas/testsuite/gas/riscv/csr-version-1p10.d | 4 + + gas/testsuite/gas/riscv/csr-version-1p10.l | 16 + + gas/testsuite/gas/riscv/csr-version-1p11.d | 4 + + gas/testsuite/gas/riscv/csr-version-1p11.l | 16 + + gas/testsuite/gas/riscv/csr-version-1p12.d | 4 + + gas/testsuite/gas/riscv/csr-version-1p12.l | 16 + + gas/testsuite/gas/riscv/csr-version-1p13.d | 941 ++++++++++++ + gas/testsuite/gas/riscv/csr-version-1p13.l | 1495 ++++++++++++++++++++ + gas/testsuite/gas/riscv/csr.s | 4 +- + include/opcode/riscv-opc.h | 16 +- + 17 files changed, 2528 insertions(+), 10 deletions(-) + create mode 100644 gas/testsuite/gas/riscv/attribute-15.d + create mode 100644 gas/testsuite/gas/riscv/attribute-16.d + create mode 100644 gas/testsuite/gas/riscv/csr-version-1p13.d + create mode 100644 gas/testsuite/gas/riscv/csr-version-1p13.l + +diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c +index 58cbdd846be..193d5709d6c 100644 +--- a/bfd/cpu-riscv.c ++++ b/bfd/cpu-riscv.c +@@ -118,6 +118,7 @@ const struct riscv_spec riscv_priv_specs[] = + {"1.10", PRIV_SPEC_CLASS_1P10}, + {"1.11", PRIV_SPEC_CLASS_1P11}, + {"1.12", PRIV_SPEC_CLASS_1P12}, ++ {"1.13", PRIV_SPEC_CLASS_1P13}, + }; + + /* Get the corresponding CSR version class by giving privilege +diff --git a/bfd/cpu-riscv.h b/bfd/cpu-riscv.h +index a395e739c5f..7fb8d01a86b 100644 +--- a/bfd/cpu-riscv.h ++++ b/bfd/cpu-riscv.h +@@ -33,6 +33,7 @@ enum riscv_spec_class + PRIV_SPEC_CLASS_1P10, + PRIV_SPEC_CLASS_1P11, + PRIV_SPEC_CLASS_1P12, ++ PRIV_SPEC_CLASS_1P13, + PRIV_SPEC_CLASS_DRAFT, + }; + +diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c +index a4161420128..b6a691771a3 100644 +--- a/gas/config/tc-riscv.c ++++ b/gas/config/tc-riscv.c +@@ -4987,7 +4987,7 @@ RISC-V options:\n\ + -fno-pic don't generate position-independent code (default)\n\ + -march=ISA set the RISC-V architecture\n\ + -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\ +- -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\ ++ -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.10, 1.11, 1.12, 1.13)\n\ + -mabi=ABI set the RISC-V ABI\n\ + -mrelax enable relax (default)\n\ + -mno-relax disable relax\n\ +diff --git a/gas/configure b/gas/configure +index 0bcb1611f4a..9200a9e7345 100755 +--- a/gas/configure ++++ b/gas/configure +@@ -12595,7 +12595,7 @@ _ACEOF + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $with_isa_spec" >&5 + $as_echo "$with_isa_spec" >&6; } + +- # --with-priv-spec=[1.9.1|1.10|1.11|1.12]. ++ # --with-priv-spec=[1.9.1|1.10|1.11|1.12|1.13]. + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for default configuration of --with-priv-spec" >&5 + $as_echo_n "checking for default configuration of --with-priv-spec... " >&6; } + if test "x${with_priv_spec}" != x; then +diff --git a/gas/configure.ac b/gas/configure.ac +index 7403ec71cd0..8eb5d60f024 100644 +--- a/gas/configure.ac ++++ b/gas/configure.ac +@@ -640,7 +640,7 @@ changequote([,])dnl + fi + AC_MSG_RESULT($with_isa_spec) + +- # --with-priv-spec=[1.9.1|1.10|1.11|1.12]. ++ # --with-priv-spec=[1.9.1|1.10|1.11|1.12|1.13]. + AC_MSG_CHECKING(for default configuration of --with-priv-spec) + if test "x${with_priv_spec}" != x; then + AC_DEFINE_UNQUOTED(DEFAULT_RISCV_PRIV_SPEC, "$with_priv_spec", +diff --git a/gas/testsuite/gas/riscv/attribute-15.d b/gas/testsuite/gas/riscv/attribute-15.d +new file mode 100644 +index 00000000000..929631a63bd +--- /dev/null ++++ b/gas/testsuite/gas/riscv/attribute-15.d +@@ -0,0 +1,8 @@ ++#as: -march-attr -mpriv-spec=1.13 ++#readelf: -A ++#source: attribute-11.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: [a-zA-Z0-9_\"].* ++ Tag_RISCV_priv_spec: 1 ++ Tag_RISCV_priv_spec_minor: 13 +diff --git a/gas/testsuite/gas/riscv/attribute-16.d b/gas/testsuite/gas/riscv/attribute-16.d +new file mode 100644 +index 00000000000..928d8d77789 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/attribute-16.d +@@ -0,0 +1,6 @@ ++#as: -march-attr -mpriv-spec=1.13 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: [a-zA-Z0-9_\"].* +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d +index dbdc077adac..6e57716b711 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.d +@@ -175,6 +175,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+30159073[ ]+csrw[ ]+misa,a1 + [ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg + [ ]+[0-9a-f]+:[ ]+30259073[ ]+csrw[ ]+medeleg,a1 ++[ ]+[0-9a-f]+:[ ]+31202573[ ]+csrr[ ]+a0,0x312 ++[ ]+[0-9a-f]+:[ ]+31259073[ ]+csrw[ ]+0x312,a1 + [ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg + [ ]+[0-9a-f]+:[ ]+30359073[ ]+csrw[ ]+mideleg,a1 + [ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie +@@ -555,6 +557,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1 + [ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg + [ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1 ++[ ]+[0-9a-f]+:[ ]+61202573[ ]+csrr[ ]+a0,0x612 ++[ ]+[0-9a-f]+:[ ]+61259073[ ]+csrw[ ]+0x612,a1 + [ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg + [ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1 + [ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie +diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l +index 054179a416d..f6be51c3175 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p10.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p10.l +@@ -273,6 +273,14 @@ + .*Info: macro .* + .*Warning: read-only CSR is written `csrw mconfigptr,a1' + .*Info: macro .* ++.*Warning: invalid CSR `medelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh' for the privileged spec `1.10' ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh' for the privileged spec `1.10' ++.*Info: macro .* + .*Warning: invalid CSR `mstatush', needs rv32i extension + .*Info: macro .* + .*Warning: invalid CSR `mstatush' for the privileged spec `1.10' +@@ -721,6 +729,14 @@ + .*Info: macro .* + .*Warning: invalid CSR `hedeleg', needs `h' extension + .*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs `h' extension ++.*Info: macro .* + .*Warning: invalid CSR `hideleg', needs `h' extension + .*Info: macro .* + .*Warning: invalid CSR `hideleg', needs `h' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d +index 7ba88b6d1d5..4610c76db86 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.d +@@ -175,6 +175,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+30159073[ ]+csrw[ ]+misa,a1 + [ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg + [ ]+[0-9a-f]+:[ ]+30259073[ ]+csrw[ ]+medeleg,a1 ++[ ]+[0-9a-f]+:[ ]+31202573[ ]+csrr[ ]+a0,0x312 ++[ ]+[0-9a-f]+:[ ]+31259073[ ]+csrw[ ]+0x312,a1 + [ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg + [ ]+[0-9a-f]+:[ ]+30359073[ ]+csrw[ ]+mideleg,a1 + [ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie +@@ -555,6 +557,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1 + [ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg + [ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1 ++[ ]+[0-9a-f]+:[ ]+61202573[ ]+csrr[ ]+a0,0x612 ++[ ]+[0-9a-f]+:[ ]+61259073[ ]+csrw[ ]+0x612,a1 + [ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg + [ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1 + [ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie +diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l +index cc365f1df41..059b4549594 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p11.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p11.l +@@ -273,6 +273,14 @@ + .*Info: macro .* + .*Warning: read-only CSR is written `csrw mconfigptr,a1' + .*Info: macro .* ++.*Warning: invalid CSR `medelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh' for the privileged spec `1.11' ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh' for the privileged spec `1.11' ++.*Info: macro .* + .*Warning: invalid CSR `mstatush', needs rv32i extension + .*Info: macro .* + .*Warning: invalid CSR `mstatush' for the privileged spec `1.11' +@@ -717,6 +725,14 @@ + .*Info: macro .* + .*Warning: invalid CSR `hedeleg', needs `h' extension + .*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs `h' extension ++.*Info: macro .* + .*Warning: invalid CSR `hideleg', needs `h' extension + .*Info: macro .* + .*Warning: invalid CSR `hideleg', needs `h' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d +index 677820b9526..4e37a9e7916 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.d ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.d +@@ -175,6 +175,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+30159073[ ]+csrw[ ]+misa,a1 + [ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg + [ ]+[0-9a-f]+:[ ]+30259073[ ]+csrw[ ]+medeleg,a1 ++[ ]+[0-9a-f]+:[ ]+31202573[ ]+csrr[ ]+a0,0x312 ++[ ]+[0-9a-f]+:[ ]+31259073[ ]+csrw[ ]+0x312,a1 + [ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg + [ ]+[0-9a-f]+:[ ]+30359073[ ]+csrw[ ]+mideleg,a1 + [ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie +@@ -555,6 +557,8 @@ Disassembly of section .text: + [ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1 + [ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg + [ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1 ++[ ]+[0-9a-f]+:[ ]+61202573[ ]+csrr[ ]+a0,0x612 ++[ ]+[0-9a-f]+:[ ]+61259073[ ]+csrw[ ]+0x612,a1 + [ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg + [ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1 + [ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie +diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l +index 7a7f5f717c5..73d72308696 100644 +--- a/gas/testsuite/gas/riscv/csr-version-1p12.l ++++ b/gas/testsuite/gas/riscv/csr-version-1p12.l +@@ -265,6 +265,14 @@ + .*Info: macro .* + .*Warning: read-only CSR is written `csrw mconfigptr,a1' + .*Info: macro .* ++.*Warning: invalid CSR `medelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh' for the privileged spec `1.12' ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh' for the privileged spec `1.12' ++.*Info: macro .* + .*Warning: invalid CSR `mstatush', needs rv32i extension + .*Info: macro .* + .*Warning: invalid CSR `mstatush', needs rv32i extension +@@ -441,6 +449,14 @@ + .*Info: macro .* + .*Warning: invalid CSR `hedeleg', needs `h' extension + .*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs `h' extension ++.*Info: macro .* + .*Warning: invalid CSR `hideleg', needs `h' extension + .*Info: macro .* + .*Warning: invalid CSR `hideleg', needs `h' extension +diff --git a/gas/testsuite/gas/riscv/csr-version-1p13.d b/gas/testsuite/gas/riscv/csr-version-1p13.d +new file mode 100644 +index 00000000000..13090304347 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/csr-version-1p13.d +@@ -0,0 +1,941 @@ ++#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.13 ++#source: csr.s ++#warning_output: csr-version-1p13.l ++#objdump: -dr -Mpriv-spec=1.13 ++ ++.*:[ ]+file format .* ++ ++ ++Disassembly of section .text: ++ ++0+000 <.text>: ++[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0 ++[ ]+[0-9a-f]+:[ ]+c0059073[ ]+csrw[ ]+cycle,a1 ++[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0 ++[ ]+[0-9a-f]+:[ ]+c0159073[ ]+csrw[ ]+time,a1 ++[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0 ++[ ]+[0-9a-f]+:[ ]+c0259073[ ]+csrw[ ]+instret,a1 ++[ ]+[0-9a-f]+:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3 ++[ ]+[0-9a-f]+:[ ]+c0359073[ ]+csrw[ ]+hpmcounter3,a1 ++[ ]+[0-9a-f]+:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4 ++[ ]+[0-9a-f]+:[ ]+c0459073[ ]+csrw[ ]+hpmcounter4,a1 ++[ ]+[0-9a-f]+:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5 ++[ ]+[0-9a-f]+:[ ]+c0559073[ ]+csrw[ ]+hpmcounter5,a1 ++[ ]+[0-9a-f]+:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6 ++[ ]+[0-9a-f]+:[ ]+c0659073[ ]+csrw[ ]+hpmcounter6,a1 ++[ ]+[0-9a-f]+:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7 ++[ ]+[0-9a-f]+:[ ]+c0759073[ ]+csrw[ ]+hpmcounter7,a1 ++[ ]+[0-9a-f]+:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8 ++[ ]+[0-9a-f]+:[ ]+c0859073[ ]+csrw[ ]+hpmcounter8,a1 ++[ ]+[0-9a-f]+:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9 ++[ ]+[0-9a-f]+:[ ]+c0959073[ ]+csrw[ ]+hpmcounter9,a1 ++[ ]+[0-9a-f]+:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10 ++[ ]+[0-9a-f]+:[ ]+c0a59073[ ]+csrw[ ]+hpmcounter10,a1 ++[ ]+[0-9a-f]+:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11 ++[ ]+[0-9a-f]+:[ ]+c0b59073[ ]+csrw[ ]+hpmcounter11,a1 ++[ ]+[0-9a-f]+:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12 ++[ ]+[0-9a-f]+:[ ]+c0c59073[ ]+csrw[ ]+hpmcounter12,a1 ++[ ]+[0-9a-f]+:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13 ++[ ]+[0-9a-f]+:[ ]+c0d59073[ ]+csrw[ ]+hpmcounter13,a1 ++[ ]+[0-9a-f]+:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14 ++[ ]+[0-9a-f]+:[ ]+c0e59073[ ]+csrw[ ]+hpmcounter14,a1 ++[ ]+[0-9a-f]+:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15 ++[ ]+[0-9a-f]+:[ ]+c0f59073[ ]+csrw[ ]+hpmcounter15,a1 ++[ ]+[0-9a-f]+:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16 ++[ ]+[0-9a-f]+:[ ]+c1059073[ ]+csrw[ ]+hpmcounter16,a1 ++[ ]+[0-9a-f]+:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17 ++[ ]+[0-9a-f]+:[ ]+c1159073[ ]+csrw[ ]+hpmcounter17,a1 ++[ ]+[0-9a-f]+:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18 ++[ ]+[0-9a-f]+:[ ]+c1259073[ ]+csrw[ ]+hpmcounter18,a1 ++[ ]+[0-9a-f]+:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19 ++[ ]+[0-9a-f]+:[ ]+c1359073[ ]+csrw[ ]+hpmcounter19,a1 ++[ ]+[0-9a-f]+:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20 ++[ ]+[0-9a-f]+:[ ]+c1459073[ ]+csrw[ ]+hpmcounter20,a1 ++[ ]+[0-9a-f]+:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21 ++[ ]+[0-9a-f]+:[ ]+c1559073[ ]+csrw[ ]+hpmcounter21,a1 ++[ ]+[0-9a-f]+:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22 ++[ ]+[0-9a-f]+:[ ]+c1659073[ ]+csrw[ ]+hpmcounter22,a1 ++[ ]+[0-9a-f]+:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23 ++[ ]+[0-9a-f]+:[ ]+c1759073[ ]+csrw[ ]+hpmcounter23,a1 ++[ ]+[0-9a-f]+:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24 ++[ ]+[0-9a-f]+:[ ]+c1859073[ ]+csrw[ ]+hpmcounter24,a1 ++[ ]+[0-9a-f]+:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25 ++[ ]+[0-9a-f]+:[ ]+c1959073[ ]+csrw[ ]+hpmcounter25,a1 ++[ ]+[0-9a-f]+:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26 ++[ ]+[0-9a-f]+:[ ]+c1a59073[ ]+csrw[ ]+hpmcounter26,a1 ++[ ]+[0-9a-f]+:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27 ++[ ]+[0-9a-f]+:[ ]+c1b59073[ ]+csrw[ ]+hpmcounter27,a1 ++[ ]+[0-9a-f]+:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28 ++[ ]+[0-9a-f]+:[ ]+c1c59073[ ]+csrw[ ]+hpmcounter28,a1 ++[ ]+[0-9a-f]+:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29 ++[ ]+[0-9a-f]+:[ ]+c1d59073[ ]+csrw[ ]+hpmcounter29,a1 ++[ ]+[0-9a-f]+:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30 ++[ ]+[0-9a-f]+:[ ]+c1e59073[ ]+csrw[ ]+hpmcounter30,a1 ++[ ]+[0-9a-f]+:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31 ++[ ]+[0-9a-f]+:[ ]+c1f59073[ ]+csrw[ ]+hpmcounter31,a1 ++[ ]+[0-9a-f]+:[ ]+c8002573[ ]+csrr[ ]+a0,cycleh ++[ ]+[0-9a-f]+:[ ]+c8059073[ ]+csrw[ ]+cycleh,a1 ++[ ]+[0-9a-f]+:[ ]+c8102573[ ]+csrr[ ]+a0,timeh ++[ ]+[0-9a-f]+:[ ]+c8159073[ ]+csrw[ ]+timeh,a1 ++[ ]+[0-9a-f]+:[ ]+c8202573[ ]+csrr[ ]+a0,instreth ++[ ]+[0-9a-f]+:[ ]+c8259073[ ]+csrw[ ]+instreth,a1 ++[ ]+[0-9a-f]+:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h ++[ ]+[0-9a-f]+:[ ]+c8359073[ ]+csrw[ ]+hpmcounter3h,a1 ++[ ]+[0-9a-f]+:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h ++[ ]+[0-9a-f]+:[ ]+c8459073[ ]+csrw[ ]+hpmcounter4h,a1 ++[ ]+[0-9a-f]+:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h ++[ ]+[0-9a-f]+:[ ]+c8559073[ ]+csrw[ ]+hpmcounter5h,a1 ++[ ]+[0-9a-f]+:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h ++[ ]+[0-9a-f]+:[ ]+c8659073[ ]+csrw[ ]+hpmcounter6h,a1 ++[ ]+[0-9a-f]+:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h ++[ ]+[0-9a-f]+:[ ]+c8759073[ ]+csrw[ ]+hpmcounter7h,a1 ++[ ]+[0-9a-f]+:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h ++[ ]+[0-9a-f]+:[ ]+c8859073[ ]+csrw[ ]+hpmcounter8h,a1 ++[ ]+[0-9a-f]+:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h ++[ ]+[0-9a-f]+:[ ]+c8959073[ ]+csrw[ ]+hpmcounter9h,a1 ++[ ]+[0-9a-f]+:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h ++[ ]+[0-9a-f]+:[ ]+c8a59073[ ]+csrw[ ]+hpmcounter10h,a1 ++[ ]+[0-9a-f]+:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h ++[ ]+[0-9a-f]+:[ ]+c8b59073[ ]+csrw[ ]+hpmcounter11h,a1 ++[ ]+[0-9a-f]+:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h ++[ ]+[0-9a-f]+:[ ]+c8c59073[ ]+csrw[ ]+hpmcounter12h,a1 ++[ ]+[0-9a-f]+:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h ++[ ]+[0-9a-f]+:[ ]+c8d59073[ ]+csrw[ ]+hpmcounter13h,a1 ++[ ]+[0-9a-f]+:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h ++[ ]+[0-9a-f]+:[ ]+c8e59073[ ]+csrw[ ]+hpmcounter14h,a1 ++[ ]+[0-9a-f]+:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h ++[ ]+[0-9a-f]+:[ ]+c8f59073[ ]+csrw[ ]+hpmcounter15h,a1 ++[ ]+[0-9a-f]+:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h ++[ ]+[0-9a-f]+:[ ]+c9059073[ ]+csrw[ ]+hpmcounter16h,a1 ++[ ]+[0-9a-f]+:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h ++[ ]+[0-9a-f]+:[ ]+c9159073[ ]+csrw[ ]+hpmcounter17h,a1 ++[ ]+[0-9a-f]+:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h ++[ ]+[0-9a-f]+:[ ]+c9259073[ ]+csrw[ ]+hpmcounter18h,a1 ++[ ]+[0-9a-f]+:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h ++[ ]+[0-9a-f]+:[ ]+c9359073[ ]+csrw[ ]+hpmcounter19h,a1 ++[ ]+[0-9a-f]+:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h ++[ ]+[0-9a-f]+:[ ]+c9459073[ ]+csrw[ ]+hpmcounter20h,a1 ++[ ]+[0-9a-f]+:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h ++[ ]+[0-9a-f]+:[ ]+c9559073[ ]+csrw[ ]+hpmcounter21h,a1 ++[ ]+[0-9a-f]+:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h ++[ ]+[0-9a-f]+:[ ]+c9659073[ ]+csrw[ ]+hpmcounter22h,a1 ++[ ]+[0-9a-f]+:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h ++[ ]+[0-9a-f]+:[ ]+c9759073[ ]+csrw[ ]+hpmcounter23h,a1 ++[ ]+[0-9a-f]+:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h ++[ ]+[0-9a-f]+:[ ]+c9859073[ ]+csrw[ ]+hpmcounter24h,a1 ++[ ]+[0-9a-f]+:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h ++[ ]+[0-9a-f]+:[ ]+c9959073[ ]+csrw[ ]+hpmcounter25h,a1 ++[ ]+[0-9a-f]+:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h ++[ ]+[0-9a-f]+:[ ]+c9a59073[ ]+csrw[ ]+hpmcounter26h,a1 ++[ ]+[0-9a-f]+:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h ++[ ]+[0-9a-f]+:[ ]+c9b59073[ ]+csrw[ ]+hpmcounter27h,a1 ++[ ]+[0-9a-f]+:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h ++[ ]+[0-9a-f]+:[ ]+c9c59073[ ]+csrw[ ]+hpmcounter28h,a1 ++[ ]+[0-9a-f]+:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h ++[ ]+[0-9a-f]+:[ ]+c9d59073[ ]+csrw[ ]+hpmcounter29h,a1 ++[ ]+[0-9a-f]+:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h ++[ ]+[0-9a-f]+:[ ]+c9e59073[ ]+csrw[ ]+hpmcounter30h,a1 ++[ ]+[0-9a-f]+:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h ++[ ]+[0-9a-f]+:[ ]+c9f59073[ ]+csrw[ ]+hpmcounter31h,a1 ++[ ]+[0-9a-f]+:[ ]+10002573[ ]+csrr[ ]+a0,sstatus ++[ ]+[0-9a-f]+:[ ]+10059073[ ]+csrw[ ]+sstatus,a1 ++[ ]+[0-9a-f]+:[ ]+10402573[ ]+csrr[ ]+a0,sie ++[ ]+[0-9a-f]+:[ ]+10459073[ ]+csrw[ ]+sie,a1 ++[ ]+[0-9a-f]+:[ ]+10502573[ ]+csrr[ ]+a0,stvec ++[ ]+[0-9a-f]+:[ ]+10559073[ ]+csrw[ ]+stvec,a1 ++[ ]+[0-9a-f]+:[ ]+10602573[ ]+csrr[ ]+a0,scounteren ++[ ]+[0-9a-f]+:[ ]+10659073[ ]+csrw[ ]+scounteren,a1 ++[ ]+[0-9a-f]+:[ ]+10a02573[ ]+csrr[ ]+a0,senvcfg ++[ ]+[0-9a-f]+:[ ]+10a59073[ ]+csrw[ ]+senvcfg,a1 ++[ ]+[0-9a-f]+:[ ]+14002573[ ]+csrr[ ]+a0,sscratch ++[ ]+[0-9a-f]+:[ ]+14059073[ ]+csrw[ ]+sscratch,a1 ++[ ]+[0-9a-f]+:[ ]+14102573[ ]+csrr[ ]+a0,sepc ++[ ]+[0-9a-f]+:[ ]+14159073[ ]+csrw[ ]+sepc,a1 ++[ ]+[0-9a-f]+:[ ]+14202573[ ]+csrr[ ]+a0,scause ++[ ]+[0-9a-f]+:[ ]+14259073[ ]+csrw[ ]+scause,a1 ++[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval ++[ ]+[0-9a-f]+:[ ]+14359073[ ]+csrw[ ]+stval,a1 ++[ ]+[0-9a-f]+:[ ]+14402573[ ]+csrr[ ]+a0,sip ++[ ]+[0-9a-f]+:[ ]+14459073[ ]+csrw[ ]+sip,a1 ++[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp ++[ ]+[0-9a-f]+:[ ]+18059073[ ]+csrw[ ]+satp,a1 ++[ ]+[0-9a-f]+:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid ++[ ]+[0-9a-f]+:[ ]+f1159073[ ]+csrw[ ]+mvendorid,a1 ++[ ]+[0-9a-f]+:[ ]+f1202573[ ]+csrr[ ]+a0,marchid ++[ ]+[0-9a-f]+:[ ]+f1259073[ ]+csrw[ ]+marchid,a1 ++[ ]+[0-9a-f]+:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid ++[ ]+[0-9a-f]+:[ ]+f1359073[ ]+csrw[ ]+mimpid,a1 ++[ ]+[0-9a-f]+:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid ++[ ]+[0-9a-f]+:[ ]+f1459073[ ]+csrw[ ]+mhartid,a1 ++[ ]+[0-9a-f]+:[ ]+f1502573[ ]+csrr[ ]+a0,mconfigptr ++[ ]+[0-9a-f]+:[ ]+f1559073[ ]+csrw[ ]+mconfigptr,a1 ++[ ]+[0-9a-f]+:[ ]+30002573[ ]+csrr[ ]+a0,mstatus ++[ ]+[0-9a-f]+:[ ]+30059073[ ]+csrw[ ]+mstatus,a1 ++[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+a0,misa ++[ ]+[0-9a-f]+:[ ]+30159073[ ]+csrw[ ]+misa,a1 ++[ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg ++[ ]+[0-9a-f]+:[ ]+30259073[ ]+csrw[ ]+medeleg,a1 ++[ ]+[0-9a-f]+:[ ]+31202573[ ]+csrr[ ]+a0,medelegh ++[ ]+[0-9a-f]+:[ ]+31259073[ ]+csrw[ ]+medelegh,a1 ++[ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg ++[ ]+[0-9a-f]+:[ ]+30359073[ ]+csrw[ ]+mideleg,a1 ++[ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie ++[ ]+[0-9a-f]+:[ ]+30459073[ ]+csrw[ ]+mie,a1 ++[ ]+[0-9a-f]+:[ ]+30502573[ ]+csrr[ ]+a0,mtvec ++[ ]+[0-9a-f]+:[ ]+30559073[ ]+csrw[ ]+mtvec,a1 ++[ ]+[0-9a-f]+:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren ++[ ]+[0-9a-f]+:[ ]+30659073[ ]+csrw[ ]+mcounteren,a1 ++[ ]+[0-9a-f]+:[ ]+31002573[ ]+csrr[ ]+a0,mstatush ++[ ]+[0-9a-f]+:[ ]+31059073[ ]+csrw[ ]+mstatush,a1 ++[ ]+[0-9a-f]+:[ ]+34002573[ ]+csrr[ ]+a0,mscratch ++[ ]+[0-9a-f]+:[ ]+34059073[ ]+csrw[ ]+mscratch,a1 ++[ ]+[0-9a-f]+:[ ]+34102573[ ]+csrr[ ]+a0,mepc ++[ ]+[0-9a-f]+:[ ]+34159073[ ]+csrw[ ]+mepc,a1 ++[ ]+[0-9a-f]+:[ ]+34202573[ ]+csrr[ ]+a0,mcause ++[ ]+[0-9a-f]+:[ ]+34259073[ ]+csrw[ ]+mcause,a1 ++[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval ++[ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mtval,a1 ++[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip ++[ ]+[0-9a-f]+:[ ]+34459073[ ]+csrw[ ]+mip,a1 ++[ ]+[0-9a-f]+:[ ]+34a02573[ ]+csrr[ ]+a0,mtinst ++[ ]+[0-9a-f]+:[ ]+34a59073[ ]+csrw[ ]+mtinst,a1 ++[ ]+[0-9a-f]+:[ ]+34b02573[ ]+csrr[ ]+a0,mtval2 ++[ ]+[0-9a-f]+:[ ]+34b59073[ ]+csrw[ ]+mtval2,a1 ++[ ]+[0-9a-f]+:[ ]+30a02573[ ]+csrr[ ]+a0,menvcfg ++[ ]+[0-9a-f]+:[ ]+30a59073[ ]+csrw[ ]+menvcfg,a1 ++[ ]+[0-9a-f]+:[ ]+31a02573[ ]+csrr[ ]+a0,menvcfgh ++[ ]+[0-9a-f]+:[ ]+31a59073[ ]+csrw[ ]+menvcfgh,a1 ++[ ]+[0-9a-f]+:[ ]+74702573[ ]+csrr[ ]+a0,mseccfg ++[ ]+[0-9a-f]+:[ ]+74759073[ ]+csrw[ ]+mseccfg,a1 ++[ ]+[0-9a-f]+:[ ]+75702573[ ]+csrr[ ]+a0,mseccfgh ++[ ]+[0-9a-f]+:[ ]+75759073[ ]+csrw[ ]+mseccfgh,a1 ++[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0 ++[ ]+[0-9a-f]+:[ ]+3a059073[ ]+csrw[ ]+pmpcfg0,a1 ++[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1 ++[ ]+[0-9a-f]+:[ ]+3a159073[ ]+csrw[ ]+pmpcfg1,a1 ++[ ]+[0-9a-f]+:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2 ++[ ]+[0-9a-f]+:[ ]+3a259073[ ]+csrw[ ]+pmpcfg2,a1 ++[ ]+[0-9a-f]+:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3 ++[ ]+[0-9a-f]+:[ ]+3a359073[ ]+csrw[ ]+pmpcfg3,a1 ++[ ]+[0-9a-f]+:[ ]+3a402573[ ]+csrr[ ]+a0,pmpcfg4 ++[ ]+[0-9a-f]+:[ ]+3a459073[ ]+csrw[ ]+pmpcfg4,a1 ++[ ]+[0-9a-f]+:[ ]+3a502573[ ]+csrr[ ]+a0,pmpcfg5 ++[ ]+[0-9a-f]+:[ ]+3a559073[ ]+csrw[ ]+pmpcfg5,a1 ++[ ]+[0-9a-f]+:[ ]+3a602573[ ]+csrr[ ]+a0,pmpcfg6 ++[ ]+[0-9a-f]+:[ ]+3a659073[ ]+csrw[ ]+pmpcfg6,a1 ++[ ]+[0-9a-f]+:[ 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]+csrr[ ]+a0,mhpmevent18h ++[ ]+[0-9a-f]+:[ ]+73259073[ ]+csrw[ ]+mhpmevent18h,a1 ++[ ]+[0-9a-f]+:[ ]+73302573[ ]+csrr[ ]+a0,mhpmevent19h ++[ ]+[0-9a-f]+:[ ]+73359073[ ]+csrw[ ]+mhpmevent19h,a1 ++[ ]+[0-9a-f]+:[ ]+73402573[ ]+csrr[ ]+a0,mhpmevent20h ++[ ]+[0-9a-f]+:[ ]+73459073[ ]+csrw[ ]+mhpmevent20h,a1 ++[ ]+[0-9a-f]+:[ ]+73502573[ ]+csrr[ ]+a0,mhpmevent21h ++[ ]+[0-9a-f]+:[ ]+73559073[ ]+csrw[ ]+mhpmevent21h,a1 ++[ ]+[0-9a-f]+:[ ]+73602573[ ]+csrr[ ]+a0,mhpmevent22h ++[ ]+[0-9a-f]+:[ ]+73659073[ ]+csrw[ ]+mhpmevent22h,a1 ++[ ]+[0-9a-f]+:[ ]+73702573[ ]+csrr[ ]+a0,mhpmevent23h ++[ ]+[0-9a-f]+:[ ]+73759073[ ]+csrw[ ]+mhpmevent23h,a1 ++[ ]+[0-9a-f]+:[ ]+73802573[ ]+csrr[ ]+a0,mhpmevent24h ++[ ]+[0-9a-f]+:[ ]+73859073[ ]+csrw[ ]+mhpmevent24h,a1 ++[ ]+[0-9a-f]+:[ ]+73902573[ ]+csrr[ ]+a0,mhpmevent25h ++[ ]+[0-9a-f]+:[ ]+73959073[ ]+csrw[ ]+mhpmevent25h,a1 ++[ ]+[0-9a-f]+:[ ]+73a02573[ ]+csrr[ ]+a0,mhpmevent26h ++[ ]+[0-9a-f]+:[ ]+73a59073[ ]+csrw[ ]+mhpmevent26h,a1 ++[ ]+[0-9a-f]+:[ ]+73b02573[ ]+csrr[ ]+a0,mhpmevent27h ++[ ]+[0-9a-f]+:[ ]+73b59073[ ]+csrw[ ]+mhpmevent27h,a1 ++[ ]+[0-9a-f]+:[ ]+73c02573[ ]+csrr[ ]+a0,mhpmevent28h ++[ ]+[0-9a-f]+:[ ]+73c59073[ ]+csrw[ ]+mhpmevent28h,a1 ++[ ]+[0-9a-f]+:[ ]+73d02573[ ]+csrr[ ]+a0,mhpmevent29h ++[ ]+[0-9a-f]+:[ ]+73d59073[ ]+csrw[ ]+mhpmevent29h,a1 ++[ ]+[0-9a-f]+:[ ]+73e02573[ ]+csrr[ ]+a0,mhpmevent30h ++[ ]+[0-9a-f]+:[ ]+73e59073[ ]+csrw[ ]+mhpmevent30h,a1 ++[ ]+[0-9a-f]+:[ ]+73f02573[ ]+csrr[ ]+a0,mhpmevent31h ++[ ]+[0-9a-f]+:[ ]+73f59073[ ]+csrw[ ]+mhpmevent31h,a1 ++[ ]+[0-9a-f]+:[ ]+14d02573[ ]+csrr[ ]+a0,stimecmp ++[ ]+[0-9a-f]+:[ ]+14d59073[ ]+csrw[ ]+stimecmp,a1 ++[ ]+[0-9a-f]+:[ ]+15d02573[ ]+csrr[ ]+a0,stimecmph ++[ ]+[0-9a-f]+:[ ]+15d59073[ ]+csrw[ ]+stimecmph,a1 ++[ ]+[0-9a-f]+:[ ]+24d02573[ ]+csrr[ ]+a0,vstimecmp ++[ ]+[0-9a-f]+:[ ]+24d59073[ ]+csrw[ ]+vstimecmp,a1 ++[ ]+[0-9a-f]+:[ ]+25d02573[ ]+csrr[ ]+a0,vstimecmph ++[ ]+[0-9a-f]+:[ ]+25d59073[ ]+csrw[ ]+vstimecmph,a1 ++[ ]+[0-9a-f]+:[ ]+14e02573[ ]+csrr[ ]+a0,sctrctl ++[ ]+[0-9a-f]+:[ ]+14e59073[ ]+csrw[ ]+sctrctl,a1 ++[ ]+[0-9a-f]+:[ ]+14f02573[ ]+csrr[ ]+a0,sctrstatus ++[ ]+[0-9a-f]+:[ ]+14f59073[ ]+csrw[ ]+sctrstatus,a1 ++[ ]+[0-9a-f]+:[ ]+15f02573[ ]+csrr[ ]+a0,sctrdepth ++[ ]+[0-9a-f]+:[ ]+15f59073[ ]+csrw[ ]+sctrdepth,a1 ++[ ]+[0-9a-f]+:[ ]+24e02573[ ]+csrr[ ]+a0,vsctrctl ++[ ]+[0-9a-f]+:[ ]+24e59073[ ]+csrw[ ]+vsctrctl,a1 ++[ ]+[0-9a-f]+:[ ]+34e02573[ ]+csrr[ ]+a0,mctrctl ++[ ]+[0-9a-f]+:[ ]+34e59073[ ]+csrw[ ]+mctrctl,a1 ++[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,0x0 ++[ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+0x0,a1 ++[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,0x4 ++[ ]+[0-9a-f]+:[ ]+00459073[ ]+csrw[ ]+0x4,a1 ++[ ]+[0-9a-f]+:[ ]+00502573[ ]+csrr[ ]+a0,0x5 ++[ ]+[0-9a-f]+:[ ]+00559073[ ]+csrw[ ]+0x5,a1 ++[ ]+[0-9a-f]+:[ ]+04002573[ ]+csrr[ ]+a0,0x40 ++[ ]+[0-9a-f]+:[ ]+04059073[ ]+csrw[ ]+0x40,a1 ++[ ]+[0-9a-f]+:[ ]+04102573[ ]+csrr[ ]+a0,0x41 ++[ ]+[0-9a-f]+:[ ]+04159073[ ]+csrw[ ]+0x41,a1 ++[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,0x42 ++[ ]+[0-9a-f]+:[ ]+04259073[ ]+csrw[ ]+0x42,a1 ++[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,0x43 ++[ ]+[0-9a-f]+:[ ]+04359073[ ]+csrw[ ]+0x43,a1 ++[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,0x44 ++[ ]+[0-9a-f]+:[ ]+04459073[ ]+csrw[ ]+0x44,a1 ++[ ]+[0-9a-f]+:[ ]+10202573[ ]+csrr[ ]+a0,0x102 ++[ ]+[0-9a-f]+:[ ]+10259073[ ]+csrw[ ]+0x102,a1 ++[ ]+[0-9a-f]+:[ ]+10302573[ ]+csrr[ ]+a0,0x103 ++[ ]+[0-9a-f]+:[ ]+10359073[ ]+csrw[ ]+0x103,a1 ++[ ]+[0-9a-f]+:[ ]+00102573[ ]+csrr[ ]+a0,fflags ++[ ]+[0-9a-f]+:[ ]+00159073[ ]+csrw[ ]+fflags,a1 ++[ ]+[0-9a-f]+:[ ]+00202573[ ]+csrr[ ]+a0,frm ++[ ]+[0-9a-f]+:[ ]+00259073[ ]+csrw[ ]+frm,a1 ++[ ]+[0-9a-f]+:[ ]+00302573[ ]+csrr[ ]+a0,fcsr ++[ ]+[0-9a-f]+:[ ]+00359073[ ]+csrw[ ]+fcsr,a1 ++[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr ++[ ]+[0-9a-f]+:[ ]+7b059073[ ]+csrw[ ]+dcsr,a1 ++[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc ++[ ]+[0-9a-f]+:[ ]+7b159073[ ]+csrw[ ]+dpc,a1 ++[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0 ++[ ]+[0-9a-f]+:[ ]+7b259073[ ]+csrw[ ]+dscratch0,a1 ++[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1 ++[ ]+[0-9a-f]+:[ ]+7b359073[ ]+csrw[ ]+dscratch1,a1 ++[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0 ++[ ]+[0-9a-f]+:[ ]+7b259073[ ]+csrw[ ]+dscratch0,a1 ++[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect ++[ ]+[0-9a-f]+:[ ]+7a059073[ ]+csrw[ ]+tselect,a1 ++[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1 ++[ ]+[0-9a-f]+:[ ]+7a159073[ ]+csrw[ ]+tdata1,a1 ++[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2 ++[ ]+[0-9a-f]+:[ ]+7a259073[ ]+csrw[ ]+tdata2,a1 ++[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 ++[ ]+[0-9a-f]+:[ ]+7a359073[ ]+csrw[ ]+tdata3,a1 ++[ ]+[0-9a-f]+:[ ]+7a402573[ ]+csrr[ ]+a0,tinfo ++[ ]+[0-9a-f]+:[ ]+7a459073[ ]+csrw[ ]+tinfo,a1 ++[ ]+[0-9a-f]+:[ ]+7a502573[ ]+csrr[ ]+a0,tcontrol ++[ ]+[0-9a-f]+:[ ]+7a559073[ ]+csrw[ ]+tcontrol,a1 ++[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext ++[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1 ++[ ]+[0-9a-f]+:[ ]+5a802573[ ]+csrr[ ]+a0,scontext ++[ ]+[0-9a-f]+:[ ]+5a859073[ ]+csrw[ ]+scontext,a1 ++[ ]+[0-9a-f]+:[ ]+7a802573[ ]+csrr[ ]+a0,mcontext ++[ ]+[0-9a-f]+:[ ]+7a859073[ ]+csrw[ ]+mcontext,a1 ++[ ]+[0-9a-f]+:[ ]+7aa02573[ ]+csrr[ ]+a0,mscontext ++[ ]+[0-9a-f]+:[ ]+7aa59073[ ]+csrw[ ]+mscontext,a1 ++[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1 ++[ ]+[0-9a-f]+:[ ]+7a159073[ ]+csrw[ ]+tdata1,a1 ++[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1 ++[ ]+[0-9a-f]+:[ ]+7a159073[ ]+csrw[ ]+tdata1,a1 ++[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1 ++[ ]+[0-9a-f]+:[ ]+7a159073[ ]+csrw[ ]+tdata1,a1 ++[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1 ++[ ]+[0-9a-f]+:[ ]+7a159073[ ]+csrw[ ]+tdata1,a1 ++[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1 ++[ ]+[0-9a-f]+:[ ]+7a159073[ ]+csrw[ ]+tdata1,a1 ++[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1 ++[ ]+[0-9a-f]+:[ ]+7a159073[ ]+csrw[ ]+tdata1,a1 ++[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 ++[ ]+[0-9a-f]+:[ ]+7a359073[ ]+csrw[ ]+tdata3,a1 ++[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 ++[ ]+[0-9a-f]+:[ ]+7a359073[ ]+csrw[ ]+tdata3,a1 ++[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed ++[ ]+[0-9a-f]+:[ ]+01559073[ ]+csrw[ ]+seed,a1 ++[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart ++[ ]+[0-9a-f]+:[ ]+00859073[ ]+csrw[ ]+vstart,a1 ++[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat ++[ ]+[0-9a-f]+:[ ]+00959073[ ]+csrw[ ]+vxsat,a1 ++[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm ++[ ]+[0-9a-f]+:[ ]+00a59073[ ]+csrw[ ]+vxrm,a1 ++[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr ++[ ]+[0-9a-f]+:[ ]+00f59073[ ]+csrw[ ]+vcsr,a1 ++[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl ++[ ]+[0-9a-f]+:[ ]+c2059073[ ]+csrw[ ]+vl,a1 ++[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype ++[ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1 ++[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb ++[ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1 ++[ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt ++[ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1 ++[ ]+[0-9a-f]+:[ ]+18102573[ ]+csrr[ ]+a0,srmcfg ++[ ]+[0-9a-f]+:[ ]+18159073[ ]+csrw[ ]+srmcfg,a1 +diff --git a/gas/testsuite/gas/riscv/csr-version-1p13.l b/gas/testsuite/gas/riscv/csr-version-1p13.l +new file mode 100644 +index 00000000000..42c8523a5ee +--- /dev/null ++++ b/gas/testsuite/gas/riscv/csr-version-1p13.l +@@ -0,0 +1,1495 @@ ++.*Assembler messages: ++.*Warning: read-only CSR is written `csrw cycle,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw time,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw instret,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter3,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter4,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter5,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter6,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter7,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter8,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter9,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter10,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter11,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter12,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter13,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter14,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter15,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter16,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter17,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter18,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter19,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter20,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter21,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter22,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter23,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter24,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter25,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter26,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter27,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter28,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter29,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter30,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter31,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `cycleh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `cycleh', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw cycleh,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `timeh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `timeh', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw timeh,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `instreth', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `instreth', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw instreth,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter3h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter4h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter5h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter6h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter7h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter8h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter9h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter10h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter11h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter12h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter13h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter14h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter15h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter16h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter17h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter18h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter19h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter20h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter21h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter22h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter23h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter24h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter25h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter26h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter27h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter28h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter29h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter30h,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hpmcounter31h,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw mvendorid,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw marchid,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw mimpid,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw mhartid,a1' ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw mconfigptr,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `medelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstatush', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstatush', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `menvcfgh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `menvcfgh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mseccfgh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mseccfgh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg1', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg1', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg3', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg3', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg5', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg5', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg7', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg7', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg9', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg9', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg11', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg11', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg13', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg13', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg15', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `pmpcfg15', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mcycleh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mcycleh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `minstreth', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `minstreth', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstatus', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstatus', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedeleg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedeleg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hedelegh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hideleg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hideleg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hie', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hie', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hcounteren', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hcounteren', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hgeie', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hgeie', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `htval', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `htval', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hip', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hip', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvip', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvip', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `htinst', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `htinst', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hgeip', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hgeip', needs `h' extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw hgeip,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `henvcfg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `henvcfg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `henvcfgh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `henvcfgh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `henvcfgh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `henvcfgh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hgatp', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hgatp', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `htimedelta', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `htimedelta', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `htimedeltah', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `htimedeltah', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `htimedeltah', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `htimedeltah', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsstatus', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsstatus', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsie', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsie', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstvec', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstvec', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsscratch', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsscratch', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsepc', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsepc', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vscause', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vscause', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstval', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstval', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsip', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsip', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsatp', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsatp', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mtopei', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mtopei', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mtopi', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mtopi', needs `smaia' extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw mtopi,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `mvien', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mvien', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mvip', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mvip', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `midelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `midelegh', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `midelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `midelegh', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mieh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mieh', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mieh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mieh', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mvienh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mvienh', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mvienh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mvienh', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mviph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mviph', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mviph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mviph', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `miph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `miph', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `miph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `miph', needs `smaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `miselect', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg', needs `smaia or smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg2', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg2', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg3', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg3', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg4', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg4', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg5', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg5', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg6', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mireg6', needs `smcsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mcyclecfg', needs `smcntrpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mcyclecfg', needs `smcntrpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `minstretcfg', needs `smcntrpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `minstretcfg', needs `smcntrpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mcyclecfgh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mcyclecfgh', needs `smcntrpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mcyclecfgh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mcyclecfgh', needs `smcntrpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `minstretcfgh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `minstretcfgh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnepc', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnepc', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mncause', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mncause', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen0', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen0', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen1', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen1', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen2', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen2', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen3', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen3', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen0', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen0', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen1', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen1', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen3', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen3', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen0h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen0h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen1h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen1h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen2h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen2h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen3h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen3h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen0h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen0h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen0h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen0h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen1h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen1h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen1h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen1h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen2h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen2h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen2h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen2h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen3h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen3h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen3h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen3h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension ++.*Info: macro .* ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `stopei', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `stopei', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `stopi', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `stopi', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw stopi,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `sieh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `sieh', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sieh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `sieh', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `siph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `siph', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `siph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `siph', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvien', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvien', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvien', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvien', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvictl', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvictl', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvictl', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvictl', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio1', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio1', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio1', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio1', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio2', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio2', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstopei', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstopei', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstopei', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstopei', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstopi', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstopi', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstopi', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstopi', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw vstopi,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `hidelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hidelegh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hidelegh', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hidelegh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hidelegh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hidelegh', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvienh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvienh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvienh', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvienh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvienh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hvienh', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviph', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviph', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviph', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviph', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio1h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio1h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio1h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio1h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio2h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio2h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio2h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio2h', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsieh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsieh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsieh', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsieh', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsieh', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsieh', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiph', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiph', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiph', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiph', needs `ssaia' extension ++.*Info: macro .* ++.*Warning: invalid CSR `ssp', needs `zicfiss' extension ++.*Info: macro .* ++.*Warning: invalid CSR `ssp', needs `zicfiss' extension ++.*Info: macro .* ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsiselect', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg', needs `ssaia or sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg2', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg3', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg4', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg5', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsireg6', needs `sscsrind' extension ++.*Info: macro .* ++.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw scountovf,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension ++.*Info: macro .* ++.*Warning: invalid CSR `stimecmp', needs `sstc' extension ++.*Info: macro .* ++.*Warning: invalid CSR `stimecmp', needs `sstc' extension ++.*Info: macro .* ++.*Warning: invalid CSR `stimecmph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `stimecmph', needs `sstc' extension ++.*Info: macro .* ++.*Warning: invalid CSR `stimecmph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `stimecmph', needs `sstc' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstimecmp', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstimecmp', needs `sstc' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstimecmp', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstimecmp', needs `sstc' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstimecmph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstimecmph', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstimecmph', needs `sstc' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstimecmph', needs rv32i extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstimecmph', needs `h' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstimecmph', needs `sstc' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrstatus', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `sctrdepth', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vsctrctl', needs `ssctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mctrctl', needs `smctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `mctrctl', needs `smctr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `ustatus' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `ustatus' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `uie' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `uie' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `utvec' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `utvec' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `uscratch' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `uscratch' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `uepc' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `uepc' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `ucause' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `ucause' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `utval' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `utval' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `uip' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `uip' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `sedeleg' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `sedeleg' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `sideleg' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `sideleg' for the privileged spec `1.13' ++.*Info: macro .* ++.*Warning: invalid CSR `fflags', needs `f' extension ++.*Info: macro .* ++.*Warning: invalid CSR `fflags', needs `f' extension ++.*Info: macro .* ++.*Warning: invalid CSR `frm', needs `f' extension ++.*Info: macro .* ++.*Warning: invalid CSR `frm', needs `f' extension ++.*Info: macro .* ++.*Warning: invalid CSR `fcsr', needs `f' extension ++.*Info: macro .* ++.*Warning: invalid CSR `fcsr', needs `f' extension ++.*Info: macro .* ++.*Warning: invalid CSR `seed', needs `zkr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `seed', needs `zkr' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstart', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vstart', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vxsat', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vxsat', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vxrm', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vxrm', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vcsr', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vcsr', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vl', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vl', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw vl,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `vtype', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vtype', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw vtype,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `vlenb', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: invalid CSR `vlenb', needs `zve32x' extension ++.*Info: macro .* ++.*Warning: read-only CSR is written `csrw vlenb,a1' ++.*Info: macro .* ++.*Warning: invalid CSR `jvt', needs `zcmt' extension ++.*Info: macro .* ++.*Warning: invalid CSR `jvt', needs `zcmt' extension ++.*Info: macro .* ++.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension ++.*Info: macro .* ++.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension ++.*Info: macro .* +diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s +index 3d8da5488a0..bab41f179b6 100644 +--- a/gas/testsuite/gas/riscv/csr.s ++++ b/gas/testsuite/gas/riscv/csr.s +@@ -3,7 +3,7 @@ + csrw \val, a1 + .endm + +- # Supported privileged specs, 1.9.1, 1.10, 1.11 and 1.12. ++ # Supported privileged specs, 1.10, 1.11, 1.12 and 1.13. + + # User Counter/Timers + csr cycle +@@ -101,6 +101,7 @@ + csr mstatus + csr misa + csr medeleg ++ csr medelegh # Added in 1.13 + csr mideleg + csr mie + csr mtvec +@@ -303,6 +304,7 @@ + # Hypervisor Trap Setup + csr hstatus + csr hedeleg ++ csr hedelegh # Added in 1.13 + csr hideleg + csr hie + csr hcounteren +diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h +index 6930f23c868..5529fab980f 100644 +--- a/include/opcode/riscv-opc.h ++++ b/include/opcode/riscv-opc.h +@@ -3220,6 +3220,7 @@ + #define CSR_MTVEC 0x305 + #define CSR_MCOUNTEREN 0x306 + #define CSR_MSTATUSH 0x310 ++#define CSR_MEDELEGH 0x312 + #define CSR_MSCRATCH 0x340 + #define CSR_MEPC 0x341 + #define CSR_MCAUSE 0x342 +@@ -3410,6 +3411,7 @@ + #define CSR_HIE 0x604 + #define CSR_HCOUNTEREN 0x606 + #define CSR_HGEIE 0x607 ++#define CSR_HEDELEGH 0x612 + #define CSR_HTVAL 0x643 + #define CSR_HIP 0x644 + #define CSR_HVIP 0x645 +@@ -4270,12 +4272,13 @@ DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_ + DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +-DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(medelegh, CSR_MEDELEGH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P13, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) ++DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mstatush, CSR_MSTATUSH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) +@@ -4464,6 +4467,7 @@ DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR + /* Privileged Hypervisor CSRs. */ + DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) ++DECLARE_CSR(hedelegh, CSR_HEDELEGH, CSR_CLASS_H_32, PRIV_SPEC_CLASS_1P13, PRIV_SPEC_CLASS_DRAFT) + DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) + DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +-- +2.51.0 + diff --git a/binutils-2.45-backport-RISC-V-Add-Profiles-RVA-B23S64-support.patch b/binutils-2.45-backport-RISC-V-Add-Profiles-RVA-B23S64-support.patch new file mode 100644 index 0000000..d48d94b --- /dev/null +++ b/binutils-2.45-backport-RISC-V-Add-Profiles-RVA-B23S64-support.patch @@ -0,0 +1,89 @@ +From f6a4905f9690aea8840dcf04bce54db06d6ae3b8 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Tue, 24 Jun 2025 21:11:26 +0800 +Subject: [PATCH 9/9] RISC-V: Add Profiles RVA/B23S64 support. + +This patch adds support for the RISC-V Profiles RVA23S64 and RVB23S64. + +Version log: +Fix wrong test for rvb23s. + +bfd/ChangeLog: + + * elfxx-riscv.c: New Profiles. + +gas/ChangeLog: + + * testsuite/gas/riscv/attribute-rva23s.d: New test. + * testsuite/gas/riscv/attribute-rvb23s.d: New test. + +(backported from 724da17ae58) +--- + bfd/elfxx-riscv.c | 16 +++++++++++++++- + gas/testsuite/gas/riscv/attribute-rva23s.d | 6 ++++++ + gas/testsuite/gas/riscv/attribute-rvb23s.d | 6 ++++++ + 3 files changed, 27 insertions(+), 1 deletion(-) + create mode 100644 gas/testsuite/gas/riscv/attribute-rva23s.d + create mode 100644 gas/testsuite/gas/riscv/attribute-rvb23s.d + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 9f07945026c..1bd0b46335b 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1272,6 +1272,14 @@ static struct riscv_profiles riscv_profiles_table[] = + "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs_supm"}, + ++ /* RVA23S contains all mandatory base ISA for RVA23U64 and the privileged ++ extensions as mandatory extensions. */ ++ {"rva23s64", "rv64imafdcbv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" ++ "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" ++ "_zfa_zawrs_supm_svbare_svade_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt" ++ "_svinval_svnapot_sstc_sscofpmf_ssnpm_ssu64xl_sha"}, ++ + /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension + 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ +@@ -1280,7 +1288,13 @@ static struct riscv_profiles riscv_profiles_table[] = + "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs_supm"}, + +- /* Currently we do not define S/M mode Profiles. */ ++ /* RVB23S contains all mandatory base ISA for RVB23U64 and the privileged ++ extensions as mandatory extensions. */ ++ {"rvb23s64", "rv64imafdcb_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" ++ "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" ++ "_zfa_zawrs_supm_svbare_svade_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt" ++ "_svinval_svnapot_sstc_sscofpmf_ssu64xl"}, + + /* Terminate the list. */ + {NULL, NULL} +diff --git a/gas/testsuite/gas/riscv/attribute-rva23s.d b/gas/testsuite/gas/riscv/attribute-rva23s.d +new file mode 100644 +index 00000000000..54e79aa28f2 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/attribute-rva23s.d +@@ -0,0 +1,6 @@ ++#as: -march=rva23s64 -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +diff --git a/gas/testsuite/gas/riscv/attribute-rvb23s.d b/gas/testsuite/gas/riscv/attribute-rvb23s.d +new file mode 100644 +index 00000000000..5cee65afde9 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/attribute-rvb23s.d +@@ -0,0 +1,6 @@ ++#as: -march=rvb23s64 -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl32b1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +-- +2.51.0 + diff --git a/binutils-2.45-backport-RISC-V-Add-augmented-hypervisor-extension-sha-suppor.patch b/binutils-2.45-backport-RISC-V-Add-augmented-hypervisor-extension-sha-suppor.patch new file mode 100644 index 0000000..34c0eec --- /dev/null +++ b/binutils-2.45-backport-RISC-V-Add-augmented-hypervisor-extension-sha-suppor.patch @@ -0,0 +1,315 @@ +From 5ba66971b90e0541e065092728aa364a553df7d4 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Fri, 9 May 2025 10:55:25 +0800 +Subject: [PATCH 5/9] RISC-V: Add augmented hypervisor extension 'sha' support. + +The augmented hypervisor extension 'sha'[1] is a new profile-defined extension +that captures the full set of features that are mandated to be supported along +with the H extension. + +https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile + +bfd/ChangeLog: + + * elfxx-riscv.c: New extension and implies. + +gas/ChangeLog: + + * testsuite/gas/riscv/imply.d: New test for sha. + * testsuite/gas/riscv/imply.s: Ditto. + * testsuite/gas/riscv/march-help.l: New extension. + +(backported from 0b0e00271c2) +--- + bfd/elfxx-riscv.c | 10 +++ + gas/testsuite/gas/riscv/imply.d | 104 +++++++++++++++++++++++ + gas/testsuite/gas/riscv/imply.s | 118 +++++++++++++++++++++++++++ + gas/testsuite/gas/riscv/march-help.l | 8 ++ + 4 files changed, 240 insertions(+) + create mode 100644 gas/testsuite/gas/riscv/imply.d + create mode 100644 gas/testsuite/gas/riscv/imply.s + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index da1049b7be6..8deeb63815d 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1115,6 +1115,15 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"m", "zmmul", check_implicit_always}, + {"zcmop", "zca", check_implicit_always}, + ++ {"sha", "h", check_implicit_always}, ++ {"sha", "ssstateen", check_implicit_always}, ++ {"sha", "shcounterenw", check_implicit_always}, ++ {"sha", "shvstvala", check_implicit_always}, ++ {"sha", "shtvala", check_implicit_always}, ++ {"sha", "shvstvecd", check_implicit_always}, ++ {"sha", "shvsatpa", check_implicit_always}, ++ {"sha", "shgatpa", check_implicit_always}, ++ + {"shcounterenw", "h", check_implicit_always}, + {"shgatpa", "h", check_implicit_always}, + {"shtvala", "h", check_implicit_always}, +@@ -1380,6 +1389,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = + + static struct riscv_supported_ext riscv_supported_std_s_ext[] = + { ++ {"sha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, +diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d +new file mode 100644 +index 00000000000..bce97ddf471 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/imply.d +@@ -0,0 +1,104 @@ ++#source: imply.s ++#as: -misa-spec=20191213 ++#objdump: --syms --special-syms ++ ++.*file format.*riscv.* ++ ++SYMBOL TABLE: ++[0-9a-f]+ l d .text 0+000 .text ++[0-9a-f]+ l d .data 0+000 .data ++[0-9a-f]+ l d .bss 0+000 .bss ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32e1p9 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p0_zicsr2p0_zifencei2p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicntr2p0_zicsr2p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zihpm2p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_m2p0_zmmul1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zaamo1p0_zabha1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zaamo1p0_zacas1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_a2p1_zaamo1p0_zalrsc1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xsfvfnrclipxfqf1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfwma1p0_zvl32b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvl64b1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcb1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmp1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmop1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zca1p0_zcmt1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicfilp1p0_zicsr2p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicfiss1p0_zicsr2p0_zimop1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssstateen1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shcounterenw1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shgatpa1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shtvala1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shvsatpa1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shvstvala1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shvstvecd1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinx1p0_zhinxmin1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinxmin1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_q2p2_zicsr2p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zdinx1p0_zqinx1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zdinx1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfa1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfh1p0_zfhmin1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcntrpmf1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smepmp1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smdbltrp1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssaia1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscsrind1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscofpmf1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscounterenw1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssstateen1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstc1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstvala1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstvecd1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssu64xl1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssdbltrp1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svade1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svadu1p0 ++[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svbare1p0 ++[0-9a-f]+ l d .riscv.attributes 0+000 .riscv.attributes +diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s +new file mode 100644 +index 00000000000..c047ed6b758 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/imply.s +@@ -0,0 +1,118 @@ ++.macro imply string base=i ++.option push ++.option arch, rv32\base\string ++nop ++.option pop ++.endm ++ ++.text ++imply ,g ++imply ,e ++imply ,i ++imply ,i2p0 ++ ++imply zicntr ++imply zihpm ++ ++imply m ++ ++imply zabha ++imply zacas ++imply a ++ ++imply xsfvcp ++imply xsfvqmaccqoq ++imply xsfvqmaccdod ++imply xsfvfnrclipxfqf ++ ++imply v ++imply zvfh ++imply zvfhmin ++imply zvfbfwma ++imply zvfbfmin ++imply zve64d ++imply zve64f ++imply zve32f ++imply zve64x ++imply zve32x ++imply zve32x_zvl65536b ++imply zve32x_zvl32768b ++imply zve32x_zvl16384b ++imply zve32x_zvl8192b ++imply zve32x_zvl4096b ++imply zve32x_zvl2048b ++imply zve32x_zvl1024b ++imply zve32x_zvl512b ++imply zve32x_zvl256b ++imply zve32x_zvl128b ++imply zve32x_zvl64b ++ ++imply zcb ++imply zcd ++imply zcf ++imply zcmp ++imply zcmop ++imply zcmt ++ ++imply zicfilp ++imply zicfiss ++ ++imply sha ++ ++imply shcounterenw ++imply shgatpa ++imply shtvala ++imply shvsatpa ++imply shvstvala ++imply shvstvecd ++imply h ++imply zhinx ++imply zhinxmin ++ ++imply q ++imply zqinx ++ ++imply d ++imply zdinx ++ ++imply zfa ++imply zfbfmin ++imply zfh ++imply zfhmin ++imply zfinx ++imply f ++ ++imply b ++ ++imply zk ++imply zkn ++imply zks ++imply zvbb ++imply zvkng ++imply zvknc ++imply zvkn ++imply zvksg ++imply zvksc ++imply zvks ++ ++imply smaia ++imply smcsrind ++imply smcntrpmf ++imply smstateen ++imply smepmp ++imply smdbltrp ++ ++imply ssaia ++imply sscsrind ++imply sscofpmf ++imply sscounterenw ++imply ssstateen ++imply sstc ++imply sstvala ++imply sstvecd ++imply ssu64xl ++imply ssdbltrp ++ ++imply svade ++imply svadu ++imply svbare +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index caf145dfc96..2a8f62a8264 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -91,6 +91,14 @@ All available -march extensions for RISC-V: + zcf 1.0 + zcd 1.0 + zcmp 1.0 ++ zcmt 1.0 ++ sha 1.0 ++ shcounterenw 1.0 ++ shgatpa 1.0 ++ shtvala 1.0 ++ shvsatpa 1.0 ++ shvstvala 1.0 ++ shvstvecd 1.0 + smaia 1.0 + smcntrpmf 1.0 + smepmp 1.0 +-- +2.51.0 + diff --git a/binutils-2.45-backport-RISC-V-Add-support-for-RISC-V-Profiles-20-22.patch b/binutils-2.45-backport-RISC-V-Add-support-for-RISC-V-Profiles-20-22.patch new file mode 100644 index 0000000..89872a8 --- /dev/null +++ b/binutils-2.45-backport-RISC-V-Add-support-for-RISC-V-Profiles-20-22.patch @@ -0,0 +1,282 @@ +From 1ce9baa5c39e4deba71483d787fa78388b8177e7 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Sun, 11 May 2025 21:38:18 +0800 +Subject: [PATCH 6/9] RISC-V: Add support for RISC-V Profiles 20/22. + +This patch introduces support for RISC-V Profiles RV20 and RV22 [1], +enabling developers to utilize these profiles through the -march option. + +[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0 + +bfd/ChangeLog: + + * elfxx-riscv.c (struct riscv_profiles): New struct. + (riscv_parse_extensions): New argument. + (riscv_find_profiles): New checking function. + (riscv_parse_subset): Add Profiles handler. + +gas/ChangeLog: + + * doc/as.texi: Update -march input type. + * doc/c-riscv.texi: Ditto. + * testsuite/gas/riscv/option-arch-fail.l: Modify hint info. + * testsuite/gas/riscv/attribute-17.d: New test. + * testsuite/gas/riscv/attribute-18.d: New test. + * testsuite/gas/riscv/march-fail-rvi20u64v.d: New test. + * testsuite/gas/riscv/march-fail-rvi20u64v.l: New test. + +(backported from 3d7fb9fa5c6) +--- + bfd/elfxx-riscv.c | 86 +++++++++++++++++-- + gas/doc/as.texi | 2 +- + gas/doc/c-riscv.texi | 15 +++- + gas/testsuite/gas/riscv/attribute-17.d | 6 ++ + gas/testsuite/gas/riscv/attribute-18.d | 6 ++ + .../gas/riscv/march-fail-rvi20u64v.d | 3 + + .../gas/riscv/march-fail-rvi20u64v.l | 1 + + gas/testsuite/gas/riscv/option-arch-fail.l | 2 +- + 8 files changed, 109 insertions(+), 12 deletions(-) + create mode 100644 gas/testsuite/gas/riscv/attribute-17.d + create mode 100644 gas/testsuite/gas/riscv/attribute-18.d + create mode 100644 gas/testsuite/gas/riscv/march-fail-rvi20u64v.d + create mode 100644 gas/testsuite/gas/riscv/march-fail-rvi20u64v.l + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 8deeb63815d..8ba677b37d4 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -949,6 +949,12 @@ static const struct elf_reloc_map riscv_reloc_map[] = + { BFD_RELOC_RISCV_SUB_ULEB128, R_RISCV_SUB_ULEB128 }, + }; + ++struct riscv_profiles ++{ ++ const char *profile_name; ++ const char *profile_string; ++}; ++ + /* Given a BFD reloc type, return a howto structure. */ + + reloc_howto_type * +@@ -1239,6 +1245,31 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {NULL, NULL, NULL} + }; + ++/* This table records the mapping form RISC-V Profiles into march string. */ ++static struct riscv_profiles riscv_profiles_table[] = ++{ ++ /* RVI20U only contains the base extension 'i' as mandatory extension. */ ++ {"rvi20u64", "rv64i"}, ++ {"rvi20u32", "rv32i"}, ++ ++ /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa, ++ zicclsm,za128rs' as mandatory extensions. */ ++ {"rva20u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_za128rs"}, ++ ++ /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr, ++ zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz, ++ zfhmin,zkt' as mandatory extensions. */ ++ {"rva22u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" ++ "_zicboz_zfhmin_zkt"}, ++ ++ /* Currently we do not define S/M mode Profiles. */ ++ ++ /* Terminate the list. */ ++ {NULL, NULL} ++}; ++ + /* For default_enable field, decide if the extension should + be enbaled by default. */ + +@@ -1865,10 +1896,11 @@ riscv_parsing_subset_version (const char *p, + static const char * + riscv_parse_extensions (riscv_parse_subset_t *rps, + const char *arch, +- const char *p) ++ const char *p, ++ bool profile) + { +- /* First letter must start with i, e or g. */ +- if (*p != 'e' && *p != 'i' && *p != 'g') ++ /* First letter must start with i, e, g or a profile. */ ++ if (*p != 'e' && *p != 'i' && *p != 'g' && !profile) + { + rps->error_handler + (_("%s: first ISA extension must be `e', `i' or `g'"), +@@ -2144,6 +2176,42 @@ riscv_set_default_arch (riscv_parse_subset_t *rps) + } + } + ++static bool ++riscv_find_profiles (riscv_parse_subset_t *rps, const char **pp) ++{ ++ const char *p = *pp; ++ ++ /* Checking if input string contains a Profiles. ++ There are two cases use Profiles in -march option: ++ ++ 1. Only use Profiles in '-march' as input ++ 2. Mixed Profiles with other extensions ++ ++ Use '_' to split Profiles and other extensions. */ ++ ++ for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) ++ { ++ /* Find profile at the begin. */ ++ if (startswith (p, riscv_profiles_table[i].profile_name)) ++ { ++ /* Handle the profile string. */ ++ riscv_parse_subset (rps, riscv_profiles_table[i].profile_string); ++ p += strlen (riscv_profiles_table[i].profile_name); ++ /* Handle string after profiles if exists. If missing underline ++ bewteen profile and other extensions, warn the user but not deal ++ as an error. */ ++ if (*p != '\0' && *p != '_') ++ _bfd_error_handler ++ (_("Warning: should use \"_\" to contact Profiles with other " ++ "extensions")); ++ *pp = p; ++ return true; ++ } ++ } ++ /* Not found profile, return directly. */ ++ return false; ++} ++ + /* Function for parsing ISA string. + + Return Value: +@@ -2181,8 +2249,14 @@ riscv_parse_subset (riscv_parse_subset_t *rps, + } + } + ++ bool profile = false; + p = arch; +- if (startswith (p, "rv32")) ++ if (riscv_find_profiles (rps, &p)) ++ { ++ /* Check if using Profiles. */ ++ profile = true; ++ } ++ else if (startswith (p, "rv32")) + { + *rps->xlen = 32; + p += 4; +@@ -2203,13 +2277,13 @@ riscv_parse_subset (riscv_parse_subset_t *rps, + string is empty. */ + if (strlen (arch)) + rps->error_handler ( +- _("%s: ISA string must begin with rv32 or rv64"), ++ _("%s: ISA string must begin with rv32, rv64 or Profiles"), + arch); + return false; + } + + /* Parse single standard and prefixed extensions. */ +- if (riscv_parse_extensions (rps, arch, p) == NULL) ++ if (riscv_parse_extensions (rps, arch, p, profile) == NULL) + return false; + + /* Finally add implicit extensions according to the current +diff --git a/gas/doc/as.texi b/gas/doc/as.texi +index 50c05436141..c1159c0321a 100644 +--- a/gas/doc/as.texi ++++ b/gas/doc/as.texi +@@ -556,7 +556,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. + + @emph{Target RISC-V options:} + [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}] +- [@b{-march}=@var{ISA}] ++ [@b{-march}=@var{ISA}|@var{Profiles}|@var{Profiles_ISA}] + [@b{-mabi}=@var{ABI}] + [@b{-mlittle-endian}|@b{-mbig-endian}] + @end ifset +diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi +index 7484a71798a..b40147f3701 100644 +--- a/gas/doc/c-riscv.texi ++++ b/gas/doc/c-riscv.texi +@@ -41,9 +41,11 @@ Generate position-independent code + @item -fno-pic + Don't generate position-independent code (default) + +-@cindex @samp{-march=ISA} option, RISC-V +-@item -march=ISA +-Select the base isa, as specified by ISA. For example -march=rv32ima. ++@cindex @samp{-march=ISA|Profiles|Profiles_ISA} option, RISC-V ++@item -march=ISA|Profiles|Profiles_ISA ++Select the base isa, as specified by ISA or Profiles or Profies_ISA. ++For example @samp{-march=rv32ima} @samp{-march=RVI20U64} ++@samp{-march=RVI20U64_d}. + If this option and the architecture attributes aren't set, then assembler + will check the default configure setting --with-arch=ISA. + +@@ -715,7 +717,12 @@ to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands + for the default version of its base ISA. On the other hand, the architecture + @code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in + which the abbreviation @code{G} is expanded to the @code{IMAFD} combination +-with default versions of the standard extensions. ++with default versions of the standard extensions. All Profiles are expanded ++ to the mandatory extensions it includes then processing. For example, ++@code{RVI20U32} is expanded to @code{RV32I2P0} for processing, which contains ++the mandatory extensions @code{I} as it defined. And you can also combine ++Profiles with ISA use underline, like @code{RVI20U32_D} is expanded to the ++@code{RV32I2P0_F2P0_D2P0}. + + @item Tag_RISCV_unaligned_access (6) + Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned +diff --git a/gas/testsuite/gas/riscv/attribute-17.d b/gas/testsuite/gas/riscv/attribute-17.d +new file mode 100644 +index 00000000000..8e87e8e6995 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/attribute-17.d +@@ -0,0 +1,6 @@ ++#as: -march=rva20u64 -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0" +diff --git a/gas/testsuite/gas/riscv/attribute-18.d b/gas/testsuite/gas/riscv/attribute-18.d +new file mode 100644 +index 00000000000..2bec0df99a6 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/attribute-18.d +@@ -0,0 +1,6 @@ ++#as: -march=rvi20u32_d -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0" +diff --git a/gas/testsuite/gas/riscv/march-fail-rvi20u64v.d b/gas/testsuite/gas/riscv/march-fail-rvi20u64v.d +new file mode 100644 +index 00000000000..175db999d6e +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-fail-rvi20u64v.d +@@ -0,0 +1,3 @@ ++#as: -march=rvi20u64v ++#source: empty.s ++#warning_output: march-fail-rvi20u64v.l +diff --git a/gas/testsuite/gas/riscv/march-fail-rvi20u64v.l b/gas/testsuite/gas/riscv/march-fail-rvi20u64v.l +new file mode 100644 +index 00000000000..ef271798c2c +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-fail-rvi20u64v.l +@@ -0,0 +1 @@ ++.*Warning: should use \"_\" to contact Profiles with other extensions +diff --git a/gas/testsuite/gas/riscv/option-arch-fail.l b/gas/testsuite/gas/riscv/option-arch-fail.l +index b9979a42618..d83f01d8ad5 100644 +--- a/gas/testsuite/gas/riscv/option-arch-fail.l ++++ b/gas/testsuite/gas/riscv/option-arch-fail.l +@@ -1,5 +1,5 @@ + .*Assembler messages: +-.*Error: m2p0: ISA string must begin with rv32 or rv64 ++.*Error: m2p0: ISA string must begin with rv32, rv64 or Profiles + .*Error: cannot \+ or \- base extension `i' in .option arch `\-i' + .*Error: cannot \+ or \- base extension `e' in .option arch `\+e' + .*Error: cannot \+ or \- base extension `g' in .option arch `\-g' +-- +2.51.0 + diff --git a/binutils-2.45-backport-RISC-V-Add-support-for-RISC-V-Profiles-23.patch b/binutils-2.45-backport-RISC-V-Add-support-for-RISC-V-Profiles-23.patch new file mode 100644 index 0000000..9e05d5b --- /dev/null +++ b/binutils-2.45-backport-RISC-V-Add-support-for-RISC-V-Profiles-23.patch @@ -0,0 +1,81 @@ +From 8d658efaf75bdc220fab86b535eeeb01f21d9687 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Sun, 11 May 2025 21:38:19 +0800 +Subject: [PATCH 7/9] RISC-V: Add support for RISC-V Profiles 23. + +This patch adds support for RISC-V RVA23 and RVB23 Profiles[1]. + +[1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-ratified + +bfd/ChangeLog: + + * elfxx-riscv.c: New profiles. + +gas/ChangeLog: + + * testsuite/gas/riscv/attribute-19.d: New test. + * testsuite/gas/riscv/attribute-20.d: New test. + +(backported from a3d6596ecf1) +--- + bfd/elfxx-riscv.c | 16 ++++++++++++++++ + gas/testsuite/gas/riscv/attribute-19.d | 6 ++++++ + gas/testsuite/gas/riscv/attribute-20.d | 6 ++++++ + 3 files changed, 28 insertions(+) + create mode 100644 gas/testsuite/gas/riscv/attribute-19.d + create mode 100644 gas/testsuite/gas/riscv/attribute-20.d + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 8ba677b37d4..d18df6ed7da 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1264,6 +1264,22 @@ static struct riscv_profiles riscv_profiles_table[] = + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt"}, + ++ /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension ++ 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory ++ extensions. */ ++ {"rva23u64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" ++ "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" ++ "_zfa_zawrs"}, ++ ++ /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension ++ 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory ++ extensions. */ ++ {"rvb23u64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" ++ "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb" ++ "_zfa_zawrs"}, ++ + /* Currently we do not define S/M mode Profiles. */ + + /* Terminate the list. */ +diff --git a/gas/testsuite/gas/riscv/attribute-19.d b/gas/testsuite/gas/riscv/attribute-19.d +new file mode 100644 +index 00000000000..1cd15d5b109 +--- /dev/null ++++ b/gas/testsuite/gas/riscv/attribute-19.d +@@ -0,0 +1,6 @@ ++#as: -march=rva23u64 -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +diff --git a/gas/testsuite/gas/riscv/attribute-20.d b/gas/testsuite/gas/riscv/attribute-20.d +new file mode 100644 +index 00000000000..e8fb7678a1a +--- /dev/null ++++ b/gas/testsuite/gas/riscv/attribute-20.d +@@ -0,0 +1,6 @@ ++#as: -march=rvb23u64 -misa-spec=20191213 ++#readelf: -A ++#source: empty.s ++Attribute Section: riscv ++File Attributes ++ Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +-- +2.51.0 + diff --git a/binutils-2.45-backport-RISC-V-Ssnpm-smnpm-and-smmpm-imply-zicsr.patch b/binutils-2.45-backport-RISC-V-Ssnpm-smnpm-and-smmpm-imply-zicsr.patch new file mode 100644 index 0000000..ab448d2 --- /dev/null +++ b/binutils-2.45-backport-RISC-V-Ssnpm-smnpm-and-smmpm-imply-zicsr.patch @@ -0,0 +1,42 @@ +From ba863bcd4c19a8383866fe4257cace8166878aa1 Mon Sep 17 00:00:00 2001 +From: Dongyan Chen +Date: Thu, 20 Mar 2025 12:51:02 +0800 +Subject: [PATCH 3/9] RISC-V: Ssnpm, smnpm and smmpm imply zicsr. + +According to the spec[1], imply zicsr for ssnpm, smnpm and smmpm. + +[1] https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc + +bfd/ChangeLog: + + * elfxx-riscv.c: imply zicsr. + +(backported from bc965121b5f) +--- + bfd/elfxx-riscv.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index cac908b88ad..da1049b7be6 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1205,6 +1205,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"smcntrpmf", "zicsr", check_implicit_always}, + {"smstateen", "ssstateen", check_implicit_always}, + {"smepmp", "zicsr", check_implicit_always}, ++ {"smnpm", "zicsr", check_implicit_always}, ++ {"smmpm", "zicsr", check_implicit_always}, + {"ssaia", "zicsr", check_implicit_always}, + {"sscofpmf", "zicsr", check_implicit_always}, + {"sscounterenw", "zicsr", check_implicit_always}, +@@ -1213,6 +1215,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = + {"sstvala", "zicsr", check_implicit_always}, + {"sstvecd", "zicsr", check_implicit_always}, + {"ssu64xl", "zicsr", check_implicit_always}, ++ {"ssnpm", "zicsr", check_implicit_always}, + + {"svade", "zicsr", check_implicit_always}, + {"svadu", "zicsr", check_implicit_always}, +-- +2.51.0 + diff --git a/binutils-2.45-backport-RISC-V-Support-pointer-masking-extension-1.0.patch b/binutils-2.45-backport-RISC-V-Support-pointer-masking-extension-1.0.patch new file mode 100644 index 0000000..1c68fda --- /dev/null +++ b/binutils-2.45-backport-RISC-V-Support-pointer-masking-extension-1.0.patch @@ -0,0 +1,115 @@ +From 54a700a0d18e3b2404d2d3f43f733a70021c8edc Mon Sep 17 00:00:00 2001 +From: Jerry Zhang Jian +Date: Mon, 17 Mar 2025 20:16:35 +0800 +Subject: [PATCH 2/9] RISC-V: Support pointer masking extension 1.0 + +- Adding Ssnpm, Smnpm, Smmpm, Sspm, and Supm +- No new CSR added +- Pointer masking only applies to RV64 +- Ref: https://github.com/riscv/riscv-j-extension/releases/download/pointer-masking-ratified/pointer-masking-ratified.pdf + +Signed-off-by: Jerry Zhang Jian + +(backported from 7b2a5f7183b) +--- + bfd/elfxx-riscv.c | 35 +++++++++++++++++++ + .../riscv/march-fail-rv32-pointer-masking.d | 3 ++ + .../riscv/march-fail-rv32-pointer-masking.l | 6 ++++ + gas/testsuite/gas/riscv/march-help.l | 5 +++ + 4 files changed, 49 insertions(+) + create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32-pointer-masking.d + create mode 100644 gas/testsuite/gas/riscv/march-fail-rv32-pointer-masking.l + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index 3336de7f168..cac908b88ad 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1402,6 +1402,11 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = + {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"ssnpm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"smnpm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"smmpm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"sspm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, ++ {"supm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {NULL, 0, 0, 0, 0} + }; + +@@ -2047,6 +2052,36 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) + (_("`xtheadvector' is conflict with the `v' extension")); + no_conflict = false; + } ++ if (riscv_lookup_subset (rps->subset_list, "ssnpm", &subset) && xlen != 64) ++ { ++ rps->error_handler (_ ("rv%d does not support the `ssnpm' extension"), ++ xlen); ++ no_conflict = false; ++ } ++ if (riscv_lookup_subset (rps->subset_list, "smnpm", &subset) && xlen != 64) ++ { ++ rps->error_handler (_ ("rv%d does not support the `smnpm' extension"), ++ xlen); ++ no_conflict = false; ++ } ++ if (riscv_lookup_subset (rps->subset_list, "smmpm", &subset) && xlen != 64) ++ { ++ rps->error_handler (_ ("rv%d does not support the `smmpm' extension"), ++ xlen); ++ no_conflict = false; ++ } ++ if (riscv_lookup_subset (rps->subset_list, "sspm", &subset) && xlen != 64) ++ { ++ rps->error_handler (_ ("rv%d does not support the `sspm' extension"), ++ xlen); ++ no_conflict = false; ++ } ++ if (riscv_lookup_subset (rps->subset_list, "supm", &subset) && xlen != 64) ++ { ++ rps->error_handler (_ ("rv%d does not support the `supm' extension"), ++ xlen); ++ no_conflict = false; ++ } + + bool support_zve = false; + bool support_zvl = false; +diff --git a/gas/testsuite/gas/riscv/march-fail-rv32-pointer-masking.d b/gas/testsuite/gas/riscv/march-fail-rv32-pointer-masking.d +new file mode 100644 +index 00000000000..fb4dfc619dc +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-fail-rv32-pointer-masking.d +@@ -0,0 +1,3 @@ ++#as: -march=rv32i_ssnpm_smnpm_smmpm_sspm_supm ++#source: empty.s ++#error_output: march-fail-rv32-pointer-masking.l +diff --git a/gas/testsuite/gas/riscv/march-fail-rv32-pointer-masking.l b/gas/testsuite/gas/riscv/march-fail-rv32-pointer-masking.l +new file mode 100644 +index 00000000000..119652878dd +--- /dev/null ++++ b/gas/testsuite/gas/riscv/march-fail-rv32-pointer-masking.l +@@ -0,0 +1,6 @@ ++.*Assembler messages: ++.*Error: rv32 does not support the `ssnpm' extension ++.*Error: rv32 does not support the `smnpm' extension ++.*Error: rv32 does not support the `smmpm' extension ++.*Error: rv32 does not support the `sspm' extension ++.*Error: rv32 does not support the `supm' extension +diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l +index c5754837e05..caf145dfc96 100644 +--- a/gas/testsuite/gas/riscv/march-help.l ++++ b/gas/testsuite/gas/riscv/march-help.l +@@ -103,6 +103,11 @@ All available -march extensions for RISC-V: + svinval 1.0 + svnapot 1.0 + svpbmt 1.0 ++ ssnpm 1.0 ++ smnpm 1.0 ++ smmpm 1.0 ++ sspm 1.0 ++ supm 1.0 + xcvmac 1.0 + xcvalu 1.0 + xtheadba 1.0 +-- +2.51.0 + diff --git a/binutils-2.45-backport-RISC-V-Update-Profiles-string-in-RV23.patch b/binutils-2.45-backport-RISC-V-Update-Profiles-string-in-RV23.patch new file mode 100644 index 0000000..1bae7a9 --- /dev/null +++ b/binutils-2.45-backport-RISC-V-Update-Profiles-string-in-RV23.patch @@ -0,0 +1,73 @@ +From eb3663f7a0825fbd51dd2083cc83627af7fb9cb1 Mon Sep 17 00:00:00 2001 +From: Jiawei +Date: Tue, 24 Jun 2025 19:09:27 +0800 +Subject: [PATCH 8/9] RISC-V: Update Profiles string in RV23. + +Update the Profiles string in RV23 to include the extensions 'b' and 'supm'. + +bfd/ChangeLog: + + * elfxx-riscv.c: Update Profiles string in RV23. + +gas/ChangeLog: + + * testsuite/gas/riscv/attribute-19.d: Update test string. + * testsuite/gas/riscv/attribute-20.d: Ditto. + +(backported from a026e16514b) +--- + bfd/elfxx-riscv.c | 8 ++++---- + gas/testsuite/gas/riscv/attribute-19.d | 2 +- + gas/testsuite/gas/riscv/attribute-20.d | 2 +- + 3 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c +index d18df6ed7da..9f07945026c 100644 +--- a/bfd/elfxx-riscv.c ++++ b/bfd/elfxx-riscv.c +@@ -1267,18 +1267,18 @@ static struct riscv_profiles riscv_profiles_table[] = + /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension + 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ +- {"rva23u64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ {"rva23u64", "rv64imafdcbv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" +- "_zfa_zawrs"}, ++ "_zfa_zawrs_supm"}, + + /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension + 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ +- {"rvb23u64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" ++ {"rvb23u64", "rv64imafdcb_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb" +- "_zfa_zawrs"}, ++ "_zfa_zawrs_supm"}, + + /* Currently we do not define S/M mode Profiles. */ + +diff --git a/gas/testsuite/gas/riscv/attribute-19.d b/gas/testsuite/gas/riscv/attribute-19.d +index 1cd15d5b109..d73e3f00ed8 100644 +--- a/gas/testsuite/gas/riscv/attribute-19.d ++++ b/gas/testsuite/gas/riscv/attribute-19.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" ++ Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0" +diff --git a/gas/testsuite/gas/riscv/attribute-20.d b/gas/testsuite/gas/riscv/attribute-20.d +index e8fb7678a1a..22bcc13f207 100644 +--- a/gas/testsuite/gas/riscv/attribute-20.d ++++ b/gas/testsuite/gas/riscv/attribute-20.d +@@ -3,4 +3,4 @@ + #source: empty.s + Attribute Section: riscv + File Attributes +- Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" ++ Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_supm1p0" +-- +2.51.0 + -- Gitee