From 7d36384cf582f3e94920c55100fed5e4763d3975 Mon Sep 17 00:00:00 2001 From: root Date: Thu, 19 Sep 2024 01:36:50 +0800 Subject: [PATCH] add sw8a patch --- 0017-ceph-Add-sw64-8A-architecture.patch | 782 +++++++++++++++++++++++ ceph.spec | 7 +- 2 files changed, 788 insertions(+), 1 deletion(-) create mode 100644 0017-ceph-Add-sw64-8A-architecture.patch diff --git a/0017-ceph-Add-sw64-8A-architecture.patch b/0017-ceph-Add-sw64-8A-architecture.patch new file mode 100644 index 0000000..e9d1c67 --- /dev/null +++ b/0017-ceph-Add-sw64-8A-architecture.patch @@ -0,0 +1,782 @@ +diff -uNar ceph-16.2.7.org/src/boost/boost/atomic/detail/ops_gcc_sw_64.hpp ceph-16.2.7.sw/src/boost/boost/atomic/detail/ops_gcc_sw_64.hpp +--- ceph-16.2.7.org/src/boost/boost/atomic/detail/ops_gcc_sw_64.hpp 2024-09-12 18:23:09.241552259 +0800 ++++ ceph-16.2.7.sw/src/boost/boost/atomic/detail/ops_gcc_sw_64.hpp 2024-09-12 18:43:20.388573540 +0800 +@@ -114,18 +114,15 @@ + static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, tmp; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" +- "mov %5, %1\n\t" ++ "ldi %2,%3\n\t" ++ "mov %4, %1\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -134,10 +131,9 @@ + + : "=&r" (original), // %0 + "=&r" (tmp), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -157,11 +153,9 @@ + "ldi %4,%6\n\t" + "lldw %2, 0(%4)\n\t" // current = *(&storage) + "cmpeq %2, %0, %5\n\t" // success = current == expected +- "wr_f %5\n\t" // success = current == expected ++ "beq %5, 2f\n\t" // if (success == 0) goto end + "mov %2, %0\n\t" // expected = current + "lstw %1, 0(%4)\n\t" // storage = desired; desired = store succeeded +- "rd_f %1\n\t" // storage = desired; desired = store succeeded +- "beq %5, 2f\n\t" // if (success == 0) goto end + "mov %1, %3\n\t" // success = desired + "2:\n\t" + : "+r" (expected), // %0 +@@ -194,11 +188,9 @@ + "mov %7, %1\n\t" // tmp = desired + "lldw %2, 0(%4)\n\t" // current = *(&storage) + "cmpeq %2, %0, %5\n\t" // success = current == expected +- "wr_f %5\n\t" // success = current == expected ++ "beq %5, 2f\n\t" // if (success == 0) goto end + "mov %2, %0\n\t" // expected = current + "lstw %1, 0(%4)\n\t" // storage = tmp; tmp = store succeeded +- "rd_f %1\n\t" // storage = tmp; tmp = store succeeded +- "beq %5, 2f\n\t" // if (success == 0) goto end + "beq %1, 3f\n\t" // if (tmp == 0) goto retry + "mov %1, %3\n\t" // success = tmp + "2:\n\t" +@@ -227,18 +219,15 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "addw %0, %5, %1\n\t" ++ "addw %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -247,10 +236,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -260,18 +248,15 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "subw %0, %5, %1\n\t" ++ "subw %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -280,10 +265,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -293,18 +277,15 @@ + static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n\t" +- "ldi %2,%4\n\t" +- "ldi %3,1\n\t" ++ "ldi %2,%3\n\t" + "lldw %0, 0(%2)\n\t" +- "wr_f %3\n\t" +- "and %0, %5, %1\n\t" ++ "and %0, %4, %1\n\t" + "lstw %1, 0(%2)\n\t" +- "rd_f %1\n\t" + "beq %1, 2f\n\t" + + ".subsection 2\n\t" +@@ -313,10 +294,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -326,18 +306,15 @@ + static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %? \n" +- "bis %0, %5, %1\n" ++ "bis %0, %4, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -346,10 +323,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -359,18 +335,15 @@ + static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "xor %0, %5, %1\n" ++ "xor %0, %4, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -379,10 +352,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -411,19 +383,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "zapnot %1, #1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -432,10 +401,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -445,19 +413,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "zapnot %1, #1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -466,10 +431,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -487,19 +451,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "sextb %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -508,10 +469,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -521,19 +481,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "sextb %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -542,10 +499,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -564,19 +520,16 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "zapnot %1, #3, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -585,10 +538,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -598,19 +550,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "zapnot %1, #3, %1\n" + "lstw %1, %2\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -619,10 +568,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -640,18 +588,15 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "addw %0, %5, %1\n" ++ "addw %0, %4, %1\n" + "sexth %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -660,10 +605,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -673,19 +617,16 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + base_type::fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldw %0, 0(%2)\n" +- "wr_f %3 \n" +- "subw %0, %5, %1\n" ++ "subw %0, %4, %1\n" + "sexth %1, %1\n" + "lstw %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -694,10 +635,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + base_type::fence_after(order); +@@ -733,18 +673,15 @@ + static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, tmp; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" +- "mov %5, %1\n" ++ "ldi %2,%3\n" ++ "mov %4, %1\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -753,10 +690,9 @@ + + : "=&r" (original), // %0 + "=&r" (tmp), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -776,11 +712,9 @@ + "ldi %4,%6\n" + "lldl %2, 0(%4)\n" // current = *(&storage) + "cmpeq %2, %0, %5\n" // success = current == expected +- "wr_f %5 \n" ++ "beq %5, 2f\n" // if (success == 0) goto end + "mov %2, %0\n" // expected = current + "lstl %1, 0(%4)\n" // storage = desired; desired = store succeeded +- "rd_f %1 \n" +- "beq %5, 2f\n" // if (success == 0) goto end + "mov %1, %3\n" // success = desired + "2:\n\t" + : "+r" (expected), // %0 +@@ -813,11 +747,9 @@ + "mov %7, %1\n" // tmp = desired + "lldl %2, 0(%4)\n" // current = *(&storage) + "cmpeq %2, %0, %5\n" // success = current == expected +- "wr_f %5 \n" ++ "beq %5, 2f\n" // if (success == 0) goto end + "mov %2, %0\n" // expected = current + "lstl %1, 0(%4)\n" // storage = tmp; tmp = store succeeded +- "rd_f %1 \n" +- "beq %5, 2f\n" // if (success == 0) goto end + "beq %1, 3f\n" // if (tmp == 0) goto retry + "mov %1, %3\n" // success = tmp + "2:\n\t" +@@ -846,18 +778,15 @@ + static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1, tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "addl %0, %5, %1\n" ++ "addl %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -866,10 +795,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -879,18 +807,15 @@ + static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "subl %0, %5, %1\n" ++ "subl %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -899,10 +824,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -912,18 +836,15 @@ + static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "and %0, %5, %1\n" ++ "and %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -932,10 +853,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -945,18 +865,15 @@ + static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "bis %0, %5, %1\n" ++ "bis %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -965,10 +882,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); +@@ -978,18 +894,15 @@ + static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT + { + storage_type original, modified; +- storage_type tmp1,tmp2; ++ storage_type tmp1; + fence_before(order); + __asm__ __volatile__ + ( + "1:\n" +- "ldi %2,%4\n" +- "ldi %3,1\n" ++ "ldi %2,%3\n" + "lldl %0, 0(%2)\n" +- "wr_f %3 \n" +- "xor %0, %5, %1\n" ++ "xor %0, %4, %1\n" + "lstl %1, 0(%2)\n" +- "rd_f %1 \n" + "beq %1, 2f\n" + + ".subsection 2\n\t" +@@ -998,10 +911,9 @@ + + : "=&r" (original), // %0 + "=&r" (modified), // %1 +- "=&r" (tmp1), // %2 +- "=&r" (tmp2) // %3 +- : "m" (storage), // %4 +- "r" (v) // %5 ++ "=&r" (tmp1) // %2 ++ : "m" (storage), // %3 ++ "r" (v) // %4 + : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC + ); + fence_after(order); diff --git a/ceph.spec b/ceph.spec index 7ed3a14..184bbef 100644 --- a/ceph.spec +++ b/ceph.spec @@ -125,7 +125,7 @@ ################################################################################# Name: ceph Version: 16.2.7 -Release: 21 +Release: 22 %if 0%{?fedora} || 0%{?rhel} || 0%{?openEuler} Epoch: 2 %endif @@ -159,6 +159,7 @@ Patch13: 0013-add-atomic-library-for-loongarch64.patch Patch14: 0014-fix-CVE-2022-3854.patch Patch15: 0015-Fix-CVE-2023-43040.patch Patch16: 0016-fix-CVE-2023-46159.patch +Patch17: 0017-ceph-Add-sw64-8A-architecture.patch %if 0%{?suse_version} # _insert_obs_source_lines_here ExclusiveArch: x86_64 aarch64 ppc64le s390x @@ -1221,6 +1222,7 @@ This package provides Ceph default alerts for Prometheus. %autosetup -p1 -n ceph-16.2.7 %ifnarch loongarch64 sw_64 +%patch17 -R -p1 %patch13 -R -p1 %patch8 -R -p1 %endif @@ -2505,6 +2507,9 @@ exit 0 %config %{_sysconfdir}/prometheus/ceph/ceph_default_alerts.yml %changelog +* Fri Sep 13 2024 wuzx - 2:16.2.7-22 +- add sw64-8A support + * Tue May 28 2024 fwind43 - 2:16.2.7-21 - fix error for cephfs subvolume -- Gitee