From 38919d66d8a9bb610f3c78d6b72c216d965dd091 Mon Sep 17 00:00:00 2001 From: dongji Date: Fri, 18 Jul 2025 22:13:14 +0800 Subject: [PATCH] Adds basic RISC-V support for isa-l-2.30.0, along with RISC-V64 platform CRC vector acceleration code implemented using the V, Zbc, Zvbc, and Zvbb extensions. Testing The verification method involves running autogen.sh and configure to generate the Makefile, followed by executing the make checks command. The verification results below were obtained on a RISC-V64 OpenEuler 24.03 virtual machine on QEMU 9.0.1 All tests successful. make --no-print-directory check-TESTS PASS: raid/pq_gen_test PASS: crc/crc16_t10dif_test PASS: crc/crc16_t10dif_copy_test PASS: raid/xor_gen_test PASS: crc/crc64_funcs_test PASS: crc/crc32_funcs_test PASS: igzip/igzip_wrapper_hdr_test PASS: igzip/checksum32_funcs_test PASS: erasure_code/gf_inverse_test PASS: erasure_code/gf_vect_mul_test PASS: raid/xor_check_test PASS: raid/pq_check_test PASS: igzip/igzip_rand_test PASS: mem/mem_zero_detect_test PASS: erasure_code/erasure_code_test PASS: erasure_code/erasure_code_update_test ============================================================================ Testsuite summary for libisal 2.30.0 ============================================================================ # TOTAL: 16 # PASS: 16 # SKIP: 0 # XFAIL: 0 # FAIL: 0 # XPASS: 0 # ERROR: 0 ============================================================================ Signed-off-by: liuqingtao (cherry picked from commit 906f064fd00c1cc73a55781ffc535ae2436c633a) --- ...-Basic-RISC-V-And-CRC-Vector-support.patch | 3759 +++++++++++++++++ isa-l.spec | 8 +- 2 files changed, 3766 insertions(+), 1 deletion(-) create mode 100644 Feature-Add-Basic-RISC-V-And-CRC-Vector-support.patch diff --git a/Feature-Add-Basic-RISC-V-And-CRC-Vector-support.patch b/Feature-Add-Basic-RISC-V-And-CRC-Vector-support.patch new file mode 100644 index 0000000..62518f4 --- /dev/null +++ b/Feature-Add-Basic-RISC-V-And-CRC-Vector-support.patch @@ -0,0 +1,3759 @@ +From 7aacf647b3dc52ea0a194add51104aea6909a492 Mon Sep 17 00:00:00 2001 +From: dongji +Date: Fri, 18 Jul 2025 20:34:49 +0800 +Subject: [PATCH] This PR adds basic RISC-V support for isa-l-2.30.0, along + with RISC-V64 platform CRC vector acceleration code implemented using the V, + Zbc, Zvbc, and Zvbb extensions. + + Testing The verification method involves + running autogen.sh and configure to generate the Makefile, followed by + executing the make checks command. The verification results below were + obtained on a RISC-V64 OpenEuler 24.03 virtual machine on QEMU 9.0.1 + + All tests successful. + make --no-print-directory check-TESTS + PASS: raid/pq_gen_test + PASS: crc/crc16_t10dif_test + PASS: crc/crc16_t10dif_copy_test + PASS: raid/xor_gen_test + PASS: crc/crc64_funcs_test + PASS: crc/crc32_funcs_test + PASS: igzip/igzip_wrapper_hdr_test + PASS: igzip/checksum32_funcs_test + PASS: erasure_code/gf_inverse_test + PASS: erasure_code/gf_vect_mul_test + PASS: raid/xor_check_test + PASS: raid/pq_check_test + PASS: igzip/igzip_rand_test + PASS: mem/mem_zero_detect_test + PASS: erasure_code/erasure_code_test + PASS: erasure_code/erasure_code_update_test + ============================================================================ + Testsuite summary for libisal 2.30.0 + ============================================================================ + # TOTAL: 16 + # PASS: 16 + # SKIP: 0 + # XFAIL: 0 + # FAIL: 0 + # XPASS: 0 + # ERROR: 0 + ============================================================================ + Signed-off-by: liuqingtao + +--- + Makefile.am | 20 ++ + configure.ac | 2 + + crc/Makefile.am | 3 +- + crc/riscv64/Makefile.am | 45 ++++ + crc/riscv64/crc16_t10dif_copy_vclmul.S | 298 +++++++++++++++++++++++++ + crc/riscv64/crc16_t10dif_vclmul.S | 279 +++++++++++++++++++++++ + crc/riscv64/crc32_gzip_refl_vclmul.S | 33 +++ + crc/riscv64/crc32_gzip_refl_vclmul.h | 84 +++++++ + crc/riscv64/crc32_ieee_norm_vclmul.S | 33 +++ + crc/riscv64/crc32_ieee_norm_vclmul.h | 84 +++++++ + crc/riscv64/crc32_iscsi_refl_vclmul.S | 56 +++++ + crc/riscv64/crc32_iscsi_refl_vclmul.h | 84 +++++++ + crc/riscv64/crc32_norm_common_vclmul.h | 111 +++++++++ + crc/riscv64/crc32_refl_common_vclmul.h | 112 ++++++++++ + crc/riscv64/crc64_ecma_norm_vclmul.S | 33 +++ + crc/riscv64/crc64_ecma_norm_vclmul.h | 179 +++++++++++++++ + crc/riscv64/crc64_ecma_refl_vclmul.S | 33 +++ + crc/riscv64/crc64_ecma_refl_vclmul.h | 179 +++++++++++++++ + crc/riscv64/crc64_iso_norm_vclmul.S | 33 +++ + crc/riscv64/crc64_iso_norm_vclmul.h | 179 +++++++++++++++ + crc/riscv64/crc64_iso_refl_vclmul.S | 33 +++ + crc/riscv64/crc64_iso_refl_vclmul.h | 179 +++++++++++++++ + crc/riscv64/crc64_jones_norm_vclmul.S | 33 +++ + crc/riscv64/crc64_jones_norm_vclmul.h | 179 +++++++++++++++ + crc/riscv64/crc64_jones_refl_vclmul.S | 33 +++ + crc/riscv64/crc64_jones_refl_vclmul.h | 179 +++++++++++++++ + crc/riscv64/crc64_norm_common_vclmul.h | 102 +++++++++ + crc/riscv64/crc64_refl_common_vclmul.h | 101 +++++++++ + crc/riscv64/crc_common_vclmul.h | 235 +++++++++++++++++++ + crc/riscv64/crc_multibinary_riscv.S | 42 ++++ + crc/riscv64/crc_riscv64_dispatcher.c | 169 ++++++++++++++ + erasure_code/Makefile.am | 2 +- + igzip/Makefile.am | 2 +- + include/riscv64_multibinary.h | 163 ++++++++++++++ + mem/Makefile.am | 2 +- + raid/Makefile.am | 2 +- + 36 files changed, 3330 insertions(+), 6 deletions(-) + create mode 100644 crc/riscv64/Makefile.am + create mode 100644 crc/riscv64/crc16_t10dif_copy_vclmul.S + create mode 100644 crc/riscv64/crc16_t10dif_vclmul.S + create mode 100644 crc/riscv64/crc32_gzip_refl_vclmul.S + create mode 100644 crc/riscv64/crc32_gzip_refl_vclmul.h + create mode 100644 crc/riscv64/crc32_ieee_norm_vclmul.S + create mode 100644 crc/riscv64/crc32_ieee_norm_vclmul.h + create mode 100644 crc/riscv64/crc32_iscsi_refl_vclmul.S + create mode 100644 crc/riscv64/crc32_iscsi_refl_vclmul.h + create mode 100644 crc/riscv64/crc32_norm_common_vclmul.h + create mode 100644 crc/riscv64/crc32_refl_common_vclmul.h + create mode 100644 crc/riscv64/crc64_ecma_norm_vclmul.S + create mode 100644 crc/riscv64/crc64_ecma_norm_vclmul.h + create mode 100644 crc/riscv64/crc64_ecma_refl_vclmul.S + create mode 100644 crc/riscv64/crc64_ecma_refl_vclmul.h + create mode 100644 crc/riscv64/crc64_iso_norm_vclmul.S + create mode 100644 crc/riscv64/crc64_iso_norm_vclmul.h + create mode 100644 crc/riscv64/crc64_iso_refl_vclmul.S + create mode 100644 crc/riscv64/crc64_iso_refl_vclmul.h + create mode 100644 crc/riscv64/crc64_jones_norm_vclmul.S + create mode 100644 crc/riscv64/crc64_jones_norm_vclmul.h + create mode 100644 crc/riscv64/crc64_jones_refl_vclmul.S + create mode 100644 crc/riscv64/crc64_jones_refl_vclmul.h + create mode 100644 crc/riscv64/crc64_norm_common_vclmul.h + create mode 100644 crc/riscv64/crc64_refl_common_vclmul.h + create mode 100644 crc/riscv64/crc_common_vclmul.h + create mode 100644 crc/riscv64/crc_multibinary_riscv.S + create mode 100644 crc/riscv64/crc_riscv64_dispatcher.c + create mode 100644 include/riscv64_multibinary.h + +diff --git a/Makefile.am b/Makefile.am +index 646b855..7602018 100644 +--- a/Makefile.am ++++ b/Makefile.am +@@ -28,10 +28,12 @@ other_tests_x86_64= + other_tests_x86_32= + other_tests_aarch64= + other_tests_ppc64le= ++other_tests_riscv64= + lsrc_x86_64= + lsrc_x86_32= + lsrc_aarch64= + lsrc_ppc64le= ++lsrc_riscv64= + lsrc_base_aliases= + lsrc32= + unit_tests32= +@@ -78,6 +80,12 @@ libisal_la_SOURCES += ${lsrc_ppc64le} + other_tests += ${other_tests_ppc64le} + endif + ++if CPU_RISCV64 ++ARCH=-Driscv64 ++libisal_la_SOURCES += ${lsrc_riscv64} ++other_tests += ${other_tests_riscv64} ++endif ++ + if CPU_UNDEFINED + libisal_la_SOURCES += ${lsrc_base_aliases} + endif +@@ -136,6 +144,10 @@ endif + endif + if CPU_AARCH64 + as_filter = $(CC) -D__ASSEMBLY__ ++else ++if CPU_RISCV64 ++ as_filter = $(CC) -D__ASSEMBLY__ ++endif + endif + + CCAS = $(as_filter) +@@ -146,8 +158,16 @@ AM_CFLAGS = ${my_CFLAGS} ${INCLUDE} $(src_include) ${D} + if CPU_AARCH64 + AM_CCASFLAGS = ${AM_CFLAGS} + else ++if CPU_RISCV64 ++AM_CCASFLAGS = ${AM_CFLAGS} ++else + AM_CCASFLAGS = ${yasm_args} ${INCLUDE} ${src_include} ${DEFS} ${D} + endif ++endif ++ ++if CPU_RISCV64 ++AM_CFLAGS += -march=rv64gcv_zbc_zvbc_zvbb ++endif + + .asm.s: + @echo " MKTMP " $@; +diff --git a/configure.ac b/configure.ac +index 8ca75ca..f69ae10 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -32,11 +32,13 @@ AS_CASE([$host_cpu], + [arm64], [CPU="aarch64"], + [powerpc64le], [CPU="ppc64le"], + [ppc64le], [CPU="ppc64le"], ++ [riscv64], [CPU="riscv64"], + ) + AM_CONDITIONAL([CPU_X86_64], [test "$CPU" = "x86_64"]) + AM_CONDITIONAL([CPU_X86_32], [test "$CPU" = "x86_32"]) + AM_CONDITIONAL([CPU_AARCH64], [test "$CPU" = "aarch64"]) + AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"]) ++AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"]) + AM_CONDITIONAL([CPU_UNDEFINED], [test "x$CPU" = "x"]) + + if test "$CPU" = "x86_64"; then +diff --git a/crc/Makefile.am b/crc/Makefile.am +index f12441c..05ff529 100644 +--- a/crc/Makefile.am ++++ b/crc/Makefile.am +@@ -28,7 +28,7 @@ + ######################################################################## + + include crc/aarch64/Makefile.am +- ++include crc/riscv64/Makefile.am + lsrc += \ + crc/crc_base.c \ + crc/crc64_base.c +@@ -36,7 +36,6 @@ lsrc += \ + lsrc_base_aliases += crc/crc_base_aliases.c + lsrc_x86_32 += crc/crc_base_aliases.c + lsrc_ppc64le += crc/crc_base_aliases.c +- + lsrc_x86_64 += \ + crc/crc16_t10dif_01.asm \ + crc/crc16_t10dif_by4.asm \ +diff --git a/crc/riscv64/Makefile.am b/crc/riscv64/Makefile.am +new file mode 100644 +index 0000000..37cb545 +--- /dev/null ++++ b/crc/riscv64/Makefile.am +@@ -0,0 +1,45 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++lsrc_riscv64 += \ ++ crc/riscv64/crc_multibinary_riscv.S \ ++ crc/riscv64/crc_riscv64_dispatcher.c ++ ++lsrc_riscv64 += \ ++ crc/riscv64/crc16_t10dif_vclmul.S \ ++ crc/riscv64/crc16_t10dif_copy_vclmul.S \ ++ crc/riscv64/crc32_ieee_norm_vclmul.S \ ++ crc/riscv64/crc32_iscsi_refl_vclmul.S \ ++ crc/riscv64/crc32_gzip_refl_vclmul.S \ ++ crc/riscv64/crc64_ecma_refl_vclmul.S \ ++ crc/riscv64/crc64_ecma_norm_vclmul.S \ ++ crc/riscv64/crc64_iso_refl_vclmul.S \ ++ crc/riscv64/crc64_iso_norm_vclmul.S \ ++ crc/riscv64/crc64_jones_refl_vclmul.S \ ++ crc/riscv64/crc64_jones_norm_vclmul.S +\ No newline at end of file +diff --git a/crc/riscv64/crc16_t10dif_copy_vclmul.S b/crc/riscv64/crc16_t10dif_copy_vclmul.S +new file mode 100644 +index 0000000..e3e7436 +--- /dev/null ++++ b/crc/riscv64/crc16_t10dif_copy_vclmul.S +@@ -0,0 +1,298 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.section .text ++.align 2 ++.global crc16_t10dif_copy_vclmul ++ ++# Arguments: ++# a0: uint16_t crc (seed) ++# a1: uint8_t *dst (pointer to data) ++# a2: uint8_t *src (pointer to data) ++# a3: size_t len (data length) ++ ++# Register usage: ++ ++crc16_t10dif_copy_vclmul: ++ # Initialize state ++ slli a0, a0, 16 ++ # Check if length >= 64 ++ li t1, 64 ++ bgeu a3, t1, .crc_fold ++ ++.crc_table_loop_pre: ++ beq a3, zero, .end ++ la a7, .LANCHOR0 ++ add a3, a3, a2 ++ ++.crc_table_loop: ++ lbu a4, 0(a2) ++ sb a4, 0(a1) ++ addi a2, a2, 1 ++ addi a1, a1, 1 ++ sllw a4, a4, 0x18 ++ xor a4, a4, a0 ++ srlw a5, a4, 0x18 ++ sll a5, a5, 0x2 ++ add a5, a5, a7 ++ lw a0, 0(a5) ++ sllw a4, a4, 0x8 ++ xor a0, a0, a4 ++ bne a2, a3, .crc_table_loop ++ ++.end: ++ slli a0, a0, 32 ++ srli a0, a0, 48 ++ ret ++ ++.crc_fold: ++ # Initialize vector registers ++ vsetivli zero, 2, e64, m1, ta, ma ++ vle64.v v6, 0(a2) ++ addi a2, a2, 16 ++ vle64.v v7, 0(a2) ++ addi a2, a2, 16 ++ vle64.v v8, 0(a2) ++ addi a2, a2, 16 ++ vle64.v v9, 0(a2) ++ addi a2, a2, 16 ++ addi a3, a3, -64 ++ ++ vse64.v v6, (a1) ++ addi a1, a1, 16 ++ vse64.v v7, (a1) ++ addi a1, a1, 16 ++ vse64.v v8, (a1) ++ addi a1, a1, 16 ++ vse64.v v9, (a1) ++ addi a1, a1, 16 ++ ++ # Prepare initial vector ++ slli a0, a0, 32 ++ vmv.s.x v4, zero ++ vrev8.v v6, v6 ++ vrev8.v v7, v7 ++ vrev8.v v8, v8 ++ vrev8.v v9, v9 ++ vslidedown.vi v0, v6, 1 ++ vslidedown.vi v1, v7, 1 ++ vslidedown.vi v2, v8, 1 ++ vslidedown.vi v3, v9, 1 ++ vslideup.vi v0, v6, 1 ++ vslideup.vi v1, v7, 1 ++ vslideup.vi v2, v8, 1 ++ vslideup.vi v3, v9, 1 ++ ++ vmv.v.x v5, a0 ++ vslideup.vi v4, v5, 1 ++ ++ vxor.vv v0, v0, v4 ++ ++ vmv.v.x v8, zero ++ bltu a3, t1, final_fold ++ ++ # Load constants ++ la t0, k_const1 ++ vle64.v v5, 0(t0) ++ ++ li t0, 64 ++ ++ # Main processing loop ++loop_start: ++ vle64.v v9, (a2) ++ addi a2, a2, 16 ++ vle64.v v10, (a2) ++ addi a2, a2, 16 ++ vle64.v v11, (a2) ++ addi a2, a2, 16 ++ vle64.v v12, (a2) ++ addi a2, a2, 16 ++ vse64.v v9, (a1) ++ addi a1, a1, 16 ++ vse64.v v10, (a1) ++ addi a1, a1, 16 ++ vse64.v v11, (a1) ++ addi a1, a1, 16 ++ vse64.v v12, (a1) ++ addi a1, a1, 16 ++ ++ vclmul.vv v4, v0, v5 ++ vclmulh.vv v0, v0, v5 ++ vredxor.vs v0, v0, v8 ++ vredxor.vs v4, v4, v8 ++ vslideup.vi v4, v0, 1 ++ vrev8.v v9, v9 ++ vslidedown.vi v6, v9, 1 ++ vslideup.vi v6, v9, 1 ++ vxor.vv v0, v4, v6 ++ ++ # Process v1-v3 (similar to v0) ++ ++ vclmul.vv v4, v1, v5 ++ vclmulh.vv v1, v1, v5 ++ vredxor.vs v1, v1, v8 ++ vredxor.vs v4, v4, v8 ++ vslideup.vi v4, v1, 1 ++ vrev8.v v10, v10 ++ vslidedown.vi v6, v10, 1 ++ vslideup.vi v6, v10, 1 ++ vxor.vv v1, v4, v6 ++ ++ vclmul.vv v4, v2, v5 ++ vclmulh.vv v2, v2, v5 ++ vredxor.vs v2, v2, v8 ++ vredxor.vs v4, v4, v8 ++ vslideup.vi v4, v2, 1 ++ vrev8.v v11, v11 ++ vslidedown.vi v6, v11, 1 ++ vslideup.vi v6, v11, 1 ++ vxor.vv v2, v4, v6 ++ ++ vclmul.vv v4, v3, v5 ++ vclmulh.vv v3, v3, v5 ++ vredxor.vs v3, v3, v8 ++ vredxor.vs v4, v4, v8 ++ vslideup.vi v4, v3, 1 ++ vrev8.v v12, v12 ++ vslidedown.vi v6, v12, 1 ++ vslideup.vi v6, v12, 1 ++ vxor.vv v3, v4, v6 ++ ++ addi a3, a3, -64 ++ bge a3, t0, loop_start ++ ++final_fold: ++ la t0, k_const2 ++ vle64.v v5, 0(t0) ++ vclmul.vv v6, v0, v5 ++ vclmulh.vv v7, v0, v5 ++ vredxor.vs v6, v6, v8 ++ vredxor.vs v7, v7, v8 ++ vslideup.vi v6, v7, 1 ++ vxor.vv v0, v6, v1 ++ vclmul.vv v6, v0, v5 ++ vclmulh.vv v7, v0, v5 ++ vredxor.vs v6, v6, v8 ++ vredxor.vs v7, v7, v8 ++ vslideup.vi v6, v7, 1 ++ vxor.vv v0, v6, v2 ++ vclmul.vv v6, v0, v5 ++ vclmulh.vv v7, v0, v5 ++ vredxor.vs v6, v6, v8 ++ vredxor.vs v7, v7, v8 ++ vslideup.vi v6, v7, 1 ++ vxor.vv v0, v6, v3 ++ ++ # Store result ++ addi sp, sp, -16 ++ vse64.v v0, (sp) ++ ++ # 128b -> 64b folding ++ ld t0, 0(sp) ++ ld t1, 8(sp) ++ li t2, 0x2d560000 ++ li t3, 0x13680000 ++ clmul a4, t1, t2 ++ clmulh a5, t1, t2 ++ slli a6, t0, 32 ++ srli a7, t0, 32 ++ xor a4, a4, a6 ++ xor a5, a5, a7 ++ clmul a5, a5, t3 ++ xor a4, a4, a5 ++ ++ # Barrett reduction ++ srli a5, a4, 32 ++ li t2, 0x1f65a57f9 # x_quo ++ clmul a5, t2, a5 ++ srli a5, a5, 32 ++ li t3, 0x18bb70000 # x_poly ++ clmul a5, a5, t3 ++ xor a0, a5, a4 ++ addi sp, sp, 16 ++ ++tail_processing: ++ # Process remaining bytes ++ beqz a3, .end ++ ++ # Call crc16_t10dif_generic equivalent for remaining bytes ++ jal x0, .crc_table_loop_pre ++ ++.section .rodata ++.align 4 ++initial_vector: ++ .quad 0x00000000 ++ .quad 0x00000000 ++ ++k_const1: ++ .quad 0x87e70000 ++ .quad 0x371d0000 ++ ++k_const2: ++ .quad 0xfb0b0000 ++ .quad 0x4c1a0000 ++ ++.LANCHOR0 = . + 0 ++ .type crc16tab, %object ++ .size crc16tab, 1024 ++crc16tab: ++ .word 0x00000000, 0x8bb70000, 0x9cd90000, 0x176e0000, 0xb2050000, 0x39b20000, 0x2edc0000, 0xa56b0000 ++ .word 0xefbd0000, 0x640a0000, 0x73640000, 0xf8d30000, 0x5db80000, 0xd60f0000, 0xc1610000, 0x4ad60000 ++ .word 0x54cd0000, 0xdf7a0000, 0xc8140000, 0x43a30000, 0xe6c80000, 0x6d7f0000, 0x7a110000, 0xf1a60000 ++ .word 0xbb700000, 0x30c70000, 0x27a90000, 0xac1e0000, 0x09750000, 0x82c20000, 0x95ac0000, 0x1e1b0000 ++ .word 0xa99a0000, 0x222d0000, 0x35430000, 0xbef40000, 0x1b9f0000, 0x90280000, 0x87460000, 0x0cf10000 ++ .word 0x46270000, 0xcd900000, 0xdafe0000, 0x51490000, 0xf4220000, 0x7f950000, 0x68fb0000, 0xe34c0000 ++ .word 0xfd570000, 0x76e00000, 0x618e0000, 0xea390000, 0x4f520000, 0xc4e50000, 0xd38b0000, 0x583c0000 ++ .word 0x12ea0000, 0x995d0000, 0x8e330000, 0x05840000, 0xa0ef0000, 0x2b580000, 0x3c360000, 0xb7810000 ++ .word 0xd8830000, 0x53340000, 0x445a0000, 0xcfed0000, 0x6a860000, 0xe1310000, 0xf65f0000, 0x7de80000 ++ .word 0x373e0000, 0xbc890000, 0xabe70000, 0x20500000, 0x853b0000, 0x0e8c0000, 0x19e20000, 0x92550000 ++ .word 0x8c4e0000, 0x07f90000, 0x10970000, 0x9b200000, 0x3e4b0000, 0xb5fc0000, 0xa2920000, 0x29250000 ++ .word 0x63f30000, 0xe8440000, 0xff2a0000, 0x749d0000, 0xd1f60000, 0x5a410000, 0x4d2f0000, 0xc6980000 ++ .word 0x71190000, 0xfaae0000, 0xedc00000, 0x66770000, 0xc31c0000, 0x48ab0000, 0x5fc50000, 0xd4720000 ++ .word 0x9ea40000, 0x15130000, 0x027d0000, 0x89ca0000, 0x2ca10000, 0xa7160000, 0xb0780000, 0x3bcf0000 ++ .word 0x25d40000, 0xae630000, 0xb90d0000, 0x32ba0000, 0x97d10000, 0x1c660000, 0x0b080000, 0x80bf0000 ++ .word 0xca690000, 0x41de0000, 0x56b00000, 0xdd070000, 0x786c0000, 0xf3db0000, 0xe4b50000, 0x6f020000 ++ .word 0x3ab10000, 0xb1060000, 0xa6680000, 0x2ddf0000, 0x88b40000, 0x03030000, 0x146d0000, 0x9fda0000 ++ .word 0xd50c0000, 0x5ebb0000, 0x49d50000, 0xc2620000, 0x67090000, 0xecbe0000, 0xfbd00000, 0x70670000 ++ .word 0x6e7c0000, 0xe5cb0000, 0xf2a50000, 0x79120000, 0xdc790000, 0x57ce0000, 0x40a00000, 0xcb170000 ++ .word 0x81c10000, 0x0a760000, 0x1d180000, 0x96af0000, 0x33c40000, 0xb8730000, 0xaf1d0000, 0x24aa0000 ++ .word 0x932b0000, 0x189c0000, 0x0ff20000, 0x84450000, 0x212e0000, 0xaa990000, 0xbdf70000, 0x36400000 ++ .word 0x7c960000, 0xf7210000, 0xe04f0000, 0x6bf80000, 0xce930000, 0x45240000, 0x524a0000, 0xd9fd0000 ++ .word 0xc7e60000, 0x4c510000, 0x5b3f0000, 0xd0880000, 0x75e30000, 0xfe540000, 0xe93a0000, 0x628d0000 ++ .word 0x285b0000, 0xa3ec0000, 0xb4820000, 0x3f350000, 0x9a5e0000, 0x11e90000, 0x06870000, 0x8d300000 ++ .word 0xe2320000, 0x69850000, 0x7eeb0000, 0xf55c0000, 0x50370000, 0xdb800000, 0xccee0000, 0x47590000 ++ .word 0x0d8f0000, 0x86380000, 0x91560000, 0x1ae10000, 0xbf8a0000, 0x343d0000, 0x23530000, 0xa8e40000 ++ .word 0xb6ff0000, 0x3d480000, 0x2a260000, 0xa1910000, 0x04fa0000, 0x8f4d0000, 0x98230000, 0x13940000 ++ .word 0x59420000, 0xd2f50000, 0xc59b0000, 0x4e2c0000, 0xeb470000, 0x60f00000, 0x779e0000, 0xfc290000 ++ .word 0x4ba80000, 0xc01f0000, 0xd7710000, 0x5cc60000, 0xf9ad0000, 0x721a0000, 0x65740000, 0xeec30000 ++ .word 0xa4150000, 0x2fa20000, 0x38cc0000, 0xb37b0000, 0x16100000, 0x9da70000, 0x8ac90000, 0x017e0000 ++ .word 0x1f650000, 0x94d20000, 0x83bc0000, 0x080b0000, 0xad600000, 0x26d70000, 0x31b90000, 0xba0e0000 ++ .word 0xf0d80000, 0x7b6f0000, 0x6c010000, 0xe7b60000, 0x42dd0000, 0xc96a0000, 0xde040000, 0x55b30000 ++ ++ +diff --git a/crc/riscv64/crc16_t10dif_vclmul.S b/crc/riscv64/crc16_t10dif_vclmul.S +new file mode 100644 +index 0000000..9f5bf0b +--- /dev/null ++++ b/crc/riscv64/crc16_t10dif_vclmul.S +@@ -0,0 +1,279 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.section .text ++.align 2 ++.global crc16_t10dif_vclmul ++ ++# Arguments: ++# a0: uint16_t crc (seed) ++# a1: uint8_t *buf (pointer to data) ++# a2: size_t len (data length) ++ ++# Register usage: ++ ++crc16_t10dif_vclmul: ++ # Initialize state ++ slli a0, a0, 16 # state = crc << 16 ++ ++ # Check if length >= 64 ++ li t1, 64 ++ bgeu a2, t1, .crc_fold ++ ++.crc_table_loop_pre: ++ beq a2, zero, .end ++ la a7, .LANCHOR0 ++ add a2, a2, a1 ++ ++.crc_table_loop: ++ lbu a4, 0(a1) ++ add a1, a1, 1 ++ sllw a4, a4, 0x18 ++ xor a4, a4, a0 ++ srlw a5, a4, 0x18 ++ sll a5, a5, 0x2 ++ add a5, a5, a7 ++ lw a0, 0(a5) ++ sllw a4, a4, 0x8 ++ xor a0, a0, a4 ++ bne a1, a2, .crc_table_loop ++ ++.end: ++ slli a0, a0, 32 ++ srli a0, a0, 48 ++ ret ++ ++.crc_fold: ++ # Initialize vector registers ++ vsetivli zero, 2, e64, m1, ta, ma ++ vle64.v v6, 0(a1) ++ addi a1, a1, 16 ++ vle64.v v7, 0(a1) ++ addi a1, a1, 16 ++ vle64.v v8, 0(a1) ++ addi a1, a1, 16 ++ vle64.v v9, 0(a1) ++ addi a1, a1, 16 ++ addi a2, a2, -64 ++ ++ # Prepare initial vector ++ slli a0, a0, 32 ++ vmv.s.x v4, zero ++ vrev8.v v6, v6 ++ vrev8.v v7, v7 ++ vrev8.v v8, v8 ++ vrev8.v v9, v9 ++ vslidedown.vi v0, v6, 1 ++ vslidedown.vi v1, v7, 1 ++ vslidedown.vi v2, v8, 1 ++ vslidedown.vi v3, v9, 1 ++ vslideup.vi v0, v6, 1 ++ vslideup.vi v1, v7, 1 ++ vslideup.vi v2, v8, 1 ++ vslideup.vi v3, v9, 1 ++ ++ vmv.v.x v5, a0 ++ vslideup.vi v4, v5, 1 ++ ++ vxor.vv v0, v0, v4 ++ ++ vmv.v.x v8, zero ++ bltu a2, t1, final_fold ++ ++ # Load constants ++ la t0, k_const1 ++ vle64.v v5, 0(t0) ++ ++ # Main processing loop ++loop_start: ++ vle64.v v9, (a1) ++ addi a1, a1, 16 ++ vle64.v v10, (a1) ++ addi a1, a1, 16 ++ vle64.v v11, (a1) ++ addi a1, a1, 16 ++ vle64.v v12, (a1) ++ addi a1, a1, 16 ++ ++ vclmul.vv v4, v0, v5 ++ vclmulh.vv v0, v0, v5 ++ vredxor.vs v0, v0, v8 ++ vredxor.vs v4, v4, v8 ++ vslideup.vi v4, v0, 1 ++ vrev8.v v9, v9 ++ vslidedown.vi v6, v9, 1 ++ vslideup.vi v6, v9, 1 ++ vxor.vv v0, v4, v6 ++ ++ # Process v1-v3 (similar to v0) ++ ++ vclmul.vv v4, v1, v5 ++ vclmulh.vv v1, v1, v5 ++ vredxor.vs v1, v1, v8 ++ vredxor.vs v4, v4, v8 ++ vslideup.vi v4, v1, 1 ++ vrev8.v v10, v10 ++ vslidedown.vi v6, v10, 1 ++ vslideup.vi v6, v10, 1 ++ vxor.vv v1, v4, v6 ++ ++ vclmul.vv v4, v2, v5 ++ vclmulh.vv v2, v2, v5 ++ vredxor.vs v2, v2, v8 ++ vredxor.vs v4, v4, v8 ++ vslideup.vi v4, v2, 1 ++ vrev8.v v11, v11 ++ vslidedown.vi v6, v11, 1 ++ vslideup.vi v6, v11, 1 ++ vxor.vv v2, v4, v6 ++ ++ vclmul.vv v4, v3, v5 ++ vclmulh.vv v3, v3, v5 ++ vredxor.vs v3, v3, v8 ++ vredxor.vs v4, v4, v8 ++ vslideup.vi v4, v3, 1 ++ vrev8.v v12, v12 ++ vslidedown.vi v6, v12, 1 ++ vslideup.vi v6, v12, 1 ++ vxor.vv v3, v4, v6 ++ ++ addi a2, a2, -64 ++ bge a2, t1, loop_start ++ ++final_fold: ++ la t0, k_const2 ++ vle64.v v5, 0(t0) ++ vclmul.vv v6, v0, v5 ++ vclmulh.vv v7, v0, v5 ++ vredxor.vs v6, v6, v8 ++ vredxor.vs v7, v7, v8 ++ vslideup.vi v6, v7, 1 ++ vxor.vv v0, v6, v1 ++ ++ vclmul.vv v6, v0, v5 ++ vclmulh.vv v7, v0, v5 ++ vredxor.vs v6, v6, v8 ++ vredxor.vs v7, v7, v8 ++ vslideup.vi v6, v7, 1 ++ vxor.vv v0, v6, v2 ++ ++ vclmul.vv v6, v0, v5 ++ vclmulh.vv v7, v0, v5 ++ vredxor.vs v6, v6, v8 ++ vredxor.vs v7, v7, v8 ++ vslideup.vi v6, v7, 1 ++ vxor.vv v0, v6, v3 ++ ++ # Store result ++ addi sp, sp, -16 ++ vse64.v v0, (sp) ++ ++ # 128b -> 64b folding ++ ld t0, 0(sp) ++ ld t1, 8(sp) ++ addi sp, sp, 16 ++ li t2, 0x2d560000 ++ li t4, 0x13680000 ++ clmul a4, t1, t2 ++ clmulh a5, t1, t2 ++ slli a6, t0, 32 ++ srli a7, t0, 32 ++ xor a4, a4, a6 ++ xor a5, a5, a7 ++ clmul a5, a5, t4 ++ xor a4, a4, a5 ++ ++ # Barrett reduction ++ srli a5, a4, 32 ++ li t2, 0x1f65a57f9 # x_quo ++ clmul a5, t2, a5 ++ srli a5, a5, 32 ++ li t4, 0x18bb70000 # x_poly ++ clmul a5, a5, t4 ++ xor a0, a5, a4 ++ ++tail_processing: ++ # Process remaining bytes ++ beqz a2, .end ++ ++ # Call crc16_t10dif_generic equivalent for remaining bytes ++ jal x0, .crc_table_loop_pre ++ ++.section .rodata ++.align 4 ++initial_vector: ++ .quad 0x00000000 ++ .quad 0x00000000 ++ ++k_const1: ++ .quad 0x87e70000 ++ .quad 0x371d0000 ++ ++k_const2: ++ .quad 0xfb0b0000 ++ .quad 0x4c1a0000 ++ ++.LANCHOR0 = . + 0 ++ .type crc16tab, %object ++ .size crc16tab, 1024 ++crc16tab: ++ .word 0x00000000, 0x8bb70000, 0x9cd90000, 0x176e0000, 0xb2050000, 0x39b20000, 0x2edc0000, 0xa56b0000 ++ .word 0xefbd0000, 0x640a0000, 0x73640000, 0xf8d30000, 0x5db80000, 0xd60f0000, 0xc1610000, 0x4ad60000 ++ .word 0x54cd0000, 0xdf7a0000, 0xc8140000, 0x43a30000, 0xe6c80000, 0x6d7f0000, 0x7a110000, 0xf1a60000 ++ .word 0xbb700000, 0x30c70000, 0x27a90000, 0xac1e0000, 0x09750000, 0x82c20000, 0x95ac0000, 0x1e1b0000 ++ .word 0xa99a0000, 0x222d0000, 0x35430000, 0xbef40000, 0x1b9f0000, 0x90280000, 0x87460000, 0x0cf10000 ++ .word 0x46270000, 0xcd900000, 0xdafe0000, 0x51490000, 0xf4220000, 0x7f950000, 0x68fb0000, 0xe34c0000 ++ .word 0xfd570000, 0x76e00000, 0x618e0000, 0xea390000, 0x4f520000, 0xc4e50000, 0xd38b0000, 0x583c0000 ++ .word 0x12ea0000, 0x995d0000, 0x8e330000, 0x05840000, 0xa0ef0000, 0x2b580000, 0x3c360000, 0xb7810000 ++ .word 0xd8830000, 0x53340000, 0x445a0000, 0xcfed0000, 0x6a860000, 0xe1310000, 0xf65f0000, 0x7de80000 ++ .word 0x373e0000, 0xbc890000, 0xabe70000, 0x20500000, 0x853b0000, 0x0e8c0000, 0x19e20000, 0x92550000 ++ .word 0x8c4e0000, 0x07f90000, 0x10970000, 0x9b200000, 0x3e4b0000, 0xb5fc0000, 0xa2920000, 0x29250000 ++ .word 0x63f30000, 0xe8440000, 0xff2a0000, 0x749d0000, 0xd1f60000, 0x5a410000, 0x4d2f0000, 0xc6980000 ++ .word 0x71190000, 0xfaae0000, 0xedc00000, 0x66770000, 0xc31c0000, 0x48ab0000, 0x5fc50000, 0xd4720000 ++ .word 0x9ea40000, 0x15130000, 0x027d0000, 0x89ca0000, 0x2ca10000, 0xa7160000, 0xb0780000, 0x3bcf0000 ++ .word 0x25d40000, 0xae630000, 0xb90d0000, 0x32ba0000, 0x97d10000, 0x1c660000, 0x0b080000, 0x80bf0000 ++ .word 0xca690000, 0x41de0000, 0x56b00000, 0xdd070000, 0x786c0000, 0xf3db0000, 0xe4b50000, 0x6f020000 ++ .word 0x3ab10000, 0xb1060000, 0xa6680000, 0x2ddf0000, 0x88b40000, 0x03030000, 0x146d0000, 0x9fda0000 ++ .word 0xd50c0000, 0x5ebb0000, 0x49d50000, 0xc2620000, 0x67090000, 0xecbe0000, 0xfbd00000, 0x70670000 ++ .word 0x6e7c0000, 0xe5cb0000, 0xf2a50000, 0x79120000, 0xdc790000, 0x57ce0000, 0x40a00000, 0xcb170000 ++ .word 0x81c10000, 0x0a760000, 0x1d180000, 0x96af0000, 0x33c40000, 0xb8730000, 0xaf1d0000, 0x24aa0000 ++ .word 0x932b0000, 0x189c0000, 0x0ff20000, 0x84450000, 0x212e0000, 0xaa990000, 0xbdf70000, 0x36400000 ++ .word 0x7c960000, 0xf7210000, 0xe04f0000, 0x6bf80000, 0xce930000, 0x45240000, 0x524a0000, 0xd9fd0000 ++ .word 0xc7e60000, 0x4c510000, 0x5b3f0000, 0xd0880000, 0x75e30000, 0xfe540000, 0xe93a0000, 0x628d0000 ++ .word 0x285b0000, 0xa3ec0000, 0xb4820000, 0x3f350000, 0x9a5e0000, 0x11e90000, 0x06870000, 0x8d300000 ++ .word 0xe2320000, 0x69850000, 0x7eeb0000, 0xf55c0000, 0x50370000, 0xdb800000, 0xccee0000, 0x47590000 ++ .word 0x0d8f0000, 0x86380000, 0x91560000, 0x1ae10000, 0xbf8a0000, 0x343d0000, 0x23530000, 0xa8e40000 ++ .word 0xb6ff0000, 0x3d480000, 0x2a260000, 0xa1910000, 0x04fa0000, 0x8f4d0000, 0x98230000, 0x13940000 ++ .word 0x59420000, 0xd2f50000, 0xc59b0000, 0x4e2c0000, 0xeb470000, 0x60f00000, 0x779e0000, 0xfc290000 ++ .word 0x4ba80000, 0xc01f0000, 0xd7710000, 0x5cc60000, 0xf9ad0000, 0x721a0000, 0x65740000, 0xeec30000 ++ .word 0xa4150000, 0x2fa20000, 0x38cc0000, 0xb37b0000, 0x16100000, 0x9da70000, 0x8ac90000, 0x017e0000 ++ .word 0x1f650000, 0x94d20000, 0x83bc0000, 0x080b0000, 0xad600000, 0x26d70000, 0x31b90000, 0xba0e0000 ++ .word 0xf0d80000, 0x7b6f0000, 0x6c010000, 0xe7b60000, 0x42dd0000, 0xc96a0000, 0xde040000, 0x55b30000 ++ ++ +diff --git a/crc/riscv64/crc32_gzip_refl_vclmul.S b/crc/riscv64/crc32_gzip_refl_vclmul.S +new file mode 100644 +index 0000000..4a32b7c +--- /dev/null ++++ b/crc/riscv64/crc32_gzip_refl_vclmul.S +@@ -0,0 +1,33 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc32_gzip_refl_vclmul.h" ++#include "crc32_refl_common_vclmul.h" ++ ++crc32_refl_func crc32_gzip_refl_vclmul +\ No newline at end of file +diff --git a/crc/riscv64/crc32_gzip_refl_vclmul.h b/crc/riscv64/crc32_gzip_refl_vclmul.h +new file mode 100644 +index 0000000..3fee53e +--- /dev/null ++++ b/crc/riscv64/crc32_gzip_refl_vclmul.h +@@ -0,0 +1,84 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.equ const_0, 0xb8bc6765 ++.equ const_1, 0xccaa009e ++.equ const_quo, 0x1f7011641 ++.equ const_poly, 0x1db710641 ++ ++ .section .rodata ++ .text ++ .align 3 ++ .set .crc_loop_const,. + 0 ++ .type const_2, %object ++ .size const_2, 16 ++const_2: ++ .quad 0x8f352d95 ++ .quad 0x1d9513d7 ++ .quad 0xae689191 ++ .quad 0xccaa009e ++ ++ .text ++ .align 4 ++ .set .lanchor_crc_tab,. + 0 ++ .type crc32_table_gzip_refl, %object ++ .size crc32_table_gzip_refl, 1024 ++crc32_table_gzip_refl: ++ .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3 ++ .word 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91 ++ .word 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7 ++ .word 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5 ++ .word 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b ++ .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59 ++ .word 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f ++ .word 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d ++ .word 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433 ++ .word 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 ++ .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457 ++ .word 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65 ++ .word 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb ++ .word 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9 ++ .word 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f ++ .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad ++ .word 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683 ++ .word 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1 ++ .word 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7 ++ .word 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 ++ .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b ++ .word 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79 ++ .word 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f ++ .word 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d ++ .word 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 ++ .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21 ++ .word 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777 ++ .word 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45 ++ .word 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db ++ .word 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 ++ .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf ++ .word 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +diff --git a/crc/riscv64/crc32_ieee_norm_vclmul.S b/crc/riscv64/crc32_ieee_norm_vclmul.S +new file mode 100644 +index 0000000..a909c7b +--- /dev/null ++++ b/crc/riscv64/crc32_ieee_norm_vclmul.S +@@ -0,0 +1,33 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc32_ieee_norm_vclmul.h" ++#include "crc32_norm_common_vclmul.h" ++ ++crc32_norm_func crc32_ieee_norm_vclmul +\ No newline at end of file +diff --git a/crc/riscv64/crc32_ieee_norm_vclmul.h b/crc/riscv64/crc32_ieee_norm_vclmul.h +new file mode 100644 +index 0000000..93443bf +--- /dev/null ++++ b/crc/riscv64/crc32_ieee_norm_vclmul.h +@@ -0,0 +1,84 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.equ const_0, 0xf200aa66 ++.equ const_1, 0x490d678d ++.equ const_quo, 0x104d101df ++.equ const_poly, 0x104c11db7 ++ ++ .section .rodata ++ .text ++ .align 4 ++ .set .crc_loop_const,. + 0 ++ .type const_2, %object ++ .size const_2, 32 ++const_2: ++ .quad 0xe6228b11 ++ .quad 0x8833794c ++ .quad 0xe8a45605 ++ .quad 0xc5b9cd4c ++ ++ .text ++ .align 4 ++ .set .lanchor_crc_tab,. + 0 ++ .type crc32_table_ieee_norm, %object ++ .size crc32_table_ieee_norm, 1024 ++crc32_table_ieee_norm: ++ .word 0x00000000, 0x04c11db7, 0x09823b6e, 0x0d4326d9, 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005 ++ .word 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd ++ .word 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75 ++ .word 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd ++ .word 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5 ++ .word 0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d ++ .word 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95 ++ .word 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d ++ .word 0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072 ++ .word 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, 0x018aeb13, 0x054bf6a4, 0x0808d07d, 0x0cc9cdca ++ .word 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02 ++ .word 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba ++ .word 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692 ++ .word 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a ++ .word 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2 ++ .word 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a ++ .word 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb ++ .word 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53 ++ .word 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b ++ .word 0x0315d626, 0x07d4cb91, 0x0a97ed48, 0x0e56f0ff, 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623 ++ .word 0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b ++ .word 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3 ++ .word 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b ++ .word 0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3 ++ .word 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c ++ .word 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24 ++ .word 0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, 0x029f3d35, 0x065e2082, 0x0b1d065b, 0x0fdc1bec ++ .word 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654 ++ .word 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c ++ .word 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4 ++ .word 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c ++ .word 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4 +diff --git a/crc/riscv64/crc32_iscsi_refl_vclmul.S b/crc/riscv64/crc32_iscsi_refl_vclmul.S +new file mode 100644 +index 0000000..3b5b355 +--- /dev/null ++++ b/crc/riscv64/crc32_iscsi_refl_vclmul.S +@@ -0,0 +1,56 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc32_iscsi_refl_vclmul.h" ++#include "crc32_refl_common_vclmul.h" ++ ++crc32_refl_func crc32_iscsi_refl_vclmul_internal ++ ++ .text ++ .align 3 ++ .global crc32_iscsi_refl_vclmul ++ .type crc32_iscsi_refl_vclmul, %function ++crc32_iscsi_refl_vclmul: ++ mv a7, a2 ++ sext.w a2, a1 ++ mv a1, a0 ++ mv a0, a7 ++ li t5, 0xffffffff ++ xori a0, a0, -1 ++ and a0, a0, t5 ++ addi sp, sp, -8 ++ sd ra, (sp) ++1: ++ auipc ra, %pcrel_hi(crc32_iscsi_refl_vclmul_internal) ++ jalr ra, %pcrel_lo(1b)(ra) ++ ld ra, (sp) ++ addi sp, sp, 8 ++ xori a0, a0, -1 ++ and a0, a0, t5 ++ ret +\ No newline at end of file +diff --git a/crc/riscv64/crc32_iscsi_refl_vclmul.h b/crc/riscv64/crc32_iscsi_refl_vclmul.h +new file mode 100644 +index 0000000..df87fdb +--- /dev/null ++++ b/crc/riscv64/crc32_iscsi_refl_vclmul.h +@@ -0,0 +1,84 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.equ const_0, 0xdd45aab8 ++.equ const_1, 0x493c7d27 ++.equ const_quo, 0x0dea713f1 ++.equ const_poly, 0x105ec76f1 ++ ++ .section .rodata ++ .text ++ .align 3 ++ .set .crc_loop_const,. + 0 ++ .type const_2, %object ++ .size const_2, 16 ++const_2: ++ .quad 0x740eef02 ++ .quad 0x9e4addf8 ++ .quad 0xf20c0dfe ++ .quad 0x493c7d27 ++ ++ .text ++ .align 4 ++ .set .lanchor_crc_tab,. + 0 ++ .type crc32_table_iscsi_refl, %object ++ .size crc32_table_iscsi_refl, 1024 ++crc32_table_iscsi_refl: ++ .word 0x00000000, 0xF26B8303, 0xE13B70F7, 0x1350F3F4, 0xC79A971F, 0x35F1141C, 0x26A1E7E8, 0xD4CA64EB ++ .word 0x8AD958CF, 0x78B2DBCC, 0x6BE22838, 0x9989AB3B, 0x4D43CFD0, 0xBF284CD3, 0xAC78BF27, 0x5E133C24 ++ .word 0x105EC76F, 0xE235446C, 0xF165B798, 0x030E349B, 0xD7C45070, 0x25AFD373, 0x36FF2087, 0xC494A384 ++ .word 0x9A879FA0, 0x68EC1CA3, 0x7BBCEF57, 0x89D76C54, 0x5D1D08BF, 0xAF768BBC, 0xBC267848, 0x4E4DFB4B ++ .word 0x20BD8EDE, 0xD2D60DDD, 0xC186FE29, 0x33ED7D2A, 0xE72719C1, 0x154C9AC2, 0x061C6936, 0xF477EA35 ++ .word 0xAA64D611, 0x580F5512, 0x4B5FA6E6, 0xB93425E5, 0x6DFE410E, 0x9F95C20D, 0x8CC531F9, 0x7EAEB2FA ++ .word 0x30E349B1, 0xC288CAB2, 0xD1D83946, 0x23B3BA45, 0xF779DEAE, 0x05125DAD, 0x1642AE59, 0xE4292D5A ++ .word 0xBA3A117E, 0x4851927D, 0x5B016189, 0xA96AE28A, 0x7DA08661, 0x8FCB0562, 0x9C9BF696, 0x6EF07595 ++ .word 0x417B1DBC, 0xB3109EBF, 0xA0406D4B, 0x522BEE48, 0x86E18AA3, 0x748A09A0, 0x67DAFA54, 0x95B17957 ++ .word 0xCBA24573, 0x39C9C670, 0x2A993584, 0xD8F2B687, 0x0C38D26C, 0xFE53516F, 0xED03A29B, 0x1F682198 ++ .word 0x5125DAD3, 0xA34E59D0, 0xB01EAA24, 0x42752927, 0x96BF4DCC, 0x64D4CECF, 0x77843D3B, 0x85EFBE38 ++ .word 0xDBFC821C, 0x2997011F, 0x3AC7F2EB, 0xC8AC71E8, 0x1C661503, 0xEE0D9600, 0xFD5D65F4, 0x0F36E6F7 ++ .word 0x61C69362, 0x93AD1061, 0x80FDE395, 0x72966096, 0xA65C047D, 0x5437877E, 0x4767748A, 0xB50CF789 ++ .word 0xEB1FCBAD, 0x197448AE, 0x0A24BB5A, 0xF84F3859, 0x2C855CB2, 0xDEEEDFB1, 0xCDBE2C45, 0x3FD5AF46 ++ .word 0x7198540D, 0x83F3D70E, 0x90A324FA, 0x62C8A7F9, 0xB602C312, 0x44694011, 0x5739B3E5, 0xA55230E6 ++ .word 0xFB410CC2, 0x092A8FC1, 0x1A7A7C35, 0xE811FF36, 0x3CDB9BDD, 0xCEB018DE, 0xDDE0EB2A, 0x2F8B6829 ++ .word 0x82F63B78, 0x709DB87B, 0x63CD4B8F, 0x91A6C88C, 0x456CAC67, 0xB7072F64, 0xA457DC90, 0x563C5F93 ++ .word 0x082F63B7, 0xFA44E0B4, 0xE9141340, 0x1B7F9043, 0xCFB5F4A8, 0x3DDE77AB, 0x2E8E845F, 0xDCE5075C ++ .word 0x92A8FC17, 0x60C37F14, 0x73938CE0, 0x81F80FE3, 0x55326B08, 0xA759E80B, 0xB4091BFF, 0x466298FC ++ .word 0x1871A4D8, 0xEA1A27DB, 0xF94AD42F, 0x0B21572C, 0xDFEB33C7, 0x2D80B0C4, 0x3ED04330, 0xCCBBC033 ++ .word 0xA24BB5A6, 0x502036A5, 0x4370C551, 0xB11B4652, 0x65D122B9, 0x97BAA1BA, 0x84EA524E, 0x7681D14D ++ .word 0x2892ED69, 0xDAF96E6A, 0xC9A99D9E, 0x3BC21E9D, 0xEF087A76, 0x1D63F975, 0x0E330A81, 0xFC588982 ++ .word 0xB21572C9, 0x407EF1CA, 0x532E023E, 0xA145813D, 0x758FE5D6, 0x87E466D5, 0x94B49521, 0x66DF1622 ++ .word 0x38CC2A06, 0xCAA7A905, 0xD9F75AF1, 0x2B9CD9F2, 0xFF56BD19, 0x0D3D3E1A, 0x1E6DCDEE, 0xEC064EED ++ .word 0xC38D26C4, 0x31E6A5C7, 0x22B65633, 0xD0DDD530, 0x0417B1DB, 0xF67C32D8, 0xE52CC12C, 0x1747422F ++ .word 0x49547E0B, 0xBB3FFD08, 0xA86F0EFC, 0x5A048DFF, 0x8ECEE914, 0x7CA56A17, 0x6FF599E3, 0x9D9E1AE0 ++ .word 0xD3D3E1AB, 0x21B862A8, 0x32E8915C, 0xC083125F, 0x144976B4, 0xE622F5B7, 0xF5720643, 0x07198540 ++ .word 0x590AB964, 0xAB613A67, 0xB831C993, 0x4A5A4A90, 0x9E902E7B, 0x6CFBAD78, 0x7FAB5E8C, 0x8DC0DD8F ++ .word 0xE330A81A, 0x115B2B19, 0x020BD8ED, 0xF0605BEE, 0x24AA3F05, 0xD6C1BC06, 0xC5914FF2, 0x37FACCF1 ++ .word 0x69E9F0D5, 0x9B8273D6, 0x88D28022, 0x7AB90321, 0xAE7367CA, 0x5C18E4C9, 0x4F48173D, 0xBD23943E ++ .word 0xF36E6F75, 0x0105EC76, 0x12551F82, 0xE03E9C81, 0x34F4F86A, 0xC69F7B69, 0xD5CF889D, 0x27A40B9E ++ .word 0x79B737BA, 0x8BDCB4B9, 0x988C474D, 0x6AE7C44E, 0xBE2DA0A5, 0x4C4623A6, 0x5F16D052, 0xAD7D5351 +diff --git a/crc/riscv64/crc32_norm_common_vclmul.h b/crc/riscv64/crc32_norm_common_vclmul.h +new file mode 100644 +index 0000000..54b009d +--- /dev/null ++++ b/crc/riscv64/crc32_norm_common_vclmul.h +@@ -0,0 +1,111 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc_common_vclmul.h" ++ ++.macro crc32_norm_func name ++ .text ++ .align 3 ++ .type \name, @function ++ .global \name ++\name: ++ xori seed, seed, -1 ++ li counter, 0 ++ li tmp_1, 64 ++ bgeu len, tmp_1, .crc_clmul_pre ++ ++.crc_tab_pre: ++ bgeu counter, len, .done ++ la crc_tab_addr, .lanchor_crc_tab ++ add buf_iter, buf, counter ++ add buf, buf, len ++ ++ .align 3 ++.loop_crc_tab: ++ lbu tmp_1, 0(buf_iter) ++ addi buf_iter, buf_iter, 1 ++ sllw tmp_1, tmp_1, 0x18 ++ xor tmp_1, tmp_1, seed ++ srlw tmp, tmp_1, 0x18 ++ sll tmp, tmp, 0x2 ++ add tmp, tmp, crc_tab_addr ++ lw seed, 0(tmp) ++ sllw tmp_1, tmp_1, 0x8 ++ xor seed, seed, tmp_1 ++ bne buf_iter, buf, .loop_crc_tab ++ ++.done: ++ xori seed, seed, -1 ++ sext.w seed, seed ++ ret ++ ++ .align 2 ++.crc_clmul_pre: ++ vsetivli zero, 2, e64, m1, ta, ma ++ slli seed, seed, 32 ++ ++ crc_norm_load_first_block ++ vmv.s.x vec_zero, zero ++ crc_load_p4 ++ addi tmp_0, len, -64 ++ bltu tmp_0, tmp_1, .clmul_loop_end ++ ++ crc_norm_loop ++ ++.clmul_loop_end: ++ addi tmp_4, tmp_4, 16 ++ crc_fold_512b_to_128b ++ ++ addi sp, sp, -16 ++ vse64.v vec_0, (sp) ++ ld tmp_0, 0(sp) ++ ld tmp_1, 8(sp) ++ addi sp, sp, 16 ++ li tmp_2, const_0 ++ li tmp_3, const_1 ++ clmul tmp_4, tmp_1, tmp_2 ++ clmulh tmp_5, tmp_1, tmp_2 ++ slli tmp_1, tmp_0, 32 ++ srli tmp_2, tmp_0, 32 ++ xor tmp_4, tmp_4, tmp_1 ++ xor tmp_5, tmp_5, tmp_2 ++ clmul tmp_5, tmp_5, tmp_3 ++ xor tmp_4, tmp_4, tmp_5 ++ ++ srli tmp_1, tmp_4, 32 ++ li tmp_2, const_quo # quo ++ clmul tmp_1, tmp_2, tmp_1 ++ srli tmp_1, tmp_1, 32 ++ li tmp_3, const_poly # poly ++ clmul tmp_1, tmp_1, tmp_3 ++ xor seed, tmp_1, tmp_4 ++ ++ j .crc_tab_pre ++ .size \name, .-\name ++.endm +\ No newline at end of file +diff --git a/crc/riscv64/crc32_refl_common_vclmul.h b/crc/riscv64/crc32_refl_common_vclmul.h +new file mode 100644 +index 0000000..9493a8a +--- /dev/null ++++ b/crc/riscv64/crc32_refl_common_vclmul.h +@@ -0,0 +1,112 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc_common_vclmul.h" ++ ++.macro crc32_refl_func name ++ .text ++ .align 3 ++ .type \name, @function ++ .global \name ++\name: ++ xori seed, seed, -1 ++ li tmp_5, 0xffffffff ++ and seed, seed, tmp_5 ++ li counter, 0 ++ li tmp_1, 64 ++ bgeu len, tmp_1, .crc_clmul_pre ++ ++.crc_tab_pre: ++ bgeu counter, len, .done ++ la crc_tab_addr, .lanchor_crc_tab ++ add buf_iter, buf, counter ++ add buf, buf, len ++ ++ .align 3 ++.loop_crc_tab: ++ lbu tmp_1, 0(buf_iter) ++ addi buf_iter, buf_iter, 1 ++ xor tmp_1, seed, tmp_1 ++ zext.b tmp, tmp_1 ++ slli tmp, tmp, 0x2 ++ add tmp, tmp, crc_tab_addr ++ lw seed, 0(tmp) ++ srliw tmp_1, tmp_1, 0x8 ++ xor seed, seed, tmp_1 ++ ++ bne buf_iter, buf, .loop_crc_tab ++ ++.done: ++ xori seed, seed, -1 ++ sext.w seed, seed ++ ret ++ ++ .align 2 ++.crc_clmul_pre: ++ vsetivli zero, 2, e64, m1, ta, ma ++ crc_refl_load_first_block ++ vmv.s.x vec_zero, zero ++ crc_load_p4 ++ addi tmp_0, len, -64 ++ bltu tmp_0, tmp_1, .clmul_loop_end ++ ++ crc_refl_loop ++ ++.clmul_loop_end: ++ addi tmp_4, tmp_4, 16 ++ crc_fold_512b_to_128b ++ ++ addi sp, sp, -16 ++ vse64.v vec_0, (sp) ++ ld tmp_0, 0(sp) ++ ld tmp_1, 8(sp) ++ addi sp, sp, 16 ++ li tmp_2, const_0 ++ li tmp_3, const_1 ++ clmul tmp_4, tmp_0, tmp_3 ++ clmulh tmp_3, tmp_0, tmp_3 ++ xor tmp_1, tmp_1, tmp_4 ++ and tmp_4, tmp_1, tmp_5 ++ srli tmp_1, tmp_1, 0x20 ++ clmul tmp_0, tmp_4, tmp_2 ++ slli tmp_3, tmp_3, 0x20 ++ xor tmp_3, tmp_3, tmp_1 ++ xor tmp_3, tmp_3, tmp_0 ++ and tmp_4, tmp_3, tmp_5 ++ li tmp_2, const_quo ++ li tmp_1, const_poly ++ clmul tmp_4, tmp_4, tmp_2 ++ and tmp_4, tmp_4, tmp_5 ++ clmul tmp_4, tmp_4, tmp_1 ++ xor tmp_4, tmp_3, tmp_4 ++ srai seed, tmp_4, 0x20 ++ ++ j .crc_tab_pre ++ .size \name, .-\name ++.endm +\ No newline at end of file +diff --git a/crc/riscv64/crc64_ecma_norm_vclmul.S b/crc/riscv64/crc64_ecma_norm_vclmul.S +new file mode 100644 +index 0000000..b0ec7ce +--- /dev/null ++++ b/crc/riscv64/crc64_ecma_norm_vclmul.S +@@ -0,0 +1,33 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc64_ecma_norm_vclmul.h" ++#include "crc64_norm_common_vclmul.h" ++ ++crc64_norm_func crc64_ecma_norm_vclmul +\ No newline at end of file +diff --git a/crc/riscv64/crc64_ecma_norm_vclmul.h b/crc/riscv64/crc64_ecma_norm_vclmul.h +new file mode 100644 +index 0000000..7e4fe07 +--- /dev/null ++++ b/crc/riscv64/crc64_ecma_norm_vclmul.h +@@ -0,0 +1,179 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.equ const_0, 0x05f5c3c7eb52fab6 ++.equ const_quo, 0x578d29d06cc4f872 ++.equ const_poly, 0x42F0E1EBA9EA3693 ++ ++ .section .rodata ++ .text ++ .align 4 ++ .set .crc_loop_const,. + 0 ++ .type const_2, %object ++ .size const_2, 64 ++const_2: ++ .quad 0x5f6843ca540df020 ++ .quad 0xddf4b6981205b83f ++ .quad 0x05f5c3c7eb52fab6 ++ .quad 0x4eb938a7d257740e ++ ++ .text ++ .align 4 ++ .set .lanchor_crc_tab,. + 0 ++ .type crc64_table_ecma_norm, %object ++ .size crc64_table_ecma_norm, 2048 ++crc64_table_ecma_norm: ++ .dword 0x0000000000000000, 0x42f0e1eba9ea3693 ++ .dword 0x85e1c3d753d46d26, 0xc711223cfa3e5bb5 ++ .dword 0x493366450e42ecdf, 0x0bc387aea7a8da4c ++ .dword 0xccd2a5925d9681f9, 0x8e224479f47cb76a ++ .dword 0x9266cc8a1c85d9be, 0xd0962d61b56fef2d ++ .dword 0x17870f5d4f51b498, 0x5577eeb6e6bb820b ++ .dword 0xdb55aacf12c73561, 0x99a54b24bb2d03f2 ++ .dword 0x5eb4691841135847, 0x1c4488f3e8f96ed4 ++ .dword 0x663d78ff90e185ef, 0x24cd9914390bb37c ++ .dword 0xe3dcbb28c335e8c9, 0xa12c5ac36adfde5a ++ .dword 0x2f0e1eba9ea36930, 0x6dfeff5137495fa3 ++ .dword 0xaaefdd6dcd770416, 0xe81f3c86649d3285 ++ .dword 0xf45bb4758c645c51, 0xb6ab559e258e6ac2 ++ .dword 0x71ba77a2dfb03177, 0x334a9649765a07e4 ++ .dword 0xbd68d2308226b08e, 0xff9833db2bcc861d ++ .dword 0x388911e7d1f2dda8, 0x7a79f00c7818eb3b ++ .dword 0xcc7af1ff21c30bde, 0x8e8a101488293d4d ++ .dword 0x499b3228721766f8, 0x0b6bd3c3dbfd506b ++ .dword 0x854997ba2f81e701, 0xc7b97651866bd192 ++ .dword 0x00a8546d7c558a27, 0x4258b586d5bfbcb4 ++ .dword 0x5e1c3d753d46d260, 0x1cecdc9e94ace4f3 ++ .dword 0xdbfdfea26e92bf46, 0x990d1f49c77889d5 ++ .dword 0x172f5b3033043ebf, 0x55dfbadb9aee082c ++ .dword 0x92ce98e760d05399, 0xd03e790cc93a650a ++ .dword 0xaa478900b1228e31, 0xe8b768eb18c8b8a2 ++ .dword 0x2fa64ad7e2f6e317, 0x6d56ab3c4b1cd584 ++ .dword 0xe374ef45bf6062ee, 0xa1840eae168a547d ++ .dword 0x66952c92ecb40fc8, 0x2465cd79455e395b ++ .dword 0x3821458aada7578f, 0x7ad1a461044d611c ++ .dword 0xbdc0865dfe733aa9, 0xff3067b657990c3a ++ .dword 0x711223cfa3e5bb50, 0x33e2c2240a0f8dc3 ++ .dword 0xf4f3e018f031d676, 0xb60301f359dbe0e5 ++ .dword 0xda050215ea6c212f, 0x98f5e3fe438617bc ++ .dword 0x5fe4c1c2b9b84c09, 0x1d14202910527a9a ++ .dword 0x93366450e42ecdf0, 0xd1c685bb4dc4fb63 ++ .dword 0x16d7a787b7faa0d6, 0x5427466c1e109645 ++ .dword 0x4863ce9ff6e9f891, 0x0a932f745f03ce02 ++ .dword 0xcd820d48a53d95b7, 0x8f72eca30cd7a324 ++ .dword 0x0150a8daf8ab144e, 0x43a04931514122dd ++ .dword 0x84b16b0dab7f7968, 0xc6418ae602954ffb ++ .dword 0xbc387aea7a8da4c0, 0xfec89b01d3679253 ++ .dword 0x39d9b93d2959c9e6, 0x7b2958d680b3ff75 ++ .dword 0xf50b1caf74cf481f, 0xb7fbfd44dd257e8c ++ .dword 0x70eadf78271b2539, 0x321a3e938ef113aa ++ .dword 0x2e5eb66066087d7e, 0x6cae578bcfe24bed ++ .dword 0xabbf75b735dc1058, 0xe94f945c9c3626cb ++ .dword 0x676dd025684a91a1, 0x259d31cec1a0a732 ++ .dword 0xe28c13f23b9efc87, 0xa07cf2199274ca14 ++ .dword 0x167ff3eacbaf2af1, 0x548f120162451c62 ++ .dword 0x939e303d987b47d7, 0xd16ed1d631917144 ++ .dword 0x5f4c95afc5edc62e, 0x1dbc74446c07f0bd ++ .dword 0xdaad56789639ab08, 0x985db7933fd39d9b ++ .dword 0x84193f60d72af34f, 0xc6e9de8b7ec0c5dc ++ .dword 0x01f8fcb784fe9e69, 0x43081d5c2d14a8fa ++ .dword 0xcd2a5925d9681f90, 0x8fdab8ce70822903 ++ .dword 0x48cb9af28abc72b6, 0x0a3b7b1923564425 ++ .dword 0x70428b155b4eaf1e, 0x32b26afef2a4998d ++ .dword 0xf5a348c2089ac238, 0xb753a929a170f4ab ++ .dword 0x3971ed50550c43c1, 0x7b810cbbfce67552 ++ .dword 0xbc902e8706d82ee7, 0xfe60cf6caf321874 ++ .dword 0xe224479f47cb76a0, 0xa0d4a674ee214033 ++ .dword 0x67c58448141f1b86, 0x253565a3bdf52d15 ++ .dword 0xab1721da49899a7f, 0xe9e7c031e063acec ++ .dword 0x2ef6e20d1a5df759, 0x6c0603e6b3b7c1ca ++ .dword 0xf6fae5c07d3274cd, 0xb40a042bd4d8425e ++ .dword 0x731b26172ee619eb, 0x31ebc7fc870c2f78 ++ .dword 0xbfc9838573709812, 0xfd39626eda9aae81 ++ .dword 0x3a28405220a4f534, 0x78d8a1b9894ec3a7 ++ .dword 0x649c294a61b7ad73, 0x266cc8a1c85d9be0 ++ .dword 0xe17dea9d3263c055, 0xa38d0b769b89f6c6 ++ .dword 0x2daf4f0f6ff541ac, 0x6f5faee4c61f773f ++ .dword 0xa84e8cd83c212c8a, 0xeabe6d3395cb1a19 ++ .dword 0x90c79d3fedd3f122, 0xd2377cd44439c7b1 ++ .dword 0x15265ee8be079c04, 0x57d6bf0317edaa97 ++ .dword 0xd9f4fb7ae3911dfd, 0x9b041a914a7b2b6e ++ .dword 0x5c1538adb04570db, 0x1ee5d94619af4648 ++ .dword 0x02a151b5f156289c, 0x4051b05e58bc1e0f ++ .dword 0x87409262a28245ba, 0xc5b073890b687329 ++ .dword 0x4b9237f0ff14c443, 0x0962d61b56fef2d0 ++ .dword 0xce73f427acc0a965, 0x8c8315cc052a9ff6 ++ .dword 0x3a80143f5cf17f13, 0x7870f5d4f51b4980 ++ .dword 0xbf61d7e80f251235, 0xfd913603a6cf24a6 ++ .dword 0x73b3727a52b393cc, 0x31439391fb59a55f ++ .dword 0xf652b1ad0167feea, 0xb4a25046a88dc879 ++ .dword 0xa8e6d8b54074a6ad, 0xea16395ee99e903e ++ .dword 0x2d071b6213a0cb8b, 0x6ff7fa89ba4afd18 ++ .dword 0xe1d5bef04e364a72, 0xa3255f1be7dc7ce1 ++ .dword 0x64347d271de22754, 0x26c49cccb40811c7 ++ .dword 0x5cbd6cc0cc10fafc, 0x1e4d8d2b65facc6f ++ .dword 0xd95caf179fc497da, 0x9bac4efc362ea149 ++ .dword 0x158e0a85c2521623, 0x577eeb6e6bb820b0 ++ .dword 0x906fc95291867b05, 0xd29f28b9386c4d96 ++ .dword 0xcedba04ad0952342, 0x8c2b41a1797f15d1 ++ .dword 0x4b3a639d83414e64, 0x09ca82762aab78f7 ++ .dword 0x87e8c60fded7cf9d, 0xc51827e4773df90e ++ .dword 0x020905d88d03a2bb, 0x40f9e43324e99428 ++ .dword 0x2cffe7d5975e55e2, 0x6e0f063e3eb46371 ++ .dword 0xa91e2402c48a38c4, 0xebeec5e96d600e57 ++ .dword 0x65cc8190991cb93d, 0x273c607b30f68fae ++ .dword 0xe02d4247cac8d41b, 0xa2dda3ac6322e288 ++ .dword 0xbe992b5f8bdb8c5c, 0xfc69cab42231bacf ++ .dword 0x3b78e888d80fe17a, 0x7988096371e5d7e9 ++ .dword 0xf7aa4d1a85996083, 0xb55aacf12c735610 ++ .dword 0x724b8ecdd64d0da5, 0x30bb6f267fa73b36 ++ .dword 0x4ac29f2a07bfd00d, 0x08327ec1ae55e69e ++ .dword 0xcf235cfd546bbd2b, 0x8dd3bd16fd818bb8 ++ .dword 0x03f1f96f09fd3cd2, 0x41011884a0170a41 ++ .dword 0x86103ab85a2951f4, 0xc4e0db53f3c36767 ++ .dword 0xd8a453a01b3a09b3, 0x9a54b24bb2d03f20 ++ .dword 0x5d45907748ee6495, 0x1fb5719ce1045206 ++ .dword 0x919735e51578e56c, 0xd367d40ebc92d3ff ++ .dword 0x1476f63246ac884a, 0x568617d9ef46bed9 ++ .dword 0xe085162ab69d5e3c, 0xa275f7c11f7768af ++ .dword 0x6564d5fde549331a, 0x279434164ca30589 ++ .dword 0xa9b6706fb8dfb2e3, 0xeb46918411358470 ++ .dword 0x2c57b3b8eb0bdfc5, 0x6ea7525342e1e956 ++ .dword 0x72e3daa0aa188782, 0x30133b4b03f2b111 ++ .dword 0xf7021977f9cceaa4, 0xb5f2f89c5026dc37 ++ .dword 0x3bd0bce5a45a6b5d, 0x79205d0e0db05dce ++ .dword 0xbe317f32f78e067b, 0xfcc19ed95e6430e8 ++ .dword 0x86b86ed5267cdbd3, 0xc4488f3e8f96ed40 ++ .dword 0x0359ad0275a8b6f5, 0x41a94ce9dc428066 ++ .dword 0xcf8b0890283e370c, 0x8d7be97b81d4019f ++ .dword 0x4a6acb477bea5a2a, 0x089a2aacd2006cb9 ++ .dword 0x14dea25f3af9026d, 0x562e43b4931334fe ++ .dword 0x913f6188692d6f4b, 0xd3cf8063c0c759d8 ++ .dword 0x5dedc41a34bbeeb2, 0x1f1d25f19d51d821 ++ .dword 0xd80c07cd676f8394, 0x9afce626ce85b507 +\ No newline at end of file +diff --git a/crc/riscv64/crc64_ecma_refl_vclmul.S b/crc/riscv64/crc64_ecma_refl_vclmul.S +new file mode 100644 +index 0000000..3dc92a5 +--- /dev/null ++++ b/crc/riscv64/crc64_ecma_refl_vclmul.S +@@ -0,0 +1,33 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc64_ecma_refl_vclmul.h" ++#include "crc64_refl_common_vclmul.h" ++ ++crc64_refl_func crc64_ecma_refl_vclmul +\ No newline at end of file +diff --git a/crc/riscv64/crc64_ecma_refl_vclmul.h b/crc/riscv64/crc64_ecma_refl_vclmul.h +new file mode 100644 +index 0000000..a3d7632 +--- /dev/null ++++ b/crc/riscv64/crc64_ecma_refl_vclmul.h +@@ -0,0 +1,179 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.equ const_0, 0xdabe95afc7875f40 ++.equ const_quo, 0x9c3e466c172963d5 ++.equ const_poly, 0x92d8af2baf0e1e85 ++ ++ .section .rodata ++ .text ++ .align 3 ++ .set .crc_loop_const,. + 0 ++ .type const_2, %object ++ .size const_2, 64 ++const_2: ++ .quad 0x6ae3efbb9dd441f3 ++ .quad 0x081f6054a7842df4 ++ .quad 0xe05dd497ca393ae4 ++ .quad 0xdabe95afc7875f40 ++ ++ .text ++ .align 4 ++ .set .lanchor_crc_tab,. + 0 ++ .type crc64_table_ecma_refl, %object ++ .size crc64_table_ecma_refl, 2048 ++crc64_table_ecma_refl: ++ .dword 0x0000000000000000, 0xb32e4cbe03a75f6f ++ .dword 0xf4843657a840a05b, 0x47aa7ae9abe7ff34 ++ .dword 0x7bd0c384ff8f5e33, 0xc8fe8f3afc28015c ++ .dword 0x8f54f5d357cffe68, 0x3c7ab96d5468a107 ++ .dword 0xf7a18709ff1ebc66, 0x448fcbb7fcb9e309 ++ .dword 0x0325b15e575e1c3d, 0xb00bfde054f94352 ++ .dword 0x8c71448d0091e255, 0x3f5f08330336bd3a ++ .dword 0x78f572daa8d1420e, 0xcbdb3e64ab761d61 ++ .dword 0x7d9ba13851336649, 0xceb5ed8652943926 ++ .dword 0x891f976ff973c612, 0x3a31dbd1fad4997d ++ .dword 0x064b62bcaebc387a, 0xb5652e02ad1b6715 ++ .dword 0xf2cf54eb06fc9821, 0x41e11855055bc74e ++ .dword 0x8a3a2631ae2dda2f, 0x39146a8fad8a8540 ++ .dword 0x7ebe1066066d7a74, 0xcd905cd805ca251b ++ .dword 0xf1eae5b551a2841c, 0x42c4a90b5205db73 ++ .dword 0x056ed3e2f9e22447, 0xb6409f5cfa457b28 ++ .dword 0xfb374270a266cc92, 0x48190ecea1c193fd ++ .dword 0x0fb374270a266cc9, 0xbc9d3899098133a6 ++ .dword 0x80e781f45de992a1, 0x33c9cd4a5e4ecdce ++ .dword 0x7463b7a3f5a932fa, 0xc74dfb1df60e6d95 ++ .dword 0x0c96c5795d7870f4, 0xbfb889c75edf2f9b ++ .dword 0xf812f32ef538d0af, 0x4b3cbf90f69f8fc0 ++ .dword 0x774606fda2f72ec7, 0xc4684a43a15071a8 ++ .dword 0x83c230aa0ab78e9c, 0x30ec7c140910d1f3 ++ .dword 0x86ace348f355aadb, 0x3582aff6f0f2f5b4 ++ .dword 0x7228d51f5b150a80, 0xc10699a158b255ef ++ .dword 0xfd7c20cc0cdaf4e8, 0x4e526c720f7dab87 ++ .dword 0x09f8169ba49a54b3, 0xbad65a25a73d0bdc ++ .dword 0x710d64410c4b16bd, 0xc22328ff0fec49d2 ++ .dword 0x85895216a40bb6e6, 0x36a71ea8a7ace989 ++ .dword 0x0adda7c5f3c4488e, 0xb9f3eb7bf06317e1 ++ .dword 0xfe5991925b84e8d5, 0x4d77dd2c5823b7ba ++ .dword 0x64b62bcaebc387a1, 0xd7986774e864d8ce ++ .dword 0x90321d9d438327fa, 0x231c512340247895 ++ .dword 0x1f66e84e144cd992, 0xac48a4f017eb86fd ++ .dword 0xebe2de19bc0c79c9, 0x58cc92a7bfab26a6 ++ .dword 0x9317acc314dd3bc7, 0x2039e07d177a64a8 ++ .dword 0x67939a94bc9d9b9c, 0xd4bdd62abf3ac4f3 ++ .dword 0xe8c76f47eb5265f4, 0x5be923f9e8f53a9b ++ .dword 0x1c4359104312c5af, 0xaf6d15ae40b59ac0 ++ .dword 0x192d8af2baf0e1e8, 0xaa03c64cb957be87 ++ .dword 0xeda9bca512b041b3, 0x5e87f01b11171edc ++ .dword 0x62fd4976457fbfdb, 0xd1d305c846d8e0b4 ++ .dword 0x96797f21ed3f1f80, 0x2557339fee9840ef ++ .dword 0xee8c0dfb45ee5d8e, 0x5da24145464902e1 ++ .dword 0x1a083bacedaefdd5, 0xa9267712ee09a2ba ++ .dword 0x955cce7fba6103bd, 0x267282c1b9c65cd2 ++ .dword 0x61d8f8281221a3e6, 0xd2f6b4961186fc89 ++ .dword 0x9f8169ba49a54b33, 0x2caf25044a02145c ++ .dword 0x6b055fede1e5eb68, 0xd82b1353e242b407 ++ .dword 0xe451aa3eb62a1500, 0x577fe680b58d4a6f ++ .dword 0x10d59c691e6ab55b, 0xa3fbd0d71dcdea34 ++ .dword 0x6820eeb3b6bbf755, 0xdb0ea20db51ca83a ++ .dword 0x9ca4d8e41efb570e, 0x2f8a945a1d5c0861 ++ .dword 0x13f02d374934a966, 0xa0de61894a93f609 ++ .dword 0xe7741b60e174093d, 0x545a57dee2d35652 ++ .dword 0xe21ac88218962d7a, 0x5134843c1b317215 ++ .dword 0x169efed5b0d68d21, 0xa5b0b26bb371d24e ++ .dword 0x99ca0b06e7197349, 0x2ae447b8e4be2c26 ++ .dword 0x6d4e3d514f59d312, 0xde6071ef4cfe8c7d ++ .dword 0x15bb4f8be788911c, 0xa6950335e42fce73 ++ .dword 0xe13f79dc4fc83147, 0x521135624c6f6e28 ++ .dword 0x6e6b8c0f1807cf2f, 0xdd45c0b11ba09040 ++ .dword 0x9aefba58b0476f74, 0x29c1f6e6b3e0301b ++ .dword 0xc96c5795d7870f42, 0x7a421b2bd420502d ++ .dword 0x3de861c27fc7af19, 0x8ec62d7c7c60f076 ++ .dword 0xb2bc941128085171, 0x0192d8af2baf0e1e ++ .dword 0x4638a2468048f12a, 0xf516eef883efae45 ++ .dword 0x3ecdd09c2899b324, 0x8de39c222b3eec4b ++ .dword 0xca49e6cb80d9137f, 0x7967aa75837e4c10 ++ .dword 0x451d1318d716ed17, 0xf6335fa6d4b1b278 ++ .dword 0xb199254f7f564d4c, 0x02b769f17cf11223 ++ .dword 0xb4f7f6ad86b4690b, 0x07d9ba1385133664 ++ .dword 0x4073c0fa2ef4c950, 0xf35d8c442d53963f ++ .dword 0xcf273529793b3738, 0x7c0979977a9c6857 ++ .dword 0x3ba3037ed17b9763, 0x888d4fc0d2dcc80c ++ .dword 0x435671a479aad56d, 0xf0783d1a7a0d8a02 ++ .dword 0xb7d247f3d1ea7536, 0x04fc0b4dd24d2a59 ++ .dword 0x3886b22086258b5e, 0x8ba8fe9e8582d431 ++ .dword 0xcc0284772e652b05, 0x7f2cc8c92dc2746a ++ .dword 0x325b15e575e1c3d0, 0x8175595b76469cbf ++ .dword 0xc6df23b2dda1638b, 0x75f16f0cde063ce4 ++ .dword 0x498bd6618a6e9de3, 0xfaa59adf89c9c28c ++ .dword 0xbd0fe036222e3db8, 0x0e21ac88218962d7 ++ .dword 0xc5fa92ec8aff7fb6, 0x76d4de52895820d9 ++ .dword 0x317ea4bb22bfdfed, 0x8250e80521188082 ++ .dword 0xbe2a516875702185, 0x0d041dd676d77eea ++ .dword 0x4aae673fdd3081de, 0xf9802b81de97deb1 ++ .dword 0x4fc0b4dd24d2a599, 0xfceef8632775faf6 ++ .dword 0xbb44828a8c9205c2, 0x086ace348f355aad ++ .dword 0x34107759db5dfbaa, 0x873e3be7d8faa4c5 ++ .dword 0xc094410e731d5bf1, 0x73ba0db070ba049e ++ .dword 0xb86133d4dbcc19ff, 0x0b4f7f6ad86b4690 ++ .dword 0x4ce50583738cb9a4, 0xffcb493d702be6cb ++ .dword 0xc3b1f050244347cc, 0x709fbcee27e418a3 ++ .dword 0x3735c6078c03e797, 0x841b8ab98fa4b8f8 ++ .dword 0xadda7c5f3c4488e3, 0x1ef430e13fe3d78c ++ .dword 0x595e4a08940428b8, 0xea7006b697a377d7 ++ .dword 0xd60abfdbc3cbd6d0, 0x6524f365c06c89bf ++ .dword 0x228e898c6b8b768b, 0x91a0c532682c29e4 ++ .dword 0x5a7bfb56c35a3485, 0xe955b7e8c0fd6bea ++ .dword 0xaeffcd016b1a94de, 0x1dd181bf68bdcbb1 ++ .dword 0x21ab38d23cd56ab6, 0x9285746c3f7235d9 ++ .dword 0xd52f0e859495caed, 0x6601423b97329582 ++ .dword 0xd041dd676d77eeaa, 0x636f91d96ed0b1c5 ++ .dword 0x24c5eb30c5374ef1, 0x97eba78ec690119e ++ .dword 0xab911ee392f8b099, 0x18bf525d915feff6 ++ .dword 0x5f1528b43ab810c2, 0xec3b640a391f4fad ++ .dword 0x27e05a6e926952cc, 0x94ce16d091ce0da3 ++ .dword 0xd3646c393a29f297, 0x604a2087398eadf8 ++ .dword 0x5c3099ea6de60cff, 0xef1ed5546e415390 ++ .dword 0xa8b4afbdc5a6aca4, 0x1b9ae303c601f3cb ++ .dword 0x56ed3e2f9e224471, 0xe5c372919d851b1e ++ .dword 0xa26908783662e42a, 0x114744c635c5bb45 ++ .dword 0x2d3dfdab61ad1a42, 0x9e13b115620a452d ++ .dword 0xd9b9cbfcc9edba19, 0x6a978742ca4ae576 ++ .dword 0xa14cb926613cf817, 0x1262f598629ba778 ++ .dword 0x55c88f71c97c584c, 0xe6e6c3cfcadb0723 ++ .dword 0xda9c7aa29eb3a624, 0x69b2361c9d14f94b ++ .dword 0x2e184cf536f3067f, 0x9d36004b35545910 ++ .dword 0x2b769f17cf112238, 0x9858d3a9ccb67d57 ++ .dword 0xdff2a94067518263, 0x6cdce5fe64f6dd0c ++ .dword 0x50a65c93309e7c0b, 0xe388102d33392364 ++ .dword 0xa4226ac498dedc50, 0x170c267a9b79833f ++ .dword 0xdcd7181e300f9e5e, 0x6ff954a033a8c131 ++ .dword 0x28532e49984f3e05, 0x9b7d62f79be8616a ++ .dword 0xa707db9acf80c06d, 0x14299724cc279f02 ++ .dword 0x5383edcd67c06036, 0xe0ada17364673f59 +diff --git a/crc/riscv64/crc64_iso_norm_vclmul.S b/crc/riscv64/crc64_iso_norm_vclmul.S +new file mode 100644 +index 0000000..93f1290 +--- /dev/null ++++ b/crc/riscv64/crc64_iso_norm_vclmul.S +@@ -0,0 +1,33 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc64_iso_norm_vclmul.h" ++#include "crc64_norm_common_vclmul.h" ++ ++crc64_norm_func crc64_iso_norm_vclmul +\ No newline at end of file +diff --git a/crc/riscv64/crc64_iso_norm_vclmul.h b/crc/riscv64/crc64_iso_norm_vclmul.h +new file mode 100644 +index 0000000..3fe52ef +--- /dev/null ++++ b/crc/riscv64/crc64_iso_norm_vclmul.h +@@ -0,0 +1,179 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.equ const_0, 0x0000000000000145 ++.equ const_quo, 0x000000000000001b ++.equ const_poly, 0x000000000000001b ++ ++ .section .rodata ++ .text ++ .align 3 ++ .set .crc_loop_const,. + 0 ++ .type const_2, %object ++ .size const_2, 64 ++const_2: ++ .quad 0x0000000101000101 ++ .quad 0x0000001b1b001b1b ++ .quad 0x0000000000000145 ++ .quad 0x0000000000001db7 ++ ++ .text ++ .align 4 ++ .set .lanchor_crc_tab,. + 0 ++ .type crc64_table_iso_norm, %object ++ .size crc64_table_iso_norm, 2048 ++crc64_table_iso_norm: ++ .dword 0x0000000000000000, 0x000000000000001b ++ .dword 0x0000000000000036, 0x000000000000002d ++ .dword 0x000000000000006c, 0x0000000000000077 ++ .dword 0x000000000000005a, 0x0000000000000041 ++ .dword 0x00000000000000d8, 0x00000000000000c3 ++ .dword 0x00000000000000ee, 0x00000000000000f5 ++ .dword 0x00000000000000b4, 0x00000000000000af ++ .dword 0x0000000000000082, 0x0000000000000099 ++ .dword 0x00000000000001b0, 0x00000000000001ab ++ .dword 0x0000000000000186, 0x000000000000019d ++ .dword 0x00000000000001dc, 0x00000000000001c7 ++ .dword 0x00000000000001ea, 0x00000000000001f1 ++ .dword 0x0000000000000168, 0x0000000000000173 ++ .dword 0x000000000000015e, 0x0000000000000145 ++ .dword 0x0000000000000104, 0x000000000000011f ++ .dword 0x0000000000000132, 0x0000000000000129 ++ .dword 0x0000000000000360, 0x000000000000037b ++ .dword 0x0000000000000356, 0x000000000000034d ++ .dword 0x000000000000030c, 0x0000000000000317 ++ .dword 0x000000000000033a, 0x0000000000000321 ++ .dword 0x00000000000003b8, 0x00000000000003a3 ++ .dword 0x000000000000038e, 0x0000000000000395 ++ .dword 0x00000000000003d4, 0x00000000000003cf ++ .dword 0x00000000000003e2, 0x00000000000003f9 ++ .dword 0x00000000000002d0, 0x00000000000002cb ++ .dword 0x00000000000002e6, 0x00000000000002fd ++ .dword 0x00000000000002bc, 0x00000000000002a7 ++ .dword 0x000000000000028a, 0x0000000000000291 ++ .dword 0x0000000000000208, 0x0000000000000213 ++ .dword 0x000000000000023e, 0x0000000000000225 ++ .dword 0x0000000000000264, 0x000000000000027f ++ .dword 0x0000000000000252, 0x0000000000000249 ++ .dword 0x00000000000006c0, 0x00000000000006db ++ .dword 0x00000000000006f6, 0x00000000000006ed ++ .dword 0x00000000000006ac, 0x00000000000006b7 ++ .dword 0x000000000000069a, 0x0000000000000681 ++ .dword 0x0000000000000618, 0x0000000000000603 ++ .dword 0x000000000000062e, 0x0000000000000635 ++ .dword 0x0000000000000674, 0x000000000000066f ++ .dword 0x0000000000000642, 0x0000000000000659 ++ .dword 0x0000000000000770, 0x000000000000076b ++ .dword 0x0000000000000746, 0x000000000000075d ++ .dword 0x000000000000071c, 0x0000000000000707 ++ .dword 0x000000000000072a, 0x0000000000000731 ++ .dword 0x00000000000007a8, 0x00000000000007b3 ++ .dword 0x000000000000079e, 0x0000000000000785 ++ .dword 0x00000000000007c4, 0x00000000000007df ++ .dword 0x00000000000007f2, 0x00000000000007e9 ++ .dword 0x00000000000005a0, 0x00000000000005bb ++ .dword 0x0000000000000596, 0x000000000000058d ++ .dword 0x00000000000005cc, 0x00000000000005d7 ++ .dword 0x00000000000005fa, 0x00000000000005e1 ++ .dword 0x0000000000000578, 0x0000000000000563 ++ .dword 0x000000000000054e, 0x0000000000000555 ++ .dword 0x0000000000000514, 0x000000000000050f ++ .dword 0x0000000000000522, 0x0000000000000539 ++ .dword 0x0000000000000410, 0x000000000000040b ++ .dword 0x0000000000000426, 0x000000000000043d ++ .dword 0x000000000000047c, 0x0000000000000467 ++ .dword 0x000000000000044a, 0x0000000000000451 ++ .dword 0x00000000000004c8, 0x00000000000004d3 ++ .dword 0x00000000000004fe, 0x00000000000004e5 ++ .dword 0x00000000000004a4, 0x00000000000004bf ++ .dword 0x0000000000000492, 0x0000000000000489 ++ .dword 0x0000000000000d80, 0x0000000000000d9b ++ .dword 0x0000000000000db6, 0x0000000000000dad ++ .dword 0x0000000000000dec, 0x0000000000000df7 ++ .dword 0x0000000000000dda, 0x0000000000000dc1 ++ .dword 0x0000000000000d58, 0x0000000000000d43 ++ .dword 0x0000000000000d6e, 0x0000000000000d75 ++ .dword 0x0000000000000d34, 0x0000000000000d2f ++ .dword 0x0000000000000d02, 0x0000000000000d19 ++ .dword 0x0000000000000c30, 0x0000000000000c2b ++ .dword 0x0000000000000c06, 0x0000000000000c1d ++ .dword 0x0000000000000c5c, 0x0000000000000c47 ++ .dword 0x0000000000000c6a, 0x0000000000000c71 ++ .dword 0x0000000000000ce8, 0x0000000000000cf3 ++ .dword 0x0000000000000cde, 0x0000000000000cc5 ++ .dword 0x0000000000000c84, 0x0000000000000c9f ++ .dword 0x0000000000000cb2, 0x0000000000000ca9 ++ .dword 0x0000000000000ee0, 0x0000000000000efb ++ .dword 0x0000000000000ed6, 0x0000000000000ecd ++ .dword 0x0000000000000e8c, 0x0000000000000e97 ++ .dword 0x0000000000000eba, 0x0000000000000ea1 ++ .dword 0x0000000000000e38, 0x0000000000000e23 ++ .dword 0x0000000000000e0e, 0x0000000000000e15 ++ .dword 0x0000000000000e54, 0x0000000000000e4f ++ .dword 0x0000000000000e62, 0x0000000000000e79 ++ .dword 0x0000000000000f50, 0x0000000000000f4b ++ .dword 0x0000000000000f66, 0x0000000000000f7d ++ .dword 0x0000000000000f3c, 0x0000000000000f27 ++ .dword 0x0000000000000f0a, 0x0000000000000f11 ++ .dword 0x0000000000000f88, 0x0000000000000f93 ++ .dword 0x0000000000000fbe, 0x0000000000000fa5 ++ .dword 0x0000000000000fe4, 0x0000000000000fff ++ .dword 0x0000000000000fd2, 0x0000000000000fc9 ++ .dword 0x0000000000000b40, 0x0000000000000b5b ++ .dword 0x0000000000000b76, 0x0000000000000b6d ++ .dword 0x0000000000000b2c, 0x0000000000000b37 ++ .dword 0x0000000000000b1a, 0x0000000000000b01 ++ .dword 0x0000000000000b98, 0x0000000000000b83 ++ .dword 0x0000000000000bae, 0x0000000000000bb5 ++ .dword 0x0000000000000bf4, 0x0000000000000bef ++ .dword 0x0000000000000bc2, 0x0000000000000bd9 ++ .dword 0x0000000000000af0, 0x0000000000000aeb ++ .dword 0x0000000000000ac6, 0x0000000000000add ++ .dword 0x0000000000000a9c, 0x0000000000000a87 ++ .dword 0x0000000000000aaa, 0x0000000000000ab1 ++ .dword 0x0000000000000a28, 0x0000000000000a33 ++ .dword 0x0000000000000a1e, 0x0000000000000a05 ++ .dword 0x0000000000000a44, 0x0000000000000a5f ++ .dword 0x0000000000000a72, 0x0000000000000a69 ++ .dword 0x0000000000000820, 0x000000000000083b ++ .dword 0x0000000000000816, 0x000000000000080d ++ .dword 0x000000000000084c, 0x0000000000000857 ++ .dword 0x000000000000087a, 0x0000000000000861 ++ .dword 0x00000000000008f8, 0x00000000000008e3 ++ .dword 0x00000000000008ce, 0x00000000000008d5 ++ .dword 0x0000000000000894, 0x000000000000088f ++ .dword 0x00000000000008a2, 0x00000000000008b9 ++ .dword 0x0000000000000990, 0x000000000000098b ++ .dword 0x00000000000009a6, 0x00000000000009bd ++ .dword 0x00000000000009fc, 0x00000000000009e7 ++ .dword 0x00000000000009ca, 0x00000000000009d1 ++ .dword 0x0000000000000948, 0x0000000000000953 ++ .dword 0x000000000000097e, 0x0000000000000965 ++ .dword 0x0000000000000924, 0x000000000000093f ++ .dword 0x0000000000000912, 0x0000000000000909 +diff --git a/crc/riscv64/crc64_iso_refl_vclmul.S b/crc/riscv64/crc64_iso_refl_vclmul.S +new file mode 100644 +index 0000000..9e3a9b8 +--- /dev/null ++++ b/crc/riscv64/crc64_iso_refl_vclmul.S +@@ -0,0 +1,33 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc64_iso_refl_vclmul.h" ++#include "crc64_refl_common_vclmul.h" ++ ++crc64_refl_func crc64_iso_refl_vclmul +\ No newline at end of file +diff --git a/crc/riscv64/crc64_iso_refl_vclmul.h b/crc/riscv64/crc64_iso_refl_vclmul.h +new file mode 100644 +index 0000000..5b2ad8c +--- /dev/null ++++ b/crc/riscv64/crc64_iso_refl_vclmul.h +@@ -0,0 +1,179 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.equ const_0, 0xf500000000000001 ++.equ const_quo, 0xb000000000000001 ++.equ const_poly, 0xb000000000000001 ++ ++ .section .rodata ++ .text ++ .align 3 ++ .set .crc_loop_const,. + 0 ++ .type const_2, %object ++ .size const_2, 64 ++const_2: ++ .quad 0x01b001b1b0000001 ++ .quad 0xb100010100000001 ++ .quad 0x6b70000000000001 ++ .quad 0xf500000000000001 ++ ++ .text ++ .align 4 ++ .set .lanchor_crc_tab,. + 0 ++ .type crc64_table_iso_refl, %object ++ .size crc64_table_iso_refl, 2048 ++crc64_table_iso_refl: ++ .dword 0x0000000000000000, 0x01b0000000000000 ++ .dword 0x0360000000000000, 0x02d0000000000000 ++ .dword 0x06c0000000000000, 0x0770000000000000 ++ .dword 0x05a0000000000000, 0x0410000000000000 ++ .dword 0x0d80000000000000, 0x0c30000000000000 ++ .dword 0x0ee0000000000000, 0x0f50000000000000 ++ .dword 0x0b40000000000000, 0x0af0000000000000 ++ .dword 0x0820000000000000, 0x0990000000000000 ++ .dword 0x1b00000000000000, 0x1ab0000000000000 ++ .dword 0x1860000000000000, 0x19d0000000000000 ++ .dword 0x1dc0000000000000, 0x1c70000000000000 ++ .dword 0x1ea0000000000000, 0x1f10000000000000 ++ .dword 0x1680000000000000, 0x1730000000000000 ++ .dword 0x15e0000000000000, 0x1450000000000000 ++ .dword 0x1040000000000000, 0x11f0000000000000 ++ .dword 0x1320000000000000, 0x1290000000000000 ++ .dword 0x3600000000000000, 0x37b0000000000000 ++ .dword 0x3560000000000000, 0x34d0000000000000 ++ .dword 0x30c0000000000000, 0x3170000000000000 ++ .dword 0x33a0000000000000, 0x3210000000000000 ++ .dword 0x3b80000000000000, 0x3a30000000000000 ++ .dword 0x38e0000000000000, 0x3950000000000000 ++ .dword 0x3d40000000000000, 0x3cf0000000000000 ++ .dword 0x3e20000000000000, 0x3f90000000000000 ++ .dword 0x2d00000000000000, 0x2cb0000000000000 ++ .dword 0x2e60000000000000, 0x2fd0000000000000 ++ .dword 0x2bc0000000000000, 0x2a70000000000000 ++ .dword 0x28a0000000000000, 0x2910000000000000 ++ .dword 0x2080000000000000, 0x2130000000000000 ++ .dword 0x23e0000000000000, 0x2250000000000000 ++ .dword 0x2640000000000000, 0x27f0000000000000 ++ .dword 0x2520000000000000, 0x2490000000000000 ++ .dword 0x6c00000000000000, 0x6db0000000000000 ++ .dword 0x6f60000000000000, 0x6ed0000000000000 ++ .dword 0x6ac0000000000000, 0x6b70000000000000 ++ .dword 0x69a0000000000000, 0x6810000000000000 ++ .dword 0x6180000000000000, 0x6030000000000000 ++ .dword 0x62e0000000000000, 0x6350000000000000 ++ .dword 0x6740000000000000, 0x66f0000000000000 ++ .dword 0x6420000000000000, 0x6590000000000000 ++ .dword 0x7700000000000000, 0x76b0000000000000 ++ .dword 0x7460000000000000, 0x75d0000000000000 ++ .dword 0x71c0000000000000, 0x7070000000000000 ++ .dword 0x72a0000000000000, 0x7310000000000000 ++ .dword 0x7a80000000000000, 0x7b30000000000000 ++ .dword 0x79e0000000000000, 0x7850000000000000 ++ .dword 0x7c40000000000000, 0x7df0000000000000 ++ .dword 0x7f20000000000000, 0x7e90000000000000 ++ .dword 0x5a00000000000000, 0x5bb0000000000000 ++ .dword 0x5960000000000000, 0x58d0000000000000 ++ .dword 0x5cc0000000000000, 0x5d70000000000000 ++ .dword 0x5fa0000000000000, 0x5e10000000000000 ++ .dword 0x5780000000000000, 0x5630000000000000 ++ .dword 0x54e0000000000000, 0x5550000000000000 ++ .dword 0x5140000000000000, 0x50f0000000000000 ++ .dword 0x5220000000000000, 0x5390000000000000 ++ .dword 0x4100000000000000, 0x40b0000000000000 ++ .dword 0x4260000000000000, 0x43d0000000000000 ++ .dword 0x47c0000000000000, 0x4670000000000000 ++ .dword 0x44a0000000000000, 0x4510000000000000 ++ .dword 0x4c80000000000000, 0x4d30000000000000 ++ .dword 0x4fe0000000000000, 0x4e50000000000000 ++ .dword 0x4a40000000000000, 0x4bf0000000000000 ++ .dword 0x4920000000000000, 0x4890000000000000 ++ .dword 0xd800000000000000, 0xd9b0000000000000 ++ .dword 0xdb60000000000000, 0xdad0000000000000 ++ .dword 0xdec0000000000000, 0xdf70000000000000 ++ .dword 0xdda0000000000000, 0xdc10000000000000 ++ .dword 0xd580000000000000, 0xd430000000000000 ++ .dword 0xd6e0000000000000, 0xd750000000000000 ++ .dword 0xd340000000000000, 0xd2f0000000000000 ++ .dword 0xd020000000000000, 0xd190000000000000 ++ .dword 0xc300000000000000, 0xc2b0000000000000 ++ .dword 0xc060000000000000, 0xc1d0000000000000 ++ .dword 0xc5c0000000000000, 0xc470000000000000 ++ .dword 0xc6a0000000000000, 0xc710000000000000 ++ .dword 0xce80000000000000, 0xcf30000000000000 ++ .dword 0xcde0000000000000, 0xcc50000000000000 ++ .dword 0xc840000000000000, 0xc9f0000000000000 ++ .dword 0xcb20000000000000, 0xca90000000000000 ++ .dword 0xee00000000000000, 0xefb0000000000000 ++ .dword 0xed60000000000000, 0xecd0000000000000 ++ .dword 0xe8c0000000000000, 0xe970000000000000 ++ .dword 0xeba0000000000000, 0xea10000000000000 ++ .dword 0xe380000000000000, 0xe230000000000000 ++ .dword 0xe0e0000000000000, 0xe150000000000000 ++ .dword 0xe540000000000000, 0xe4f0000000000000 ++ .dword 0xe620000000000000, 0xe790000000000000 ++ .dword 0xf500000000000000, 0xf4b0000000000000 ++ .dword 0xf660000000000000, 0xf7d0000000000000 ++ .dword 0xf3c0000000000000, 0xf270000000000000 ++ .dword 0xf0a0000000000000, 0xf110000000000000 ++ .dword 0xf880000000000000, 0xf930000000000000 ++ .dword 0xfbe0000000000000, 0xfa50000000000000 ++ .dword 0xfe40000000000000, 0xfff0000000000000 ++ .dword 0xfd20000000000000, 0xfc90000000000000 ++ .dword 0xb400000000000000, 0xb5b0000000000000 ++ .dword 0xb760000000000000, 0xb6d0000000000000 ++ .dword 0xb2c0000000000000, 0xb370000000000000 ++ .dword 0xb1a0000000000000, 0xb010000000000000 ++ .dword 0xb980000000000000, 0xb830000000000000 ++ .dword 0xbae0000000000000, 0xbb50000000000000 ++ .dword 0xbf40000000000000, 0xbef0000000000000 ++ .dword 0xbc20000000000000, 0xbd90000000000000 ++ .dword 0xaf00000000000000, 0xaeb0000000000000 ++ .dword 0xac60000000000000, 0xadd0000000000000 ++ .dword 0xa9c0000000000000, 0xa870000000000000 ++ .dword 0xaaa0000000000000, 0xab10000000000000 ++ .dword 0xa280000000000000, 0xa330000000000000 ++ .dword 0xa1e0000000000000, 0xa050000000000000 ++ .dword 0xa440000000000000, 0xa5f0000000000000 ++ .dword 0xa720000000000000, 0xa690000000000000 ++ .dword 0x8200000000000000, 0x83b0000000000000 ++ .dword 0x8160000000000000, 0x80d0000000000000 ++ .dword 0x84c0000000000000, 0x8570000000000000 ++ .dword 0x87a0000000000000, 0x8610000000000000 ++ .dword 0x8f80000000000000, 0x8e30000000000000 ++ .dword 0x8ce0000000000000, 0x8d50000000000000 ++ .dword 0x8940000000000000, 0x88f0000000000000 ++ .dword 0x8a20000000000000, 0x8b90000000000000 ++ .dword 0x9900000000000000, 0x98b0000000000000 ++ .dword 0x9a60000000000000, 0x9bd0000000000000 ++ .dword 0x9fc0000000000000, 0x9e70000000000000 ++ .dword 0x9ca0000000000000, 0x9d10000000000000 ++ .dword 0x9480000000000000, 0x9530000000000000 ++ .dword 0x97e0000000000000, 0x9650000000000000 ++ .dword 0x9240000000000000, 0x93f0000000000000 ++ .dword 0x9120000000000000, 0x9090000000000000 +diff --git a/crc/riscv64/crc64_jones_norm_vclmul.S b/crc/riscv64/crc64_jones_norm_vclmul.S +new file mode 100644 +index 0000000..17630f7 +--- /dev/null ++++ b/crc/riscv64/crc64_jones_norm_vclmul.S +@@ -0,0 +1,33 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc64_jones_norm_vclmul.h" ++#include "crc64_norm_common_vclmul.h" ++ ++crc64_norm_func crc64_jones_norm_vclmul +\ No newline at end of file +diff --git a/crc/riscv64/crc64_jones_norm_vclmul.h b/crc/riscv64/crc64_jones_norm_vclmul.h +new file mode 100644 +index 0000000..9fe71bc +--- /dev/null ++++ b/crc/riscv64/crc64_jones_norm_vclmul.h +@@ -0,0 +1,179 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.equ const_0, 0x4445ed2750017038 ++.equ const_quo, 0xddf3eeb298be6cf8 ++.equ const_poly, 0xad93d23594c935a9 ++ ++ .section .rodata ++ .text ++ .align 4 ++ .set .crc_loop_const,. + 0 ++ .type const_2, %object ++ .size const_2, 64 ++const_2: ++ .quad 0x4e501e58ca43d25e ++ .quad 0x13c961588f27f643 ++ .quad 0x4445ed2750017038 ++ .quad 0x698b74157cfbd736 ++ ++ .text ++ .align 4 ++ .set .lanchor_crc_tab,. + 0 ++ .type crc64_table_jones_norm, %object ++ .size crc64_table_jones_norm, 2048 ++crc64_table_jones_norm: ++ .dword 0x0000000000000000, 0xad93d23594c935a9 ++ .dword 0xf6b4765ebd5b5efb, 0x5b27a46b29926b52 ++ .dword 0x40fb3e88ee7f885f, 0xed68ecbd7ab6bdf6 ++ .dword 0xb64f48d65324d6a4, 0x1bdc9ae3c7ede30d ++ .dword 0x81f67d11dcff10be, 0x2c65af2448362517 ++ .dword 0x77420b4f61a44e45, 0xdad1d97af56d7bec ++ .dword 0xc10d4399328098e1, 0x6c9e91aca649ad48 ++ .dword 0x37b935c78fdbc61a, 0x9a2ae7f21b12f3b3 ++ .dword 0xae7f28162d3714d5, 0x03ecfa23b9fe217c ++ .dword 0x58cb5e48906c4a2e, 0xf5588c7d04a57f87 ++ .dword 0xee84169ec3489c8a, 0x4317c4ab5781a923 ++ .dword 0x183060c07e13c271, 0xb5a3b2f5eadaf7d8 ++ .dword 0x2f895507f1c8046b, 0x821a8732650131c2 ++ .dword 0xd93d23594c935a90, 0x74aef16cd85a6f39 ++ .dword 0x6f726b8f1fb78c34, 0xc2e1b9ba8b7eb99d ++ .dword 0x99c61dd1a2ecd2cf, 0x3455cfe43625e766 ++ .dword 0xf16d8219cea71c03, 0x5cfe502c5a6e29aa ++ .dword 0x07d9f44773fc42f8, 0xaa4a2672e7357751 ++ .dword 0xb196bc9120d8945c, 0x1c056ea4b411a1f5 ++ .dword 0x4722cacf9d83caa7, 0xeab118fa094aff0e ++ .dword 0x709bff0812580cbd, 0xdd082d3d86913914 ++ .dword 0x862f8956af035246, 0x2bbc5b633bca67ef ++ .dword 0x3060c180fc2784e2, 0x9df313b568eeb14b ++ .dword 0xc6d4b7de417cda19, 0x6b4765ebd5b5efb0 ++ .dword 0x5f12aa0fe39008d6, 0xf281783a77593d7f ++ .dword 0xa9a6dc515ecb562d, 0x04350e64ca026384 ++ .dword 0x1fe994870def8089, 0xb27a46b29926b520 ++ .dword 0xe95de2d9b0b4de72, 0x44ce30ec247debdb ++ .dword 0xdee4d71e3f6f1868, 0x7377052baba62dc1 ++ .dword 0x2850a14082344693, 0x85c3737516fd733a ++ .dword 0x9e1fe996d1109037, 0x338c3ba345d9a59e ++ .dword 0x68ab9fc86c4bcecc, 0xc5384dfdf882fb65 ++ .dword 0x4f48d60609870daf, 0xe2db04339d4e3806 ++ .dword 0xb9fca058b4dc5354, 0x146f726d201566fd ++ .dword 0x0fb3e88ee7f885f0, 0xa2203abb7331b059 ++ .dword 0xf9079ed05aa3db0b, 0x54944ce5ce6aeea2 ++ .dword 0xcebeab17d5781d11, 0x632d792241b128b8 ++ .dword 0x380add49682343ea, 0x95990f7cfcea7643 ++ .dword 0x8e45959f3b07954e, 0x23d647aaafcea0e7 ++ .dword 0x78f1e3c1865ccbb5, 0xd56231f41295fe1c ++ .dword 0xe137fe1024b0197a, 0x4ca42c25b0792cd3 ++ .dword 0x1783884e99eb4781, 0xba105a7b0d227228 ++ .dword 0xa1ccc098cacf9125, 0x0c5f12ad5e06a48c ++ .dword 0x5778b6c67794cfde, 0xfaeb64f3e35dfa77 ++ .dword 0x60c18301f84f09c4, 0xcd5251346c863c6d ++ .dword 0x9675f55f4514573f, 0x3be6276ad1dd6296 ++ .dword 0x203abd891630819b, 0x8da96fbc82f9b432 ++ .dword 0xd68ecbd7ab6bdf60, 0x7b1d19e23fa2eac9 ++ .dword 0xbe25541fc72011ac, 0x13b6862a53e92405 ++ .dword 0x489122417a7b4f57, 0xe502f074eeb27afe ++ .dword 0xfede6a97295f99f3, 0x534db8a2bd96ac5a ++ .dword 0x086a1cc99404c708, 0xa5f9cefc00cdf2a1 ++ .dword 0x3fd3290e1bdf0112, 0x9240fb3b8f1634bb ++ .dword 0xc9675f50a6845fe9, 0x64f48d65324d6a40 ++ .dword 0x7f281786f5a0894d, 0xd2bbc5b36169bce4 ++ .dword 0x899c61d848fbd7b6, 0x240fb3eddc32e21f ++ .dword 0x105a7c09ea170579, 0xbdc9ae3c7ede30d0 ++ .dword 0xe6ee0a57574c5b82, 0x4b7dd862c3856e2b ++ .dword 0x50a1428104688d26, 0xfd3290b490a1b88f ++ .dword 0xa61534dfb933d3dd, 0x0b86e6ea2dfae674 ++ .dword 0x91ac011836e815c7, 0x3c3fd32da221206e ++ .dword 0x671877468bb34b3c, 0xca8ba5731f7a7e95 ++ .dword 0xd1573f90d8979d98, 0x7cc4eda54c5ea831 ++ .dword 0x27e349ce65ccc363, 0x8a709bfbf105f6ca ++ .dword 0x9e91ac0c130e1b5e, 0x33027e3987c72ef7 ++ .dword 0x6825da52ae5545a5, 0xc5b608673a9c700c ++ .dword 0xde6a9284fd719301, 0x73f940b169b8a6a8 ++ .dword 0x28dee4da402acdfa, 0x854d36efd4e3f853 ++ .dword 0x1f67d11dcff10be0, 0xb2f403285b383e49 ++ .dword 0xe9d3a74372aa551b, 0x44407576e66360b2 ++ .dword 0x5f9cef95218e83bf, 0xf20f3da0b547b616 ++ .dword 0xa92899cb9cd5dd44, 0x04bb4bfe081ce8ed ++ .dword 0x30ee841a3e390f8b, 0x9d7d562faaf03a22 ++ .dword 0xc65af24483625170, 0x6bc9207117ab64d9 ++ .dword 0x7015ba92d04687d4, 0xdd8668a7448fb27d ++ .dword 0x86a1cccc6d1dd92f, 0x2b321ef9f9d4ec86 ++ .dword 0xb118f90be2c61f35, 0x1c8b2b3e760f2a9c ++ .dword 0x47ac8f555f9d41ce, 0xea3f5d60cb547467 ++ .dword 0xf1e3c7830cb9976a, 0x5c7015b69870a2c3 ++ .dword 0x0757b1ddb1e2c991, 0xaac463e8252bfc38 ++ .dword 0x6ffc2e15dda9075d, 0xc26ffc20496032f4 ++ .dword 0x9948584b60f259a6, 0x34db8a7ef43b6c0f ++ .dword 0x2f07109d33d68f02, 0x8294c2a8a71fbaab ++ .dword 0xd9b366c38e8dd1f9, 0x7420b4f61a44e450 ++ .dword 0xee0a5304015617e3, 0x43998131959f224a ++ .dword 0x18be255abc0d4918, 0xb52df76f28c47cb1 ++ .dword 0xaef16d8cef299fbc, 0x0362bfb97be0aa15 ++ .dword 0x58451bd25272c147, 0xf5d6c9e7c6bbf4ee ++ .dword 0xc1830603f09e1388, 0x6c10d43664572621 ++ .dword 0x3737705d4dc54d73, 0x9aa4a268d90c78da ++ .dword 0x8178388b1ee19bd7, 0x2cebeabe8a28ae7e ++ .dword 0x77cc4ed5a3bac52c, 0xda5f9ce03773f085 ++ .dword 0x40757b122c610336, 0xede6a927b8a8369f ++ .dword 0xb6c10d4c913a5dcd, 0x1b52df7905f36864 ++ .dword 0x008e459ac21e8b69, 0xad1d97af56d7bec0 ++ .dword 0xf63a33c47f45d592, 0x5ba9e1f1eb8ce03b ++ .dword 0xd1d97a0a1a8916f1, 0x7c4aa83f8e402358 ++ .dword 0x276d0c54a7d2480a, 0x8afede61331b7da3 ++ .dword 0x91224482f4f69eae, 0x3cb196b7603fab07 ++ .dword 0x679632dc49adc055, 0xca05e0e9dd64f5fc ++ .dword 0x502f071bc676064f, 0xfdbcd52e52bf33e6 ++ .dword 0xa69b71457b2d58b4, 0x0b08a370efe46d1d ++ .dword 0x10d4399328098e10, 0xbd47eba6bcc0bbb9 ++ .dword 0xe6604fcd9552d0eb, 0x4bf39df8019be542 ++ .dword 0x7fa6521c37be0224, 0xd2358029a377378d ++ .dword 0x891224428ae55cdf, 0x2481f6771e2c6976 ++ .dword 0x3f5d6c94d9c18a7b, 0x92cebea14d08bfd2 ++ .dword 0xc9e91aca649ad480, 0x647ac8fff053e129 ++ .dword 0xfe502f0deb41129a, 0x53c3fd387f882733 ++ .dword 0x08e45953561a4c61, 0xa5778b66c2d379c8 ++ .dword 0xbeab1185053e9ac5, 0x1338c3b091f7af6c ++ .dword 0x481f67dbb865c43e, 0xe58cb5ee2cacf197 ++ .dword 0x20b4f813d42e0af2, 0x8d272a2640e73f5b ++ .dword 0xd6008e4d69755409, 0x7b935c78fdbc61a0 ++ .dword 0x604fc69b3a5182ad, 0xcddc14aeae98b704 ++ .dword 0x96fbb0c5870adc56, 0x3b6862f013c3e9ff ++ .dword 0xa142850208d11a4c, 0x0cd157379c182fe5 ++ .dword 0x57f6f35cb58a44b7, 0xfa6521692143711e ++ .dword 0xe1b9bb8ae6ae9213, 0x4c2a69bf7267a7ba ++ .dword 0x170dcdd45bf5cce8, 0xba9e1fe1cf3cf941 ++ .dword 0x8ecbd005f9191e27, 0x235802306dd02b8e ++ .dword 0x787fa65b444240dc, 0xd5ec746ed08b7575 ++ .dword 0xce30ee8d17669678, 0x63a33cb883afa3d1 ++ .dword 0x388498d3aa3dc883, 0x95174ae63ef4fd2a ++ .dword 0x0f3dad1425e60e99, 0xa2ae7f21b12f3b30 ++ .dword 0xf989db4a98bd5062, 0x541a097f0c7465cb ++ .dword 0x4fc6939ccb9986c6, 0xe25541a95f50b36f ++ .dword 0xb972e5c276c2d83d, 0x14e137f7e20bed94 +diff --git a/crc/riscv64/crc64_jones_refl_vclmul.S b/crc/riscv64/crc64_jones_refl_vclmul.S +new file mode 100644 +index 0000000..aeb91cf +--- /dev/null ++++ b/crc/riscv64/crc64_jones_refl_vclmul.S +@@ -0,0 +1,33 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc64_jones_refl_vclmul.h" ++#include "crc64_refl_common_vclmul.h" ++ ++crc64_refl_func crc64_jones_refl_vclmul +\ No newline at end of file +diff --git a/crc/riscv64/crc64_jones_refl_vclmul.h b/crc/riscv64/crc64_jones_refl_vclmul.h +new file mode 100644 +index 0000000..feb949d +--- /dev/null ++++ b/crc/riscv64/crc64_jones_refl_vclmul.h +@@ -0,0 +1,179 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++.equ const_0, 0x381d0015c96f4444 ++.equ const_quo, 0x3e6cfa329aef9f77 ++.equ const_poly, 0x2b5926535897936b ++ ++ .section .rodata ++ .text ++ .align 3 ++ .set .crc_loop_const,. + 0 ++ .type const_2, %object ++ .size const_2, 64 ++const_2: ++ .quad 0xaf86efb16d9ab4fb ++ .quad 0xf49784a634f014e4 ++ .quad 0xd9d7be7d505da32c ++ .quad 0x381d0015c96f4444 ++ ++ .text ++ .align 4 ++ .set .lanchor_crc_tab,. + 0 ++ .type crc64_table_jones_refl, %object ++ .size crc64_table_jones_refl, 2048 ++crc64_table_jones_refl: ++ .dword 0x0000000000000000, 0x7ad870c830358979 ++ .dword 0xf5b0e190606b12f2, 0x8f689158505e9b8b ++ .dword 0xc038e5739841b68f, 0xbae095bba8743ff6 ++ .dword 0x358804e3f82aa47d, 0x4f50742bc81f2d04 ++ .dword 0xab28ecb46814fe75, 0xd1f09c7c5821770c ++ .dword 0x5e980d24087fec87, 0x24407dec384a65fe ++ .dword 0x6b1009c7f05548fa, 0x11c8790fc060c183 ++ .dword 0x9ea0e857903e5a08, 0xe478989fa00bd371 ++ .dword 0x7d08ff3b88be6f81, 0x07d08ff3b88be6f8 ++ .dword 0x88b81eabe8d57d73, 0xf2606e63d8e0f40a ++ .dword 0xbd301a4810ffd90e, 0xc7e86a8020ca5077 ++ .dword 0x4880fbd87094cbfc, 0x32588b1040a14285 ++ .dword 0xd620138fe0aa91f4, 0xacf86347d09f188d ++ .dword 0x2390f21f80c18306, 0x594882d7b0f40a7f ++ .dword 0x1618f6fc78eb277b, 0x6cc0863448deae02 ++ .dword 0xe3a8176c18803589, 0x997067a428b5bcf0 ++ .dword 0xfa11fe77117cdf02, 0x80c98ebf2149567b ++ .dword 0x0fa11fe77117cdf0, 0x75796f2f41224489 ++ .dword 0x3a291b04893d698d, 0x40f16bccb908e0f4 ++ .dword 0xcf99fa94e9567b7f, 0xb5418a5cd963f206 ++ .dword 0x513912c379682177, 0x2be1620b495da80e ++ .dword 0xa489f35319033385, 0xde51839b2936bafc ++ .dword 0x9101f7b0e12997f8, 0xebd98778d11c1e81 ++ .dword 0x64b116208142850a, 0x1e6966e8b1770c73 ++ .dword 0x8719014c99c2b083, 0xfdc17184a9f739fa ++ .dword 0x72a9e0dcf9a9a271, 0x08719014c99c2b08 ++ .dword 0x4721e43f0183060c, 0x3df994f731b68f75 ++ .dword 0xb29105af61e814fe, 0xc849756751dd9d87 ++ .dword 0x2c31edf8f1d64ef6, 0x56e99d30c1e3c78f ++ .dword 0xd9810c6891bd5c04, 0xa3597ca0a188d57d ++ .dword 0xec09088b6997f879, 0x96d1784359a27100 ++ .dword 0x19b9e91b09fcea8b, 0x636199d339c963f2 ++ .dword 0xdf7adabd7a6e2d6f, 0xa5a2aa754a5ba416 ++ .dword 0x2aca3b2d1a053f9d, 0x50124be52a30b6e4 ++ .dword 0x1f423fcee22f9be0, 0x659a4f06d21a1299 ++ .dword 0xeaf2de5e82448912, 0x902aae96b271006b ++ .dword 0x74523609127ad31a, 0x0e8a46c1224f5a63 ++ .dword 0x81e2d7997211c1e8, 0xfb3aa75142244891 ++ .dword 0xb46ad37a8a3b6595, 0xceb2a3b2ba0eecec ++ .dword 0x41da32eaea507767, 0x3b024222da65fe1e ++ .dword 0xa2722586f2d042ee, 0xd8aa554ec2e5cb97 ++ .dword 0x57c2c41692bb501c, 0x2d1ab4dea28ed965 ++ .dword 0x624ac0f56a91f461, 0x1892b03d5aa47d18 ++ .dword 0x97fa21650afae693, 0xed2251ad3acf6fea ++ .dword 0x095ac9329ac4bc9b, 0x7382b9faaaf135e2 ++ .dword 0xfcea28a2faafae69, 0x8632586aca9a2710 ++ .dword 0xc9622c4102850a14, 0xb3ba5c8932b0836d ++ .dword 0x3cd2cdd162ee18e6, 0x460abd1952db919f ++ .dword 0x256b24ca6b12f26d, 0x5fb354025b277b14 ++ .dword 0xd0dbc55a0b79e09f, 0xaa03b5923b4c69e6 ++ .dword 0xe553c1b9f35344e2, 0x9f8bb171c366cd9b ++ .dword 0x10e3202993385610, 0x6a3b50e1a30ddf69 ++ .dword 0x8e43c87e03060c18, 0xf49bb8b633338561 ++ .dword 0x7bf329ee636d1eea, 0x012b592653589793 ++ .dword 0x4e7b2d0d9b47ba97, 0x34a35dc5ab7233ee ++ .dword 0xbbcbcc9dfb2ca865, 0xc113bc55cb19211c ++ .dword 0x5863dbf1e3ac9dec, 0x22bbab39d3991495 ++ .dword 0xadd33a6183c78f1e, 0xd70b4aa9b3f20667 ++ .dword 0x985b3e827bed2b63, 0xe2834e4a4bd8a21a ++ .dword 0x6debdf121b863991, 0x1733afda2bb3b0e8 ++ .dword 0xf34b37458bb86399, 0x8993478dbb8deae0 ++ .dword 0x06fbd6d5ebd3716b, 0x7c23a61ddbe6f812 ++ .dword 0x3373d23613f9d516, 0x49aba2fe23cc5c6f ++ .dword 0xc6c333a67392c7e4, 0xbc1b436e43a74e9d ++ .dword 0x95ac9329ac4bc9b5, 0xef74e3e19c7e40cc ++ .dword 0x601c72b9cc20db47, 0x1ac40271fc15523e ++ .dword 0x5594765a340a7f3a, 0x2f4c0692043ff643 ++ .dword 0xa02497ca54616dc8, 0xdafce7026454e4b1 ++ .dword 0x3e847f9dc45f37c0, 0x445c0f55f46abeb9 ++ .dword 0xcb349e0da4342532, 0xb1eceec59401ac4b ++ .dword 0xfebc9aee5c1e814f, 0x8464ea266c2b0836 ++ .dword 0x0b0c7b7e3c7593bd, 0x71d40bb60c401ac4 ++ .dword 0xe8a46c1224f5a634, 0x927c1cda14c02f4d ++ .dword 0x1d148d82449eb4c6, 0x67ccfd4a74ab3dbf ++ .dword 0x289c8961bcb410bb, 0x5244f9a98c8199c2 ++ .dword 0xdd2c68f1dcdf0249, 0xa7f41839ecea8b30 ++ .dword 0x438c80a64ce15841, 0x3954f06e7cd4d138 ++ .dword 0xb63c61362c8a4ab3, 0xcce411fe1cbfc3ca ++ .dword 0x83b465d5d4a0eece, 0xf96c151de49567b7 ++ .dword 0x76048445b4cbfc3c, 0x0cdcf48d84fe7545 ++ .dword 0x6fbd6d5ebd3716b7, 0x15651d968d029fce ++ .dword 0x9a0d8ccedd5c0445, 0xe0d5fc06ed698d3c ++ .dword 0xaf85882d2576a038, 0xd55df8e515432941 ++ .dword 0x5a3569bd451db2ca, 0x20ed197575283bb3 ++ .dword 0xc49581ead523e8c2, 0xbe4df122e51661bb ++ .dword 0x3125607ab548fa30, 0x4bfd10b2857d7349 ++ .dword 0x04ad64994d625e4d, 0x7e7514517d57d734 ++ .dword 0xf11d85092d094cbf, 0x8bc5f5c11d3cc5c6 ++ .dword 0x12b5926535897936, 0x686de2ad05bcf04f ++ .dword 0xe70573f555e26bc4, 0x9ddd033d65d7e2bd ++ .dword 0xd28d7716adc8cfb9, 0xa85507de9dfd46c0 ++ .dword 0x273d9686cda3dd4b, 0x5de5e64efd965432 ++ .dword 0xb99d7ed15d9d8743, 0xc3450e196da80e3a ++ .dword 0x4c2d9f413df695b1, 0x36f5ef890dc31cc8 ++ .dword 0x79a59ba2c5dc31cc, 0x037deb6af5e9b8b5 ++ .dword 0x8c157a32a5b7233e, 0xf6cd0afa9582aa47 ++ .dword 0x4ad64994d625e4da, 0x300e395ce6106da3 ++ .dword 0xbf66a804b64ef628, 0xc5bed8cc867b7f51 ++ .dword 0x8aeeace74e645255, 0xf036dc2f7e51db2c ++ .dword 0x7f5e4d772e0f40a7, 0x05863dbf1e3ac9de ++ .dword 0xe1fea520be311aaf, 0x9b26d5e88e0493d6 ++ .dword 0x144e44b0de5a085d, 0x6e963478ee6f8124 ++ .dword 0x21c640532670ac20, 0x5b1e309b16452559 ++ .dword 0xd476a1c3461bbed2, 0xaeaed10b762e37ab ++ .dword 0x37deb6af5e9b8b5b, 0x4d06c6676eae0222 ++ .dword 0xc26e573f3ef099a9, 0xb8b627f70ec510d0 ++ .dword 0xf7e653dcc6da3dd4, 0x8d3e2314f6efb4ad ++ .dword 0x0256b24ca6b12f26, 0x788ec2849684a65f ++ .dword 0x9cf65a1b368f752e, 0xe62e2ad306bafc57 ++ .dword 0x6946bb8b56e467dc, 0x139ecb4366d1eea5 ++ .dword 0x5ccebf68aecec3a1, 0x2616cfa09efb4ad8 ++ .dword 0xa97e5ef8cea5d153, 0xd3a62e30fe90582a ++ .dword 0xb0c7b7e3c7593bd8, 0xca1fc72bf76cb2a1 ++ .dword 0x45775673a732292a, 0x3faf26bb9707a053 ++ .dword 0x70ff52905f188d57, 0x0a2722586f2d042e ++ .dword 0x854fb3003f739fa5, 0xff97c3c80f4616dc ++ .dword 0x1bef5b57af4dc5ad, 0x61372b9f9f784cd4 ++ .dword 0xee5fbac7cf26d75f, 0x9487ca0fff135e26 ++ .dword 0xdbd7be24370c7322, 0xa10fceec0739fa5b ++ .dword 0x2e675fb4576761d0, 0x54bf2f7c6752e8a9 ++ .dword 0xcdcf48d84fe75459, 0xb71738107fd2dd20 ++ .dword 0x387fa9482f8c46ab, 0x42a7d9801fb9cfd2 ++ .dword 0x0df7adabd7a6e2d6, 0x772fdd63e7936baf ++ .dword 0xf8474c3bb7cdf024, 0x829f3cf387f8795d ++ .dword 0x66e7a46c27f3aa2c, 0x1c3fd4a417c62355 ++ .dword 0x935745fc4798b8de, 0xe98f353477ad31a7 ++ .dword 0xa6df411fbfb21ca3, 0xdc0731d78f8795da ++ .dword 0x536fa08fdfd90e51, 0x29b7d047efec8728 +diff --git a/crc/riscv64/crc64_norm_common_vclmul.h b/crc/riscv64/crc64_norm_common_vclmul.h +new file mode 100644 +index 0000000..2e6e46e +--- /dev/null ++++ b/crc/riscv64/crc64_norm_common_vclmul.h +@@ -0,0 +1,102 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc_common_vclmul.h" ++ ++.macro crc64_norm_func name ++ .text ++ .align 3 ++ .type \name, @function ++ .global \name ++\name: ++ xori seed, seed, -1 ++ li counter, 0 ++ li tmp_1, 64 ++ bgeu len, tmp_1, .crc_clmul_pre ++ ++.crc_tab_pre: ++ bgeu counter, len, .done ++ la crc_tab_addr, .lanchor_crc_tab ++ add buf_iter, buf, counter ++ add buf, buf, len ++ ++ .align 3 ++.loop_crc_tab: ++ lbu tmp_1, 0(buf_iter) ++ addi buf_iter, buf_iter, 1 ++ srli tmp, seed, 0x38 ++ xor tmp, tmp_1, tmp ++ slli tmp, tmp, 0x3 ++ add tmp, tmp, crc_tab_addr ++ ld tmp, 0(tmp) ++ slli seed, seed, 0x8 ++ xor seed, seed, tmp ++ bne buf_iter, buf, .loop_crc_tab ++ ++.done: ++ xori seed, seed, -1 ++ ret ++ ++ .align 2 ++.crc_clmul_pre: ++ vsetivli zero, 2, e64, m1, ta, ma ++ vmv.s.x vec_zero, zero ++ crc_norm_load_first_block ++ vmv.s.x vec_zero, zero ++ crc_load_p4 ++ addi tmp_0, len, -64 ++ bltu tmp_0, tmp_1, .clmul_loop_end ++ ++ crc_norm_loop ++ ++.clmul_loop_end: ++ addi tmp_4, tmp_4, 16 ++ crc_fold_512b_to_128b ++ ++ addi sp, sp, -16 ++ vse64.v vec_0, (sp) ++ ld tmp_0, 0(sp) ++ ld tmp_1, 8(sp) ++ addi sp, sp, 16 ++ li tmp_2, const_0 ++ clmul tmp_4, tmp_1, tmp_2 ++ clmulh tmp_5, tmp_1, tmp_2 ++ xor tmp_5, tmp_5, tmp_0 ++ li tmp_2, const_quo ++ li tmp_3, const_poly ++ clmul tmp_1, tmp_2, tmp_5 ++ clmulh tmp_0, tmp_2, tmp_5 ++ xor tmp_1, tmp_4, tmp_1 ++ xor tmp_0, tmp_5, tmp_0 ++ clmul tmp_1, tmp_0, tmp_3 ++ xor seed, tmp_1, tmp_4 ++ ++ j .crc_tab_pre ++ .size \name, .-\name ++.endm +\ No newline at end of file +diff --git a/crc/riscv64/crc64_refl_common_vclmul.h b/crc/riscv64/crc64_refl_common_vclmul.h +new file mode 100644 +index 0000000..6664518 +--- /dev/null ++++ b/crc/riscv64/crc64_refl_common_vclmul.h +@@ -0,0 +1,101 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++#include "crc_common_vclmul.h" ++ ++.macro crc64_refl_func name ++ .text ++ .align 3 ++ .type \name, @function ++ .global \name ++\name: ++ xori seed, seed, -1 ++ li counter, 0 ++ li tmp_1, 64 ++ bgeu len, tmp_1, .crc_clmul_pre ++ ++.crc_tab_pre: ++ bgeu counter, len, .done ++ la crc_tab_addr, .lanchor_crc_tab ++ add buf_iter, buf, counter ++ add buf, buf, len ++ ++ .align 3 ++.loop_crc_tab: ++ lbu tmp_1, 0(buf_iter) ++ addi buf_iter, buf_iter, 1 ++ xor tmp_1, tmp_1, seed ++ zext.b tmp, tmp_1 ++ slli tmp, tmp, 0x3 ++ add tmp, tmp, crc_tab_addr ++ ld seed, 0(tmp) ++ srli tmp_1, tmp_1, 0x8 ++ xor seed, seed, tmp_1 ++ bne buf_iter, buf, .loop_crc_tab ++ ++.done: ++ xori seed, seed, -1 ++ ret ++ ++ .align 2 ++.crc_clmul_pre: ++ vsetivli zero, 2, e64, m1, ta, ma ++ vmv.s.x vec_zero, zero ++ crc_refl_load_first_block ++ vmv.s.x vec_zero, zero ++ crc_load_p4 ++ addi tmp_0, len, -64 ++ bltu tmp_0, tmp_1, .clmul_loop_end ++ ++ crc_refl_loop ++ ++.clmul_loop_end: ++ addi tmp_4, tmp_4, 16 ++ crc_fold_512b_to_128b ++ ++ addi sp, sp, -16 ++ vse64.v vec_0, (sp) ++ ld tmp_0, 0(sp) ++ ld tmp_1, 8(sp) ++ addi sp, sp, 16 ++ li tmp_2, const_0 ++ clmul tmp_4, tmp_0, tmp_2 ++ clmulh tmp_5, tmp_0, tmp_2 ++ xor tmp_1, tmp_1, tmp_4 ++ ++ li tmp_2, const_quo # quo ++ li tmp_3, const_poly # poly ++ clmul tmp_1, tmp_1, tmp_2 ++ clmulh tmp_4, tmp_1, tmp_3 ++ xor tmp_4, tmp_4, tmp_1 ++ xor seed, tmp_4, tmp_5 ++ ++ j .crc_tab_pre ++ .size \name, .-\name ++.endm +\ No newline at end of file +diff --git a/crc/riscv64/crc_common_vclmul.h b/crc/riscv64/crc_common_vclmul.h +new file mode 100644 +index 0000000..f0c8be7 +--- /dev/null ++++ b/crc/riscv64/crc_common_vclmul.h +@@ -0,0 +1,235 @@ ++######################################################################## ++# Copyright (c) 2025 ZTE Corporation. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++ ++// parameters ++#define seed a0 ++#define buf a1 ++#define len a2 ++ ++// return ++#define crc_ret a0 ++ ++// global variables ++#define counter a3 ++#define buf_iter a4 ++#define crc_tab_addr a5 ++#define buf_end a6 ++#define tmp a7 ++#define tmp_0 t0 ++#define tmp_1 t1 ++#define tmp_2 t2 ++#define tmp_3 t3 ++#define tmp_4 t4 ++#define tmp_5 t5 ++ ++#define vec_0 v0 ++#define vec_1 v1 ++#define vec_2 v2 ++#define vec_3 v3 ++#define vec_4 v4 ++#define vec_5 v5 ++#define vec_6 v6 ++#define vec_7 v7 ++#define vec_zero v8 ++#define vec_8 v8 ++#define vec_9 v9 ++ ++.macro crc_refl_load_first_block ++ mv buf_iter, buf ++ vle64.v vec_0, 0(buf_iter) ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_1, 0(buf_iter) ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_2, 0(buf_iter) ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_3, 0(buf_iter) ++ addi buf_iter, buf_iter, 16 ++ andi counter, len, ~63 ++ addi tmp_0, counter, -64 ++ ++ vmv.s.x vec_4, zero ++ vmv.s.x vec_5, seed ++ vslideup.vi vec_5, vec_4, 1 ++ vxor.vv vec_0, vec_0, vec_5 ++.endm ++ ++.macro crc_norm_load_first_block ++ mv buf_iter, buf ++ vle64.v vec_6, 0(buf_iter) ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_7, 0(buf_iter) ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_8, 0(buf_iter) ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_9, 0(buf_iter) ++ addi buf_iter, buf_iter, 16 ++ andi counter, len, ~63 ++ addi tmp_0, counter, -64 ++ ++ vmv.s.x vec_4, zero ++ vmv.s.x vec_5, seed ++ vslideup.vi vec_4, vec_5, 1 ++ vrev8.v vec_6, vec_6 ++ vrev8.v vec_7, vec_7 ++ vrev8.v vec_8, vec_8 ++ vrev8.v vec_9, vec_9 ++ vslidedown.vi vec_0, vec_6, 1 ++ vslidedown.vi vec_1, vec_7, 1 ++ vslidedown.vi vec_2, vec_8, 1 ++ vslidedown.vi vec_3, vec_9, 1 ++ vslideup.vi vec_0, vec_6, 1 ++ vslideup.vi vec_1, vec_7, 1 ++ vslideup.vi vec_2, vec_8, 1 ++ vslideup.vi vec_3, vec_9, 1 ++ vxor.vv vec_0, vec_0, vec_4 ++.endm ++ ++.macro crc_load_p4 ++ add buf_end, buf_iter, tmp_0 ++ la tmp_4, .crc_loop_const ++ vle64.v vec_5, 0(tmp_4) ++.endm ++ ++.macro crc_refl_loop ++ .align 3 ++.clmul_loop: ++ vle64.v vec_7, 0(buf_iter) ++ vclmul.vv vec_4, vec_0, vec_5 ++ vclmulh.vv vec_0, vec_0, vec_5 ++ vredxor.vs vec_0, vec_0, vec_zero ++ vredxor.vs vec_4, vec_4, vec_zero ++ vslideup.vi vec_4, vec_0, 1 ++ vxor.vv vec_0, vec_4, vec_7 ++ ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_7, 0(buf_iter) ++ vclmul.vv vec_4, vec_1, vec_5 ++ vclmulh.vv vec_1, vec_1, vec_5 ++ vredxor.vs vec_1, vec_1, vec_zero ++ vredxor.vs vec_4, vec_4, vec_zero ++ vslideup.vi vec_4, vec_1, 1 ++ vxor.vv vec_1, vec_4, vec_7 ++ ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_7, 0(buf_iter) ++ vclmul.vv vec_4, vec_2, vec_5 ++ vclmulh.vv vec_2, vec_2, vec_5 ++ vredxor.vs vec_2, vec_2, vec_zero ++ vredxor.vs vec_4, vec_4, vec_zero ++ vslideup.vi vec_4, vec_2, 1 ++ vxor.vv vec_2, vec_4, vec_7 ++ ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_7, 0(buf_iter) ++ vclmul.vv vec_4, vec_3, vec_5 ++ vclmulh.vv vec_3, vec_3, vec_5 ++ vredxor.vs vec_3, vec_3, vec_zero ++ vredxor.vs vec_4, vec_4, vec_zero ++ vslideup.vi vec_4, vec_3, 1 ++ vxor.vv vec_3, vec_4, vec_7 ++ ++ addi buf_iter, buf_iter, 16 ++ bne buf_iter, buf_end, .clmul_loop ++.endm ++ ++.macro crc_norm_loop ++ .align 3 ++.clmul_loop: ++ vle64.v vec_7, 0(buf_iter) ++ vclmul.vv vec_4, vec_0, vec_5 ++ vclmulh.vv vec_0, vec_0, vec_5 ++ vredxor.vs vec_0, vec_0, vec_zero ++ vredxor.vs vec_4, vec_4, vec_zero ++ vslideup.vi vec_4, vec_0, 1 ++ vrev8.v vec_7, vec_7 ++ vslidedown.vi vec_6, vec_7, 1 ++ vslideup.vi vec_6, vec_7, 1 ++ vxor.vv vec_0, vec_4, vec_6 ++ ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_7, 0(buf_iter) ++ vclmul.vv vec_4, vec_1, vec_5 ++ vclmulh.vv vec_1, vec_1, vec_5 ++ vredxor.vs vec_1, vec_1, vec_zero ++ vredxor.vs vec_4, vec_4, vec_zero ++ vslideup.vi vec_4, vec_1, 1 ++ vrev8.v vec_7, vec_7 ++ vslidedown.vi vec_6, vec_7, 1 ++ vslideup.vi vec_6, vec_7, 1 ++ vxor.vv vec_1, vec_4, vec_6 ++ ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_7, 0(buf_iter) ++ vclmul.vv vec_4, vec_2, vec_5 ++ vclmulh.vv vec_2, vec_2, vec_5 ++ vredxor.vs vec_2, vec_2, vec_zero ++ vredxor.vs vec_4, vec_4, vec_zero ++ vslideup.vi vec_4, vec_2, 1 ++ vrev8.v vec_7, vec_7 ++ vslidedown.vi vec_6, vec_7, 1 ++ vslideup.vi vec_6, vec_7, 1 ++ vxor.vv vec_2, vec_4, vec_6 ++ ++ addi buf_iter, buf_iter, 16 ++ vle64.v vec_7, 0(buf_iter) ++ vclmul.vv vec_4, vec_3, vec_5 ++ vclmulh.vv vec_3, vec_3, vec_5 ++ vredxor.vs vec_3, vec_3, vec_zero ++ vredxor.vs vec_4, vec_4, vec_zero ++ vslideup.vi vec_4, vec_3, 1 ++ vrev8.v vec_7, vec_7 ++ vslidedown.vi vec_6, vec_7, 1 ++ vslideup.vi vec_6, vec_7, 1 ++ vxor.vv vec_3, vec_4, vec_6 ++ ++ addi buf_iter, buf_iter, 16 ++ bne buf_iter, buf_end, .clmul_loop ++.endm ++ ++.macro crc_fold_512b_to_128b ++ vle64.v vec_5, 0(tmp_4) ++ vclmul.vv vec_6, vec_0, vec_5 ++ vclmulh.vv vec_7, vec_0, vec_5 ++ vredxor.vs vec_6, vec_6, vec_zero ++ vredxor.vs vec_7, vec_7, vec_zero ++ vslideup.vi vec_6, vec_7, 1 ++ vxor.vv vec_0, vec_6, vec_1 ++ vclmul.vv vec_6, vec_0, vec_5 ++ vclmulh.vv vec_7, vec_0, vec_5 ++ vredxor.vs vec_6, vec_6, vec_zero ++ vredxor.vs vec_7, vec_7, vec_zero ++ vslideup.vi vec_6, vec_7, 1 ++ vxor.vv vec_0, vec_6, vec_2 ++ vclmul.vv vec_6, vec_0, vec_5 ++ vclmulh.vv vec_7, vec_0, vec_5 ++ vredxor.vs vec_6, vec_6, vec_zero ++ vredxor.vs vec_7, vec_7, vec_zero ++ vslideup.vi vec_6, vec_7, 1 ++ vxor.vv vec_0, vec_6, vec_3 ++.endm +\ No newline at end of file +diff --git a/crc/riscv64/crc_multibinary_riscv.S b/crc/riscv64/crc_multibinary_riscv.S +new file mode 100644 +index 0000000..ef36681 +--- /dev/null ++++ b/crc/riscv64/crc_multibinary_riscv.S +@@ -0,0 +1,42 @@ ++######################################################################## ++# Copyright(c) 2025 ZTE Corporation All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of ZTE Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++######################################################################### ++#include ++ ++ ++mbin_interface crc32_iscsi ++mbin_interface crc16_t10dif ++mbin_interface crc16_t10dif_copy ++mbin_interface crc32_ieee ++mbin_interface crc32_gzip_refl ++mbin_interface crc64_ecma_refl ++mbin_interface crc64_ecma_norm ++mbin_interface crc64_iso_refl ++mbin_interface crc64_iso_norm ++mbin_interface crc64_jones_refl ++mbin_interface crc64_jones_norm +\ No newline at end of file +diff --git a/crc/riscv64/crc_riscv64_dispatcher.c b/crc/riscv64/crc_riscv64_dispatcher.c +new file mode 100644 +index 0000000..6ded667 +--- /dev/null ++++ b/crc/riscv64/crc_riscv64_dispatcher.c +@@ -0,0 +1,169 @@ ++/********************************************************************** ++ Copyright(c) 2025 ZTE Corporation All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions ++ are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ * Neither the name of ZTE Corporation nor the names of its ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++**********************************************************************/ ++#include ++ ++DEFINE_INTERFACE_DISPATCHER(crc16_t10dif) ++{ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc16_t10dif_vclmul); ++ } ++ ++ return PROVIDER_BASIC(crc16_t10dif); ++} ++ ++DEFINE_INTERFACE_DISPATCHER(crc16_t10dif_copy) ++{ ++ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc16_t10dif_copy_vclmul); ++ } ++ ++ return PROVIDER_BASIC(crc16_t10dif_copy); ++} ++ ++DEFINE_INTERFACE_DISPATCHER(crc32_ieee) ++{ ++ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc32_ieee_norm_vclmul); ++ ++ } ++ ++ return PROVIDER_BASIC(crc32_ieee); ++} ++ ++DEFINE_INTERFACE_DISPATCHER(crc32_iscsi) ++{ ++ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc32_iscsi_refl_vclmul); ++ ++ } ++ ++ return PROVIDER_BASIC(crc32_iscsi); ++} ++ ++DEFINE_INTERFACE_DISPATCHER(crc32_gzip_refl) ++{ ++ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc32_gzip_refl_vclmul); ++ ++ } ++ ++ return PROVIDER_BASIC(crc32_gzip_refl); ++} ++ ++DEFINE_INTERFACE_DISPATCHER(crc64_ecma_refl) ++{ ++ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc64_ecma_refl_vclmul); ++ ++ } ++ ++ return PROVIDER_BASIC(crc64_ecma_refl); ++} ++ ++DEFINE_INTERFACE_DISPATCHER(crc64_ecma_norm) ++{ ++ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc64_ecma_norm_vclmul); ++ ++ } ++ ++ return PROVIDER_BASIC(crc64_ecma_norm); ++} ++ ++DEFINE_INTERFACE_DISPATCHER(crc64_iso_refl) ++{ ++ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc64_iso_refl_vclmul); ++ ++ } ++ ++ return PROVIDER_BASIC(crc64_iso_refl); ++} ++ ++DEFINE_INTERFACE_DISPATCHER(crc64_iso_norm) ++{ ++ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc64_iso_norm_vclmul); ++ ++ } ++ ++ return PROVIDER_BASIC(crc64_iso_norm); ++} ++ ++DEFINE_INTERFACE_DISPATCHER(crc64_jones_refl) ++{ ++ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc64_jones_refl_vclmul); ++ ++ } ++ ++ return PROVIDER_BASIC(crc64_jones_refl); ++} ++ ++DEFINE_INTERFACE_DISPATCHER(crc64_jones_norm) ++{ ++ ++ unsigned long auxval = getauxval(AT_HWCAP); ++ if (auxval & HWCAP_RV('V')) { ++ if (has_riscv_ext("zvbc") && has_riscv_ext("zvbb") && has_riscv_ext("zbc")) ++ return PROVIDER_INFO(crc64_jones_norm_vclmul); ++ ++ } ++ ++ return PROVIDER_BASIC(crc64_jones_norm); ++} +\ No newline at end of file +diff --git a/erasure_code/Makefile.am b/erasure_code/Makefile.am +index f1d0d1d..b4b2f45 100644 +--- a/erasure_code/Makefile.am ++++ b/erasure_code/Makefile.am +@@ -32,7 +32,7 @@ include erasure_code/aarch64/Makefile.am + include erasure_code/ppc64le/Makefile.am + + lsrc += erasure_code/ec_base.c +- ++lsrc_riscv64 += erasure_code/ec_base_aliases.c + lsrc_base_aliases += erasure_code/ec_base_aliases.c + lsrc_x86_64 += \ + erasure_code/ec_highlevel_func.c \ +diff --git a/igzip/Makefile.am b/igzip/Makefile.am +index bec359a..636d58d 100644 +--- a/igzip/Makefile.am ++++ b/igzip/Makefile.am +@@ -39,7 +39,7 @@ lsrc += igzip/igzip.c \ + lsrc_base_aliases += igzip/igzip_base_aliases.c igzip/proc_heap_base.c + lsrc_x86_32 += igzip/igzip_base_aliases.c igzip/proc_heap_base.c + lsrc_ppc64le += igzip/igzip_base_aliases.c igzip/proc_heap_base.c +- ++lsrc_riscv64 += igzip/igzip_base_aliases.c igzip/proc_heap_base.c + lsrc_aarch64 += igzip/aarch64/igzip_inflate_multibinary_arm64.S \ + igzip/aarch64/igzip_multibinary_arm64.S \ + igzip/aarch64/igzip_isal_adler32_neon.S \ +diff --git a/include/riscv64_multibinary.h b/include/riscv64_multibinary.h +new file mode 100644 +index 0000000..ad66970 +--- /dev/null ++++ b/include/riscv64_multibinary.h +@@ -0,0 +1,163 @@ ++/********************************************************************** ++ Copyright(c) 2024 All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions ++ are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++**********************************************************************/ ++ ++#ifndef __RISCV64_MULTIBINARY_H__ ++#define __RISCV64_MULTIBINARY_H__ ++ ++#ifndef __riscv ++#error "This file is for RISC-V only" ++#endif ++ ++#ifdef __ASSEMBLY__ ++ ++/** ++ * # mbin_interface : the wrapper layer for isal-l api ++ * ++ * ## references: ++ * * aarch64_multibinary.h ++ * ## Usage: ++ * ++ * 1. Define dispather function ++ * 2. name must be \name\()_dispatcher ++ * 3. Prototype should be *"void * \name\()_dispatcher"* ++ * 4. The dispather should return the right function pointer , revision and a string information . ++ **/ ++ .macro mbin_interface name:req ++ .section .data ++ .align 3 ++ .global \name\()_dispatcher_info ++ .type \name\()_dispatcher_info, @object ++\name\()_dispatcher_info: ++ .quad \name\()_mbinit ++ .section .text ++ .global \name\()_mbinit ++\name\()_mbinit: ++ addi sp, sp, -56 ++ sd ra, 48(sp) ++ sd a0, 0(sp) ++ sd a1, 8(sp) ++ sd a2, 16(sp) ++ sd a3, 24(sp) ++ sd a4, 32(sp) ++ sd a5, 40(sp) ++ call \name\()_dispatcher ++ mv t2, a0 ++ la t0, \name\()_dispatcher_info ++ sd a0, 0(t0) ++ ld ra, 48(sp) ++ ld a0, 0(sp) ++ ld a1, 8(sp) ++ ld a2, 16(sp) ++ ld a3, 24(sp) ++ ld a4, 32(sp) ++ ld a5, 40(sp) ++ addi sp, sp, 56 ++ jr t2 ++.global \name\() ++.type \name,%function ++\name\(): ++ la t0, \name\()_dispatcher_info ++ ld t1, 0(t0) ++ jr t1 ++.size \name,. - \name ++.endm ++ ++/** ++* mbin_interface_base is used for the interfaces which have only ++* noarch implementation ++*/ ++.macro mbin_interface_base name:req, base:req ++ .extern \base ++ .data ++ .align 3 ++ .global \name\()_dispatcher_info ++ .type \name\()_dispatcher_info, @object ++\name\()_dispatcher_info: ++ .dword \base ++ .text ++ .global \name ++ .type \name, @function ++\name: ++ la t0, \name\()_dispatcher_info ++ ld t0, (t0) ++ jr t0 ++.endm ++ ++#else /* __ASSEMBLY__ */ ++#include ++#include ++#include ++#define HWCAP_RV(letter) (1ul << ((letter) - 'A')) ++ ++/* Define interface dispatcher macro */ ++#define DEFINE_INTERFACE_DISPATCHER(name) \ ++ void * name##_dispatcher(void) ++ ++/* Define basic provider macro */ ++#define PROVIDER_BASIC(name) \ ++ PROVIDER_INFO(name##_base) ++ ++#define DO_DIGNOSTIC(x) _Pragma GCC diagnostic ignored "-W"#x ++#define DO_PRAGMA(x) _Pragma (#x) ++#define DIGNOSTIC_IGNORE(x) DO_PRAGMA(GCC diagnostic ignored #x) ++#define DIGNOSTIC_PUSH() DO_PRAGMA(GCC diagnostic push) ++#define DIGNOSTIC_POP() DO_PRAGMA(GCC diagnostic pop) ++ ++#define PROVIDER_INFO(_func_entry) \ ++ ({ DIGNOSTIC_PUSH() \ ++ DIGNOSTIC_IGNORE(-Wnested-externs) \ ++ extern void _func_entry(void); \ ++ DIGNOSTIC_POP() \ ++ _func_entry; \ ++ }) ++ ++/* RISC-V extension detection */ ++static inline int has_riscv_ext(const char *ext) { ++ FILE *fp = fopen("/proc/cpuinfo", "r"); ++ if (!fp) return 0; ++ ++ char line[1024]; ++ int found = 0; ++ while (fgets(line, sizeof(line), fp)) { ++ char *isa = strstr(line, "isa"); ++ if (isa) { ++ char *colon = strchr(isa, ':'); ++ if (colon) { ++ char *isa_str = colon + 1; ++ while (*isa_str == ' ' || *isa_str == '\t') isa_str++; ++ if (strstr(isa_str, ext)) { ++ found = 1; ++ break; ++ } ++ } ++ } ++ } ++ fclose(fp); ++ return found; ++} ++ ++#endif /* __ASSEMBLY__ */ ++#endif /* __RISCV64_MULTIBINARY_H__ */ +\ No newline at end of file +diff --git a/mem/Makefile.am b/mem/Makefile.am +index c864f66..f6d244f 100644 +--- a/mem/Makefile.am ++++ b/mem/Makefile.am +@@ -33,7 +33,7 @@ lsrc += mem/mem_zero_detect_base.c + + lsrc_base_aliases += mem/mem_zero_detect_base_aliases.c + lsrc_ppc64le += mem/mem_zero_detect_base_aliases.c +- ++lsrc_riscv64 += mem/mem_zero_detect_base_aliases.c + lsrc_x86_64 += mem/mem_zero_detect_avx.asm \ + mem/mem_zero_detect_sse.asm \ + mem/mem_multibinary.asm +diff --git a/raid/Makefile.am b/raid/Makefile.am +index 5f98668..3d09944 100644 +--- a/raid/Makefile.am ++++ b/raid/Makefile.am +@@ -33,7 +33,7 @@ lsrc += raid/raid_base.c + + lsrc_base_aliases += raid/raid_base_aliases.c + lsrc_ppc64le += raid/raid_base_aliases.c +- ++lsrc_riscv64 += raid/raid_base_aliases.c + lsrc_x86_64 += \ + raid/xor_gen_sse.asm \ + raid/pq_gen_sse.asm \ +-- +2.27.0 + diff --git a/isa-l.spec b/isa-l.spec index 871e5de..0ecbea6 100644 --- a/isa-l.spec +++ b/isa-l.spec @@ -2,11 +2,14 @@ %define isal_devname libisa-l-devel Name: isa-l Version: 2.30.0 -Release: 2 +Release: 3 Summary: Intelligent Storage Acceleration Library License: BSD-3-Clause URL: https://github.com/intel/isa-l Source0: https://github.com/intel/isa-l/archive/refs/tags/v%{version}.tar.gz + +Patch1: Feature-Add-Basic-RISC-V-And-CRC-Vector-support.patch + BuildRequires: yasm gcc BuildRequires: autoconf automake libtool %description @@ -67,6 +70,9 @@ find %{?buildroot} -name *.la -print0 | xargs -r0 rm -f %{_libdir}/pkgconfig/libisal.pc %changelog +* Fri Jul 18 2025 liuqingtao - 2.30.0-3 +- Add basic RISC-V and CRC Vector support + * Sat Feb 25 2023 yaoxin - 2.30.0-2 - Add conflicts for libisal -- Gitee