diff --git a/Sw64-Port-mpfr.patch b/Sw64-Port-mpfr.patch
new file mode 100644
index 0000000000000000000000000000000000000000..46cdd07b1b9a55b5ccda4da26214e61d58cc1b7f
--- /dev/null
+++ b/Sw64-Port-mpfr.patch
@@ -0,0 +1,151 @@
+diff --git a/config.guess b/config.guess
+index f50dcdb..b681fa9 100755
+--- a/config.guess
++++ b/config.guess
+@@ -918,6 +918,17 @@ EOF
+ 	if test "$?" = 0 ; then LIBC=gnulibc1 ; fi
+ 	echo "$UNAME_MACHINE"-unknown-linux-"$LIBC"
+ 	exit ;;
++    sw_64:Linux:*:*)
++        case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
++          SW6)   UNAME_MACHINE=sw_64sw6 ;;
++          SW6A)  UNAME_MACHINE=sw_64sw6a ;;
++          SW6B) UNAME_MACHINE=sw_64sw6b ;;
++          SW8A) UNAME_MACHINE=sw_64sw8a ;;
++        esac
++        objdump --private-headers /bin/sh | grep -q ld.so.1
++        if test "$?" = 0 ; then LIBC=gnulibc1 ; fi
++        echo "$UNAME_MACHINE"-unknown-linux-"$LIBC"
++        exit ;;
+     arc:Linux:*:* | arceb:Linux:*:*)
+ 	echo "$UNAME_MACHINE"-unknown-linux-"$LIBC"
+ 	exit ;;
+@@ -1397,6 +1408,7 @@ EOF
+ 	UNAME_MACHINE=`(uname -p) 2>/dev/null`
+ 	case "$UNAME_MACHINE" in
+ 	    A*) echo alpha-dec-vms ; exit ;;
++	    S*) echo sw_64-dec-vms ; exit ;;
+ 	    I*) echo ia64-dec-vms ; exit ;;
+ 	    V*) echo vax-dec-vms ; exit ;;
+ 	esac ;;
+diff --git a/config.sub b/config.sub
+index 1d8e98b..ca1a38f 100755
+--- a/config.sub
++++ b/config.sub
+@@ -247,6 +247,7 @@ case $basic_machine in
+ 	| aarch64 | aarch64_be \
+ 	| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
+ 	| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
++	| sw_64 | sw_64sw6a | sw_64sw6b | sw_64sw8a \
+ 	| am33_2.0 \
+ 	| arc | arceb \
+ 	| arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \
+@@ -372,6 +373,7 @@ case $basic_machine in
+ 	| alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \
+ 	| alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \
+ 	| alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \
++	| sw_64-* | sw_64sw6a-* | sw_64sw6b-* | sw_64sw8a-* \
+ 	| arm-*  | armbe-* | armle-* | armeb-* | armv*-* \
+ 	| avr-* | avr32-* \
+ 	| ba-* \
+diff --git a/src/mpfr-longlong.h b/src/mpfr-longlong.h
+index 83eda2f..6767d18 100644
+--- a/src/mpfr-longlong.h
++++ b/src/mpfr-longlong.h
+@@ -278,6 +278,96 @@ long __MPN(count_leading_zeros) (UDItype);
+ #endif /* clz using mpn */
+ #endif /* __alpha */
+ 
++//__sw_64 start
++#if defined (__sw_64) && W_TYPE_SIZE == 64
++/* Most sw_64-based machines, except Cray systems. */
++#if defined (__GNUC__)
++#if __GMP_GNUC_PREREQ (3,3)
++#define umul_ppmm(ph, pl, m0, m1) \
++  do {                                                                  \
++    UDItype __m0 = (m0), __m1 = (m1);                                   \
++    (ph) = __builtin_sw_64_umulh (__m0, __m1);                          \
++    (pl) = __m0 * __m1;                                                 \
++  } while (0)
++#else
++#define umul_ppmm(ph, pl, m0, m1) \
++  do {                                                                  \
++    UDItype __m0 = (m0), __m1 = (m1);                                   \
++    __asm__ ("umulh %r1,%2,%0"                                          \
++             : "=r" (ph)                                                \
++             : "%rJ" (__m0), "rI" (__m1));                              \
++    (pl) = __m0 * __m1;                                                 \
++  } while (0)
++#endif
++#define UMUL_TIME 18
++#else /* ! __GNUC__ */
++#include <machine/builtins.h>
++#define umul_ppmm(ph, pl, m0, m1) \
++  do {                                                                  \
++    UDItype __m0 = (m0), __m1 = (m1);                                   \
++    (ph) = __UMULH (__m0, __m1);                                        \
++    (pl) = __m0 * __m1;                                                 \
++  } while (0)
++#endif
++#ifndef LONGLONG_STANDALONE
++#define udiv_qrnnd(q, r, n1, n0, d) \
++  do { UWtype __di;                                                     \
++    __di = __MPN(invert_limb) (d);                                      \
++    udiv_qrnnd_preinv (q, r, n1, n0, d, __di);                          \
++  } while (0)
++#define UDIV_PREINV_ALWAYS  1
++#define UDIV_NEEDS_NORMALIZATION 1
++#define UDIV_TIME 220
++#endif /* LONGLONG_STANDALONE */
++
++/* clz_tab is required in all configurations, since mpn/sw_64/cntlz.asm
++   always goes into libgmp.so, even when not actually used.  */
++#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
++
++#if defined (__GNUC__) && HAVE_HOST_CPU_sw_64_CIX
++#define count_leading_zeros(COUNT,X) \
++  __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X))
++#define count_trailing_zeros(COUNT,X) \
++  __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X))
++#endif /* clz/ctz using cix */
++
++#if ! defined (count_leading_zeros)                             \
++  && defined (__GNUC__) && ! defined (LONGLONG_STANDALONE)
++/* SW_64_CMPBGE_0 gives "cmpbge $31,src,dst", ie. test src bytes == 0.
++   "$31" is written explicitly in the asm, since an "r" constraint won't
++   select reg 31.  There seems no need to worry about "r31" syntax for cray,
++   since gcc itself (pre-release 3.4) emits just $31 in various places.  */
++#define SW_64_CMPBGE_0(dst, src)                                        \
++  do { asm ("cmpgeb $31, %1, %0" : "=r" (dst) : "r" (src)); } while (0)
++/* Zero bytes are turned into bits with cmpbge, a __clz_tab lookup counts
++   them, locating the highest non-zero byte.  A second __clz_tab lookup
++   counts the leading zero bits in that byte, giving the result.  */
++#define count_leading_zeros(count, x)                                   \
++  do {                                                                  \
++    UWtype  __clz__b, __clz__c, __clz__x = (x);                         \
++    SW_64_CMPBGE_0 (__clz__b,  __clz__x);           /* zero bytes */    \
++    __clz__b = __clz_tab [(__clz__b >> 1) ^ 0x7F];  /* 8 to 1 byte */   \
++    __clz__b = __clz__b * 8 - 7;                    /* 57 to 1 shift */ \
++    __clz__x >>= __clz__b;                                              \
++    __clz__c = __clz_tab [__clz__x];                /* 8 to 1 bit */    \
++    __clz__b = 65 - __clz__b;                                           \
++    (count) = __clz__b - __clz__c;                                      \
++  } while (0)
++#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
++#endif /* clz using cmpbge */
++
++#if ! defined (count_leading_zeros) && ! defined (LONGLONG_STANDALONE)
++#if HAVE_ATTRIBUTE_CONST
++long __MPN(count_leading_zeros) (UDItype) __attribute__ ((const));
++#else
++long __MPN(count_leading_zeros) (UDItype);
++#endif
++#define count_leading_zeros(count, x) \
++  ((count) = __MPN(count_leading_zeros) (x))
++#endif /* clz using mpn */
++#endif /* __sw_64 */
++//__sw_64 end
++
+ #if defined (__AVR) && W_TYPE_SIZE == 8
+ #define umul_ppmm(ph, pl, m0, m1) \
+   do {									\
diff --git a/mpfr.spec b/mpfr.spec
index 4e92905a4a639265b7163059850cc96362bd6f98..b76bb5e86a08011cf2f93386630e50dbe08a79a5 100644
--- a/mpfr.spec
+++ b/mpfr.spec
@@ -1,6 +1,6 @@
 Name: mpfr
 Version: 4.1.0
-Release: 3
+Release: 4
 Summary: A C library for multiple-precision floating-point computations
 URL: http://www.mpfr.org/
 License: LGPLv3+ and GPLv3+ and GFDL
@@ -12,6 +12,9 @@ Source0: http://www.mpfr.org/%{name}-%{version}/%{name}-%{version}.tar.xz
 
 Patch6000: backport-allpatches.patch
 
+# Sw64 Port
+Patch7000: Sw64-Port-mpfr.patch
+
 %description
 MPFR is a C library for arbitrary-precision binary floating-point computation 
 with correct rounding, based on Multi-Precision Library. The computation is 
@@ -80,6 +83,9 @@ fi
 %{_libdir}/pkgconfig/mpfr.pc
 
 %changelog
+* Thu Oct 24 2024 swcompiler <lc@wxiat.com> - 4.1.0-4
+- Add Sw64 ISA support
+
 * Mon Nov 27 2023 Wenyu Liu<liuwenyu7@huawei.com> - 4.1.0-3
 - backport upstream patch for 4.1.0.