diff --git a/Backport-JDK-8349632-RISC-V-Add-Zfa-fminm-fmaxm.patch b/Backport-JDK-8349632-RISC-V-Add-Zfa-fminm-fmaxm.patch new file mode 100644 index 0000000000000000000000000000000000000000..9c32401f4443139f25134e3c2c5458da744e8914 --- /dev/null +++ b/Backport-JDK-8349632-RISC-V-Add-Zfa-fminm-fmaxm.patch @@ -0,0 +1,151 @@ +From 38ad78d198d86d01e69eaf4ec8410b30e932b9da Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=E5=BC=A0=E6=B3=BD=E5=BB=BA10053720?= + +Date: Mon, 24 Nov 2025 11:45:28 +0800 +Subject: [PATCH] Backport 8349632: RISC-V: Add Zfa fminm/fmaxm + +--- + src/hotspot/cpu/riscv/assembler_riscv.hpp | 21 ++++++++ + src/hotspot/cpu/riscv/riscv.ad | 60 +++++++++++++++++++++++ + 2 files changed, 81 insertions(+) + +diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp +index 4c167073a..10cce8362 100644 +--- a/src/hotspot/cpu/riscv/assembler_riscv.hpp ++++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp +@@ -1366,6 +1366,27 @@ public: + + #undef INSN + ++// Zfa Instruction Definitions Minimum and Maximum ++#define INSN(NAME, funct3, funct7) \ ++ void NAME(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) { \ ++ assert_cond(UseZfa); \ ++ unsigned insn = 0; \ ++ patch((address)&insn, 6, 0, 0b1010011); \ ++ patch((address)&insn, 14, 12, funct3); \ ++ patch((address)&insn, 31, 25, funct7); \ ++ patch_reg((address)&insn, 7, Rd); \ ++ patch_reg((address)&insn, 15, Rs1); \ ++ patch_reg((address)&insn, 20, Rs2); \ ++ emit(insn); \ ++ } ++ ++ INSN(fminm_s, 0b010, 0b0010100); ++ INSN(fmaxm_s, 0b011, 0b0010100); ++ INSN(fminm_d, 0b010, 0b0010101); ++ INSN(fmaxm_d, 0b011, 0b0010101); ++ ++#undef INSN ++ + // ========================== + // RISC-V Vector Extension + // ========================== +diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad +index 6e381d3f0..064442801 100644 +--- a/src/hotspot/cpu/riscv/riscv.ad ++++ b/src/hotspot/cpu/riscv/riscv.ad +@@ -7467,6 +7467,7 @@ instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{ + + // Math.max(FF)F + instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{ ++ predicate(!UseZfa); + match(Set dst (MaxF src1 src2)); + effect(TEMP_DEF dst, KILL cr); + +@@ -7481,8 +7482,23 @@ instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{ + ins_pipe(pipe_class_default); + %} + ++instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{ ++ predicate(UseZfa); ++ match(Set dst (MaxF src1 src2)); ++ ++ format %{ "maxF $dst, $src1, $src2" %} ++ ++ ins_encode %{ ++ __ fmaxm_s(as_FloatRegister($dst$$reg), ++ as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg)); ++ %} ++ ++ ins_pipe(pipe_class_default); ++%} ++ + // Math.min(FF)F + instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{ ++ predicate(!UseZfa); + match(Set dst (MinF src1 src2)); + effect(TEMP_DEF dst, KILL cr); + +@@ -7497,8 +7513,23 @@ instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{ + ins_pipe(pipe_class_default); + %} + ++instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{ ++ predicate(UseZfa); ++ match(Set dst (MinF src1 src2)); ++ ++ format %{ "minF $dst, $src1, $src2" %} ++ ++ ins_encode %{ ++ __ fminm_s(as_FloatRegister($dst$$reg), ++ as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg)); ++ %} ++ ++ ins_pipe(pipe_class_default); ++%} ++ + // Math.max(DD)D + instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{ ++ predicate(!UseZfa); + match(Set dst (MaxD src1 src2)); + effect(TEMP_DEF dst, KILL cr); + +@@ -7513,8 +7544,23 @@ instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{ + ins_pipe(pipe_class_default); + %} + ++instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{ ++ predicate(UseZfa); ++ match(Set dst (MaxD src1 src2)); ++ ++ format %{ "maxD $dst, $src1, $src2" %} ++ ++ ins_encode %{ ++ __ fmaxm_d(as_FloatRegister($dst$$reg), ++ as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg)); ++ %} ++ ++ ins_pipe(pipe_class_default); ++%} ++ + // Math.min(DD)D + instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{ ++ predicate(!UseZfa); + match(Set dst (MinD src1 src2)); + effect(TEMP_DEF dst, KILL cr); + +@@ -7529,6 +7575,20 @@ instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{ + ins_pipe(pipe_class_default); + %} + ++instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{ ++ predicate(UseZfa); ++ match(Set dst (MinD src1 src2)); ++ ++ format %{ "minD $dst, $src1, $src2" %} ++ ++ ins_encode %{ ++ __ fminm_d(as_FloatRegister($dst$$reg), ++ as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg)); ++ %} ++ ++ ins_pipe(pipe_class_default); ++%} ++ + // Float.isInfinite + instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src) + %{ +-- +2.25.1 + diff --git a/openjdk-21.spec b/openjdk-21.spec index c0ed2a6f9ca66741d748b6fa11457884b8541c02..a6e5f6c8696cf1dcf8e25f3dae38ad302544f0f6 100644 --- a/openjdk-21.spec +++ b/openjdk-21.spec @@ -905,7 +905,7 @@ Name: java-21-%{origin} Version: %{newjavaver}.%{buildver} # This package needs `.rolling` as part of Release so as to not conflict on install with # java-X-openjdk. I.e. when latest rolling release is also an LTS release packaged as -Release: 5 +Release: 6 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons @@ -1078,6 +1078,7 @@ Patch3021: Backport-JDK-8315743-8315856-8344010-8344382-RISC-V-Use-Zacas-extensi Patch3022: Backport-JDK-8319778-8324881-8319797-8319900-Recursive-lightweight-locking-riscv64-implementation.patch Patch3023: Backport-JDK-8345351-8356159-RISC-V-Add-Zabha.patch Patch3024: Backport-JDK-8344306-8352607-8330213-8352504-8352248-RISC-V-Add-zicond.patch +Patch3025: Backport-JDK-8349632-RISC-V-Add-Zfa-fminm-fmaxm.patch BuildRequires: autoconf BuildRequires: automake @@ -1396,6 +1397,7 @@ pushd %{top_level_dir_name} %patch3022 -p1 %patch3023 -p1 %patch3024 -p1 +%patch3025 -p1 popd %endif @@ -1953,6 +1955,9 @@ cjc.mainProgram(args) -- the returns from copy_jdk_configs.lua should not affect %changelog +* Tue Nov 25 2025 zhangzejian - 1:21.0.9.10-6 +- RISC-V Add Zfa fminm fmaxm + * Thu Nov 20 2025 zhangshihui - 1:21.0.9.10-5 - RISC-V add Zicond