From 08f2f8f55dccec83535d45b833033b541b69b4da Mon Sep 17 00:00:00 2001
From: vicwang-oc <vicwang-oc@zhaoxin.com>
Date: Fri, 5 Sep 2025 17:57:23 +0800
Subject: [PATCH] add zhaoxin processors support.

---
 openjdk-latest.spec              |  7 ++-
 zhaoxin-processors-support.patch | 81 ++++++++++++++++++++++++++++++++
 2 files changed, 87 insertions(+), 1 deletion(-)
 create mode 100644 zhaoxin-processors-support.patch

diff --git a/openjdk-latest.spec b/openjdk-latest.spec
index b946bdd..2fbfbd0 100644
--- a/openjdk-latest.spec
+++ b/openjdk-latest.spec
@@ -898,7 +898,7 @@ Name:    java-latest-%{origin}
 Version: %{newjavaver}.%{buildver}
 # This package needs `.rolling` as part of Release so as to not conflict on install with
 # java-X-openjdk. I.e. when latest rolling release is also an LTS release packaged as
-Release: 2
+Release: 3
 
 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons
 # and this change was brought into RHEL-4. java-1.5.0-ibm packages
@@ -980,6 +980,7 @@ Patch8: downgrade-the-glibc-symver-of-log2f-posix_spawn.patch
 
 # 23.0.1
 Patch9: 8332854-Unable-to-build-openjdk-with-with-harfbuzz=system.patch
+Patch10: zhaoxin-processors-support.patch
 
 ############################################
 #
@@ -1218,6 +1219,7 @@ pushd %{top_level_dir_name}
 %patch7 -p1
 %patch8 -p1
 %patch9 -p1
+%patch10 -p1
 popd # openjdk
 
 %patch1000
@@ -1795,6 +1797,9 @@ cjc.mainProgram(args) -- the returns from copy_jdk_configs.lua should not affect
 
 
 %changelog
+* Fri Sep 5 2025 vicwang-oc <vicwang-oc@zhaoxin.com> - 1:23.0.1.11-3
+- add zhaoxin processors support.
+
 * Mon Jun 9 2025 Benshuai5D <zhanngyunbo7@huawei.com> - 1:23.0.1.11-2
 - remove OpenJDK23U-jdk tar
 
diff --git a/zhaoxin-processors-support.patch b/zhaoxin-processors-support.patch
new file mode 100644
index 0000000..1de1705
--- /dev/null
+++ b/zhaoxin-processors-support.patch
@@ -0,0 +1,81 @@
+diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp
+index f5389d0ef90..9126ea35365 100644
+--- a/src/hotspot/cpu/x86/vm_version_x86.cpp
++++ b/src/hotspot/cpu/x86/vm_version_x86.cpp
+@@ -887,10 +887,18 @@ void VM_Version::get_processor_features() {
+   if (UseSSE < 1)
+     _features &= ~CPU_SSE;
+ 
+-  //since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0.
+-  if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
+-    UseAVX = 0;
+-  }
++  // ZX cpus specific settings
++  if (is_zx() && FLAG_IS_DEFAULT(UseAVX)) {
++    if (cpu_family() == 7) {
++      if (extended_cpu_model() == 0x5B || extended_cpu_model() == 0x6B) {
++	UseAVX = 1;
++      } else if (extended_cpu_model() == 0x1B || extended_cpu_model() == 0x3B) {
++        UseAVX = 0;
++      }
++    } else if (cpu_family() == 6) {
++      UseAVX = 0;
++    }
++  }    
+ 
+   // UseSSE is set to the smaller of what hardware supports and what
+   // the command line requires.  I.e., you cannot set UseSSE to 2 on
+@@ -2637,6 +2645,7 @@ void VM_Version::resolve_cpu_information_details(void) {
+ 
+ const char* VM_Version::cpu_family_description(void) {
+   int cpu_family_id = extended_cpu_family();
++  int cpu_model_id = extended_cpu_model();
+   if (is_amd()) {
+     if (cpu_family_id < ExtendedFamilyIdLength_AMD) {
+       return _family_id_amd[cpu_family_id];
+@@ -2650,6 +2659,22 @@ const char* VM_Version::cpu_family_description(void) {
+       return _family_id_intel[cpu_family_id];
+     }
+   }
++  if (is_zx()) {
++    if (cpu_family_id == 7) {
++      switch (cpu_model_id) {
++	case 0x1B:
++	  return "wudaokou";
++	case 0x3B:
++	  return "lujiazui";
++	case 0x5B:
++	  return "yongfeng";
++	case 0x6B:
++	  return "shijidadao";
++      }
++    } else if (cpu_family_id == 6) {
++	return "zhangjiang";
++    }
++  }
+   if (is_hygon()) {
+     return "Dhyana";
+   }
+@@ -2669,6 +2694,9 @@ int VM_Version::cpu_type_description(char* const buf, size_t buf_len) {
+   } else if (is_amd()) {
+     cpu_type = "AMD";
+     x64 = cpu_is_em64t() ? " AMD64" : "";
++  } else if (is_zx()) {
++    cpu_type = "Zhaoxin";
++    x64 = cpu_is_em64t() ? " x86_64" : "";
+   } else if (is_hygon()) {
+     cpu_type = "Hygon";
+     x64 = cpu_is_em64t() ? " AMD64" : "";
+@@ -3239,6 +3267,12 @@ int VM_Version::allocate_prefetch_distance(bool use_watermark_prefetch) {
+     } else {
+       return 128; // Athlon
+     }
++  } else if (is_zx()) {
++    if (supports_sse2()) {
++      return 256;
++    } else {
++      return 128;
++    }
+   } else { // Intel
+     if (supports_sse3() && cpu_family() == 6) {
+       if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
-- 
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