diff --git a/AllWinner-Pine64-bits.patch b/AllWinner-Pine64-bits.patch deleted file mode 100644 index 569afc8d45bca6a63f34d41a0abc303158b033bf..0000000000000000000000000000000000000000 --- a/AllWinner-Pine64-bits.patch +++ /dev/null @@ -1,2172 +0,0 @@ -From 2c213379d9ec786480a655f8c5687b2df376017f Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 10 Mar 2020 12:27:15 +0000 -Subject: [PATCH 1/9] arm: dts: AllWinner: sync sun50i-a64.dtsi to 5.6-rc1 - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/sun50i-a64.dtsi | 472 ++++++++++++++++++++++++++++------- - 1 file changed, 387 insertions(+), 85 deletions(-) - -diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi -index ff41abc96a..862b47dc9d 100644 ---- a/arch/arm/dts/sun50i-a64.dtsi -+++ b/arch/arm/dts/sun50i-a64.dtsi -@@ -1,46 +1,7 @@ --/* -- * Copyright (C) 2016 ARM Ltd. -- * based on the Allwinner H3 dtsi: -- * Copyright (C) 2015 Jens Kuske -- * -- * This file is dual-licensed: you can use it either under the terms -- * of the GPL or the X11 license, at your option. Note that this dual -- * licensing only applies to this file, and not this project as a -- * whole. -- * -- * a) This file is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of the -- * License, or (at your option) any later version. -- * -- * This file is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * Or, alternatively, -- * -- * b) Permission is hereby granted, free of charge, to any person -- * obtaining a copy of this software and associated documentation -- * files (the "Software"), to deal in the Software without -- * restriction, including without limitation the rights to use, -- * copy, modify, merge, publish, distribute, sublicense, and/or -- * sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following -- * conditions: -- * -- * The above copyright notice and this permission notice shall be -- * included in all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. -- */ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+// Copyright (C) 2016 ARM Ltd. -+// based on the Allwinner H3 dtsi: -+// Copyright (C) 2015 Jens Kuske - - #include - #include -@@ -49,6 +10,7 @@ - #include - #include - #include -+#include - - / { - interrupt-parent = <&gic>; -@@ -84,35 +46,47 @@ - #size-cells = <0>; - - cpu0: cpu@0 { -- compatible = "arm,cortex-a53", "arm,armv8"; -+ compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&L2>; -+ clocks = <&ccu 21>; -+ clock-names = "cpu"; -+ #cooling-cells = <2>; - }; - - cpu1: cpu@1 { -- compatible = "arm,cortex-a53", "arm,armv8"; -+ compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&L2>; -+ clocks = <&ccu 21>; -+ clock-names = "cpu"; -+ #cooling-cells = <2>; - }; - - cpu2: cpu@2 { -- compatible = "arm,cortex-a53", "arm,armv8"; -+ compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - next-level-cache = <&L2>; -+ clocks = <&ccu 21>; -+ clock-names = "cpu"; -+ #cooling-cells = <2>; - }; - - cpu3: cpu@3 { -- compatible = "arm,cortex-a53", "arm,armv8"; -+ compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - next-level-cache = <&L2>; -+ clocks = <&ccu 21>; -+ clock-names = "cpu"; -+ #cooling-cells = <2>; - }; - - L2: l2-cache { -@@ -139,15 +113,16 @@ - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; -- clock-output-names = "osc32k"; -+ clock-output-names = "ext-osc32k"; - }; - -- iosc: internal-osc-clk { -- #clock-cells = <0>; -- compatible = "fixed-clock"; -- clock-frequency = <16000000>; -- clock-accuracy = <300000000>; -- clock-output-names = "iosc"; -+ pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { -@@ -155,6 +130,30 @@ - method = "smc"; - }; - -+ sound: sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "sun50i-a64-audio"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,frame-master = <&cpudai>; -+ simple-audio-card,bitclock-master = <&cpudai>; -+ simple-audio-card,mclk-fs = <128>; -+ simple-audio-card,aux-devs = <&codec_analog>; -+ simple-audio-card,routing = -+ "Left DAC", "AIF1 Slot 0 Left", -+ "Right DAC", "AIF1 Slot 0 Right", -+ "AIF1 Slot 0 Left ADC", "Left ADC", -+ "AIF1 Slot 0 Right ADC", "Right ADC"; -+ status = "disabled"; -+ -+ cpudai: simple-audio-card,cpu { -+ sound-dai = <&dai>; -+ }; -+ -+ link_codec: simple-audio-card,codec { -+ sound-dai = <&codec>; -+ }; -+ }; -+ - sound_spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "On-board SPDIF"; -@@ -175,6 +174,7 @@ - - timer { - compatible = "arm,armv8-timer"; -+ allwinner,erratum-unknown1; - interrupts = , - ; - }; - -+ thermal-zones { -+ cpu_thermal: cpu0-thermal { -+ /* milliseconds */ -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 0>; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert0>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ map1 { -+ trip = <&cpu_alert1>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ -+ trips { -+ cpu_alert0: cpu_alert0 { -+ /* milliCelsius */ -+ temperature = <75000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu_alert1: cpu_alert1 { -+ /* milliCelsius */ -+ temperature = <90000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ -+ cpu_crit: cpu_crit { -+ /* milliCelsius */ -+ temperature = <110000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ gpu0_thermal: gpu0-thermal { -+ /* milliseconds */ -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 1>; -+ }; -+ -+ gpu1_thermal: gpu1-thermal { -+ /* milliseconds */ -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 2>; -+ }; -+ }; -+ - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - -- de2@1000000 { -+ bus@1000000 { - compatible = "allwinner,sun50i-a64-de2"; - reg = <0x1000000 0x400000>; - allwinner,sram = <&de2_sram 1>; -@@ -202,10 +265,10 @@ - display_clocks: clock@0 { - compatible = "allwinner,sun50i-a64-de2-clk"; - reg = <0x0 0x100000>; -- clocks = <&ccu CLK_DE>, -- <&ccu CLK_BUS_DE>; -- clock-names = "mod", -- "bus"; -+ clocks = <&ccu CLK_BUS_DE>, -+ <&ccu CLK_DE>; -+ clock-names = "bus", -+ "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; -@@ -225,11 +288,19 @@ - #size-cells = <0>; - - mixer0_out: port@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; - reg = <1>; - -- mixer0_out_tcon0: endpoint { -+ mixer0_out_tcon0: endpoint@0 { -+ reg = <0>; - remote-endpoint = <&tcon0_in_mixer0>; - }; -+ -+ mixer0_out_tcon1: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&tcon1_in_mixer0>; -+ }; - }; - }; - }; -@@ -248,9 +319,17 @@ - #size-cells = <0>; - - mixer1_out: port@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; - reg = <1>; - -- mixer1_out_tcon1: endpoint { -+ mixer1_out_tcon0: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&tcon0_in_mixer1>; -+ }; -+ -+ mixer1_out_tcon1: endpoint@1 { -+ reg = <1>; - remote-endpoint = <&tcon1_in_mixer1>; - }; - }; -@@ -259,8 +338,7 @@ - }; - - syscon: syscon@1c00000 { -- compatible = "allwinner,sun50i-a64-system-control", -- "syscon"; -+ compatible = "allwinner,sun50i-a64-system-control"; - reg = <0x01c00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -@@ -278,6 +356,20 @@ - reg = <0x0000 0x28000>; - }; - }; -+ -+ sram_c1: sram@1d00000 { -+ compatible = "mmio-sram"; -+ reg = <0x01d00000 0x40000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x01d00000 0x40000>; -+ -+ ve_sram: sram-section@0 { -+ compatible = "allwinner,sun50i-a64-sram-c1", -+ "allwinner,sun4i-a10-sram-c1"; -+ reg = <0x000000 0x40000>; -+ }; -+ }; - }; - - dma: dma-controller@1c02000 { -@@ -299,6 +391,7 @@ - clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; - clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; -+ #clock-cells = <0>; - resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; - reset-names = "lcd", "lvds"; - -@@ -315,12 +408,23 @@ - reg = <0>; - remote-endpoint = <&mixer0_out_tcon0>; - }; -+ -+ tcon0_in_mixer1: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&mixer1_out_tcon0>; -+ }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; -+ -+ tcon0_out_dsi: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&dsi_in_tcon0>; -+ allwinner,tcon-channel = <1>; -+ }; - }; - }; - }; -@@ -340,9 +444,17 @@ - #size-cells = <0>; - - tcon1_in: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; - reg = <0>; - -- tcon1_in_mixer1: endpoint { -+ tcon1_in_mixer0: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&mixer0_out_tcon1>; -+ }; -+ -+ tcon1_in_mixer1: endpoint@1 { -+ reg = <1>; - remote-endpoint = <&mixer1_out_tcon1>; - }; - }; -@@ -360,6 +472,17 @@ - }; - }; - -+ video-codec@1c0e000 { -+ compatible = "allwinner,sun50i-a64-video-engine"; -+ reg = <0x01c0e000 0x1000>; -+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, -+ <&ccu CLK_DRAM_VE>; -+ clock-names = "ahb", "mod", "ram"; -+ resets = <&ccu RST_BUS_VE>; -+ interrupts = ; -+ allwinner,sram = <&ve_sram 1>; -+ }; -+ - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun50i-a64-mmc"; - reg = <0x01c0f000 0x1000>; -@@ -405,6 +528,21 @@ - sid: eeprom@1c14000 { - compatible = "allwinner,sun50i-a64-sid"; - reg = <0x1c14000 0x400>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ ths_calibration: thermal-sensor-calibration@34 { -+ reg = <0x34 0x8>; -+ }; -+ }; -+ -+ crypto: crypto@1c15000 { -+ compatible = "allwinner,sun50i-a64-crypto"; -+ reg = <0x01c15000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; -+ clock-names = "bus", "mod"; -+ resets = <&ccu RST_BUS_CE>; - }; - - usb_otg: usb@1c19000 { -@@ -417,6 +555,7 @@ - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; -+ dr_mode = "otg"; - status = "disabled"; - }; - -@@ -491,7 +630,7 @@ - ccu: clock@1c20000 { - compatible = "allwinner,sun50i-a64-ccu"; - reg = <0x01c20000 0x400>; -- clocks = <&osc24M>, <&osc32k>; -+ clocks = <&osc24M>, <&rtc 0>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; -@@ -503,22 +642,45 @@ - interrupts = , - , - ; -- clocks = <&ccu 58>; -+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; -+ clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - -- i2c0_pins: i2c0_pins { -+ csi_pins: csi-pins { -+ pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", -+ "PE7", "PE8", "PE9", "PE10", "PE11"; -+ function = "csi"; -+ }; -+ -+ /omit-if-no-ref/ -+ csi_mclk_pin: csi-mclk-pin { -+ pins = "PE1"; -+ function = "csi"; -+ }; -+ -+ i2c0_pins: i2c0-pins { - pins = "PH0", "PH1"; - function = "i2c0"; - }; - -- i2c1_pins: i2c1_pins { -+ i2c1_pins: i2c1-pins { - pins = "PH2", "PH3"; - function = "i2c1"; - }; - -+ /omit-if-no-ref/ -+ lcd_rgb666_pins: lcd-rgb666-pins { -+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", -+ "PD5", "PD6", "PD7", "PD8", "PD9", -+ "PD10", "PD11", "PD12", "PD13", -+ "PD14", "PD15", "PD16", "PD17", -+ "PD18", "PD19", "PD20", "PD21"; -+ function = "lcd0"; -+ }; -+ - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; -@@ -551,19 +713,19 @@ - bias-pull-up; - }; - -- pwm_pin: pwm_pin { -+ pwm_pin: pwm-pin { - pins = "PD22"; - function = "pwm"; - }; - -- rmii_pins: rmii_pins { -+ rmii_pins: rmii-pins { - pins = "PD10", "PD11", "PD13", "PD14", "PD17", - "PD18", "PD19", "PD20", "PD22", "PD23"; - function = "emac"; - drive-strength = <40>; - }; - -- rgmii_pins: rgmii_pins { -+ rgmii_pins: rgmii-pins { - pins = "PD8", "PD9", "PD10", "PD11", "PD12", - "PD13", "PD15", "PD16", "PD17", "PD18", - "PD19", "PD20", "PD21", "PD22", "PD23"; -@@ -571,17 +733,17 @@ - drive-strength = <40>; - }; - -- spdif_tx_pin: spdif { -+ spdif_tx_pin: spdif-tx-pin { - pins = "PH8"; - function = "spdif"; - }; - -- spi0_pins: spi0 { -+ spi0_pins: spi0-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - -- spi1_pins: spi1 { -+ spi1_pins: spi1-pins { - pins = "PD0", "PD1", "PD2", "PD3"; - function = "spi1"; - }; -@@ -591,12 +753,12 @@ - function = "uart0"; - }; - -- uart1_pins: uart1_pins { -+ uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - -- uart1_rts_cts_pins: uart1_rts_cts_pins { -+ uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; -@@ -638,6 +800,14 @@ - status = "disabled"; - }; - -+ lradc: lradc@1c21800 { -+ compatible = "allwinner,sun50i-a64-lradc", -+ "allwinner,sun8i-a83t-r-lradc"; -+ reg = <0x01c21800 0x400>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-i2s", -@@ -666,6 +836,41 @@ - status = "disabled"; - }; - -+ dai: dai@1c22c00 { -+ #sound-dai-cells = <0>; -+ compatible = "allwinner,sun50i-a64-codec-i2s"; -+ reg = <0x01c22c00 0x200>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; -+ clock-names = "apb", "mod"; -+ resets = <&ccu RST_BUS_CODEC>; -+ dmas = <&dma 15>, <&dma 15>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ -+ codec: codec@1c22e00 { -+ #sound-dai-cells = <0>; -+ compatible = "allwinner,sun8i-a33-codec"; -+ reg = <0x01c22e00 0x600>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; -+ clock-names = "bus", "mod"; -+ status = "disabled"; -+ }; -+ -+ ths: thermal-sensor@1c25000 { -+ compatible = "allwinner,sun50i-a64-ths"; -+ reg = <0x01c25000 0x100>; -+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; -+ clock-names = "bus", "mod"; -+ interrupts = ; -+ resets = <&ccu RST_BUS_THS>; -+ nvmem-cells = <&ths_calibration>; -+ nvmem-cell-names = "calibration"; -+ #thermal-sensor-cells = <1>; -+ }; -+ - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; -@@ -727,6 +932,8 @@ - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; -@@ -738,6 +945,8 @@ - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; -@@ -808,6 +1017,28 @@ - }; - }; - -+ mali: gpu@1c40000 { -+ compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; -+ reg = <0x01c40000 0x10000>; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ ; -+ interrupt-names = "gp", -+ "gpmmu", -+ "pp0", -+ "ppmmu0", -+ "pp1", -+ "ppmmu1", -+ "pmu"; -+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; -+ clock-names = "bus", "core"; -+ resets = <&ccu RST_BUS_GPU>; -+ }; -+ - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, -@@ -830,6 +1061,51 @@ - status = "disabled"; - }; - -+ csi: csi@1cb0000 { -+ compatible = "allwinner,sun50i-a64-csi"; -+ reg = <0x01cb0000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_CSI>, -+ <&ccu CLK_CSI_SCLK>, -+ <&ccu CLK_DRAM_CSI>; -+ clock-names = "bus", "mod", "ram"; -+ resets = <&ccu RST_BUS_CSI>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&csi_pins>; -+ status = "disabled"; -+ }; -+ -+ dsi: dsi@1ca0000 { -+ compatible = "allwinner,sun50i-a64-mipi-dsi"; -+ reg = <0x01ca0000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_MIPI_DSI>; -+ resets = <&ccu RST_BUS_MIPI_DSI>; -+ phys = <&dphy>; -+ phy-names = "dphy"; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port { -+ dsi_in_tcon0: endpoint { -+ remote-endpoint = <&tcon0_out_dsi>; -+ }; -+ }; -+ }; -+ -+ dphy: d-phy@1ca1000 { -+ compatible = "allwinner,sun50i-a64-mipi-dphy", -+ "allwinner,sun6i-a31-mipi-dphy"; -+ reg = <0x01ca1000 0x1000>; -+ clocks = <&ccu CLK_BUS_MIPI_DSI>, -+ <&ccu CLK_DSI_DPHY>; -+ clock-names = "bus", "mod"; -+ resets = <&ccu RST_BUS_MIPI_DSI>; -+ status = "disabled"; -+ #phy-cells = <0>; -+ }; -+ - hdmi: hdmi@1ee0000 { - compatible = "allwinner,sun50i-a64-dw-hdmi", - "allwinner,sun8i-a83t-dw-hdmi"; -@@ -842,7 +1118,7 @@ - resets = <&ccu RST_BUS_HDMI1>; - reset-names = "ctrl"; - phys = <&hdmi_phy>; -- phy-names = "hdmi-phy"; -+ phy-names = "phy"; - status = "disabled"; - - ports { -@@ -867,7 +1143,7 @@ - compatible = "allwinner,sun50i-a64-hdmi-phy"; - reg = <0x01ef0000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, -- <&ccu 7>; -+ <&ccu CLK_PLL_VIDEO0>; - clock-names = "bus", "mod", "pll-0"; - resets = <&ccu RST_BUS_HDMI0>; - reset-names = "phy"; -@@ -875,11 +1151,12 @@ - }; - - rtc: rtc@1f00000 { -- compatible = "allwinner,sun6i-a31-rtc"; -- reg = <0x01f00000 0x54>; -+ compatible = "allwinner,sun50i-a64-rtc", -+ "allwinner,sun8i-h3-rtc"; -+ reg = <0x01f00000 0x400>; - interrupts = , - ; -- clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; -+ clock-output-names = "osc32k", "osc32k-out", "iosc"; - clocks = <&osc32k>; - #clock-cells = <1>; - }; -@@ -896,13 +1173,19 @@ - r_ccu: clock@1f01400 { - compatible = "allwinner,sun50i-a64-r-ccu"; - reg = <0x01f01400 0x100>; -- clocks = <&osc24M>, <&osc32k>, <&iosc>, -- <&ccu 11>; -+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, -+ <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -+ codec_analog: codec-analog@1f015c0 { -+ compatible = "allwinner,sun50i-a64-codec-analog"; -+ reg = <0x01f015c0 0x4>; -+ status = "disabled"; -+ }; -+ - r_i2c: i2c@1f02400 { - compatible = "allwinner,sun50i-a64-i2c", - "allwinner,sun6i-a31-i2c"; -@@ -915,6 +1198,19 @@ - #size-cells = <0>; - }; - -+ r_ir: ir@1f02000 { -+ compatible = "allwinner,sun50i-a64-ir", -+ "allwinner,sun6i-a31-ir"; -+ reg = <0x01f02000 0x400>; -+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; -+ clock-names = "apb", "ir"; -+ resets = <&r_ccu RST_APB0_IR>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&r_ir_rx_pin>; -+ status = "disabled"; -+ }; -+ - r_pwm: pwm@1f03800 { - compatible = "allwinner,sun50i-a64-pwm", - "allwinner,sun5i-a13-pwm"; -@@ -942,12 +1238,17 @@ - function = "s_i2c"; - }; - -- r_pwm_pin: pwm { -+ r_ir_rx_pin: r-ir-rx-pin { -+ pins = "PL11"; -+ function = "s_cir_rx"; -+ }; -+ -+ r_pwm_pin: r-pwm-pin { - pins = "PL10"; - function = "s_pwm"; - }; - -- r_rsb_pins: rsb { -+ r_rsb_pins: r-rsb-pins { - pins = "PL0", "PL1"; - function = "s_rsb"; - }; -@@ -972,6 +1273,7 @@ - "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; -+ clocks = <&osc24M>; - }; - }; - }; --- -2.26.0 - -From fbe1642e24188e96f20ab5a3b003597288104e31 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 10 Mar 2020 15:32:51 +0000 -Subject: [PATCH 2/9] arm: dts: AllWinner: sync axp803.dtsi to 5.6-rc1 - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/axp803.dtsi | 82 ++++++++++++++++++++-------------------- - 1 file changed, 41 insertions(+), 41 deletions(-) - -diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi -index e5eae8bafc..10e9186a76 100644 ---- a/arch/arm/dts/axp803.dtsi -+++ b/arch/arm/dts/axp803.dtsi -@@ -1,44 +1,5 @@ --/* -- * Copyright 2017 Icenowy Zheng -- * -- * This file is dual-licensed: you can use it either under the terms -- * of the GPL or the X11 license, at your option. Note that this dual -- * licensing only applies to this file, and not this project as a -- * whole. -- * -- * a) This file is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of the -- * License, or (at your option) any later version. -- * -- * This file is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * Or, alternatively, -- * -- * b) Permission is hereby granted, free of charge, to any person -- * obtaining a copy of this software and associated documentation -- * files (the "Software"), to deal in the Software without -- * restriction, including without limitation the rights to use, -- * copy, modify, merge, publish, distribute, sublicense, and/or -- * sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following -- * conditions: -- * -- * The above copyright notice and this permission notice shall be -- * included in all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. -- */ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+// Copyright 2017 Icenowy Zheng - - /* - * AXP803 Integrated Power Management Chip -@@ -49,6 +10,39 @@ - interrupt-controller; - #interrupt-cells = <1>; - -+ ac_power_supply: ac-power-supply { -+ compatible = "x-powers,axp803-ac-power-supply", -+ "x-powers,axp813-ac-power-supply"; -+ status = "disabled"; -+ }; -+ -+ axp_adc: adc { -+ compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; -+ #io-channel-cells = <1>; -+ }; -+ -+ axp_gpio: gpio { -+ compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ gpio0_ldo: gpio0-ldo { -+ pins = "GPIO0"; -+ function = "ldo"; -+ }; -+ -+ gpio1_ldo: gpio1-ldo { -+ pins = "GPIO1"; -+ function = "ldo"; -+ }; -+ }; -+ -+ battery_power_supply: battery-power-supply { -+ compatible = "x-powers,axp803-battery-power-supply", -+ "x-powers,axp813-battery-power-supply"; -+ status = "disabled"; -+ }; -+ - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <3000>; -@@ -152,4 +146,10 @@ - status = "disabled"; - }; - }; -+ -+ usb_power_supply: usb-power-supply { -+ compatible = "x-powers,axp803-usb-power-supply", -+ "x-powers,axp813-usb-power-supply"; -+ status = "disabled"; -+ }; - }; --- -2.26.0 - -From f44987a0ccf064f9da4a119e7700605a3eb56447 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 10 Mar 2020 15:34:58 +0000 -Subject: [PATCH 3/9] arm: dts: AllWinner: sync sun50i-a64.dtsi to 5.7-rc1 - -Adds the following two patches queued for 5.7: -- arm64: dts: sun50i-a64: Add i2c2 pins -- arm64: dts: allwinner: a64: Add MBUS controller node - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/sun50i-a64.dtsi | 16 +++++++++++++++- - 1 file changed, 15 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi -index 862b47dc9d..89a60fcf5a 100644 ---- a/arch/arm/dts/sun50i-a64.dtsi -+++ b/arch/arm/dts/sun50i-a64.dtsi -@@ -671,6 +671,11 @@ - function = "i2c1"; - }; - -+ i2c2_pins: i2c2-pins { -+ pins = "PE14", "PE15"; -+ function = "i2c2"; -+ }; -+ - /omit-if-no-ref/ - lcd_rgb666_pins: lcd-rgb666-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", -@@ -958,12 +963,13 @@ - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - -- - spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; -@@ -1061,6 +1067,14 @@ - status = "disabled"; - }; - -+ mbus: dram-controller@1c62000 { -+ compatible = "allwinner,sun50i-a64-mbus"; -+ reg = <0x01c62000 0x1000>; -+ clocks = <&ccu 112>; -+ dma-ranges = <0x00000000 0x40000000 0xc0000000>; -+ #interconnect-cells = <1>; -+ }; -+ - csi: csi@1cb0000 { - compatible = "allwinner,sun50i-a64-csi"; - reg = <0x01cb0000 0x1000>; --- -2.26.0 - -From 465dbf297edb9881e79c1b81fef8d9328fbaf7ad Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 10 Mar 2020 15:37:39 +0000 -Subject: [PATCH 4/9] arm: dts: allwinner: Add initial support for Pine64 - PinePhone - -The initial DT for the PinePhone models are queued for 5.7-rc1: -- 1.0: Early Developer Batch -- 1.1: Braveheart Batch - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/Makefile | 2 + - arch/arm/dts/sun50i-a64-pinephone-1.0.dts | 11 + - arch/arm/dts/sun50i-a64-pinephone-1.1.dts | 11 + - arch/arm/dts/sun50i-a64-pinephone.dtsi | 379 ++++++++++++++++++++++ - 4 files changed, 403 insertions(+) - create mode 100644 arch/arm/dts/sun50i-a64-pinephone-1.0.dts - create mode 100644 arch/arm/dts/sun50i-a64-pinephone-1.1.dts - create mode 100644 arch/arm/dts/sun50i-a64-pinephone.dtsi - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 820ee9733a..fb7516ee83 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -573,6 +573,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ - sun50i-a64-pine64-plus.dtb \ - sun50i-a64-pine64.dtb \ - sun50i-a64-pinebook.dtb \ -+ sun50i-a64-pinephone-1.0.dtb \ -+ sun50i-a64-pinephone-1.1.dtb \ - sun50i-a64-sopine-baseboard.dtb \ - sun50i-a64-teres-i.dtb - dtb-$(CONFIG_MACH_SUN9I) += \ -diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts -new file mode 100644 -index 0000000000..0c42272106 ---- /dev/null -+++ b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts -@@ -0,0 +1,11 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+// Copyright (C) 2020 Ondrej Jirman -+ -+/dts-v1/; -+ -+#include "sun50i-a64-pinephone.dtsi" -+ -+/ { -+ model = "Pine64 PinePhone Developer Batch (1.0)"; -+ compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64"; -+}; -diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts -new file mode 100644 -index 0000000000..06a775c416 ---- /dev/null -+++ b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts -@@ -0,0 +1,11 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+// Copyright (C) 2020 Ondrej Jirman -+ -+/dts-v1/; -+ -+#include "sun50i-a64-pinephone.dtsi" -+ -+/ { -+ model = "Pine64 PinePhone Braveheart (1.1)"; -+ compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64"; -+}; -diff --git a/arch/arm/dts/sun50i-a64-pinephone.dtsi b/arch/arm/dts/sun50i-a64-pinephone.dtsi -new file mode 100644 -index 0000000000..cefda145c3 ---- /dev/null -+++ b/arch/arm/dts/sun50i-a64-pinephone.dtsi -@@ -0,0 +1,379 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+// Copyright (C) 2019 Icenowy Zheng -+// Copyright (C) 2020 Martijn Braam -+// Copyright (C) 2020 Ondrej Jirman -+ -+#include "sun50i-a64.dtsi" -+#include "sun50i-a64-cpu-opp.dtsi" -+ -+#include -+#include -+#include -+#include -+ -+/ { -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ blue { -+ function = LED_FUNCTION_INDICATOR; -+ color = ; -+ gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ -+ }; -+ -+ green { -+ function = LED_FUNCTION_INDICATOR; -+ color = ; -+ gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ -+ }; -+ -+ red { -+ function = LED_FUNCTION_INDICATOR; -+ color = ; -+ gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ -+ }; -+ }; -+ -+ speaker_amp: audio-amplifier { -+ compatible = "simple-audio-amplifier"; -+ enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ -+ sound-name-prefix = "Speaker Amp"; -+ }; -+ -+ vibrator { -+ compatible = "gpio-vibrator"; -+ enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ -+ vcc-supply = <®_dcdc1>; -+ }; -+}; -+ -+&codec { -+ status = "okay"; -+}; -+ -+&codec_analog { -+ cpvdd-supply = <®_eldo1>; -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <®_dcdc2>; -+}; -+ -+&cpu1 { -+ cpu-supply = <®_dcdc2>; -+}; -+ -+&cpu2 { -+ cpu-supply = <®_dcdc2>; -+}; -+ -+&cpu3 { -+ cpu-supply = <®_dcdc2>; -+}; -+ -+&dai { -+ status = "okay"; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ /* Magnetometer */ -+ lis3mdl@1e { -+ compatible = "st,lis3mdl-magn"; -+ reg = <0x1e>; -+ vdd-supply = <®_dldo1>; -+ vddio-supply = <®_dldo1>; -+ }; -+ -+ /* Accelerometer/gyroscope */ -+ mpu6050@68 { -+ compatible = "invensense,mpu6050"; -+ reg = <0x68>; -+ interrupt-parent = <&pio>; -+ interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */ -+ vdd-supply = <®_dldo1>; -+ vddio-supply = <®_dldo1>; -+ }; -+}; -+ -+/* Connected to pogo pins (external spring based pinheader for user addons) */ -+&i2c2 { -+ status = "okay"; -+}; -+ -+&lradc { -+ vref-supply = <®_aldo3>; -+ status = "okay"; -+ -+ button-200 { -+ label = "Volume Up"; -+ linux,code = ; -+ channel = <0>; -+ voltage = <200000>; -+ }; -+ -+ button-400 { -+ label = "Volume Down"; -+ linux,code = ; -+ channel = <0>; -+ voltage = <400000>; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins>; -+ vmmc-supply = <®_dcdc1>; -+ vqmmc-supply = <®_dcdc1>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -+ disable-wp; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&mmc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc2_pins>; -+ vmmc-supply = <®_dcdc1>; -+ vqmmc-supply = <®_dcdc1>; -+ bus-width = <8>; -+ non-removable; -+ cap-mmc-hw-reset; -+ status = "okay"; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&pio { -+ vcc-pb-supply = <®_dcdc1>; -+ vcc-pc-supply = <®_dcdc1>; -+ vcc-pd-supply = <®_dcdc1>; -+ vcc-pe-supply = <®_aldo1>; -+ vcc-pf-supply = <®_dcdc1>; -+ vcc-pg-supply = <®_dldo4>; -+ vcc-ph-supply = <®_dcdc1>; -+}; -+ -+&r_pio { -+ /* -+ * FIXME: We can't add that supply for now since it would -+ * create a circular dependency between pinctrl, the regulator -+ * and the RSB Bus. -+ * -+ * vcc-pl-supply = <®_aldo2>; -+ */ -+}; -+ -+&r_rsb { -+ status = "okay"; -+ -+ axp803: pmic@3a3 { -+ compatible = "x-powers,axp803"; -+ reg = <0x3a3>; -+ interrupt-parent = <&r_intc>; -+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ }; -+}; -+ -+#include "axp803.dtsi" -+ -+&ac_power_supply { -+ status = "okay"; -+}; -+ -+&battery_power_supply { -+ status = "okay"; -+}; -+ -+®_aldo1 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "dovdd-csi"; -+}; -+ -+®_aldo2 { -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc-pl"; -+}; -+ -+®_aldo3 { -+ regulator-always-on; -+ regulator-min-microvolt = <2700000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-pll-avcc"; -+}; -+ -+®_dcdc1 { -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-3v3"; -+}; -+ -+®_dcdc2 { -+ regulator-always-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-name = "vdd-cpux"; -+}; -+ -+/* DCDC3 is polyphased with DCDC2 */ -+ -+®_dcdc5 { -+ regulator-always-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "vcc-dram"; -+}; -+ -+®_dcdc6 { -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-name = "vdd-sys"; -+}; -+ -+®_dldo1 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-dsi-sensor"; -+}; -+ -+®_dldo2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc-mipi-io"; -+}; -+ -+®_dldo3 { -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ regulator-name = "avdd-csi"; -+}; -+ -+®_dldo4 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-wifi-io"; -+}; -+ -+®_eldo1 { -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc-lpddr"; -+}; -+ -+®_eldo3 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "dvdd-1v8-csi"; -+}; -+ -+®_fldo1 { -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "vcc-1v2-hsic"; -+}; -+ -+®_fldo2 { -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-name = "vdd-cpus"; -+}; -+ -+®_ldo_io0 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-lcd-ctp-stk"; -+ status = "okay"; -+}; -+ -+®_ldo_io1 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc-1v8-typec"; -+ status = "okay"; -+}; -+ -+®_rtc_ldo { -+ regulator-name = "vcc-rtc"; -+}; -+ -+&sound { -+ status = "okay"; -+ simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; -+ simple-audio-card,widgets = "Microphone", "Headset Microphone", -+ "Microphone", "Internal Microphone", -+ "Headphone", "Headphone Jack", -+ "Speaker", "Internal Earpiece", -+ "Speaker", "Internal Speaker"; -+ simple-audio-card,routing = -+ "Headphone Jack", "HP", -+ "Internal Earpiece", "EARPIECE", -+ "Internal Speaker", "Speaker Amp OUTL", -+ "Internal Speaker", "Speaker Amp OUTR", -+ "Speaker Amp INL", "LINEOUT", -+ "Speaker Amp INR", "LINEOUT", -+ "Left DAC", "AIF1 Slot 0 Left", -+ "Right DAC", "AIF1 Slot 0 Right", -+ "AIF1 Slot 0 Left ADC", "Left ADC", -+ "AIF1 Slot 0 Right ADC", "Right ADC", -+ "Internal Microphone", "MBIAS", -+ "MIC1", "Internal Microphone", -+ "Headset Microphone", "HBIAS", -+ "MIC2", "Headset Microphone"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pb_pins>; -+ status = "okay"; -+}; -+ -+/* Connected to the modem (hardware flow control can't be used) */ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins>; -+ status = "okay"; -+}; -+ -+&usb_otg { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usb_power_supply { -+ status = "okay"; -+}; -+ -+&usbphy { -+ status = "okay"; -+}; --- -2.26.0 - -From e8fd62cbf02828da817628d15111e6e974144473 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 10 Mar 2020 15:46:43 +0000 -Subject: [PATCH 5/9] sync sun50i-a64 clocks with linux 5.6 - -Signed-off-by: Peter Robinson ---- - include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h -index d66432c6e6..e512a1c9b0 100644 ---- a/include/dt-bindings/clock/sun50i-a64-ccu.h -+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h -@@ -43,8 +43,10 @@ - #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ - #define _DT_BINDINGS_CLK_SUN50I_A64_H_ - -+#define CLK_PLL_VIDEO0 7 - #define CLK_PLL_PERIPH0 11 - -+#define CLK_CPUX 21 - #define CLK_BUS_MIPI_DSI 28 - #define CLK_BUS_CE 29 - #define CLK_BUS_DMA 30 --- -2.26.0 - -From a07a9d6cb77ea0bc21cd64922bb428faf5b7e121 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 10 Mar 2020 15:49:11 +0000 -Subject: [PATCH 6/9] add upstream sun50i-a64-cpu-opp.dtsi added in 5.6 - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 75 ++++++++++++++++++++++++++++ - 1 file changed, 75 insertions(+) - create mode 100644 arch/arm/dts/sun50i-a64-cpu-opp.dtsi - -diff --git a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi -new file mode 100644 -index 0000000000..578c37490d ---- /dev/null -+++ b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi -@@ -0,0 +1,75 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2020 Vasily khoruzhick -+ */ -+ -+/ { -+ cpu0_opp_table: opp_table0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-648000000 { -+ opp-hz = /bits/ 64 <648000000>; -+ opp-microvolt = <1040000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-816000000 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-912000000 { -+ opp-hz = /bits/ 64 <912000000>; -+ opp-microvolt = <1120000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-960000000 { -+ opp-hz = /bits/ 64 <960000000>; -+ opp-microvolt = <1160000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-1008000000 { -+ opp-hz = /bits/ 64 <1008000000>; -+ opp-microvolt = <1200000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-1056000000 { -+ opp-hz = /bits/ 64 <1056000000>; -+ opp-microvolt = <1240000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-1104000000 { -+ opp-hz = /bits/ 64 <1104000000>; -+ opp-microvolt = <1260000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ -+ opp-1152000000 { -+ opp-hz = /bits/ 64 <1152000000>; -+ opp-microvolt = <1300000>; -+ clock-latency-ns = <244144>; /* 8 32k periods */ -+ }; -+ }; -+}; -+ -+&cpu0 { -+ operating-points-v2 = <&cpu0_opp_table>; -+}; -+ -+&cpu1 { -+ operating-points-v2 = <&cpu0_opp_table>; -+}; -+ -+&cpu2 { -+ operating-points-v2 = <&cpu0_opp_table>; -+}; -+ -+&cpu3 { -+ operating-points-v2 = <&cpu0_opp_table>; -+}; --- -2.26.0 - -From 493869ec73e6ba999b6f7c49369e966ebfb8ef0b Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 14 Apr 2020 09:50:11 +0100 -Subject: [PATCH 7/9] Initial Pinephone support - -Signed-off-by: Peter Robinson ---- - configs/pinephone_defconfig | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - create mode 100644 configs/pinephone_defconfig - -diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig -new file mode 100644 -index 0000000000..a7d1e610d4 ---- /dev/null -+++ b/configs/pinephone_defconfig -@@ -0,0 +1,26 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_SPL=y -+CONFIG_MACH_SUN50I=y -+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y -+CONFIG_DRAM_CLK=552 -+CONFIG_DRAM_ZQ=3881949 -+CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -+CONFIG_R_I2C_ENABLE=y -+CONFIG_SPL_SPI_SUNXI=y -+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_USE_PREBOOT=y -+# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_SPL_EFI_PARTITION is not set -+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.1" -+CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.0" -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_SUNXI=y -+CONFIG_LED=y -+CONFIG_LED_GPIO=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y --- -2.26.0 - -From 163b30d9cd1c0cf77107e0330567bbda063410da Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 14 Apr 2020 09:51:44 +0100 -Subject: [PATCH 8/9] Initial PineTab dts from linux 5.7-rc1 - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/sun50i-a64-pinetab.dts | 460 ++++++++++++++++++++++++++++ - 2 files changed, 461 insertions(+) - create mode 100644 arch/arm/dts/sun50i-a64-pinetab.dts - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index fb7516ee83..50c1d48e84 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -575,6 +575,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \ - sun50i-a64-pinebook.dtb \ - sun50i-a64-pinephone-1.0.dtb \ - sun50i-a64-pinephone-1.1.dtb \ -+ sun50i-a64-pinetab.dtb \ - sun50i-a64-sopine-baseboard.dtb \ - sun50i-a64-teres-i.dtb - dtb-$(CONFIG_MACH_SUN9I) += \ -diff --git a/arch/arm/dts/sun50i-a64-pinetab.dts b/arch/arm/dts/sun50i-a64-pinetab.dts -new file mode 100644 -index 0000000000..316e8a4439 ---- /dev/null -+++ b/arch/arm/dts/sun50i-a64-pinetab.dts -@@ -0,0 +1,460 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (C) 2019 Icenowy Zheng -+ * -+ */ -+ -+/dts-v1/; -+ -+#include "sun50i-a64.dtsi" -+#include "sun50i-a64-cpu-opp.dtsi" -+ -+#include -+#include -+#include -+ -+/ { -+ model = "PineTab"; -+ compatible = "pine64,pinetab", "allwinner,sun50i-a64"; -+ -+ aliases { -+ serial0 = &uart0; -+ ethernet0 = &rtl8723cs; -+ }; -+ -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; -+ brightness-levels = <0 16 18 20 22 24 26 29 32 35 38 42 46 51 56 62 68 75 83 91 100>; -+ default-brightness-level = <15>; -+ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ -+ power-supply = <&vdd_bl>; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ i2c-csi { -+ compatible = "i2c-gpio"; -+ sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */ -+ scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */ -+ i2c-gpio,delay-us = <5>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* Rear camera */ -+ ov5640: camera@3c { -+ compatible = "ovti,ov5640"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&csi_mclk_pin>; -+ clocks = <&ccu CLK_CSI_MCLK>; -+ clock-names = "xclk"; -+ -+ AVDD-supply = <®_dldo3>; -+ DOVDD-supply = <®_aldo1>; -+ DVDD-supply = <®_eldo3>; -+ reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */ -+ powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ -+ -+ port { -+ ov5640_ep: endpoint { -+ remote-endpoint = <&csi_ep>; -+ bus-width = <8>; -+ hsync-active = <1>; /* Active high */ -+ vsync-active = <0>; /* Active low */ -+ data-active = <1>; /* Active high */ -+ pclk-sample = <1>; /* Rising */ -+ }; -+ }; -+ }; -+ }; -+ -+ speaker_amp: audio-amplifier { -+ compatible = "simple-audio-amplifier"; -+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ -+ sound-name-prefix = "Speaker Amp"; -+ }; -+ -+ vdd_bl: regulator@0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "bl-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ -+ enable-active-high; -+ }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ -+ post-power-on-delay-ms = <200>; -+ }; -+}; -+ -+&codec { -+ status = "okay"; -+}; -+ -+&codec_analog { -+ hpvcc-supply = <®_eldo1>; -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <®_dcdc2>; -+}; -+ -+&cpu1 { -+ cpu-supply = <®_dcdc2>; -+}; -+ -+&cpu2 { -+ cpu-supply = <®_dcdc2>; -+}; -+ -+&cpu3 { -+ cpu-supply = <®_dcdc2>; -+}; -+ -+&csi { -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ csi_ep: endpoint { -+ remote-endpoint = <&ov5640_ep>; -+ bus-width = <8>; -+ hsync-active = <1>; /* Active high */ -+ vsync-active = <0>; /* Active low */ -+ data-active = <1>; /* Active high */ -+ pclk-sample = <1>; /* Rising */ -+ }; -+ }; -+}; -+ -+&dai { -+ status = "okay"; -+}; -+ -+&de { -+ status = "okay"; -+}; -+ -+&dphy { -+ status = "okay"; -+}; -+ -+&dsi { -+ vcc-dsi-supply = <®_dldo1>; -+ status = "okay"; -+ -+ panel@0 { -+ compatible = "feixin,k101-im2ba02"; -+ reg = <0>; -+ avdd-supply = <®_dc1sw>; -+ dvdd-supply = <®_dc1sw>; -+ cvdd-supply = <®_ldo_io1>; -+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ -+ backlight = <&backlight>; -+ }; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ touchscreen@5d { -+ compatible = "goodix,gt9271"; -+ reg = <0x5d>; -+ interrupt-parent = <&pio>; -+ interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */ -+ irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ -+ reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ -+ AVDD28-supply = <®_ldo_io1>; -+ }; -+}; -+ -+&i2c0_pins { -+ bias-pull-up; -+}; -+ -+&i2c1 { -+ status = "okay"; -+ -+ /* TODO: add Bochs BMA223 accelerometer here */ -+}; -+ -+&lradc { -+ vref-supply = <®_aldo3>; -+ status = "okay"; -+ -+ button-200 { -+ label = "Volume Up"; -+ linux,code = ; -+ channel = <0>; -+ voltage = <200000>; -+ }; -+ -+ button-400 { -+ label = "Volume Down"; -+ linux,code = ; -+ channel = <0>; -+ voltage = <400000>; -+ }; -+}; -+ -+&mixer1 { -+ status = "okay"; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc0_pins>; -+ vmmc-supply = <®_dcdc1>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ vmmc-supply = <®_dldo4>; -+ vqmmc-supply = <®_eldo1>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8723cs: wifi@1 { -+ reg = <1>; -+ }; -+}; -+ -+&mmc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc2_pins>; -+ vmmc-supply = <®_dcdc1>; -+ vqmmc-supply = <®_dcdc1>; -+ bus-width = <8>; -+ non-removable; -+ cap-mmc-hw-reset; -+ status = "okay"; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&pwm { -+ status = "okay"; -+}; -+ -+&r_rsb { -+ status = "okay"; -+ -+ axp803: pmic@3a3 { -+ compatible = "x-powers,axp803"; -+ reg = <0x3a3>; -+ interrupt-parent = <&r_intc>; -+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; -+ x-powers,drive-vbus-en; -+ }; -+}; -+ -+#include "axp803.dtsi" -+ -+&ac_power_supply { -+ status = "okay"; -+}; -+ -+&battery_power_supply { -+ status = "okay"; -+}; -+ -+®_aldo1 { -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ regulator-name = "dovdd-csi"; -+}; -+ -+®_aldo2 { -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-pl"; -+}; -+ -+®_aldo3 { -+ regulator-always-on; -+ regulator-min-microvolt = <2700000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-pll-avcc"; -+}; -+ -+®_dc1sw { -+ regulator-name = "vcc-lcd"; -+}; -+ -+®_dcdc1 { -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-3v3"; -+}; -+ -+®_dcdc2 { -+ regulator-always-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-name = "vdd-cpux"; -+}; -+ -+/* DCDC3 is polyphased with DCDC2 */ -+ -+®_dcdc5 { -+ regulator-always-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "vcc-dram"; -+}; -+ -+®_dcdc6 { -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-name = "vdd-sys"; -+}; -+ -+®_dldo1 { -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-hdmi-dsi-sensor"; -+}; -+ -+®_dldo3 { -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ regulator-name = "avdd-csi"; -+}; -+ -+®_dldo4 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-wifi"; -+}; -+ -+®_drivevbus { -+ regulator-name = "usb0-vbus"; -+ status = "okay"; -+}; -+ -+®_eldo1 { -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "cpvdd"; -+}; -+ -+®_eldo2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca-1v8"; -+}; -+ -+®_eldo3 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "dvdd-1v8-csi"; -+}; -+ -+®_fldo1 { -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "vcc-1v2-hsic"; -+}; -+ -+®_fldo2 { -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-name = "vdd-cpus"; -+}; -+ -+®_ldo_io0 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc-usb"; -+ status = "okay"; -+}; -+ -+®_ldo_io1 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-enable-ramp-delay = <3500000>; -+ regulator-name = "vcc-touchscreen"; -+ status = "okay"; -+}; -+ -+®_rtc_ldo { -+ regulator-name = "vcc-rtc"; -+}; -+ -+&sound { -+ status = "okay"; -+ simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; -+ simple-audio-card,widgets = "Microphone", "Internal Microphone Left", -+ "Microphone", "Internal Microphone Right", -+ "Headphone", "Headphone Jack", -+ "Speaker", "Internal Speaker"; -+ simple-audio-card,routing = -+ "Left DAC", "AIF1 Slot 0 Left", -+ "Right DAC", "AIF1 Slot 0 Right", -+ "Speaker Amp INL", "LINEOUT", -+ "Speaker Amp INR", "LINEOUT", -+ "Internal Speaker", "Speaker Amp OUTL", -+ "Internal Speaker", "Speaker Amp OUTR", -+ "Headphone Jack", "HP", -+ "AIF1 Slot 0 Left ADC", "Left ADC", -+ "AIF1 Slot 0 Right ADC", "Right ADC", -+ "Internal Microphone Left", "MBIAS", -+ "MIC1", "Internal Microphone Left", -+ "Internal Microphone Right", "HBIAS", -+ "MIC2", "Internal Microphone Right"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pb_pins>; -+ status = "okay"; -+}; -+ -+&usb_otg { -+ dr_mode = "otg"; -+ status = "okay"; -+}; -+ -+&usb_power_supply { -+ status = "okay"; -+}; -+ -+&usbphy { -+ usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ -+ usb0_vbus_power-supply = <&usb_power_supply>; -+ usb0_vbus-supply = <®_drivevbus>; -+ usb1_vbus-supply = <®_ldo_io0>; -+ status = "okay"; -+}; --- -2.26.0 - -From 6bf15552c2b6becb48ce7732120e0ddb2078cb1a Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 14 Apr 2020 09:53:07 +0100 -Subject: [PATCH 9/9] initial pinetab support - -Signed-off-by: Peter Robinson ---- - configs/pinetab_defconfig | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - create mode 100644 configs/pinetab_defconfig - -diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig -new file mode 100644 -index 0000000000..5b9620f3e5 ---- /dev/null -+++ b/configs/pinetab_defconfig -@@ -0,0 +1,26 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_SUNXI=y -+CONFIG_SPL=y -+CONFIG_MACH_SUN50I=y -+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y -+CONFIG_DRAM_CLK=552 -+CONFIG_DRAM_ZQ=3881949 -+CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -+CONFIG_R_I2C_ENABLE=y -+CONFIG_SPL_SPI_SUNXI=y -+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_USE_PREBOOT=y -+# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_SPL_EFI_PARTITION is not set -+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinetab" -+CONFIG_OF_LIST="sun50i-a64-pinetab" -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_PWM=y -+CONFIG_PWM_SUNXI=y -+CONFIG_LED=y -+CONFIG_LED_GPIO=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y --- -2.26.0 diff --git a/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch b/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch deleted file mode 100644 index 720b1bacbba27502772b2bf0180ae02a72db3ac6..0000000000000000000000000000000000000000 --- a/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch +++ /dev/null @@ -1,993 +0,0 @@ -From 47d0df70fbe5997770090aca05b07d774a19a722 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Wed, 10 Jun 2020 13:15:45 +0100 -Subject: [PATCH] USB host support for Raspberry Pi 4 board (64-bit) - -Signed-off-by: Peter Robinson ---- - arch/arm/mach-bcm283x/init.c | 20 +- - configs/rpi_4_defconfig | 9 + - configs/rpi_arm64_defconfig | 8 +- - drivers/pci/Kconfig | 9 + - drivers/pci/Makefile | 1 + - drivers/pci/pci-rcar-gen3.c | 8 - - drivers/pci/pcie_brcmstb.c | 623 ++++++++++++++++++++++++++++++++++ - drivers/pci/pcie_intel_fpga.c | 3 - - drivers/usb/host/xhci-mem.c | 3 + - include/linux/bitfield.h | 52 +++ - include/pci.h | 22 +- - include/usb/xhci.h | 8 - - 12 files changed, 740 insertions(+), 26 deletions(-) - create mode 100644 drivers/pci/pcie_brcmstb.c - -diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index f4d00d892d..cf4c5b245d 100644 ---- a/arch/arm/mach-bcm283x/init.c -+++ b/arch/arm/mach-bcm283x/init.c -@@ -12,10 +12,15 @@ - #include - #include - -+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL -+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL -+ - #ifdef CONFIG_ARM64 - #include - --static struct mm_region bcm283x_mem_map[] = { -+#define MEM_MAP_MAX_ENTRIES (4) -+ -+static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -@@ -35,11 +40,11 @@ static struct mm_region bcm283x_mem_map[] = { - } - }; - --static struct mm_region bcm2711_mem_map[] = { -+static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -- .size = 0xfe000000UL, -+ .size = 0xfc000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { -@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = { - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN -+ }, { -+ .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, -+ .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, -+ .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | -+ PTE_BLOCK_NON_SHARE | -+ PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, -@@ -72,7 +84,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) - { - int i; - -- for (i = 0; i < 2; i++) { -+ for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) { - mem_map[i].virt = pd[i].virt; - mem_map[i].phys = pd[i].phys; - mem_map[i].size = pd[i].size; -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index f0301dc8bc..b42efe6072 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 - CONFIG_ENV_SIZE=0x4000 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -@@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_DFU=y - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y - CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -@@ -26,12 +30,17 @@ CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y - CONFIG_DM_USB_GADGET=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_USB_GADGET=y - CONFIG_USB_GADGET_MANUFACTURER="FSL" - CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index d16c2388af..0feea7f0be 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -7,13 +7,14 @@ CONFIG_ENV_SIZE=0x4000 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_USE_PREBOOT=y --CONFIG_PREBOOT="usb start" -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y - CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y -@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_USB_DWC2=y - CONFIG_USB_KEYBOARD=y - CONFIG_USB_HOST_ETHER=y -diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig -index 6d8c22aacf..7e1e51d9ea 100644 ---- a/drivers/pci/Kconfig -+++ b/drivers/pci/Kconfig -@@ -205,4 +205,13 @@ config PCIE_ROCKCHIP - Say Y here if you want to enable PCIe controller support on - Rockchip SoCs. - -+config PCI_BRCMSTB -+ bool "Broadcom STB PCIe controller" -+ depends on DM_PCI -+ depends on ARCH_BCM283X -+ help -+ Say Y here if you want to enable support for PCIe controller -+ on Broadcom set-top-box (STB) SoCs. -+ This driver currently supports only BCM2711 SoC and RC mode -+ of the controller. - endif -diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile -index 955351c5c2..3e1ff417d7 100644 ---- a/drivers/pci/Makefile -+++ b/drivers/pci/Makefile -@@ -43,4 +43,5 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o - obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o - obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o - obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o -+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o - obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o -diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c -index df7b37a592..1f51854ccc 100644 ---- a/drivers/pci/pci-rcar-gen3.c -+++ b/drivers/pci/pci-rcar-gen3.c -@@ -118,14 +118,6 @@ - #define RCAR_PCI_MAX_RESOURCES 4 - #define MAX_NR_INBOUND_MAPS 6 - --#define PCI_EXP_FLAGS 2 /* Capabilities register */ --#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ --#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ --#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ --#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ --#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ --#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -- - enum { - RCAR_PCI_ACCESS_READ, - RCAR_PCI_ACCESS_WRITE, -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -new file mode 100644 -index 0000000000..dade79e9c8 ---- /dev/null -+++ b/drivers/pci/pcie_brcmstb.c -@@ -0,0 +1,623 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Broadcom STB PCIe controller driver -+ * -+ * Copyright (C) 2020 Samsung Electronics Co., Ltd. -+ * -+ * Based on upstream Linux kernel driver: -+ * drivers/pci/controller/pcie-brcmstb.c -+ * Copyright (C) 2009 - 2017 Broadcom -+ * -+ * Based driver by Nicolas Saenz Julienne -+ * Copyright (C) 2020 Nicolas Saenz Julienne -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Offset of the mandatory PCIe capability config registers */ -+#define BRCM_PCIE_CAP_REGS 0x00ac -+ -+/* The PCIe controller register offsets */ -+#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188 -+#define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc -+#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0 -+ -+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c -+#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff -+ -+#define PCIE_RC_DL_MDIO_ADDR 0x1100 -+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104 -+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108 -+ -+#define PCIE_MISC_MISC_CTRL 0x4008 -+#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 -+#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 -+#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 -+#define MISC_CTRL_MAX_BURST_SIZE_128 0x0 -+#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c -+#define PCIE_MEM_WIN0_LO(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 -+#define PCIE_MEM_WIN0_HI(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) -+ -+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c -+#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f -+ -+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 -+#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f -+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 -+ -+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c -+#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f -+ -+#define PCIE_MISC_PCIE_STATUS 0x4068 -+#define STATUS_PCIE_PORT_MASK 0x80 -+#define STATUS_PCIE_PORT_SHIFT 7 -+#define STATUS_PCIE_DL_ACTIVE_MASK 0x20 -+#define STATUS_PCIE_DL_ACTIVE_SHIFT 5 -+#define STATUS_PCIE_PHYLINKUP_MASK 0x10 -+#define STATUS_PCIE_PHYLINKUP_SHIFT 4 -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 -+#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 -+#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 -+#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12 -+#define PCIE_MEM_WIN0_BASE_LIMIT(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 -+#define MEM_WIN0_BASE_HI_BASE_MASK 0xff -+#define PCIE_MEM_WIN0_BASE_HI(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 -+#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff -+#define PCIE_MEM_WIN0_LIMIT_HI(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) -+ -+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 -+#define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 -+#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 -+ -+#define PCIE_MSI_INTR2_CLR 0x4508 -+#define PCIE_MSI_INTR2_MASK_SET 0x4510 -+ -+#define PCIE_EXT_CFG_DATA 0x8000 -+ -+#define PCIE_EXT_CFG_INDEX 0x9000 -+#define PCIE_EXT_BUSNUM_SHIFT 20 -+#define PCIE_EXT_SLOT_SHIFT 15 -+#define PCIE_EXT_FUNC_SHIFT 12 -+ -+#define PCIE_RGR1_SW_INIT_1 0x9210 -+#define RGR1_SW_INIT_1_PERST_MASK 0x1 -+#define RGR1_SW_INIT_1_INIT_MASK 0x2 -+ -+/* PCIe parameters */ -+#define BRCM_NUM_PCIE_OUT_WINS 4 -+ -+/* MDIO registers */ -+#define MDIO_PORT0 0x0 -+#define MDIO_DATA_MASK 0x7fffffff -+#define MDIO_DATA_SHIFT 0 -+#define MDIO_PORT_MASK 0xf0000 -+#define MDIO_PORT_SHIFT 16 -+#define MDIO_REGAD_MASK 0xffff -+#define MDIO_REGAD_SHIFT 0 -+#define MDIO_CMD_MASK 0xfff00000 -+#define MDIO_CMD_SHIFT 20 -+#define MDIO_CMD_READ 0x1 -+#define MDIO_CMD_WRITE 0x0 -+#define MDIO_DATA_DONE_MASK 0x80000000 -+#define SSC_REGS_ADDR 0x1100 -+#define SET_ADDR_OFFSET 0x1f -+#define SSC_CNTL_OFFSET 0x2 -+#define SSC_CNTL_OVRD_EN_MASK 0x8000 -+#define SSC_CNTL_OVRD_VAL_MASK 0x4000 -+#define SSC_STATUS_OFFSET 0x1 -+#define SSC_STATUS_SSC_MASK 0x400 -+#define SSC_STATUS_SSC_SHIFT 10 -+#define SSC_STATUS_PLL_LOCK_MASK 0x800 -+#define SSC_STATUS_PLL_LOCK_SHIFT 11 -+ -+/** -+ * struct brcm_pcie - the PCIe controller state -+ * @base: Base address of memory mapped IO registers of the controller -+ * @gen: Non-zero value indicates limitation of the PCIe controller operation -+ * to a specific generation (1, 2 or 3) -+ * @ssc: true indicates active Spread Spectrum Clocking operation -+ */ -+struct brcm_pcie { -+ void __iomem *base; -+ -+ int gen; -+ bool ssc; -+}; -+ -+/** -+ * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size -+ * @size: The inbound region size -+ * -+ * This function converts size of the inbound "BAR" region to the non-linear -+ * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field. -+ * -+ * Return: The encoded inbound region size -+ */ -+static int brcm_pcie_encode_ibar_size(u64 size) -+{ -+ int log2_in = ilog2(size); -+ -+ if (log2_in >= 12 && log2_in <= 15) -+ /* Covers 4KB to 32KB (inclusive) */ -+ return (log2_in - 12) + 0x1c; -+ else if (log2_in >= 16 && log2_in <= 37) -+ /* Covers 64KB to 32GB, (inclusive) */ -+ return log2_in - 15; -+ -+ /* Something is awry so disable */ -+ return 0; -+} -+ -+/** -+ * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode -+ * @pcie: Pointer to the PCIe controller state -+ * -+ * The controller is capable of serving in both RC and EP roles. -+ * -+ * Return: true for RC mode, false for EP mode. -+ */ -+static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) -+{ -+ u32 val; -+ -+ val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); -+ -+ return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT; -+} -+ -+/** -+ * brcm_pcie_link_up() - Check whether the PCIe link is up -+ * @pcie: Pointer to the PCIe controller state -+ * -+ * Return: true if the link is up, false otherwise. -+ */ -+static bool brcm_pcie_link_up(struct brcm_pcie *pcie) -+{ -+ u32 val, dla, plu; -+ -+ val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); -+ dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT; -+ plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT; -+ -+ return dla && plu; -+} -+ -+static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, -+ uint offset, void **paddress) -+{ -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ unsigned int pci_bus = PCI_BUS(bdf); -+ unsigned int pci_dev = PCI_DEV(bdf); -+ unsigned int pci_func = PCI_FUNC(bdf); -+ int idx; -+ -+ /* -+ * Busses 0 (host PCIe bridge) and 1 (its immediate child) -+ * are limited to a single device each -+ */ -+ if (pci_bus < 2 && pci_dev > 0) -+ return -EINVAL; -+ -+ /* Accesses to the RC go right to the RC registers */ -+ if (pci_bus == 0) { -+ *paddress = pcie->base + offset; -+ return 0; -+ } -+ -+ /* For devices, write to the config space index register */ -+ idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT) -+ | (pci_dev << PCIE_EXT_SLOT_SHIFT) -+ | (pci_func << PCIE_EXT_FUNC_SHIFT); -+ -+ writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); -+ *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; -+ -+ return 0; -+} -+ -+static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, -+ uint offset, ulong *valuep, -+ enum pci_size_t size) -+{ -+ return pci_generic_mmap_read_config(bus, brcm_pcie_config_address, -+ bdf, offset, valuep, size); -+} -+ -+static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf, -+ uint offset, ulong value, -+ enum pci_size_t size) -+{ -+ return pci_generic_mmap_write_config(bus, brcm_pcie_config_address, -+ bdf, offset, value, size); -+} -+ -+static const char *link_speed_to_str(unsigned int cls) -+{ -+ switch (cls) { -+ case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5"; -+ case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0"; -+ case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0"; -+ default: -+ break; -+ } -+ -+ return "??"; -+} -+ -+static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad, -+ unsigned int cmd) -+{ -+ u32 pkt; -+ -+ pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK; -+ pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK; -+ pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK; -+ -+ return pkt; -+} -+ -+/** -+ * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus -+ * @base: Pointer to the PCIe controller IO registers -+ * @port: The MDIO port number -+ * @regad: The register address -+ * @val: A pointer at which to store the read value -+ * -+ * Return: 0 on success and register value in @val, negative error value -+ * on failure. -+ */ -+static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port, -+ unsigned int regad, u32 *val) -+{ -+ u32 data, addr; -+ int ret; -+ -+ addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ); -+ writel(addr, base + PCIE_RC_DL_MDIO_ADDR); -+ readl(base + PCIE_RC_DL_MDIO_ADDR); -+ -+ ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data, -+ (data & MDIO_DATA_DONE_MASK), 100); -+ -+ *val = data & MDIO_DATA_MASK; -+ -+ return ret; -+} -+ -+/** -+ * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus -+ * @base: Pointer to the PCIe controller IO registers -+ * @port: The MDIO port number -+ * @regad: Address of the register -+ * @wrdata: The value to write -+ * -+ * Return: 0 on success, negative error value on failure. -+ */ -+static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port, -+ unsigned int regad, u16 wrdata) -+{ -+ u32 data, addr; -+ -+ addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE); -+ writel(addr, base + PCIE_RC_DL_MDIO_ADDR); -+ readl(base + PCIE_RC_DL_MDIO_ADDR); -+ writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); -+ -+ return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data, -+ !(data & MDIO_DATA_DONE_MASK), 100); -+} -+ -+/** -+ * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking -+ * @base: pointer to the PCIe controller IO registers -+ * -+ * Return: 0 on success, negative error value on failure. -+ */ -+static int brcm_pcie_set_ssc(void __iomem *base) -+{ -+ int pll, ssc; -+ int ret; -+ u32 tmp; -+ -+ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, -+ SSC_REGS_ADDR); -+ if (ret < 0) -+ return ret; -+ -+ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); -+ if (ret < 0) -+ return ret; -+ -+ tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK); -+ -+ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); -+ if (ret < 0) -+ return ret; -+ -+ udelay(1000); -+ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); -+ if (ret < 0) -+ return ret; -+ -+ ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT; -+ pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT; -+ -+ return ssc && pll ? 0 : -EIO; -+} -+ -+/** -+ * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3) -+ * @pcie: pointer to the PCIe controller state -+ * @gen: PCIe generation to limit the controller's operation to -+ */ -+static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen) -+{ -+ void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS; -+ -+ u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2); -+ u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP); -+ -+ lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; -+ writel(lnkcap, cap_base + PCI_EXP_LNKCAP); -+ -+ lnkctl2 = (lnkctl2 & ~0xf) | gen; -+ writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2); -+} -+ -+static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, -+ unsigned int win, u64 phys_addr, -+ u64 pcie_addr, u64 size) -+{ -+ void __iomem *base = pcie->base; -+ u32 phys_addr_mb_high, limit_addr_mb_high; -+ phys_addr_t phys_addr_mb, limit_addr_mb; -+ int high_addr_shift; -+ u32 tmp; -+ -+ /* Set the base of the pcie_addr window */ -+ writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win)); -+ writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win)); -+ -+ /* Write the addr base & limit lower bits (in MBs) */ -+ phys_addr_mb = phys_addr / SZ_1M; -+ limit_addr_mb = (phys_addr + size - 1) / SZ_1M; -+ -+ tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win)); -+ u32p_replace_bits(&tmp, phys_addr_mb, -+ MEM_WIN0_BASE_LIMIT_BASE_MASK); -+ u32p_replace_bits(&tmp, limit_addr_mb, -+ MEM_WIN0_BASE_LIMIT_LIMIT_MASK); -+ writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win)); -+ -+ /* Write the cpu & limit addr upper bits */ -+ high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT; -+ phys_addr_mb_high = phys_addr_mb >> high_addr_shift; -+ tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win)); -+ u32p_replace_bits(&tmp, phys_addr_mb_high, -+ MEM_WIN0_BASE_HI_BASE_MASK); -+ writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win)); -+ -+ limit_addr_mb_high = limit_addr_mb >> high_addr_shift; -+ tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win)); -+ u32p_replace_bits(&tmp, limit_addr_mb_high, -+ PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); -+ writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); -+} -+ -+static int brcm_pcie_probe(struct udevice *dev) -+{ -+ struct udevice *ctlr = pci_get_controller(dev); -+ struct pci_controller *hose = dev_get_uclass_priv(ctlr); -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ void __iomem *base = pcie->base; -+ bool ssc_good = false; -+ int num_out_wins = 0; -+ u64 rc_bar2_offset, rc_bar2_size; -+ unsigned int scb_size_val; -+ int i, ret; -+ u16 nlw, cls, lnksta; -+ u32 tmp; -+ -+ /* -+ * Reset the bridge, assert the fundamental reset. Note for some SoCs, -+ * e.g. BCM7278, the fundamental reset should not be asserted here. -+ * This will need to be changed when support for other SoCs is added. -+ */ -+ setbits_le32(base + PCIE_RGR1_SW_INIT_1, -+ RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK); -+ /* -+ * The delay is a safety precaution to preclude the reset signal -+ * from looking like a glitch. -+ */ -+ udelay(100); -+ -+ /* Take the bridge out of reset */ -+ clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK); -+ -+ clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, -+ PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); -+ -+ /* Wait for SerDes to be stable */ -+ udelay(100); -+ -+ /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ -+ clrsetbits_le32(base + PCIE_MISC_MISC_CTRL, -+ MISC_CTRL_MAX_BURST_SIZE_MASK, -+ MISC_CTRL_SCB_ACCESS_EN_MASK | -+ MISC_CTRL_CFG_READ_UR_MODE_MASK | -+ MISC_CTRL_MAX_BURST_SIZE_128); -+ /* -+ * TODO: When support for other SoCs than BCM2711 is added we may -+ * need to use the base address and size(s) provided in the dma-ranges -+ * property. -+ */ -+ rc_bar2_offset = 0; -+ rc_bar2_size = 0xc0000000; -+ -+ tmp = lower_32_bits(rc_bar2_offset); -+ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), -+ RC_BAR2_CONFIG_LO_SIZE_MASK); -+ writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); -+ writel(upper_32_bits(rc_bar2_offset), -+ base + PCIE_MISC_RC_BAR2_CONFIG_HI); -+ -+ scb_size_val = rc_bar2_size ? -+ ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ -+ -+ tmp = readl(base + PCIE_MISC_MISC_CTRL); -+ u32p_replace_bits(&tmp, scb_size_val, -+ MISC_CTRL_SCB0_SIZE_MASK); -+ writel(tmp, base + PCIE_MISC_MISC_CTRL); -+ -+ /* Disable the PCIe->GISB memory window (RC_BAR1) */ -+ clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO, -+ RC_BAR1_CONFIG_LO_SIZE_MASK); -+ -+ /* Disable the PCIe->SCB memory window (RC_BAR3) */ -+ clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO, -+ RC_BAR3_CONFIG_LO_SIZE_MASK); -+ -+ /* Mask all interrupts since we are not handling any yet */ -+ writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET); -+ -+ /* Clear any interrupts we find on boot */ -+ writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); -+ -+ if (pcie->gen) -+ brcm_pcie_set_gen(pcie, pcie->gen); -+ -+ /* Unassert the fundamental reset */ -+ clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, -+ RGR1_SW_INIT_1_PERST_MASK); -+ -+ /* Give the RC/EP time to wake up, before trying to configure RC. -+ * Intermittently check status for link-up, up to a total of 100ms. -+ */ -+ for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) -+ mdelay(5); -+ -+ if (!brcm_pcie_link_up(pcie)) { -+ printf("PCIe BRCM: link down\n"); -+ return -EINVAL; -+ } -+ -+ if (!brcm_pcie_rc_mode(pcie)) { -+ printf("PCIe misconfigured; is in EP mode\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < hose->region_count; i++) { -+ struct pci_region *reg = &hose->regions[i]; -+ -+ if (reg->flags != PCI_REGION_MEM) -+ continue; -+ -+ if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) -+ return -EINVAL; -+ -+ brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start, -+ reg->bus_start, reg->size); -+ -+ num_out_wins++; -+ } -+ -+ /* -+ * For config space accesses on the RC, show the right class for -+ * a PCIe-PCIe bridge (the default setting is to be EP mode). -+ */ -+ clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3, -+ CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400); -+ -+ if (pcie->ssc) { -+ ret = brcm_pcie_set_ssc(pcie->base); -+ if (!ret) -+ ssc_good = true; -+ else -+ printf("PCIe BRCM: failed attempt to enter SSC mode\n"); -+ } -+ -+ lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); -+ cls = lnksta & PCI_EXP_LNKSTA_CLS; -+ nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; -+ -+ printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls), -+ nlw, ssc_good ? "(SSC)" : "(!SSC)"); -+ -+ /* PCIe->SCB endian mode for BAR */ -+ clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1, -+ VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK, -+ VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN); -+ /* -+ * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 -+ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. -+ */ -+ setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, -+ PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK); -+ -+ return 0; -+} -+ -+static int brcm_pcie_ofdata_to_platdata(struct udevice *dev) -+{ -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ ofnode dn = dev_ofnode(dev); -+ u32 max_link_speed; -+ int ret; -+ -+ /* Get the controller base address */ -+ pcie->base = dev_read_addr_ptr(dev); -+ if (!pcie->base) -+ return -EINVAL; -+ -+ pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); -+ -+ ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); -+ if (ret < 0 || max_link_speed > 4) -+ pcie->gen = 0; -+ else -+ pcie->gen = max_link_speed; -+ -+ return 0; -+} -+ -+static const struct dm_pci_ops brcm_pcie_ops = { -+ .read_config = brcm_pcie_read_config, -+ .write_config = brcm_pcie_write_config, -+}; -+ -+static const struct udevice_id brcm_pcie_ids[] = { -+ { .compatible = "brcm,bcm2711-pcie" }, -+ { } -+}; -+ -+U_BOOT_DRIVER(pcie_brcm_base) = { -+ .name = "pcie_brcm", -+ .id = UCLASS_PCI, -+ .ops = &brcm_pcie_ops, -+ .of_match = brcm_pcie_ids, -+ .probe = brcm_pcie_probe, -+ .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata, -+ .priv_auto_alloc_size = sizeof(struct brcm_pcie), -+}; -diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c -index aa1903e547..9f102c64c6 100644 ---- a/drivers/pci/pcie_intel_fpga.c -+++ b/drivers/pci/pcie_intel_fpga.c -@@ -67,9 +67,6 @@ - #define IS_ROOT_PORT(pcie, bdf) \ - ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) - --#define PCI_EXP_LNKSTA 18 /* Link Status */ --#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -- - /** - * struct intel_fpga_pcie - Intel FPGA PCIe controller state - * @bus: Pointer to the PCI bus -diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c -index 2d968aafb0..f446520528 100644 ---- a/drivers/usb/host/xhci-mem.c -+++ b/drivers/usb/host/xhci-mem.c -@@ -395,6 +395,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) - scratchpad->sp_array[i] = cpu_to_le64(ptr); - } - -+ xhci_flush_cache((uintptr_t)scratchpad->sp_array, -+ sizeof(u64) * num_sp); -+ - return 0; - - fail_sp3: -diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h -index 8b9d6fff00..7ad8b088ed 100644 ---- a/include/linux/bitfield.h -+++ b/include/linux/bitfield.h -@@ -103,4 +103,56 @@ - (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ - }) - -+extern void __compiletime_error("value doesn't fit into mask") -+__field_overflow(void); -+extern void __compiletime_error("bad bitfield mask") -+__bad_mask(void); -+ -+static __always_inline u64 field_multiplier(u64 field) -+{ -+ if ((field | (field - 1)) & ((field | (field - 1)) + 1)) -+ __bad_mask(); -+ return field & -field; -+} -+ -+static __always_inline u64 field_mask(u64 field) -+{ -+ return field / field_multiplier(field); -+} -+ -+#define ____MAKE_OP(type, base, to, from) \ -+static __always_inline __##type type##_encode_bits(base v, base field) \ -+{ \ -+ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ -+ __field_overflow(); \ -+ return to((v & field_mask(field)) * field_multiplier(field)); \ -+} \ -+static __always_inline __##type type##_replace_bits(__##type old, \ -+ base val, base field) \ -+{ \ -+ return (old & ~to(field)) | type##_encode_bits(val, field); \ -+} \ -+static __always_inline void type##p_replace_bits(__##type * p, \ -+ base val, base field) \ -+{ \ -+ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ -+} \ -+static __always_inline base type##_get_bits(__##type v, base field) \ -+{ \ -+ return (from(v) & field) / field_multiplier(field); \ -+} -+ -+#define __MAKE_OP(size) \ -+ ____MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \ -+ ____MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \ -+ ____MAKE_OP(u##size, u##size, ,) -+ -+____MAKE_OP(u8, u8, ,) -+__MAKE_OP(16) -+__MAKE_OP(32) -+__MAKE_OP(64) -+ -+#undef __MAKE_OP -+#undef ____MAKE_OP -+ - #endif -diff --git a/include/pci.h b/include/pci.h -index 19c9244b94..281f353916 100644 ---- a/include/pci.h -+++ b/include/pci.h -@@ -471,10 +471,28 @@ - #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ - - /* PCI Express capabilities */ -+#define PCI_EXP_FLAGS 2 /* Capabilities register */ -+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ - #define PCI_EXP_DEVCAP 4 /* Device capabilities */ --#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ -+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ - #define PCI_EXP_DEVCTL 8 /* Device Control */ --#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ -+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ -+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -+#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ -+#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ -+#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -+#define PCI_EXP_LNKSTA 18 /* Link Status */ -+#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ -+#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ -+#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ -+#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ -+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ -+#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ -+#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ - - /* Include the ID list */ - -diff --git a/include/usb/xhci.h b/include/usb/xhci.h -index 20e4a21066..1170c0ac69 100644 ---- a/include/usb/xhci.h -+++ b/include/usb/xhci.h -@@ -1114,28 +1114,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) - */ - static inline u64 xhci_readq(__le64 volatile *regs) - { --#if BITS_PER_LONG == 64 -- return readq(regs); --#else - __u32 *ptr = (__u32 *)regs; - u64 val_lo = readl(ptr); - u64 val_hi = readl(ptr + 1); - return val_lo + (val_hi << 32); --#endif - } - - static inline void xhci_writeq(__le64 volatile *regs, const u64 val) - { --#if BITS_PER_LONG == 64 -- writeq(val, regs); --#else - __u32 *ptr = (__u32 *)regs; - u32 val_lo = lower_32_bits(val); - /* FIXME */ - u32 val_hi = upper_32_bits(val); - writel(val_lo, ptr); - writel(val_hi, ptr + 1); --#endif - } - - int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, --- -2.26.2 - diff --git a/arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch b/arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch deleted file mode 100644 index df63c4ef7f570a75fbb6f103c9282ba2ff9218ac..0000000000000000000000000000000000000000 --- a/arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch +++ /dev/null @@ -1,55 +0,0 @@ -From a63eb1bdcd25246b2c637c7846917dc6dc607725 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Thu, 18 Apr 2019 15:44:59 +0100 -Subject: [PATCH] add BOOTENV_EFI_SET_FDTFILE_FALLBACK for tegra186 because tx2 - variants - -Signed-off-by: Peter Robinson ---- - include/config_distro_bootcmd.h | 2 ++ - include/configs/tegra186-common.h | 7 ++++++- - 2 files changed, 8 insertions(+), 1 deletion(-) - -diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h -index fc0935fa21..fd1c5f5afa 100644 ---- a/include/config_distro_bootcmd.h -+++ b/include/config_distro_bootcmd.h -@@ -118,8 +118,10 @@ - "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \ - "fi; " - #else -+#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK - #define BOOTENV_EFI_SET_FDTFILE_FALLBACK - #endif -+#endif - - - #define BOOTENV_SHARED_EFI \ -diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h -index 5c3ad35c76..d5f21e0907 100644 ---- a/include/configs/tegra186-common.h -+++ b/include/configs/tegra186-common.h -@@ -20,6 +20,12 @@ - /* Generic Interrupt Controller */ - #define CONFIG_GICV2 - -+#undef FDTFILE -+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ -+ "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ -+ "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \ -+ "fi; " -+ - /* - * Memory layout for where various images get loaded by boot scripts: - * -@@ -49,7 +55,6 @@ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ -- "fdtfile=" FDTFILE "\0" \ - "fdt_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x82100000\0" - --- -2.26.0 - diff --git a/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch b/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch deleted file mode 100644 index 8f28d1ce8884ef04231268099e4b417b70ac93ac..0000000000000000000000000000000000000000 --- a/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 88725c4d036bab25c900cc3c962fc42d94e0ab69 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Wed, 10 Jun 2020 13:26:43 +0100 -Subject: [PATCH] arm: rk3399: enable rng on rock960 and firefly3399 - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/rk3399-firefly-u-boot.dtsi | 4 ++++ - arch/arm/dts/rk3399-rock960-u-boot.dtsi | 4 ++++ - arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ - configs/firefly-rk3399_defconfig | 2 ++ - configs/rock960-rk3399_defconfig | 2 ++ - configs/rockpro64-rk3399_defconfig | 2 ++ - 6 files changed, 18 insertions(+) - -diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi -index 38e0897db9..a6c7b913da 100644 ---- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi -@@ -11,3 +11,7 @@ - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; - }; -+ -+&rng { -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi -index c190089e26..08292dbd39 100644 ---- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi -@@ -24,3 +24,7 @@ - }; - - }; -+ -+&rng { -+ status = "okay"; -+}; -diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -index bac09df4a3..38fe3bb0ec 100644 ---- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -@@ -25,6 +25,10 @@ - }; - }; - -+&rng { -+ status = "okay"; -+}; -+ - &vdd_center { - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; -diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig -index 5bb54f5835..551687d6d0 100644 ---- a/configs/firefly-rk3399_defconfig -+++ b/configs/firefly-rk3399_defconfig -@@ -35,6 +35,8 @@ CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y - CONFIG_SF_DEFAULT_SPEED=20000000 - CONFIG_DM_ETH=y - CONFIG_ETH_DESIGNWARE=y -diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig -index 59a85c78a1..f31cb92884 100644 ---- a/configs/rock960-rk3399_defconfig -+++ b/configs/rock960-rk3399_defconfig -@@ -37,6 +37,8 @@ CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y - CONFIG_DM_ETH=y - CONFIG_NVME=y - CONFIG_PCI=y -diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig -index 807747485a..f778f0b640 100644 ---- a/configs/rockpro64-rk3399_defconfig -+++ b/configs/rockpro64-rk3399_defconfig -@@ -40,6 +40,8 @@ CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y - CONFIG_SPI_FLASH_GIGADEVICE=y - CONFIG_DM_ETH=y - CONFIG_ETH_DESIGNWARE=y --- -2.26.2 - diff --git a/arm-tegra-define-fdtfile-option-for-distro-boot.patch b/arm-tegra-define-fdtfile-option-for-distro-boot.patch deleted file mode 100644 index 923ccb1b0cad6dcea98f6962f209d2e4954c5dba..0000000000000000000000000000000000000000 --- a/arm-tegra-define-fdtfile-option-for-distro-boot.patch +++ /dev/null @@ -1,113 +0,0 @@ -From c3332b102d2ddae01710ae8f4393a2a18a3a1bb3 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Tue, 12 May 2020 08:19:48 +0100 -Subject: [PATCH] arm: tegra: define fdtfile option for distro boot - -For booting via UEFI we need to define the fdtfile option so -bootefi has the option to load a fdtfile from disk. For arm64 -the kernel dtb is located in a vendor directory so we define -that as nvidia for that architecture. - -Signed-off-by: Peter Robinson ---- - include/configs/tegra-common.h | 6 ++++++ - include/configs/tegra114-common.h | 1 + - include/configs/tegra124-common.h | 1 + - include/configs/tegra186-common.h | 1 + - include/configs/tegra20-common.h | 1 + - include/configs/tegra210-common.h | 1 + - include/configs/tegra30-common.h | 1 + - 7 files changed, 12 insertions(+) - -diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h -index 175c55c613..8026f4b32e 100644 ---- a/include/configs/tegra-common.h -+++ b/include/configs/tegra-common.h -@@ -52,6 +52,12 @@ - /* Boot Argument Buffer Size */ - #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -+#ifdef CONFIG_ARM64 -+#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" -+#else -+#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" -+#endif -+ - /*----------------------------------------------------------------------- - * Physical Memory Map - */ -diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h -index d3a7045697..9d751b6740 100644 ---- a/include/configs/tegra114-common.h -+++ b/include/configs/tegra114-common.h -@@ -50,6 +50,7 @@ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ -+ "fdtfile=" FDTFILE "\0" \ - "fdt_addr_r=0x83000000\0" \ - "ramdisk_addr_r=0x83100000\0" - -diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h -index 522993b958..0eb8f92809 100644 ---- a/include/configs/tegra124-common.h -+++ b/include/configs/tegra124-common.h -@@ -52,6 +52,7 @@ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ -+ "fdtfile=" FDTFILE "\0" \ - "fdt_addr_r=0x83000000\0" \ - "ramdisk_addr_r=0x83100000\0" - -diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h -index b4936cc731..5c3ad35c76 100644 ---- a/include/configs/tegra186-common.h -+++ b/include/configs/tegra186-common.h -@@ -49,6 +49,7 @@ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ -+ "fdtfile=" FDTFILE "\0" \ - "fdt_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x82100000\0" - -diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h -index 1e31d82574..fdd8996955 100644 ---- a/include/configs/tegra20-common.h -+++ b/include/configs/tegra20-common.h -@@ -51,6 +51,7 @@ - "scriptaddr=0x10000000\0" \ - "pxefile_addr_r=0x10100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ -+ "fdtfile=" FDTFILE "\0" \ - "fdt_addr_r=0x03000000\0" \ - "ramdisk_addr_r=0x03100000\0" - -diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h -index 1b8e94b60c..2226effe16 100644 ---- a/include/configs/tegra210-common.h -+++ b/include/configs/tegra210-common.h -@@ -46,6 +46,7 @@ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ -+ "fdtfile=" FDTFILE "\0" \ - "fdt_addr_r=0x83000000\0" \ - "ramdisk_addr_r=0x83200000\0" - -diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h -index 54bc6756ab..6c5dc24b26 100644 ---- a/include/configs/tegra30-common.h -+++ b/include/configs/tegra30-common.h -@@ -47,6 +47,7 @@ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ -+ "fdtfile=" FDTFILE "\0" \ - "fdt_addr_r=0x83000000\0" \ - "ramdisk_addr_r=0x83100000\0" - --- -2.26.2 - diff --git a/backport-0001-CVE-2021-27097.patch b/backport-0001-CVE-2021-27097.patch deleted file mode 100644 index 36d7de085e4be3102cb7d15539cf055c93e51a5a..0000000000000000000000000000000000000000 --- a/backport-0001-CVE-2021-27097.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 8a7d4cf9820ea16fabd25a6379351b4dc291204b Mon Sep 17 00:00:00 2001 -From: Simon Glass -Date: Mon, 15 Feb 2021 17:08:05 -0700 -Subject: [PATCH] fdt_region: Check for a single root node of the correct name - -At present fdt_find_regions() assumes that the FIT is a valid devicetree. -If the FIT has two root nodes this is currently not detected in this -function, nor does libfdt's fdt_check_full() notice. Also it is possible -for the root node to have a name even though it should not. - -Add checks for these and return -FDT_ERR_BADSTRUCTURE if a problem is -detected. - -CVE-2021-27097 - -Signed-off-by: Simon Glass -Reported-by: Bruce Monroe -Reported-by: Arie Haenel -Reported-by: Julien Lenoir ---- - common/fdt_region.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/common/fdt_region.c b/common/fdt_region.c -index ff12c518e97..e4ef0ca7703 100644 ---- a/common/fdt_region.c -+++ b/common/fdt_region.c -@@ -43,6 +43,7 @@ int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, - int depth = -1; - int want = 0; - int base = fdt_off_dt_struct(fdt); -+ bool expect_end = false; - - end = path; - *end = '\0'; -@@ -59,6 +60,10 @@ int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, - tag = fdt_next_tag(fdt, offset, &nextoffset); - stop_at = nextoffset; - -+ /* If we see two root nodes, something is wrong */ -+ if (expect_end && tag != FDT_END) -+ return -FDT_ERR_BADLAYOUT; -+ - switch (tag) { - case FDT_PROP: - include = want >= 2; -@@ -81,6 +86,10 @@ int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, - if (depth == FDT_MAX_DEPTH) - return -FDT_ERR_BADSTRUCTURE; - name = fdt_get_name(fdt, offset, &len); -+ -+ /* The root node must have an empty name */ -+ if (!depth && *name) -+ return -FDT_ERR_BADLAYOUT; - if (end - path + 2 + len >= path_len) - return -FDT_ERR_NOSPACE; - if (end != path + 1) -@@ -108,6 +117,8 @@ int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, - while (end > path && *--end != '/') - ; - *end = '\0'; -+ if (depth == -1) -+ expect_end = true; - break; - - case FDT_END: diff --git a/backport-0001-CVE-2021-27138.patch b/backport-0001-CVE-2021-27138.patch deleted file mode 100644 index 0e5d850540027e8501de7aecf1c20402b18a9f89..0000000000000000000000000000000000000000 --- a/backport-0001-CVE-2021-27138.patch +++ /dev/null @@ -1,240 +0,0 @@ -From 79af75f7776fc20b0d7eb6afe1e27c00fdb4b9b4 Mon Sep 17 00:00:00 2001 -From: Simon Glass -Date: Mon, 15 Feb 2021 17:08:06 -0700 -Subject: [PATCH] fit: Don't allow verification of images with @ nodes - -When searching for a node called 'fred', any unit address appended to the -name is ignored by libfdt, meaning that 'fred' can match 'fred@1'. This -means that we cannot be sure that the node originally intended is the one -that is used. - -Disallow use of nodes with unit addresses. - -Update the forge test also, since it uses @ addresses. - -CVE-2021-27138 - -Signed-off-by: Simon Glass -Reported-by: Bruce Monroe -Reported-by: Arie Haenel -Reported-by: Julien Lenoir ---- - common/image-fit-sig.c | 22 ++++++++++++++++++++-- - common/image-fit.c | 20 +++++++++++++++----- - test/py/tests/test_fit.py | 24 ++++++++++++------------ - test/py/tests/vboot_forge.py | 12 ++++++------ - 4 files changed, 53 insertions(+), 25 deletions(-) - -diff --git a/common/image-fit-sig.c b/common/image-fit-sig.c -index 897e04c7a38..34ebb8edfe2 100644 ---- a/common/image-fit-sig.c -+++ b/common/image-fit-sig.c -@@ -149,6 +149,14 @@ static int fit_image_verify_sig(const void *fit, int image_noffset, - fdt_for_each_subnode(noffset, fit, image_noffset) { - const char *name = fit_get_name(fit, noffset, NULL); - -+ /* -+ * We don't support this since libfdt considers names with the -+ * name root but different @ suffix to be equal -+ */ -+ if (strchr(name, '@')) { -+ err_msg = "Node name contains @"; -+ goto error; -+ } - if (!strncmp(name, FIT_SIG_NODENAME, - strlen(FIT_SIG_NODENAME))) { - ret = fit_image_check_sig(fit, noffset, data, -@@ -398,9 +406,10 @@ static int fit_config_verify_sig(const void *fit, int conf_noffset, - return -EPERM; - } - --int fit_config_verify_required_sigs(const void *fit, int conf_noffset, -- const void *sig_blob) -+static int fit_config_verify_required_sigs(const void *fit, int conf_noffset, -+ const void *sig_blob) - { -+ const char *name = fit_get_name(fit, conf_noffset, NULL); - int noffset; - int sig_node; - int verified = 0; -@@ -408,6 +417,15 @@ int fit_config_verify_required_sigs(const void *fit, int conf_noffset, - bool reqd_policy_all = true; - const char *reqd_mode; - -+ /* -+ * We don't support this since libfdt considers names with the -+ * name root but different @ suffix to be equal -+ */ -+ if (strchr(name, '@')) { -+ printf("Configuration node '%s' contains '@'\n", name); -+ return -EPERM; -+ } -+ - /* Work out what we need to verify */ - sig_node = fdt_subnode_offset(sig_blob, 0, FIT_SIG_NODENAME); - if (sig_node < 0) { -diff --git a/common/image-fit.c b/common/image-fit.c -index adc3e551de9..c3dc814115f 100644 ---- a/common/image-fit.c -+++ b/common/image-fit.c -@@ -1369,21 +1369,31 @@ int fit_image_verify_with_data(const void *fit, int image_noffset, - */ - int fit_image_verify(const void *fit, int image_noffset) - { -+ const char *name = fit_get_name(fit, image_noffset, NULL); - const void *data; - size_t size; -- int noffset = 0; - char *err_msg = ""; - -+ if (strchr(name, '@')) { -+ /* -+ * We don't support this since libfdt considers names with the -+ * name root but different @ suffix to be equal -+ */ -+ err_msg = "Node name contains @"; -+ goto err; -+ } - /* Get image data and data length */ - if (fit_image_get_data_and_size(fit, image_noffset, &data, &size)) { - err_msg = "Can't get image data/size"; -- printf("error!\n%s for '%s' hash node in '%s' image node\n", -- err_msg, fit_get_name(fit, noffset, NULL), -- fit_get_name(fit, image_noffset, NULL)); -- return 0; -+ goto err; - } - - return fit_image_verify_with_data(fit, image_noffset, data, size); -+ -+err: -+ printf("error!\n%s in '%s' image node\n", err_msg, -+ fit_get_name(fit, image_noffset, NULL)); -+ return 0; - } - - /** -diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py -index 84b3f958505..6d5b43c3bab 100755 ---- a/test/py/tests/test_fit.py -+++ b/test/py/tests/test_fit.py -@@ -17,7 +17,7 @@ - #address-cells = <1>; - - images { -- kernel@1 { -+ kernel-1 { - data = /incbin/("%(kernel)s"); - type = "kernel"; - arch = "sandbox"; -@@ -26,7 +26,7 @@ - load = <0x40000>; - entry = <0x8>; - }; -- kernel@2 { -+ kernel-2 { - data = /incbin/("%(loadables1)s"); - type = "kernel"; - arch = "sandbox"; -@@ -35,19 +35,19 @@ - %(loadables1_load)s - entry = <0x0>; - }; -- fdt@1 { -+ fdt-1 { - description = "snow"; - data = /incbin/("%(fdt)s"); - type = "flat_dt"; - arch = "sandbox"; - %(fdt_load)s - compression = "%(compression)s"; -- signature@1 { -+ signature-1 { - algo = "sha1,rsa2048"; - key-name-hint = "dev"; - }; - }; -- ramdisk@1 { -+ ramdisk-1 { - description = "snow"; - data = /incbin/("%(ramdisk)s"); - type = "ramdisk"; -@@ -56,7 +56,7 @@ - %(ramdisk_load)s - compression = "%(compression)s"; - }; -- ramdisk@2 { -+ ramdisk-2 { - description = "snow"; - data = /incbin/("%(loadables2)s"); - type = "ramdisk"; -@@ -67,10 +67,10 @@ - }; - }; - configurations { -- default = "conf@1"; -- conf@1 { -- kernel = "kernel@1"; -- fdt = "fdt@1"; -+ default = "conf-1"; -+ conf-1 { -+ kernel = "kernel-1"; -+ fdt = "fdt-1"; - %(ramdisk_config)s - %(loadables_config)s - }; -@@ -410,7 +410,7 @@ def run_fit_test(mkimage): - - # Try a ramdisk - with cons.log.section('Kernel + FDT + Ramdisk load'): -- params['ramdisk_config'] = 'ramdisk = "ramdisk@1";' -+ params['ramdisk_config'] = 'ramdisk = "ramdisk-1";' - params['ramdisk_load'] = 'load = <%#x>;' % params['ramdisk_addr'] - fit = make_fit(mkimage, params) - cons.restart_uboot() -@@ -419,7 +419,7 @@ def run_fit_test(mkimage): - - # Configuration with some Loadables - with cons.log.section('Kernel + FDT + Ramdisk load + Loadables'): -- params['loadables_config'] = 'loadables = "kernel@2", "ramdisk@2";' -+ params['loadables_config'] = 'loadables = "kernel-2", "ramdisk-2";' - params['loadables1_load'] = ('load = <%#x>;' % - params['loadables1_addr']) - params['loadables2_load'] = ('load = <%#x>;' % -diff --git a/test/py/tests/vboot_forge.py b/test/py/tests/vboot_forge.py -index 0fb7ef40247..b41105bd0e3 100644 ---- a/test/py/tests/vboot_forge.py -+++ b/test/py/tests/vboot_forge.py -@@ -376,12 +376,12 @@ def manipulate(root, strblock): - """ - Maliciously manipulates the structure to create a crafted FIT file - """ -- # locate /images/kernel@1 (frankly, it just expects it to be the first one) -+ # locate /images/kernel-1 (frankly, it just expects it to be the first one) - kernel_node = root[0][0] - # clone it to save time filling all the properties - fake_kernel = kernel_node.clone() - # rename the node -- fake_kernel.name = b'kernel@2' -+ fake_kernel.name = b'kernel-2' - # get rid of signatures/hashes - fake_kernel.children = [] - # NOTE: this simply replaces the first prop... either description or data -@@ -391,13 +391,13 @@ def manipulate(root, strblock): - root[0].children.append(fake_kernel) - - # modify the default configuration -- root[1].props[0].value = b'conf@2\x00' -+ root[1].props[0].value = b'conf-2\x00' - # clone the first (only?) configuration - fake_conf = root[1][0].clone() - # rename and change kernel and fdt properties to select the crafted kernel -- fake_conf.name = b'conf@2' -- fake_conf.props[0].value = b'kernel@2\x00' -- fake_conf.props[1].value = b'fdt@1\x00' -+ fake_conf.name = b'conf-2' -+ fake_conf.props[0].value = b'kernel-2\x00' -+ fake_conf.props[1].value = b'fdt-1\x00' - # insert the new configuration under /configurations - root[1].children.append(fake_conf) - diff --git a/backport-0002-CVE-2021-27097.patch b/backport-0002-CVE-2021-27097.patch deleted file mode 100644 index 04ab4894e59d9d1c0b7e00923488eef8a5ffac10..0000000000000000000000000000000000000000 --- a/backport-0002-CVE-2021-27097.patch +++ /dev/null @@ -1,403 +0,0 @@ -From c5819701a3de61e2ba2ef7ad0b616565b32305e5 Mon Sep 17 00:00:00 2001 -From: Simon Glass -Date: Mon, 15 Feb 2021 17:08:09 -0700 -Subject: [PATCH] image: Adjust the workings of fit_check_format() - -At present this function does not accept a size for the FIT. This means -that it must be read from the FIT itself, introducing potential security -risk. Update the function to include a size parameter, which can be -invalid, in which case fit_check_format() calculates it. - -For now no callers pass the size, but this can be updated later. - -Also adjust the return value to an error code so that all the different -types of problems can be distinguished by the user. - -Signed-off-by: Simon Glass -Reported-by: Bruce Monroe -Reported-by: Arie Haenel -Reported-by: Julien Lenoir - ---- - arch/arm/cpu/armv8/sec_firmware.c | 2 +- - cmd/bootm.c | 6 ++-- - cmd/disk.c | 2 +- - cmd/fpga.c | 2 +- - cmd/nand.c | 2 +- - cmd/source.c | 2 +- - cmd/ximg.c | 2 +- - common/image-fdt.c | 2 +- - common/image-fit.c | 45 +++++++++++++++--------------- - common/splash_source.c | 6 ++-- - common/update.c | 2 +- - drivers/fpga/socfpga_arria10.c | 6 ++-- - drivers/net/fsl-mc/mc.c | 2 +- - drivers/net/pfe_eth/pfe_firmware.c | 2 +- - include/image.h | 21 +++++++++++++- - tools/fit_common.c | 3 +- - tools/fit_image.c | 2 +- - tools/mkimage.h | 2 ++ - 18 files changed, 67 insertions(+), 44 deletions(-) - -diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c -index bfc0fac3..0561f5ef 100644 ---- a/arch/arm/cpu/armv8/sec_firmware.c -+++ b/arch/arm/cpu/armv8/sec_firmware.c -@@ -316,7 +316,7 @@ __weak bool sec_firmware_is_valid(const void *sec_firmware_img) - return false; - } - -- if (!fit_check_format(sec_firmware_img)) { -+ if (fit_check_format(sec_firmware_img, IMAGE_SIZE_INVAL)) { - printf("SEC Firmware: Bad firmware image (bad FIT header)\n"); - return false; - } -diff --git a/cmd/bootm.c b/cmd/bootm.c -index d5f877cb..cf9c8def 100644 ---- a/cmd/bootm.c -+++ b/cmd/bootm.c -@@ -291,7 +291,7 @@ static int image_info(ulong addr) - case IMAGE_FORMAT_FIT: - puts(" FIT image found\n"); - -- if (!fit_check_format(hdr)) { -+ if (fit_check_format(hdr, IMAGE_SIZE_INVAL)) { - puts("Bad FIT image format!\n"); - unmap_sysmem(hdr); - return 1; -@@ -368,7 +368,7 @@ static int do_imls_nor(void) - #endif - #if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: -- if (!fit_check_format(hdr)) -+ if (fit_check_format(hdr, IMAGE_SIZE_INVAL)) - goto next_sector; - - printf("FIT Image at %08lX:\n", (ulong)hdr); -@@ -448,7 +448,7 @@ static int nand_imls_fitimage(struct mtd_info *mtd, int nand_dev, loff_t off, - return ret; - } - -- if (!fit_check_format(imgdata)) { -+ if (fit_check_format(imgdata, IMAGE_SIZE_INVAL)) { - free(imgdata); - return 0; - } -diff --git a/cmd/disk.c b/cmd/disk.c -index 8060e753..3195db91 100644 ---- a/cmd/disk.c -+++ b/cmd/disk.c -@@ -114,7 +114,7 @@ int common_diskboot(struct cmd_tbl *cmdtp, const char *intf, int argc, - /* This cannot be done earlier, - * we need complete FIT image in RAM first */ - if (genimg_get_format((void *) addr) == IMAGE_FORMAT_FIT) { -- if (!fit_check_format(fit_hdr)) { -+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) { - bootstage_error(BOOTSTAGE_ID_IDE_FIT_READ); - puts("** Bad FIT image format\n"); - return 1; -diff --git a/cmd/fpga.c b/cmd/fpga.c -index 8ae1c936..51410a8e 100644 ---- a/cmd/fpga.c -+++ b/cmd/fpga.c -@@ -330,7 +330,7 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, - return CMD_RET_FAILURE; - } - -- if (!fit_check_format(fit_hdr)) { -+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) { - puts("Bad FIT image format\n"); - return CMD_RET_FAILURE; - } -diff --git a/cmd/nand.c b/cmd/nand.c -index 92d039af..97e117a9 100644 ---- a/cmd/nand.c -+++ b/cmd/nand.c -@@ -917,7 +917,7 @@ static int nand_load_image(struct cmd_tbl *cmdtp, struct mtd_info *mtd, - #if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { -- if (!fit_check_format (fit_hdr)) { -+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) { - bootstage_error(BOOTSTAGE_ID_NAND_FIT_READ); - puts ("** Bad FIT image format\n"); - return 1; -diff --git a/cmd/source.c b/cmd/source.c -index b6c709a3..71f71528 100644 ---- a/cmd/source.c -+++ b/cmd/source.c -@@ -107,7 +107,7 @@ int image_source_script(ulong addr, const char *fit_uname) - #if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = buf; -- if (!fit_check_format (fit_hdr)) { -+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) { - puts ("Bad FIT image format\n"); - return 1; - } -diff --git a/cmd/ximg.c b/cmd/ximg.c -index 159ba516..ef738ebf 100644 ---- a/cmd/ximg.c -+++ b/cmd/ximg.c -@@ -136,7 +136,7 @@ do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) - "at %08lx ...\n", uname, addr); - - fit_hdr = (const void *)addr; -- if (!fit_check_format(fit_hdr)) { -+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) { - puts("Bad FIT image format\n"); - return 1; - } -diff --git a/common/image-fdt.c b/common/image-fdt.c -index b63e772b..0b770e27 100644 ---- a/common/image-fdt.c -+++ b/common/image-fdt.c -@@ -399,7 +399,7 @@ int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, - */ - #if CONFIG_IS_ENABLED(FIT) - /* check FDT blob vs FIT blob */ -- if (fit_check_format(buf)) { -+ if (!fit_check_format(buf, IMAGE_SIZE_INVAL)) { - ulong load, len; - - fdt_noffset = boot_get_fdt_fit(images, -diff --git a/common/image-fit.c b/common/image-fit.c -index 1ece100a..470321c5 100644 ---- a/common/image-fit.c -+++ b/common/image-fit.c -@@ -8,6 +8,8 @@ - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -+#define LOG_CATEGORY LOGC_BOOT -+ - #ifdef USE_HOSTCC - #include "mkimage.h" - #include -@@ -1533,40 +1535,39 @@ int fit_image_check_comp(const void *fit, int noffset, uint8_t comp) - return (comp == image_comp); - } - --/** -- * fit_check_format - sanity check FIT image format -- * @fit: pointer to the FIT format image header -- * -- * fit_check_format() runs a basic sanity FIT image verification. -- * Routine checks for mandatory properties, nodes, etc. -- * -- * returns: -- * 1, on success -- * 0, on failure -- */ --int fit_check_format(const void *fit) -+int fit_check_format(const void *fit, ulong size) - { -+ int ret; -+ -+ /* A FIT image must be a valid FDT */ -+ ret = fdt_check_header(fit); -+ if (ret) { -+ log_debug("Wrong FIT format: not a flattened device tree (err=%d)\n", -+ ret); -+ return -ENOEXEC; -+ } -+ - /* mandatory / node 'description' property */ -- if (fdt_getprop(fit, 0, FIT_DESC_PROP, NULL) == NULL) { -- debug("Wrong FIT format: no description\n"); -- return 0; -+ if (!fdt_getprop(fit, 0, FIT_DESC_PROP, NULL)) { -+ log_debug("Wrong FIT format: no description\n"); -+ return -ENOMSG; - } - - if (IMAGE_ENABLE_TIMESTAMP) { - /* mandatory / node 'timestamp' property */ -- if (fdt_getprop(fit, 0, FIT_TIMESTAMP_PROP, NULL) == NULL) { -- debug("Wrong FIT format: no timestamp\n"); -- return 0; -+ if (!fdt_getprop(fit, 0, FIT_TIMESTAMP_PROP, NULL)) { -+ log_debug("Wrong FIT format: no timestamp\n"); -+ return -ENODATA; - } - } - - /* mandatory subimages parent '/images' node */ - if (fdt_path_offset(fit, FIT_IMAGES_PATH) < 0) { -- debug("Wrong FIT format: no images parent node\n"); -- return 0; -+ log_debug("Wrong FIT format: no images parent node\n"); -+ return -ENOENT; - } - -- return 1; -+ return 0; - } - - -@@ -1899,7 +1900,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr, - printf("## Loading %s from FIT Image at %08lx ...\n", prop_name, addr); - - bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT); -- if (!fit_check_format(fit)) { -+ if (fit_check_format(fit, IMAGE_SIZE_INVAL)) { - printf("Bad FIT %s image format!\n", prop_name); - bootstage_error(bootstage_id + BOOTSTAGE_SUB_FORMAT); - return -ENOEXEC; -diff --git a/common/splash_source.c b/common/splash_source.c -index f51ca5dd..bad9a779 100644 ---- a/common/splash_source.c -+++ b/common/splash_source.c -@@ -336,10 +336,10 @@ static int splash_load_fit(struct splash_location *location, u32 bmp_load_addr) - if (res < 0) - return res; - -- res = fit_check_format(fit_header); -- if (!res) { -+ res = fit_check_format(fit_header, IMAGE_SIZE_INVAL); -+ if (res) { - debug("Could not find valid FIT image\n"); -- return -EINVAL; -+ return res; - } - - /* Get the splash image node */ -diff --git a/common/update.c b/common/update.c -index c8dd346a..12626706 100644 ---- a/common/update.c -+++ b/common/update.c -@@ -282,7 +282,7 @@ int update_tftp(ulong addr, char *interface, char *devstring) - got_update_file: - fit = (void *)addr; - -- if (!fit_check_format((void *)fit)) { -+ if (fit_check_format((void *)fit, IMAGE_SIZE_INVAL)) { - printf("Bad FIT format of the update file, aborting " - "auto-update\n"); - return 1; -diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c -index dfd3cbb4..c80c4bc3 100644 ---- a/drivers/fpga/socfpga_arria10.c -+++ b/drivers/fpga/socfpga_arria10.c -@@ -564,10 +564,10 @@ static int first_loading_rbf_to_buffer(struct udevice *dev, - if (ret < 0) - return ret; - -- ret = fit_check_format(buffer_p); -- if (!ret) { -+ ret = fit_check_format(buffer_p, IMAGE_SIZE_INVAL); -+ if (ret) { - debug("FPGA: No valid FIT image was found.\n"); -- return -EBADF; -+ return ret; - } - - confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH); -diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c -index e516c3c1..c7df8d24 100644 ---- a/drivers/net/fsl-mc/mc.c -+++ b/drivers/net/fsl-mc/mc.c -@@ -141,7 +141,7 @@ int parse_mc_firmware_fit_image(u64 mc_fw_addr, - return -EINVAL; - } - -- if (!fit_check_format(fit_hdr)) { -+ if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) { - printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n"); - return -EINVAL; - } -diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c -index 0493cfe8..b0ef83c5 100644 ---- a/drivers/net/pfe_eth/pfe_firmware.c -+++ b/drivers/net/pfe_eth/pfe_firmware.c -@@ -154,7 +154,7 @@ static int pfe_fit_check(void) - return ret; - } - -- if (!fit_check_format(pfe_fit_addr)) { -+ if (fit_check_format(pfe_fit_addr, IMAGE_SIZE_INVAL)) { - printf("PFE Firmware: Bad firmware image (bad FIT header)\n"); - ret = -1; - return ret; -diff --git a/include/image.h b/include/image.h -index ad81dad4..2ea5a685 100644 ---- a/include/image.h -+++ b/include/image.h -@@ -116,6 +116,9 @@ extern ulong image_load_addr; /* Default Load Address */ - extern ulong image_save_addr; /* Default Save Address */ - extern ulong image_save_size; /* Default Save Size */ - -+/* An invalid size, meaning that the image size is not known */ -+#define IMAGE_SIZE_INVAL (-1UL) -+ - enum ih_category { - IH_ARCH, - IH_COMP, -@@ -1112,7 +1115,23 @@ int fit_image_check_os(const void *fit, int noffset, uint8_t os); - int fit_image_check_arch(const void *fit, int noffset, uint8_t arch); - int fit_image_check_type(const void *fit, int noffset, uint8_t type); - int fit_image_check_comp(const void *fit, int noffset, uint8_t comp); --int fit_check_format(const void *fit); -+ -+/** -+ * fit_check_format() - Check that the FIT is valid -+ * -+ * This performs various checks on the FIT to make sure it is suitable for -+ * use, looking for mandatory properties, nodes, etc. -+ * -+ * If FIT_FULL_CHECK is enabled, it also runs it through libfdt to make -+ * sure that there are no strange tags or broken nodes in the FIT. -+ * -+ * @fit: pointer to the FIT format image header -+ * @return 0 if OK, -ENOEXEC if not an FDT file, -EINVAL if the full FDT check -+ * failed (e.g. due to bad structure), -ENOMSG if the description is -+ * missing, -ENODATA if the timestamp is missing, -ENOENT if the /images -+ * path is missing -+ */ -+int fit_check_format(const void *fit, ulong size); - - int fit_conf_find_compat(const void *fit, const void *fdt); - -diff --git a/tools/fit_common.c b/tools/fit_common.c -index cdf987d3..52b63296 100644 ---- a/tools/fit_common.c -+++ b/tools/fit_common.c -@@ -26,7 +26,8 @@ - int fit_verify_header(unsigned char *ptr, int image_size, - struct image_tool_params *params) - { -- if (fdt_check_header(ptr) != EXIT_SUCCESS || !fit_check_format(ptr)) -+ if (fdt_check_header(ptr) != EXIT_SUCCESS || -+ fit_check_format(ptr, IMAGE_SIZE_INVAL)) - return EXIT_FAILURE; - - return EXIT_SUCCESS; -diff --git a/tools/fit_image.c b/tools/fit_image.c -index a082d938..44990822 100644 ---- a/tools/fit_image.c -+++ b/tools/fit_image.c -@@ -883,7 +883,7 @@ static int fit_extract_contents(void *ptr, struct image_tool_params *params) - /* Indent string is defined in header image.h */ - p = IMAGE_INDENT_STRING; - -- if (!fit_check_format(fit)) { -+ if (fit_check_format(fit, IMAGE_SIZE_INVAL)) { - printf("Bad FIT image format\n"); - return -1; - } -diff --git a/tools/mkimage.h b/tools/mkimage.h -index 5b096a54..0d314844 100644 ---- a/tools/mkimage.h -+++ b/tools/mkimage.h -@@ -29,6 +29,8 @@ - #define debug(fmt,args...) - #endif /* MKIMAGE_DEBUG */ - -+#define log_debug(fmt, args...) debug(fmt, ##args) -+ - static inline void *map_sysmem(ulong paddr, unsigned long len) - { - return (void *)(uintptr_t)paddr; --- -2.23.0 - diff --git a/backport-0002-CVE-2021-27138.patch b/backport-0002-CVE-2021-27138.patch deleted file mode 100644 index 2c74fee71dcca2939bca58d0276302307936b690..0000000000000000000000000000000000000000 --- a/backport-0002-CVE-2021-27138.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 3f04db891a353f4b127ed57279279f851c6b4917 Mon Sep 17 00:00:00 2001 -From: Simon Glass -Date: Mon, 15 Feb 2021 17:08:12 -0700 -Subject: [PATCH] image: Check for unit addresses in FITs - -Using unit addresses in a FIT is a security risk. Add a check for this -and disallow it. - -CVE-2021-27138 - -Signed-off-by: Simon Glass -Reported-by: Bruce Monroe -Reported-by: Arie Haenel -Reported-by: Julien Lenoir ---- - common/image-fit.c | 56 ++++++++++++++++++++++++++++++++++++++++++---- - 1 file changed, 52 insertions(+), 4 deletions(-) - -diff --git a/common/image-fit.c b/common/image-fit.c -index 47f3b7f7..3d173ad4 100644 ---- a/common/image-fit.c -+++ b/common/image-fit.c -@@ -1545,6 +1545,34 @@ int fit_image_check_comp(const void *fit, int noffset, uint8_t comp) - return (comp == image_comp); - } - -+/** -+ * fdt_check_no_at() - Check for nodes whose names contain '@' -+ * -+ * This checks the parent node and all subnodes recursively -+ * -+ * @fit: FIT to check -+ * @parent: Parent node to check -+ * @return 0 if OK, -EADDRNOTAVAIL is a node has a name containing '@' -+ */ -+static int fdt_check_no_at(const void *fit, int parent) -+{ -+ const char *name; -+ int node; -+ int ret; -+ -+ name = fdt_get_name(fit, parent, NULL); -+ if (!name || strchr(name, '@')) -+ return -EADDRNOTAVAIL; -+ -+ fdt_for_each_subnode(node, fit, parent) { -+ ret = fdt_check_no_at(fit, node); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ - int fit_check_format(const void *fit, ulong size) - { - int ret; -@@ -1566,10 +1594,27 @@ int fit_check_format(const void *fit, ulong size) - if (size == IMAGE_SIZE_INVAL) - size = fdt_totalsize(fit); - ret = fdt_check_full(fit, size); -+ if (ret) -+ ret = -EINVAL; -+ -+ /* -+ * U-Boot stopped using unit addressed in 2017. Since libfdt -+ * can match nodes ignoring any unit address, signature -+ * verification can see the wrong node if one is inserted with -+ * the same name as a valid node but with a unit address -+ * attached. Protect against this by disallowing unit addresses. -+ */ -+ if (!ret && CONFIG_IS_ENABLED(FIT_SIGNATURE)) { -+ ret = fdt_check_no_at(fit, 0); - -+ if (ret) { -+ log_debug("FIT check error %d\n", ret); -+ return ret; -+ } -+ } - if (ret) { - log_debug("FIT check error %d\n", ret); -- return -EINVAL; -+ return ret; - } - } - -@@ -1926,10 +1971,13 @@ int fit_image_load(bootm_headers_t *images, ulong addr, - printf("## Loading %s from FIT Image at %08lx ...\n", prop_name, addr); - - bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT); -- if (fit_check_format(fit, IMAGE_SIZE_INVAL)) { -- printf("Bad FIT %s image format!\n", prop_name); -+ ret = fit_check_format(fit, IMAGE_SIZE_INVAL); -+ if (ret) { -+ printf("Bad FIT %s image format! (err=%d)\n", prop_name, ret); -+ if (CONFIG_IS_ENABLED(FIT_SIGNATURE) && ret == -EADDRNOTAVAIL) -+ printf("Signature checking prevents use of unit addresses (@) in nodes\n"); - bootstage_error(bootstage_id + BOOTSTAGE_SUB_FORMAT); -- return -ENOEXEC; -+ return ret; - } - bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT_OK); - if (fit_uname) { --- -2.23.0 - diff --git a/backport-0003-CVE-2021-27097.patch b/backport-0003-CVE-2021-27097.patch deleted file mode 100644 index aae141c3d221a0146187b7e940a73c451c53a0ec..0000000000000000000000000000000000000000 --- a/backport-0003-CVE-2021-27097.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 6f3c2d8aa5e6cbd80b5e869bbbddecb66c329d01 Mon Sep 17 00:00:00 2001 -From: Simon Glass -Date: Mon, 15 Feb 2021 17:08:10 -0700 -Subject: [PATCH] image: Add an option to do a full check of the FIT - -Some strange modifications of the FIT can introduce security risks. Add an -option to check it thoroughly, using libfdt's fdt_check_full() function. - -Enable this by default if signature verification is enabled. - -CVE-2021-27097 - -Signed-off-by: Simon Glass -Reported-by: Bruce Monroe -Reported-by: Arie Haenel -Reported-by: Julien Lenoir ---- - Kconfig | 19 +++++++++++++++++++ - common/image-fit.c | 18 +++++++++++++++++- - 2 files changed, 36 insertions(+), 1 deletion(-) - -diff --git a/Kconfig b/Kconfig -index 8f3fba08..11b480f6 100644 ---- a/Kconfig -+++ b/Kconfig -@@ -365,6 +365,15 @@ config FIT_ENABLE_SHA256_SUPPORT - SHA256 variant is supported: SHA512 and others are not currently - supported in U-Boot. - -+config FIT_FULL_CHECK -+ bool "Do a full check of the FIT before using it" -+ default y -+ help -+ Enable this do a full check of the FIT to make sure it is valid. This -+ helps to protect against carefully crafted FITs which take advantage -+ of bugs or omissions in the code. This includes a bad structure, -+ multiple root nodes and the like. -+ - config FIT_SIGNATURE - bool "Enable signature verification of FIT uImages" - depends on DM -@@ -372,6 +381,7 @@ config FIT_SIGNATURE - select RSA - select RSA_VERIFY - select IMAGE_SIGN_INFO -+ select FIT_FULL_CHECK - help - This option enables signature verification of FIT uImages, - using a hash signed and verified using RSA. If -@@ -455,6 +465,14 @@ config SPL_FIT_PRINT - help - Support printing the content of the fitImage in a verbose manner in SPL. - -+config SPL_FIT_FULL_CHECK -+ bool "Do a full check of the FIT before using it" -+ help -+ Enable this do a full check of the FIT to make sure it is valid. This -+ helps to protect against carefully crafted FITs which take advantage -+ of bugs or omissions in the code. This includes a bad structure, -+ multiple root nodes and the like. -+ - config SPL_FIT_SIGNATURE - bool "Enable signature verification of FIT firmware within SPL" - depends on SPL_DM -@@ -462,6 +480,7 @@ config SPL_FIT_SIGNATURE - select SPL_RSA - select SPL_RSA_VERIFY - select SPL_IMAGE_SIGN_INFO -+ select SPL_FIT_FULL_CHECK - - config SPL_LOAD_FIT - bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)" -diff --git a/common/image-fit.c b/common/image-fit.c -index 470321c5..e49baea7 100644 ---- a/common/image-fit.c -+++ b/common/image-fit.c -@@ -17,7 +17,6 @@ - #include - #else - #include --#include - #include - #include - #include -@@ -29,6 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; - - #include - #include -+#include - #include - #include - #include -@@ -1547,6 +1547,22 @@ int fit_check_format(const void *fit, ulong size) - return -ENOEXEC; - } - -+ if (CONFIG_IS_ENABLED(FIT_FULL_CHECK)) { -+ /* -+ * If we are not given the size, make do wtih calculating it. -+ * This is not as secure, so we should consider a flag to -+ * control this. -+ */ -+ if (size == IMAGE_SIZE_INVAL) -+ size = fdt_totalsize(fit); -+ ret = fdt_check_full(fit, size); -+ -+ if (ret) { -+ log_debug("FIT check error %d\n", ret); -+ return -EINVAL; -+ } -+ } -+ - /* mandatory / node 'description' property */ - if (!fdt_getprop(fit, 0, FIT_DESC_PROP, NULL)) { - log_debug("Wrong FIT format: no description\n"); --- -2.23.0 - diff --git a/dragonboard-fixes.patch b/dragonboard-fixes.patch index c49ea50196b8c0a51156ccaa48f6cd960de0ab0d..892a024d8c1d6ed337db57f48be7b700d1273d02 100644 --- a/dragonboard-fixes.patch +++ b/dragonboard-fixes.patch @@ -80,16 +80,16 @@ diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconf index a55abaf8df5..4ece0cafbe4 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig -@@ -7,6 +7,8 @@ CONFIG_NR_DRAM_BANKS=1 +@@ -10,6 +10,8 @@ CONFIG_DISTRO_DEFAULTS=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y +CONFIG_FAT_WRITE=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y - CONFIG_MISC_INIT_R=y + CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -@@ -41,6 +43,13 @@ CONFIG_DM_PMIC=y +@@ -45,6 +47,13 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_PM8916=y CONFIG_MSM_SERIAL=y CONFIG_SPMI_MSM=y @@ -101,15 +101,16 @@ index a55abaf8df5..4ece0cafbe4 100644 +CONFIG_VIDEO_SIMPLE=y +CONFIG_USB_KEYBOARD=y CONFIG_USB=y - CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -@@ -57,5 +66,6 @@ CONFIG_USB_HOST_ETHER=y + CONFIG_USB_EHCI_MSM=y +@@ -54,6 +63,7 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y - CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 -- 2.19.1 diff --git a/rockchip-Pinebook-Pro-Fixes.patch b/rockchip-Pinebook-Pro-Fixes.patch deleted file mode 100644 index 0b0a2d7159b720675ec70a8317baee9d83e3a632..0000000000000000000000000000000000000000 --- a/rockchip-Pinebook-Pro-Fixes.patch +++ /dev/null @@ -1,200 +0,0 @@ -From e27621a7c2c0e090977c17f604093c720ca01fe4 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 8 Jun 2020 20:31:33 +0100 -Subject: [PATCH 1/3] rockchip: Pinebook Pro: enable rng to provide an entropy - source - -Enable the rng so UEFI can provide entropy for KASLR - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4 ++++ - arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ - configs/pinebook-pro-rk3399_defconfig | 2 ++ - 3 files changed, 10 insertions(+) - -diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -index 1a2e24d3ef..296321d697 100644 ---- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -@@ -24,6 +24,10 @@ - u-boot,dm-pre-reloc; - }; - -+&rng { -+ status = "okay"; -+}; -+ - &sdhci { - max-frequency = <25000000>; - u-boot,dm-pre-reloc; -diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -index bac09df4a3..cb8991aa25 100644 ---- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi -@@ -19,6 +19,10 @@ - }; - }; - -+&rng { -+ status = "okay"; -+}; -+ - &spi1 { - spi_flash: flash@0 { - u-boot,dm-pre-reloc; -diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -index 0c129b9aeb..21eecf477c 100644 ---- a/configs/pinebook-pro-rk3399_defconfig -+++ b/configs/pinebook-pro-rk3399_defconfig -@@ -54,6 +54,8 @@ CONFIG_DM_PMIC_FAN53555=y - CONFIG_PMIC_RK8XX=y - CONFIG_REGULATOR_PWM=y - CONFIG_REGULATOR_RK8XX=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y - CONFIG_PWM_ROCKCHIP=y - CONFIG_RAM_RK3399_LPDDR4=y - CONFIG_DM_RESET=y --- -2.26.2 - -From 99a3c9ba5a8ab7a94aa700649e031f53d498e857 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 8 Jun 2020 22:23:05 +0100 -Subject: [PATCH 2/3] rockchip: Pinebook Pro: Fix USB and the USB attached - keyboard - -The built in keyboard on the Pinebook Pro is attached via USB so -fix this up to ensure USB works as expected. - -Signed-off-by: Peter Robinson ---- - configs/pinebook-pro-rk3399_defconfig | 5 +++++ - include/configs/pinebook-pro-rk3399.h | 3 +++ - 2 files changed, 8 insertions(+) - -diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -index 21eecf477c..733463556a 100644 ---- a/configs/pinebook-pro-rk3399_defconfig -+++ b/configs/pinebook-pro-rk3399_defconfig -@@ -61,6 +61,8 @@ CONFIG_RAM_RK3399_LPDDR4=y - CONFIG_DM_RESET=y - CONFIG_BAUDRATE=1500000 - CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="usb start" - CONFIG_ROCKCHIP_SPI=y - CONFIG_SYSRESET=y - CONFIG_USB=y -@@ -68,8 +70,11 @@ CONFIG_USB_XHCI_HCD=y - CONFIG_USB_XHCI_DWC3=y - CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y - CONFIG_USB_DWC3=y - CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_DM_KEYBOARD=y - CONFIG_USB_KEYBOARD=y - CONFIG_USB_HOST_ETHER=y - CONFIG_USB_ETHER_ASIX=y -diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h -index 4bc8802d11..d910830582 100644 ---- a/include/configs/pinebook-pro-rk3399.h -+++ b/include/configs/pinebook-pro-rk3399.h -@@ -25,4 +25,7 @@ - - #define SDRAM_BANK_SIZE (2UL << 30) - -+#define CONFIG_USB_OHCI_NEW -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -+ - #endif --- -2.26.2 - -From 64d43a4f0a135486a9a524b107c853831e492eb6 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Mon, 8 Jun 2020 23:41:50 +0100 -Subject: [PATCH 3/3] rockchip: Pinebook Pro: Fix SPI flash and store env on it - -Some minor fixes for SPI flash on the Pinebook Pro and also -default to saving environment to the SPI flash as it's -guaranteed to be on board. - -Signed-off-by: Peter Robinson ---- - arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 6 +++++- - configs/pinebook-pro-rk3399_defconfig | 3 +++ - include/configs/pinebook-pro-rk3399.h | 9 --------- - 3 files changed, 8 insertions(+), 10 deletions(-) - -diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -index 296321d697..ded7db0aef 100644 ---- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi -@@ -12,7 +12,11 @@ - }; - - chosen { -- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc; -+ }; -+ -+ config { -+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ - }; - }; - -diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig -index 733463556a..18b2d74253 100644 ---- a/configs/pinebook-pro-rk3399_defconfig -+++ b/configs/pinebook-pro-rk3399_defconfig -@@ -1,6 +1,7 @@ - CONFIG_ARM=y - CONFIG_ARCH_ROCKCHIP=y - CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_ENV_SIZE=0x8000 - CONFIG_ROCKCHIP_RK3399=y - CONFIG_TARGET_PINEBOOK_PRO_RK3399=y - CONFIG_NR_DRAM_BANKS=1 -@@ -17,6 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y - CONFIG_SPL_STACK_R=y - CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 - CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_SPL_SPI_LOAD=y - CONFIG_TPL=y - CONFIG_CMD_BOOTZ=y - CONFIG_CMD_GPIO=y -@@ -32,6 +34,7 @@ CONFIG_CMD_REGULATOR=y - CONFIG_SPL_OF_CONTROL=y - CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" - CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_SPI_FLASH=y - CONFIG_SYS_RELOC_GD_ENV_ADDR=y - CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y -diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h -index d910830582..d478b19917 100644 ---- a/include/configs/pinebook-pro-rk3399.h -+++ b/include/configs/pinebook-pro-rk3399.h -@@ -14,15 +14,6 @@ - - #include - --#if defined(CONFIG_ENV_IS_IN_MMC) --#define CONFIG_SYS_MMC_ENV_DEV 0 --#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) --#define CONFIG_ENV_SECT_SIZE (8 * 1024) --#endif -- --#undef CONFIG_SYS_SPI_U_BOOT_OFFS --#define CONFIG_SYS_SPI_U_BOOT_OFFS 1024 * 512 -- - #define SDRAM_BANK_SIZE (2UL << 30) - - #define CONFIG_USB_OHCI_NEW --- -2.26.2 - diff --git a/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch b/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch index 0e30129caccdcfb5274ae26f283fd626b2d8ce93..5d7d7901c45820d094a3038ea3a9d3f374f292bd 100644 --- a/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch +++ b/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch @@ -5,15 +5,16 @@ Subject: [PATCH] rpi: Use firmware provided device tree Signed-off-by: Peter Robinson --- - configs/rpi_0_w_defconfig | 2 +- - configs/rpi_2_defconfig | 2 +- - configs/rpi_3_32b_defconfig | 2 +- - configs/rpi_3_defconfig | 2 +- - configs/rpi_defconfig | 2 +- - 5 files changed, 5 insertions(+), 5 deletions(-) - + configs/rpi_0_w_defconfig | 2 +- + configs/rpi_2_defconfig | 2 +- + configs/rpi_3_32b_defconfig | 2 +- + configs/rpi_3_b_plus_defconfig | 2 +- + configs/rpi_3_defconfig | 2 +- + configs/rpi_defconfig | 2 +- + 6 files changed, 6 insertions(+), 6 deletions(-) + diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig -index 5053a38822..3c6af2b367 100644 +index bba5e12b12..0241f4c6d3 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y @@ -22,11 +23,11 @@ index 5053a38822..3c6af2b367 100644 CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y - CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig -index 0000a759f1..f27c5ab1f6 100644 +index 1c2bbb29ce..9573e475f4 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y @@ -35,11 +36,11 @@ index 0000a759f1..f27c5ab1f6 100644 CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y - CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig -index a714f9ec49..90ce6ea22e 100644 +index b8a3d17f43..252df994e6 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y @@ -48,11 +49,24 @@ index a714f9ec49..90ce6ea22e 100644 CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y - CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig +index 4c361438fa..3b2996a2f9 100644 +--- a/configs/rpi_3_b_plus_defconfig ++++ b/configs/rpi_3_b_plus_defconfig +@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y +-CONFIG_OF_EMBED=y ++CONFIG_OF_BOARD=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig -index 244d9b3a78..f72d6d35e2 100644 +index 9b281a4f15..1e9ee6122e 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y @@ -61,11 +75,11 @@ index 244d9b3a78..f72d6d35e2 100644 CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y - CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig -index 64bb184c2b..645dbbec33 100644 +index b5ad53c37b..223fc03275 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y @@ -74,9 +88,8 @@ index 64bb184c2b..645dbbec33 100644 CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y - CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -- -2.26.2 diff --git a/u-boot-2020.07.tar.bz2 b/u-boot-2021.10.tar.bz2 similarity index 60% rename from u-boot-2020.07.tar.bz2 rename to u-boot-2021.10.tar.bz2 index c68c5a6150f615df3e492db3740f907cb315d521..e7b569f79ecd38de4e707069d6e8f85e954a10dd 100644 Binary files a/u-boot-2020.07.tar.bz2 and b/u-boot-2021.10.tar.bz2 differ diff --git a/uboot-tools.spec b/uboot-tools.spec index 4f543c6c37bae4514541279660b7d26b7c75deac..0c37080df322da6fe4b2f150e72a112cc9cc15cc 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -2,8 +2,8 @@ %global with_armv8 1 Name: uboot-tools -Version: 2020.07 -Release: 7 +Version: 2021.10 +Release: 1 Summary: tools for U-Boot License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -18,22 +18,11 @@ Patch0001: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch # Board fixes and enablement Patch0002: usb-kbd-fixes.patch Patch0003: dragonboard-fixes.patch -# Tegra improvements -Patch0004: arm-tegra-define-fdtfile-option-for-distro-boot.patch -Patch0005: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch -# AllWinner improvements -Patch0006: AllWinner-Pine64-bits.patch + # Rockchips improvements -Patch0007: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch Patch0008: rockchip-Pinebook-Pro-Fixes.patch # RPi4 -Patch0009: USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch Patch0010: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch -Patch0011: backport-0001-CVE-2021-27097.patch -Patch0012: backport-0002-CVE-2021-27097.patch -Patch0013: backport-0003-CVE-2021-27097.patch -Patch0014: backport-0001-CVE-2021-27138.patch -Patch0015: backport-0002-CVE-2021-27138.patch BuildRequires: bc dtc gcc make flex bison git-core openssl-devel BuildRequires: python3-unversioned-command python3-devel python3-setuptools @@ -250,12 +239,15 @@ cp -p board/warp7/README builds/docs/README.warp7 %files help %doc README doc/README.kwbimage doc/README.distro doc/README.gpt -%doc doc/README.odroid doc/README.rockchip doc/uefi doc/uImage.FIT -%doc doc/README.chromium builds/docs/* doc/arch/arm64.rst +%doc doc/README.odroid doc/README.rockchip doc/uImage.FIT +%doc builds/docs/* doc/arch/arm64.rst %doc doc/board/amlogic/ doc/board/rockchip/ %{_mandir}/man1/mkimage.1* %changelog +* Mon Dec 6 2021 yangcheng - 2021.10-1 +- Upgrade to 2021.10 + * Wed Jul 21 2021 yushaogui - 2020.07-7 - Delete a Buildrequires for gdb diff --git a/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch b/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch index c5ecb618bcbf83eafe3b23535acfe57246e0636c..48cad2319b3846f64a0e478df0e1aee9390b9f6b 100644 --- a/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch +++ b/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch @@ -22,14 +22,14 @@ knows) and SoC/board specific ${fdtfile} (which grub does not know). Signed-off-by: Rob Clark Signed-off-by: Peter Robinson --- - include/config_distro_bootcmd.h | 34 ++++++++++++++++++++++----------- - 1 file changed, 23 insertions(+), 11 deletions(-) - + include/config_distro_bootcmd.h | 35 ++++++++++++++++++++++----------- + 1 file changed, 23 insertions(+), 12 deletions(-) + diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h -index 4993303f4d..f4b3b62fca 100644 +index 2627c2a6a5..eadd1080b3 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h -@@ -138,25 +138,37 @@ +@@ -148,26 +148,37 @@ "fi\0" \ \ "load_efi_dtb=" \ @@ -51,6 +51,7 @@ index 4993303f4d..f4b3b62fca 100644 - "run load_efi_dtb; " \ - "fi;" \ - "done;" \ +- "run boot_efi_bootmgr;" \ + "part list ${devtype} ${devnum} dtb_devplist; " \ + "env exists dtb_devplist || setenv dtb_devplist " \ + "${distro_bootpart}; " \ @@ -78,6 +79,4 @@ index 4993303f4d..f4b3b62fca 100644 "echo EFI LOAD FAILED: continuing...; " \ "fi; " \ "setenv efi_fdtfile\0" --- -2.21.0 - +-- \ No newline at end of file