diff --git a/10-devicetree.install b/10-devicetree.install index 752e5d062449bab61559155fed659851bd91fdb4..3345391b682e72a8cb6041ad9bb7e291bbf84eec 100644 --- a/10-devicetree.install +++ b/10-devicetree.install @@ -9,6 +9,18 @@ KERNEL_VERSION="$2" #BOOT_DIR_ABS="$3" #KERNEL_IMAGE="$4" +[ -f /etc/u-boot.conf ] && source /etc/u-boot.conf || true +[ -z "$FIRMWAREDT" ] || FirmwareDT=$FIRMWAREDT + +if [[ $FirmwareDT == "True" ]] +then + # if we want to use firmware DT we remove symlink to current kernel DT + if [ -h /boot/dtb ]; then + rm -f /boot/dtb + fi + exit 0 +fi + # Setup a /boot/dtb -> /boot/dtb-$newest_kernel_version symlink so that # u-boot can find the correct dtb to load. # diff --git a/AllWinner-Pine64-bits.patch b/AllWinner-Pine64-bits.patch new file mode 100644 index 0000000000000000000000000000000000000000..569afc8d45bca6a63f34d41a0abc303158b033bf --- /dev/null +++ b/AllWinner-Pine64-bits.patch @@ -0,0 +1,2172 @@ +From 2c213379d9ec786480a655f8c5687b2df376017f Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 12:27:15 +0000 +Subject: [PATCH 1/9] arm: dts: AllWinner: sync sun50i-a64.dtsi to 5.6-rc1 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/sun50i-a64.dtsi | 472 ++++++++++++++++++++++++++++------- + 1 file changed, 387 insertions(+), 85 deletions(-) + +diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi +index ff41abc96a..862b47dc9d 100644 +--- a/arch/arm/dts/sun50i-a64.dtsi ++++ b/arch/arm/dts/sun50i-a64.dtsi +@@ -1,46 +1,7 @@ +-/* +- * Copyright (C) 2016 ARM Ltd. +- * based on the Allwinner H3 dtsi: +- * Copyright (C) 2015 Jens Kuske +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2016 ARM Ltd. ++// based on the Allwinner H3 dtsi: ++// Copyright (C) 2015 Jens Kuske + + #include + #include +@@ -49,6 +10,7 @@ + #include + #include + #include ++#include + + / { + interrupt-parent = <&gic>; +@@ -84,35 +46,47 @@ + #size-cells = <0>; + + cpu0: cpu@0 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&L2>; ++ clocks = <&ccu 21>; ++ clock-names = "cpu"; ++ #cooling-cells = <2>; + }; + + cpu1: cpu@1 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + next-level-cache = <&L2>; ++ clocks = <&ccu 21>; ++ clock-names = "cpu"; ++ #cooling-cells = <2>; + }; + + cpu2: cpu@2 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + next-level-cache = <&L2>; ++ clocks = <&ccu 21>; ++ clock-names = "cpu"; ++ #cooling-cells = <2>; + }; + + cpu3: cpu@3 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + next-level-cache = <&L2>; ++ clocks = <&ccu 21>; ++ clock-names = "cpu"; ++ #cooling-cells = <2>; + }; + + L2: l2-cache { +@@ -139,15 +113,16 @@ + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; +- clock-output-names = "osc32k"; ++ clock-output-names = "ext-osc32k"; + }; + +- iosc: internal-osc-clk { +- #clock-cells = <0>; +- compatible = "fixed-clock"; +- clock-frequency = <16000000>; +- clock-accuracy = <300000000>; +- clock-output-names = "iosc"; ++ pmu { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { +@@ -155,6 +130,30 @@ + method = "smc"; + }; + ++ sound: sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "sun50i-a64-audio"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,frame-master = <&cpudai>; ++ simple-audio-card,bitclock-master = <&cpudai>; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,aux-devs = <&codec_analog>; ++ simple-audio-card,routing = ++ "Left DAC", "AIF1 Slot 0 Left", ++ "Right DAC", "AIF1 Slot 0 Right", ++ "AIF1 Slot 0 Left ADC", "Left ADC", ++ "AIF1 Slot 0 Right ADC", "Right ADC"; ++ status = "disabled"; ++ ++ cpudai: simple-audio-card,cpu { ++ sound-dai = <&dai>; ++ }; ++ ++ link_codec: simple-audio-card,codec { ++ sound-dai = <&codec>; ++ }; ++ }; ++ + sound_spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; +@@ -175,6 +174,7 @@ + + timer { + compatible = "arm,armv8-timer"; ++ allwinner,erratum-unknown1; + interrupts = , + ; + }; + ++ thermal-zones { ++ cpu_thermal: cpu0-thermal { ++ /* milliseconds */ ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 0>; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert0>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ map1 { ++ trip = <&cpu_alert1>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ ++ trips { ++ cpu_alert0: cpu_alert0 { ++ /* milliCelsius */ ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_alert1: cpu_alert1 { ++ /* milliCelsius */ ++ temperature = <90000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ ++ cpu_crit: cpu_crit { ++ /* milliCelsius */ ++ temperature = <110000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ gpu0_thermal: gpu0-thermal { ++ /* milliseconds */ ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 1>; ++ }; ++ ++ gpu1_thermal: gpu1-thermal { ++ /* milliseconds */ ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&ths 2>; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + +- de2@1000000 { ++ bus@1000000 { + compatible = "allwinner,sun50i-a64-de2"; + reg = <0x1000000 0x400000>; + allwinner,sram = <&de2_sram 1>; +@@ -202,10 +265,10 @@ + display_clocks: clock@0 { + compatible = "allwinner,sun50i-a64-de2-clk"; + reg = <0x0 0x100000>; +- clocks = <&ccu CLK_DE>, +- <&ccu CLK_BUS_DE>; +- clock-names = "mod", +- "bus"; ++ clocks = <&ccu CLK_BUS_DE>, ++ <&ccu CLK_DE>; ++ clock-names = "bus", ++ "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -225,11 +288,19 @@ + #size-cells = <0>; + + mixer0_out: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; + reg = <1>; + +- mixer0_out_tcon0: endpoint { ++ mixer0_out_tcon0: endpoint@0 { ++ reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; ++ ++ mixer0_out_tcon1: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&tcon1_in_mixer0>; ++ }; + }; + }; + }; +@@ -248,9 +319,17 @@ + #size-cells = <0>; + + mixer1_out: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; + reg = <1>; + +- mixer1_out_tcon1: endpoint { ++ mixer1_out_tcon0: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&tcon0_in_mixer1>; ++ }; ++ ++ mixer1_out_tcon1: endpoint@1 { ++ reg = <1>; + remote-endpoint = <&tcon1_in_mixer1>; + }; + }; +@@ -259,8 +338,7 @@ + }; + + syscon: syscon@1c00000 { +- compatible = "allwinner,sun50i-a64-system-control", +- "syscon"; ++ compatible = "allwinner,sun50i-a64-system-control"; + reg = <0x01c00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; +@@ -278,6 +356,20 @@ + reg = <0x0000 0x28000>; + }; + }; ++ ++ sram_c1: sram@1d00000 { ++ compatible = "mmio-sram"; ++ reg = <0x01d00000 0x40000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x01d00000 0x40000>; ++ ++ ve_sram: sram-section@0 { ++ compatible = "allwinner,sun50i-a64-sram-c1", ++ "allwinner,sun4i-a10-sram-c1"; ++ reg = <0x000000 0x40000>; ++ }; ++ }; + }; + + dma: dma-controller@1c02000 { +@@ -299,6 +391,7 @@ + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; ++ #clock-cells = <0>; + resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + +@@ -315,12 +408,23 @@ + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; ++ ++ tcon0_in_mixer1: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&mixer1_out_tcon0>; ++ }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; ++ ++ tcon0_out_dsi: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&dsi_in_tcon0>; ++ allwinner,tcon-channel = <1>; ++ }; + }; + }; + }; +@@ -340,9 +444,17 @@ + #size-cells = <0>; + + tcon1_in: port@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; + reg = <0>; + +- tcon1_in_mixer1: endpoint { ++ tcon1_in_mixer0: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&mixer0_out_tcon1>; ++ }; ++ ++ tcon1_in_mixer1: endpoint@1 { ++ reg = <1>; + remote-endpoint = <&mixer1_out_tcon1>; + }; + }; +@@ -360,6 +472,17 @@ + }; + }; + ++ video-codec@1c0e000 { ++ compatible = "allwinner,sun50i-a64-video-engine"; ++ reg = <0x01c0e000 0x1000>; ++ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, ++ <&ccu CLK_DRAM_VE>; ++ clock-names = "ahb", "mod", "ram"; ++ resets = <&ccu RST_BUS_VE>; ++ interrupts = ; ++ allwinner,sram = <&ve_sram 1>; ++ }; ++ + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun50i-a64-mmc"; + reg = <0x01c0f000 0x1000>; +@@ -405,6 +528,21 @@ + sid: eeprom@1c14000 { + compatible = "allwinner,sun50i-a64-sid"; + reg = <0x1c14000 0x400>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ ths_calibration: thermal-sensor-calibration@34 { ++ reg = <0x34 0x8>; ++ }; ++ }; ++ ++ crypto: crypto@1c15000 { ++ compatible = "allwinner,sun50i-a64-crypto"; ++ reg = <0x01c15000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_CE>; + }; + + usb_otg: usb@1c19000 { +@@ -417,6 +555,7 @@ + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; ++ dr_mode = "otg"; + status = "disabled"; + }; + +@@ -491,7 +630,7 @@ + ccu: clock@1c20000 { + compatible = "allwinner,sun50i-a64-ccu"; + reg = <0x01c20000 0x400>; +- clocks = <&osc24M>, <&osc32k>; ++ clocks = <&osc24M>, <&rtc 0>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -503,22 +642,45 @@ + interrupts = , + , + ; +- clocks = <&ccu 58>; ++ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; ++ clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + +- i2c0_pins: i2c0_pins { ++ csi_pins: csi-pins { ++ pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", ++ "PE7", "PE8", "PE9", "PE10", "PE11"; ++ function = "csi"; ++ }; ++ ++ /omit-if-no-ref/ ++ csi_mclk_pin: csi-mclk-pin { ++ pins = "PE1"; ++ function = "csi"; ++ }; ++ ++ i2c0_pins: i2c0-pins { + pins = "PH0", "PH1"; + function = "i2c0"; + }; + +- i2c1_pins: i2c1_pins { ++ i2c1_pins: i2c1-pins { + pins = "PH2", "PH3"; + function = "i2c1"; + }; + ++ /omit-if-no-ref/ ++ lcd_rgb666_pins: lcd-rgb666-pins { ++ pins = "PD0", "PD1", "PD2", "PD3", "PD4", ++ "PD5", "PD6", "PD7", "PD8", "PD9", ++ "PD10", "PD11", "PD12", "PD13", ++ "PD14", "PD15", "PD16", "PD17", ++ "PD18", "PD19", "PD20", "PD21"; ++ function = "lcd0"; ++ }; ++ + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; +@@ -551,19 +713,19 @@ + bias-pull-up; + }; + +- pwm_pin: pwm_pin { ++ pwm_pin: pwm-pin { + pins = "PD22"; + function = "pwm"; + }; + +- rmii_pins: rmii_pins { ++ rmii_pins: rmii-pins { + pins = "PD10", "PD11", "PD13", "PD14", "PD17", + "PD18", "PD19", "PD20", "PD22", "PD23"; + function = "emac"; + drive-strength = <40>; + }; + +- rgmii_pins: rgmii_pins { ++ rgmii_pins: rgmii-pins { + pins = "PD8", "PD9", "PD10", "PD11", "PD12", + "PD13", "PD15", "PD16", "PD17", "PD18", + "PD19", "PD20", "PD21", "PD22", "PD23"; +@@ -571,17 +733,17 @@ + drive-strength = <40>; + }; + +- spdif_tx_pin: spdif { ++ spdif_tx_pin: spdif-tx-pin { + pins = "PH8"; + function = "spdif"; + }; + +- spi0_pins: spi0 { ++ spi0_pins: spi0-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + +- spi1_pins: spi1 { ++ spi1_pins: spi1-pins { + pins = "PD0", "PD1", "PD2", "PD3"; + function = "spi1"; + }; +@@ -591,12 +753,12 @@ + function = "uart0"; + }; + +- uart1_pins: uart1_pins { ++ uart1_pins: uart1-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + +- uart1_rts_cts_pins: uart1_rts_cts_pins { ++ uart1_rts_cts_pins: uart1-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; +@@ -638,6 +800,14 @@ + status = "disabled"; + }; + ++ lradc: lradc@1c21800 { ++ compatible = "allwinner,sun50i-a64-lradc", ++ "allwinner,sun8i-a83t-r-lradc"; ++ reg = <0x01c21800 0x400>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-a64-i2s", +@@ -666,6 +836,41 @@ + status = "disabled"; + }; + ++ dai: dai@1c22c00 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun50i-a64-codec-i2s"; ++ reg = <0x01c22c00 0x200>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; ++ clock-names = "apb", "mod"; ++ resets = <&ccu RST_BUS_CODEC>; ++ dmas = <&dma 15>, <&dma 15>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ codec: codec@1c22e00 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun8i-a33-codec"; ++ reg = <0x01c22e00 0x600>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; ++ clock-names = "bus", "mod"; ++ status = "disabled"; ++ }; ++ ++ ths: thermal-sensor@1c25000 { ++ compatible = "allwinner,sun50i-a64-ths"; ++ reg = <0x01c25000 0x100>; ++ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; ++ clock-names = "bus", "mod"; ++ interrupts = ; ++ resets = <&ccu RST_BUS_THS>; ++ nvmem-cells = <&ths_calibration>; ++ nvmem-cell-names = "calibration"; ++ #thermal-sensor-cells = <1>; ++ }; ++ + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; +@@ -727,6 +932,8 @@ + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; +@@ -738,6 +945,8 @@ + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; +@@ -808,6 +1017,28 @@ + }; + }; + ++ mali: gpu@1c40000 { ++ compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; ++ reg = <0x01c40000 0x10000>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "gp", ++ "gpmmu", ++ "pp0", ++ "ppmmu0", ++ "pp1", ++ "ppmmu1", ++ "pmu"; ++ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; ++ clock-names = "bus", "core"; ++ resets = <&ccu RST_BUS_GPU>; ++ }; ++ + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, +@@ -830,6 +1061,51 @@ + status = "disabled"; + }; + ++ csi: csi@1cb0000 { ++ compatible = "allwinner,sun50i-a64-csi"; ++ reg = <0x01cb0000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_CSI>, ++ <&ccu CLK_CSI_SCLK>, ++ <&ccu CLK_DRAM_CSI>; ++ clock-names = "bus", "mod", "ram"; ++ resets = <&ccu RST_BUS_CSI>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&csi_pins>; ++ status = "disabled"; ++ }; ++ ++ dsi: dsi@1ca0000 { ++ compatible = "allwinner,sun50i-a64-mipi-dsi"; ++ reg = <0x01ca0000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_MIPI_DSI>; ++ resets = <&ccu RST_BUS_MIPI_DSI>; ++ phys = <&dphy>; ++ phy-names = "dphy"; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port { ++ dsi_in_tcon0: endpoint { ++ remote-endpoint = <&tcon0_out_dsi>; ++ }; ++ }; ++ }; ++ ++ dphy: d-phy@1ca1000 { ++ compatible = "allwinner,sun50i-a64-mipi-dphy", ++ "allwinner,sun6i-a31-mipi-dphy"; ++ reg = <0x01ca1000 0x1000>; ++ clocks = <&ccu CLK_BUS_MIPI_DSI>, ++ <&ccu CLK_DSI_DPHY>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_MIPI_DSI>; ++ status = "disabled"; ++ #phy-cells = <0>; ++ }; ++ + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun50i-a64-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; +@@ -842,7 +1118,7 @@ + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; +- phy-names = "hdmi-phy"; ++ phy-names = "phy"; + status = "disabled"; + + ports { +@@ -867,7 +1143,7 @@ + compatible = "allwinner,sun50i-a64-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, +- <&ccu 7>; ++ <&ccu CLK_PLL_VIDEO0>; + clock-names = "bus", "mod", "pll-0"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; +@@ -875,11 +1151,12 @@ + }; + + rtc: rtc@1f00000 { +- compatible = "allwinner,sun6i-a31-rtc"; +- reg = <0x01f00000 0x54>; ++ compatible = "allwinner,sun50i-a64-rtc", ++ "allwinner,sun8i-h3-rtc"; ++ reg = <0x01f00000 0x400>; + interrupts = , + ; +- clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; ++ clock-output-names = "osc32k", "osc32k-out", "iosc"; + clocks = <&osc32k>; + #clock-cells = <1>; + }; +@@ -896,13 +1173,19 @@ + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; +- clocks = <&osc24M>, <&osc32k>, <&iosc>, +- <&ccu 11>; ++ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, ++ <&ccu CLK_PLL_PERIPH0>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + ++ codec_analog: codec-analog@1f015c0 { ++ compatible = "allwinner,sun50i-a64-codec-analog"; ++ reg = <0x01f015c0 0x4>; ++ status = "disabled"; ++ }; ++ + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun50i-a64-i2c", + "allwinner,sun6i-a31-i2c"; +@@ -915,6 +1198,19 @@ + #size-cells = <0>; + }; + ++ r_ir: ir@1f02000 { ++ compatible = "allwinner,sun50i-a64-ir", ++ "allwinner,sun6i-a31-ir"; ++ reg = <0x01f02000 0x400>; ++ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; ++ clock-names = "apb", "ir"; ++ resets = <&r_ccu RST_APB0_IR>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; ++ status = "disabled"; ++ }; ++ + r_pwm: pwm@1f03800 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; +@@ -942,12 +1238,17 @@ + function = "s_i2c"; + }; + +- r_pwm_pin: pwm { ++ r_ir_rx_pin: r-ir-rx-pin { ++ pins = "PL11"; ++ function = "s_cir_rx"; ++ }; ++ ++ r_pwm_pin: r-pwm-pin { + pins = "PL10"; + function = "s_pwm"; + }; + +- r_rsb_pins: rsb { ++ r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + }; +@@ -972,6 +1273,7 @@ + "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; ++ clocks = <&osc24M>; + }; + }; + }; +-- +2.26.0 + +From fbe1642e24188e96f20ab5a3b003597288104e31 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 15:32:51 +0000 +Subject: [PATCH 2/9] arm: dts: AllWinner: sync axp803.dtsi to 5.6-rc1 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/axp803.dtsi | 82 ++++++++++++++++++++-------------------- + 1 file changed, 41 insertions(+), 41 deletions(-) + +diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi +index e5eae8bafc..10e9186a76 100644 +--- a/arch/arm/dts/axp803.dtsi ++++ b/arch/arm/dts/axp803.dtsi +@@ -1,44 +1,5 @@ +-/* +- * Copyright 2017 Icenowy Zheng +- * +- * This file is dual-licensed: you can use it either under the terms +- * of the GPL or the X11 license, at your option. Note that this dual +- * licensing only applies to this file, and not this project as a +- * whole. +- * +- * a) This file is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of the +- * License, or (at your option) any later version. +- * +- * This file is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * Or, alternatively, +- * +- * b) Permission is hereby granted, free of charge, to any person +- * obtaining a copy of this software and associated documentation +- * files (the "Software"), to deal in the Software without +- * restriction, including without limitation the rights to use, +- * copy, modify, merge, publish, distribute, sublicense, and/or +- * sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following +- * conditions: +- * +- * The above copyright notice and this permission notice shall be +- * included in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright 2017 Icenowy Zheng + + /* + * AXP803 Integrated Power Management Chip +@@ -49,6 +10,39 @@ + interrupt-controller; + #interrupt-cells = <1>; + ++ ac_power_supply: ac-power-supply { ++ compatible = "x-powers,axp803-ac-power-supply", ++ "x-powers,axp813-ac-power-supply"; ++ status = "disabled"; ++ }; ++ ++ axp_adc: adc { ++ compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; ++ #io-channel-cells = <1>; ++ }; ++ ++ axp_gpio: gpio { ++ compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ gpio0_ldo: gpio0-ldo { ++ pins = "GPIO0"; ++ function = "ldo"; ++ }; ++ ++ gpio1_ldo: gpio1-ldo { ++ pins = "GPIO1"; ++ function = "ldo"; ++ }; ++ }; ++ ++ battery_power_supply: battery-power-supply { ++ compatible = "x-powers,axp803-battery-power-supply", ++ "x-powers,axp813-battery-power-supply"; ++ status = "disabled"; ++ }; ++ + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <3000>; +@@ -152,4 +146,10 @@ + status = "disabled"; + }; + }; ++ ++ usb_power_supply: usb-power-supply { ++ compatible = "x-powers,axp803-usb-power-supply", ++ "x-powers,axp813-usb-power-supply"; ++ status = "disabled"; ++ }; + }; +-- +2.26.0 + +From f44987a0ccf064f9da4a119e7700605a3eb56447 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 15:34:58 +0000 +Subject: [PATCH 3/9] arm: dts: AllWinner: sync sun50i-a64.dtsi to 5.7-rc1 + +Adds the following two patches queued for 5.7: +- arm64: dts: sun50i-a64: Add i2c2 pins +- arm64: dts: allwinner: a64: Add MBUS controller node + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/sun50i-a64.dtsi | 16 +++++++++++++++- + 1 file changed, 15 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi +index 862b47dc9d..89a60fcf5a 100644 +--- a/arch/arm/dts/sun50i-a64.dtsi ++++ b/arch/arm/dts/sun50i-a64.dtsi +@@ -671,6 +671,11 @@ + function = "i2c1"; + }; + ++ i2c2_pins: i2c2-pins { ++ pins = "PE14", "PE15"; ++ function = "i2c2"; ++ }; ++ + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", +@@ -958,12 +963,13 @@ + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + +- + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; +@@ -1061,6 +1067,14 @@ + status = "disabled"; + }; + ++ mbus: dram-controller@1c62000 { ++ compatible = "allwinner,sun50i-a64-mbus"; ++ reg = <0x01c62000 0x1000>; ++ clocks = <&ccu 112>; ++ dma-ranges = <0x00000000 0x40000000 0xc0000000>; ++ #interconnect-cells = <1>; ++ }; ++ + csi: csi@1cb0000 { + compatible = "allwinner,sun50i-a64-csi"; + reg = <0x01cb0000 0x1000>; +-- +2.26.0 + +From 465dbf297edb9881e79c1b81fef8d9328fbaf7ad Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 15:37:39 +0000 +Subject: [PATCH 4/9] arm: dts: allwinner: Add initial support for Pine64 + PinePhone + +The initial DT for the PinePhone models are queued for 5.7-rc1: +- 1.0: Early Developer Batch +- 1.1: Braveheart Batch + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/Makefile | 2 + + arch/arm/dts/sun50i-a64-pinephone-1.0.dts | 11 + + arch/arm/dts/sun50i-a64-pinephone-1.1.dts | 11 + + arch/arm/dts/sun50i-a64-pinephone.dtsi | 379 ++++++++++++++++++++++ + 4 files changed, 403 insertions(+) + create mode 100644 arch/arm/dts/sun50i-a64-pinephone-1.0.dts + create mode 100644 arch/arm/dts/sun50i-a64-pinephone-1.1.dts + create mode 100644 arch/arm/dts/sun50i-a64-pinephone.dtsi + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 820ee9733a..fb7516ee83 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -573,6 +573,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ + sun50i-a64-pine64-plus.dtb \ + sun50i-a64-pine64.dtb \ + sun50i-a64-pinebook.dtb \ ++ sun50i-a64-pinephone-1.0.dtb \ ++ sun50i-a64-pinephone-1.1.dtb \ + sun50i-a64-sopine-baseboard.dtb \ + sun50i-a64-teres-i.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ +diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts +new file mode 100644 +index 0000000000..0c42272106 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2020 Ondrej Jirman ++ ++/dts-v1/; ++ ++#include "sun50i-a64-pinephone.dtsi" ++ ++/ { ++ model = "Pine64 PinePhone Developer Batch (1.0)"; ++ compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64"; ++}; +diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts +new file mode 100644 +index 0000000000..06a775c416 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2020 Ondrej Jirman ++ ++/dts-v1/; ++ ++#include "sun50i-a64-pinephone.dtsi" ++ ++/ { ++ model = "Pine64 PinePhone Braveheart (1.1)"; ++ compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64"; ++}; +diff --git a/arch/arm/dts/sun50i-a64-pinephone.dtsi b/arch/arm/dts/sun50i-a64-pinephone.dtsi +new file mode 100644 +index 0000000000..cefda145c3 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pinephone.dtsi +@@ -0,0 +1,379 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2019 Icenowy Zheng ++// Copyright (C) 2020 Martijn Braam ++// Copyright (C) 2020 Ondrej Jirman ++ ++#include "sun50i-a64.dtsi" ++#include "sun50i-a64-cpu-opp.dtsi" ++ ++#include ++#include ++#include ++#include ++ ++/ { ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ blue { ++ function = LED_FUNCTION_INDICATOR; ++ color = ; ++ gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ ++ }; ++ ++ green { ++ function = LED_FUNCTION_INDICATOR; ++ color = ; ++ gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ ++ }; ++ ++ red { ++ function = LED_FUNCTION_INDICATOR; ++ color = ; ++ gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ ++ }; ++ }; ++ ++ speaker_amp: audio-amplifier { ++ compatible = "simple-audio-amplifier"; ++ enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ ++ sound-name-prefix = "Speaker Amp"; ++ }; ++ ++ vibrator { ++ compatible = "gpio-vibrator"; ++ enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ ++ vcc-supply = <®_dcdc1>; ++ }; ++}; ++ ++&codec { ++ status = "okay"; ++}; ++ ++&codec_analog { ++ cpvdd-supply = <®_eldo1>; ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu2 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu3 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&dai { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ /* Magnetometer */ ++ lis3mdl@1e { ++ compatible = "st,lis3mdl-magn"; ++ reg = <0x1e>; ++ vdd-supply = <®_dldo1>; ++ vddio-supply = <®_dldo1>; ++ }; ++ ++ /* Accelerometer/gyroscope */ ++ mpu6050@68 { ++ compatible = "invensense,mpu6050"; ++ reg = <0x68>; ++ interrupt-parent = <&pio>; ++ interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */ ++ vdd-supply = <®_dldo1>; ++ vddio-supply = <®_dldo1>; ++ }; ++}; ++ ++/* Connected to pogo pins (external spring based pinheader for user addons) */ ++&i2c2 { ++ status = "okay"; ++}; ++ ++&lradc { ++ vref-supply = <®_aldo3>; ++ status = "okay"; ++ ++ button-200 { ++ label = "Volume Up"; ++ linux,code = ; ++ channel = <0>; ++ voltage = <200000>; ++ }; ++ ++ button-400 { ++ label = "Volume Down"; ++ linux,code = ; ++ channel = <0>; ++ voltage = <400000>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_dcdc1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&pio { ++ vcc-pb-supply = <®_dcdc1>; ++ vcc-pc-supply = <®_dcdc1>; ++ vcc-pd-supply = <®_dcdc1>; ++ vcc-pe-supply = <®_aldo1>; ++ vcc-pf-supply = <®_dcdc1>; ++ vcc-pg-supply = <®_dldo4>; ++ vcc-ph-supply = <®_dcdc1>; ++}; ++ ++&r_pio { ++ /* ++ * FIXME: We can't add that supply for now since it would ++ * create a circular dependency between pinctrl, the regulator ++ * and the RSB Bus. ++ * ++ * vcc-pl-supply = <®_aldo2>; ++ */ ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++&ac_power_supply { ++ status = "okay"; ++}; ++ ++&battery_power_supply { ++ status = "okay"; ++}; ++ ++®_aldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "dovdd-csi"; ++}; ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-dsi-sensor"; ++}; ++ ++®_dldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-mipi-io"; ++}; ++ ++®_dldo3 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "avdd-csi"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi-io"; ++}; ++ ++®_eldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-lpddr"; ++}; ++ ++®_eldo3 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "dvdd-1v8-csi"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_ldo_io0 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-lcd-ctp-stk"; ++ status = "okay"; ++}; ++ ++®_ldo_io1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc-1v8-typec"; ++ status = "okay"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&sound { ++ status = "okay"; ++ simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; ++ simple-audio-card,widgets = "Microphone", "Headset Microphone", ++ "Microphone", "Internal Microphone", ++ "Headphone", "Headphone Jack", ++ "Speaker", "Internal Earpiece", ++ "Speaker", "Internal Speaker"; ++ simple-audio-card,routing = ++ "Headphone Jack", "HP", ++ "Internal Earpiece", "EARPIECE", ++ "Internal Speaker", "Speaker Amp OUTL", ++ "Internal Speaker", "Speaker Amp OUTR", ++ "Speaker Amp INL", "LINEOUT", ++ "Speaker Amp INR", "LINEOUT", ++ "Left DAC", "AIF1 Slot 0 Left", ++ "Right DAC", "AIF1 Slot 0 Right", ++ "AIF1 Slot 0 Left ADC", "Left ADC", ++ "AIF1 Slot 0 Right ADC", "Right ADC", ++ "Internal Microphone", "MBIAS", ++ "MIC1", "Internal Microphone", ++ "Headset Microphone", "HBIAS", ++ "MIC2", "Headset Microphone"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pb_pins>; ++ status = "okay"; ++}; ++ ++/* Connected to the modem (hardware flow control can't be used) */ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usb_power_supply { ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; +-- +2.26.0 + +From e8fd62cbf02828da817628d15111e6e974144473 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 15:46:43 +0000 +Subject: [PATCH 5/9] sync sun50i-a64 clocks with linux 5.6 + +Signed-off-by: Peter Robinson +--- + include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h +index d66432c6e6..e512a1c9b0 100644 +--- a/include/dt-bindings/clock/sun50i-a64-ccu.h ++++ b/include/dt-bindings/clock/sun50i-a64-ccu.h +@@ -43,8 +43,10 @@ + #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ + #define _DT_BINDINGS_CLK_SUN50I_A64_H_ + ++#define CLK_PLL_VIDEO0 7 + #define CLK_PLL_PERIPH0 11 + ++#define CLK_CPUX 21 + #define CLK_BUS_MIPI_DSI 28 + #define CLK_BUS_CE 29 + #define CLK_BUS_DMA 30 +-- +2.26.0 + +From a07a9d6cb77ea0bc21cd64922bb428faf5b7e121 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 10 Mar 2020 15:49:11 +0000 +Subject: [PATCH 6/9] add upstream sun50i-a64-cpu-opp.dtsi added in 5.6 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 75 ++++++++++++++++++++++++++++ + 1 file changed, 75 insertions(+) + create mode 100644 arch/arm/dts/sun50i-a64-cpu-opp.dtsi + +diff --git a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi +new file mode 100644 +index 0000000000..578c37490d +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi +@@ -0,0 +1,75 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2020 Vasily khoruzhick ++ */ ++ ++/ { ++ cpu0_opp_table: opp_table0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-648000000 { ++ opp-hz = /bits/ 64 <648000000>; ++ opp-microvolt = <1040000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-912000000 { ++ opp-hz = /bits/ 64 <912000000>; ++ opp-microvolt = <1120000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-960000000 { ++ opp-hz = /bits/ 64 <960000000>; ++ opp-microvolt = <1160000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <1200000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1056000000 { ++ opp-hz = /bits/ 64 <1056000000>; ++ opp-microvolt = <1240000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <1260000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ ++ opp-1152000000 { ++ opp-hz = /bits/ 64 <1152000000>; ++ opp-microvolt = <1300000>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ }; ++ }; ++}; ++ ++&cpu0 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; ++ ++&cpu1 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; ++ ++&cpu2 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; ++ ++&cpu3 { ++ operating-points-v2 = <&cpu0_opp_table>; ++}; +-- +2.26.0 + +From 493869ec73e6ba999b6f7c49369e966ebfb8ef0b Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 14 Apr 2020 09:50:11 +0100 +Subject: [PATCH 7/9] Initial Pinephone support + +Signed-off-by: Peter Robinson +--- + configs/pinephone_defconfig | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + create mode 100644 configs/pinephone_defconfig + +diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig +new file mode 100644 +index 0000000000..a7d1e610d4 +--- /dev/null ++++ b/configs/pinephone_defconfig +@@ -0,0 +1,26 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN50I=y ++CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y ++CONFIG_DRAM_CLK=552 ++CONFIG_DRAM_ZQ=3881949 ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_R_I2C_ENABLE=y ++CONFIG_SPL_SPI_SUNXI=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_USE_PREBOOT=y ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.1" ++CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.0" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_SUNXI=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +-- +2.26.0 + +From 163b30d9cd1c0cf77107e0330567bbda063410da Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 14 Apr 2020 09:51:44 +0100 +Subject: [PATCH 8/9] Initial PineTab dts from linux 5.7-rc1 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/sun50i-a64-pinetab.dts | 460 ++++++++++++++++++++++++++++ + 2 files changed, 461 insertions(+) + create mode 100644 arch/arm/dts/sun50i-a64-pinetab.dts + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index fb7516ee83..50c1d48e84 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -575,6 +575,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \ + sun50i-a64-pinebook.dtb \ + sun50i-a64-pinephone-1.0.dtb \ + sun50i-a64-pinephone-1.1.dtb \ ++ sun50i-a64-pinetab.dtb \ + sun50i-a64-sopine-baseboard.dtb \ + sun50i-a64-teres-i.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ +diff --git a/arch/arm/dts/sun50i-a64-pinetab.dts b/arch/arm/dts/sun50i-a64-pinetab.dts +new file mode 100644 +index 0000000000..316e8a4439 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pinetab.dts +@@ -0,0 +1,460 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2019 Icenowy Zheng ++ * ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64.dtsi" ++#include "sun50i-a64-cpu-opp.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "PineTab"; ++ compatible = "pine64,pinetab", "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = &rtl8723cs; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; ++ brightness-levels = <0 16 18 20 22 24 26 29 32 35 38 42 46 51 56 62 68 75 83 91 100>; ++ default-brightness-level = <15>; ++ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ ++ power-supply = <&vdd_bl>; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ i2c-csi { ++ compatible = "i2c-gpio"; ++ sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */ ++ scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */ ++ i2c-gpio,delay-us = <5>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* Rear camera */ ++ ov5640: camera@3c { ++ compatible = "ovti,ov5640"; ++ reg = <0x3c>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&csi_mclk_pin>; ++ clocks = <&ccu CLK_CSI_MCLK>; ++ clock-names = "xclk"; ++ ++ AVDD-supply = <®_dldo3>; ++ DOVDD-supply = <®_aldo1>; ++ DVDD-supply = <®_eldo3>; ++ reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */ ++ powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ ++ ++ port { ++ ov5640_ep: endpoint { ++ remote-endpoint = <&csi_ep>; ++ bus-width = <8>; ++ hsync-active = <1>; /* Active high */ ++ vsync-active = <0>; /* Active low */ ++ data-active = <1>; /* Active high */ ++ pclk-sample = <1>; /* Rising */ ++ }; ++ }; ++ }; ++ }; ++ ++ speaker_amp: audio-amplifier { ++ compatible = "simple-audio-amplifier"; ++ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ ++ sound-name-prefix = "Speaker Amp"; ++ }; ++ ++ vdd_bl: regulator@0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "bl-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ ++ enable-active-high; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ ++ post-power-on-delay-ms = <200>; ++ }; ++}; ++ ++&codec { ++ status = "okay"; ++}; ++ ++&codec_analog { ++ hpvcc-supply = <®_eldo1>; ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu1 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu2 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&cpu3 { ++ cpu-supply = <®_dcdc2>; ++}; ++ ++&csi { ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ csi_ep: endpoint { ++ remote-endpoint = <&ov5640_ep>; ++ bus-width = <8>; ++ hsync-active = <1>; /* Active high */ ++ vsync-active = <0>; /* Active low */ ++ data-active = <1>; /* Active high */ ++ pclk-sample = <1>; /* Rising */ ++ }; ++ }; ++}; ++ ++&dai { ++ status = "okay"; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&dphy { ++ status = "okay"; ++}; ++ ++&dsi { ++ vcc-dsi-supply = <®_dldo1>; ++ status = "okay"; ++ ++ panel@0 { ++ compatible = "feixin,k101-im2ba02"; ++ reg = <0>; ++ avdd-supply = <®_dc1sw>; ++ dvdd-supply = <®_dc1sw>; ++ cvdd-supply = <®_ldo_io1>; ++ reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ ++ backlight = <&backlight>; ++ }; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ touchscreen@5d { ++ compatible = "goodix,gt9271"; ++ reg = <0x5d>; ++ interrupt-parent = <&pio>; ++ interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */ ++ irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ ++ reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ ++ AVDD28-supply = <®_ldo_io1>; ++ }; ++}; ++ ++&i2c0_pins { ++ bias-pull-up; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ /* TODO: add Bochs BMA223 accelerometer here */ ++}; ++ ++&lradc { ++ vref-supply = <®_aldo3>; ++ status = "okay"; ++ ++ button-200 { ++ label = "Volume Up"; ++ linux,code = ; ++ channel = <0>; ++ voltage = <200000>; ++ }; ++ ++ button-400 { ++ label = "Volume Down"; ++ linux,code = ; ++ channel = <0>; ++ voltage = <400000>; ++ }; ++}; ++ ++&mixer1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_dldo4>; ++ vqmmc-supply = <®_eldo1>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ rtl8723cs: wifi@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_dcdc1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&pwm { ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ x-powers,drive-vbus-en; ++ }; ++}; ++ ++#include "axp803.dtsi" ++ ++&ac_power_supply { ++ status = "okay"; ++}; ++ ++&battery_power_supply { ++ status = "okay"; ++}; ++ ++®_aldo1 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "dovdd-csi"; ++}; ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dc1sw { ++ regulator-name = "vcc-lcd"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi-dsi-sensor"; ++}; ++ ++®_dldo3 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "avdd-csi"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi"; ++}; ++ ++®_drivevbus { ++ regulator-name = "usb0-vbus"; ++ status = "okay"; ++}; ++ ++®_eldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "cpvdd"; ++}; ++ ++®_eldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca-1v8"; ++}; ++ ++®_eldo3 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "dvdd-1v8-csi"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_ldo_io0 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-usb"; ++ status = "okay"; ++}; ++ ++®_ldo_io1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <3500000>; ++ regulator-name = "vcc-touchscreen"; ++ status = "okay"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&sound { ++ status = "okay"; ++ simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; ++ simple-audio-card,widgets = "Microphone", "Internal Microphone Left", ++ "Microphone", "Internal Microphone Right", ++ "Headphone", "Headphone Jack", ++ "Speaker", "Internal Speaker"; ++ simple-audio-card,routing = ++ "Left DAC", "AIF1 Slot 0 Left", ++ "Right DAC", "AIF1 Slot 0 Right", ++ "Speaker Amp INL", "LINEOUT", ++ "Speaker Amp INR", "LINEOUT", ++ "Internal Speaker", "Speaker Amp OUTL", ++ "Internal Speaker", "Speaker Amp OUTR", ++ "Headphone Jack", "HP", ++ "AIF1 Slot 0 Left ADC", "Left ADC", ++ "AIF1 Slot 0 Right ADC", "Right ADC", ++ "Internal Microphone Left", "MBIAS", ++ "MIC1", "Internal Microphone Left", ++ "Internal Microphone Right", "HBIAS", ++ "MIC2", "Internal Microphone Right"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pb_pins>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usb_power_supply { ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ ++ usb0_vbus_power-supply = <&usb_power_supply>; ++ usb0_vbus-supply = <®_drivevbus>; ++ usb1_vbus-supply = <®_ldo_io0>; ++ status = "okay"; ++}; +-- +2.26.0 + +From 6bf15552c2b6becb48ce7732120e0ddb2078cb1a Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 14 Apr 2020 09:53:07 +0100 +Subject: [PATCH 9/9] initial pinetab support + +Signed-off-by: Peter Robinson +--- + configs/pinetab_defconfig | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + create mode 100644 configs/pinetab_defconfig + +diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig +new file mode 100644 +index 0000000000..5b9620f3e5 +--- /dev/null ++++ b/configs/pinetab_defconfig +@@ -0,0 +1,26 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN50I=y ++CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y ++CONFIG_DRAM_CLK=552 ++CONFIG_DRAM_ZQ=3881949 ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_R_I2C_ENABLE=y ++CONFIG_SPL_SPI_SUNXI=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_USE_PREBOOT=y ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinetab" ++CONFIG_OF_LIST="sun50i-a64-pinetab" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_SUNXI=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +-- +2.26.0 diff --git a/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch b/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch new file mode 100644 index 0000000000000000000000000000000000000000..720b1bacbba27502772b2bf0180ae02a72db3ac6 --- /dev/null +++ b/USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch @@ -0,0 +1,993 @@ +From 47d0df70fbe5997770090aca05b07d774a19a722 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 10 Jun 2020 13:15:45 +0100 +Subject: [PATCH] USB host support for Raspberry Pi 4 board (64-bit) + +Signed-off-by: Peter Robinson +--- + arch/arm/mach-bcm283x/init.c | 20 +- + configs/rpi_4_defconfig | 9 + + configs/rpi_arm64_defconfig | 8 +- + drivers/pci/Kconfig | 9 + + drivers/pci/Makefile | 1 + + drivers/pci/pci-rcar-gen3.c | 8 - + drivers/pci/pcie_brcmstb.c | 623 ++++++++++++++++++++++++++++++++++ + drivers/pci/pcie_intel_fpga.c | 3 - + drivers/usb/host/xhci-mem.c | 3 + + include/linux/bitfield.h | 52 +++ + include/pci.h | 22 +- + include/usb/xhci.h | 8 - + 12 files changed, 740 insertions(+), 26 deletions(-) + create mode 100644 drivers/pci/pcie_brcmstb.c + +diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c +index f4d00d892d..cf4c5b245d 100644 +--- a/arch/arm/mach-bcm283x/init.c ++++ b/arch/arm/mach-bcm283x/init.c +@@ -12,10 +12,15 @@ + #include + #include + ++#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL ++#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL ++ + #ifdef CONFIG_ARM64 + #include + +-static struct mm_region bcm283x_mem_map[] = { ++#define MEM_MAP_MAX_ENTRIES (4) ++ ++static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, +@@ -35,11 +40,11 @@ static struct mm_region bcm283x_mem_map[] = { + } + }; + +-static struct mm_region bcm2711_mem_map[] = { ++static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, +- .size = 0xfe000000UL, ++ .size = 0xfc000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { +@@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = { + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN ++ }, { ++ .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, ++ .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, ++ .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, ++ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | ++ PTE_BLOCK_NON_SHARE | ++ PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, +@@ -72,7 +84,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) + { + int i; + +- for (i = 0; i < 2; i++) { ++ for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) { + mem_map[i].virt = pd[i].virt; + mem_map[i].phys = pd[i].phys; + mem_map[i].size = pd[i].size; +diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig +index f0301dc8bc..b42efe6072 100644 +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_ENV_SIZE=0x4000 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start;" + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set +@@ -13,6 +15,8 @@ CONFIG_SYS_PROMPT="U-Boot> " + CONFIG_CMD_DFU=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_BOARD=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +@@ -26,12 +30,17 @@ CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set + CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_DM_USB_GADGET=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_PCI=y + CONFIG_USB_GADGET=y + CONFIG_USB_GADGET_MANUFACTURER="FSL" + CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index d16c2388af..0feea7f0be 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -7,13 +7,14 @@ CONFIG_ENV_SIZE=0x4000 + CONFIG_DISTRO_DEFAULTS=y + CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="usb start" ++CONFIG_PREBOOT="pci enum; usb start;" + CONFIG_MISC_INIT_R=y + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set + CONFIG_SYS_PROMPT="U-Boot> " + CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y + CONFIG_OF_BOARD=y +@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_DM_ETH=y + CONFIG_BCMGENET=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set + CONFIG_USB=y + CONFIG_DM_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_PCI=y + CONFIG_USB_DWC2=y + CONFIG_USB_KEYBOARD=y + CONFIG_USB_HOST_ETHER=y +diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig +index 6d8c22aacf..7e1e51d9ea 100644 +--- a/drivers/pci/Kconfig ++++ b/drivers/pci/Kconfig +@@ -205,4 +205,13 @@ config PCIE_ROCKCHIP + Say Y here if you want to enable PCIe controller support on + Rockchip SoCs. + ++config PCI_BRCMSTB ++ bool "Broadcom STB PCIe controller" ++ depends on DM_PCI ++ depends on ARCH_BCM283X ++ help ++ Say Y here if you want to enable support for PCIe controller ++ on Broadcom set-top-box (STB) SoCs. ++ This driver currently supports only BCM2711 SoC and RC mode ++ of the controller. + endif +diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile +index 955351c5c2..3e1ff417d7 100644 +--- a/drivers/pci/Makefile ++++ b/drivers/pci/Makefile +@@ -43,4 +43,5 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o + obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o + obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o + obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o ++obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o + obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o +diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c +index df7b37a592..1f51854ccc 100644 +--- a/drivers/pci/pci-rcar-gen3.c ++++ b/drivers/pci/pci-rcar-gen3.c +@@ -118,14 +118,6 @@ + #define RCAR_PCI_MAX_RESOURCES 4 + #define MAX_NR_INBOUND_MAPS 6 + +-#define PCI_EXP_FLAGS 2 /* Capabilities register */ +-#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +-#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +-#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +-#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ +-#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +-#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +- + enum { + RCAR_PCI_ACCESS_READ, + RCAR_PCI_ACCESS_WRITE, +diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c +new file mode 100644 +index 0000000000..dade79e9c8 +--- /dev/null ++++ b/drivers/pci/pcie_brcmstb.c +@@ -0,0 +1,623 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Broadcom STB PCIe controller driver ++ * ++ * Copyright (C) 2020 Samsung Electronics Co., Ltd. ++ * ++ * Based on upstream Linux kernel driver: ++ * drivers/pci/controller/pcie-brcmstb.c ++ * Copyright (C) 2009 - 2017 Broadcom ++ * ++ * Based driver by Nicolas Saenz Julienne ++ * Copyright (C) 2020 Nicolas Saenz Julienne ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Offset of the mandatory PCIe capability config registers */ ++#define BRCM_PCIE_CAP_REGS 0x00ac ++ ++/* The PCIe controller register offsets */ ++#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188 ++#define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc ++#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0 ++ ++#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c ++#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff ++ ++#define PCIE_RC_DL_MDIO_ADDR 0x1100 ++#define PCIE_RC_DL_MDIO_WR_DATA 0x1104 ++#define PCIE_RC_DL_MDIO_RD_DATA 0x1108 ++ ++#define PCIE_MISC_MISC_CTRL 0x4008 ++#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 ++#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 ++#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 ++#define MISC_CTRL_MAX_BURST_SIZE_128 0x0 ++#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c ++#define PCIE_MEM_WIN0_LO(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 ++#define PCIE_MEM_WIN0_HI(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) ++ ++#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c ++#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f ++ ++#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 ++#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f ++#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 ++ ++#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c ++#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f ++ ++#define PCIE_MISC_PCIE_STATUS 0x4068 ++#define STATUS_PCIE_PORT_MASK 0x80 ++#define STATUS_PCIE_PORT_SHIFT 7 ++#define STATUS_PCIE_DL_ACTIVE_MASK 0x20 ++#define STATUS_PCIE_DL_ACTIVE_SHIFT 5 ++#define STATUS_PCIE_PHYLINKUP_MASK 0x10 ++#define STATUS_PCIE_PHYLINKUP_SHIFT 4 ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 ++#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 ++#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 ++#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12 ++#define PCIE_MEM_WIN0_BASE_LIMIT(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 ++#define MEM_WIN0_BASE_HI_BASE_MASK 0xff ++#define PCIE_MEM_WIN0_BASE_HI(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) ++ ++#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 ++#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff ++#define PCIE_MEM_WIN0_LIMIT_HI(win) \ ++ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) ++ ++#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 ++#define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 ++#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 ++ ++#define PCIE_MSI_INTR2_CLR 0x4508 ++#define PCIE_MSI_INTR2_MASK_SET 0x4510 ++ ++#define PCIE_EXT_CFG_DATA 0x8000 ++ ++#define PCIE_EXT_CFG_INDEX 0x9000 ++#define PCIE_EXT_BUSNUM_SHIFT 20 ++#define PCIE_EXT_SLOT_SHIFT 15 ++#define PCIE_EXT_FUNC_SHIFT 12 ++ ++#define PCIE_RGR1_SW_INIT_1 0x9210 ++#define RGR1_SW_INIT_1_PERST_MASK 0x1 ++#define RGR1_SW_INIT_1_INIT_MASK 0x2 ++ ++/* PCIe parameters */ ++#define BRCM_NUM_PCIE_OUT_WINS 4 ++ ++/* MDIO registers */ ++#define MDIO_PORT0 0x0 ++#define MDIO_DATA_MASK 0x7fffffff ++#define MDIO_DATA_SHIFT 0 ++#define MDIO_PORT_MASK 0xf0000 ++#define MDIO_PORT_SHIFT 16 ++#define MDIO_REGAD_MASK 0xffff ++#define MDIO_REGAD_SHIFT 0 ++#define MDIO_CMD_MASK 0xfff00000 ++#define MDIO_CMD_SHIFT 20 ++#define MDIO_CMD_READ 0x1 ++#define MDIO_CMD_WRITE 0x0 ++#define MDIO_DATA_DONE_MASK 0x80000000 ++#define SSC_REGS_ADDR 0x1100 ++#define SET_ADDR_OFFSET 0x1f ++#define SSC_CNTL_OFFSET 0x2 ++#define SSC_CNTL_OVRD_EN_MASK 0x8000 ++#define SSC_CNTL_OVRD_VAL_MASK 0x4000 ++#define SSC_STATUS_OFFSET 0x1 ++#define SSC_STATUS_SSC_MASK 0x400 ++#define SSC_STATUS_SSC_SHIFT 10 ++#define SSC_STATUS_PLL_LOCK_MASK 0x800 ++#define SSC_STATUS_PLL_LOCK_SHIFT 11 ++ ++/** ++ * struct brcm_pcie - the PCIe controller state ++ * @base: Base address of memory mapped IO registers of the controller ++ * @gen: Non-zero value indicates limitation of the PCIe controller operation ++ * to a specific generation (1, 2 or 3) ++ * @ssc: true indicates active Spread Spectrum Clocking operation ++ */ ++struct brcm_pcie { ++ void __iomem *base; ++ ++ int gen; ++ bool ssc; ++}; ++ ++/** ++ * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size ++ * @size: The inbound region size ++ * ++ * This function converts size of the inbound "BAR" region to the non-linear ++ * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field. ++ * ++ * Return: The encoded inbound region size ++ */ ++static int brcm_pcie_encode_ibar_size(u64 size) ++{ ++ int log2_in = ilog2(size); ++ ++ if (log2_in >= 12 && log2_in <= 15) ++ /* Covers 4KB to 32KB (inclusive) */ ++ return (log2_in - 12) + 0x1c; ++ else if (log2_in >= 16 && log2_in <= 37) ++ /* Covers 64KB to 32GB, (inclusive) */ ++ return log2_in - 15; ++ ++ /* Something is awry so disable */ ++ return 0; ++} ++ ++/** ++ * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode ++ * @pcie: Pointer to the PCIe controller state ++ * ++ * The controller is capable of serving in both RC and EP roles. ++ * ++ * Return: true for RC mode, false for EP mode. ++ */ ++static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) ++{ ++ u32 val; ++ ++ val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); ++ ++ return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT; ++} ++ ++/** ++ * brcm_pcie_link_up() - Check whether the PCIe link is up ++ * @pcie: Pointer to the PCIe controller state ++ * ++ * Return: true if the link is up, false otherwise. ++ */ ++static bool brcm_pcie_link_up(struct brcm_pcie *pcie) ++{ ++ u32 val, dla, plu; ++ ++ val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); ++ dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT; ++ plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT; ++ ++ return dla && plu; ++} ++ ++static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf, ++ uint offset, void **paddress) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ unsigned int pci_bus = PCI_BUS(bdf); ++ unsigned int pci_dev = PCI_DEV(bdf); ++ unsigned int pci_func = PCI_FUNC(bdf); ++ int idx; ++ ++ /* ++ * Busses 0 (host PCIe bridge) and 1 (its immediate child) ++ * are limited to a single device each ++ */ ++ if (pci_bus < 2 && pci_dev > 0) ++ return -EINVAL; ++ ++ /* Accesses to the RC go right to the RC registers */ ++ if (pci_bus == 0) { ++ *paddress = pcie->base + offset; ++ return 0; ++ } ++ ++ /* For devices, write to the config space index register */ ++ idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT) ++ | (pci_dev << PCIE_EXT_SLOT_SHIFT) ++ | (pci_func << PCIE_EXT_FUNC_SHIFT); ++ ++ writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); ++ *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; ++ ++ return 0; ++} ++ ++static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, ++ uint offset, ulong *valuep, ++ enum pci_size_t size) ++{ ++ return pci_generic_mmap_read_config(bus, brcm_pcie_config_address, ++ bdf, offset, valuep, size); ++} ++ ++static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf, ++ uint offset, ulong value, ++ enum pci_size_t size) ++{ ++ return pci_generic_mmap_write_config(bus, brcm_pcie_config_address, ++ bdf, offset, value, size); ++} ++ ++static const char *link_speed_to_str(unsigned int cls) ++{ ++ switch (cls) { ++ case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5"; ++ case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0"; ++ case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0"; ++ default: ++ break; ++ } ++ ++ return "??"; ++} ++ ++static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad, ++ unsigned int cmd) ++{ ++ u32 pkt; ++ ++ pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK; ++ pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK; ++ pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK; ++ ++ return pkt; ++} ++ ++/** ++ * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus ++ * @base: Pointer to the PCIe controller IO registers ++ * @port: The MDIO port number ++ * @regad: The register address ++ * @val: A pointer at which to store the read value ++ * ++ * Return: 0 on success and register value in @val, negative error value ++ * on failure. ++ */ ++static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port, ++ unsigned int regad, u32 *val) ++{ ++ u32 data, addr; ++ int ret; ++ ++ addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ); ++ writel(addr, base + PCIE_RC_DL_MDIO_ADDR); ++ readl(base + PCIE_RC_DL_MDIO_ADDR); ++ ++ ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data, ++ (data & MDIO_DATA_DONE_MASK), 100); ++ ++ *val = data & MDIO_DATA_MASK; ++ ++ return ret; ++} ++ ++/** ++ * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus ++ * @base: Pointer to the PCIe controller IO registers ++ * @port: The MDIO port number ++ * @regad: Address of the register ++ * @wrdata: The value to write ++ * ++ * Return: 0 on success, negative error value on failure. ++ */ ++static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port, ++ unsigned int regad, u16 wrdata) ++{ ++ u32 data, addr; ++ ++ addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE); ++ writel(addr, base + PCIE_RC_DL_MDIO_ADDR); ++ readl(base + PCIE_RC_DL_MDIO_ADDR); ++ writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); ++ ++ return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data, ++ !(data & MDIO_DATA_DONE_MASK), 100); ++} ++ ++/** ++ * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking ++ * @base: pointer to the PCIe controller IO registers ++ * ++ * Return: 0 on success, negative error value on failure. ++ */ ++static int brcm_pcie_set_ssc(void __iomem *base) ++{ ++ int pll, ssc; ++ int ret; ++ u32 tmp; ++ ++ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, ++ SSC_REGS_ADDR); ++ if (ret < 0) ++ return ret; ++ ++ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); ++ if (ret < 0) ++ return ret; ++ ++ tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK); ++ ++ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); ++ if (ret < 0) ++ return ret; ++ ++ udelay(1000); ++ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); ++ if (ret < 0) ++ return ret; ++ ++ ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT; ++ pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT; ++ ++ return ssc && pll ? 0 : -EIO; ++} ++ ++/** ++ * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3) ++ * @pcie: pointer to the PCIe controller state ++ * @gen: PCIe generation to limit the controller's operation to ++ */ ++static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen) ++{ ++ void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS; ++ ++ u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2); ++ u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP); ++ ++ lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; ++ writel(lnkcap, cap_base + PCI_EXP_LNKCAP); ++ ++ lnkctl2 = (lnkctl2 & ~0xf) | gen; ++ writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2); ++} ++ ++static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, ++ unsigned int win, u64 phys_addr, ++ u64 pcie_addr, u64 size) ++{ ++ void __iomem *base = pcie->base; ++ u32 phys_addr_mb_high, limit_addr_mb_high; ++ phys_addr_t phys_addr_mb, limit_addr_mb; ++ int high_addr_shift; ++ u32 tmp; ++ ++ /* Set the base of the pcie_addr window */ ++ writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win)); ++ writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win)); ++ ++ /* Write the addr base & limit lower bits (in MBs) */ ++ phys_addr_mb = phys_addr / SZ_1M; ++ limit_addr_mb = (phys_addr + size - 1) / SZ_1M; ++ ++ tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win)); ++ u32p_replace_bits(&tmp, phys_addr_mb, ++ MEM_WIN0_BASE_LIMIT_BASE_MASK); ++ u32p_replace_bits(&tmp, limit_addr_mb, ++ MEM_WIN0_BASE_LIMIT_LIMIT_MASK); ++ writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win)); ++ ++ /* Write the cpu & limit addr upper bits */ ++ high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT; ++ phys_addr_mb_high = phys_addr_mb >> high_addr_shift; ++ tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win)); ++ u32p_replace_bits(&tmp, phys_addr_mb_high, ++ MEM_WIN0_BASE_HI_BASE_MASK); ++ writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win)); ++ ++ limit_addr_mb_high = limit_addr_mb >> high_addr_shift; ++ tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win)); ++ u32p_replace_bits(&tmp, limit_addr_mb_high, ++ PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); ++ writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); ++} ++ ++static int brcm_pcie_probe(struct udevice *dev) ++{ ++ struct udevice *ctlr = pci_get_controller(dev); ++ struct pci_controller *hose = dev_get_uclass_priv(ctlr); ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ void __iomem *base = pcie->base; ++ bool ssc_good = false; ++ int num_out_wins = 0; ++ u64 rc_bar2_offset, rc_bar2_size; ++ unsigned int scb_size_val; ++ int i, ret; ++ u16 nlw, cls, lnksta; ++ u32 tmp; ++ ++ /* ++ * Reset the bridge, assert the fundamental reset. Note for some SoCs, ++ * e.g. BCM7278, the fundamental reset should not be asserted here. ++ * This will need to be changed when support for other SoCs is added. ++ */ ++ setbits_le32(base + PCIE_RGR1_SW_INIT_1, ++ RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK); ++ /* ++ * The delay is a safety precaution to preclude the reset signal ++ * from looking like a glitch. ++ */ ++ udelay(100); ++ ++ /* Take the bridge out of reset */ ++ clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK); ++ ++ clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, ++ PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); ++ ++ /* Wait for SerDes to be stable */ ++ udelay(100); ++ ++ /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ ++ clrsetbits_le32(base + PCIE_MISC_MISC_CTRL, ++ MISC_CTRL_MAX_BURST_SIZE_MASK, ++ MISC_CTRL_SCB_ACCESS_EN_MASK | ++ MISC_CTRL_CFG_READ_UR_MODE_MASK | ++ MISC_CTRL_MAX_BURST_SIZE_128); ++ /* ++ * TODO: When support for other SoCs than BCM2711 is added we may ++ * need to use the base address and size(s) provided in the dma-ranges ++ * property. ++ */ ++ rc_bar2_offset = 0; ++ rc_bar2_size = 0xc0000000; ++ ++ tmp = lower_32_bits(rc_bar2_offset); ++ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), ++ RC_BAR2_CONFIG_LO_SIZE_MASK); ++ writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); ++ writel(upper_32_bits(rc_bar2_offset), ++ base + PCIE_MISC_RC_BAR2_CONFIG_HI); ++ ++ scb_size_val = rc_bar2_size ? ++ ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ ++ ++ tmp = readl(base + PCIE_MISC_MISC_CTRL); ++ u32p_replace_bits(&tmp, scb_size_val, ++ MISC_CTRL_SCB0_SIZE_MASK); ++ writel(tmp, base + PCIE_MISC_MISC_CTRL); ++ ++ /* Disable the PCIe->GISB memory window (RC_BAR1) */ ++ clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO, ++ RC_BAR1_CONFIG_LO_SIZE_MASK); ++ ++ /* Disable the PCIe->SCB memory window (RC_BAR3) */ ++ clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO, ++ RC_BAR3_CONFIG_LO_SIZE_MASK); ++ ++ /* Mask all interrupts since we are not handling any yet */ ++ writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET); ++ ++ /* Clear any interrupts we find on boot */ ++ writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); ++ ++ if (pcie->gen) ++ brcm_pcie_set_gen(pcie, pcie->gen); ++ ++ /* Unassert the fundamental reset */ ++ clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1, ++ RGR1_SW_INIT_1_PERST_MASK); ++ ++ /* Give the RC/EP time to wake up, before trying to configure RC. ++ * Intermittently check status for link-up, up to a total of 100ms. ++ */ ++ for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) ++ mdelay(5); ++ ++ if (!brcm_pcie_link_up(pcie)) { ++ printf("PCIe BRCM: link down\n"); ++ return -EINVAL; ++ } ++ ++ if (!brcm_pcie_rc_mode(pcie)) { ++ printf("PCIe misconfigured; is in EP mode\n"); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < hose->region_count; i++) { ++ struct pci_region *reg = &hose->regions[i]; ++ ++ if (reg->flags != PCI_REGION_MEM) ++ continue; ++ ++ if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) ++ return -EINVAL; ++ ++ brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start, ++ reg->bus_start, reg->size); ++ ++ num_out_wins++; ++ } ++ ++ /* ++ * For config space accesses on the RC, show the right class for ++ * a PCIe-PCIe bridge (the default setting is to be EP mode). ++ */ ++ clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3, ++ CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400); ++ ++ if (pcie->ssc) { ++ ret = brcm_pcie_set_ssc(pcie->base); ++ if (!ret) ++ ssc_good = true; ++ else ++ printf("PCIe BRCM: failed attempt to enter SSC mode\n"); ++ } ++ ++ lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); ++ cls = lnksta & PCI_EXP_LNKSTA_CLS; ++ nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; ++ ++ printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls), ++ nlw, ssc_good ? "(SSC)" : "(!SSC)"); ++ ++ /* PCIe->SCB endian mode for BAR */ ++ clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1, ++ VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK, ++ VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN); ++ /* ++ * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 ++ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. ++ */ ++ setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, ++ PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK); ++ ++ return 0; ++} ++ ++static int brcm_pcie_ofdata_to_platdata(struct udevice *dev) ++{ ++ struct brcm_pcie *pcie = dev_get_priv(dev); ++ ofnode dn = dev_ofnode(dev); ++ u32 max_link_speed; ++ int ret; ++ ++ /* Get the controller base address */ ++ pcie->base = dev_read_addr_ptr(dev); ++ if (!pcie->base) ++ return -EINVAL; ++ ++ pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); ++ ++ ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); ++ if (ret < 0 || max_link_speed > 4) ++ pcie->gen = 0; ++ else ++ pcie->gen = max_link_speed; ++ ++ return 0; ++} ++ ++static const struct dm_pci_ops brcm_pcie_ops = { ++ .read_config = brcm_pcie_read_config, ++ .write_config = brcm_pcie_write_config, ++}; ++ ++static const struct udevice_id brcm_pcie_ids[] = { ++ { .compatible = "brcm,bcm2711-pcie" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(pcie_brcm_base) = { ++ .name = "pcie_brcm", ++ .id = UCLASS_PCI, ++ .ops = &brcm_pcie_ops, ++ .of_match = brcm_pcie_ids, ++ .probe = brcm_pcie_probe, ++ .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata, ++ .priv_auto_alloc_size = sizeof(struct brcm_pcie), ++}; +diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c +index aa1903e547..9f102c64c6 100644 +--- a/drivers/pci/pcie_intel_fpga.c ++++ b/drivers/pci/pcie_intel_fpga.c +@@ -67,9 +67,6 @@ + #define IS_ROOT_PORT(pcie, bdf) \ + ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) + +-#define PCI_EXP_LNKSTA 18 /* Link Status */ +-#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ +- + /** + * struct intel_fpga_pcie - Intel FPGA PCIe controller state + * @bus: Pointer to the PCI bus +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index 2d968aafb0..f446520528 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -395,6 +395,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) + scratchpad->sp_array[i] = cpu_to_le64(ptr); + } + ++ xhci_flush_cache((uintptr_t)scratchpad->sp_array, ++ sizeof(u64) * num_sp); ++ + return 0; + + fail_sp3: +diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h +index 8b9d6fff00..7ad8b088ed 100644 +--- a/include/linux/bitfield.h ++++ b/include/linux/bitfield.h +@@ -103,4 +103,56 @@ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + ++extern void __compiletime_error("value doesn't fit into mask") ++__field_overflow(void); ++extern void __compiletime_error("bad bitfield mask") ++__bad_mask(void); ++ ++static __always_inline u64 field_multiplier(u64 field) ++{ ++ if ((field | (field - 1)) & ((field | (field - 1)) + 1)) ++ __bad_mask(); ++ return field & -field; ++} ++ ++static __always_inline u64 field_mask(u64 field) ++{ ++ return field / field_multiplier(field); ++} ++ ++#define ____MAKE_OP(type, base, to, from) \ ++static __always_inline __##type type##_encode_bits(base v, base field) \ ++{ \ ++ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ ++ __field_overflow(); \ ++ return to((v & field_mask(field)) * field_multiplier(field)); \ ++} \ ++static __always_inline __##type type##_replace_bits(__##type old, \ ++ base val, base field) \ ++{ \ ++ return (old & ~to(field)) | type##_encode_bits(val, field); \ ++} \ ++static __always_inline void type##p_replace_bits(__##type * p, \ ++ base val, base field) \ ++{ \ ++ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ ++} \ ++static __always_inline base type##_get_bits(__##type v, base field) \ ++{ \ ++ return (from(v) & field) / field_multiplier(field); \ ++} ++ ++#define __MAKE_OP(size) \ ++ ____MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \ ++ ____MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \ ++ ____MAKE_OP(u##size, u##size, ,) ++ ++____MAKE_OP(u8, u8, ,) ++__MAKE_OP(16) ++__MAKE_OP(32) ++__MAKE_OP(64) ++ ++#undef __MAKE_OP ++#undef ____MAKE_OP ++ + #endif +diff --git a/include/pci.h b/include/pci.h +index 19c9244b94..281f353916 100644 +--- a/include/pci.h ++++ b/include/pci.h +@@ -471,10 +471,28 @@ + #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ + + /* PCI Express capabilities */ ++#define PCI_EXP_FLAGS 2 /* Capabilities register */ ++#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ ++#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ + #define PCI_EXP_DEVCAP 4 /* Device capabilities */ +-#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ ++#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ + #define PCI_EXP_DEVCTL 8 /* Device Control */ +-#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ ++#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ ++#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ ++#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ ++#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ ++#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ ++#define PCI_EXP_LNKSTA 18 /* Link Status */ ++#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ ++#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ ++#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ ++#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ ++#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ ++#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ ++#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ ++#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ ++#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ ++#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ + + /* Include the ID list */ + +diff --git a/include/usb/xhci.h b/include/usb/xhci.h +index 20e4a21066..1170c0ac69 100644 +--- a/include/usb/xhci.h ++++ b/include/usb/xhci.h +@@ -1114,28 +1114,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) + */ + static inline u64 xhci_readq(__le64 volatile *regs) + { +-#if BITS_PER_LONG == 64 +- return readq(regs); +-#else + __u32 *ptr = (__u32 *)regs; + u64 val_lo = readl(ptr); + u64 val_hi = readl(ptr + 1); + return val_lo + (val_hi << 32); +-#endif + } + + static inline void xhci_writeq(__le64 volatile *regs, const u64 val) + { +-#if BITS_PER_LONG == 64 +- writeq(val, regs); +-#else + __u32 *ptr = (__u32 *)regs; + u32 val_lo = lower_32_bits(val); + /* FIXME */ + u32 val_hi = upper_32_bits(val); + writel(val_lo, ptr); + writel(val_hi, ptr + 1); +-#endif + } + + int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, +-- +2.26.2 + diff --git a/aarch64-boards b/aarch64-boards index 054230c08d6b2d3c7cb3dcd7162b6c878cde2153..cc0d265e1bb8f44b533348d3529541aa2fd3faf5 100644 --- a/aarch64-boards +++ b/aarch64-boards @@ -1,40 +1,69 @@ a64-olinuxino -avnet_ultra96_rev1 +amarula_a64_relic +bananapi_m2_plus_h5 bananapi_m64 dragonboard410c dragonboard820c espresso7420 evb-rk3328 evb-rk3399 +ficus-rk3399 firefly-rk3399 geekbox hikey +khadas-edge-captain-rk3399 +khadas-edge-v-rk3399 +khadas-edge-rk3399 khadas-vim -libretech-cc +khadas-vim2 +khadas-vim3 +khadas-vim3l +libretech-ac libretech_all_h3_cc_h5 +libretech_all_h3_it_h5 +libretech_all_h5_cc_h5 +libretech-cc mvebu_espressobin-88f3720 mvebu_mcbin-88f8040 +nanopc-t4-rk3399 +nanopi_a64 nanopi-k2 +nanopi-m4-rk3399 nanopi_neo2 +nanopi-neo4-rk3399 nanopi_neo_plus2 odroid-c2 +orangepi_lite2 orangepi_one_plus orangepi_pc2 orangepi_prime +orangepi-rk3399 orangepi_win orangepi_zero_plus orangepi_zero_plus2 p212 p2371-2180 p2771-0000-500 -pine_h64 +p3450-0000 +pine64-lts pine64_plus +pinebook +pinebook-pro-rk3399 +pinephone +pinetab +pine_h64 poplar +puma-rk3399 +rock64-rk3328 rock960-rk3399 +rock-pi-4-rk3399 +rockpro64-rk3399 +roc-pc-rk3399 rpi_3 +rpi_4 +rpi_arm64 sopine_baseboard +teres_i turris_mox -vexpress_aemv8a_dram vexpress_aemv8a_juno -vexpress_aemv8a_semi -xilinx_zynqmp_zcu100_revC +xilinx_zynqmp_virt diff --git a/arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch b/arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch new file mode 100644 index 0000000000000000000000000000000000000000..df63c4ef7f570a75fbb6f103c9282ba2ff9218ac --- /dev/null +++ b/arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch @@ -0,0 +1,55 @@ +From a63eb1bdcd25246b2c637c7846917dc6dc607725 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Thu, 18 Apr 2019 15:44:59 +0100 +Subject: [PATCH] add BOOTENV_EFI_SET_FDTFILE_FALLBACK for tegra186 because tx2 + variants + +Signed-off-by: Peter Robinson +--- + include/config_distro_bootcmd.h | 2 ++ + include/configs/tegra186-common.h | 7 ++++++- + 2 files changed, 8 insertions(+), 1 deletion(-) + +diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h +index fc0935fa21..fd1c5f5afa 100644 +--- a/include/config_distro_bootcmd.h ++++ b/include/config_distro_bootcmd.h +@@ -118,8 +118,10 @@ + "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \ + "fi; " + #else ++#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK + #define BOOTENV_EFI_SET_FDTFILE_FALLBACK + #endif ++#endif + + + #define BOOTENV_SHARED_EFI \ +diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h +index 5c3ad35c76..d5f21e0907 100644 +--- a/include/configs/tegra186-common.h ++++ b/include/configs/tegra186-common.h +@@ -20,6 +20,12 @@ + /* Generic Interrupt Controller */ + #define CONFIG_GICV2 + ++#undef FDTFILE ++#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ ++ "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ ++ "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \ ++ "fi; " ++ + /* + * Memory layout for where various images get loaded by boot scripts: + * +@@ -49,7 +55,6 @@ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ +- "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +-- +2.26.0 + diff --git a/arm-boards b/arm-boards index 95c7f5a0ff042d32ea80ce0574e835627d8ba94b..c07fc976f319d23d89ebb3596432fafb41c7a202 100644 --- a/arm-boards +++ b/arm-boards @@ -6,24 +6,26 @@ A20-Olimex-SOM-EVB A20-OLinuXino-Lime A20-OLinuXino-Lime2 A20-OLinuXino_MICRO -am335x_boneblack am335x_evm -am335x_evm_usbspl am57xx_evm Ampe_A76 +apalis_imx6 arndale Auxtek-T003 Auxtek-T004 ba10_tv_box Bananapi +bananapi_m1_plus bananapi_m2_berry +Bananapi_m2m +bananapi_m2_plus_h3 Bananapi_M2_Ultra +bananapi_m2_zero Bananapro chiliboard CHIP Chuwi_V7_CW0825 clearfog -cl-som-am57x cm_fx6 Colombus colorfly_e708_q1 @@ -37,7 +39,6 @@ db-mv784mp-gp difrnce_dit4350 dserve_dsrv9703c evb-rk3229 -fennec-rk3288 firefly-rk3288 helios4 Hummingbird_A31 @@ -86,7 +87,6 @@ novena odroid odroid-xu3 omap3_beagle -omap3_pandora omap4_panda omap5_uevm Orangepi @@ -115,17 +115,15 @@ rock rock2 rpi_2 rpi_3_32b +rpi_4_32b Sinlinx_SinA31s Sinovoip_BPI_M2 -Sinovoip_BPI_M2_Plus Sinovoip_BPI_M3 -smdkv310 stih410-b2260 sunxi_Gemei_G9 tbs_a711 tinker-rk3288 trimslice -turris_omnia udoo udoo_neo usbarmory @@ -138,6 +136,142 @@ warp7 Wexler_TAB7200 Wits_Pro_A20_DKT Yones_Toptech_BS1078_V2 -zynq_microzed -zynq_zed -zynq_zybo +xilinx_zynq_virtA10-OLinuXino-Lime +A10s-OLinuXino-M +A13-OLinuXino +A13-OLinuXinoM +A20-Olimex-SOM-EVB +A20-OLinuXino-Lime +A20-OLinuXino-Lime2 +A20-OLinuXino_MICRO +am335x_evm +am57xx_evm +Ampe_A76 +apalis_imx6 +arndale +Auxtek-T003 +Auxtek-T004 +ba10_tv_box +Bananapi +bananapi_m1_plus +bananapi_m2_berry +Bananapi_m2m +bananapi_m2_plus_h3 +Bananapi_M2_Ultra +bananapi_m2_zero +Bananapro +chiliboard +CHIP +Chuwi_V7_CW0825 +clearfog +cm_fx6 +Colombus +colorfly_e708_q1 +CSQ_CS908 +Cubieboard +Cubieboard2 +Cubieboard4 +Cubietruck +Cubietruck_plus +db-mv784mp-gp +difrnce_dit4350 +dserve_dsrv9703c +evb-rk3229 +firefly-rk3288 +helios4 +Hummingbird_A31 +Hyundai_A7HD +i12-tvbox +icnova-a20-swac +inet1 +iNet_3F +iNet_3W +inet86dz +iNet_86VS +inet97fv2 +inet98v_rev2 +inet9f_rev03 +inet_q972 +Itead_Ibox_A20 +jesurun_q5 +jetson-tk1 +kc1 +Lamobo_R1 +libretech_all_h3_cc_h2_plus +Linksprite_pcDuino +Linksprite_pcDuino3 +Linksprite_pcDuino3_Nano +liteboard +marsboard +Marsboard_A10 +Mele_A1000 +Mele_A1000G_quad +Mele_I7 +Mele_M3 +Mele_M5 +Mele_M9 +Mini-X +mk802 +mk802_a10s +mk802ii +MK808C +MSI_Primo73 +MSI_Primo81 +mx6cuboxi +nanopi_m1 +nanopi_m1_plus +nanopi_neo +novena +odroid +odroid-xu3 +omap3_beagle +omap4_panda +omap5_uevm +Orangepi +orangepi_2 +orangepi_lite +Orangepi_mini +orangepi_one +orangepi_pc +orangepi_pc_plus +orangepi_plus +orangepi_plus2e +orangepi_r1 +orangepi_zero +origen +paz00 +polaroid_mid2809pxe04 +pov_protab2_ips9 +q8_a13_tablet +q8_a23_tablet_800x480 +q8_a33_tablet_1024x600 +q8_a33_tablet_800x480 +qemu_arm +r7-tv-dongle +riotboard +rock +rock2 +rpi_2 +rpi_3_32b +rpi_4_32b +Sinlinx_SinA31s +Sinovoip_BPI_M2 +Sinovoip_BPI_M3 +stih410-b2260 +sunxi_Gemei_G9 +tbs_a711 +tinker-rk3288 +trimslice +udoo +udoo_neo +usbarmory +UTOO_P66 +vexpress_ca15_tc2 +vexpress_ca9x4 +wandboard +warp +warp7 +Wexler_TAB7200 +Wits_Pro_A20_DKT +Yones_Toptech_BS1078_V2 +xilinx_zynq_virt \ No newline at end of file diff --git a/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch b/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch new file mode 100644 index 0000000000000000000000000000000000000000..8f28d1ce8884ef04231268099e4b417b70ac93ac --- /dev/null +++ b/arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch @@ -0,0 +1,96 @@ +From 88725c4d036bab25c900cc3c962fc42d94e0ab69 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 10 Jun 2020 13:26:43 +0100 +Subject: [PATCH] arm: rk3399: enable rng on rock960 and firefly3399 + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 4 ++++ + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 4 ++++ + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ + configs/firefly-rk3399_defconfig | 2 ++ + configs/rock960-rk3399_defconfig | 2 ++ + configs/rockpro64-rk3399_defconfig | 2 ++ + 6 files changed, 18 insertions(+) + +diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi +index 38e0897db9..a6c7b913da 100644 +--- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi +@@ -11,3 +11,7 @@ + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; + }; ++ ++&rng { ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi +index c190089e26..08292dbd39 100644 +--- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi +@@ -24,3 +24,7 @@ + }; + + }; ++ ++&rng { ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +index bac09df4a3..38fe3bb0ec 100644 +--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +@@ -25,6 +25,10 @@ + }; + }; + ++&rng { ++ status = "okay"; ++}; ++ + &vdd_center { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; +diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig +index 5bb54f5835..551687d6d0 100644 +--- a/configs/firefly-rk3399_defconfig ++++ b/configs/firefly-rk3399_defconfig +@@ -35,6 +35,8 @@ CONFIG_MMC_DW=y + CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_SF_DEFAULT_SPEED=20000000 + CONFIG_DM_ETH=y + CONFIG_ETH_DESIGNWARE=y +diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig +index 59a85c78a1..f31cb92884 100644 +--- a/configs/rock960-rk3399_defconfig ++++ b/configs/rock960-rk3399_defconfig +@@ -37,6 +37,8 @@ CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_DM_ETH=y + CONFIG_NVME=y + CONFIG_PCI=y +diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig +index 807747485a..f778f0b640 100644 +--- a/configs/rockpro64-rk3399_defconfig ++++ b/configs/rockpro64-rk3399_defconfig +@@ -40,6 +40,8 @@ CONFIG_MMC_DW=y + CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_SPI_FLASH_GIGADEVICE=y + CONFIG_DM_ETH=y + CONFIG_ETH_DESIGNWARE=y +-- +2.26.2 + diff --git a/arm-tegra-define-fdtfile-option-for-distro-boot.patch b/arm-tegra-define-fdtfile-option-for-distro-boot.patch new file mode 100644 index 0000000000000000000000000000000000000000..923ccb1b0cad6dcea98f6962f209d2e4954c5dba --- /dev/null +++ b/arm-tegra-define-fdtfile-option-for-distro-boot.patch @@ -0,0 +1,113 @@ +From c3332b102d2ddae01710ae8f4393a2a18a3a1bb3 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 12 May 2020 08:19:48 +0100 +Subject: [PATCH] arm: tegra: define fdtfile option for distro boot + +For booting via UEFI we need to define the fdtfile option so +bootefi has the option to load a fdtfile from disk. For arm64 +the kernel dtb is located in a vendor directory so we define +that as nvidia for that architecture. + +Signed-off-by: Peter Robinson +--- + include/configs/tegra-common.h | 6 ++++++ + include/configs/tegra114-common.h | 1 + + include/configs/tegra124-common.h | 1 + + include/configs/tegra186-common.h | 1 + + include/configs/tegra20-common.h | 1 + + include/configs/tegra210-common.h | 1 + + include/configs/tegra30-common.h | 1 + + 7 files changed, 12 insertions(+) + +diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h +index 175c55c613..8026f4b32e 100644 +--- a/include/configs/tegra-common.h ++++ b/include/configs/tegra-common.h +@@ -52,6 +52,12 @@ + /* Boot Argument Buffer Size */ + #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + ++#ifdef CONFIG_ARM64 ++#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" ++#else ++#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" ++#endif ++ + /*----------------------------------------------------------------------- + * Physical Memory Map + */ +diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h +index d3a7045697..9d751b6740 100644 +--- a/include/configs/tegra114-common.h ++++ b/include/configs/tegra114-common.h +@@ -50,6 +50,7 @@ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83100000\0" + +diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h +index 522993b958..0eb8f92809 100644 +--- a/include/configs/tegra124-common.h ++++ b/include/configs/tegra124-common.h +@@ -52,6 +52,7 @@ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83100000\0" + +diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h +index b4936cc731..5c3ad35c76 100644 +--- a/include/configs/tegra186-common.h ++++ b/include/configs/tegra186-common.h +@@ -49,6 +49,7 @@ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x82000000\0" \ + "ramdisk_addr_r=0x82100000\0" + +diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h +index 1e31d82574..fdd8996955 100644 +--- a/include/configs/tegra20-common.h ++++ b/include/configs/tegra20-common.h +@@ -51,6 +51,7 @@ + "scriptaddr=0x10000000\0" \ + "pxefile_addr_r=0x10100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x03000000\0" \ + "ramdisk_addr_r=0x03100000\0" + +diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h +index 1b8e94b60c..2226effe16 100644 +--- a/include/configs/tegra210-common.h ++++ b/include/configs/tegra210-common.h +@@ -46,6 +46,7 @@ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83200000\0" + +diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h +index 54bc6756ab..6c5dc24b26 100644 +--- a/include/configs/tegra30-common.h ++++ b/include/configs/tegra30-common.h +@@ -47,6 +47,7 @@ + "scriptaddr=0x90000000\0" \ + "pxefile_addr_r=0x90100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ ++ "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x83000000\0" \ + "ramdisk_addr_r=0x83100000\0" + +-- +2.26.2 + diff --git a/dragonboard-fixes.patch b/dragonboard-fixes.patch index 10ee96b3baf04512069da7db76130bab9637aa91..c49ea50196b8c0a51156ccaa48f6cd960de0ab0d 100644 --- a/dragonboard-fixes.patch +++ b/dragonboard-fixes.patch @@ -1,17 +1,17 @@ -From fbd0bffb20ca5edd21bbeb7cc20e24d091ab4280 Mon Sep 17 00:00:00 2001 +From 8b0274a733cd1ce39ad9ad18e1bd8efdd02a40b7 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 21 Jun 2017 14:21:15 -0400 -Subject: [PATCH 1/4] WIP: fix usb +Subject: [PATCH 1/3] WIP: fix usb --- common/usb_storage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/usb_storage.c b/common/usb_storage.c -index a91b1c0d2f..caea87a09f 100644 +index d92ebb6eb19..9df3c3daaf4 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c -@@ -1018,7 +1018,7 @@ static int usb_request_sense(struct scsi_cmd *srb, struct us_data *ss) +@@ -1016,7 +1016,7 @@ static int usb_request_sense(struct scsi_cmd *srb, struct us_data *ss) static int usb_test_unit_ready(struct scsi_cmd *srb, struct us_data *ss) { @@ -20,7 +20,7 @@ index a91b1c0d2f..caea87a09f 100644 do { memset(&srb->cmd[0], 0, 12); -@@ -1041,7 +1041,7 @@ static int usb_test_unit_ready(struct scsi_cmd *srb, struct us_data *ss) +@@ -1039,7 +1039,7 @@ static int usb_test_unit_ready(struct scsi_cmd *srb, struct us_data *ss) if ((srb->sense_buf[2] == 0x02) && (srb->sense_buf[12] == 0x3a)) return -1; @@ -30,12 +30,12 @@ index a91b1c0d2f..caea87a09f 100644 return -1; -- -2.14.3 +2.19.1 -From d1b25b8d6461c5278228d657de9c24e0979e4b9d Mon Sep 17 00:00:00 2001 +From 7bf41d74ca9d58bc2243b7688f8987c1d373ea56 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 3 Jul 2017 08:34:37 -0400 -Subject: [PATCH 2/4] HACK: disable emmc +Subject: [PATCH 2/3] HACK: disable emmc Hitting some timeout which makes boot take much longer. And uefi/boot/rootfs partitions will be on sd-card or usb disk, etc, @@ -45,18 +45,18 @@ so we can just ignore emmc. 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts -index 5ccfe7f8c8..9e2d3f5d9b 100644 +index fa348bc621e..bfe7f15d5ed 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts -@@ -67,6 +67,7 @@ - reg = <0x78d9000 0x400>; +@@ -106,6 +106,7 @@ + #phy-cells = <0>; }; +/* sdhci@07824000 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x11c 0x7824000 0x800>; -@@ -76,6 +77,7 @@ +@@ -115,6 +116,7 @@ clock = <&clkc 0>; clock-frequency = <100000000>; }; @@ -65,22 +65,23 @@ index 5ccfe7f8c8..9e2d3f5d9b 100644 sdhci@07864000 { compatible = "qcom,sdhci-msm-v4"; -- -2.14.3 -From 6baac1d73a20f880cb91f3bc03fe4f9cf88c61f6 Mon Sep 17 00:00:00 2001 +2.19.1 + +From 871fe802cf3ab593b9332c4f36ab2b3f179d51ae Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 4 Sep 2018 12:21:59 +0100 -Subject: [PATCH] add options for dm410c config +Subject: [PATCH 3/3] add options for dm410c config --- configs/dragonboard410c_defconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig -index 96a831443a..d167c765b1 100644 +index a55abaf8df5..4ece0cafbe4 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig -@@ -6,6 +6,8 @@ CONFIG_DISTRO_DEFAULTS=y - CONFIG_NR_DRAM_BANKS=1 +@@ -7,6 +7,8 @@ CONFIG_NR_DRAM_BANKS=1 + # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y +CONFIG_FAT_WRITE=y @@ -88,7 +89,7 @@ index 96a831443a..d167c765b1 100644 CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -@@ -35,6 +37,13 @@ CONFIG_DM_PMIC=y +@@ -41,6 +43,13 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_PM8916=y CONFIG_MSM_SERIAL=y CONFIG_SPMI_MSM=y @@ -102,7 +103,7 @@ index 96a831443a..d167c765b1 100644 CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -@@ -46,5 +55,6 @@ CONFIG_USB_HOST_ETHER=y +@@ -57,5 +66,6 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y @@ -110,5 +111,5 @@ index 96a831443a..d167c765b1 100644 CONFIG_USB_ETHER_SMSC95XX=y CONFIG_OF_LIBFDT_OVERLAY=y -- -2.19.0.rc0 +2.19.1 diff --git a/rk3399-Rock960-board-support.patch b/rk3399-Rock960-board-support.patch deleted file mode 100644 index 0342d2d0f8f7c7cb8771503c814ec9cae649504d..0000000000000000000000000000000000000000 --- a/rk3399-Rock960-board-support.patch +++ /dev/null @@ -1,772 +0,0 @@ -From patchwork Tue Aug 21 17:28:16 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,1/2] arm: dts: Add Rock960 devicetree support -X-Patchwork-Submitter: Manivannan Sadhasivam -X-Patchwork-Id: 960637 -Message-Id: <20180821172817.26463-2-manivannan.sadhasivam@linaro.org> -To: sjg@chromium.org, - philipp.tomsich@theobroma-systems.com -Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, - u-boot@lists.denx.de, - Manivannan Sadhasivam , - stephen@vamrs.com -Date: Tue, 21 Aug 2018 22:58:16 +0530 -From: Manivannan Sadhasivam -List-Id: U-Boot discussion - -Add devicetree support for Vamrs Limited Rock960. This board is one of -the 96Boards Consumer Edition platform. - -Signed-off-by: Manivannan Sadhasivam ---- - -Changes in v2: - -* Added missing DTB entry in arch/arm/dts/Makefile - - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3399-rock960.dts | 348 ++++++++++++++++++++++++++++++++ - 2 files changed, 349 insertions(+) - create mode 100644 arch/arm/dts/rk3399-rock960.dts - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index ebfa2272627..9b891826b73 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rk3399-puma-ddr1333.dtb \ - rk3399-puma-ddr1600.dtb \ - rk3399-puma-ddr1866.dtb \ -+ rk3399-rock960.dtb \ - rv1108-evb.dtb - dtb-$(CONFIG_ARCH_MESON) += \ - meson-gxbb-nanopi-k2.dtb \ -diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts -new file mode 100644 -index 00000000000..8662548e642 ---- /dev/null -+++ b/arch/arm/dts/rk3399-rock960.dts -@@ -0,0 +1,348 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2018 Manivannan Sadhasivam -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include "rk3399.dtsi" -+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" -+ -+/ { -+ model = "Vamrs Limited Rock960 96Board"; -+ compatible = "rockchip,rk3399-rock960", "rockchip,rk3399"; -+ -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = \ -+ &sdhci, &sdmmc; -+ }; -+ -+ vccsys: vccsys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vccsys"; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc5v0_usb: vcc5v0-usb { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc5v0_host0: vcc5v0-host0-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host0"; -+ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vcc5v0_host1: vcc5v0-host1-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host1"; -+ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vcc5v0_host2: vcc5v0-host2-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host2"; -+ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vbus_typec: vbus-typec-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vbus_typec"; -+ gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vdd_log: vdd-log { -+ compatible = "pwm-regulator"; -+ pwms = <&pwm2 0 25000 1>; -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-init-microvolt = <900000>; -+ }; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&pwm3 { -+ status = "okay"; -+}; -+ -+&saradc { -+ status = "okay"; -+}; -+ -+&sdmmc { -+ u-boot,dm-pre-reloc; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ non-removable; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ i2c-scl-falling-time-ns = <50>; -+ i2c-scl-rising-time-ns = <100>; -+ u-boot,dm-pre-reloc; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc5v0_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc5v0_sys>; -+ vcc12-supply = <&vcc3v3_sys>; -+ vcc13-supply = <&vcc5v0_sys>; -+ vcc14-supply = <&vcc5v0_sys>; -+ vddio-supply = <&vcc_1v8>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-name = "vdd_center"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG1 { -+ regulator-name = "vcc1v8_dvp"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_hdmi: LDO_REG2 { -+ regulator-name = "vcca1v8_hdmi"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG3 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-name = "vcc_sdio"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcca1v8_mipi: LDO_REG5 { -+ regulator-name = "vcca1v8_mipi"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-name = "vcc_1v5"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca0v9_hdmi: LDO_REG7 { -+ regulator-name = "vcca0v9_hdmi"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-name = "vcc_3v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <0>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = -+ <1 21 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; - -From patchwork Tue Aug 21 17:28:17 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,v2,2/2] board: Add Vamrs Limited Rock960 board support -X-Patchwork-Submitter: Manivannan Sadhasivam -X-Patchwork-Id: 960641 -Message-Id: <20180821172817.26463-3-manivannan.sadhasivam@linaro.org> -To: sjg@chromium.org, - philipp.tomsich@theobroma-systems.com -Cc: tom@vamrs.com, amit.kucheria@linaro.org, dev@vamrs.com, - u-boot@lists.denx.de, - Manivannan Sadhasivam , - stephen@vamrs.com -Date: Tue, 21 Aug 2018 22:58:17 +0530 -From: Manivannan Sadhasivam -List-Id: U-Boot discussion - -Add board support for Vamrs Limited Rock960 board, which is -one of the 96Boards Consumer Edition platform. - -Rock960 features: - * CPU: ARMv8 64bit Big-Little architecture, - * Big: dual-core Cortex-A72 - * Little: quad-core Cortex-A53 - * IRAM: 200KB - * DRAM: 2GB/4GB LPDDR3 @ 1866MHz - * eMMC: 16/32GB eMMC 5.1 - * PMU: RK808 - * SD/MMC - * USB: - * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only) and - 1x USB 3.0 type C OTG - * Display: - * 1x HDMI 2.0(Type A - full) up to 4Kx2K@60Hz, - 1x 4L - MIPI DSI up to 1080p@60Hz, - 1x DP 1.2(Type C) up to 4Kx2K@60 - * Camera: 2x 4-lane MIPI CSI - * PCI-E: 4- lane M.2 PCI-E 2.1 - * Low Speed Expansion Connector - * High Speed Expansion Connector - -Signed-off-by: Manivannan Sadhasivam ---- - -Changes in v2: None - - arch/arm/mach-rockchip/rk3399/Kconfig | 16 +++++ - board/vamrs/rock960_rk3399/Kconfig | 15 ++++ - board/vamrs/rock960_rk3399/MAINTAINERS | 6 ++ - board/vamrs/rock960_rk3399/Makefile | 6 ++ - board/vamrs/rock960_rk3399/README | 79 +++++++++++++++++++++ - board/vamrs/rock960_rk3399/rock960-rk3399.c | 50 +++++++++++++ - configs/rock960-rk3399_defconfig | 62 ++++++++++++++++ - include/configs/rock960_rk3399.h | 15 ++++ - 8 files changed, 249 insertions(+) - create mode 100644 board/vamrs/rock960_rk3399/Kconfig - create mode 100644 board/vamrs/rock960_rk3399/MAINTAINERS - create mode 100644 board/vamrs/rock960_rk3399/Makefile - create mode 100644 board/vamrs/rock960_rk3399/README - create mode 100644 board/vamrs/rock960_rk3399/rock960-rk3399.c - create mode 100644 configs/rock960-rk3399_defconfig - create mode 100644 include/configs/rock960_rk3399.h - -diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig -index 415466a49bb..ce4605187e3 100644 ---- a/arch/arm/mach-rockchip/rk3399/Kconfig -+++ b/arch/arm/mach-rockchip/rk3399/Kconfig -@@ -28,6 +28,21 @@ config TARGET_PUMA_RK3399 - * HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI - * SPI, I2C, I2S, UART, GPIO, ... - -+config TARGET_ROCK960_RK3399 -+ bool "Vamrs Limited Rock960 board" -+ help -+ Support for Rock960 board. This board complies with -+ 96Board Consumer Edition Specification. -+ -+ Features: -+ * Rockchip RK3399 SoC (2xCortex A72, 4xCortex A53, ARM Mali T860MP4) -+ * 2GiB/4GiB RAM -+ * 16/32GB eMMC, uSD slot -+ * WiFi, Bluetooth -+ * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only), 1x USB 3.0 type C OTG -+ * HDMI -+ * 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons -+ - endchoice - - config SYS_SOC -@@ -38,5 +53,6 @@ config SYS_MALLOC_F_LEN - - source "board/rockchip/evb_rk3399/Kconfig" - source "board/theobroma-systems/puma_rk3399/Kconfig" -+source "board/vamrs/rock960_rk3399/Kconfig" - - endif -diff --git a/board/vamrs/rock960_rk3399/Kconfig b/board/vamrs/rock960_rk3399/Kconfig -new file mode 100644 -index 00000000000..cacc53f3780 ---- /dev/null -+++ b/board/vamrs/rock960_rk3399/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_ROCK960_RK3399 -+ -+config SYS_BOARD -+ default "rock960_rk3399" -+ -+config SYS_VENDOR -+ default "vamrs" -+ -+config SYS_CONFIG_NAME -+ default "rock960_rk3399" -+ -+config BOARD_SPECIFIC_OPTIONS # dummy -+ def_bool y -+ -+endif -diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS b/board/vamrs/rock960_rk3399/MAINTAINERS -new file mode 100644 -index 00000000000..9f3fe75f4fb ---- /dev/null -+++ b/board/vamrs/rock960_rk3399/MAINTAINERS -@@ -0,0 +1,6 @@ -+ROCK960-RK3399 -+M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org -+S: Maintained -+F: board/rockchip/rock960_rk3399 -+F: include/configs/rock960_rk3399.h -+F: configs/rock960-rk3399_defconfig -diff --git a/board/vamrs/rock960_rk3399/Makefile b/board/vamrs/rock960_rk3399/Makefile -new file mode 100644 -index 00000000000..6c3e475b3a8 ---- /dev/null -+++ b/board/vamrs/rock960_rk3399/Makefile -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+# Copyright (C) 2018 Manivannan Sadhasivam -+# -+ -+obj-y += rock960-rk3399.o -diff --git a/board/vamrs/rock960_rk3399/README b/board/vamrs/rock960_rk3399/README -new file mode 100644 -index 00000000000..be6b5cd1d34 ---- /dev/null -+++ b/board/vamrs/rock960_rk3399/README -@@ -0,0 +1,79 @@ -+Introduction -+============ -+ -+Rock960 is a 96Boards Consumer Edition platform featuring the Rockchip -+RK3399 SoC. -+ -+Rock960 features: -+ * CPU: ARMv8 64bit Big-Little architecture, -+ * Big: dual-core Cortex-A72 -+ * Little: quad-core Cortex-A53 -+ * IRAM: 200KB -+ * DRAM: 2GB/4GB LPDDR3 @ 1866MHz -+ * eMMC: 16/32GB eMMC 5.1 -+ * PMU: RK808 -+ * SD/MMC -+ * USB: -+ * 1x USB 3.0 type A, 1x USB 2.0 type A (host mode only) and -+ 1x USB 3.0 type C OTG -+ * Display: -+ * 1x HDMI 2.0(Type A - full) up to 4Kx2K@60Hz, -+ 1x 4L - MIPI DSI up to 1080p@60Hz, -+ 1x DP 1.2(Type C) up to 4Kx2K@60 -+ * Camera: 2x 4-lane MIPI CSI -+ * PCI-E: 4- lane M.2 PCI-E 2.1 -+ * Low Speed Expansion Connector -+ * High Speed Expansion Connector -+ -+Here is the step-by-step to boot to U-Boot on rk3399. -+ -+Get the Source and prebuild binary -+================================== -+ -+ > git clone https://github.com/96rocks/rkbin.git -+ > git clone https://github.com/rockchip-linux/rkdeveloptool.git -+ -+Compile the U-Boot -+================== -+ -+ > cd ../u-boot -+ > export ARCH=arm64 -+ > export CROSS_COMPILE=aarch64-linux-gnu- -+ > make rock960-rk3399_defconfig -+ > make -+ -+Compile the rkdeveloptool -+========================= -+ Follow instructions in latest README -+ > cd ../rkdeveloptool -+ > autoreconf -i -+ > ./configure -+ > make -+ > sudo make install -+ -+Package the image -+================= -+ -+Package the image for Rockchip miniloader -+------------------------------------------ -+ > cd ../rkbin -+ > ./tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img 0x200000 -+ -+ > ../u-boot/tools/mkimage -n rk3399 -T rksd -d rk3399_ddr_933MHz_v1.08.bin idbloader.img -+ > cat ./rk33/rk3399_miniloader_v1.06.bin >> idbloader.img -+ -+ Get uboot.img and idbloader.img in this step. -+ -+Flash the image to eMMC -+======================= -+ -+Flash the image with Rockchip miniloader -+---------------------------------------- -+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: -+ > rkdeveloptool db ./rk33/rk3399_loader_v1.08.106.bin -+ > rkdeveloptool wl 0x40 idbloader.img -+ > rkdeveloptool wl 0x4000 uboot.img -+ > rkdeveloptool wl 0x6000 ./img/rk3399/trust.img -+ > rkdeveloptool rd -+ -+You should be able to get U-Boot log in console/UART2(baurdrate 1500000) -diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c -new file mode 100644 -index 00000000000..d3775b22191 ---- /dev/null -+++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c -@@ -0,0 +1,50 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2018 Manivannan Sadhasivam -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+int board_init(void) -+{ -+ int ret; -+ -+ ret = regulators_enable_boot_on(false); -+ if (ret) -+ debug("%s: Cannot enable boot on regulator\n", __func__); -+ -+ return 0; -+} -+ -+void spl_board_init(void) -+{ -+ struct udevice *pinctrl; -+ int ret; -+ -+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); -+ if (ret) { -+ debug("%s: Cannot find pinctrl device\n", __func__); -+ goto err; -+ } -+ -+ /* Enable debug UART */ -+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); -+ if (ret) { -+ debug("%s: Failed to set up console UART\n", __func__); -+ goto err; -+ } -+ -+ preloader_console_init(); -+ return; -+err: -+ printf("%s: Error %d\n", __func__, ret); -+ -+ /* No way to report error here */ -+ hang(); -+} -diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig -new file mode 100644 -index 00000000000..998c7a4b707 ---- /dev/null -+++ b/configs/rock960-rk3399_defconfig -@@ -0,0 +1,62 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_SYS_MALLOC_F_LEN=0x4000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 -+CONFIG_TARGET_ROCK960_RK3399=y -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_BAUDRATE=1500000 -+CONFIG_SPL_STACK_R_ADDR=0x80000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" -+CONFIG_SYS_PROMPT="rock960 => " -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_SF=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_PINCTRL_ROCKCHIP_RK3399=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_SYSRESET=y -+CONFIG_USE_TINY_PRINTF=y -+CONFIG_ERRNO_STR=y -diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h -new file mode 100644 -index 00000000000..746d24cbff5 ---- /dev/null -+++ b/include/configs/rock960_rk3399.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright (C) 2018 Manivannan Sadhasivam -+ */ -+ -+#ifndef __ROCK960_RK3399_H -+#define __ROCK960_RK3399_H -+ -+#include -+ -+#define CONFIG_SYS_MMC_ENV_DEV 1 -+ -+#define SDRAM_BANK_SIZE (2UL << 30) -+ -+#endif diff --git a/rockchip-Pinebook-Pro-Fixes.patch b/rockchip-Pinebook-Pro-Fixes.patch new file mode 100644 index 0000000000000000000000000000000000000000..0b0a2d7159b720675ec70a8317baee9d83e3a632 --- /dev/null +++ b/rockchip-Pinebook-Pro-Fixes.patch @@ -0,0 +1,200 @@ +From e27621a7c2c0e090977c17f604093c720ca01fe4 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Mon, 8 Jun 2020 20:31:33 +0100 +Subject: [PATCH 1/3] rockchip: Pinebook Pro: enable rng to provide an entropy + source + +Enable the rng so UEFI can provide entropy for KASLR + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4 ++++ + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ + configs/pinebook-pro-rk3399_defconfig | 2 ++ + 3 files changed, 10 insertions(+) + +diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +index 1a2e24d3ef..296321d697 100644 +--- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +@@ -24,6 +24,10 @@ + u-boot,dm-pre-reloc; + }; + ++&rng { ++ status = "okay"; ++}; ++ + &sdhci { + max-frequency = <25000000>; + u-boot,dm-pre-reloc; +diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +index bac09df4a3..cb8991aa25 100644 +--- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +@@ -19,6 +19,10 @@ + }; + }; + ++&rng { ++ status = "okay"; ++}; ++ + &spi1 { + spi_flash: flash@0 { + u-boot,dm-pre-reloc; +diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig +index 0c129b9aeb..21eecf477c 100644 +--- a/configs/pinebook-pro-rk3399_defconfig ++++ b/configs/pinebook-pro-rk3399_defconfig +@@ -54,6 +54,8 @@ CONFIG_DM_PMIC_FAN53555=y + CONFIG_PMIC_RK8XX=y + CONFIG_REGULATOR_PWM=y + CONFIG_REGULATOR_RK8XX=y ++CONFIG_DM_RNG=y ++CONFIG_RNG_ROCKCHIP=y + CONFIG_PWM_ROCKCHIP=y + CONFIG_RAM_RK3399_LPDDR4=y + CONFIG_DM_RESET=y +-- +2.26.2 + +From 99a3c9ba5a8ab7a94aa700649e031f53d498e857 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Mon, 8 Jun 2020 22:23:05 +0100 +Subject: [PATCH 2/3] rockchip: Pinebook Pro: Fix USB and the USB attached + keyboard + +The built in keyboard on the Pinebook Pro is attached via USB so +fix this up to ensure USB works as expected. + +Signed-off-by: Peter Robinson +--- + configs/pinebook-pro-rk3399_defconfig | 5 +++++ + include/configs/pinebook-pro-rk3399.h | 3 +++ + 2 files changed, 8 insertions(+) + +diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig +index 21eecf477c..733463556a 100644 +--- a/configs/pinebook-pro-rk3399_defconfig ++++ b/configs/pinebook-pro-rk3399_defconfig +@@ -61,6 +61,8 @@ CONFIG_RAM_RK3399_LPDDR4=y + CONFIG_DM_RESET=y + CONFIG_BAUDRATE=1500000 + CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="usb start" + CONFIG_ROCKCHIP_SPI=y + CONFIG_SYSRESET=y + CONFIG_USB=y +@@ -68,8 +70,11 @@ CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_DWC3=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y + CONFIG_USB_DWC3=y + CONFIG_ROCKCHIP_USB2_PHY=y ++CONFIG_DM_KEYBOARD=y + CONFIG_USB_KEYBOARD=y + CONFIG_USB_HOST_ETHER=y + CONFIG_USB_ETHER_ASIX=y +diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h +index 4bc8802d11..d910830582 100644 +--- a/include/configs/pinebook-pro-rk3399.h ++++ b/include/configs/pinebook-pro-rk3399.h +@@ -25,4 +25,7 @@ + + #define SDRAM_BANK_SIZE (2UL << 30) + ++#define CONFIG_USB_OHCI_NEW ++#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 ++ + #endif +-- +2.26.2 + +From 64d43a4f0a135486a9a524b107c853831e492eb6 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Mon, 8 Jun 2020 23:41:50 +0100 +Subject: [PATCH 3/3] rockchip: Pinebook Pro: Fix SPI flash and store env on it + +Some minor fixes for SPI flash on the Pinebook Pro and also +default to saving environment to the SPI flash as it's +guaranteed to be on board. + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 6 +++++- + configs/pinebook-pro-rk3399_defconfig | 3 +++ + include/configs/pinebook-pro-rk3399.h | 9 --------- + 3 files changed, 8 insertions(+), 10 deletions(-) + +diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +index 296321d697..ded7db0aef 100644 +--- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +@@ -12,7 +12,11 @@ + }; + + chosen { +- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; ++ u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc; ++ }; ++ ++ config { ++ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ + }; + }; + +diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig +index 733463556a..18b2d74253 100644 +--- a/configs/pinebook-pro-rk3399_defconfig ++++ b/configs/pinebook-pro-rk3399_defconfig +@@ -1,6 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_ROCKCHIP=y + CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_ENV_SIZE=0x8000 + CONFIG_ROCKCHIP_RK3399=y + CONFIG_TARGET_PINEBOOK_PRO_RK3399=y + CONFIG_NR_DRAM_BANKS=1 +@@ -17,6 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_STACK_R=y + CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 + CONFIG_SPL_MTD_SUPPORT=y ++CONFIG_SPL_SPI_LOAD=y + CONFIG_TPL=y + CONFIG_CMD_BOOTZ=y + CONFIG_CMD_GPIO=y +@@ -32,6 +34,7 @@ CONFIG_CMD_REGULATOR=y + CONFIG_SPL_OF_CONTROL=y + CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" + CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ROCKCHIP_GPIO=y + CONFIG_SYS_I2C_ROCKCHIP=y +diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h +index d910830582..d478b19917 100644 +--- a/include/configs/pinebook-pro-rk3399.h ++++ b/include/configs/pinebook-pro-rk3399.h +@@ -14,15 +14,6 @@ + + #include + +-#if defined(CONFIG_ENV_IS_IN_MMC) +-#define CONFIG_SYS_MMC_ENV_DEV 0 +-#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +-#define CONFIG_ENV_SECT_SIZE (8 * 1024) +-#endif +- +-#undef CONFIG_SYS_SPI_U_BOOT_OFFS +-#define CONFIG_SYS_SPI_U_BOOT_OFFS 1024 * 512 +- + #define SDRAM_BANK_SIZE (2UL << 30) + + #define CONFIG_USB_OHCI_NEW +-- +2.26.2 + diff --git a/rockchip-make_fit_atf-fix-warning-unit_address_vs_reg.patch b/rockchip-make_fit_atf-fix-warning-unit_address_vs_reg.patch deleted file mode 100644 index d64cbb1f3091f68540c29b8042a428937ecb62a3..0000000000000000000000000000000000000000 --- a/rockchip-make_fit_atf-fix-warning-unit_address_vs_reg.patch +++ /dev/null @@ -1,103 +0,0 @@ -From patchwork Thu Apr 26 06:43:06 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot] rockchip: make_fit_atf: fix warning unit_address_vs_reg -X-Patchwork-Submitter: Kever Yang -X-Patchwork-Id: 904884 -Message-Id: <1524724986-28497-1-git-send-email-kever.yang@rock-chips.com> -To: u-boot@lists.denx.de -Date: Thu, 26 Apr 2018 14:43:06 +0800 -From: Kever Yang -List-Id: U-Boot discussion - -Patch fix warning: -/builddir/BUILD/u-boot-2018.05-rc2/"arch/arm/mach-rockchip/make_fit_atf.py" \ -arch/arm/dts/rk3399-firefly.dtb > u-boot.its - ./tools/mkimage -f u-boot.its -E u-boot.itb >/dev/null && cat -/dev/null -u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1 -has a unit name, but no reg property -u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@1 has -a unit name, but no reg property -u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@2 has -a unit name, but no reg property -u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@3 has -a unit name, but no reg property -u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/fdt@1 has -a unit name, but no reg property -u-boot.itb.tmp: Warning (unit_address_vs_reg): Node -/configurations/config@1 has a unit name, but no reg property -make[1]: Leaving directory -'/builddir/BUILD/u-boot-2018.05-rc2/builds/firefly-rk3399' - -Reported-by: Peter Robinson -Signed-off-by: Kever Yang ---- - - arch/arm/mach-rockchip/make_fit_atf.py | 18 +++++++++--------- - 1 file changed, 9 insertions(+), 9 deletions(-) - -diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py -index 7c6dd57..513e088 100755 ---- a/arch/arm/mach-rockchip/make_fit_atf.py -+++ b/arch/arm/mach-rockchip/make_fit_atf.py -@@ -37,7 +37,7 @@ DT_HEADER="""/* - #address-cells = <1>; - - images { -- uboot@1 { -+ uboot { - description = "U-Boot (64-bit)"; - data = /incbin/("u-boot-nodtb.bin"); - type = "standalone"; -@@ -61,7 +61,7 @@ def append_atf_node(file, atf_index, phy_addr): - Append ATF DT node to input FIT dts file. - """ - data = 'bl31_0x%08x.bin' % phy_addr -- print >> file, '\t\tatf@%d {' % atf_index -+ print >> file, '\t\tatf_%d {' % atf_index - print >> file, '\t\t\tdescription = \"ARM Trusted Firmware\";' - print >> file, '\t\t\tdata = /incbin/("%s");' % data - print >> file, '\t\t\ttype = "firmware";' -@@ -81,7 +81,7 @@ def append_fdt_node(file, dtbs): - cnt = 1 - for dtb in dtbs: - dtname = os.path.basename(dtb) -- print >> file, '\t\tfdt@%d {' % cnt -+ print >> file, '\t\tfdt_%d {' % cnt - print >> file, '\t\t\tdescription = "%s";' % dtname - print >> file, '\t\t\tdata = /incbin/("%s");' % dtb - print >> file, '\t\t\ttype = "flat_dt";' -@@ -91,17 +91,17 @@ def append_fdt_node(file, dtbs): - cnt = cnt + 1 - - def append_conf_section(file, cnt, dtname, atf_cnt): -- print >> file, '\t\tconfig@%d {' % cnt -+ print >> file, '\t\tconfig_%d {' % cnt - print >> file, '\t\t\tdescription = "%s";' % dtname -- print >> file, '\t\t\tfirmware = "atf@1";' -- print >> file, '\t\t\tloadables = "uboot@1",', -+ print >> file, '\t\t\tfirmware = "atf_1";' -+ print >> file, '\t\t\tloadables = "uboot",', - for i in range(1, atf_cnt): -- print >> file, '"atf@%d"' % (i+1), -+ print >> file, '"atf_%d"' % (i+1), - if i != (atf_cnt - 1): - print >> file, ',', - else: - print >> file, ';' -- print >> file, '\t\t\tfdt = "fdt@1";' -+ print >> file, '\t\t\tfdt = "fdt_1";' - print >> file, '\t\t};' - print >> file, '' - -@@ -111,7 +111,7 @@ def append_conf_node(file, dtbs, atf_cnt): - """ - cnt = 1 - print >> file, '\tconfigurations {' -- print >> file, '\t\tdefault = "config@1";' -+ print >> file, '\t\tdefault = "config_1";' - for dtb in dtbs: - dtname = os.path.basename(dtb) - append_conf_section(file, cnt, dtname, atf_cnt) diff --git a/rockchip-make_fit_atf-use-elf-entry-point.patch b/rockchip-make_fit_atf-use-elf-entry-point.patch deleted file mode 100644 index fc2aa99c4007fba3e621ef354873a4a7ebeddc42..0000000000000000000000000000000000000000 --- a/rockchip-make_fit_atf-use-elf-entry-point.patch +++ /dev/null @@ -1,81 +0,0 @@ -From patchwork Wed May 16 16:44:33 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot] rockchip: make_fit_atf: use elf entry point -X-Patchwork-Submitter: Mian Yousaf Kaukab -X-Patchwork-Id: 914901 -Message-Id: <20180516164433.30998-1-yousaf.kaukab@suse.com> -To: u-boot@lists.denx.de -Cc: Mian Yousaf Kaukab -Date: Wed, 16 May 2018 18:44:33 +0200 -From: Mian Yousaf Kaukab -List-Id: U-Boot discussion - -make_fit_atf.py uses physical address of first segment as the -entry point to bl31. It is incorrect and causes following abort -when bl31_entry() is called: - -U-Boot SPL board initTrying to boot from MMC1 -"Synchronous Abort" handler, esr 0x02000000 -elr: 0000000000000000 lr : 00000000ff8c7e8c -x 0: 00000000ff8e0000 x 1: 0000000000000000 -x 2: 0000000000000000 x 3: 00000000ff8e0180 -x 4: 0000000000000000 x 5: 0000000000000000 -x 6: 0000000000000030 x 7: 00000000ff8e0188 -x 8: 00000000000001e0 x 9: 0000000000000000 -x10: 000000000007fcdc x11: 00000000002881b8 -x12: 00000000000001a2 x13: 0000000000000198 -x14: 000000000007fdcc x15: 00000000002881b8 -x16: 00000000003c0724 x17: 00000000003c0718 -x18: 000000000007fe80 x19: 00000000ff8e0000 -x20: 0000000000200000 x21: 00000000ff8e0000 -x22: 0000000000000000 x23: 000000000007fe30 -x24: 00000000ff8d1c3c x25: 00000000ff8d5000 -x26: 00000000deadbeef x27: 00000000000004a0 -x28: 000000000000009c x29: 000000000007fd90 - -Fix it by using the entry point from the elf header. - -Signed-off-by: Mian Yousaf Kaukab ---- - arch/arm/mach-rockchip/make_fit_atf.py | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py -index 6b3d9201c9..b88a5e1f16 100755 ---- a/arch/arm/mach-rockchip/make_fit_atf.py -+++ b/arch/arm/mach-rockchip/make_fit_atf.py -@@ -53,7 +53,7 @@ DT_END=""" - }; - """ - --def append_atf_node(file, atf_index, phy_addr): -+def append_atf_node(file, atf_index, phy_addr, elf_entry): - """ - Append ATF DT node to input FIT dts file. - """ -@@ -67,7 +67,7 @@ def append_atf_node(file, atf_index, phy_addr): - print >> file, '\t\t\tcompression = "none";' - print >> file, '\t\t\tload = <0x%08x>;' % phy_addr - if atf_index == 1: -- print >> file, '\t\t\tentry = <0x%08x>;' % phy_addr -+ print >> file, '\t\t\tentry = <0x%08x>;' % elf_entry - print >> file, '\t\t};' - print >> file, '' - -@@ -141,12 +141,13 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_fi - - with open(bl31_file_name) as bl31_file: - bl31 = ELFFile(bl31_file) -+ elf_entry = bl31.header['e_entry'] - for i in range(bl31.num_segments()): - seg = bl31.get_segment(i) - if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)): - paddr = seg.__getitem__(ELF_SEG_P_PADDR) - p= seg.__getitem__(ELF_SEG_P_PADDR) -- append_atf_node(fit_file, i+1, paddr) -+ append_atf_node(fit_file, i+1, paddr, elf_entry) - atf_cnt = i+1 - append_fdt_node(fit_file, dtbs_file_name) - print >> fit_file, '%s' % DT_IMAGES_NODE_END diff --git a/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch b/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch index f3d20a6e25499392e109b48639f3b252ad09252e..0e30129caccdcfb5274ae26f283fd626b2d8ce93 100644 --- a/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch +++ b/rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch @@ -1,6 +1,6 @@ -From 44dd1455f924aa99e6bff0b124a9be0a85dcfa89 Mon Sep 17 00:00:00 2001 +From 7389a936fbd5ccaae7c39d38d1440e0359f9d0e5 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 4 Sep 2018 11:59:18 +0100 +Date: Tue, 12 May 2020 08:14:26 +0100 Subject: [PATCH] rpi: Use firmware provided device tree Signed-off-by: Peter Robinson @@ -13,70 +13,70 @@ Signed-off-by: Peter Robinson 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig -index d5bf01b76e..08f177f34a 100644 +index 5053a38822..3c6af2b367 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig -@@ -13,7 +13,7 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_GPIO=y +@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig -index a50a815759..0918c6c9ff 100644 +index 0000a759f1..f27c5ab1f6 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig -@@ -13,7 +13,7 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_GPIO=y +@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig -index ec395d29ed..22165bde53 100644 +index a714f9ec49..90ce6ea22e 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig -@@ -14,7 +14,7 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_GPIO=y +@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig -index ac99f2000a..0ca298cd54 100644 +index 244d9b3a78..f72d6d35e2 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig -@@ -14,7 +14,7 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_GPIO=y +@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig -index db42ffd135..0ec1365b1b 100644 +index 64bb184c2b..645dbbec33 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig -@@ -13,7 +13,7 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_GPIO=y +@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- -2.19.0.rc0 +2.26.2 diff --git a/sunxi-DT-A64-add-Pine64-LTS-support.patch b/sunxi-DT-A64-add-Pine64-LTS-support.patch deleted file mode 100644 index cf041afcb1bbd02ba9078e764e8dbbed031331f9..0000000000000000000000000000000000000000 --- a/sunxi-DT-A64-add-Pine64-LTS-support.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 82cc7aca5fb7c7103256229a3ead0b8075da5813 Mon Sep 17 00:00:00 2001 -From: Peter Robinson -Date: Wed, 5 Sep 2018 17:00:25 +0100 -Subject: [PATCH] sunxi: DT: A64: add Pine64-LTS support - -The Pine64-LTS board is a new board version of the Pine64, though -actually it's a non-SoM version of the SoPine and its baseboard. -In contrast to the original Pine64 it features LPDDR3 DRAM, an eMMC -socket and a SPI flash chip for storing firmware (like U-Boot). -Add it as a variant to the existing SoPine defconfig, since from a -software point of view they are really not different. - -Signed-off-by: Andre Przywara -Signed-off-by: Peter Robinson ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/sun50i-a64-pine64-lts.dts | 13 +++++++++++++ - configs/sopine_baseboard_defconfig | 1 + - 3 files changed, 15 insertions(+) - create mode 100644 arch/arm/dts/sun50i-a64-pine64-lts.dts - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index ebfa227262..6cd440d6af 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -401,6 +401,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \ - sun50i-a64-nanopi-a64.dtb \ - sun50i-a64-olinuxino.dtb \ - sun50i-a64-orangepi-win.dtb \ -+ sun50i-a64-pine64-lts.dtb \ - sun50i-a64-pine64-plus.dtb \ - sun50i-a64-pine64.dtb \ - sun50i-a64-sopine-baseboard.dtb -diff --git a/arch/arm/dts/sun50i-a64-pine64-lts.dts b/arch/arm/dts/sun50i-a64-pine64-lts.dts -new file mode 100644 -index 0000000000..72d6961dc3 ---- /dev/null -+++ b/arch/arm/dts/sun50i-a64-pine64-lts.dts -@@ -0,0 +1,13 @@ -+/* -+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ * -+ * Copyright (c) 2018 ARM Ltd. -+ */ -+ -+#include "sun50i-a64-sopine-baseboard.dts" -+ -+/ { -+ model = "Pine64 LTS"; -+ compatible = "pine64,pine64-lts", "allwinner,sun50i-r18", -+ "allwinner,sun50i-a64"; -+}; -diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig -index 9ede081c08..eead38a1e3 100644 ---- a/configs/sopine_baseboard_defconfig -+++ b/configs/sopine_baseboard_defconfig -@@ -15,6 +15,7 @@ CONFIG_NR_DRAM_BANKS=1 - # CONFIG_SPL_DOS_PARTITION is not set - # CONFIG_SPL_EFI_PARTITION is not set - CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-sopine-baseboard" -+CONFIG_OF_LIST="sun50i-a64-sopine-baseboard sun50i-a64-pine64-lts" - CONFIG_SUN8I_EMAC=y - CONFIG_USB_EHCI_HCD=y - CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y --- -2.19.0.rc0 - diff --git a/tegra-efi_loader-simplify-ifdefs.patch b/tegra-efi_loader-simplify-ifdefs.patch deleted file mode 100644 index 1b39a4a8e12d2a3c2f36f6db9a495654d67a98c0..0000000000000000000000000000000000000000 --- a/tegra-efi_loader-simplify-ifdefs.patch +++ /dev/null @@ -1,194 +0,0 @@ -From patchwork Thu Aug 30 21:43:43 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot,V3,1/3] efi_loader: simplify ifdefs -X-Patchwork-Submitter: Stephen Warren -X-Patchwork-Id: 964248 -X-Patchwork-Delegate: agraf@suse.de -Message-Id: <20180830214345.2475-1-swarren@wwwdotorg.org> -To: Tom Rini -Cc: Stephen Warren , xypron.glpk@gmx.de, agraf@suse.de, - u-boot@lists.denx.de, Tom Warren -Date: Thu, 30 Aug 2018 15:43:43 -0600 -From: Stephen Warren -List-Id: U-Boot discussion - -From: Stephen Warren - -Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL -too. This simplifies the conditional. - -Signed-off-by: Stephen Warren ---- -v3: New patch. ---- - arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- - arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- - arch/x86/lib/e820.c | 4 ++-- - include/efi_loader.h | 6 +++--- - 4 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c -index 052e0708d454..be00bd55ab68 100644 ---- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c -+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c -@@ -835,7 +835,7 @@ int dram_init_banksize(void) - return 0; - } - --#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) -+#if CONFIG_IS_ENABLED(EFI_LOADER) - void efi_add_known_memory(void) - { - int i; -diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c -index fc9de73bcef4..c9c2c3f6d3e8 100644 ---- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c -+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c -@@ -135,7 +135,7 @@ remove_psci_node: - - fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code, - *boot_code_size); --#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) -+#if CONFIG_IS_ENABLED(EFI_LOADER) - efi_add_memory_map((uintptr_t)&secondary_boot_code, - ALIGN(*boot_code_size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT, - EFI_RESERVED_MEMORY_TYPE, false); -diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c -index 8b34f677d96d..d6ae2c4e9d77 100644 ---- a/arch/x86/lib/e820.c -+++ b/arch/x86/lib/e820.c -@@ -36,7 +36,7 @@ __weak unsigned int install_e820_map(unsigned int max_entries, - return 4; - } - --#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) -+#if CONFIG_IS_ENABLED(EFI_LOADER) - void efi_add_known_memory(void) - { - struct e820_entry e820[E820MAX]; -@@ -72,4 +72,4 @@ void efi_add_known_memory(void) - efi_add_memory_map(start, pages, type, false); - } - } --#endif /* defined(EFI_LOADER) && !defined(CONFIG_SPL_BUILD) */ -+#endif /* CONFIG_IS_ENABLED(EFI_LOADER) */ -diff --git a/include/efi_loader.h b/include/efi_loader.h -index f162adfff7e2..b46babf9316f 100644 ---- a/include/efi_loader.h -+++ b/include/efi_loader.h -@@ -13,7 +13,7 @@ - #include - - /* No need for efi loader support in SPL */ --#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) -+#if CONFIG_IS_ENABLED(EFI_LOADER) - - #include - -@@ -460,7 +460,7 @@ efi_status_t EFIAPI efi_set_variable(u16 *variable_name, efi_guid_t *vendor, - void *efi_bootmgr_load(struct efi_device_path **device_path, - struct efi_device_path **file_path); - --#else /* defined(EFI_LOADER) && !defined(CONFIG_SPL_BUILD) */ -+#else /* CONFIG_IS_ENABLED(EFI_LOADER) */ - - /* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */ - #define __efi_runtime_data -@@ -477,6 +477,6 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr, - static inline void efi_net_set_dhcp_ack(void *pkt, int len) { } - static inline void efi_print_image_infos(void *pc) { } - --#endif /* CONFIG_EFI_LOADER && !CONFIG_SPL_BUILD */ -+#endif /* CONFIG_IS_ENABLED(EFI_LOADER) */ - - #endif /* _EFI_LOADER_H */ - -From patchwork Thu Aug 30 21:43:44 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [U-Boot, V3, - 2/3] ARM: tegra: reserve unmapped RAM so EFI doesn't use it -X-Patchwork-Submitter: Stephen Warren -X-Patchwork-Id: 964249 -X-Patchwork-Delegate: agraf@suse.de -Message-Id: <20180830214345.2475-2-swarren@wwwdotorg.org> -To: Tom Rini -Cc: Stephen Warren , xypron.glpk@gmx.de, agraf@suse.de, - u-boot@lists.denx.de, Tom Warren -Date: Thu, 30 Aug 2018 15:43:44 -0600 -From: Stephen Warren -List-Id: U-Boot discussion - -From: Stephen Warren - -Tegra U-Boot ensures that board_get_usable_ram_top() never returns a value -over 4GB, since some peripherals can't access such addresses. However, on -systems with more than 2GB of RAM, RAM bank 1 does describe this extra -RAM, so that Linux (or whatever OS) can use it, subject to DMA -limitations. Since board_get_usable_ram_top() points at the top of RAM -bank 0, the memory locations describes by RAM bank 1 are not mapped by -U-Boot's MMU configuration, and so cannot be used for anything. - -For some completely inexplicable reason, U-Boot's EFI support ignores the -value returned by board_get_usable_ram_top(), and EFI memory allocation -routines will return values above U-Boot's RAM top. This causes U-Boot to -crash when it accesses that RAM, since it isn't mapped by the MMU. One -use-case where this happens is TFTP download of a file on Jetson TX1 -(p2371-2180). - -This change explicitly tells the EFI code that this extra RAM should not -be used, thus avoiding the crash. - -A previous attempt to make EFI honor board_get_usable_ram_top() was -rejected. So, this patch will need to be replicated for any board that -implements board_get_usable_ram_top(). - -Fixes: aa909462d018 ("efi_loader: efi_allocate_pages is too restrictive") -Signed-off-by: Stephen Warren ---- -v3: -- Use shift not divide for page count calculation. -- Enhance ifdef to avoid EFI references from SPL builds. -v2: -- Don't hard-code EFI page size. -- Register RAM as a boot services data rather than reserved. ---- - arch/arm/mach-tegra/board2.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c -index 421a71b3014d..12257a42b51b 100644 ---- a/arch/arm/mach-tegra/board2.c -+++ b/arch/arm/mach-tegra/board2.c -@@ -6,6 +6,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -210,6 +211,19 @@ int board_early_init_f(void) - - int board_late_init(void) - { -+#if CONFIG_IS_ENABLED(EFI_LOADER) -+ if (gd->bd->bi_dram[1].start) { -+ /* -+ * Only bank 0 is below board_get_usable_ram_top(), so all of -+ * bank 1 is not mapped by the U-Boot MMU configuration, and so -+ * we must prevent EFI from using it. -+ */ -+ efi_add_memory_map(gd->bd->bi_dram[1].start, -+ gd->bd->bi_dram[1].size >> EFI_PAGE_SHIFT, -+ EFI_BOOT_SERVICES_DATA, false); -+ } -+#endif -+ - #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) - if (tegra_cpu_is_non_secure()) { - printf("CPU is in NS mode\n"); - diff --git a/u-boot-2018.09.tar.bz2 b/u-boot-2020.07.tar.bz2 similarity index 56% rename from u-boot-2018.09.tar.bz2 rename to u-boot-2020.07.tar.bz2 index 3814bb9337e8808871a8ab00c2578bd41f6f808c..c68c5a6150f615df3e492db3740f907cb315d521 100644 Binary files a/u-boot-2018.09.tar.bz2 and b/u-boot-2020.07.tar.bz2 differ diff --git a/uboot-tools.spec b/uboot-tools.spec index 75457c0d8cdd02dd282d7351ebc053214bebfc55..80649c89a1fbd96a199235f8ef2fd018ce4b19db 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,6 +1,8 @@ +%global _default_patch_fuzz 2 + Name: uboot-tools -Version: 2018.09 -Release: 9 +Version: 2020.07 +Release: 1 Summary: tools for U-Boot License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -10,21 +12,29 @@ Source2: arm-chromebooks Source3: aarch64-boards Source4: aarch64-chromebooks Source5: 10-devicetree.install -Patch0001: usb-kbd-fixes.patch -Patch0002: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch -Patch0003: rockchip-make_fit_atf-fix-warning-unit_address_vs_reg.patch -Patch0004: rockchip-make_fit_atf-use-elf-entry-point.patch -Patch0005: rk3399-Rock960-board-support.patch -Patch0006: dragonboard-fixes.patch -Patch0007: tegra-efi_loader-simplify-ifdefs.patch -Patch0008: sunxi-DT-A64-add-Pine64-LTS-support.patch + +Patch0001: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch +# Board fixes and enablement +Patch0002: usb-kbd-fixes.patch +Patch0003: dragonboard-fixes.patch +# Tegra improvements +Patch0004: arm-tegra-define-fdtfile-option-for-distro-boot.patch +Patch0005: arm-add-BOOTENV_EFI_SET_FDTFILE_FALLBACK-for-tegra186-be.patch +# AllWinner improvements +Patch0006: AllWinner-Pine64-bits.patch +# Rockchips improvements +Patch0007: arm-rk3399-enable-rng-on-rock960-and-firefly3399.patch +Patch0008: rockchip-Pinebook-Pro-Fixes.patch +# RPi4 +Patch0009: USB-host-support-for-Raspberry-Pi-4-board-64-bit.patch +Patch0010: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch BuildRequires: bc dtc gcc make flex bison git-core openssl-devel gdb -BuildRequires: python-unversioned-command python2-devel python2-setuptools +BuildRequires: python-unversioned-command python3-devel python3-setuptools BuildRequires: python3-libfdt python3-pyelftools SDL-devel swig # this required when /usr/bin/python link to python3 BuildRequires: python3-devel -%ifarch %{arm} aarch64 +%ifarch %{arm} aarch64 BuildRequires: vboot-utils %endif %ifarch aarch64 @@ -32,6 +42,10 @@ BuildRequires: arm-trusted-firmware-armv8 %endif Requires: dtc systemd +%ifarch aarch64 %{arm} +Obsoletes: uboot-images-elf < 2019.07 +Provides: uboot-images-elf >= 2019.07 +%endif %description This package includes the mkimage program, which allows generation of U-Boot @@ -62,8 +76,8 @@ u-boot bootloader images for armv7 boards %package -n uboot-images-elf Summary: u-boot bootloader images for armv7 boards Requires: uboot-tools -Obsoletes: uboot-images-qemu -Provides: uboot-images-qemu +Obsoletes: uboot-images-qemu < %{version}-%{release} +Provides: uboot-images-qemu = %{version}-%{release} %description -n uboot-images-elf u-boot bootloader ELF images for use with qemu and other platforms @@ -72,24 +86,10 @@ u-boot bootloader ELF images for use with qemu and other platforms %package_help %prep -%setup -q -n u-boot-%{version} - -git init -git config --global gc.auto 0 -git config user.email "noone@example.com" -git config user.name "no one" -git add . -git commit -a -q -m "%{version} baseline" -git am %{patches} 2020.07-1 +- Upgrade to 2020.07-1 + * Fri Jun 19 2020 zhujunhao - 2018.09-9 - drop python2 requires @@ -320,4 +279,3 @@ cp -p board/warp7/README builds/docs/README.warp7 * Sat Oct 12 2019 openEuler Buildteam - 2018.09-3 - Package init - diff --git a/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch b/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch new file mode 100644 index 0000000000000000000000000000000000000000..c5ecb618bcbf83eafe3b23535acfe57246e0636c --- /dev/null +++ b/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch @@ -0,0 +1,83 @@ +From 67c05a07288ef24b3ac9d013f35a0868d26a34c7 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 18 Jun 2019 11:51:21 +0100 +Subject: [PATCH 1/2] distro: load FDT from any partition on boot device + +In the EFI_LOADER boot path, we were only checking the FAT partition +containing the EFI payload for dtb files. But this is somewhat of a +fiction. In reality there will be one small (V)FAT partition containing +grub (or whatever the payload may be), and a second boot partition +containing kernel/initrd/fdt (typically ext4). It is this second +partition where we should be looking for a FDT to load. + +So instead scan all the partitions of the disk containing the EFI +payload. This matches where grub looks for kernel/initrd (barring +custom grub.cfg, in which case the user can use grub's 'devicetree' +command to load the correct FDT). + +The other option is somehow passing the ${fdtfile} to grub so that it +can load the FDT based on selected kernel version location (which grub +knows) and SoC/board specific ${fdtfile} (which grub does not know). + +Signed-off-by: Rob Clark +Signed-off-by: Peter Robinson +--- + include/config_distro_bootcmd.h | 34 ++++++++++++++++++++++----------- + 1 file changed, 23 insertions(+), 11 deletions(-) + +diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h +index 4993303f4d..f4b3b62fca 100644 +--- a/include/config_distro_bootcmd.h ++++ b/include/config_distro_bootcmd.h +@@ -138,25 +138,37 @@ + "fi\0" \ + \ + "load_efi_dtb=" \ +- "load ${devtype} ${devnum}:${distro_bootpart} " \ +- "${fdt_addr_r} ${prefix}${efi_fdtfile}\0" \ ++ "load ${devtype} ${devnum}:${dtb_devp} " \ ++ "${fdt_addr_r} ${prefix}${efi_fdtfile} && " \ ++ "run boot_efi_binary\0" \ + \ + "efi_dtb_prefixes=/ /dtb/ /dtb/current/\0" \ +- "scan_dev_for_efi=" \ ++ "scan_dev_for_dtb=" \ + "setenv efi_fdtfile ${fdtfile}; " \ + BOOTENV_EFI_SET_FDTFILE_FALLBACK \ +- "for prefix in ${efi_dtb_prefixes}; do " \ +- "if test -e ${devtype} " \ +- "${devnum}:${distro_bootpart} " \ +- "${prefix}${efi_fdtfile}; then " \ +- "run load_efi_dtb; " \ +- "fi;" \ +- "done;" \ ++ "part list ${devtype} ${devnum} dtb_devplist; " \ ++ "env exists dtb_devplist || setenv dtb_devplist " \ ++ "${distro_bootpart}; " \ ++ "for dtb_devp in ${dtb_devplist}; do " \ ++ "for prefix in ${efi_dtb_prefixes}; do " \ ++ "if test -e ${devtype} " \ ++ "${devnum}:${dtb_devp} " \ ++ "${prefix}${efi_fdtfile};"\ ++ " then " \ ++ "echo Found DTB ${devtype} " \ ++ "${devnum}:${dtb_devp} " \ ++ "${prefix}${efi_fdtfile};"\ ++ "run load_efi_dtb; " \ ++ "fi;" \ ++ "done; " \ ++ "done; " \ ++ "run boot_efi_binary\0" \ ++ "scan_dev_for_efi=" \ + "if test -e ${devtype} ${devnum}:${distro_bootpart} " \ + "efi/boot/"BOOTEFI_NAME"; then " \ + "echo Found EFI removable media binary " \ + "efi/boot/"BOOTEFI_NAME"; " \ +- "run boot_efi_binary; " \ ++ "run scan_dev_for_dtb; " \ + "echo EFI LOAD FAILED: continuing...; " \ + "fi; " \ + "setenv efi_fdtfile\0" +-- +2.21.0 + diff --git a/usb-kbd-fixes.patch b/usb-kbd-fixes.patch index 095029a49aeb5884f4dd01871a1e96af05670c83..fb6a0e08eea2cfd685bc2e71fdf2db3ebe2042b9 100644 --- a/usb-kbd-fixes.patch +++ b/usb-kbd-fixes.patch @@ -1,19 +1,19 @@ -From 1a8fa60aedff8a2368ac357a51dc15357065fabe Mon Sep 17 00:00:00 2001 +From a49845f198af088c4e5e0019edbf519344d78c97 Mon Sep 17 00:00:00 2001 From: Peter Robinson -Date: Tue, 5 Dec 2017 00:11:54 +0000 -Subject: [PATCH 3/5] usb kbd fixes +Date: Tue, 4 Dec 2018 15:29:14 +0000 +Subject: [PATCH] usb kbd fixes Signed-off-by: Peter Robinson --- - common/usb_kbd.c | 66 +++++++++++++++++++++++++++++++++++++++++-------------- + common/usb_kbd.c | 66 +++++++++++++++++++++++++++++++++++------------ include/console.h | 2 -- 2 files changed, 50 insertions(+), 18 deletions(-) diff --git a/common/usb_kbd.c b/common/usb_kbd.c -index 8cbdba6ac2..82ad93f6ca 100644 +index 020f0d4117f..47674ce4458 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c -@@ -516,25 +516,59 @@ static int probe_usb_keyboard(struct usb_device *dev) +@@ -518,25 +518,59 @@ static int probe_usb_keyboard(struct usb_device *dev) return error; stdinname = env_get("stdin"); @@ -87,8 +87,8 @@ index 8cbdba6ac2..82ad93f6ca 100644 +#endif } - #ifndef CONFIG_DM_USB -@@ -640,7 +674,7 @@ static int usb_kbd_remove(struct udevice *dev) + #if !CONFIG_IS_ENABLED(DM_USB) +@@ -642,7 +676,7 @@ static int usb_kbd_remove(struct udevice *dev) return 0; err: @@ -98,10 +98,10 @@ index 8cbdba6ac2..82ad93f6ca 100644 } diff --git a/include/console.h b/include/console.h -index cea29ed6dc..7dfd36d7d1 100644 +index e935c601f12..6382ec8e0d6 100644 --- a/include/console.h +++ b/include/console.h -@@ -57,8 +57,6 @@ int console_announce_r(void); +@@ -56,8 +56,6 @@ int console_announce_r(void); /* * CONSOLE multiplexing. */ @@ -111,5 +111,5 @@ index cea29ed6dc..7dfd36d7d1 100644 #endif -- -2.14.3 +2.19.2