# VerilogCodingStyle

**Repository Path**: sspg/VerilogCodingStyle

## Basic Information

- **Project Name**: VerilogCodingStyle
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2021-01-05
- **Last Updated**: 2021-01-05

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

This is a coding style document for SystemVerilog. It is used for hardware design, not for verification. If you like it, please give us a star. The whole document is shown in [Verilog Coding Style](https://verilogcodingstyle.readthedocs.io/en/latest/index.html).