# hdl

**Repository Path**: tonyhan2017/hdl

## Basic Information

- **Project Name**: hdl
- **Description**: 在ADI github clone的，ADI的用FPGA驱动的参考例程。
再次备份防止哪天github又打不开。
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 3
- **Created**: 2019-04-24
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

#HDL Reference Designs

Analog Devices HDL libraries and projects

###Tools version:
- **Xilinx** : [Vivado 2014.4.1]
- **Altera** : [Quartus 15.0]

###Documentation and support

For first time users, it is **highly recommended** to go through our [HDL user guide].

For support please visit our [FPGA Reference Designs Support Community] on EngineerZone.

[Vivado 2014.4.1]:http://www.xilinx.com/content/xilinx/en/downloadNav/vivado-design-tools/2014-4.html
[Quartus 15.0]:http://dl.altera.com/15.0/?edition=subscription
[HDL user guide]:http://wiki.analog.com/resources/fpga/docs/hdl
[FPGA Reference Designs Support Community]:http://ez.analog.com/community/fpga