# F103-XLINK

**Repository Path**: upw/f103-xlink

## Basic Information

- **Project Name**: F103-XLINK
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2026-10-05
- **Last Updated**: 2026-11-02

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# JLINK-OB for STM32F103CB — MDK Project (Work in Progress)

Reproducing the SEGGER J-Link OB firmware behavior on a Wildfire STM32F103C8T6
core board (which uses an STM32F103CB chip — 64 KB Flash, 20 KB RAM).

## Topology

```
[Host: JLinkExe / J-Flash]                [Target: STM32F103C8]
                                            ┌──────────────┐
   WinUSB (WinUSB driver auto-load)   <--->  │  PB14 SWDIO  │
   Bulk OUT (EP 0x01, 64 B max)             │  PB13 SWCLK  │
   Bulk IN  (EP 0x81, 64 B max)             │  PA15 USB-PU*│
   Vendor requests (EMUCmd / EMUInfo)       │  PB15 TDI    │
                                            │  PB0  nRST   │
                                            │  PA0  VTref  │
   USB DP / DM  <----------------------->    │  PA11/PA12   │
   (PA11/PA12 from 103 USB FS PHY)          │   HSE 8MHz   │
                                            │  HSE→PLL 72M │
                                            └──────────────┘
```

## Source layout (D:\Project\JlinkFW\new\jlink_f103_mdK\)

```
Drivers/
  CMSIS/                            — Cortex-M3 CMSIS core + STM32F1xx device headers
  STM32F1xx_HAL_Driver/             — ST HAL (RCC/GPIO/USB-PCD/ADC/...) src + Inc
Startup/startup_stm32f103xb.s       — copied from wildfire MDK-ARM/ start-up
RT-Thread/                          — RT-Thread Nano kernel (subset of src/)
CherryUSB/                          — CherryUSB device core + fsdev port
jlink_proto/                        — protocol parser (SWD/JTAG/CoreSight/cmd/RV/RTT/flash)
port/
  jlink_io/   stm32f103_jlink_io.*  — GPIO bit-bang IO layer
  winusb/     cherryusb_glue.c      — USB IRQ + clock glue
              usbd_winusb.c         — WinUSB bulk class driver
User/main.c                         — entry, scheduler, SystemClock
Project.uvprojx                     — MDK project file (AC5/AC6)
jlink_f103cb.sct                    — scatter-loading file (64K Flash / 20K RAM)
```

## IO Reverse-Engineering (from JLINK_OB_STLINK_STM32F103C8.hex)

Decompiling V21 of ST-LINK V2-1 to extract its SWD bit-banger at `0x080083F8`
found: `lsls r5, r2, #13; lsls r6, r2, #14; ldr r7, =0x40010C00` — pointing
to the **GPIOB_CRL/CRH region**, indicating:

- `r2=0` → `lsls #13` → bit 13 → **PB13 = SWDIO**
- `r2=1` → `lsls #14` → bit 14 → **PB14 = SWCLK**
- The `lsls r6` (output enable) bit 13 again = same SWDIO line
- `0x40010C00` is `GPIOB` base, `CRL/CRH` for config

> ⚠️ **Note (2026-09-23):** this V21 ST-LINK hex analysis (PB13=SWDIO,
> PB14=SWCLK) **differs from the implemented firmware**. The current
> implementation follows `stm32f103_jlink_io.h` (from disassembling
> `JLINK_OB_STLINK_STM32F103C8.hex` @ `0x80076DE`): **PB14 = SWDIO,
> PB13 = SWCLK**, PB12 = SWDIO_OE. Physical wiring to a target must use
> the implemented mapping (probe PB14 → target PA13/SWDIO, probe PB13 →
> target PA14/SWCLK). See `scripts/check_wiring.jlink` for a wiring test.

## Build

1. Open `Project.uvprojx` in Keil MDK v5.36+ (AC5 or AC6 toolchain).
2. Compile (F7) — produces `Objects\jlink_ob_f103.axf` (~30 KB).
3. Program with local USB J-Link (S/N 38465217) or ST-Link V2.

## Current Status

- HAL + CMSIS + jlink_proto library in place
- CherryUSB core + fsdev port extracted, vendor-class driver scaffolded
- RT-Thread Nano: in progress (rtthread-src clone ongoing)
- MDK project file: scaffolded, will refine after RT-Thread sources are placed
- WinUSB bulk: descriptors in place but tested only on host deserialisation layer

This work is an **independent sub-project** inside `D:\Project\JlinkFW\new\` and
must **not** be mixed into the `D:\Project\JlinkFW\c_reimpl` V11 reverse-engineering
project.

## Known Constraints

- STM32F103CB has 64 KB Flash / 20 KB RAM. jlink_proto static data + CherryUSB
  + RT-Thread scheduler + WinUSB stack will fit, but we're tight. Final size
  to be measured at first compile.
- USB FS (12 Mbps) requires 48 MHz clock from PLL — already configured.
- SWD bit-bang protocol needs tuning — line reset + jtag→swd select sequence
  lives in `stm32f103_jlink_io.c`.