# 平头哥调试协议说明 **Repository Path**: uyami/T-HEAD_DEBUG ## Basic Information - **Project Name**: 平头哥调试协议说明 - **Description**: No description available - **Primary Language**: Unknown - **License**: Not specified - **Default Branch**: master - **Homepage**: None - **GVP Project**: No ## Statistics - **Stars**: 1 - **Forks**: 0 - **Created**: 2024-05-18 - **Last Updated**: 2025-01-21 ## Categories & Tags **Categories**: Uncategorized **Tags**: None ## README ## 平头哥(T-Head) RISCV调试协议说明 平头哥有些平台的调试协议与RISCV的DTM不同,有些则兼容RISCV的DTM模块.详细说明可以参考芯片手册. 针对全志F133(D1s),则使用其自带的调试协议(针对多核优化?),详细协议代码可参考openc910的软核代码(非c906) ### 以下是简略说明 协议是以ir_len=16,进行,ir值的每位表示如下 |15 |14|13|12-8 | | core_id | |R/W|GO|EX|index[4:0]|bank_sel[7:5|000|cpu_sel| R/W: 读写,1:读 GO : 运行标识,1:会退出调试模式,需要hcr & 0x8000==0,0:则不会退出调试模式, 例如 ir_go_ex 则会退出调试模式,使用 ir_go_nex, 则不会退出调试模式 EX : 未知 core_id: 核心id,全志F133单单使用0作为核心 index: bank0 下 ID_NUM = 5'd2; HAD_ID register OTC_NUM = 5'd3; MBCA_NUM = 5'd4; 内存断点A MBCB_NUM = 5'd5; 内存断点B PCFIFO_NUM = 5'd6; BABA_NUM = 5'd7; 断点A的基地址 BABB_NUM = 5'd8; 断点B的基地址 BAMA_NUM = 5'd9; 断点A的MASK BAMB_NUM = 5'd10; 断点B的MASK BYPASS_NUM = 5'd12; HCR_NUM = 5'd13; HAD控制 HSR_NUM = 5'd14; HAD状态 WBBR_NUM = 5'd17; 读写数据使用到的寄存器 PSR_NUM = 5'd18; PC_NUM = 5'd19; IR_NUM = 5'd20; 执行指令代码使用到的寄存器? CSR_NUM = 5'd21; DADDR_NUM = 5'd24; DDATA_NUM = 5'd25; bank2 EVENT_OE_NUM = 5'd2; EVENT_IE_NUM = 5'd3; DBGFIFO_NUM = 5'd4; PIPEFIFO_NUM = 5'd5; PIPESEL_NUM = 5'd6; bank1 MBIR_NUM = 5'd27; ### 有关id的说明 (默认JTAG的IDCODE输出) 值为0x08052b43 //========================================================== // HAD_ID register //========================================================== // +-------+-----+---------+----+----+-------+------+-----+-----+ // | 31:28 |27:26| 25:18 | 17 | 16 | 15:12 | 11:8 | 7:4 | 3:0 | // +-------+-----+---------+----+----+-------+------+-----+-----+ // | | | | | | | | // | | | | | | | +--- ID_VERSION = 3 // | | | | | | +--------- HAD_VERSION = 4 // | | | | | +-------------- HAD_REVISION = b // | | | | +---------------------- BKPT_NUM = 2 // | | | +----------------------------- DDC = 1 // | | +---------------------------------- BANK1 = 0 // | +--------------------------------------- CPU Inst. Arch = 2 // +---------------------------------------------- JTAG InterfaceType = 0 ### 有关调试模块初始化 重置jtag, write_reg event_outen 0x3 32 write_reg event_inen 0x3 32 write_reg hcr 0x8000 32 0x8000为进入调试模块控制 write_reg hcr 0x0 32 并不会退出,根据IR的GO标识进行退出 write_reg event_outen 0 32 关闭 其他有关说明参考f133.cfg 或者参考openC910的源代码