# riscv-mcu

**Repository Path**: virtual-computer/cpu-v

## Basic Information

- **Project Name**: riscv-mcu
- **Description**: 基于Digital数字电路仿真软件,构建支持简易指令集的CPU以及简单的外设电路仿真。  
目标能够支持系统的引导、启动、运行、中断处理、外设控制等功能。

本项目用于辅助学习CPU结构/数字电路设计，微机组成原理，汇编/C语言开发，嵌入式开发等技术入门。
- **Primary Language**: C
- **License**: Apache-2.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 37
- **Forks**: 11
- **Created**: 2024-08-03
- **Last Updated**: 2025-09-27

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# riscv-mcu 
[中文](README_zh.md)

## Directory Introduction

1. **netlist**: there are CPU designs based on the digital software, created through wiring methods, along with the corresponding boot and test codes. This part is finalized and will no longer be updated. For specific introductions, see: [riscv-digital](doc/netlist.md).
2. **verilog**: there is RISC-V CPU code developed in Verilog, which is continuously being updated.
3. **digital_soc**: there is a SoC built with CPU modules written in Verilog using the digital software, which can be run through digital simulation.
3. **fpga_soc**: there is a SoC constructed with RISC-V CPU modules based on FPGA. This has not yet started, with the goal being to run the CPU IP implemented in Verilog on an FPGA development board.

#### digital_soc Introduction

**1. Generating Bootloader and Test Program Hex Files** 

The bootloader and test program code are located in the digital_soc/src directory. To generate the hex files for the bootloader and test program, execute the following commands within that directory:  

```shell 
    make; python3 ./mkhex.py
```  

**2. Verilog Simulation**  
For Verilog simulation, follow these steps:  
* Navigate to the verilog directory.
* Execute the following command to build the simulation:  

```shell
./make.bat digital_soc 
```  
* After the build is complete, run the simulation waveform viewer using:
``` shell
gtkwave.exe ./digital_soc.vcd 
```
This will allow you to view the simulation waveforms generated by the Verilog simulation.

**3. Digital Simulation**

To perform digital simulation, follow these steps:

* Open the Digital software.
* Load the digital_soc/digital/digital_soc.dig file.
* Before running the simulation, you need to configure the riscvmcu component:
    * Right-click on the riscvmcu component.
    * In the context menu, select the Options tab.
    * Locate the iverilog option.
    * Modify the dependency path to match the corresponding path on your local machine.
* Save the changes and close the configuration window.
* Run the simulation.