# Verilog-Practice_HDLbits

**Repository Path**: wang_jinruimayun/verilog-practice_-hdlbits

## Basic Information

- **Project Name**: Verilog-Practice_HDLbits
- **Description**: HDLbits网站的在线verilog仿真编辑练习
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 1
- **Created**: 2020-09-14
- **Last Updated**: 2024-02-25

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Verilog-Practice

[![996.icu](https://img.shields.io/badge/link-996.icu-red.svg)](https://996.icu) ![visitors](https://visitor-badge.glitch.me/badge?page_id=xiaopi-verilog-practice)

There are some [HDLBits website][1] practices. And all of them have been verified. I really hope that my practices can help you to realize how Verilog works.

2020.4.22 - 6:09:54: All of the problems are **done**. 

And there is my [blog][2].

At the end, life is fantastic bro.

[1]: https://hdlbits.01xz.net/wiki/Main_Page
[2]: https://blog.began.me