# vTbgen

**Repository Path**: wangchaosun/vTbgen

## Basic Information

- **Project Name**: vTbgen
- **Description**: Verilog/SystemVerilog Testbench generator
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-12-08
- **Last Updated**: 2025-12-08

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# vTbgen

reference: https://github.com/truecrab/VSCode_Extension_Verilog

## usage

```c
python vTbgen.py xxx.v
```