# MMCM_Dynamic-Reconfiguration

**Repository Path**: wei_celebrates/MMCM_Dynamic-Reconfiguration

## Basic Information

- **Project Name**: MMCM_Dynamic-Reconfiguration
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-03-05
- **Last Updated**: 2025-03-05

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# MMCM_Dynamic-Reconfiguration
This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock manager (MMCM) for the Xilinx® 7 series FPGA  
Useage  
  1.Move into work   
  2.Open vivado  
  3.In the TCL console: source ../scripts/readout_mmcmRC.tcl  
  4.Generate Bitstream and download it into the KC705 board  
  5.Make sure your computer connects the board correctly  
  6.Move into directory software  
  7.In the terminal:python mmcm_top.py