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whik 提交于 2019-08-23 19:31 . 新建串口工程
Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o D:/FPGA_Study/Xilinx/UART_Demo_Verilog/uart_tx_demo_tb_isim_beh.exe -prj D:/FPGA_Study/Xilinx/UART_Demo_Verilog/uart_tx_demo_tb_beh.prj work.uart_tx_demo_tb work.glbl
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Analyzing Verilog file "D:/FPGA_Study/Xilinx/UART_Demo_Verilog/HDL/uart_tx_8bit.v" into library work
Analyzing Verilog file "D:/FPGA_Study/Xilinx/UART_Demo_Verilog/HDL/uart_tx_demo.v" into library work
Analyzing Verilog file "D:/FPGA_Study/Xilinx/UART_Demo_Verilog/HDL/uart_tx_demo_tb.v" into library work
Analyzing Verilog file "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Compiling module uart_tx_8bit
Compiling module uart_tx_demo
Compiling module uart_tx_demo_tb
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
WARNING:Simulator - Unable to copy libPortabilityNOSH.dll to the simulation executable directory: boost::filesystem::copy_file: 系统找不到指定的路径。, "isim\uart_tx_demo_tb_isim_beh.exe.sim\libPortability.dll".
Compiled 4 Verilog Units
Built simulation executable D:/FPGA_Study/Xilinx/UART_Demo_Verilog/uart_tx_demo_tb_isim_beh.exe
Fuse Memory Usage: 27900 KB
Fuse CPU Usage: 781 ms
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