ISim log file
Running: D:\FPGA_Study\Xilinx\UART_Demo_Verilog\uart_tx_demo_tb_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb D:/FPGA_Study/Xilinx/UART_Demo_Verilog/uart_tx_demo_tb_isim_beh.wdb 
ISim P.20131013 (signature 0x7708f090)
This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# run 1s
Stopped at time : 142192300500 ps : File "D:/FPGA_Study/Xilinx/UART_Demo_Verilog/HDL/uart_tx_demo.v" Line 28