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top_level

Description

verilog顶层文件,该项目可以调用JK触发器,奇偶校验位和8位寄存器模块。

Software Architecture

Software architecture description

Installation

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Instructions

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  2. Create Feat_xxx branch
  3. Commit your code
  4. Create Pull Request

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verilog顶层文件,该项目可以调用JK触发器,奇偶校验位和8位寄存器模块。 expand collapse
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