# yarvi

**Repository Path**: wqqwin/yarvi

## Basic Information

- **Project Name**: yarvi
- **Description**: Yet Another RISC-V Implementation
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2020-08-09
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# YARVI - Yet Another RISC-V Implementation #

Here is a very simple RISC-V RV32I implementation.  The point is
clearity and correctness, not performance (that will follow).

The included example has been tested mostly against the wonderful $149
Arrow BeMicro CV A9, but the core itself is completely vendor neutral.

[![tip for next commit](http://prime4commit.com/projects/274.svg)](http://prime4commit.com/projects/274)