# NTHU-ICLAB

**Repository Path**: ynxing/NTHU-ICLAB

## Basic Information

- **Project Name**: NTHU-ICLAB
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: main
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-02-19
- **Last Updated**: 2025-02-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# NTHU EE4292 IC Design Laboratory (ICLab)
## Labs

<table border=2 class="dataframe">
    </thead>
        <tr>
            <th>#</th>
            <th>Content</th>
        </tr>
    </thead>
    <tbody>
        <tr>
            <th>lab01</th>
            <th>Workstation</th>
        </tr>
        <tr>
            <th>lab02</th>
            <th>NC-Verlilog</th>
        </tr>
        <tr>
            <th>lab03</th>
            <th>Testbench Debugging and Writing</th>
        </tr>
        <tr>
            <th>lab04</th>
            <th>Verdi & Finite State Machine</th>
        </tr>
        <tr>
            <th>lab05</th>
            <th>RTL Simulation and Debugging</th>
        </tr>
        <tr>
            <th>lab06</th>
            <th>Coding for synthesis and optimization</th>
        </tr>
        <tr>
            <th>lab07</th>
            <th>Line-based Image Processing</th>
        </tr>
        <tr>
            <th>lab08</th>
            <th>Coding for Synthesis</th>
        </tr>
        <tr>
            <th>lab09</th>
            <th>Conformal check with LEC & ECO-Integer Division</th>
        </tr>
        <tr>
            <th>lab10</th>
            <th>APR Flow with IC Compiler (Design Setup and Floorplan)</th>
        </tr>
        <tr>
            <th>lab11</th>
            <th>APR Flow with IC Compiler (Powerplan and Placement)</th>
        </tr>
        <tr>
            <th>lab12</th>
            <th>APR Flow with IC Compiler
(CTS, Routing, Verification and Power Analysis)</th>
        </tr>
    </tbody>
</table>

## Homework

<table border=2 class="dataframe">
    </thead>
        <tr>
            <th>#</th>
            <th>Content</th>
        </tr>
    </thead>
    <tbody>
        <tr>
            <th>HW1</th>
            <th>Three-input Raster Operations (ROP3) for Computer Graphics</th>
        </tr>
        <tr>
            <th>HW2</th>
            <th>Enigma</th>
        </tr>
        <tr>
            <th>HW3</th>
            <th>Logic Synthesis for Enigma</th>
        </tr>
        <tr>
            <th>HW3.1</th>
            <th>Logic Synthesis for ROP3</th>
        </tr>
        <tr>
            <th>HW4</th>
            <th>QR Code Decoder with Error Correction</th>
        </tr>
        <tr>
            <th>HW5</th>
            <th>Digit classification using CNN</th>
        </tr>
    </tbody>
</table>

## Final Project
Implement Edge Detection on Images using HOG Algorithm with Some Noise Filters