# VLSI-final-new

**Repository Path**: ynxing/vlsi-final-new

## Basic Information

- **Project Name**: VLSI-final-new
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2026-01-19
- **Last Updated**: 2026-01-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# NCKU-VLSI-System-Design    
This is NCKU VLSI System Design (VSD) Labs and Project of Jun-An, Chen (N26124989)  
Welcome for disscussion, but copying is not tolerant.  
## LAB1: Pipeline RISC-V CPU design  
### (Finished)  
## LAB2: AXI-Bus built-in CPU system  
### (Finished)  
## LAB3: Asynchronous Real-world system  
### (Finished)  



##### Copyright © 2023 VCSDL Jun-An, Chen. All rights reserved.