diff --git a/components/controller/rf_phy_driver.h b/components/controller/rf_phy_driver.h index 79449bd0d9faa03788b37af6af535fd3baf43266..b09f10eceb36d06f7879a4a8bec38710856a9d67 100755 --- a/components/controller/rf_phy_driver.h +++ b/components/controller/rf_phy_driver.h @@ -270,6 +270,9 @@ extern volatile uint32_t g_dtmAccessCode ; #define RF_PHY_DTM_MANUL_MAX_GAIN 0x08 #define RF_PHY_DTM_MANUL_ALL 0xFF + +#define RF_PHY_DEFAULT_XTAL_CAP 0x09 +#define RF_PHY_DEFAULT_FREQOFF RF_PHY_FREQ_FOFF_00KHZ /******************************************************************************* * FUNCION DEFINE */ @@ -295,74 +298,18 @@ uint8_t rf_phy_direct_test_ate(uint32_t cmdWord, uint8_t regPatchNum, uint32 void rf_phy_dtm_zigbee_pkt_gen(void); -/************************************************************************************** - * @fn rf_phy_dtm_ext_rx_demod_burst - * - * @brief This function process for rf phy direct test, test mode interup - * - * input parameters - * - * @param rfChnIdx : rf channel = 2402+(rfChnIdx<<1) - * rfFoff : rf freq offset = rfFoff*4KHz - * pktLength : pkt length(Byte) - * rxWindow : rx demod window length(us) - * rxTimeOut : rx on time (ms) - * - * output parameters - * - * @param rxEstFoff : rx demod estimated frequency offset - * rxEstRssi : rx demod estimated rssi - * rxEstCarrSens : rx demod estimated carrier sense - * rxPktNum : rx demod received pkt number - * - * @return none - */ +void rf_phy_dtm_ext_tx_singleTone(uint8_t txPower, uint8_t rfChnIdx,uint8_t xtal_cap,int8_t rfFoff ,uint32 testTimeUs); +void rf_phy_dtm_ext_tx_modulation(uint8_t txPower, uint8_t rfChnIdx,uint8_t xtal_cap,int8_t rfFoff ,uint8_t pktType,uint32 testTimeUs); +void rf_phy_dtm_ext_tx_mod_burst(uint8_t txPower, uint8_t rfChnIdx,uint8_t xtal_cap,int8_t rfFoff , + uint8_t pktType, uint8_t pktLength,uint32 txPktNum,uint32 txPktIntv); void rf_phy_dtm_ext_rx_demod_burst(uint8_t rfChnIdx,int8_t rfFoff,uint8_t xtal_cap,uint8_t pktLength,uint32 rxTimeOut,uint32 rxWindow, int16_t* rxEstFoff,uint8_t* rxEstRssi,uint8_t* rxEstCarrSens,uint16_t* rxPktNum); - -/************************************************************************************** - * @fn rf_phy_dtm_ext_tx_mt_burst - * - * @brief This function process for rf phy direct test, test mode interup - * - * input parameters - * - * @param txPower : rf tx power - * rfChnIdx : rf channel = 2402+(rfChnIdx<<1) - * rfFoff : rf freq offset = rfFoff*4KHz - * pktType : modulaiton data type, 0: prbs9, 1: 1111000: 2 10101010 - * pktLength : pkt length(Byte) - * - * txPktNum : burst pkt tx number - * txPktIntv : txPkt intv,0 txPkt intv is pkt interval = ceil((L+249)/625) * 625 - * - * output parameters - * - * @param none - * - * @return none - */ -void rf_phy_dtm_ext_tx_mod_burst(uint8_t txPower, uint8_t rfChnIdx,uint8_t xtal_cap,int8_t rfFoff , +void rf_phy_dtm_tx_singleTone(uint8_t rfPhyPktFmt,uint8_t txPower, uint8_t rfChnIdx,uint8_t xtal_cap,int8_t rfFoff ,uint32 testTimeUs); +void rf_phy_dtm_tx_modulation(uint8_t rfPhyPktFmt,uint8_t txPower, uint8_t rfChnIdx,uint8_t xtal_cap,int8_t rfFoff ,uint8_t pktType,uint32 testTimeUs); +void rf_phy_dtm_tx_mod_burst(uint8_t rfPhyPktFmt,uint8_t txPower, uint8_t rfChnIdx,uint8_t xtal_cap,int8_t rfFoff , uint8_t pktType, uint8_t pktLength,uint32 txPktNum,uint32 txPktIntv); +void rf_phy_dtm_rx_demod_burst(uint8_t rfPhyPktFmt,uint8_t rfChnIdx,int8_t rfFoff,uint8_t xtal_cap,uint8_t pktLength,uint32 rxTimeOut,uint32 rxWindow, + int16_t* rxEstFoff,uint8_t* rxEstRssi,uint8_t* rxEstCarrSens,uint16_t* rxPktNum); -/************************************************************************************** - * @fn rf_phy_dtm_ext_tx_singleTone - * - * @brief This function process for rf phy direct test, test mode interup - * - * input parameters - * - * @param txPower : rf tx power - * rfChnIdx : rf channel = 2402+(rfChnIdx<<1) - * rfFoff : rf freq offset = rfFoff*4KHz - * testTimeUs : test loop active time(ms) - * - * output parameters - * - * @param none - * - * @return none - */ -void rf_phy_dtm_ext_tx_singleTone(uint8_t txPower, uint8_t rfChnIdx,uint8_t xtal_cap,int8_t rfFoff ,uint32 testTimeUs); - +void rf_phy_dtm_ext_acc_code_set(uint32 accCode); #endif diff --git a/components/driver/inc/flash_phy6220.h b/components/driver/inc/flash_phy6220.h new file mode 100644 index 0000000000000000000000000000000000000000..61ac26b391d1c790b12a29e7c36c188a7074d253 --- /dev/null +++ b/components/driver/inc/flash_phy6220.h @@ -0,0 +1,163 @@ +/************************************************************************************************** + + Phyplus Microelectronics Limited confidential and proprietary. + All rights reserved. + + IMPORTANT: All rights of this software belong to Phyplus Microelectronics + Limited ("Phyplus"). Your use of this Software is limited to those + specific rights granted under the terms of the business contract, the + confidential agreement, the non-disclosure agreement and any other forms + of agreements as a customer or a partner of Phyplus. You may not use this + Software unless you agree to abide by the terms of these agreements. + You acknowledge that the Software may not be modified, copied, + distributed or disclosed unless embedded on a Phyplus Bluetooth Low Energy + (BLE) integrated circuit, either as a product or is integrated into your + products. Other than for the aforementioned purposes, you may not use, + reproduce, copy, prepare derivative works of, modify, distribute, perform, + display or sell this Software and/or its documentation for any purposes. + + YOU FURTHER ACKNOWLEDGE AND AGREE THAT THE SOFTWARE AND DOCUMENTATION ARE + PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, + INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE, + NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL + PHYPLUS OR ITS SUBSIDIARIES BE LIABLE OR OBLIGATED UNDER CONTRACT, + NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR OTHER + LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES + INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE + OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT + OF SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES + (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. + +**************************************************************************************************/ + +/******************************************************************************* +* @file flash.h +* @brief Contains all functions support for flash driver +* @version 0.0 +* @date 27. Nov. 2017 +* @author qing.han +* +* Copyright(C) 2016, PhyPlus Semiconductor +* All rights reserved. +* +*******************************************************************************/ +#ifndef _FLASH_H_ +#define _FLASH_H_ + +#include "rom_sym_def.h" + +#include "types.h" +#include "gpio.h" + + + +//define flash ucds +#define FLASH_UCDS_ADDR_BASE 0x11005000 + +#define CHIP_ID_LENGTH 64 +#define CHIP_ID_PID_LEN 16 +#define CHIP_ID_LID_LEN 10 +#define CHIP_ID_MID_LEN 16 +#define CHIP_ID_TID_LEN 14 +#define CHIP_ID_SID_LEN 8 + +#define CHIP_MADDR_LEN 6 + +typedef enum { + CHIP_ID_UNCHECK, + CHIP_ID_EMPTY, + CHIP_ID_VALID, + CHIP_ID_INVALID, +} CHIP_ID_STATUS_e; + +typedef struct { + CHIP_ID_STATUS_e chipIdStatus; + uint8_t pid[CHIP_ID_PID_LEN]; + uint8_t lid[CHIP_ID_LID_LEN]; + uint8_t mid[CHIP_ID_MID_LEN]; + uint8_t tid[CHIP_ID_TID_LEN]; + uint8_t sid[CHIP_ID_SID_LEN]; +} chipId_t; + +typedef struct { + CHIP_ID_STATUS_e chipMAddrStatus; + uint8_t mAddr[CHIP_MADDR_LEN]; +} chipMAddr_t; + +extern chipId_t g_chipId; +extern chipMAddr_t g_chipMAddr; + + +uint32_t WriteFlash(uint32_t offset, uint8_t *pvalue, uint32_t len); +uint32_t WriteFlashByte(uint32_t offset, uint8_t value); +uint32_t WriteFlashShort(uint32_t offset, uint16_t value); +uint32_t WriteFlashWord(uint32_t offset, uint32_t value); + +uint32_t ReadFlash(uint32_t offset, uint8_t *value, uint32_t len); +uint32_t ReadFlashByte(uint32_t offset, uint8_t *value); +uint32_t ReadFlashShort(uint32_t offset, uint16_t *value); +uint32_t ReadFlashWord(uint32_t offset, uint32_t *value); + +uint32_t flash_block64_erase(uint32_t addr); +uint32_t flash_sector_erase(uint32_t addr); +uint32_t flash_all_erase(void); + +uint8_t flash_write_ucds(uint32_t addr, uint32_t value); +uint32_t flash_read_ucds(uint32_t addr); +void flash_erase_ucds_all(void); +uint8_t flash_erase_ucds(uint32_t addr); +uint8_t flash_write_ucds_block(uint32_t addr, uint32_t length, uint32_t *buf); +uint8_t flash_read_ucds_block(uint32_t addr, uint32_t length, uint32_t *tobuf); +uint8_t flash_write_ucds_block_byte(uint32_t addr, uint32_t length, uint8_t *buf); +uint8_t flash_read_ucds_block_byte(uint32_t addr, uint32_t length, uint8_t *tobuf); + + +void check_chip_id(void); +void check_chip_mAddr(void); +void LOG_CHIP_ID(void); +void LOG_CHIP_MADDR(void); + +/******************************************************************************* + * @fn pplus_enter_programming_mode + * + * @brief force deive enter to programing mode. + * + * input parameters + * + * @param none. + * + * output parameters + * + * @param none. + * + * @return none. + */ +void pplus_enter_programming_mode(void); + + +/******************************************************************************* + * @fn pplus_LoadMACFromChipMAddr + * + * @brief Used to load MAC Address from chip Maddr + * + * input parameters + * + * @param None. + * + * output parameters + * + * @param None. + * + * @return CHIP_ID_STATUS_e. + */ +extern CHIP_ID_STATUS_e pplus_LoadMACFromChipMAddr(void); + +#endif + + + + + + + + diff --git a/components/driver/inc/gpio.h b/components/driver/inc/gpio.h index 31764281bdde7d18d4687aaae8877a798d297fe7..d23a22db9b71663ab1507d06a259117eca977041 100644 --- a/components/driver/inc/gpio.h +++ b/components/driver/inc/gpio.h @@ -204,5 +204,6 @@ int phy_gpioretention_unregister(gpio_pin_e pin); int phy_gpioretention_register(gpio_pin_e pin); void phy_gpioretention_prepare_sleep_action(void); void phy_gpioretention_prepare_wakeup_action(void); +__attribute__((section(".__sram.code"))) void phy_gpioretention_disable(void); #endif diff --git a/components/driver/src/clock.c b/components/driver/src/clock.c index f8a0d5558664138c4cba6a24827d2587f8eed8ee..8d7b0f3fe733261c3bfcc07cd86473a9162d224f 100644 --- a/components/driver/src/clock.c +++ b/components/driver/src/clock.c @@ -254,9 +254,11 @@ void hal_rtc_clock_config(CLK32K_e clk32Mode) subWriteReg(&(AP_AON->PMCTL0), 31, 27, 0x16); //pGlobal_config[LL_SWITCH]&=0xffffffee; } +#if !(defined(CONFIG_SYS_CLK_XTAL_16M) && CONFIG_SYS_CLK_XTAL_16M > 0) //ZQ 20200812 for rc32k wakeup subWriteReg(&(AP_AON->PMCTL0),28,28,0x1);//turn on 32kxtal subWriteReg(&(AP_AON->PMCTL1),18,17,0x0);// reduce 32kxtal bias current +#endif } uint32_t hal_systick(void) diff --git a/components/driver/src/gpio.c b/components/driver/src/gpio.c index d170f4c886c48e88a52173a6b90cc9a315d0d639..99e0f11c17911d4453043d2e9fa76311d42f81ed 100644 --- a/components/driver/src/gpio.c +++ b/components/driver/src/gpio.c @@ -553,6 +553,20 @@ __attribute__((section(".__sram.code"))) void phy_gpioretention_prepare_sleep_ac } } +__attribute__((section(".__sram.code"))) void phy_gpioretention_disable(void) +{ + gpio_pin_e pin=0; + + for(pin=0;pinPMCTL0 &= ~BIT(retention_reg[pin][1]); + } else { + AP_AON->IOCTL[retention_reg[pin][0]] &= ~BIT(retention_reg[pin][1]); + } + } +} + __attribute__((section(".__sram.code"))) void phy_gpioretention_prepare_wakeup_action(void) { gpio_pin_e pin=0; diff --git a/components/driver/src/kscan.c b/components/driver/src/kscan.c index 94173d464d0c7318aa719bd5b14549b79a81e449..506df7ab70d4dc95ce45ca360ee3ec568ff17cdf 100644 --- a/components/driver/src/kscan.c +++ b/components/driver/src/kscan.c @@ -54,7 +54,6 @@ //#include "log.h" #include "jump_function.h" #include "comdef.h" - typedef struct { bool enable; kscan_Cfg_t cfg; diff --git a/components/driver/src/phy_adc.c b/components/driver/src/phy_adc.c index 0cd4bda94905486147c2defbb64223c4010be6dc..a15dccbf409f95d900d0da99f55b5598429a9187 100644 --- a/components/driver/src/phy_adc.c +++ b/components/driver/src/phy_adc.c @@ -1,46 +1,4 @@ -/************************************************************************************************** - - Phyplus Microelectronics Limited confidential and proprietary. - All rights reserved. - - IMPORTANT: All rights of this software belong to Phyplus Microelectronics - Limited ("Phyplus"). Your use of this Software is limited to those - specific rights granted under the terms of the business contract, the - confidential agreement, the non-disclosure agreement and any other forms - of agreements as a customer or a partner of Phyplus. You may not use this - Software unless you agree to abide by the terms of these agreements. - You acknowledge that the Software may not be modified, copied, - distributed or disclosed unless embedded on a Phyplus Bluetooth Low Energy - (BLE) integrated circuit, either as a product or is integrated into your - products. Other than for the aforementioned purposes, you may not use, - reproduce, copy, prepare derivative works of, modify, distribute, perform, - display or sell this Software and/or its documentation for any purposes. - - YOU FURTHER ACKNOWLEDGE AND AGREE THAT THE SOFTWARE AND DOCUMENTATION ARE - PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, - INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE, - NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL - PHYPLUS OR ITS SUBSIDIARIES BE LIABLE OR OBLIGATED UNDER CONTRACT, - NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR OTHER - LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES - INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE - OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT - OF SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES - (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. - -**************************************************************************************************/ - -/******************************************************************************* -* @file adc.c -* @brief Contains all functions support for adc driver -* @version 0.0 -* @date 18. Oct. 2017 -* @author qing.han -* -* Copyright(C) 2016, PhyPlus Semiconductor -* All rights reserved. -* -*******************************************************************************/ + #include #include "error.h" #include "gpio.h" @@ -264,7 +222,7 @@ int phy_adc_start_int_dis(void) //hal_pwrmgr_lock(MOD_ADCC); //JUMP_FUNCTION(V29_IRQ_HANDLER) = (uint32_t)&hal_ADC_IRQHandler; - MASK_ADC_INT; + AP_ADCC->intr_mask = 0x1ff; drv_irq_disable(ADCC_IRQn); drv_irq_unregister(ADCC_IRQn); @@ -384,7 +342,7 @@ int phy_adc_config_channel(adc_Cfg_t cfg, adc_event_cb_t evt_handler) for (i = 2; i < 8; i++) { if (cfg.channel & BIT(i)) { gpio_pin_e pin = s_pinmap[i]; - phy_gpio_pull_set(pin,GPIO_FLOATING); + phy_gpio_pull_set(pin,GPIO_FLOATING); phy_gpio_ds_control(pin, Bit_ENABLE); phy_gpio_cfg_analog_io(pin, Bit_ENABLE); @@ -470,7 +428,7 @@ int phy_adc_config_channel(adc_Cfg_t cfg, adc_event_cb_t evt_handler) //LOG("%d %d %x\n",pin,pin_neg,*(volatile int*)0x40003800); phy_gpio_pull_set(pin,GPIO_FLOATING); - phy_gpio_pull_set(pin_neg,GPIO_FLOATING); + phy_gpio_pull_set(pin_neg,GPIO_FLOATING); phy_gpio_cfg_analog_io(pin, Bit_ENABLE); phy_gpio_cfg_analog_io(pin_neg, Bit_ENABLE); //LOG("%d %d %x\n",pin,pin_neg,*(volatile int*)0x40003800); @@ -537,13 +495,16 @@ int phy_adc_stop(void) **************************************************************************************/ static void phy_adc_load_calibration_value(void) { - if (adc_cal_read_flag == FALSE) { - adc_cal_read_flag = TRUE; - adc_cal_negtive = read_reg(0x11001000) & 0x0fff; - adc_cal_postive = (read_reg(0x11001000) >> 16) & 0x0fff; - //printf("->adc_cal_negtive:%x\n",adc_cal_negtive); - //printf("->adc_cal_postive:%x\n",adc_cal_postive); - } + if (adc_cal_read_flag == FALSE) { + adc_cal_read_flag = TRUE; + adc_cal_negtive = read_reg(0x11001000) & 0x0fff; + adc_cal_postive = (read_reg(0x11001000) >> 16) & 0x0fff; + + if((adc_cal_negtive < 0x733)||(adc_cal_negtive > 0x8cc) ||(adc_cal_postive < 0x733)||(adc_cal_postive > 0x8cc)){ + adc_cal_negtive = 0xfff; + adc_cal_postive = 0xfff; + } + } } @@ -561,13 +522,26 @@ const unsigned int adc_Lambda[ADC_CH_NUM] = 4047198,//P20, 0,//GPIO_DUMMY, //ADC_CH_VOICE =8, + }; //#elif(SDK_VER_CHIP == __DEF_CHIP_TSOP16__) /* +const unsigned short adc_Lambda[ADC_CH_NUM] = +{ + 0, //ADC_CH0 =0, + 0, //ADC_CH1 =1, + 867,//P11, + 0,//P23, + 0,//P24, + 857,//P14, + 800,//P15, + 780,//P20, + 0,//GPIO_DUMMY, //ADC_CH_VOICE =8, }; */ //#endif + int phy_adc_value_cal(adc_CH_t ch, uint16_t *buf, uint32_t size, bool high_resol, bool diff_mode) { volatile float result = 0.0; @@ -575,7 +549,7 @@ int phy_adc_value_cal(adc_CH_t ch, uint16_t *buf, uint32_t size, bool high_resol phy_adc_load_calibration_value(); result = (float)buf[0]; //printf("\n->%d %d %d %d\n",ch,adc_Lambda[ch],(int)result,size); - //printf("\n->%d\n",(int)result); + //printf("[%d]",(int)result); if((adc_cal_postive!=0xfff)&&(adc_cal_negtive!=0xfff)){ float delta = ((int)(adc_cal_postive-adc_cal_negtive))/2.0; if(ch&0x01) @@ -606,6 +580,8 @@ int phy_adc_value_cal(adc_CH_t ch, uint16_t *buf, uint32_t size, bool high_resol } + + /* */ #include @@ -636,6 +612,7 @@ adc_handle_t drv_adc_initialize(int32_t idx, adc_event_cb_t cb_event) adc_priv->evt_handler = cb_event; hal_clk_reset(MOD_ADCC); + hal_clk_gate_enable(MOD_ADCC); phy_adc_init(); @@ -654,7 +631,7 @@ int32_t drv_adc_uninitialize(adc_handle_t handle) //hal_pwrmgr_register(MOD_ADCC,NULL,NULL); phy_clear_adcc_cfg(); //hal_adc_init(); - AP_AON->PMCTL2_1 = 0x00; + AP_AON->PMCTL2_1 =0x00; hal_clk_gate_disable(MOD_ADCC); return 0; @@ -908,10 +885,13 @@ static int read_multiple_channel_n(adc_handle_t handle, uint32_t *data, uint32_t break; ch_cur=(ch%2)?(ch-1):(ch+1); + + while(!(read_reg(0x4005003c)&BIT(ch_cur))); + + subWriteReg(0x40050038,ch_cur,ch_cur,1); - ++i; - i=i%8; - + ++i; + i&=0x07; adc_sum = 0; for (n = 0; n < 29; n++) { adc_sum += (uint16_t)(read_reg(ADC_CH_BASE + (ch_cur * 0x80) + ((n+2) * 4))&0xfff); @@ -926,6 +906,7 @@ static int read_multiple_channel_n(adc_handle_t handle, uint32_t *data, uint32_t //printf("[%x %x ]",s_adc_cfg.is_high_resolution,s_adc_cfg.is_differential_mode); //printf("[%d %d %d]",i,high_resol,diff_mode); data[i] = phy_adc_value_cal(ch,adc_avg,1,high_resol,diff_mode); + //printf("[%d %d %d ] ",i,data[i],ch_cur); ch++; diff --git a/components/driver/src/pinmux.c b/components/driver/src/pinmux.c index ac79aea0a2e1042a37677ba8a1556c042e9ebf5f..78c255403d07acf2d68023033f52c24798e541ed 100644 --- a/components/driver/src/pinmux.c +++ b/components/driver/src/pinmux.c @@ -35,6 +35,7 @@ #define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) uint8_t uart_tx_rx_pin[4] = {0xff,0xff,0xff,0xff}; + /** \brief initial hobbit pinmux. \return none @@ -43,12 +44,14 @@ void ioreuse_initial(void) { } + /** \brief config the pin function. \param[in] pin refs to pin_name_e. \param[in] pin_func refs to pin_func_e. \return 0-success or -1-failure */ + int32_t drv_pinmux_config(pin_name_e pin, pin_func_e pin_func) { if (pin_func == PIN_FUNC_GPIO) { diff --git a/components/dut/dut_test.c b/components/dut/dut_test.c index 3867434548d60a1257a327cc63bfe8807d365c1d..f1169cbae357b357bd7e55c4692b71ee5846cb6e 100755 --- a/components/dut/dut_test.c +++ b/components/dut/dut_test.c @@ -15,12 +15,19 @@ #include "pm.h" #include #include +#include "drv/gpio.h" +#include "pinmux.h" +#include "pin_name.h" /* Must be aligned with 4 Bytes */ typedef struct { uint8_t mac[6]; uint8_t reserved1[2]; +#ifdef CONFIG_CALIBRATE_WITH_FREQOFF + uint32_t freqoff; +#else uint32_t xtalcap; +#endif uint8_t reserved[CONFIG_USER_FACTORY_DATA_SIZE]; } dut_factory_data_t; @@ -91,7 +98,7 @@ int dut_hal_factorydata_read(uint32_t offset, uint8_t *buffer, uint32_t length) return -1; } - int real_off = sizeof(dut_factory_data->mac) + sizeof(dut_factory_data->reserved1) + sizeof(dut_factory_data->xtalcap) + offset; + int real_off = sizeof(dut_factory_data->mac) + sizeof(dut_factory_data->reserved1) + sizeof(uint32_t) + offset; ret = nvram_read(real_off, buffer, length); if (ret < 0) { @@ -155,6 +162,7 @@ int dut_hal_sleep(uint8_t mode) subWriteReg(0x4000f01c, 6, 6, 0x00); //disable software control enter_sleep_off_mode(SYSTEM_OFF_MODE); } + return 0; } @@ -214,12 +222,66 @@ int dut_hal_mac_store(uint8_t addr[6]) return 0; } -/* - Attetion: This function will be called by system, should not printf here. - Here, we use XIP address to get value directly. - Since aos_malloc depend on aos system init, but dut_hal_xtalcap_get will be called - in hal_rfphy_init(), in that time aos was not init yet. -*/ +#ifdef CONFIG_CALIBRATE_WITH_FREQOFF +int dut_hal_freqoff_get(int32_t *freqoff) +{ + uint32_t freqoff_xip = (*(volatile unsigned int *)(CONFIG_FCDS_XTALCAP)); + + if (freqoff == NULL) { + return -1; + } + + if ((RF_PHY_FREQ_FOFF_N200KHZ > ((int32_t)freqoff_xip) || + ((int32_t)freqoff_xip) > RF_PHY_FREQ_FOFF_200KHZ) || + (freqoff_xip == 0xffffffff)) { + *freqoff = RF_PHY_DEFAULT_FREQOFF << 2; + } else { + *freqoff = (int32_t)freqoff_xip << 2; + } + + return 0; +} + +int dut_hal_freqoff_store(int32_t freqoff) +{ + dut_factory_data_t *dut_factory_data = NULL; + int ret = -1; + int real_off = 0; + int real_freqoff = 0; + + real_freqoff = (freqoff - freqoff % 20)/4; + + if (real_freqoff < RF_PHY_FREQ_FOFF_N200KHZ || real_freqoff > RF_PHY_FREQ_FOFF_200KHZ) { + return -1; + } + + dut_factory_data = (dut_factory_data_t *)aos_malloc(sizeof(dut_factory_data_t)); + if (dut_factory_data == NULL) { + return -1; + } + + ret = nvram_read(real_off, (uint8_t *)dut_factory_data, sizeof(dut_factory_data_t)); + if (ret < 0) { + aos_free(dut_factory_data); + return -1; + } + + dut_factory_data->freqoff = (uint32_t)real_freqoff; + + ret = nvram_write((uint8_t *)dut_factory_data, sizeof(dut_factory_data_t)); + if (ret < 0) { + aos_free(dut_factory_data); + return -1; + } + + aos_free(dut_factory_data); + + g_rfPhyFreqOffSet = real_freqoff; + + return 0; +} +#else +/* Attetion: This function will be called by system, should not printf here */ int dut_hal_xtalcap_get(uint32_t *xtalcap) { uint32_t xtalcap_xip = (*(volatile unsigned int *)(CONFIG_FCDS_XTALCAP)); @@ -263,6 +325,7 @@ int dut_hal_xtalcap_store(uint32_t xtalcap) return 0; } +#endif /* API for ble test */ /************************************************************************************** @@ -289,7 +352,7 @@ int dut_hal_ble_tx_single_tone(uint8_t phy_fmt, uint8_t rf_chn_idx, uint32_t xta { uint32 testTimeUs = 1000; - if (phy_fmt != PKT_FMT_BLE1M) { + if (!(phy_fmt == PKT_FMT_BLE1M||phy_fmt ==PKT_FMT_BLE2M||phy_fmt ==PKT_FMT_BLR500K||phy_fmt ==PKT_FMT_BLR125K)) { return -2; } @@ -297,11 +360,20 @@ int dut_hal_ble_tx_single_tone(uint8_t phy_fmt, uint8_t rf_chn_idx, uint32_t xta return -3; } - if (rf_chn_idx > 39) { - return -4; + uint32_t cap = RF_PHY_DEFAULT_XTAL_CAP; + /* + singletone test, if flash have no data, we test with 0; + else we need use value from flash. + */ + int32_t freqoff = RF_PHY_FREQ_FOFF_00KHZ; + int ret = dut_hal_freqoff_get(&freqoff); + if (ret == 0 && freqoff != 0) { + g_rfPhyFreqOffSet = freqoff >> 2; + freqoff = g_rfPhyFreqOffSet; } + //printf("%s, g_freqoff = %d,freqoff = %d\n", __func__, g_rfPhyFreqOffSet, freqoff); - rf_phy_dtm_ext_tx_singleTone(txpower, rf_chn_idx, xtalcap, 0, testTimeUs); + rf_phy_dtm_ext_tx_singleTone(txpower, rf_chn_idx, cap, freqoff, testTimeUs); return 0; } @@ -335,7 +407,7 @@ int dut_hal_ble_tx_mod_burst(uint8_t phy_fmt, uint8_t rf_chn_idx,uint32_t xtalca uint8_t pktLength = 37; //max pkt length in 625us uint32_t txPktNum = 1000; //send 1000 pkt - if (phy_fmt != PKT_FMT_BLE1M) { + if (!(phy_fmt == PKT_FMT_BLE1M||phy_fmt ==PKT_FMT_BLE2M||phy_fmt ==PKT_FMT_BLR500K||phy_fmt ==PKT_FMT_BLR125K)) { return -2; } @@ -343,15 +415,19 @@ int dut_hal_ble_tx_mod_burst(uint8_t phy_fmt, uint8_t rf_chn_idx,uint32_t xtalca return -3; } - if (rf_chn_idx > 39) { - return -4; - } - - if (pkt_type > 3) { + if (pkt_type > 5) { return -5; } + uint32_t cap = RF_PHY_DEFAULT_XTAL_CAP; + int32_t freqoff = RF_PHY_FREQ_FOFF_00KHZ; + int ret = dut_hal_freqoff_get(&freqoff); + if (ret == 0 && freqoff != 0) { + g_rfPhyFreqOffSet = freqoff >> 2; + freqoff = g_rfPhyFreqOffSet; + } + //printf("%s, g_freqoff = %d,freqoff = %d\n", __func__, g_rfPhyFreqOffSet, freqoff); - rf_phy_dtm_ext_tx_mod_burst(txpower, rf_chn_idx, xtalcap, 0, pkt_type, pktLength, txPktNum, txPktIntv); + rf_phy_dtm_ext_tx_mod_burst(txpower, rf_chn_idx, cap, freqoff, pkt_type, pktLength, txPktNum, txPktIntv); return 0; } @@ -386,15 +462,20 @@ int dut_hal_ble_rx_demod_burst(uint8_t phy_fmt, uint8_t rf_chn_idx, uint32_t xta uint32 rxWindow = 625; //pkt interval unit:us uint32 rxTimeOut = 625; //1000 pkt cost 625ms unit:ms - if (phy_fmt != PKT_FMT_BLE1M) { + if (!(phy_fmt == PKT_FMT_BLE1M||phy_fmt ==PKT_FMT_BLE2M||phy_fmt ==PKT_FMT_BLR500K||phy_fmt ==PKT_FMT_BLR125K)) { return -2; } - if (rf_chn_idx > 39) { - return -4; + uint32_t cap = RF_PHY_DEFAULT_XTAL_CAP; + int32_t freqoff = RF_PHY_FREQ_FOFF_00KHZ; + int ret = dut_hal_freqoff_get(&freqoff); + if (ret == 0 && freqoff != 0) { + g_rfPhyFreqOffSet = freqoff >> 2; + freqoff = g_rfPhyFreqOffSet; } + //printf("%s, g_freqoff = %d,freqoff = %d\n", __func__, g_rfPhyFreqOffSet, freqoff); - rf_phy_dtm_ext_rx_demod_burst(rf_chn_idx, 0, xtalcap, pktLength, rxTimeOut, rxWindow, rx_freq_off, rx_rssi, rx_carr_sens, rx_pkt_num); + rf_phy_dtm_ext_rx_demod_burst(rf_chn_idx, freqoff, cap, pktLength, rxTimeOut, rxWindow, rx_freq_off, rx_rssi, rx_carr_sens, rx_pkt_num); return 0; } @@ -404,3 +485,80 @@ int dut_hal_ble_transmit_stop(void) rf_phy_dtm_stop(); return 0; } + +int dut_hal_rx_current_test(uint32_t sleep_time) +{ + int16_t rxEstFoff = 0; + uint8_t rx_est_rssi = 0; + uint8_t rx_est_carrsens = 0; + uint16_t rx_pkt_num = 0; + uint8_t rfChnIdx = 0; + uint8_t pktLength = 37; //max pkt length in 625us + uint32 rxWindow = 625; //pkt interval unit:us + + if (sleep_time < 10) { + sleep_time = 10; + } + + uint32_t cap = RF_PHY_DEFAULT_XTAL_CAP; + int32_t freqoff = RF_PHY_FREQ_FOFF_00KHZ; + int ret = dut_hal_freqoff_get(&freqoff); + if (ret == 0 && freqoff != 0) { + g_rfPhyFreqOffSet = freqoff >> 2; + freqoff = g_rfPhyFreqOffSet; + } + //printf("%s, g_freqoff = %d,freqoff = %d\n", __func__, g_rfPhyFreqOffSet, freqoff); + + drv_pm_sleep_enable(); + + rf_phy_dtm_ext_rx_demod_burst(rfChnIdx, freqoff, cap, pktLength, sleep_time, rxWindow, + &rxEstFoff, &rx_est_rssi, &rx_est_carrsens, &rx_pkt_num); + + rf_phy_dtm_stop(); + drv_pm_sleep_disable(); + + return OK; +} + + +int dut_hal_test_gpio_write(uint8_t wrgpio, uint8_t value) +{ + int ret; + gpio_pin_handle_t *pin = NULL; + + if (wrgpio >= GPIO_NUM) { + return -1; + } + + drv_pinmux_config(wrgpio, PIN_FUNC_GPIO); + pin = csi_gpio_pin_initialize(wrgpio, NULL); + + ret = csi_gpio_pin_config_direction(pin, GPIO_DIRECTION_OUTPUT); + if(ret < 0){ + return ret; + } + csi_gpio_pin_write(pin, value); + return 0; +} + +int dut_hal_test_gpio_read(uint8_t wrgpio, uint8_t *value) +{ + int ret; + bool *bool_value = (bool *)value; + gpio_pin_handle_t *pin = NULL; + + if (wrgpio >= GPIO_NUM) { + return -1; + } + + drv_pinmux_config(wrgpio, PIN_FUNC_GPIO); + pin = csi_gpio_pin_initialize(wrgpio, NULL); + + ret = csi_gpio_pin_config_direction(pin,GPIO_DIRECTION_INPUT); + if(ret < 0){ + return ret; + } + csi_gpio_pin_read(pin,bool_value); + return 0; +} + diff --git a/components/inc/mcu.h b/components/inc/mcu.h index cb00fde109925026908680f41a64dc83279a32fd..cb5a4a9f13d9cb8ca9c7e07b3692d2b8cd844fbb 100644 --- a/components/inc/mcu.h +++ b/components/inc/mcu.h @@ -96,9 +96,11 @@ #define HAL_ICER *((volatile uint32_t *)(0xe000e180)) //subWriteReg: write value to register zone: bit[high:low] -#define subWriteReg(addr,high,low,value) write_reg(addr,(read_reg(addr)&\ +#define subWriteReg(addr,high,low,value) {write_reg(addr,(read_reg(addr)&\ (~((((unsigned int)1<<((high)-(low)+1))-1)<<(low))))|\ - ((unsigned int)(value)<<(low))) +((unsigned int)(value)<<(low)));__asm volatile("nop");} + + #define TIME_BASE (0x003fffff) // 24bit count shift 2 bit as 1us/bit #define TIME_DELTA(x,y) ( (x>=y) ? x-y : TIME_BASE-y+x ) diff --git a/components/inc/types.h b/components/inc/types.h index d1c404bc2c1cb85fc489599dafd7fca46463d5a4..147692285c519207bd6dbbc7b697eff5a3099455 100644 --- a/components/inc/types.h +++ b/components/inc/types.h @@ -169,7 +169,7 @@ typedef struct _comm_evt_t { typedef void (*comm_cb_t)(comm_evt_t *pev); - +#define __ATTR_FUNC_XIP__(fn) __attribute__(( section("__xip_function__."#fn))) fn #endif diff --git a/components/osal/include/comdef.h b/components/osal/include/comdef.h index a3cfe33fef1e4bd779213b4ed3b10878959e50f5..1e134cec498a2c8e8d00051716528e01a04d395c 100644 --- a/components/osal/include/comdef.h +++ b/components/osal/include/comdef.h @@ -36,7 +36,9 @@ extern "C" #define NULL_OK #define INP #define OUTP +#ifndef UNUSED #define UNUSED +#endif #define ONLY #define READONLY #define SHARED diff --git a/csi_drivers/ck_irq.c b/csi_drivers/ck_irq.c index a68f6e39911e5cb6edf937e8aad6199436dd9e08..f745cc39e638b91cd538cd1e165e7a14dda75a40 100644 --- a/csi_drivers/ck_irq.c +++ b/csi_drivers/ck_irq.c @@ -23,11 +23,11 @@ extern void (*g_irqvector[])(void); */ __attribute__((section(".__sram.code"))) void drv_irq_enable(uint32_t irq_num) { -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_enable_sirq(irq_num); -#else +//#ifdef CONFIG_SYSTEM_SECURE + //csi_vic_enable_sirq(irq_num); +//#else csi_vic_enable_irq(irq_num); -#endif +//#endif } /** @@ -37,11 +37,11 @@ __attribute__((section(".__sram.code"))) void drv_irq_enable(uint32_t irq_num) */ __attribute__((section(".__sram.code"))) void drv_irq_disable(uint32_t irq_num) { -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_disable_sirq(irq_num); -#else +//#ifdef CONFIG_SYSTEM_SECURE + //csi_vic_disable_sirq(irq_num); +//#else csi_vic_disable_irq(irq_num); -#endif +//#endif } /** diff --git a/csi_drivers/dw_dmac.c b/csi_drivers/dw_dmac.c index a3bec64f2e1f6b29352e72fc10054ba22f5c2fe2..e619618588f42a0b0a58f95232aa586d4ba4be5b 100644 --- a/csi_drivers/dw_dmac.c +++ b/csi_drivers/dw_dmac.c @@ -48,7 +48,7 @@ static const dma_capabilities_t dma_capabilities = { #define writel(b, addr) \ *((volatile uint32_t *)(addr)) = b -static void dw_dma_set_channel(uint32_t addr, uint8_t ch, uint32_t source, uint32_t dest, uint32_t size) +__attribute__((section(".__sram.code"))) static void dw_dma_set_channel(uint32_t addr, uint8_t ch, uint32_t source, uint32_t dest, uint32_t size) { writel(size, addr + (ch % 4) * 0x58 + DMA_REG_CTRLbx); writel(source, addr + (ch % 4) * 0x58 + DMA_REG_SARx); @@ -112,7 +112,7 @@ static int32_t dw_dma_set_transferwidth(uint32_t addr, uint8_t ch, dma_datawidth return 0; } -static void dw_dma_set_burstlength(uint32_t addr, uint8_t ch, uint8_t burstlength) +__attribute__((section(".__sram.code"))) static void dw_dma_set_burstlength(uint32_t addr, uint8_t ch, uint8_t burstlength) { uint32_t value = readl(addr + (ch % 4) * 0x58 + DMA_REG_CTRLax); value &= ~(0x1f800); @@ -147,7 +147,7 @@ static int32_t dw_dma_assign_hdhs_interface(uint32_t addr, uint8_t ch, dwenum_dm return 0; } -static void dw_dmac_intr_ch_error(int32_t idx) +static __attribute__((section(".__sram.code"))) void dw_dmac_intr_ch_error(int32_t idx) { dw_dma_priv_t *dma_priv = &dma_instance[idx]; uint32_t addr = dma_priv->base; @@ -200,7 +200,7 @@ __attribute__((section(".__sram.code"))) void dw_dmac_irqhandler(int32_t idx) for (ch_num = 0; ch_num < CONFIG_DMA_CHANNEL_NUM; ch_num++) { if (status & (1ul << ch_num)) { - dw_dmac_intr_ch_complete(ch_num); + dw_dmac_intr_ch_error(ch_num); } } @@ -421,7 +421,7 @@ int32_t csi_dma_config_channel(int32_t ch, dma_config_t *config, dma_event_cb_t return ret; } - ret = dw_dma_assign_hdhs_interface(addr, dma_priv->ch_num, config->hs_if, config->hs_if); + ret = dw_dma_assign_hdhs_interface(addr, dma_priv->ch_num, 0, config->hs_if); if (ret < 0) { return ret; @@ -435,7 +435,7 @@ int32_t csi_dma_config_channel(int32_t ch, dma_config_t *config, dma_event_cb_t return ret; } - ret = dw_dma_assign_hdhs_interface(addr, dma_priv->ch_num, config->hs_if, config->hs_if); + ret = dw_dma_assign_hdhs_interface(addr, dma_priv->ch_num, config->hs_if, 0); if (ret < 0) { return ret; @@ -456,7 +456,7 @@ int32_t csi_dma_config_channel(int32_t ch, dma_config_t *config, dma_event_cb_t \param[in] pdstaddr dma transfer destination address \param[in] length dma transfer length (unit: bytes). */ -void csi_dma_start(int32_t ch, void *psrcaddr, +__attribute__((section(".__sram.code"))) void csi_dma_start(int32_t ch, void *psrcaddr, void *pdstaddr, uint32_t length) { if (ch >= CONFIG_DMA_CHANNEL_NUM || ch < 0 || psrcaddr == NULL || pdstaddr == NULL) { @@ -472,13 +472,13 @@ void csi_dma_start(int32_t ch, void *psrcaddr, return; } - uint8_t i; + uint8_t i = 0; - for (i = 2; i > 0; i--) { - if (!((length * dma_priv->src_tw / dma_priv->dst_tw) % (2 << i))) { - break; - } - } + //for (i = 2; i > 0; i--) { + // if (!((length * dma_priv->src_tw / dma_priv->dst_tw) % (2 << i))) { + // break; + // } + //} int32_t grouplen = i; @@ -503,7 +503,7 @@ void csi_dma_start(int32_t ch, void *psrcaddr, \brief Stop generate dma channel signal. \param[in] ch dma channel num */ -void csi_dma_stop(int32_t ch) +__attribute__((section(".__sram.code"))) void csi_dma_stop(int32_t ch) { if (ch >= CONFIG_DMA_CHANNEL_NUM || ch < 0) { return; diff --git a/csi_drivers/dw_usart.c b/csi_drivers/dw_usart.c index 421d655ac99a4faa2e17903f6af1d68a4b6e1de4..ac8b0327264798075f6080c7903e9d41df762867 100644 --- a/csi_drivers/dw_usart.c +++ b/csi_drivers/dw_usart.c @@ -9,7 +9,6 @@ * @version V1.0 * @date 02. June 2017 ******************************************************************************/ - #include #include #include @@ -18,6 +17,9 @@ #include #include #include +#if defined CONFIG_DW_UART_DMAC +#include +#endif #include #include #include @@ -98,6 +100,17 @@ typedef struct { uint32_t last_rx_num; int32_t idx; uint32_t fcr_reg; +#if defined CONFIG_DW_UART_DMAC + int32_t dma_tx_ch; + int32_t dma_rx_ch; + uint8_t dma_tx_mode; // 0-not sending 1-sending + uint8_t dma_rx_mode; // 0-not receiving 1-receiving + uint32_t rx_block_num; + uint32_t tx_block_num; + uint32_t rx_num; + uint32_t tx_num; + dma_config_t config; +#endif } dw_usart_priv_t; extern int32_t target_usart_init(int32_t idx, uint32_t *base, uint32_t *irq, void **handler); @@ -114,6 +127,120 @@ static const usart_capabilities_t usart_capabilities = { .event_rx_timeout = 0, /* Signal receive character timeout event */ }; +#if defined CONFIG_DW_UART_DMAC +__attribute__((section(".__sram.code"))) static void dw_usart_dma_event_cb(int32_t ch, dma_event_e event, void *arg) +{ + dw_usart_priv_t *usart_priv = NULL; + int8_t priv_num = 0; + + for (priv_num = 0; priv_num < CONFIG_USART_NUM; priv_num++) { + usart_priv = &usart_instance[priv_num]; + + if ((usart_priv->dma_tx_ch == ch && usart_priv->dma_tx_mode == 1) || (usart_priv->dma_rx_ch == ch && usart_priv->dma_rx_mode == 1)) { + break; + } + } + + dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base); + + if (event == DMA_EVENT_TRANSFER_ERROR) { /* DMA transfer ERROR */ + if (usart_priv->dma_tx_ch == ch && usart_priv->dma_tx_mode == 1) { + csi_dma_stop(usart_priv->dma_tx_ch); + csi_dma_release_channel(usart_priv->dma_tx_ch); + usart_priv->tx_busy = 0; + usart_priv->dma_tx_mode = 0; + usart_priv->dma_tx_ch = -1; + usart_priv->fcr_reg &= ~DW_FCR_TET_FIFO_HALF; + //addr->FCR = usart_priv->fcr_reg; + + if (usart_priv->cb_event) { + usart_priv->cb_event(priv_num, USART_EVENT_TX_UNDERFLOW); + } + } else { + csi_dma_stop(usart_priv->dma_rx_ch); + csi_dma_release_channel(usart_priv->dma_rx_ch); + usart_priv->rx_busy = 0; + usart_priv->dma_rx_mode = 0; + usart_priv->dma_rx_ch = -1; + + /* FIFO enable */ + usart_priv->fcr_reg &= ~(DW_FCR_RT_FIFO_LESSTWO); + // addr->FCR |= DW_FCR_FIFOE | DW_FCR_RT_FIFO_HALF; + usart_priv->fcr_reg |= DW_FCR_RT_FIFO_HALF; + /* enable received data available */ + addr->IER |= IER_RDA_INT_ENABLE | IIR_RECV_LINE_ENABLE; + + if (usart_priv->cb_event) { + usart_priv->cb_event(priv_num, USART_EVENT_RX_FRAMING_ERROR); + } + } + } else if (event == DMA_EVENT_TRANSFER_DONE) { /* DMA transfer complete */ + if (usart_priv->dma_tx_ch == ch && usart_priv->dma_tx_mode == 1) { + usart_priv->tx_num += usart_priv->tx_block_num; + + if (usart_priv->tx_num >= usart_priv->tx_total_num) { + csi_dma_stop(usart_priv->dma_tx_ch); + csi_dma_release_channel(usart_priv->dma_tx_ch); + usart_priv->tx_busy = 0; + usart_priv->dma_tx_mode = 0; + usart_priv->dma_tx_ch = -1; + usart_priv->fcr_reg &= ~(DW_FCR_TET_FIFO_HALF); + //addr->FCR = usart_priv->fcr_reg; + + if (usart_priv->cb_event) { + usart_priv->cb_event(priv_num, USART_EVENT_SEND_COMPLETE); + } + } else { + uint32_t max_block_size = DMA_MAX_TRANSPORT_SIZE(usart_priv->dma_tx_ch); + uint32_t next_tx_size = usart_priv->tx_total_num - usart_priv->tx_num; + usart_priv->tx_block_num = (next_tx_size > max_block_size) ? max_block_size : next_tx_size; + csi_dma_start(usart_priv->dma_tx_ch, usart_priv->tx_buf + usart_priv->tx_num, (uint8_t *) & (addr->THR), usart_priv->tx_block_num); + } + } else if (usart_priv->dma_rx_ch == ch && usart_priv->dma_rx_mode == 1) { + usart_priv->rx_num += usart_priv->rx_block_num; + + if (usart_priv->rx_num >= usart_priv->rx_total_num) { + csi_dma_stop(usart_priv->dma_rx_ch); + //csi_dma_release_channel(usart_priv->dma_rx_ch); + //usart_priv->rx_busy = 0; + //usart_priv->dma_rx_mode = 0; + //usart_priv->dma_rx_ch = -1; + + /* FIFO enable */ + //usart_priv->fcr_reg &= ~(DW_FCR_RT_FIFO_LESSTWO); + //usart_priv->fcr_reg |= DW_FCR_RT_FIFO_HALF; + //addr->FCR = usart_priv->fcr_reg; + /* enable received data available */ + //addr->IER |= IER_RDA_INT_ENABLE | IIR_RECV_LINE_ENABLE; + + //uint32_t max_block_size = DMA_MAX_TRANSPORT_SIZE(usart_priv->dma_rx_ch); + //usart_priv->rx_block_num = (usart_priv->rx_total_num > max_block_size) ? max_block_size : usart_priv->rx_total_num; + //usart_priv->rx_num = 0; + //csi_dma_start(usart_priv->dma_rx_ch, (uint8_t *) & (addr->THR), usart_priv->rx_buf, usart_priv->rx_block_num); + if (usart_priv->cb_event) { + usart_priv->cb_event(priv_num, USART_EVENT_RECEIVE_COMPLETE); + } + } else { + uint32_t max_block_size = DMA_MAX_TRANSPORT_SIZE(usart_priv->dma_rx_ch); + uint32_t next_rx_size = usart_priv->rx_total_num - usart_priv->rx_num; + usart_priv->rx_block_num = (next_rx_size > max_block_size) ? max_block_size : next_rx_size; + + uint8_t i; + + for (i = 2; i > 0; i--) { + if (!(usart_priv->rx_block_num % (2 << i))) { + break; + } + } + + csi_dma_start(usart_priv->dma_rx_ch, (uint8_t *) & (addr->THR), usart_priv->rx_buf + usart_priv->rx_num, usart_priv->rx_block_num); + } + + } + } +} +#endif + static int32_t usart_wait_timeout(usart_handle_t handle, dw_usart_reg_t *addr) { uint32_t timecount = 0; @@ -557,7 +684,11 @@ __attribute__((section(".__sram.code"))) void dw_usart_irqhandler(int32_t idx) { dw_usart_priv_t *usart_priv = &usart_instance[idx]; dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base); - +#if defined CONFIG_DW_UART_DMAC + if (usart_priv->dma_rx_mode) { + return; + } +#endif uint8_t intr_state = addr->IIR & 0xf; switch (intr_state) { @@ -625,41 +756,44 @@ __attribute__((section(".__sram.code"))) void csi_usart_prepare_sleep_action(vo uint32_t addr = 0x40004000; uint32_t set_fcr_value; while (!(*(volatile uint32_t *)(addr + 0x7c) & 0x4)); - - *(volatile uint32_t *)(addr + 0xc) |= 0x80; - registers_save((uint32_t *)usart_regs_saved, (uint32_t *)addr, 2); - *(volatile uint32_t *)(addr + 0xc) &= ~0x80; - registers_save(&usart_regs_saved[2], (uint32_t *)addr + 1, 1); - registers_save(&usart_regs_saved[3], (uint32_t *)addr + 3, 2); - - for(int i = 0; i < 4 ; i++) { - if(uart_tx_rx_pin[i] != 0xff) { - phy_gpio_fmux(uart_tx_rx_pin[i], Bit_DISABLE); - } - } - +// for(int i = 0; i < 4 ; i++) { +// if(uart_tx_rx_pin[i] != 0xff) { +// phy_gpio_fmux(uart_tx_rx_pin[i], Bit_DISABLE); +// } +// } +// while ((*(volatile uint32_t *)(addr + 0x7c) & 0x1)); set_fcr_value = (*(volatile uint32_t *)(addr + 0x98) & 0x01) | ((*(volatile uint32_t *)(addr + 0x94) & 0x01)<<3) | ((*(volatile uint32_t *)(addr + 0x9c) & 0x03)<<6) | ((*(volatile uint32_t *)(addr + 0xa0) & 0x03)<<4) | DW_FCR_RFIFOR | DW_FCR_XFIFOR; + + registers_save(&usart_regs_saved[3], (uint32_t *)addr + 3, 1); + + do{ - *(volatile uint32_t *)(addr + 0x8) = set_fcr_value; - }while (*(volatile uint32_t *)(addr + 0x7c) & 0x1); - - usart_regs_saved[4] = set_fcr_value; + *(volatile uint32_t *)(addr + 0xc) = 0x80; + }while(*(volatile uint32_t *)(addr + 0xc) != 0x80); + registers_save((uint32_t *)usart_regs_saved, (uint32_t *)addr, 2); + do{ + *(volatile uint32_t *)(addr + 0xc) = usart_regs_saved[3]; + }while(*(volatile uint32_t *)(addr + 0xc) != usart_regs_saved[3]); + registers_save(&usart_regs_saved[2], (uint32_t *)addr + 1, 1); + usart_regs_saved[4] = set_fcr_value; } __attribute__((section(".__sram.code"))) void csi_usart_wakeup_sleep_action(void) { uint32_t addr = 0x40004000; - //while (*(volatile uint32_t *)(addr + 0x7c) & 0x1); - *(volatile uint32_t *)(addr + 0xc) |= 0x80; + do{ + *(volatile uint32_t *)(addr + 0xc) = 0x80; + }while(*(volatile uint32_t *)(addr + 0xc) != 0x80); registers_save((uint32_t *)addr, usart_regs_saved, 2); - *(volatile uint32_t *)(addr + 0xc) &= ~0x80; + do{ + *(volatile uint32_t *)(addr + 0xc) = usart_regs_saved[3]; + }while(*(volatile uint32_t *)(addr + 0xc) != usart_regs_saved[3]); registers_save((uint32_t *)addr + 1, &usart_regs_saved[2], 1); - registers_save((uint32_t *)addr + 3, &usart_regs_saved[3], 2); registers_save((uint32_t *)addr + 2, &usart_regs_saved[4], 1); } @@ -703,6 +837,13 @@ usart_handle_t csi_usart_initialize(int32_t idx, usart_event_cb_t cb_event) usart_priv->cb_event = cb_event; usart_priv->idx = idx; +#if defined CONFIG_DW_UART_DMAC + usart_priv->dma_tx_ch = -1; + usart_priv->dma_rx_ch = -1; + usart_priv->dma_tx_mode = 0; + usart_priv->dma_rx_mode = 0; +#endif + #ifdef CONFIG_LPM csi_usart_power_control(usart_priv, DRV_POWER_FULL); #endif @@ -717,8 +858,8 @@ usart_handle_t csi_usart_initialize(int32_t idx, usart_event_cb_t cb_event) dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base); /* FIFO enable */ - addr->FCR = DW_FCR_FIFOE | DW_FCR_RT_FIFO_QUARTER; //DW_FCR_RT_FIFO_SINGLE; - usart_priv->fcr_reg = DW_FCR_FIFOE | DW_FCR_RT_FIFO_QUARTER; //DW_FCR_RT_FIFO_SINGLE; + addr->FCR = DW_FCR_FIFOE | DW_FCR_RT_FIFO_SINGLE; + usart_priv->fcr_reg = DW_FCR_FIFOE | DW_FCR_RT_FIFO_SINGLE; /* enable received data available */ addr->IER = IER_RDA_INT_ENABLE | IIR_RECV_LINE_ENABLE; @@ -813,6 +954,69 @@ int32_t csi_usart_config(usart_handle_t handle, return 0; } +#if defined CONFIG_DW_UART_DMAC +static int32_t dw_usart_send_dma(dw_usart_priv_t *usart_priv) +{ + dma_config_t config; + config.src_inc = DMA_ADDR_INC; + config.dst_inc = DMA_ADDR_CONSTANT; + config.src_tw = 1; + config.dst_tw = 1; + if (usart_priv->idx == 0) { + config.hs_if = DWENUM_DMA_UART0_TX; + } else if (usart_priv->idx == 1) { + config.hs_if = DWENUM_DMA_UART1_TX; + } else { + return ERR_USART(DRV_ERROR_PARAMETER); + } + config.type = DMA_MEM2PERH; + if (usart_priv->dma_tx_ch == -1) { + usart_priv->dma_tx_ch = csi_dma_alloc_channel(); + if (usart_priv->dma_tx_ch == -1) { + return ERR_USART(DRV_ERROR_PARAMETER); + } + } + int32_t ret = csi_dma_config_channel(usart_priv->dma_tx_ch, &config, dw_usart_dma_event_cb, NULL); + if (ret < 0) { + csi_dma_release_channel(usart_priv->dma_tx_ch); + return ret; + } + usart_priv->config = config; + uint32_t max_block_size = DMA_MAX_TRANSPORT_SIZE(usart_priv->dma_tx_ch); + usart_priv->tx_block_num = (usart_priv->tx_total_num > max_block_size) ? max_block_size : usart_priv->tx_total_num; + dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base); + addr->FCR = usart_priv->fcr_reg | (DW_FCR_TET_FIFO_HALF); + usart_priv->fcr_reg |= (DW_FCR_TET_FIFO_HALF); + csi_dma_start(usart_priv->dma_tx_ch, usart_priv->tx_buf, (uint8_t *) & (addr->THR), usart_priv->tx_block_num); + return 0; +} +int32_t csi_usart_send_dma(usart_handle_t handle, const void *data, uint32_t num) +{ + USART_NULL_PARAM_CHK(handle); + USART_NULL_PARAM_CHK(data); + + uint8_t *buff = (uint8_t *)data; + + if (num == 0) { + return ERR_USART(DRV_ERROR_PARAMETER); + } + + dw_usart_priv_t *usart_priv = handle; + + usart_priv->tx_buf = buff; + usart_priv->tx_total_num = num; + + usart_priv->dma_tx_mode = 1; + usart_priv->tx_busy = 1; + usart_priv->last_tx_num = 0; + usart_priv->tx_num = 0; + + int32_t ret = dw_usart_send_dma(usart_priv); + + return ret; +} + +#endif /** \brief Start sending data to UART transmitter,(received data is ignored). The function is non-blocking,UART_EVENT_TRANSFER_COMPLETE is signaled when transfer completes. @@ -858,6 +1062,111 @@ int32_t csi_usart_abort_send(usart_handle_t handle) return ERR_USART(DRV_ERROR_UNSUPPORTED); } +#if defined CONFIG_DW_UART_DMAC +static int32_t dw_usart_receive_dma(dw_usart_priv_t *usart_priv) +{ + dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base); + /* disable received data available */ + + dma_config_t config; + config.src_inc = DMA_ADDR_CONSTANT; + config.dst_inc = DMA_ADDR_INC; + config.src_tw = 1; + config.dst_tw = 1; + + if (usart_priv->idx == 0) { + config.hs_if = DWENUM_DMA_UART0_RX; + } else if (usart_priv->idx == 1) { + config.hs_if = DWENUM_DMA_UART1_RX; + } else { + return ERR_USART(DRV_ERROR_PARAMETER); + } + + //addr->IER &= ~(IER_RDA_INT_ENABLE | IIR_RECV_LINE_ENABLE); + config.type = DMA_PERH2MEM; + + if (usart_priv->dma_rx_ch == -1) { + usart_priv->dma_rx_ch = csi_dma_alloc_channel(); + + if (usart_priv->dma_rx_ch == -1) { + return ERR_USART(DRV_ERROR_PARAMETER); + } + } + + csi_dma_stop(usart_priv->dma_rx_ch); + + int ret = csi_dma_config_channel(usart_priv->dma_rx_ch, &config, dw_usart_dma_event_cb, NULL); + + if (ret < 0) { + csi_dma_release_channel(usart_priv->dma_rx_ch); + return ret; + } + + usart_priv->config = config; + + uint32_t max_block_size = DMA_MAX_TRANSPORT_SIZE(usart_priv->dma_rx_ch); + usart_priv->rx_block_num = (usart_priv->rx_total_num > max_block_size) ? max_block_size : usart_priv->rx_total_num; + + uint8_t i; + + for (i = 2; i > 0; i--) { + if (!(usart_priv->rx_block_num % (2 << i))) { + break; + } + } + + usart_priv->dma_rx_mode = 1; + + //usart_priv->fcr_reg &= ~(DW_FCR_RT_FIFO_LESSTWO); + //addr->FCR = 1 << DW_USART_FCR_RFIFOR_Pos | (1 << DW_USART_FCR_RT_Pos) | usart_priv->fcr_reg; + //usart_priv->fcr_reg |= (i << DW_USART_FCR_RT_Pos); + csi_dma_start(usart_priv->dma_rx_ch, (uint8_t *) & (addr->THR), usart_priv->rx_buf, usart_priv->rx_block_num); + return 0; +} + +int32_t csi_usart_receive_dma(usart_handle_t handle, void *data, uint32_t num) +{ + USART_NULL_PARAM_CHK(handle); + USART_NULL_PARAM_CHK(data); + + dw_usart_priv_t *usart_priv = handle; + + usart_priv->rx_buf = (uint8_t *)data; // Save receive buffer usart + usart_priv->rx_total_num = num; // Save number of data to be received + usart_priv->rx_cnt = 0; + usart_priv->rx_busy = 1; + usart_priv->last_rx_num = 0; + usart_priv->rx_num = 0; + + int32_t ret = dw_usart_receive_dma(usart_priv); + + return ret; + +} + +__attribute__((section(".__sram.code"))) int32_t csi_usart_restart_receive_dma(usart_handle_t handle) +{ + dw_usart_priv_t *usart_priv = handle; + dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base); + + /* if rx buffer pointer is working,but uart is idle, meanings rx buffer have unused data, need reset */ + uint32_t flags = csi_irq_save(); + if ((((volatile uint32_t )(AP_DMA_CH_CFG(usart_priv->dma_rx_ch)->DAR)) != usart_priv->rx_buf ) && + ((addr->USR & USR_UART_BUSY) == 0)) { + uint32_t max_block_size = DMA_MAX_TRANSPORT_SIZE(usart_priv->dma_rx_ch); + usart_priv->rx_block_num = (usart_priv->rx_total_num > max_block_size) ? max_block_size : usart_priv->rx_total_num; + usart_priv->rx_num = 0; + csi_dma_stop(usart_priv->dma_rx_ch); + csi_dma_start(usart_priv->dma_rx_ch, (uint8_t *) & (addr->THR), usart_priv->rx_buf, usart_priv->rx_block_num); + irq_unlock(flags); + return 0; + } + csi_irq_restore(flags); + return -1; +} + +#endif + /** \brief Start receiving data from UART receiver. \param[in] handle usart handle to operate. diff --git a/csi_drivers/dw_wdt.c b/csi_drivers/dw_wdt.c index 0fcf3fdbbc17c6de1fb96b577b4beeb3ff15de84..fcfc5b0ebb35bcb994a5473c12540462ee4516d5 100644 --- a/csi_drivers/dw_wdt.c +++ b/csi_drivers/dw_wdt.c @@ -34,7 +34,8 @@ //#define SYSTEM_CLOCK_MS (30000 / 1000) //uint32_t timeout_ms[16]; -const uint32_t timeout_ms[8] = {2000, 4000, 8000, 16000, 32000, 64000, 128000, 256000}; +//const uint32_t timeout_ms[8] = {2000, 4000, 8000, 16000, 32000, 64000, 128000, 256000}; +uint32_t timeout_ms[8] = {2000, 4000, 8000, 16000, 32000, 64000, 128000, 256000}; typedef struct { #ifdef CONFIG_LPM uint8_t wdt_power_status; @@ -52,7 +53,7 @@ static dw_wdt_priv_t wdt_instance[CONFIG_WDT_NUM]; static inline void dw_wdt_enable(dw_wdt_reg_t *addr) { - addr->WDT_CR = 0x1F; + addr->WDT_CR = 0x1D; } static inline void dw_wdt_disable(dw_wdt_reg_t *addr) @@ -197,7 +198,7 @@ int32_t csi_wdt_power_control(wdt_handle_t handle, csi_power_stat_e state) \param[in] value the timeout value(ms) \ref:timeout_ms[] \return \ref execution_status */ -int32_t csi_wdt_set_timeout(wdt_handle_t handle, uint32_t value) +__attribute__((section(".__sram.code"))) int32_t csi_wdt_set_timeout(wdt_handle_t handle, uint32_t value) { WDT_NULL_PARAM_CHK(handle); uint32_t i = 0u; @@ -275,7 +276,7 @@ int32_t csi_wdt_stop(wdt_handle_t handle) \param[in] handle wdt handle to operate. \return \ref execution_status */ -int32_t csi_wdt_restart(wdt_handle_t handle) +__attribute__((section(".__sram.code"))) int32_t csi_wdt_restart(wdt_handle_t handle) { WDT_NULL_PARAM_CHK(handle); diff --git a/csi_drivers/phy_rtc.c b/csi_drivers/phy_rtc.c index ff353aace686bec179ceb1b65722e4e62bb6dc48..febea6972e72b86d496cb9ae3ce146079f402c76 100644 --- a/csi_drivers/phy_rtc.c +++ b/csi_drivers/phy_rtc.c @@ -72,7 +72,7 @@ static const rtc_capabilities_t rtc_capabilities = { extern void WaitRTCCount(uint32_t rtcDelyCnt); -static uint8 phy_rc32k_calibration(void) +static uint8 rc32k_calibration(void) { int delay = 15000;//4000;//ZQ 20181203 for HCLK=48M uint32_t temp = 0; @@ -148,7 +148,7 @@ static uint8 rc32k_calibration_check(uint8 hLimt, uint8 lLimt, uint8 rdCnt, uint uint32 temp; while (calCnt--) { - rc0 = phy_rc32k_calibration(); + rc0 = rc32k_calibration(); if (rc0 < hLimt && rc0 > lLimt) { temp = rc32k_tracking_check(rdCnt, ckCnt); diff --git a/csi_drivers/spif.c b/csi_drivers/spif.c index c908237718c4486fcf5aef2915554a83e6a3497c..f737ee992b63431f6048b3f7207845636a43ec57 100644 --- a/csi_drivers/spif.c +++ b/csi_drivers/spif.c @@ -55,6 +55,11 @@ extern void spif_set_deep_sleep(void); extern void spif_release_deep_sleep(void); extern void spif_cmd(uint8_t op, uint8_t addrlen, uint8_t rdlen, uint8_t wrlen, uint8_t mbit, uint8_t dummy); extern void spif_rddata(uint8_t *data, uint8_t len); +extern void WaitRTCCount(uint32_t rtcDelyCnt); +extern uint8_t spif_flash_status_reg_0(void); +extern uint8_t spif_flash_status_reg_1(void); +extern void spif_wrdata(uint8_t* data, uint8_t len); +extern void ll_patch_restore(uint8_t flg); #define SPIF_TIMEOUT 1000000 @@ -98,6 +103,7 @@ __attribute__((section(".__sram.code"))) static inline uint32_t spif_lock() VIC->ICER[0] = 0xFFFFFFFF; //enable ll irq and tim1 irq VIC->ISER[0] = 0x100010; + ll_patch_restore(0); HAL_EXIT_CRITICAL_SECTION(); return vic_iser; } @@ -107,6 +113,7 @@ __attribute__((section(".__sram.code"))) static inline void spif_unlock(uint32_ _HAL_CS_ALLOC_(); HAL_ENTER_CRITICAL_SECTION(); VIC->ISER[0] = vic_iser; + ll_patch_restore(1); HAL_EXIT_CRITICAL_SECTION(); } @@ -131,7 +138,7 @@ __attribute__((section(".__sram.code"))) static inline void spif_unlock(uint32_ #define spif_wait_nobusy(flg, tout_ns, return_val) {if(_spif_wait_nobusy_x(flg, tout_ns)){if(return_val){ return return_val;}}} -__attribute__((section(".__sram.code"))) static void hal_cache_tag_flush(void) +__attribute__((section(".__sram.code"))) void hal_cache_tag_flush(void) { _HAL_CS_ALLOC_(); HAL_ENTER_CRITICAL_SECTION(); @@ -139,10 +146,10 @@ __attribute__((section(".__sram.code"))) static void hal_cache_tag_flush(void) volatile int dly = 8; if (cb == 0) { - AP_CACHE->CTRL0 = 0x02; + AP_PCR->CACHE_BYPASS = 1; } - + AP_CACHE->CTRL0 = 0x02; while (dly--) { ; }; @@ -154,10 +161,10 @@ __attribute__((section(".__sram.code"))) static void hal_cache_tag_flush(void) while (dly--) { ; }; - + AP_CACHE->CTRL0 = 0; if (cb == 0) { AP_PCR->CACHE_BYPASS = 0; - AP_CACHE->CTRL0 = 0; + } HAL_EXIT_CRITICAL_SECTION(); @@ -178,6 +185,7 @@ __attribute__((section(".__sram.code"))) static int _spif_wait_nobusy_x(uint8_t volatile int tout = (int)(tout_ns); for (; tout ; tout --) { + WaitRTCCount(1);//increase polling interval status = _spif_read_status_reg_x(); if ((status & flg) == 0) { @@ -188,6 +196,89 @@ __attribute__((section(".__sram.code"))) static int _spif_wait_nobusy_x(uint8_t return PPlus_ERR_BUSY; } +__attribute__((section(".__sram.code"))) uint16_t hal_flash_lock_status() +{ + uint16_t status = _spif_read_status_reg_x(); + if(s_spif_ctx.mid == FLASH_TH_ID) + return status&(FCMD_DATAPRO_AREA_512_TH | FCMD_SRP_REG_TH); + return status&(FCMD_DATAPRO_AREA_512 | FCMD_SRP_REG); +} + +__attribute__((section(".__sram.code"))) uint8_t hal_flash_write_disable(void) +{ + uint32_t cs = spif_lock(); + uint8_t status; + status = _spif_read_status_reg_x(); + if(status & SFLG_WEL) + { + AP_SPIF->fcmd = XFRD_FCMD_WRDI; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + } + spif_unlock(cs); + return 0; +} + +__attribute__((section(".__sram.code"))) int hal_flash_lock(uint16_t area) +{ + uint32_t cs = spif_lock(); + if(s_spif_ctx.mid == FLASH_TH_ID) + { + area |= FCMD_DATAPRO_AREA_512_TH; + area |= FCMD_SRP_REG_TH; + } + else + { + area &= FCMD_DATAPRO_AREA_512; + area |= FCMD_SRP_REG; + } + if(area != hal_flash_lock_status()) + { + if(s_spif_ctx.mid == FLASH_TH_ID) + { + area |= FCMD_SRP_REG_TH; + hal_flash_wr_status_reg((uint8 *)&area,2); + + } + else + { + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + AP_SPIF->fcmd = XFRD_FCMD_WREN; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + AP_SPIF->fcmd_wrdata[0] = area | FCMD_SRP_REG; + AP_SPIF->fcmd = XFRD_FCMD_WRST; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + } + } + spif_unlock(cs); + return 0; +} +__attribute__((section(".__sram.code"))) int hal_flash_unlock() +{ + + uint32_t cs = spif_lock(); + + if(FCMD_DATAPRO_AREA_NONE != hal_flash_lock_status()) + { + subWriteReg(&AP_SPIF->config, 14, 14, 0); //disable wp bit(14) + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + AP_SPIF->fcmd = XFRD_FCMD_WREN; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + AP_SPIF->fcmd_wrdata[0] = FCMD_DATAPRO_AREA_NONE; + AP_SPIF->fcmd = XFRD_FCMD_WRST; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + } + spif_unlock(cs); + return 0; +} + + __attribute__((section(".__sram.code"))) static int hal_flash_write(uint32_t addr, uint8_t *data, uint32_t size) { uint8_t retval; @@ -275,8 +366,9 @@ __attribute__((section(".__sram.code"))) int hal_flash_erase_sector(unsigned in __attribute__((section(".__sram.code"))) int hal_flash_erase_block64(unsigned int addr) { - uint32_t cs = spif_lock(); uint8_t retval; + uint32_t cs = spif_lock(); + uint32_t cb = AP_PCR->CACHE_BYPASS; SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); @@ -294,8 +386,9 @@ __attribute__((section(".__sram.code"))) int hal_flash_erase_block64(unsigned i __attribute__((section(".__sram.code"))) int hal_flash_erase_all(void) { - uint32_t cs = spif_lock(); uint8_t retval; + uint32_t cs = spif_lock(); + uint32_t cb = AP_PCR->CACHE_BYPASS; SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); @@ -311,6 +404,14 @@ __attribute__((section(".__sram.code"))) int hal_flash_erase_all(void) return retval; } +__attribute__((section(".__sram.code")))uint16_t hal_flash_area_choose() +{ + uint16_t area = FCMD_DATAPRO_AREA_384; + if(s_spif_ctx.mid == FLASH_TH_ID) + area = FCMD_DATAPRO_AREA_384_TH | FCMD_DATAPRO_AREA_384_TH_CMP; + return area; +} + /* basic spif driver */ @@ -376,6 +477,101 @@ uint32_t phy_flash_block64_erase(unsigned int addr) return hal_flash_erase_block64(addr); } +__attribute__((section(".__sram.code"))) int hal_flash_rd_status_reg(uint8* buf,bool low_8bit) +{ + uint8_t retval = PPlus_SUCCESS; + uint32_t cs = spif_lock(); + + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + + if(low_8bit == TRUE) + { + *buf = spif_flash_status_reg_0(); + } + else + { + *buf = spif_flash_status_reg_1(); + } + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + spif_unlock(cs); + return retval; +} + + +__attribute__((section(".__sram.code"))) int hal_flash_wr_status_reg(uint8* buf,int len) +{ + uint8_t retval = PPlus_SUCCESS; + //uint32_t result; + + if((len != 1) && (len != 2)) + { + return PPlus_ERR_INVALID_PARAM; + } + + uint32_t cs = spif_lock(); + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + + AP_SPIF->fcmd = XFRD_FCMD_WREN; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + + spif_wrdata(buf, len); + spif_cmd(FCMD_WRST, 0,0,len,0,0); + + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + + spif_unlock(cs); + return retval; +} + + + +__attribute__((section(".__sram.code"))) static int hal_flash_config_srp(void) +{ + uint8_t retval; + uint8_t status_reg[2]; + uint8_t status_reg_len = 1; + + FLASH_WP_HIGH_LEVEL; + retval = hal_flash_rd_status_reg(&status_reg[0],TRUE); + +#if (FLASH_STATUS_REGISTER_LEN == 1) + if((status_reg[0] & 0x80) != 0x80) //SRP=1 +#elif (FLASH_STATUS_REGISTER_LEN == 2) + retval = hal_flash_rd_status_reg(&status_reg[1],FALSE); + if(((status_reg[1] & 0x01) != 0x00) || ((status_reg[0] & 0x80) != 0x80)) //SRP1=0&& SRP0=1 +#endif + { +#if (FLASH_STATUS_REGISTER_LEN == 2) + status_reg_len = 2; + status_reg[1] &= ~(1<<0); +#endif + status_reg[0] |= (1<<7); + hal_flash_wr_status_reg(status_reg,status_reg_len); + } + + return retval; +} + +__attribute__((section(".__sram.code"))) int hal_flash_switch_hardware_protect_mode(void) +{ + uint8_t retval = hal_flash_config_srp(); + FLASH_WP_LOW_LEVEL; + return retval; +} + +__attribute__((section(".__sram.code"))) int hal_flash_switch_hardware_unprotect_mode(void) +{ + uint8_t retval = hal_flash_config_srp(); + FLASH_WP_HIGH_LEVEL; + return retval; +} + + /* cpi api */ @@ -738,3 +934,4 @@ int32_t csi_spiflash_power_control(spiflash_handle_t handle, /*csi_power_stat_e* return state; } + diff --git a/include/dw_dmac.h b/include/dw_dmac.h index 6ff772dbe72e2190d218ee4b97ce56de1ca8373f..64068c40e90593dac99a928d4bdade3b0c5a79a1 100644 --- a/include/dw_dmac.h +++ b/include/dw_dmac.h @@ -102,6 +102,7 @@ typedef enum { #define DMA_REG_Cfg 0x398 #define DMA_REG_ChEn 0x3a0 +#define DMA_MAX_TRANSPORT_SIZE(ch) ((ch == 0) ? 0x7ff : 0x1f) //typedef struct { // __IOM uint32_t SAR; /* offset: 0x00 (R/W) Channel Source Address Register */ // __IOM uint32_t DAR; /* offset: 0x04 (R/W) Channel Destination Address Register */ diff --git a/include/soc.h b/include/soc.h index 43af8e127d5da42d2da91e9e3bd4d5bd3fb04a2d..3402866488457b2c30e577624d2fae1d12878a6a 100644 --- a/include/soc.h +++ b/include/soc.h @@ -51,5 +51,6 @@ #define CONFIG_AES_NUM 1 #define CONFIG_PMU_NUM 1 #define CONFIG_ADC_NUM 1 - +#define CONFIG_OTP_BANK_SIZE 1024 +#define SHA_CONTEXT_SIZE 224 #endif /* _SOC_H_ */ diff --git a/include/spif.h b/include/spif.h index f9f4313d5b8e499b4f362a87f41f034aa0e5b0cf..5cff3a61baa05278a9da77451cc61a89d97716c6 100644 --- a/include/spif.h +++ b/include/spif.h @@ -25,6 +25,7 @@ //#include "drv_spiflash.h" //#include "soc.h" #include "types.h" +#include "rom_sym_def.h" #ifdef __cplusplus extern "C" { @@ -35,6 +36,27 @@ extern "C" { #define __IOM volatile /*! Defines 'read / write' structure member permissions */ #endif +typedef struct{ + uint8_t state; + uint32_t size; + + bool w_protect; + + uint8_t clk_div; + + uint32_t qspi_en; + uint32_t rd_instr; + uint32_t wr_instr; + uint32_t remap; + + /*device id*/ + uint8_t mid; + uint8_t mtype; //mempry type + uint8_t mcapc; //memory capcity +}spif_ctx_t; + +extern spif_ctx_t s_spif_ctx; + #define CONFIG_SPIFLASH_NUM 1 #define DEBUG_EN 1 //#define SPIF_ADDR_START 0x11005000 @@ -52,6 +74,12 @@ extern "C" { #define XFRD_FCMD_READ 0x801000B #define XFRD_FCMD_READ_DUAL 0x801003B #define XFRD_FCMD_READ_QUAD 0x801006B +#define XFRD_FCMD_WREN 0x6000001 +#define XFRD_FCMD_WRDI 0x4000001 //flash write disable +#define XFRD_FCMD_WRST 0x1008001 + + + #define FCMD_RESET 0x99 //reset @@ -81,6 +109,66 @@ extern "C" { #define FCMD_READQIO 0xeB //quad I/O fast read #define FCMD_READQIOW 0xe7 //quad I/O fast read word +#define FCMD_CMD_EXCUTE 0x01 +#define FCMD_SRP_REG 0x80 +#define FCMD_SRP_REG_TH 0x0080 + +#define FCMD_DATAPRO_AREA_NONE 0x00 +#define FCMD_DATAPRO_AREA_504 0x04 +#define FCMD_DATAPRO_AREA_496 0x08 +#define FCMD_DATAPRO_AREA_480 0x0c +#define FCMD_DATAPRO_AREA_448 0x10 +#define FCMD_DATAPRO_AREA_384 0x14 +#define FCMD_DATAPRO_AREA_384_TH 0x0008 +#define FCMD_DATAPRO_AREA_384_TH_CMP 0x4000 +#define FCMD_DATAPRO_AREA_256 0x18 +#define FCMD_DATAPRO_AREA_512 0x1c +#define FCMD_DATAPRO_AREA_512_TH 0x0000 + + + +#define FCMD_DATAPRO_NONE_BIT 0x00 +#define FCMD_DATAPRO_504_BIT 0x04 +#define FCMD_DATAPRO_496_BIT 0x08 +#define FCMD_DATAPRO_480_BIT 0x0c +#define FCMD_DATAPRO_448_BIT 0x10 +#define FCMD_DATAPRO_384_BIT 0x14 +#define FCMD_DATAPRO_256_BIT 0x18 +#define FCMD_DATAPRO_512_BIT 0x1c + + + + +#define FLASH_STATUS_REGISTER_LEN 1 + +#define XFRD_FCMD_WREN 0x6000001 +#define XFRD_FCMD_WRST 0x1008001 + +#define FLASH_WP_HIGH_LEVEL (AP_SPIF->config &= ~(1<<14)) +#define FLASH_WP_LOW_LEVEL (AP_SPIF->config |= (1<<14)) +#define FLASH_WP_LEVEL_GET (0x4000-(AP_SPIF->config & (1<<14))) + +#define FLASH_GD_ID 0xc8 +#define FLASH_XTX_ID 0x0b +#define FLASH_TH_ID 0xcd + + + +extern uint8_t spif_flash_status_reg_1(void); +extern int spif_read_id(uint32_t* pid); +extern void spif_wrdata(uint8_t* data, uint8_t len); + +__attribute__((section(".__sram.code"))) void hal_cache_tag_flush(void); + + +__attribute__((section(".__sram.code"))) int hal_flash_rd_status_reg(uint8* buf,bool low_8bit); +__attribute__((section(".__sram.code"))) int hal_flash_wr_status_reg(uint8* buf,int len); + +__attribute__((section(".__sram.code"))) int hal_flash_switch_hardware_protect_mode(void); +__attribute__((section(".__sram.code"))) int hal_flash_switch_hardware_unprotect_mode(void); +__attribute__((section(".__sram.code"))) uint8_t hal_flash_write_disable(void); + + #ifdef __cplusplus } #endif diff --git a/misc/rom_sym_def.h b/misc/rom_sym_def.h index 7ed7555bc1b8a06d2c68a16c937e7b6d8ca249df..0e106ac316b0bac9616aa0a06be074968366210b 100644 --- a/misc/rom_sym_def.h +++ b/misc/rom_sym_def.h @@ -4,6 +4,8 @@ #define __ROM_SYM_H__ #ifdef USE_ROMSYM_ALIAS +#define g_system_reset_cause _symrom_g_system_reset_cause +#define SystemResetCause _symrom_SystemResetCause #define WaitMs _symrom_WaitMs #define WaitRTCCount _symrom_WaitRTCCount #define WaitUs _symrom_WaitUs @@ -40,6 +42,7 @@ #define conn_param _symrom_conn_param #define connUpdateTimer _symrom_connUpdateTimer #define counter_tracking _symrom_counter_tracking +#define g_llScanMode _symrom_g_llScanMode #define crc16_rom _symrom_crc16 #define ctrlToHostEnable _symrom_ctrlToHostEnable #define dataPkt _symrom_dataPkt @@ -569,7 +572,7 @@ #define LL_SetPeriodicAdvEnable _symrom_LL_SetPeriodicAdvEnable #define LL_SetPeriodicAdvParameter _symrom_LL_SetPeriodicAdvParameter #define LL_SetPhyMode _symrom_LL_SetPhyMode -#define LL_SetRandomAddress _symrom_LL_SetRandomAddress +//#define LL_SetRandomAddress _symrom_LL_SetRandomAddress #define LL_SetResolvablePrivateAddressTimeout _symrom_LL_SetResolvablePrivateAddressTimeout #define LL_SetScanControl _symrom_LL_SetScanControl #define LL_SetScanParam _symrom_LL_SetScanParam @@ -873,6 +876,7 @@ #define spif_set_deep_sleep _symrom_spif_set_deep_sleep #define spif_wrdata _symrom_spif_wrdata #define spif_write _symrom_spif_write +#define spif_read_id _symrom_spif_read_id #define spif_write_protect _symrom_spif_write_protect #define sram_ret_patch _symrom_sram_ret_patch #define supportedCmdsTable _symrom_supportedCmdsTable @@ -909,6 +913,15 @@ #define rom_hal_uart_send_buff _symrom_hal_uart_send_buff #define rom_hal_uart_tx _symrom_hal_uart_tx #define move_to_slave_function0 _symrom_move_to_slave_function0 +#define ll_scheduler0 _symrom_ll_scheduler0 +#define g_llAdvMode _symrom_g_llAdvMode +#define LL_AdvSetTerminatedCback _symrom_LL_AdvSetTerminatedCback +#define g_timer4_irq_pending_time _symrom_g_timer4_irq_pending_time +#define llSetupNextSlaveEvent0 _symrom_llSetupNextSlaveEvent0 +#define llProcessSlaveControlPacket0 _symrom_llProcessSlaveControlPacket0 +#define llProcessMasterControlPacket0 _symrom_llProcessMasterControlPacket0 +#define LL_slave_conn_event0 _symrom_LL_slave_conn_event0 +#define LL_SetScanParam0 _symrom_LL_SetScanParam0 #endif #endif diff --git a/package.yaml b/package.yaml index 39b02164cf97057f1f80a9f6e933dab0db0ece6d..fca480f510c1e95f9a5f61427f38ae127638f56f 100755 --- a/package.yaml +++ b/package.yaml @@ -145,6 +145,7 @@ def_config: # 组件的可配置项 AOS_MAX_APP_PRI: 14 CONFIG_KERNEL_PRI_MAX: 14 CONFIG_SYSTICK_HZ: 1000 + CONFIG_CALIBRATE_WITH_FREQOFF: 1 # CONFIG_DEBUG: y # CONFIG_PARAM_NOT_CHECK: y # CONFIG_CLI: y diff --git a/phy_pmu.c b/phy_pmu.c index da0550eb9d18c8f6d49e6354f54c0e1f715da3d2..fa1d8029878dc94c6f90ab587c83c92353be0ad7 100755 --- a/phy_pmu.c +++ b/phy_pmu.c @@ -25,7 +25,7 @@ #include #include - +#include "global_config.h" #define ERR_PMU(errno) (CSI_DRV_ERRNO_PMU_BASE | errno) #define PMU_NULL_PARAM_CHK(para) HANDLE_PARAM_CHK(para, ERR_PMU(DRV_ERROR_PARAMETER)) @@ -36,6 +36,7 @@ typedef struct { extern int32_t arch_do_cpu_save(void); extern int32_t arch_do_cpu_resume(void); +extern uint32_t rtc_get_counter(void); static uint8_t pmu_power_status; static phy_pmu_priv_t pmu_handle[CONFIG_PMU_NUM]; @@ -73,6 +74,9 @@ static void do_prepare_sleep_action(int32_t idx) static void do_wakeup_sleep_action(int32_t idx) { int i = 0; + + subWriteReg(&AP_SPIF->config, 14, 14, 1); //enable wp bit(14) + /* resume vic register */ VIC->ISER[0U] = vic_regs_saved[0]; VIC->ISPR[0U] = vic_regs_saved[1]; @@ -106,7 +110,10 @@ pmu_handle_t csi_pmu_initialize(int32_t idx, pmu_event_cb_t cb_event) pmu_priv->idx = idx; pmu_priv->cb = cb_event; - JUMP_FUNCTION(WAKEUP_PROCESS) = (uint32_t)arch_do_cpu_resume; + /* + WAKEUP_PROCESS jump func will be registed as arch_do_cpu_resume in enter_sleep_process + */ + //JUMP_FUNCTION(WAKEUP_PROCESS) = (uint32_t)arch_do_cpu_resume; return (pmu_handle_t)pmu_priv; } @@ -188,6 +195,18 @@ int32_t csi_pmu_enter_sleep(pmu_handle_t handle, pmu_mode_e mode) do_prepare_sleep_action(0); if (arch_do_cpu_save() == 0) { + subWriteReg(0x4000f03c, 2, 0, 0); //switch hclk to RC32M + uint32_t rtc_current; + extern uint32 *pGlobal_config; + rtc_current = rtc_get_counter(); + if(((AP_AON->RTCCC0 - rtc_current)>(pGlobal_config[MAX_SLEEP_TIME]>>4)) || + ((AP_AON->RTCCC0 - rtc_current)<(pGlobal_config[MIN_SLEEP_TIME]>>6))) + { + extern void just_enter_sleep(uint32 time); + just_enter_sleep(33000); + } + extern int32_t arch_do_cpu_resume(void); + JUMP_FUNCTION(WAKEUP_PROCESS) = (uint32_t)arch_do_cpu_resume; enter_sleep_off_mode(SYSTEM_SLEEP_MODE); } @@ -203,6 +222,7 @@ int32_t csi_pmu_enter_sleep(pmu_handle_t handle, pmu_mode_e mode) if (pmu_priv->cb) { pmu_priv->cb(pmu_priv->idx, PMU_EVENT_PREPARE_SLEEP, mode); } + set_sleep_flag(0); *((unsigned int *)0x4000f0c0) = 0x2; subWriteReg(0x4000f01c, 6, 6, 0x00); //disable software control enter_sleep_off_mode(SYSTEM_OFF_MODE); @@ -215,6 +235,7 @@ int32_t csi_pmu_enter_sleep(pmu_handle_t handle, pmu_mode_e mode) return 0; } + /** \brief Config the wakeup source. \param[in] handle pmu handle to operate diff --git a/pm.c b/pm.c index 21e8dd08ad613f2abde36a7d6c1fb1edff0cef27..2483d07c9ddeeb9e3111c5a6fc19c0ae46f9562c 100644 --- a/pm.c +++ b/pm.c @@ -22,6 +22,7 @@ #include "pwrmgr.h" #include "pin.h" #include "pm.h" +#include "spif.h" #define DBGIO_LL_TRIG P14 #define DBGIO_LL_IRQ P15 @@ -33,6 +34,7 @@ #define MIN_TIME_TO_SLEEP 50 //ms #define MIN_TIME_TO_SUSPEND 10000 //ms + extern int g_spif_ref_clk; //pwrmgr_attribute_t pwrmgr_attribute; extern uint32_t ll_remain_time; @@ -40,7 +42,7 @@ extern uint32_t g_wakeup_rtc_tick;// = 0; extern uint32_t sleep_flag;// = 0; // when sleep, set this value to SLEEP_MAGIC. when wakeup, set this value to 0 extern uint32_t osal_sys_tick; -extern uint32_t g_counter_traking_avg ;// = 3906; +extern uint32_t g_counter_traking_avg ;// = 3906;7812(bug fix 2021/11/15) extern volatile uint32_t llWaitingIrq; //used for sleep timer sync @@ -65,6 +67,11 @@ extern uint32 read_LL_remainder_time(void); extern uint32_t read_current_fine_time(void); extern int clk_spif_ref_clk(sysclk_t spif_ref_sel); extern void hal_mpu_config(void); +extern void drv_reboot(int cmd); +extern void *osal_memcpy( void *dst, const void GENERIC *src, unsigned int len ); +extern void *osal_memset( void *dest, uint8 value, int len ); +extern __attribute__((section(".__sram.code"))) void config_reset_handler(int rstMod); +extern void jump_area_init(void); static uint32_t irq_flags; @@ -102,6 +109,10 @@ pm_wakeup_by_io_cb g_wakeup_cb = NULL; #define CONFIG_WDT 0 #endif +#ifndef CONFIG_LOW_POWER_WAKE_DEBUG +#define CONFIG_LOW_POWER_WAKE_DEBUG 0 +#endif + #if (CONFIG_WDT > 0) #define WDT_TIMEOUT 2000 static wdt_handle_t wdt_handle = NULL; @@ -200,7 +211,7 @@ void wdt_wakeup_action() while (delay-- > 0); - AP_WDT->CR = 0x1F; + AP_WDT->CR = 0x1D; csi_wdt_set_timeout(wdt_handle, WDT_TIMEOUT); #endif @@ -282,71 +293,6 @@ __attribute__((section(".__sram.code"))) static void usart_wakeup_action(void) registers_save((uint32_t *)addr + 3, &usart_regs_saved[3], 2); } #endif -#define CRY32_2_CYCLE_16MHZ_CYCLE_MAX (976 + 196) // tracking value range std +/- 20% -#define CRY32_2_CYCLE_16MHZ_CYCLE_MIN (976 - 196) -#define CRY32_2_CYCLE_DELTA_LMT (97) - -uint32_t g_xtal16M_waitCnt=0; -uint32_t g_xtal16M_tmp=0; -volatile uint8_t g_rc32kCalRes; - -extern uint8 rc32k_calibration(void); - -void rf_calibrate2(void) -{ - //========== do rf tp cal for tx and rx dcoffset cal - rf_phy_ana_cfg(); - rf_tpCal_gen_cap_arrary(); //generate the tpCal cap arrary - //rf_tpCal_cfg(/*rfChn*/2); - rf_rxDcoc_cfg(/*rfChn*/88,/*bwSet*/1,&g_rfPhyRxDcIQ); //set the rfChn as 2488 for BW=1MHz - g_rc32kCalRes = rc32k_calibration(); -} - -static void check_16MXtal_by_rcTracking(void) -{ - /* - for fiset wakeupini, not do rcCal, just skip the rcTacking - */ - if(g_rc32kCalRes==0xFF) - { - WaitRTCCount(30); - return; - } - - uint32_t temp,temp1,waitCnt; - // ======== enable tracking 32KHz RC timer with 16MHz crystal clock - temp = *(volatile uint32_t *)0x4000f040; - *(volatile uint32_t *)0x4000f040 = temp | BIT(18); - - waitCnt=0; - - temp = *(volatile uint32_t *)0x4000f05C; - *(volatile uint32_t *)0x4000f05C = (temp & 0xfffefe00) | 0x0028; - WaitRTCCount(2); - temp = (*(volatile uint32_t *)0x4000f064 & 0x1ffff); - - while(1) // - { - // 1. read RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle - waitCnt++; - WaitRTCCount(2); - temp1 = (*(volatile uint32_t *)0x4000f064 & 0x1ffff); - - if( temp1>CRY32_2_CYCLE_16MHZ_CYCLE_MIN && - temp1CRY32_2_CYCLE_16MHZ_CYCLE_MIN && - temp temp1 ? (temp -temp1):(temp1>temp)))waitCnt) ? g_xtal16M_waitCnt: waitCnt; -} uint8_t isSleepAllowInPM(void) { @@ -400,6 +346,22 @@ void set_sleep_flag(int flag) // *(volatile uint32_t *) 0x4000f024 |= 1 << 15; //enable comparator0 inerrupt //*(volatile uint32_t *) 0x4000f024 |= 0x148000; // combine above 3 statement to save MCU time +void rc32k_cap_cal(uint32_t temp) +{ + uint32_t rccap; + if((temp > CRY32_16_CYCLE_16MHZ_CYCLE_MAX) && ((*(volatile uint32_t *) 0x4000f018 & 0x7e) > 0)) + { + rccap = ((read_reg(0x4000f018)>>1) & 0x3f) - 1; + subWriteReg(0x4000f018,6,1,rccap); + WaitRTCCount(3); + } + else if((temp < CRY32_16_CYCLE_16MHZ_CYCLE_MIN) && ((*(volatile uint32_t *) 0x4000f018 & 0x7e) < 0x7e)) + { + rccap = ((read_reg(0x4000f018)>>1) & 0x3f) + 1; + subWriteReg(0x4000f018,6,1,rccap); + WaitRTCCount(3); + } +} void enterSleepProcess1(uint32_t time) { @@ -410,7 +372,7 @@ void enterSleepProcess1(uint32_t time) if (pGlobal_config[LL_SWITCH] & RC32_TRACKINK_ALLOW) { // 1. read RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle - temp = *(volatile uint32_t *)0x4000f064 & 0x1ffff; + temp = AP_PCRM->cal_ro1 & 0x1ffff; //====== assume the error cnt is (n+1/2) cycle,for this case, it should be 9 or 10 // error_delt = (temp>STD_CRY32_8_CYCLE_16MHZ_CYCLE) @@ -433,7 +395,8 @@ void enterSleepProcess1(uint32_t time) counter_tracking = (temp > CRY32_16_CYCLE_16MHZ_CYCLE_MAX) ? counter_tracking : temp; //20181204 filter the counter_tracking spur, due to the N+1 issue - + rc32k_cap_cal(temp); + if (g_counter_traking_cnt < 1000) { //before traking converage use hard limitation counter_tracking = (counter_tracking > CRY32_16_CYCLE_16MHZ_CYCLE_MAX || counter_tracking < CRY32_16_CYCLE_16MHZ_CYCLE_MIN) @@ -443,8 +406,8 @@ void enterSleepProcess1(uint32_t time) } else { //after tracking converage use soft limitation - counter_tracking = (counter_tracking > g_counter_traking_avg + (g_counter_traking_avg >> 8) - || counter_tracking < g_counter_traking_avg - (g_counter_traking_avg >> 8)) + counter_tracking = (counter_tracking > g_counter_traking_avg + (g_counter_traking_avg >> 3) + || counter_tracking < g_counter_traking_avg - (g_counter_traking_avg >> 3)) ? g_counter_traking_avg : counter_tracking; } @@ -502,7 +465,6 @@ void enterSleepProcess1(uint32_t time) // 5. set sleep flag(AON reg & retention SRAM variable) set_sleep_flag(1); - // 6. trigger system sleep csi_pmu_enter_sleep(pmu_handle, PMU_MODE_DORMANT); } @@ -512,7 +474,11 @@ void osal_pwrmgr_powerconserve_dummy(void) //do nothing return; } - +void sram_HardFault_Handler(void) +{ + subWriteReg(&(AP_PCRM->CLKSEL),2,0,SYS_CLK_RC_32M); + drv_reboot(1); +} /****************************************** // SOC interfaces ******************************************/ @@ -534,6 +500,9 @@ int sys_soc_suspend(uint32_t suspend_tick) RHINO_CPU_INTRPT_DISABLE(); irq_flags = psr; + extern void check_hclk_by_rc32k_rtc(void); + check_hclk_by_rc32k_rtc(); + if (!isSleepAllowInPM()) { RHINO_CPU_INTRPT_ENABLE(); __WFI(); @@ -702,6 +671,289 @@ int sys_soc_suspend(uint32_t suspend_tick) #define BASE_TIME_UNITS (0x3fffff) #endif +#define CRY32_2_CYCLE_16MHZ_CYCLE_MAX (976 + 98) // tracking value range std +/- 20% +#define CRY32_2_CYCLE_16MHZ_CYCLE_MIN (976 - 98) +#define CRY32_2_CYCLE_DELTA_LMT (19) +#define TRACKING_96M_16M_MULTI6_DELTA_LIMIT (10*6) //96M:16M*6 +- 1% +#define DLL_ENABLE_MAX (5) +#define TRACKING_16M_TICK_MAX (3300) +#define TRACKING_MAX_SLEEPTIME (1980000) //MAX sleep time is 60 seconds. + +//volatile uint8_t g_rc32kCalRes = 0xff; +uint32_t g_xtal16M_tmp=0; +uint32_t g_xtal96M_temp=0; +uint32_t DLL_enable_num=1; +uint32_t tracking_16M_num = 0; +extern void Reset_Handler(); +extern int SystemResetCause(void); +extern uint32_t g_system_reset_cause; +void _rom_data_init(void) +{ + //copy rom data section + osal_memcpy((void *)0x1fff0800,(const void GENERIC *)0x17c7c,(0x1fff0924-0x1fff0800)); + //clr rom bss section skip g_top_trapstack + osal_memset((void *)0x1fff0924,0,(0x1fff0988-0x1fff0924)); + osal_memset((void *)0x1fff0b8c,0,(0x1fff1a3c-0x1fff0b8c)); +} + +void sram_reset_handler(void) +{ + subWriteReg(&AP_SPIF->config, 14, 14, 1); //enable wp bit(14) + + AP_PCR->CACHE_BYPASS = 1;//disable cache + AP_SPIF->fcmd_wrdata[0] = 0x94; + clk_init(SYS_CLK_RC_32M); + config_reset_handler(1); + + + + g_spif_ref_clk = SYS_CLK_RC_32M; + hal_cache_init(); + hal_flash_write_disable(); + hal_mpu_config(); + + _rom_data_init(); + + + + /* + update reset cause, add 0x80 to mark the reset path from sram_reset_handler + */ + SystemResetCause(); + g_system_reset_cause |=0x80; + + //check just_sleep_reset flg + if(((AP_AON->SLEEP_R[1] & 0x0f)>>2)) + g_system_reset_cause |=0x40; + + Reset_Handler(); +} +void just_enter_sleep(uint32 time) +{ + if (time < MIN_TIME_TO_SLEEP) + time = MIN_TIME_TO_SLEEP; + + jump_area_init(); + JUMP_FUNCTION(WAKEUP_PROCESS) = (uint32_t)sram_reset_handler; + + /* set sleep flag , rom boot will check the flag and + set reset path from WAKEUP_PROCESS */ + phy_gpioretention_disable(); + set_sleep_flag(1); + + subWriteReg(&(AP_AON->PMCTL2_0),6,6,0x00); //disable software control + // config wakeup timer + uint32_t sleep_tick_now = AP_AON->RTCCNT; + WaitRTCCount(1); + AP_AON->RTCCC0 = sleep_tick_now + time; + AP_AON->RTCCTL |= BIT(15)|BIT(18)|BIT(20); + + // clear sram retention + // hal_pwrmgr_RAM_retention_clr(); + + /** + config reset casue as RSTC_WARM_NDWC + reset path walkaround dwc + */ + if (((AP_AON->SLEEP_R[1] & 0xFF00) >>8) > 100) + AP_AON->SLEEP_R[1]=0; + + AP_AON->SLEEP_R[0]=4; + + // trigger system sleep + enter_sleep_off_mode(SYSTEM_SLEEP_MODE); +} + + +#define RTC_32KRC_3_CYCLE_LIMIT_LOW (60) //3*30.5 normal pclk +#define RTC_32KRC_3_CYCLE_LIMIT_HIGH (120) //3*30.5 normal pclk + +void check_hclk_by_rc32k_rtc(void) +{ + WaitRTCCount(1); + uint32_t t0 = read_current_fine_time(); + WaitRTCCount(3); + uint32_t t1 = read_current_fine_time(); + if((TIME_DELTA(t1,t0)RTC_32KRC_3_CYCLE_LIMIT_HIGH)) + { + subWriteReg(&(AP_PCRM->CLKSEL), 2, 0, 0); //switch hclk to RC32M + just_enter_sleep(33000); + + } + + +} + + +void check_16MXtal_by_rcTracking(void) +{ + /* + + for fiset wakeupini, not do rcCal, just skip the rcTacking + */ + + if((AP_AON->SLEEP_R[1] & 0x80) == 0) + { + WaitRTCCount(60); + return; + } + + uint32_t tracking_start = rtc_get_counter(); + + uint32_t temp,temp1; + uint32_t temp31,temp32,temp33; + uint32_t temp_min,temp_max; + + // ======== enable tracking 32KHz RC timer with 16MHz crystal clock + temp = AP_PCRM->CLKHF_CTL0; + AP_PCRM->CLKHF_CTL0 = temp | BIT(18); + temp = AP_PCRM->cal_rw; + AP_PCRM->cal_rw = (temp & 0xfffefe00) | 0x0028; + WaitRTCCount(3); + + temp31 = (AP_PCRM->cal_ro1 & 0x1ffff); + WaitRTCCount(3); + + temp32 = (AP_PCRM->cal_ro1 & 0x1ffff); + WaitRTCCount(3); + + temp33 = (AP_PCRM->cal_ro1 & 0x1ffff); + + while(1) + { + temp_min = (temp31 >=temp32) ? (temp32):(temp31); + temp_min = (temp_min >=temp33) ? (temp33):(temp_min); + temp_max = (temp31 >=temp32) ? (temp31):(temp32); + temp_max = (temp_max >=temp33) ? (temp_max):(temp33); + + if( temp31>CRY32_2_CYCLE_16MHZ_CYCLE_MIN && + temp31CRY32_2_CYCLE_16MHZ_CYCLE_MIN && + temp32 CRY32_2_CYCLE_16MHZ_CYCLE_MIN && + temp33 SLEEP_R[1]),3,2,0); + + //reset tracking sleep num + subWriteReg(&(AP_AON->SLEEP_R[1]),15,8,0); + break; + } + + temp31= temp32; + temp32 = temp33; + WaitRTCCount(3); + temp33 = (AP_PCRM->cal_ro1 & 0x1ffff); + + //check tracking cost + uint32_t tracking_end = rtc_get_counter(); + uint32_t tracking_16M_tick = (tracking_end>=tracking_start) ? (tracking_end-tracking_start) : (0xffffffff-tracking_start+tracking_end); + if(tracking_16M_tick >= TRACKING_16M_TICK_MAX) + { + uint32_t tracking_sleep_num = (AP_AON->SLEEP_R[1] & 0xFF00) >>8; + subWriteReg(&(AP_AON->SLEEP_R[1]),15,8,tracking_sleep_num+1); + subWriteReg(&(AP_AON->SLEEP_R[1]),3,2,1); + if ((uint32_t)((uint32_t)1 << tracking_sleep_num)*33000 < TRACKING_MAX_SLEEPTIME) + { + just_enter_sleep((1 << tracking_sleep_num)*33000); + } + else + { + just_enter_sleep(TRACKING_MAX_SLEEPTIME); + } + } + + } + + temp1 = (AP_PCRM->cal_ro1 & 0x1ffff); + + subWriteReg(&(AP_PCRM->cal_rw),3,3,0); + + g_xtal16M_tmp = temp1; +} + +void check_96MXtal_by_rcTracking(void) +{ + uint32_t temp,temp1; + //for first wakeupinit + + if((AP_AON->SLEEP_R[1] & 0x80) == 0) + { + //enable DLL + temp = AP_PCRM->CLKHF_CTL1; + AP_PCRM->CLKHF_CTL1 = temp | BIT(7); + WaitRTCCount(3); + return; + } + + DLL_enable_num=0; + + // ======== enable tracking 32KHz RC timer with 16MHz crystal clock + temp = AP_PCRM->CLKHF_CTL0; + AP_PCRM->CLKHF_CTL0 = temp | BIT(18); + + while(1) + { + //enable DLL + temp = AP_PCRM->CLKHF_CTL1; + AP_PCRM->CLKHF_CTL1 = temp | BIT(7); + WaitRTCCount(3); + DLL_enable_num++; + + // //enable digclk 96M + + temp = AP_PCRM->CLKHF_CTL1; + AP_PCRM->CLKHF_CTL1 = temp | BIT(16); + for(uint8 index=0;index<5;index++) + { + temp = AP_PCRM->cal_rw; + AP_PCRM->cal_rw = (temp & 0xfffefe00) | 0x0028 | BIT(16); + WaitRTCCount(3); + temp1 = (AP_PCRM->cal_ro1 & 0x1ffff); + subWriteReg(&(AP_PCRM->cal_rw),3,3,0); + if( (g_xtal16M_tmp*6 >=temp1 ? (g_xtal16M_tmp*6 -temp1):(temp1-g_xtal16M_tmp*6))cal_rw),16,16,0); + subWriteReg(&(AP_PCRM->CLKHF_CTL1),16,16,0); + g_xtal96M_temp = temp1; + subWriteReg(&(AP_AON->SLEEP_R[1]),5,4,0); + return; + } + + } + + //disable 96M + subWriteReg(&(AP_PCRM->cal_rw),16,16,0); + subWriteReg(&(AP_PCRM->CLKHF_CTL1),16,16,0); + + //should not be here + + if(DLL_enable_num>= DLL_ENABLE_MAX) + { + subWriteReg(&(AP_AON->SLEEP_R[1]),5,4,1); + just_enter_sleep(60); + } + + //disable DLL + + subWriteReg(&(AP_PCRM->CLKHF_CTL1),7,7,0); + WaitRTCCount(3); + + //update g_xtal16M_tmp + temp = AP_PCRM->cal_rw; + AP_PCRM->cal_rw = (temp & 0xfffefe00) | 0x0028 ; + WaitRTCCount(3); + g_xtal16M_tmp = (AP_PCRM->cal_ro1 & 0x1ffff); + + subWriteReg(&(AP_PCRM->cal_rw),3,3,0); + } + +} + +uint32_t tracking_cnt=0; void wakeup_init1() { uint8_t pktFmt = 1; // packet format 1: BLE 1M uint32_t temp; @@ -713,7 +965,27 @@ void wakeup_init1() { //each rtc count is about 30.5us //after 15count , xtal will be feedout to dll and doubler //WaitRTCCount(pGlobal_config[WAKEUP_DELAY]); - check_16MXtal_by_rcTracking(); + if(g_system_clk == SYS_CLK_XTAL_16M) + { + //WaitRTCCount(pGlobal_config[WAKEUP_DELAY]); + WaitRTCCount(10); + check_16MXtal_by_rcTracking(); + } + else + { + uint32_t tracking_c1,tracking_c2; + tracking_c1 = rtc_get_counter(); + WaitRTCCount(30); + subWriteReg(&(AP_AON->SLEEP_R[1]),1,0,0); + check_16MXtal_by_rcTracking(); + WaitRTCCount(6); + subWriteReg(&(AP_AON->SLEEP_R[1]),1,0,1); + check_96MXtal_by_rcTracking(); + subWriteReg(&(AP_AON->SLEEP_R[1]),1,0,2); + tracking_c2 = rtc_get_counter(); + tracking_cnt = (tracking_c2>=tracking_c1) ? (tracking_c2-tracking_c1) : (0xffffffff-tracking_c1+tracking_c2); + pGlobal_config[WAKEUP_ADVANCE] =1500+30*tracking_cnt; + } // ============ config BB Top *(volatile uint32_t *) 0x40030000 = 0x3d068001; // set tx pkt =2 @@ -721,7 +993,7 @@ void wakeup_init1() { *(volatile uint32_t *) 0x400300a4 = 0x140; //[6] for tpm_en clk_init(g_system_clk); - + subWriteReg(&(AP_AON->SLEEP_R[1]),1,0,3); hal_wakeup_irq_config(); // ========== init timers @@ -745,8 +1017,8 @@ void wakeup_init1() { ll_hw_ign_rfifo(LL_HW_IGN_SSN | LL_HW_IGN_CRC | LL_HW_IGN_EMP); // ======== enable tracking 32KHz RC timer with 16MHz crystal clock - temp = *(volatile uint32_t *)0x4000f05C; - *(volatile uint32_t *)0x4000f05C = (temp & 0xfffefe00) | 0x0108; //[16] 16M [8:4] cnt [3] track_en_rc32k + temp = AP_PCRM->cal_rw; + AP_PCRM->cal_rw = (temp & 0xfffefe00) | 0x0108; //[16] 16M [8:4] cnt [3] track_en_rc32k } static void hw_spif_cache_config(void) { @@ -755,6 +1027,8 @@ static void hw_spif_cache_config(void) { hal_cache_init(); } +extern void efuse_init(void); + int sys_soc_resume(int pm_state) { uint32_t current_RTC_tick; uint32_t wakeup_time, wakeup_time0, next_time; @@ -764,6 +1038,15 @@ int sys_soc_resume(int pm_state) { if (pm_state == SYS_POWER_STATE_RUN) { return 0; } + + AP_PCR->CACHE_BYPASS = 1;//disable cache + AP_SPIF->fcmd_wrdata[0] = 0x94; + + config_reset_handler(1); + + efuse_init(); + + wdt_wakeup_action(); DBG_GPIO_WRITE(DBGIO_APP_WAKEUP, 1); // restore HW registers @@ -789,14 +1072,14 @@ int sys_soc_resume(int pm_state) { //config the tx2rx timing according to the g_rfPhyPktFmt ll_hw_tx2rx_timing_config(g_rfPhyPktFmt); - if (pGlobal_config[LL_SWITCH] & LL_RC32K_SEL) { - subWriteReg(0x4000f01c, 16, 7, 0x3fb); //software control 32k_clk - subWriteReg(0x4000f01c, 6, 6 , 0x01); //enable software control + // if (pGlobal_config[LL_SWITCH] & LL_RC32K_SEL) { + // subWriteReg(0x4000f01c, 16, 7, 0x3fb); //software control 32k_clk + // subWriteReg(0x4000f01c, 6, 6 , 0x01); //enable software control - } else { - subWriteReg(0x4000f01c, 9, 8, 0x03); //software control 32k_clk - subWriteReg(0x4000f01c, 6, 6, 0x00); //disable software control - } + // } else { + // subWriteReg(0x4000f01c, 9, 8, 0x03); //software control 32k_clk + // subWriteReg(0x4000f01c, 6, 6, 0x00); //disable software control + // } //20181201 by ZQ //restart the TIM2 to align the RTC @@ -924,7 +1207,7 @@ int sys_soc_resume(int pm_state) { ll_debug_output(DEBUG_WAKEUP); - set_sleep_flag(0); +// set_sleep_flag(0); DBG_GPIO_WRITE(DBGIO_APP_WAKEUP, 1); @@ -932,12 +1215,27 @@ int sys_soc_resume(int pm_state) { hal_mpu_config(); //clk_spif_ref_clk(g_spif_ref_clk); - + /* clear tick irq state by reading reg */ + int count; + unsigned int v = *((volatile unsigned int *) (0xE000E010)); + while((v & 0x10000) > 0) + { + v = *((volatile unsigned int *) (0xE000E010)); + count++; + } + #if (CONFIG_LOW_POWER_WAKE_DEBUG == 1) + gpio_write(P25,1); + gpio_write(P25,0); + #endif CPSR_ALLOC(); psr = irq_flags; RHINO_CPU_INTRPT_ENABLE(); - wdt_wakeup_action(); +// wdt_wakeup_action(); + #if(CONFIG_LOW_POWER_WAKE_DEBUG == 1) + gpio_write(P33,1); + gpio_write(P33,0); + #endif //usart_wakeup_action(); pm_after_sleep_action(); diff --git a/port_s.S b/port_s.S index a3b38f67e3693ea5968d48bb37f2b73c5be4923e..38152f3d3b6fc31dc5c468ae872e8a221e5d21fa 100644 --- a/port_s.S +++ b/port_s.S @@ -218,7 +218,7 @@ tspend_handler: jbsr krhino_stack_ovf_check #endif -#if (RHINO_CONFIG_TASK_SCHED_STATS > 0) +#if (RHINO_CONFIG_SYS_STATS > 0) jbsr krhino_task_sched_stats_get #endif diff --git a/reboot.c b/reboot.c index b64b5013655046e0d5ffdff16e64d0273b403468..3c2a4bb0f959add686419ef21429b49c63db9547 100644 --- a/reboot.c +++ b/reboot.c @@ -14,27 +14,49 @@ #include #include #include +#include "jump_function.h" + +#define RST_FROM_ROM_BOOT 0 +#define RST_FROM_APP_RST_HANDLER 1 + extern size_t cpu_intrpt_save(void); +extern void sram_reset_handler(void); +extern void set_sleep_flag(int flag); + +__attribute__((section(".__sram.code"))) void config_reset_handler(int rstMod) +{ + if(rstMod==RST_FROM_ROM_BOOT) + { + set_sleep_flag(0); + } + else + { + JUMP_FUNCTION(WAKEUP_PROCESS) = (uint32_t)sram_reset_handler; + extern void trap_c(uint32_t *regs); + extern void sram_HardFault_Handler(void); + JUMP_FUNCTION(CK802_TRAP_C) = (uint32_t)&sram_HardFault_Handler; //register trap irq handler + set_sleep_flag(1); + } +} __attribute__((section(".__sram.code"))) void drv_reboot(int cmd) { csi_irq_save(); - - volatile int dly = 100; - - //cache rst + AP_PCR->CACHE_BYPASS = 1; +// hal_flash_write_disable(); +// AP_SPIF->config = 0; AP_PCR->CACHE_RST = 0; - while (dly--) {}; - - AP_PCR->CACHE_RST = 0x03; - - //cache flush tag - AP_CACHE->CTRL0 = 0x03; - - //cache enable - AP_PCR->CACHE_BYPASS = 1; + // config reset path , from rom or app + config_reset_handler(cmd); + /** + config reset casue as RSTC_WARM_NDWC + reset path walkaround dwc + */ + AP_AON->SLEEP_R[0]=4; + + AP_AON->SLEEP_R[1]=0; *(volatile uint32_t *) 0x40000004 = 0x00; diff --git a/startup.S b/startup.S index 9e110598c00c2b28b29c4288cb2ee647e0580869..c8077d39a2535aa0245f0dd5e98a2b924f84d5be 100644 --- a/startup.S +++ b/startup.S @@ -32,9 +32,6 @@ .globl __Vectors .type __Vectors, @object __Vectors: - .long Reset_Handler - .size __Vectors, . - __Vectors - br Reset_Handler .align 2 .long 0x594B5343 /* CSKY ASCII */ diff --git a/system.c b/system.c index 1722b794d43b7cb9fdf121c0f3aa312aaedce869..d99e7fa14e1c94334c153a958c65590b1dfee2a4 100644 --- a/system.c +++ b/system.c @@ -35,6 +35,11 @@ #include "sys_freq.h" #include #include "pm.h" +#include "spif.h" + +#ifndef CONFIG_SYSTICK_HZ +#define CONFIG_SYSTICK_HZ 100 +#endif extern volatile sysclk_t g_system_clk; int g_spif_ref_clk = SYS_CLK_DLL_64M; @@ -71,7 +76,7 @@ __attribute__((section(".__sram.code"))) void hal_cache_init(void) hal_clk_gate_enable(MOD_PCLK_CACHE); //cache rst - AP_PCR->CACHE_RST = 0x00; + AP_PCR->CACHE_RST = 0x02; while (dly--) {}; @@ -79,13 +84,16 @@ __attribute__((section(".__sram.code"))) void hal_cache_init(void) AP_PCR->CACHE_RST = 0x03; //cache flush tag - AP_CACHE->CTRL0 = 0x01; + //AP_CACHE->CTRL0 = 0x01; + hal_cache_tag_flush(); //cache enable AP_PCR->CACHE_BYPASS = 0; spif_config(g_spif_ref_clk, 0x1, 0x801003b, 0, 0); + subWriteReg(&AP_SPIF->config, 14, 14, 1); //enable wp bit(14) + AP_SPIF->low_wr_protection = 0; AP_SPIF->up_wr_protection = 0x10; @@ -194,7 +202,9 @@ static void hal_low_power_io_init(void) drv_pm_ram_retention(RET_SRAM0 | RET_SRAM1 | RET_SRAM2); //hal_pwrmgr_RAM_retention(RET_SRAM0); hal_pwrmgr_RAM_retention_set(); +#if (defined(CONFIG_SYS_CLK_XTAL_16M) && CONFIG_SYS_CLK_XTAL_16M > 0) hal_pwrmgr_LowCurrentLdo_enable(); +#endif //========= low power module clk gate #if(PHY_MCU_TYPE==MCU_BUMBEE_CK802) *(volatile uint32_t *)0x40000008 = 0x001961f1; // @@ -210,7 +220,7 @@ static void hal_low_power_io_init(void) static void hal_init(void) { hal_low_power_io_init(); - + hal_rtc_clock_config(g_clk32K_config); //hal_pwrmgr_init(); } @@ -229,9 +239,12 @@ __attribute__((section(".__data_copy_first__"))) void check_before_startup() { //check_data = -1; } - void SystemInit(void) { + // /* USE CONFIG_WDT=1 to enable wdt */ + extern void wdt_init(void); + wdt_init(); + subWriteReg(&AP_SPIF->config, 14, 14, 1); //enable wp bit(14) /* Clear active and pending IRQ */ VIC->IABR[0] = 0x0; VIC->ICPR[0] = 0xFFFFFFFF; @@ -249,9 +262,9 @@ void SystemInit(void) g_spif_ref_clk = SYS_CLK_DLL_64M; - hal_rtc_clock_config(g_clk32K_config); - - JUMP_FUNCTION(CK802_TRAP_C) = (uint32_t)&trap_c; //register trap irq handler + + extern void sram_HardFault_Handler(void); + JUMP_FUNCTION(CK802_TRAP_C) = (uint32_t)&sram_HardFault_Handler; //register trap irq handler #ifdef CONFIG_KERNEL_NONE _system_init_for_baremetal(); @@ -286,7 +299,8 @@ void SystemInit(void) //replace TS_PEND IRQ with IRQ0 drv_irq_enable(0); - csi_vic_set_prio(0, 3); + csi_vic_set_prio(0, 3); + spif_read_id(NULL); hal_cache_init(); hal_mpu_config(); diff --git a/trap_c.c b/trap_c.c index 0a764a7c30bb7189151a1632b9a2df5e76146b3f..2d1e126da92c3c302c64aed2b6888770d5a1f031 100644 --- a/trap_c.c +++ b/trap_c.c @@ -27,6 +27,16 @@ #include void (*trap_c_callback)(void); +extern char * strerror(int errnum); +extern void drv_reboot(int cmd); + + +static void except_process_function(int errno, const char *file, int line, const char *func_name, void *caller) +{ + printf("Except! errno is %s, caller: %p\n", strerror(errno), caller); + drv_reboot(1); +} + void trap_c(uint32_t *regs) { @@ -47,9 +57,11 @@ void trap_c(uint32_t *regs) printf("epsr: %8x\n", regs[16]); printf("epc : %8x\n", regs[17]); - if (trap_c_callback) { - trap_c_callback(); - } + except_process_function(1, __FILE__, __LINE__, __func__, NULL); + +// if (trap_c_callback) { +// trap_c_callback(); +// } while (1); }