# easysim

**Repository Path**: yuhang0313/easysim

## Basic Information

- **Project Name**: easysim
- **Description**: No description available
- **Primary Language**: Python
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2022-02-21
- **Last Updated**: 2022-02-21

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README


# Intro.

This is a simple and quick simulation tool for module level design.

Support the following features:
- run simulation with irun, xrun or vcs
- debug with verdi
- view rtl only with verdi

# Usage:

0. make sure you have installed python3 and git
1. git clone https://gitee.com/exasic/easysim 
2. copy rtl to rtl directory
3. edit sim/conf/conf.json
4. go to sim/rsim directory and run cmd `./run_sim.py`

Example:
1. Run simulation with Cadence Incisive

```
  python3 run_sim.py -tc=tc_sanity
  python3 run_sim.py -top=iic -tc=tc_sanity
```

2. Run Verdi

```
  python3 run_sim.py -verdi
  python3 run_sim.py -verdi -tc=tc_sanity
  python3 run_sim.py -verdi -top=iic -tc=tc_sanity
```

3. View RTL

```
  python3 run_sim.py -rtl_view
  python3 run_sim.py -rtl_view -top=iic
```

4. Switch Cadence Incisive to Synopsys VCS

  Edit conf.json, add "simulator"="vcs"
  
5. Print final command line info only for debug

```
  python3 run_sim.py ...  -dryrun
```
  
6. Specify or override fron conf file

  Edit conf.json, add "timescale=1ns/1ps", or "override_timescale=1ns/1ps"