# Pipelined_RISC-V_Processor

**Repository Path**: zhaokangding/Pipelined_RISC-V_Processor

## Basic Information

- **Project Name**: Pipelined_RISC-V_Processor
- **Description**: 从git上搬运下来的
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: main
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2023-03-06
- **Last Updated**: 2023-03-06

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Pipelined_RISC-V_Processor

### CSCE 3301 – Computer Architecture
### Fall 2020

#### This is a pipelined RISC-V datapath implementation supporting all RV32I (40 instructions).
#### Basic testcase is provided. The testcase is loaded in the instruction memory, and is provided as an assembly text and binary text as well.
#### This implementation uses single memory for instructions and data.

## Datapath

![Pipelined_Final](https://user-images.githubusercontent.com/50206880/219979831-c4027e9f-e09a-43cf-bb52-2e8c0f0bafc4.jpg)