# 开源设计

**Repository Path**: zhoushunmin1/open-source-design

## Basic Information

- **Project Name**: 开源设计
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-07-08
- **Last Updated**: 2025-07-08

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Awesome-dv

## Design/Verification

### Project

- Ibex: https://github.com/lowRISC/ibex

- opentitan: https://github.com/lowRISC/opentitan

- nvdla:  https://github.com/nvdla/hw

- riscv-dv: https://github.com/google/riscv-dv

- core-v-verif: https://github.com/openhwgroup/core-v-verif

- openhmc: https://github.com/unihd-cag/openhmc

- riscv-vip: https://github.com/jerralph/riscv-vip

- ISP-UVM: https://github.com/nelsoncsc/ISP_UVM

- force-riscv: https://github.com/openhwgroup/force-riscv

- core-v-isg:   https://github.com/openhwgroup/core-v-isg

  

### interfaces

- apb-vip-uvm: https://github.com/zhangyl4991/apb-vip-uvm

- axi-uvm:  https://github.com/marcoz001/axi-uvm

- amba3-vip: amba3 apb/axi vip

  https://github.com/luuvish/amba3-vip

- tvip-axi: https://github.com/taichi-ishitani/tvip-axi

- i2c-vip-uvm: https://github.com/zhangyl4991/i2c-vip-uvm

- tnoc:  https://github.com/taichi-ishitani/tnoc

- SDRAM-Verification: https://github.com/yvnr4you/SDRAM-Verification

- ethernet_10ge_mac_SV_UVM_tb: https://github.com/andres-mancera/ethernet_10ge_mac_SV_UVM_tb

- AXI/AHB/Ethernet:
  https://github.com/zhajio1988/ExtremeDV_UVM

### For Newbie
- Practical-UVM-Step-By-Step: https://github.com/Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step
- uvmprimer: https://github.com/rdsalemi/uvmprimer
- UVM Tutorial for Candy Lovers: https://github.com/cluelogic/uvm-tutorial-for-candy-lovers

  

## Design

- Cores-SweRV: https://github.com/chipsalliance/Cores-SweRV

- e200_opensource: https://github.com/SI-RISCV/e200_opensource

- ariane: https://github.com/pulp-platform/ariane

- rsd: https://github.com/rsd-devel/rsd

- ultraembedded_riscv: https://github.com/ultraembedded/riscv

- ultraembedded_ipcores: https://github.com/ultraembedded/cores

- schoolMIPS: https://github.com/MIPSfpga/schoolMIPS

- patmos: https://github.com/t-crest/patmos

- verilog-pcie: https://github.com/alexforencich/verilog-pcie

- verilog-axi: https://github.com/alexforencich/verilog-axi

- wb2axi: https://github.com/ZipCPU/wb2axip

- alice5: https://github.com/bradgrantham/alice5

- black-parrot: https://github.com/black-parrot/black-parrot  

  BlackParrot aims to be the default Linux-capable, cache-coherent, RV64GC multicore used by the world.

- zet:  https://github.com/marmolejo/zet  
  Open source implementation of a x86 processor 

- ao486: https://github.com/alfikpl/ao486  
  The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.
  
- VexRiscv: https://github.com/SpinalHDL/VexRiscv  
  A FPGA friendly 32 bit RISC-V CPU implementation from SpinalHDL
  
- hadbadge2019_fpgasoc:  FPGA SoC code and application example for Hackaday Supercon 2019 badge
  
  https://github.com/Spritetm/hadbadge2019_fpgasoc



## Virtual Prototyping

- Soclib: http://www.soclib.fr/trac/dev
- Gem5:  http://www.m5sim.org/Main_Page