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本期概要
semi engineering：每周三，周五发布
"Linux 5.10-rc3 Released As A "Normal" RC3 Version (From www.phoronix.com 2020.11.14)"
Mail Archived
KVM
QEMU
BP Deac, A Colesa - Proceedings of the 2020 ACM SIGSAC Conference on …, 2020
It is widely known that return-oriented programming (ROP) attack can be mounted on
x86, ARM and SPARC architectures. However, it remained an open question if ROP
was possible on RISC-V, a new and promising free and open instruction set …
VL Guglielmi - 2020
This thesis was developed while working at Barcelona Supercomputing Center, a
research center specialized in High Performance Computing and investigation in
many fields, such as cloud computing, bioinformatics, material science and more …
L Valente - 2020
Power dissipation and Energy consumption of digital circuits has emerged as an
important design parameter in the evaluation of microelectronic circuits. This has led
electronic architects to value Parallel Architectures that allow to perform many …
A Dalbom, T Svensson - 2020
As cores have become better at exposing Instruction-Level Parallelism (ILP), they
have become bigger, more complex, and consumes more power. These cores are
approaching the Power-and Memory-wall quickly. A new microarchitecture proposed …
L Lavagno, N Sonmez, L Valente
Power dissipation and Energy consumption of digital circuits have emerged as
important design parameters in the evaluation of microelectronic circuits. This has
led electronic architects to value Parallel Architectures that allow to perform many …
BP Deac, A Colesa - Proceedings of the 2020 ACM SIGSAC Conference on …, 2020
It is widely known that return-oriented programming (ROP) attack can be mounted on
x86, ARM and SPARC architectures. However, it remained an open question if ROP
was possible on RISC-V, a new and promising free and open instruction set …
L Valente - 2020
Power dissipation and Energy consumption of digital circuits has emerged as an
important design parameter in the evaluation of microelectronic circuits. This has led
electronic architects to value Parallel Architectures that allow to perform many …
A Dalbom, T Svensson - 2020
As cores have become better at exposing Instruction-Level Parallelism (ILP), they
have become bigger, more complex, and consumes more power. These cores are
approaching the Power-and Memory-wall quickly. A new microarchitecture proposed …
L Lavagno, N Sonmez, L Valente
Power dissipation and Energy consumption of digital circuits have emerged as
important design parameters in the evaluation of microelectronic circuits. This has
led electronic architects to value Parallel Architectures that allow to perform many …
VBY Kumar, S Deb, N Gupta, S Bhasin, J Haj-Yahya… - Journal of Hardware and …, 2020
A rising tide of exploits, in the recent years, following a steady discovery of the many
vulnerabilities pervasive in modern computing systems has led to a growing number
of studies in designing systems-on-chip (SoCs) with security as a first-class …
C Ramírez, CA Hernández, O Palomar, O Unsal… - ACM Transactions on …, 2020
Vector architectures lack tools for research. Consider the gem5 simulator, which is
possibly the leading platform for computer-system architecture research.
Unfortunately, gem5 does not have an available distribution that includes a flexible …
A Singh, N Franklin, N Gaur, P Bhulania - 2020 IEEE 5th International Conference on …, 2020
In this paper, a 32-bit Datapath with RISC-**V **instruction set architecture based on
RV32I CPU instruction set has been designed. Furthermore, through analysis of
function and theory of RISC-**V **CPU instruction set, the processor has been optimized …
I Gamino del Río, A Martínez Hellín, Ó R Polo… - Electronics, 2020
Code instrumentation enables the observability of an embedded software system
during its execution. A usage example of code instrumentation is the estimation of
“worst-case execution time” using hybrid analysis. This analysis combines static …
J Castro-Godínez, M Shafique, J Henkel - 2020 International Conference on …, 2020
… We present results of automated approximate software generated with AxSWGen and
executed on a RISC-V processor (SiFive HiFive1 board), achieving up to 50% energy
reduction for a 5% image degradation for an approximate Gaussian filter …
M Maas - Proceedings of the 17th International Conference on …, 2020
… efficiently than a CPU. I will also talk about current work within the open-source
RISC-V project on developing standard extensions for managed-language support
in the context of the free and open RISC-V ISA. Finally, I will …
R Alidori - 2020
… and execution latency. Besides the SoA, three additional formats are proposed in
this work: Custom Posit, Not Contiguous Posit and Modified Posit. This work is
implemented in a RISC-V environment. This architecture supports …
G Tombesi - 2020
… integration challenges in heterogeneous systems. In most of the cases, the instruction
set architecture (ISA) of the RISC-V1 project is leveraged for the processor cores of
the proposed platforms. Among the existing implementations …
F Templeton
… The first biometric wearable containing an “edge AI chip” ie,
microprocessors embedded with machine-learning algorithms, was based
on open-source RISC-V chip architecture, launched by scientists at the …
P Talluri - 2020
… Its main steps comprises design instrumentation, simulation based fault injection and
automatic fault classification. RISC-V is chosen as the target architecture due to its open
source nature and its increasing adoption by academia and industry …
M Jamieson, N Brown - arXiv preprint arXiv:2011.04983, 2020
… When choosing an IoT architecture, whether it be a physical chip or
soft-core, it is important that the choice made is a good one, however with
over 40 implementations of the RISC-V architecture alone, the ability to …
JK Szewczyk
… The tool also worked correctly on larger designs: an Intel 8051‑compatible
core and a RISC‑V processor used in labs for the CArD course. Page 3.
Contents … 3 • Generating correct Verilog with fault injection for a RISC‑V code …
A Kritikakou, S Skalistis - 2020 International Conference on Embedded Software …, 2020
… In this preliminary experimental set-up, we consider the PULP RISC-V
processor of GAP8 platform [10] as our platform model … [10] E. Flamand,
D. Rossi, F. Conti, I. Loi, A. Pullini, F. Rotenberg, and L. Benini, “Gap-8: A …
AB Kahng
… Following are some preliminary thoughts.5 Open-source EDA is part of a movement. The
open hardware community will use OpenROAD. A vi- brant open-source hardware
ecosystem sparked by RISC-V has grown rapidly in recent years [32], [34], [45] …
T Odajima, Y Kodama, M Sato - The Journal of Supercomputing, 2020
… Therefore, we employ gem5, which is a general-purpose processor simulator, used
to evaluate SVE architecture. Additionally, gem5 supports several kinds of processors
such as Alpha, Arm, SPARC, x86, RISC-V, and GPU …
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每周六发布
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