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采用了大量FPGA,即将发射的美国火星漫游车技术揭秘

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2021-05-23 12:49

http://xilinx.eetop.cn/view-3078.html
发布者:jackzhang 时间:2020-07-22 23:21:07

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即将发射的美国火星漫游车“毅力号”(Perseverance)将配备多种观测设备,用于搜索生命迹象等,FPGA也被广泛应用于整个车辆。

最近Xilinx公司系统架构师Minal Sawant的透漏了更多关于FPGA用于火星探测车细节。

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Minal Sawant

在此我们为大家做一个简单介绍。

FPGA用于太空示例

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使用xilin FPGA的卫星和航天器示例

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在JAXA卫星中也有采用

而对于火星探测器,FPGA的首次使用是2003年的勇气号(Spirit)和机遇号(Opportunity)火星漫游车,采用了Virtex-1系列FPGA用于的电机控制。 其中,"机遇号 "持续探索火星表面15年,大大超过了预期的3个月的寿命,证明了其可靠性。

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美国火星探测车:越做越大,功能越来越多

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起始于从勇气号/机遇号,火星漫游车开始使用FPGA

2011年的"好奇号 "则采用了Virtex-2系列。随着重量一下子增加到900公斤左右,仪器数量的增加,FPGA的使用范围也随之扩大,在MAHLI和ChemCam等仪器和总线设备中都有使用。

于2020年推出的毅力号(Perseverance)将在“ LVS”(Lander Vision System)中使用Virtex-5系列“ XQR5VFX130”。

毅力号将采用与好奇号相同的“天车”模式降落在火星上。首先,用降落伞减速,然后在大约1英里(1.6公里)的高度分开。从那里,下降模块的火箭射流减速以悬停,悬挂绳索,并轻轻地将先前悬挂在地面上的流动站掉落。这是“空中的起重机”。

相同的 "天吊 "方式登陆火星。用降落伞减速后,航天器将在1英里(1.6公里)的高度分离。从那里,漫游车将被下降舱的火箭火力减速、悬停,然后通过悬挂绳索缓缓下降到地面。是真正的 “空中的起重机”。

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需要注意的是,火星表面也有危险的山脉和山谷。探测器需要下降到预先选定的平坦地点,以便安全着陆,而在下降过程中观察地表的LVS将被用来帮助导航。通过比较摄像头的图像和地图数据,漫游车可以确定其当前位置。

XQR5VFX130被用作图像处理的硬件加速器,在勇气号/机遇号中只使用20MHz的CPU(RAD6000),计算时间约为160秒,而毅力号使用200MHz的CPU(RAD750)和FPGA之间进行分工处理,使其速度提高了18倍,降至仅8.8秒。

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毅力号的LVS,在中心“视觉计算元件”中使用了FPGA

毅力号还将其FPGA用于其他观测设备和总线仪器,如 "PIXL"、"Mastcam-Z "和 "SHERLOC"。

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使用相同FPGA的毅力号设备

为什么使用FPGA

现场可编程门阵列(FPGA)是一种可以由用户自由重新配置(编程)的集成电路。另一方面,ASIC具有高性能、低功耗的特点,但其电路不能改变。FPGA是CPU和ASIC的良好结合,其自由度高,功耗低。

对于量产产品来说,开发一个专门的ASIC是有利可图的,但对于卫星和空间探测器来说,基本上最多也就几十台,这点用量ASIC明显不适合。而FPGA不需要大量的初始成本,而且可以马上设计出来,对于航天来说,FPGA可能是非常适合的。

据Xilinx公司介绍,从2000年左右开始,Xilinx就开始提供空间级FPGA。在太空中,FPGA具有与地面一样的优势,尤其是发射后可以重写。Sawant指出:"由于能够灵活地适应任务变化,它还将延长卫星本身的寿命。

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xilinx 的太空FPGA。使用了特殊的陶瓷封装

然而,太空中的空间辐射很强,会带来半导体电路中被称为 "单次事件效应"(SEE)的问题。单个事件包括存储器反转超限(SEU)和过流闩锁(SEL)。由于这些事件会导致故障和失效,因此在太空中使用它们需要很高的抗辐射能力。

该公司提供了两款空间级FPGA,分别是90纳米工艺的Virtex-4QV和65纳米工艺的Virtex-5QV。"4QV "采用了与消费类产品相同的硅片,而 "5QV "则在设计本身内置了抗辐射功能(RHBD:Radiation Hardened by Design),"我们已经能够将颠覆的发生限制在一年两次左右" ,Sawant表示。

作为下一代产品,该公司于2020年5月宣布了20 nm工艺“ RT Kintex Ultra Scale”,目前正在样品供货中。这是一款一次性跳过几代流程的高性能产品,预计将除了做图像处理外还可用于机器学习。

通常,随着制造过程变得越来越精细,芯片会变得更容易受到辐射的影响,但是RT Kintex UltraScale“通过设计架构和设计,使其很难发生单一事件。”那。

通常情况下,随着制造工艺的变小,相对来说更容易受到辐射的影响,但据xilinx的RT Kintex UltraScale 过在架构和设计上下功夫,使单一事件难以发生,提高了抗辐射能力。

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目前毅力号定于7月30日(美国时间)发射。预计在2021年2月登陆火星。

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Past, Present, Future - Xilinx on Mars Rovers…!

https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Past-Present-Future-Xilinx-on-Mars-Rovers/ba-p/944915

这是通过搜索关键字:Missions with Virtex-5QV - More in Pipeline Minal Sawant xilinx
来自 bing.com 的第一篇文章,它同样自本文相同的作者,Xilinx 公司系统架构师 Minal Sawant

By Minal Sawant, System Architect, Xilinx Space Products

NASA’s Opportunity Rover Mission came to an end on February 13, 2019 after exploring the surface of Mars for 15 earth years, even though the design was intended to last just 90 Martian days. NASA’s Mars Exploration Program is one of the most successful interplanetary exploration missions ever. We congratulate the team at Jet Propulsion Labs (JPL) and thank them for making Xilinx part of these historic missions. Though the Opportunity Rover is shutting down, the Curiosity Rover (aka MSL), also with Xilinx FPGAs on board, is still roaming the Martian surface. And as Curiosity continues to navigate, Xilinx is getting ready for future mission MARS2020!

What's In The Past?

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MER Opportunity.jpg

Figure 1: MER Opportunity (Source: NASA)

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Spirit-rover-on-Mars.jpg

Figure 2: Spirit Rover on Mars (Image credit: NASA/JPL)

NASA’s Mars Exploration Rover (MER) mission involved two Mars rovers: “Spirit” and “Opportunity.” They were designed to explore the planet for water sources on Mars. Planned to last 90 days, the rovers exceeded everyone’s expectations with Spirit lasting 7+ years (20X longer) and Opportunity lasting 15 years (55X longer) — both returning valuable information about the geological composition of the planet!

In creating these incredible MERs, designed to run on solar power, the JPL team used radiation-tolerant Xilinx Virtex®-4 FPGAs, state of the art in FPGA space-grade technology at the time of the design, for both the landing and on-surface operation of the Mars rovers. Specifically, XQVR4062 FPGAs went into each MER landing craft to control the crucial pyrotechnic operations during a rover’s multiphase descent and landing procedure, when the engineers trigger explosives for various stages of the maneuver. NASA engineers used the FPGAs at the heart of the Lander Pyro Switch Interface system, which orchestrated the MERs’ elaborate pyrotechnic sequence to the millisecond. In addition, NASA also used XQVR1000s in the MER Motor Control Board, which oversees the motors for the wheels, steering, arms, cameras, and various instrumentation, enabling the rovers to travel about the planet’s often silt-like surface and negotiate various obstacles.

Present Defines The Future

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Figure 3. Curiosity Rover on Mars (Image credit: NASA/JPL-Caltech/MSSS)

The next rover to travel to Mars, the Mars Science Lab (MSL), aka “Curiosity,” was launched in 2011 and traveled for eight months on a 352-million-mile journey. Designed to run on nuclear power, it is still (!) navigating the Martian surface, trying to ascertain whether the planet ever supported microbial lifeform. Initially designed for a 2-year mission, the rover is still operational and going strong 8+ years later and will likely continue to do so for years to come.

Xilinx space-grade products enable key instruments systems like MAHLI (imager), ChemCam (remote sensing instruments), Electra-Lite (communications), and MALIN (processor) on the rover. Mars Hand Lens Imager (MAHLI), a camera on the rover’s robotic arm, acquires images, while the MALIN system consists of backend image processing boxes that process images from all onboard cameras. Xilinx’s Virtex-II (XQR2V3000) radiation-tolerant FPGAs implements the image pipelines in these systems. All interface, compression, and timing functions are implemented as logic peripherals of a MicroBlaze™ soft-processor core in the Virtex-II FPGA. This enables the Curiosity to send back stunning images of an alien landscape that is 35 million miles away. ChemCam (Chemistry and Camera Complex) provides elemental compositions and high-resolution images of rock and soil using Xilinx’s radiation-tolerant XQ2V1000 FPGA.

Curiosity is equipped with significant telecommunications systems like the X Band transmitter and receiver that can communicate with Earth and a UHF Electra-Lite software defined radio for communicating with Mars’ orbiters that serve as the primary path for data return to Earth. Xilinx’s XQR2V3000 radiation-tolerant FPGAs serve in these communication boxes, providing critical links back to Earth.

The Future Will Be Here Soon Enough

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MARS 2020 Mission.jpg

Figure 4. MARS2020 Mission (Image Credit: NASA)

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Vision Compute Element.png

Figure 5: Vision Compute Element (Source: EEJournal)

NASA is planning to launch the MARS2020 rover mission based on the MSL mission architecture for the touchdown in February 2021. The mission will seek signs of habitable conditions, search for biosignatures, and collect samples for future Mars-sample-return missions and human expeditions.

The MARS2020 rover includes a new FPGA-based hardware accelerator in its Vision Compute Element (VCE) that will aid in landing navigation and autonomous driving on the Martian surface. Xilinx’s radiation-hardened Virtex-5QV (SIRF) FPGAs serve as the reprogrammable visual processor in the Computer Vision Accelerator Card (CVAC) used to accelerate certain stereo and visual tasks like image rectification, filtering, detection, and matching. Also included on some of the instruments are the Mastcam-Z, a multispectral stereoscopic imaging instrument, which uses a radiation-tolerant Virtex-II FPGA (XQR2V3000) in the digital box based on the MSL architecture, and the Scanning Habitable Environments with Raman & Luminescence for Organics and Chemicals (SHERLOC) spectrometer, which uses the MAHLI with a camera system incorporating the XQR2V3000 FPGAs.

Xilinx gives our customers license to architect an adaptable future, are YOU ready for future missions and scientific pursuits?

To learn about Xilinx space solutions, visit https://www.xilinx.com/applications/aerospace-and-defense.html
If you want to see JPL’s extensive test results for the Virtex-5QV FPGA, click here.
https://parts.jpl.nasa.gov/wp-content/uploads/V5QV-Static-SEU-Summary-ReportRevD.pdf

5631341 yuandj 1624973227 袁德俊 拥有者
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https://www.xilinx.com/support/documentation/data_sheets/ds192_V5QV_Device_Overview.pdf

Virtex-5QV FPGA Features

This section briefly describes the features of the Virtex-5QV family of FPGAs.
Input/Output Blocks (SelectIO Resources)
IOBs are programmable and can be categorized as follows:

  • Programmable single-ended or differential (LVDS) operation
  • Input block with an optional single data rate (SDR) or double data rate (DDR) register
  • Output block with an optional SDR or DDR register
  • Bidirectional block
  • Per-bit deskew circuitry
  • Dedicated I/O and regional clocking resources
  • Built-in data serializer/deserializer

The IOB registers are either edge-triggered D-type flip-flops or level-sensitive latches.
IOBs support the following single-ended standards:

  • LVTTL
  • LVCMOS (3.3V, 2.5V, 1.8V, 1.5V, and 1.2V)
  • PCI (33 and 66 MHz)
  • PCI-X
  • GTL and GTLP
  • HSTL 1.5V and 1.8V (Class I, II, III, and IV)
  • HSTL 1.2V (Class 1)
  • SSTL 1.8V and 2.5V (Class I and II)

The Digitally Controlled Impedance (DCI) I/O feature can be configured to provide on-chip termination for each single-ended
I/O standard and some differential I/O standards.
The IOB elements also support these differential signaling I/O standards:

  • LVDS and Extended LVDS (2.5V only)
  • BLVDS (Bus LVDS)
  • ULVDS
  • HyperTransport™ technology
  • Differential HSTL 1.5V and 1.8V (Class I and II)
  • Differential SSTL 1.8V and 2.5V (Class I and II)
  • RSDS (2.5V point-to-point)

Two adjacent pads are used for each differential pair. Two or four IOB blocks connect to one switch matrix to access the
routing resources.
Per-bit deskew circuitry allows for programmable signal delay internal to the FPGA. Per-bit deskew flexibly provides
fine-grained increments of delay to carefully produce a range of signal delays. This is especially useful for synchronizing
signal edges in source-synchronous interfaces.
General-purpose I/O in select locations (eight per bank) are designed to be “regional clock capable” I/O by adding special
hardware connections for I/O in the same locality. These regional clock inputs are distributed within a limited region to
minimize clock skew between IOBs. Regional I/O clocking supplements the global clocking resources.
Data serializer/deserializer capability is added to every I/O to support source-synchronous interfaces. A serial-to-parallel
converter with associated clock divider is included in the input path, and a parallel-to-serial converter in the output path.

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https://www.xilinx.com/applications/aerospace-and-defense.html

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