Rocket chip on Zedboard

http://venividiwiki.ee.virginia.edu/mediawiki/index.php/Rocket_chip_on_Zedboard

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/002940_596905f6_5631341.png "屏幕截图.png")

## FPGA Lab Project - Rocket Chip on Zedboard

## Objective

The goal of this project is to implement the RISC-V Rocket Chip on the Zynq-based ZedBoard and run applications on it. This project is based on a project from UC Berkeley Architecture Research: Rocket Chip on Zynq FPGAs

## Introduction

### RISC-V

RISC-V is an open instruction set architecture (ISA) based on the reduced instruction set computing (RISC). RISC architectures are characterized by a small set of simple and general instructions. This is contrasted by complex instruction set computing (CISC), which have a large set of complex and specialized instructions. The project began in 2010 at the University of California, Berkeley. You can find more information about the project and the ISA at the [RISK-V Foundation Website](https://riscv.org/)

### The Rocket Chip Generator

Rocket Chip is an open-source Sysem-on-Chip (SoC) design generator that emits synthesizable RTL. It uses the Chisel hardware construction language to compose a library of sophisticated generators for cores, caches, and interconnects into an integrated SoC. It generates general-purpose processor cores that use the open RISC-V ISA, and provides both an in-order core generator (Rocket) and an out-of-order core generator (BOOM).

The technical details are on the Berkely EECS page: [The Rocket Chip Generator Technical Report](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html)

The project is hosted on GitHub: [Rocket Chip Generator Repository](https://github.com/freechipsproject/rocket-chip)

The figure below shows an instance of an SoC generated by the Rocket Chip Generator.

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/003242_28e98f0d_5631341.png "屏幕截图.png")

## Project Overview

We will implement Rocket Chip on the FPGA and run applications on it. The rough top-down stack is shown below:

-  **Target Application**

This is a binary application compiled with either [riscv-gcc](https://github.com/riscv/riscv-gcc) or [riscv-llvm](https://github.com/riscv/riscv-llvm).

-  **RISC-V Kernel**

Can run the proxy kernel [proxy kernel](https://github.com/riscv/riscv-pk) designed to run single binary applications. Can alternatively run the lightweight [RISC-V Linux](https://github.com/riscv/riscv-linux).

-  **Rocket Chip**

[Rocket Core](https://github.com/freechipsproject/rocket-chip) instantiated on FPGA. It communicates to the host ARM on the Zynq via AXI.

-  **Front-end Server**

[RISC-V Front-end Server](https://github.com/riscv/riscv-fesvr) which runs on the host ARM core and interfaces to the Rocket Chip.

-  **Zynq ARM Core**

Process on the Zynq SoC that runs Linux.

-  **Development Board**

[ZedBoard](http://www.zedboard.org/product/zedboard) Development board with the Zynq SoC. SD Card used to configure the FPGA.

-  **External Communication**

Communication between PC and FPGA board over Ethernet.

-  **User Interface**

SSH Client terminal on PC.

## Step 1: Project Setup

### Download the files needed

We will use fpga-zynq repository from UCB. Run the command below in the terminal to download the repository:

```
git clone https://github.com/ucb-bar/fpga-zynq
```

Since fpga-zynq uses files from other repositories such as rocket-chip, we will also need to download those files as well. Run this command to get all the files needed for fpga-zynq:

```
cd fpga-zynq
git submodule update --init --recursive
```

### Project setup

First go to fpga-zynq directory and run this command to generate a vivado project for Zedboard:

```
cd fpga-zynq/zedboard
make project
```
Then open this project:

```
make vivado

```
If you want to go back to the project later, the project file is located here:

```
cd fpga-zynq/zedboard/zedboard_rocketchip_ZynqSmallConfig
vivado zedboard_rocketchip_ZynqSmallConfig.xpr
```
If you create the project successfully, then open the block diagram from the left. You should see something like this:

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004136_18df7e19_5631341.png "屏幕截图.png")

## Step 2: Generate the files for zedboard

### Bitstream

First generate the bitstream in Vivado. You should see the device diagram and project summary.

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004223_a51745be_5631341.png "屏幕截图.png")

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004240_211aef87_5631341.png "屏幕截图.png")

### FSBL(first stage boot loader)

Then export the hardware from select File -> Export -> Export Hardware and launch SDK. In SDK, select File -> New -> Application Project. In the new window, type "FSBL" as the Project name. The window should be like this:

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004312_8592c4a0_5631341.png "屏幕截图.png")

Select Next, then select ZYNQ FSBL in the next window and finish.

### u-boot for the Zynq ARM Core

To run the command that generates the u-boot file, we need to change the value of SDK environment variable LD_LIBRARY_PATH to 'nothing':

```
export LD_LIBRARY_PATH=""

```
Then generate the u-boot file:

The u-boot file is placed in fpga-zynq/zedboard/soft_build/u-boot.elf

```
cd fpga-zynq/zedboard
make arm-uboot
```
### boot.bin

Returning to the Xilinx SDK, select Xilinx Tools -> Create Boot Image.

Set output BIF file path to fpga-zynq/zedboard/deliver_output. Create the folder if it does not exist.

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004446_258be5ed_5631341.png "屏幕截图.png")

Next, we will add the individual files that make up BOOT.bin

Click on ADD, and then Browse. The file we need is located at fpga-zynq/zedboard/zedboard_rocketchip_ZynqSmallConfig/zedboard_rocketchip_ZynqSmallConfig.sdk/FSBL/Debug/FSBL.elf. And make sure the Partition type is bootloader. Then click on OK.

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004505_0b3ccf7c_5631341.png "屏幕截图.png")

Similarly, add rocketchip_wrapper.bit and u-boot.elf as well. The Partition type of these two files is datafile. The files are located at:fpga-zynq/zedboard/zedboard_rocketchip_ZynqSmallConfig/zedboard_rocketchip_ZynqSmallConfig.runs/impl_1/rocketchip_wrapper.bit and fpga-zynq/zedboard/soft_build/u-boot.elf.

Select Create Image. This will produce a BOOT.bin file in the $REPO/zybo/deliver_output directory.

### Other files

We also need some files to boot Linux. Run the following commands:

```
cd fpga-zynq/zedboard
make arm-linux
make arm-dtb
make fetch-ramdisk
```

Now there are four files in /deliver_output:

- BOOT.bin - This contains the FSBL, the bitstream with Rocket, and u-boot.
- uImage - Linux for the ARM PS.
- devicetree.dtb - Contains information about the ARM core's peripherals for linux.
- uramdisk.image.gz - The root filesystem for linux on the ARM Core.

Copy these files into the root directory of SD card.

### Step 3: Test

First connect the ZedBoard to your computer with Ethernet cable. If you are using Linux, go to internet settings. Select the current Ethernet connection and click on Edit.

Go to IPv4 Settings tab. Change the addresses as shown below:

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004652_a977173b_5631341.png "屏幕截图.png")

Open a new terminal, run this command to get access to the processor. The IP address of zedboard is always 192.168.1.5. The default password is root:

```
ssh root@192.168.1.5

```
You could also use a terminal with support for SSH such PuTTY. Login with "root" for both username and password. At this point, you are running Linux on the ARM core:

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004736_09a599f3_5631341.png "屏幕截图.png")

### Booting Up and Interacting with the RISC-V Rocket Core

You can run a compiled application on the RISC-V on top of the proxy kernel.

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004759_ae56df49_5631341.png "屏幕截图.png")

You can also boot up RISC-V Linux:

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004816_286ea623_5631341.png "屏幕截图.png")

RISC-V Linux supports these commands:

![输入图片说明](https://images.gitee.com/uploads/images/2022/0103/004831_6b86f53d_5631341.png "屏幕截图.png")

## References
- [RISC-V Foundation](https://riscv.org/)
- [RISC-V Foundation GitHub](https://github.com/riscv)
- [Rocket Chip Generator](https://github.com/freechipsproject/rocket-chip)
- [Rocket Chip Generator Technical Report](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html)
- [Rocket Chip on Zynq FPGAs](https://github.com/ucb-bar/fpga-zynq#overview)

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