代码拉取完成，页面将自动刷新
<?xml version="1.0" encoding="utf-8" standalone="no"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<vendor>HiSilicon (Shanghai) Technologies Co., Ltd.</vendor>
<name>Hi38x1</name>
<version>1.0</version>
<description>Hi3861 V100/Hi3861L V100/Hi3881 V100 Wi-Fi Chip</description>
<addressUnitBits>8</addressUnitBits> <!-- todo: verify -->
<width>32</width>
<size>32</size>
<access>read-write</access>
<peripherals>
<peripheral>
<name>GLB_CTL</name>
<description>Global software interrupt controller</description>
<baseAddress>0x50000000</baseAddress>
<interrupt>
<name>SOFT0</name>
<description>Software interrupt 0</description>
<value>51</value>
</interrupt>
<interrupt>
<name>SOFT1</name>
<description>Software interrupt 1</description>
<value>52</value>
</interrupt>
<interrupt>
<name>SOFT2</name>
<description>Software interrupt 2</description>
<value>53</value>
</interrupt>
<interrupt>
<name>SOFT3</name>
<description>Software interrupt 3</description>
<value>54</value>
</interrupt>
<registers>
<register>
<name>soft_int_en</name>
<description>Software interrupt enable register</description>
<addressOffset>0x280</addressOffset>
<fields>
<field>
<name>soft_int%s_en</name>
<description>Software interrupt enable</description>
<access>read-write</access>
<lsb>0</lsb>
<msb>0</msb>
<dim>4</dim>
<dimIncrement>1</dimIncrement>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>Software interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>Software interrupt is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>soft_int_set</name>
<description>Software interrupt set register</description>
<addressOffset>0x284</addressOffset>
<fields>
<field>
<name>soft_int%s_set</name>
<description>Software interrupt set</description>
<access>write-only</access>
<lsb>0</lsb>
<msb>0</msb>
<dim>4</dim>
<dimIncrement>1</dimIncrement>
<enumeratedValues>
<enumeratedValue>
<name>set</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>soft_int_clr</name>
<description>Software interrupt clear register</description>
<addressOffset>0x288</addressOffset>
<fields>
<field>
<name>soft_int%s_clr</name>
<description>Software interrupt clear</description>
<access>write-only</access>
<lsb>0</lsb>
<msb>0</msb>
<dim>4</dim>
<dimIncrement>1</dimIncrement>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>The interrupt is cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>soft_int_sts</name>
<description>Software interrupt status register</description>
<addressOffset>0x28C</addressOffset>
<fields>
<field>
<name>soft_int%s_sts</name>
<description>Software interrupt status</description>
<access>read-only</access>
<lsb>0</lsb>
<msb>0</msb>
<dim>4</dim>
<dimIncrement>1</dimIncrement>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>The interrupt is cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>set</name>
<description>The interrupt is set.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIO</name>
<description>General purpose input/output</description>
<baseAddress>0x50006000</baseAddress>
<interrupt>
<name>GPIO</name>
<description>GPIO interrupt</description>
<value>45</value>
</interrupt>
<registers>
<register>
<name>data_output</name>
<description>Port data output register</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>gpio%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>16</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>direction</name>
<description>Port data transfer direction register</description>
<addressOffset>0x04</addressOffset>
<fields>
<field>
<name>gpio%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>16</dim>
<dimIncrement>1</dimIncrement>
<enumeratedValues>
<name>DIRECTION</name>
<enumeratedValue>
<name>input</name>
<description>Pin is input</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>output</name>
<description>Pin is output</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>interrupt_enable</name>
<description>Port interrupt enable register</description>
<addressOffset>0x30</addressOffset>
<fields>
<field>
<name>gpio%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>16</dim>
<dimIncrement>1</dimIncrement>
<enumeratedValues>
<name>MODE</name>
<enumeratedValue>
<name>normal</name>
<description>Normal mode (default value)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>interrupt</name>
<description>Interrupt mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>interrupt_mask</name>
<description>Port interrupt mask register</description>
<addressOffset>0x34</addressOffset>
<fields>
<field>
<name>gpio%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>16</dim>
<dimIncrement>1</dimIncrement>
<enumeratedValues>
<name>MASK</name>
<enumeratedValue>
<name>not_masked</name>
<description>Not masked (default value)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>masked</name>
<description>Masked</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>interrupt_type</name>
<description>Port interrupt type register</description>
<addressOffset>0x38</addressOffset>
<fields>
<field>
<name>gpio%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>16</dim>
<dimIncrement>1</dimIncrement>
<enumeratedValues>
<name>TRIGGER</name>
<enumeratedValue>
<name>level</name>
<description>Level triggered (defulat value)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>edge</name>
<description>Edge triggered</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>interrupt_ploarity</name>
<description>Port interrupt polarity register</description>
<addressOffset>0x3C</addressOffset>
<fields>
<field>
<name>gpio%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>16</dim>
<dimIncrement>1</dimIncrement>
<enumeratedValues>
<name>POLARITY</name>
<enumeratedValue>
<name>falling_low</name>
<description>falling edge or low level-triggered (default value)</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>rising_high</name>
<description>Rising edge or high level-triggered</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>interrupt_status</name>
<description>Interrupt status registers</description>
<addressOffset>0x40</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>gpio%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>16</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>interrupt_status_raw</name>
<description>Raw interrupt status registers</description>
<addressOffset>0x44</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>gpio%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>16</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>interrupt_clear</name>
<description>Raw interrupt status registers</description>
<addressOffset>0x44</addressOffset>
<access>write-only</access>
<fields>
<field>
<name>gpio%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>16</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
<register>
<name>data_input</name>
<description>External port (data input) registers</description>
<addressOffset>0x50</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>gpio%s</name>
<lsb>0</lsb>
<msb>0</msb>
<dim>16</dim>
<dimIncrement>1</dimIncrement>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTC</name>
<groupName>RTC</groupName>
<description>The RTC counts down from the preset data to 0, triggering an interrupt.</description>
<baseAddress>0x50007000</baseAddress>
<registers>
<cluster>
<name>timer%s</name>
<description>Timer cluster</description>
<addressOffset>0x0</addressOffset>
<dim>4</dim>
<dimIndex>1-4</dimIndex>
<dimIncrement>0x14</dimIncrement>
<register>
<name>load_count</name>
<description>TIMER_LOADCOUNT is the timer initial value register.</description>
<addressOffset>0x000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>current_value</name>
<description>TIMER_CURRENTVALUE is the timer current value register.</description>
<addressOffset>0x004</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>control</name>
<description>TIMER_CONTROLREG is the timer control register.</description>
<addressOffset>0x008</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>timer_lock</name>
<description>Timer lock control.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>unlocked</name>
<description>not locked.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>locked</name>
<description>Locks the timer value to TIMER_CURRENTVALUE.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>timer_int_mask</name>
<description>Timer interrupt mask.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>unmasked</name>
<description>not masked.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>masked</name>
<description>masked.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>timer_mode</name>
<description>Timer mode control</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>free</name>
<description>free mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>periodic</name>
<description>periodic mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>timer_en</name>
<description>Timer enable.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>eoi</name>
<description>TIMER_EOI is the timer interrupt clear register</description>
<addressOffset>0x00c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>timer_eoi</name>
<description>Read this register to clear timer interrupt flag.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>interrupt_status</name>
<description>TIMER_INTSTATUS is the timer interrupt status register.</description>
<addressOffset>0x010</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>timer_int_status</name>
<description>Masked interrupt status of timer.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>The interrupt is invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The interrupt is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</cluster>
<register>
<name>TIMERS_INTSTATUS</name>
<description>TIMERS_INTSTATUS is the interrupt status register for timers.</description>
<addressOffset>0x0A0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>timer4_int_status_sum</name>
<description>Masked interrupt status of timer4</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>The interrupt is invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The interrupt is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>timer3_int_status_sum</name>
<description>Masked interrupt status of timer3</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>The interrupt is invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The interrupt is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>timer2_int_status_sum</name>
<description>Masked interrupt status of timer2</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>The interrupt is invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The interrupt is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>timer1_int_status_sum</name>
<description>Masked interrupt status of timer1</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>The interrupt is invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The interrupt is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TIMERS_EOI</name>
<description>TIMERS_EOI is the interrupt clear register for timers.</description>
<addressOffset>0x0A4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>timer_seoi</name>
<description>Reading this register clears interrupt for timers.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>TIMERS_RAWINTSTATUS</name>
<description>TIMERS_RAWINTSTATUS is the raw interrupt status register for timers.</description>
<addressOffset>0x0A8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>timer4_raw_int_status</name>
<description>Raw interrupt status of timer4</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>The interrupt is invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The interrupt is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>timer3_raw_int_status</name>
<description>Raw interrupt status of timer3</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>The interrupt is invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The interrupt is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>timer2_raw_int_status</name>
<description>Raw interrupt status of timer2</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>The interrupt is invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The interrupt is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>timer1_raw_int_status</name>
<description>Raw interrupt status of timer1</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>The interrupt is invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The interrupt is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- ADC -->
<peripheral>
<name>ADC</name>
<description>Analog to Digit Converter</description>
<baseAddress>0x40070000</baseAddress>
<registers>
<register>
<name>LSADC_CTRL0</name>
<description>LSADC_CTRL0 is the ADC control register.</description>
<addressOffset>0x000</addressOffset>
<size>32</size>
<resetValue>0x0000F000</resetValue>
<fields>
<field>
<name>cur_bais</name>
<description>Analog power control.</description>
<access>read-write</access>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>auto</name>
<description>automatic control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>manual_1p8</name>
<description>manual control, AVDD = 1.8 V.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>manual_3p3</name>
<description>manual control, AVDD = 3.3 V.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rst_cnt</name>
<description>Count time from the reset (RST) to the start of the conversion.</description>
<access>read-write</access>
<bitOffset>12</bitOffset>
<bitWidth>12</bitWidth>
<resetMask>0x00F</resetMask>
</field>
<field>
<name>equ_model_sel</name>
<description>Average algorithm mode select.</description>
<access>read-write</access>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>model_1</name>
<description>1-time average (that is, not average).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>model_2</name>
<description>2-time average algorithm.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>model_4</name>
<description>4-time average algorithm.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>model_8</name>
<description>8-time average algorithm.</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ch_vld</name>
<description>Whether the channel is valid.bit[0]–bit[7] correspond to channels A–H, respectively</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL1</name>
<description>LSADC_CTRL1 is the ADC FIFO configuration register.</description>
<addressOffset>0x004</addressOffset>
<size>32</size>
<resetValue>0x00000002</resetValue>
<fields>
<field>
<name>rxintsize</name>
<description>FIFO threshold setting.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x2</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>size_127</name>
<description>127</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>size_124</name>
<description>124</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>size_64</name>
<description>64</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>size_32</name>
<description>32</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>size_16</name>
<description>16</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>size_8</name>
<description>8</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>size_4</name>
<description>4</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>size_1</name>
<description>1</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL2</name>
<description>LSADC_CTRL2 is the ADC interrupt control register.</description>
<addressOffset>0x008</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>rxim</name>
<description>Threshold interrupt mask.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>masked</name>
<description>Masked.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>unmasked</name>
<description>Unmasked.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rorim</name>
<description>FIFO overflow interrupt mask.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>masked</name>
<description>Masked.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>unmasked</name>
<description>Unmasked.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL3</name>
<description>LSADC_CTRL3 is the ADC interrupt clear register.</description>
<addressOffset>0x00C</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>roric</name>
<description>FIFO overflow interrupt clear.</description>
<access>write-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_clear</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL4</name>
<description>LSADC_CTRL4 is the ADC FIFO status register.</description>
<addressOffset>0x010</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>bsy</name>
<description>ADC busy indicator.</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>idle</name>
<description>Idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>busy</name>
<description>Busy.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rff</name>
<description>Whether the FIFO is full.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_full</name>
<description>no.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>full</name>
<description>yes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rne</name>
<description>Whether the FIFO is empty.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>empty</name>
<description>yes.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>not_empty</name>
<description>no.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL5</name>
<description>LSADC_CTRL5 is the ADC raw interrupt status register.</description>
<addressOffset>0x014</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>rxris</name>
<description>Raw RX FIFO interrupt status.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rorris</name>
<description>Raw RX overflow interrupt.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL6</name>
<description>LSADC_CTRL6 is the ADC masked interrupt status register.</description>
<addressOffset>0x018</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>rxmis</name>
<description>Masked RX FIFO interrupt status.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rormis</name>
<description>Masked RX overflow interrupt state.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL7</name>
<description>LSADC_CTRL7 is the ADC start scanning control register.</description>
<addressOffset>0x01C</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>lsadc_start</name>
<description>Masked RX FIFO interrupt status.</description>
<access>write-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>start</name>
<description>Start LSADC.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL8</name>
<description>LSADC_CTRL8 is the ADC stop scanning control register.</description>
<addressOffset>0x020</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>lsadc_stop</name>
<description>Stops auto scanning.</description>
<access>write-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>stop</name>
<description>Disables the scanning function of the LSADC.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL9</name>
<description>LSADC_CTRL9 is the ADC FIFO read data control register.</description>
<addressOffset>0x024</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>dr</name>
<description>Reads ADC data.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL10</name>
<description>LSADC_CTRL10 is the ADC reserve control register.</description>
<addressOffset>0x028</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>lsadc_reg_3to0</name>
<description>General register 4.</description>
<access>read-write</access>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>lsadc_reg2_5to0</name>
<description>General register 3.</description>
<access>read-write</access>
<bitOffset>16</bitOffset>
<bitWidth>6</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>lsadc_reg1_7to6</name>
<description>General register 2.</description>
<access>read-write</access>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>lsadc_reg1_3</name>
<description>General register 1.</description>
<access>read-write</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>lsadc_reg0_6to0</name>
<description>General register 1.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>LSADC_CTRL11</name>
<description>LSADC_CTRL11 is the ADC power-off control register.</description>
<addressOffset>0x02C</addressOffset>
<size>32</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>power_down</name>
<description>ADC power-down control.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>working</name>
<description>Working normally.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>powered_down</name>
<description>Powered down.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- ADC --><peripheral>
<name>HPM</name>
<description>Hardware performance monitor</description>
<baseAddress>0x40068000</baseAddress>
<registers>
<register>
<name>PERI_PMC22</name>
<description>PERI_PMC22 is the HPM0 clock and soft reset control register.</description>
<addressOffset>0x0058</addressOffset>
<size>32</size>
<resetValue>0x0000000A</resetValue>
<fields>
<field>
<name>hpm0_rst_req</name>
<description>HPM0 reset request enable.</description>
<access>read-write</access>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm0_monitor_en</name>
<description>HPM0 cyclic monitoring enable.</description>
<access>read-write</access>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disable</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm0_bypass</name>
<description>Single-time HPM0 enable signal.</description>
<access>read-write</access>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>by_monitor</name>
<description>The start signal of HPM0 is determined by [hpm0_monitor_en].</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>by_peripheral</name> <!-- Is this name appropriate? luojia65 2020/12/31 -->
<description>The start signal of the HPM0 is determined by [hpm0_en].</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm0_en</name>
<description>Single HPM0 measurement enable.</description>
<access>read-write</access>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>retained</name>
<description>The value is retained 0 before a process is started.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>started</name> <!-- Is this name appropriate? luojia65 2020/12/31 -->
<description>A frequency modulation process is started.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm0_offset</name>
<description>Offset after the HPM0 original code word is shifted rightwards.</description>
<access>read-write</access>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm0_shift</name>
<description>Number of right shift bits of the HPM0 original code word.</description>
<access>read-write</access>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm0_div</name>
<description>HPM0 clock divider.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<resetMask>0x0A</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC23</name>
<description>PERI_PMC23 is the HPM0 original code word and alarm information register.</description>
<addressOffset>0x005C</addressOffset>
<size>32</size>
<resetValue>0x0000000A</resetValue>
<fields>
<field>
<name>hpm0_up_warning</name>
<description>Report flag when the HPM0 original code word exceeds the upper threshold.</description>
<access>read-only</access>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_exceed</name>
<description>The value does not exceed the upper threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>exceed</name>
<description>The value exceeds the upper threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm0_low_warning</name>
<description>Report flag when the HPM0 original code word is lower than the lower threshold.</description>
<access>read-only</access>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_lower</name>
<description>The value is not lower than the lower threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>lower</name>
<description>The value is lower than the lower threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm0_pc_record1</name>
<description>Reported value of the HPM0 original code word (the last historical value).</description>
<access>read-only</access>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm0_pc_valid</name>
<description>HPM0 output validity indicator.</description>
<access>read-only</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>last_value</name>
<description>the last read value of [hpm0_pc_record0].</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>current_value</name>
<description> the current read value of [hpm0_pc_record0].</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm0_pc_record0</name>
<description>Reported value of the HPM0 original code word (current value).</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC24</name>
<description>PERI_PMC24 is the HPM0 original code word and RCC code report register.</description>
<addressOffset>0x0060</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>hpm0_rcc</name>
<description>RCC code output by the HPM0.</description>
<access>read-only</access>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm0_pc_record3</name>
<description>Reported value of the HPM0 original code word (last three historical values).</description>
<access>read-only</access>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm0_pc_record2</name>
<description>Reported value of the HPM0 original code word (last two historical values).</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC25</name>
<description>PERI_PMC25 is the HPM0 original code pattern threshold configuration register.</description>
<addressOffset>0x0064</addressOffset>
<size>32</size>
<resetValue>0x01000000</resetValue>
<fields>
<field>
<name>hpm0_monitor_period</name>
<description>HPM0 cyclic monitoring period.</description>
<access>read-write</access>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x01</resetMask>
</field>
<field>
<name>hpm0_lowlimit</name>
<description>Lower limit of the HPM0 original code pattern.</description>
<access>read-write</access>
<bitOffset>12</bitOffset>
<bitWidth>11</bitWidth>
<resetMask>0x01</resetMask>
</field>
<field>
<name>hpm0_uplimit</name>
<description>Upper limit of the HPM0 original code pattern.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC26</name>
<description>PERI_PMC26 is the HPM1 clock and soft reset control register.</description>
<addressOffset>0x0068</addressOffset>
<size>32</size>
<resetValue>0x0000000A</resetValue>
<fields>
<field>
<name>hpm1_rst_req</name>
<description>HPM1 reset request enable.</description>
<access>read-write</access>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm1_monitor_en</name>
<description>HPM1 cyclic monitoring enable.</description>
<access>read-write</access>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm1_bypass</name>
<description>Single-time HPM1 enable signal.</description>
<access>read-write</access>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>by_monitor</name>
<description>The start signal of HPM1 is determined by [hpm1_monitor_en].</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>by_peripheral</name>
<description>The start signal of the HPM1 is determined by [hpm1_en].</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm1_en</name>
<description>Single HPM1 measurement enable.</description>
<access>read-write</access>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>retained</name>
<description>The value is retained 0 before a process is started.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>started</name>
<description>A frequency modulation process is started.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm1_offset</name>
<description>Offset after the HPM1 original code word is shifted rightwards.</description>
<access>read-write</access>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm1_shift</name>
<description>Number of right shift bits of the HPM1 original code word.</description>
<access>read-write</access>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm1_div</name>
<description>HPM1 clock divider.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC27</name>
<description>PERI_PMC27 is the HPM1 original code word and alarm information register.</description>
<addressOffset>0x006C</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>hpm1_up_warning</name>
<description>Report flag when the HPM1 original code word exceeds the upper threshold.</description>
<access>read-only</access>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_exceed</name>
<description>The value does not exceed the upper threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>exceed</name>
<description>The value exceeds the upper threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm1_low_warning</name>
<description>Report flag when the HPM1 original code word is lower than the lower threshold.</description>
<access>read-only</access>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_lower</name>
<description>The value is not lower than the lower threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>lower</name>
<description>The value is lower than the lower threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm1_pc_record1</name>
<description>Reported value of the HPM1 original code word (last historical value).</description>
<access>read-only</access>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm1_pc_valid</name>
<description>HPM1 output validity indicator.</description>
<access>read-only</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>last_value</name>
<description>the last read value of [hpm1_pc_record0].</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>current_value</name>
<description> the current read value of [hpm1_pc_record0].</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm1_pc_record0</name>
<description>Reported value of the HPM1 original code word (current value).</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC28</name>
<description>PERI_PMC28 is the HPM1 original code word and RCC code report register.</description>
<addressOffset>0x0070</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>hpm1_rcc</name>
<description>RCC code output by HPM1.</description>
<access>read-only</access>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm1_pc_record3</name>
<description>Reported value of the HPM1 original code word (last three historical values).</description>
<access>read-only</access>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm1_pc_record2</name>
<description>Reported value of the HPM1 original code word (last two historical values).</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC29</name>
<description>PERI_PMC29 is the HPM1 original code pattern threshold configuration register.</description>
<addressOffset>0x0074</addressOffset>
<size>32</size>
<resetValue>0x01000000</resetValue>
<fields>
<field>
<name>hpm1_rcc</name>
<description>hpm1_monitor_period.</description>
<access>read-write</access>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x1</resetMask>
</field>
<field>
<name>hpm1_lowlimit</name>
<description>Lower limit of the HPM1 original code pattern.</description>
<access>read-write</access>
<bitOffset>12</bitOffset>
<bitWidth>12</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm1_uplimit</name>
<description>Upper limit of the HPM1 original code pattern.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC30</name>
<description>HPM2 reset request enable.</description>
<addressOffset>0x0078</addressOffset>
<size>32</size>
<resetValue>0x0000000A</resetValue>
<fields>
<field>
<name>hpm2_rst_req</name>
<description>hpm1_monitor_period.</description>
<access>read-write</access>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm2_monitor_en</name>
<description>HPM2 cyclic monitoring enable.</description>
<access>read-write</access>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm2_bypass</name>
<description>Single-time HPM2 enable signal.</description>
<access>read-write</access>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>by_monitor</name>
<description>The start signal of HPM2 is determined by [hpm2_monitor_en].</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>by_peripheral</name>
<description>The start signal of the HPM2 is determined by [hpm2_en].</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm2_en</name>
<description>Single HPM2 measurement enable.</description>
<access>read-write</access>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>retained</name>
<description>The value is retained 0 before a process is started.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>started</name>
<description>A frequency modulation process is started.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm2_offset</name>
<description>Offset after the HPM2 original code word is shifted rightwards.</description>
<access>read-write</access>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm2_shift</name>
<description>Number of right shift bits of the original HPM2 code word.</description>
<access>read-write</access>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm2_div</name>
<description>HPM2 clock divider.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC31</name>
<description>PERI_PMC31 is the HPM2 original code word and alarm information register.</description>
<addressOffset>0x007C</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>hpm2_up_warning</name>
<description>Report flag when the HPM2 original code word exceeds the upper threshold.</description>
<access>read-only</access>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_exceed</name>
<description>The value does not exceed the upper threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>exceed</name>
<description>The value exceeds the upper threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm2_low_warning</name>
<description>Report flag when the HPM2 original code word is lower than the lower threshold.</description>
<access>read-only</access>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_lower</name>
<description>The value is not lower than the lower threshold.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>lower</name>
<description>The value is lower than the lower threshold.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm2_pc_record1</name>
<description>Reported value of the HPM2 original code word (last historical value).</description>
<access>read-only</access>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm2_pc_valid</name>
<description>HPM2 output validity indicator.</description>
<access>read-only</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>last_value</name>
<description>the last read value of [hpm2_pc_record0].</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>current_value</name>
<description>the current read value of [hpm2_pc_record0].</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>hpm2_pc_record0</name>
<description>Reported value of the HPM2 original code word (current value).</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC32</name>
<description>PERI_PMC32 is the HPM2 original code word and RCC code report register.</description>
<addressOffset>0x0080</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>hpm2_rcc</name>
<description>RCC code output by HPM2.</description>
<access>read-only</access>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm2_pc_record3</name>
<description>Reported value of the HPM2 original code word (last three historical values).</description>
<access>read-only</access>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>hpm2_pc_record2</name>
<description>Reported value of the HPM2 original code word (last two historical values).</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>PERI_PMC33</name>
<description>PERI_PMC33 is the HPM2 original code pattern threshold configuration register.</description>
<addressOffset>0x0084</addressOffset>
<size>32</size>
<resetValue>0x01000000</resetValue>
<fields>
<field>
<name>hpm2_monitor_period</name>
<description>HPM2 cyclic monitoring period.</description>
<access>read-write</access>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x1</resetMask>
</field>
<field>
<name>hpm2_lowlimit</name>
<description>Lower limit of the HPM2 original code pattern.</description>
<access>read-write</access>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x1</resetMask>
</field>
<field>
<name>hpm2_uplimit</name>
<description>Upper limit of the HPM2 original code pattern.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<resetMask>0x1</resetMask>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- I2C0 -->
<peripheral>
<name>I2C0</name>
<description>Inter-Integrated Circuit Bus 0</description>
<groupName>I2C</groupName>
<baseAddress>0x40018000</baseAddress>
<interrupt>
<name>I2C0</name>
<description>I2C0 interrupt</description>
<value>41</value>
</interrupt>
<registers>
<register>
<name>I2C_CTRL</name>
<description>I2C_CTRL is the I2C control register, used to enable I2C peripheral and mask interrupts.</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>int_txfifo_over_mask</name>
<description>TX FIFO data completion interrupt mask.</description>
<access>read-write</access>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>mode_ctrl</name>
<description>I2C operating mode select.</description>
<access>read-write</access>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_used</name>
<description>The FIFO transmission mode is not used.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>used</name>
<description>The FIFO transmission mode is used.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_txtide_mask</name>
<description>TX FIFO overflow interrupt mask.</description>
<access>read-write</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_rxtide_mask</name>
<description>RX FIFO overflow interrupt mask.</description>
<access>read-write</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>i2c_en</name>
<description>I2C enable.</description>
<access>read-write</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_mask</name>
<description>General I2C interrupt mask.</description>
<access>read-write</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_start_mask</name>
<description>TX completion interrupt mask for the start condition of the master.</description>
<access>read-write</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_stop_mask</name>
<description>TX completion interrupt mask for the stop condition of the master.</description>
<access>read-write</access>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_tx_mask</name>
<description>Master TX interrupt mask.</description>
<access>read-write</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_rx_mask</name>
<description>Master RX interrupt mask.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_ack_err_mask</name>
<description>Slave ACK error interrupt mask.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_arb_loss_mask</name>
<description>Bus arbitration failure interrupt mask.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_done_mask</name>
<description>Bus transfer completion interrupt mask.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>I2C_COM</name>
<description>I2C_COM is the I2C command register. It is used to configure the commands for the working of the I2C module.</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>op_ack</name>
<description>Whether the master sends an ACK as a receiver.</description>
<access>read-write</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>yes</name>
<description>yes.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>no</name>
<description>no.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>op_start</name>
<description>Generation of the start condition.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>complete</name>
<description>The operation is complete.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The operation is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>op_rd</name>
<description>Generation of the read operation.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>complete</name>
<description>The operation is complete.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The operation is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>op_we</name>
<description>Generation of the write operation.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>complete</name>
<description>The operation is complete.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The operation is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>op_stop</name>
<description>Generation of the stop condition.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>complete</name>
<description>The operation is complete.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>The operation is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>I2C_ICR</name>
<description>I2C_ICR is the I2C interrupt clear register.</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>clr_int_txfifo_over</name>
<description>TX FIFO data completion interrupt clear.</description>
<access>write-only</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>clr_int_txtide</name>
<description>TX FIFO overflow interrupt clear.</description>
<access>write-only</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>clr_int_rxtide</name>
<description>RX FIFO overflow interrupt clear.</description>
<access>write-only</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>clr_int_start</name>
<description>TX completion interrupt clear for the start condition of the master.</description>
<access>write-only</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>clr_int_stop</name>
<description>TX completion interrupt clear for the stop condition of the master.</description>
<access>write-only</access>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>clr_int_tx</name>
<description>Master TX interrupt clear.</description>
<access>write-only</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>clr_int_rx</name>
<description>Master RX interrupt clear.</description>
<access>write-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>clr_int_ack_err</name>
<description>Slave ACK error interrupt clear.</description>
<access>write-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>clr_int_arb_loss</name>
<description>Bus arbitration failure interrupt clear.</description>
<access>write-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>clr_int_done</name>
<description>Bus transfer completion interrupt clear.</description>
<access>write-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>I2C_SR</name>
<description>I2C_SR is the I2C module status register. It is used to read the operating status of the I2C module.</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>int_txfifo_over</name>
<description>TX FIFO data completion interrupt.</description>
<access>read-only</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_generated</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>generated</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_txtide</name>
<description>TX FIFO overflow interrupt.</description>
<access>read-only</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_generated</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>generated</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_rxtide</name>
<description>RX FIFO overflow interrupt.</description>
<access>read-only</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_generated</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>generated</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>bus_busy</name>
<description>Bus busy flag.</description>
<access>read-only</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>idle</name>
<description>idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>busy</name>
<description>busy.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_start</name>
<description>TX completion interrupt for the start condition of the master.</description>
<access>read-only</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_generated</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>generated</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_stop</name>
<description>TX completion interrupt for the stop condition of the master.</description>
<access>read-only</access>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_generated</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>generated</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_tx</name>
<description>Master TX interrupt flag.</description>
<access>read-only</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_generated</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>generated</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_rx</name>
<description>Master RX interrupt flag.</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_generated</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>generated</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_ack_err</name>
<description>Slave ACK error interrupt flag.</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_generated</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>generated</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_arb_loss</name>
<description>Failure interrupt flag for the bus arbitration.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_generated</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>generated</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>int_done</name>
<description>Bus transfer completion interrupt flag.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_generated</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>generated</name>
<description>An interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>I2C_SCL_H</name>
<description>I2C_SCL_H is the I2C SCL high-level cycle count register. It is used to configure the number of SCL high-level cycles when the I2C module is working.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>scl_h</name>
<description>Number of SCL high-level cycles. The actual number of SCL high-level cycles is 2 times the configured value.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<resetMask>0x0000</resetMask>
</field>
</fields>
</register>
<register>
<name>I2C_SCL_L</name>
<description>I2C_SCL_L is the I2C SCL low-level cycle count register. It is used to configure the number of SCL low-level cycles when the I2C module is working.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>scl_l</name>
<description>Number of SCL low-level cycles. The actual number of SCL low-level cycles is 2 times the configured value.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<resetMask>0x0000</resetMask>
</field>
</fields>
</register>
<register>
<name>I2C_TXR</name>
<description>I2C_TXR is the I2C TX data register. It is used to configure the data to be transmitted when the I2C module is working.</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>i2c_txr</name>
<description>Data TX by the master.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x0000</resetMask>
</field>
</fields>
</register>
<register>
<name>I2C_RXR</name>
<description>I2C_RXR is the I2C RX data register. It is used for the master to receive data from the slave.</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>i2c_rxr</name>
<description>Data received by the master.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x0000</resetMask>
</field>
</fields>
</register>
<register>
<name>I2C_FIFOSTATUS</name>
<description>I2C_FIFOSTATUS is the fifo status register.</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>rxfe</name>
<description>Is receive FIFO empty?</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_empty</name>
<description>not empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>empty</name>
<description>empty.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxff</name>
<description>Is receive FIFO full?</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_full</name>
<description>not full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>full</name>
<description>full.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>txfe</name>
<description>Is transmit FIFO empty?</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_empty</name>
<description>not empty.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>empty</name>
<description>empty.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>txff</name>
<description>Is transmit FIFO full?</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_full</name>
<description>not full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>full</name>
<description>full.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>I2C_TXCOUNT</name>
<description>I2C_TXCOUNT is the register for transmit FIFO data count.</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>txcount</name>
<description>Read this register to return the data byte count in transmit FIFO, write any value to this register to clear the transmit FIFO.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<resetMask>0x00</resetMask>
</field>
</fields>
</register>
<register>
<name>I2C_RXCOUNT</name>
<description>I2C_RXCOUNT is the register for receive FIFO data count.</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>rxcount</name>
<description>Read this register to return the data byte count in receive FIFO, write any value to this register to clear the receive FIFO.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<resetMask>0x00</resetMask>
</field>
</fields>
</register>
<register>
<name>I2C_RXTIDE</name>
<description>I2C_RXTIDE is the register for receive FIFO overflow limit.</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>rxtide</name>
<description>Sets the trigger limit in receive FIFO for int_rxtide interrupt. When character count in receive FIFO >= rxtide, will trigger FIFO overflow interrupt.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<resetMask>0x01</resetMask>
</field>
</fields>
</register>
<register>
<name>I2C_TXTIDE</name>
<description>I2C_TXTIDE is the register for transmit FIFO overflow limit. When character count in transmit FIFO <= txtide, will trigger FIFO overflow interrupt.</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>rxtide</name>
<description>Sets the trigger limit in transmit FIFO for int_txtide interrupt.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<resetMask>0x01</resetMask>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- I2C0 -->
<!-- I2C1 -->
<peripheral derivedFrom="I2C0">
<name>I2C1</name>
<description>Inter-Integrated Circuit Bus 1</description>
<baseAddress>0x40019000</baseAddress>
<interrupt>
<name>I2C1</name>
<description>I2C1 interrupt</description>
<value>42</value>
</interrupt>
</peripheral>
<!-- I2C1 -->
<!-- I2S -->
<peripheral>
<name>I2S0</name>
<groupName>I2S</groupName>
<description>The I2S module works as a slave device on the advanced peripheral bus (APB) while a master device on the I2S bus.</description>
<baseAddress>0xF8CC0000</baseAddress>
<interrupt>
<name>I2S0</name>
<description>I2S0 interrupt</description>
<value>59</value>
</interrupt>
<registers>
<register>
<name>AUDIO_AIAO_CTRL</name>
<description>AUDIO_AIAO_CTRL is the control register.</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<resetValue>0x00709000</resetValue>
<fields>
<field>
<name>tx_rerror_int_mask</name>
<description>TX FIFO underflow interrupt enable.</description>
<access>read-write</access>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rx_werror_int_mask</name>
<description>RX FIFO overflow interrupt enable.</description>
<access>read-write</access>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<!-- other value 8 -->
<field>
<name>aiao_fsclk_div</name>
<description>Frequency ratio of BCLK to WS.</description>
<access>read-write</access>
<bitOffset>21</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x3</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>div_16</name>
<description>16.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>div_32</name>
<description>32.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>div_48</name>
<description>48.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>div_64</name>
<description>64.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>div_128</name>
<description>128.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>div_256</name>
<description>256.</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>aiao_bclk_div</name>
<description>Frequency ratio of MCLK to BCLK.</description>
<access>read-write</access>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
<resetMask>0x3</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>div_1</name>
<description>1.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>div_3</name>
<description>3.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>div_2</name>
<description>2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>div_4</name>
<description>4.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>div_6</name>
<description>6.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>div_8</name>
<description>8.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>div_12</name>
<description>12.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>div_16</name>
<description>16.</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>div_24</name>
<description>24.</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>div_32</name>
<description>32.</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>div_48</name>
<description>48.</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>div_64</name>
<description>64.</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>div_96</name>
<description>96.</description>
<value>0xC</value>
</enumeratedValue>
<!-- other values are reserved -->
</enumeratedValues>
</field>
<field>
<name>dma_tx_level</name>
<description>TX FIFO threshold.</description>
<access>read-write</access>
<bitOffset>14</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x2</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>level_2</name>
<description>2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>level_4</name>
<description>4.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>level_8</name>
<description>8.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>level_12</name>
<description>12.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>level_14</name>
<description>14.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dma_rx_level</name>
<description>RX FIFO threshold.</description>
<access>read-write</access>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x2</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>level_2</name>
<description>2.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>level_4</name>
<description>4.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>level_8</name>
<description>8.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>level_12</name>
<description>12.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>level_14</name>
<description>14.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>aiao_ck_gt_en</name>
<description>Low power consumption enable.</description>
<access>read-write</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>Clock disabled.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>Clock enabled.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tx_level_int_mask</name>
<description>TX threshold interrupt enable.</description>
<access>read-write</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tx_unfull_int_mask</name>
<description>TX unfull interrupt enable.</description>
<access>read-write</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rx_level_int_mask</name>
<description>RX threshold interrupt enable.</description>
<access>read-write</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rx_unempty_int_mask</name>
<description>RX non-empty interrupt enable.</description>
<access>read-write</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dma_tx_en</name>
<description>DMA TX enable.</description>
<access>read-write</access>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dma_rx_en</name>
<description>DMA RX enable.</description>
<access>read-write</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>bclk_inv_en</name>
<description>Output BCLK phase reverse enable.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_invert</name>
<description>The output BCLK phase does not change.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>invert</name>
<description>The Output BCLK phase is inverted.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tx_en</name>
<description>TX enable.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rx_en</name>
<description>RX enable.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>data_bit</name>
<description>Bit width.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>width_16</name>
<description>16-bit.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>width_24</name>
<description>24-bit.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AUDIO_AIAO_RX_FIFO_INT_CLR</name>
<description>AUDIO_AIAO_RX_FIFO_INT_CLR is the RX_FIFO interrupt clear register.</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>rx_fifo_int_clr</name>
<description>RX FIFO overflow interrupt clear.</description>
<access>read-write</access>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AUDIO_AIAO_TX_FIFO_INT_CLR</name>
<description>AUDIO_AIAO_TX_FIFO_INT_CLR is the ATX_FIFO interrupt clear register.</description>
<addressOffset>0x0008</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>tx_fifo_int_clr</name>
<description>TX FIFO underflow interrupt clear.</description>
<access>read-write</access>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_cleared</name>
<description>not cleared.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cleared</name>
<description>cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AUDIO_AIAO_BCLK_CNT</name>
<description>AUDIO_AIAO_BCLK_CNT is the BCLK_CNT register.</description>
<addressOffset>0x000C</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>bclk_cnt</name>
<description>Debug register.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>AUDIO_AIAO_INT</name>
<description>AUDIO_AIAO_INT is the interrupt register.</description>
<addressOffset>0x0010</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>tx_rerror_int</name>
<description>TX FIFO overflow interrupt source flag (with mask).</description>
<access>read-only</access>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tx_rerror_int_unmask</name>
<description>TX FIFO overflow interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tx_level_int</name>
<description>TX FIFO threshold interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tx_level_int_unmask</name>
<description>TX FIFO threshold interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tx_unfull_int</name>
<description>TX FIFO unfull interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tx_unfull_int_unmask</name>
<description>TX FIFO unfull interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rx_werror_int</name>
<description>RX FIFO overflow interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rx_werror_int_unmask</name>
<description>RX FIFO overflow interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rx_level_int</name>
<description>RX FIFO threshold interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rx_level_int_unmask</name>
<description>RX FIFO threshold interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rx_unempty_int</name>
<description>RX FIFO non-empty interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rx_unempty_int_unmask</name>
<description>RX FIFO non-empty interrupt source flag (without mask).</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AUDIO_AIAO_DMA_WR</name>
<description>AUDIO_AIAO_DMA_WR is the DMA write address register.</description>
<addressOffset>0x0014</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>dma_wr_addr</name>
<description>The DMA writes data to the AIAO through this address.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>AUDIO_AIAO_DMA_RD</name>
<description>AUDIO_AIAO_DMA_RD is the DMA read address register.</description>
<addressOffset>0x0018</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>dma_rd_addr</name>
<description>The DMA reads data from the AIAO through this address.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- I2S --><!-- PWM0 -->
<peripheral>
<name>PWM0</name>
<description>The PWM module is used to generate PWM signals and adjust the illuminator brightness.</description>
<baseAddress>0x40040000</baseAddress>
<registers>
<register>
<name>PWM_EN</name>
<description>PWM_EN is the PWM enable register.</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<resetValue>0x1</resetValue>
<fields>
<field>
<name>pwm_en</name>
<description>PWM function enable.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.The pwm_out is always 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWM_START</name>
<description>PWM_START is the PWM configuration enforce register.</description>
<addressOffset>0x04</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>pwm_start</name>
<description>PWM configuration enforce register.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PWM_FREQ</name>
<description>PWM_FREQ is the PWM frequency control count value register.</description>
<addressOffset>0x08</addressOffset>
<size>32</size>
<resetValue>0x000005DC</resetValue>
<fields>
<field>
<name>pwm_freq</name>
<description>PWM frequency control count value.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<resetMask>0x05DC</resetMask>
</field>
</fields>
</register>
<register>
<name>PWM_DUTY</name>
<description>PWM_DUTY is the PWM duty cycle count value register.</description>
<addressOffset>0x0C</addressOffset>
<size>32</size>
<resetValue>0x000002EE</resetValue>
<fields>
<field>
<name>pwm_duty</name>
<description>PWM duty cycle control count value.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<resetMask>0x02EE</resetMask>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- PWM0 -->
<!-- PWM1 -->
<peripheral derivedFrom="PWM0">
<name>PWM1</name>
<description>The PWM module is used to generate PWM signals and adjust the illuminator brightness.</description>
<baseAddress>0x40040100</baseAddress>
</peripheral>
<!-- PWM1 -->
<!-- PWM2 -->
<peripheral derivedFrom="PWM0">
<name>PWM2</name>
<description>The PWM module is used to generate PWM signals and adjust the illuminator brightness.</description>
<baseAddress>0x40040200</baseAddress>
</peripheral>
<!-- PWM2 -->
<!-- PWM3 -->
<peripheral derivedFrom="PWM0">
<name>PWM3</name>
<description>The PWM module is used to generate PWM signals and adjust the illuminator brightness.</description>
<baseAddress>0x40040300</baseAddress>
</peripheral>
<!-- PWM3 -->
<!-- PWM4 -->
<peripheral derivedFrom="PWM0">
<name>PWM4</name>
<description>The PWM module is used to generate PWM signals and adjust the illuminator brightness.</description>
<baseAddress>0x40040400</baseAddress>
</peripheral>
<!-- PWM4 -->
<!-- PWM5 -->
<peripheral derivedFrom="PWM0">
<name>PWM5</name>
<description>The PWM module is used to generate PWM signals and adjust the illuminator brightness.</description>
<baseAddress>0x40040500</baseAddress>
</peripheral>
<!-- PWM5 --><!-- SPI0 -->
<peripheral>
<name>SPI0</name>
<description>Serial peripheral interface 0</description>
<groupName>SPI</groupName>
<baseAddress>0x40058000</baseAddress>
<interrupt>
<name>SPI0</name>
<description>SPI0 interrupt</description>
<value>43</value>
</interrupt>
<registers>
<register>
<name>SPICR0</name>
<description>SPICR0 is SPI control register 0.</description>
<addressOffset>0x00</addressOffset>
<size>16</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>scr</name>
<description>Serial clock rate, ranging from 0 to 255.</description>
<access>read-write</access>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x00</resetMask>
</field>
<field>
<name>sph</name>
<description>SPICLKOUT phase.</description>
<access>read-write</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>spo</name>
<description>SPICLKOUT polarity.</description>
<access>read-write</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
</field>
<field>
<name>frf</name>
<description>Frame format select.</description>
<access>read-write</access>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>motorola_spi</name>
<description>Motorola SPI frame format.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ti_synchronous</name>
<description>TI synchronous serial frame.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>national_microwire</name>
<description>National Microwire frame format.</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dss</name>
<description>Data bit width.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>width_4</name>
<description>4 bits.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>width_5</name>
<description>5 bits.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>width_6</name>
<description>6 bits.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>width_7</name>
<description>7 bits.</description>
<value>0x6</value>
</enumeratedValue>
<enumeratedValue>
<name>width_8</name>
<description>8 bits.</description>
<value>0x7</value>
</enumeratedValue>
<enumeratedValue>
<name>width_9</name>
<description>9 bits.</description>
<value>0x8</value>
</enumeratedValue>
<enumeratedValue>
<name>width_10</name>
<description>10 bits.</description>
<value>0x9</value>
</enumeratedValue>
<enumeratedValue>
<name>width_11</name>
<description>11 bits.</description>
<value>0xA</value>
</enumeratedValue>
<enumeratedValue>
<name>width_12</name>
<description>12 bits.</description>
<value>0xB</value>
</enumeratedValue>
<enumeratedValue>
<name>width_13</name>
<description>13 bits.</description>
<value>0xC</value>
</enumeratedValue>
<enumeratedValue>
<name>width_14</name>
<description>14 bits.</description>
<value>0xD</value>
</enumeratedValue>
<enumeratedValue>
<name>width_15</name>
<description>15 bits.</description>
<value>0xE</value>
</enumeratedValue>
<enumeratedValue>
<name>width_16</name>
<description>16 bits.</description>
<value>0xF</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPICR1</name>
<description>SPICR1 is SPI control register 1.</description>
<addressOffset>0x004</addressOffset>
<size>16</size>
<resetValue>0x7F00</resetValue>
<fields>
<field>
<name>bigend</name>
<description>Data endian mode.</description>
<access>read-write</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>le</name>
<description>little endian.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>be</name>
<description>big endian.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ms</name>
<description>Master or slave mode.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>master</name>
<description>master mode (default value).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>slave</name>
<description>slave mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>sse</name>
<description>SPI enable.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>lbm</name>
<description>Set loopback mode.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>normal</name>
<description>The normal serial port operation is enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>outloop</name>
<description>outloop mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPIDR</name>
<description>SPIDR is the SPI TX/RX data register.</description>
<access>read-write</access>
<addressOffset>0x008</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
</register>
<register>
<name>SPISR</name>
<description>SPISR is the SPI status register.</description>
<addressOffset>0x00C</addressOffset>
<size>16</size>
<resetValue>0x0003</resetValue>
<fields>
<field>
<name>bsy</name>
<description>SPI busy indicator.</description>
<access>read-only</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>idle</name>
<description>idle.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>busy</name>
<description>busy.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rff</name>
<description>Whether the RX FIFO is full.</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_full</name>
<description>no.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>full</name>
<description>full.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rne</name>
<description>Whether the RX FIFO is empty.</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_empty</name>
<description>no.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>empty</name>
<description>yes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tnf</name>
<description>Whether the TX FIFO is full.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_full</name>
<description>no.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>full</name>
<description>full.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tfe</name>
<description>Whether the TX FIFO is empty.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_empty</name>
<description>no.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>empty</name>
<description>yes.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPICPSR</name>
<description>SPICPSR is the SPI clock frequency division register..</description>
<addressOffset>0x010</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>cpsdvsr</name>
<description>Clock divider.The value must be an even number ranging from 2 to 254.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x00</resetMask>
</field>
</fields>
</register>
<register>
<name>SPIIMSC</name>
<description>SPIIMSC is the SPI interrupt mask register.</description>
<addressOffset>0x014</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>txim</name>
<description>Interrupt mask when the TX FIFO is half empty or less.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxim</name>
<description>Whether the RX FIFO is full.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rtim</name>
<description>RX timeout interrupt mask.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rorim</name>
<description>RX FIFO overflow interrupt mask.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPIRIS</name>
<description>SPIRIS is the raw interrupt status register.</description>
<addressOffset>0x018</addressOffset>
<size>16</size>
<resetValue>0x0008</resetValue>
<fields>
<field>
<name>txris</name>
<description>Raw TX FIFO interrupt status.</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxris</name>
<description>Raw RX FIFO interrupt status.</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rtris</name>
<description>Raw RX timeout interrupt status.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rorris</name>
<description>Raw RX overflow interrupt status.</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPIMIS</name>
<description>SPIMIS is the SPI masked interrupt status register.</description>
<addressOffset>0x01C</addressOffset>
<size>16</size>
<resetValue>0x0008</resetValue>
<fields>
<field>
<name>txmis</name>
<description>Masked TX FIFO interrupt status.</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxmis</name>
<description>Masked RX FIFO interrupt status.</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rtmis</name>
<description>Masked RX timeout interrupt state.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated..</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rormis</name>
<description>Masked RX overflow interrupt state.</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated..</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>The interrupt is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPIICR</name>
<description>SPIICR is the SPI interrupt clear register.</description>
<addressOffset>0x020</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>rtic</name>
<description>RX timeout interrupt clear.</description>
<access>write-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>Writing 1 clears the interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>roric</name>
<description>RX overflow interrupt clear.</description>
<access>write-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>interrupt cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPIDMACR</name>
<description>SPIDMACR is an SPI DMA enable register.</description>
<addressOffset>0x024</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>dmatxen</name>
<description>SPI DMA TX enable.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dmarxen</name>
<description>SPI DMA RX enable.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPITXFIFOCR</name>
<description>SPITXFIFOCR is the SPI TX FIFO control register.</description>
<addressOffset>0x028</addressOffset>
<size>16</size>
<resetValue>0x0009</resetValue>
<fields>
<field>
<name>txintsize</name>
<description>Threshold for triggering a TX FIFO interrupt.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>threshold_1</name>
<description>1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_4</name>
<description>4.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_8</name>
<description>8.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_16</name>
<description>16.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_32</name>
<description>32.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_64</name>
<description>64.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_128</name>
<description>128.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_192</name>
<description>192.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dmatxbrsizepclk</name>
<description>Configures the burst request of the TX FIFO.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>threshold_255</name>
<description>The threshold level is 255.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_252</name>
<description>The threshold level is 252.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_248</name>
<description>The threshold level is 248.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_240</name>
<description>The threshold level is 240.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_224</name>
<description>The threshold level is 224.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_192</name>
<description>The threshold level is 192.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_128</name>
<description>The threshold level is 128.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_64</name>
<description>The threshold level is 64.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPIRXFIFOCR</name>
<description>SPIRXFIFOCR is the SPI RX FIFO control register.</description>
<addressOffset>0x02C</addressOffset>
<size>16</size>
<resetValue>0x0009</resetValue>
<fields>
<field>
<name>rxintsize</name>
<description>Threshold for triggering an RX FIFO interrupt.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>threshold2552</name>
<description>255.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_252</name>
<description>252.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_248</name>
<description>248.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_240</name>
<description>240.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_224</name>
<description>224.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_192</name>
<description>192.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_128</name>
<description>128.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_32</name>
<description>32.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dmarxbrsizepclk</name>
<description>Configures the burst request of the RX FIFO.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>threshold_1</name>
<description>The threshold level is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_4</name>
<description>The threshold level is 4.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_8</name>
<description>The threshold level is 8.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_16</name>
<description>The threshold level is 16.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_32</name>
<description>The threshold level is 32.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_64</name>
<description>The threshold level is 64.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_128</name>
<description>The threshold level is 128.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_192</name>
<description>The threshold level is 192.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- SPI0 -->
<!-- SPI1 -->
<peripheral derivedFrom="SPI0">
<name>SPI1</name>
<description>Serial peripheral interface 1</description>
<groupName>SPI</groupName>
<baseAddress>0x40059000</baseAddress>
<interrupt>
<name>SPI1</name>
<description>SPI1 interrupt</description>
<value>44</value>
</interrupt>
<registers>
<register>
<name>SPITXFIFOCR</name>
<description>SPITXFIFOCR is the SPI TX FIFO control register.</description>
<addressOffset>0x028</addressOffset>
<size>16</size>
<resetValue>0x0009</resetValue>
<fields>
<field>
<name>txintsize</name>
<description>Threshold for triggering a TX FIFO interrupt.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>threshold_1</name>
<description>1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_4</name>
<description>4.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_8</name>
<description>8.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_16</name>
<description>16.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_32</name>
<description>32.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_48</name>
<description>48.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_56</name>
<description>56.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_64</name>
<description>64.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dmatxbrsizepclk</name>
<description>Configures the burst request of the TX FIFO.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>threshold_63</name>
<description>The threshold level is 63.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_60</name>
<description>The threshold level is 60.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_48</name>
<description>The threshold level is 48.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_32</name>
<description>The threshold level is 32.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_16</name>
<description>The threshold level is 16.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_8</name>
<description>The threshold level is 8.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_4</name>
<description>The threshold level is 4.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_1</name>
<description>The threshold level is 1.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SPIRXFIFOCR</name>
<description>SPIRXFIFOCR is the SPI RX FIFO control register.</description>
<addressOffset>0x02C</addressOffset>
<size>16</size>
<resetValue>0x0009</resetValue>
<fields>
<field>
<name>rxintsize</name>
<description>Threshold for triggering an RX FIFO interrupt.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>threshold_65</name>
<description>65.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_62</name>
<description>62.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_48</name>
<description>48.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_32</name>
<description>32.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_16</name>
<description>16.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_8</name>
<description>8.</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_4</name>
<description>4.</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_1</name>
<description>1.</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dmarxbrsizepclk</name>
<description>Configures the burst request of the RX FIFO.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>threshold_1</name>
<description>The threshold level is 1.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_4</name>
<description>The threshold level is 4.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_8</name>
<description>The threshold level is 8.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_16</name>
<description>The threshold level is 16.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_32</name>
<description>The threshold level is 32.</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>threshold_64</name>
<description>The threshold level is 64.</description>
<value>5</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- SPI1 --><!-- UART0 -->
<peripheral>
<name>UART0</name>
<description>Universal asynchronous receiver 0</description>
<groupName>UART</groupName>
<baseAddress>0x40008000</baseAddress>
<interrupt>
<name>UART0</name>
<description>UART0 interrupt</description>
<value>38</value>
</interrupt>
<registers>
<register>
<name>UART_DR</name>
<description>UART_DR is the UART data register.</description>
<addressOffset>0x000</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>oe</name>
<description>Overflow error status.</description>
<access>read-only</access>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_error</name>
<description>No overflow error occurs.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_error</name>
<description>An overflow error occurs.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>be</name>
<description>Break error status.</description>
<access>read-only</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_error</name>
<description>No break error occurs.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_error</name>
<description>A break error occurs.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>pe</name>
<description>Parity error status.</description>
<access>read-only</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_error</name>
<description>No parity error occurs.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_error</name>
<description>A parity error occurs.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>fe</name>
<description>Frame error status.</description>
<access>read-only</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_error</name>
<description>No frame error is detected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_error</name>
<description>A frame error occurs.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>data</name>
<description>Data to be transmitted and received.</description>
<access>read-write</access>
<bitOffset>7</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x00</resetMask>
</field>
</fields>
</register>
<register>
<name>UART_RSR</name>
<description>UART_RSR is the RX status register or error clear register.</description>
<addressOffset>0x004</addressOffset>
<size>8</size>
<resetValue>0x00</resetValue>
<fields>
<field>
<name>oe</name>
<description>Overflow error status and clear.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_error</name>
<description>No overflow error occurs.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_error</name>
<description>An overflow error occurs.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>be</name>
<description>OBreak error status and clear.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_error</name>
<description>No break error occurs.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_error</name>
<description>A break error occurs.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>pe</name>
<description>Parity error status and clear.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_error</name>
<description>No parity error occurs.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_error</name>
<description>A parity error of the received data occurs.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>fe</name>
<description>Frame error status and clear.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_error</name>
<description>No frame error is detected.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_error</name>
<description>An error occurs at the stop bit of the received data.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART_FR</name>
<description>UART_FR is the UART flag register.</description>
<addressOffset>0x018</addressOffset>
<size>16</size>
<resetValue>0x0197</resetValue>
<fields>
<field>
<name>txfe</name>
<description>TX FIFO empty status.</description>
<access>read-only</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_empty</name>
<description>When UART_LCR_H[fen] is set to 0:The TX holding register is not empty.When UART_LCR_H[fen] is set to 1:The TX FIFO is not empty.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>empty</name>
<description>When UART_LCR_H[fen] is set to 0:The TX holding register is empty.When UART_LCR_H[fen] is set to 1:The TX FIFO is empty.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxff</name>
<description>RX FIFO full status.</description>
<access>read-only</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_full</name>
<description>When UART_LCR_H[fen] is set to 0:The RX holding register is not full.When UART_LCR_H[fen] is set to 1:The RX FIFO is not full.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>full</name>
<description>When UART_LCR_H[fen] is set to 0:The RX holding register is full.When UART_LCR_H[fen] is set to 1:The RX FIFO is full.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>txff</name>
<description>TX FIFO full status.</description>
<access>read-only</access>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_full</name>
<description>When UART_LCR_H[fen] is set to 0:The TX holding register is not full.When UART_LCR_H[fen] is set to 1:The TX FIFO is not full.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>full</name>
<description>When UART_LCR_H[fen] is set to 0:The TX holding register is full.When UART_LCR_H[fen] is set to 1:The TX FIFO is not full.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxfe</name>
<description>RX FIFO empty status.</description>
<access>read-only</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_empty</name>
<description>When UART_LCR_H[fen] is set to 0:The RX holding register is not empty.When UART_LCR_H[fen] is set to 1:The RX FIFO is not empty.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>empty</name>
<description>When UART_LCR_H[fen] is set to 0:RX holding register empty.When UART_LCR_H[fen] is set to 1:The RX FIFO is empty.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>busy</name>
<description>UART busy/idle state.</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>idle_or_complete</name>
<description>The UART is idle or data transmission is complete.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>busy</name>
<description>The UART is busy transmitting data.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART_IBRD</name>
<description>UART_IBRD is the integral baud rate register.</description>
<addressOffset>0x024</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>bauddivint</name>
<description>Frequency divider value for the integral part of the baud rate.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>UART_FBRD</name>
<description>UART_FBRD is the fractional baud rate register.</description>
<addressOffset>0x028</addressOffset>
<size>8</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>banddivfrac</name>
<description>Frequency divider value for the fractional part of the baud rate.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<resetMask>0x00</resetMask>
</field>
</fields>
</register>
<register>
<name>UART_LCR_H</name>
<description>UART_LCR_H is the transfer mode control register.</description>
<addressOffset>0x02C</addressOffset>
<size>16</size>
<resetValue>0x00</resetValue>
<fields>
<field>
<name>sps</name>
<description>Parity bit enable.</description>
<access>read-write</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x00</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>Stick Parity disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>When [pen] and [eps] are set to 1, the parity bit is transmitted and checked as 0. When [pen] is set to 1 and [eps] is set to 0, the parity bit is transmitted and checked as 1.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>wlen</name>
<description>Number of data bits in a frame to be sent or received.</description>
<access>read-write</access>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<resetMask>0x00</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>len_5</name>
<description>5 bits.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>len_6</name>
<description>6 bits.</description>
<value>0x01</value>
</enumeratedValue>
<enumeratedValue>
<name>len_7</name>
<description>7 bits.</description>
<value>0x02</value>
</enumeratedValue>
<enumeratedValue>
<name>len_8</name>
<description>8 bits.</description>
<value>0x03</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>fen</name>
<description>TX/RX FIFO enable.</description>
<access>read-write</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x00</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>stp2</name>
<description>Whether a 2-bit stop bit exists at the end of a transmitted frame.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x00</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no</name>
<description>No 2-bit stop bit exists.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>yes</name>
<description>A 2-bit stop bit exists.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>eps</name>
<description>Parity bit select during data transmission and reception.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x00</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>odd</name>
<description>odd parity generation and checking.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>even</name>
<description>even parity generation and checking.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>pen</name>
<description>Parity check select.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x00</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>The parity check is disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>The parity bit is generated at the TX end and checked at the RX end.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>brk</name>
<description>TX break select.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x00</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>brk</name>
<description>After the current data transmission is complete, the UTXD outputs low level continuously.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART_CR</name>
<description>UART_CR is the UART control register..</description>
<addressOffset>0x030</addressOffset>
<size>16</size>
<resetValue>0x0300</resetValue>
<fields>
<field>
<name>ctsen</name>
<description>CTS hardware flow control enable.</description>
<access>read-write</access>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x00</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rtsen</name>
<description>RTS hardware flow control enable.</description>
<access>read-write</access>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rts</name>
<description>Request transmission setting.</description>
<access>read-write</access>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>unchanged</name>
<description>The output signal remains unchanged.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>zero</name>
<description>The output signal is 0.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>dtr</name>
<description>Data transmission preparation setting.</description>
<access>read-write</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>unchanged</name>
<description>The output signal remains unchanged.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>zero</name>
<description>The output signal is 0.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxe</name>
<description>UART RX enable.</description>
<access>read-write</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>txe</name>
<description>UART TX enable.</description>
<access>read-write</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>lbe</name>
<description>Loopback enable.</description>
<access>read-write</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>The UARTTXD output is looped back to UARTRXD.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>uarten</name>
<description>UART enable.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART_IFLS</name>
<description>UART_IFLS is the interrupt FIFO threshold select register.</description>
<addressOffset>0x034</addressOffset>
<size>16</size>
<resetValue>0x0092</resetValue>
<fields>
<field>
<name>rtsflsel</name>
<description>Hardware flow control rts_n trigger condition.</description>
<access>read-write</access>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x2</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>cond_1d8</name>
<description>RX FIFO ≥ 1/8 full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_1d4</name>
<description>RX FIFO ≥ 1/4 full.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_1d2</name>
<description>RX FIFO ≥ 1/2 full.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_3d4</name>
<description>RX FIFO ≥ 3/4 full.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_7d8</name>
<description>RX FIFO ≥ 7/8 full.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxiflsel</name>
<description>RX interrupt FIFO threshold.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x2</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>cond_1d8</name>
<description>RX FIFO ≥ 1/8 full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_1d4</name>
<description>RX FIFO ≥ 1/4 full.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_1d2</name>
<description>RX FIFO ≥ 1/2 full.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_3d4</name>
<description>RX FIFO ≥ 3/4 full.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_7d8</name>
<description>RX FIFO ≥ 7/8 full.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>txiflsel</name>
<description>TX interrupt FIFO threshold.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<resetMask>0x2</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>cond_1d8</name>
<description>RX FIFO ≥ 1/8 full.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_1d4</name>
<description>RX FIFO ≥ 1/4 full.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_1d2</name>
<description>RX FIFO ≥ 1/2 full.</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_3d4</name>
<description>RX FIFO ≥ 3/4 full.</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>cond_7d8</name>
<description>RX FIFO ≥ 7/8 full.</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART_IMSC</name>
<description>INT_MASK is the interrupt mask register.</description>
<addressOffset>0x038</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>oeim</name>
<description>Overflow error interrupt mask.</description>
<access>read-write</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>beim</name>
<description>Break error interrupt mask.</description>
<access>read-write</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>peim</name>
<description>Check interrupt mask.</description>
<access>read-write</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>feim</name>
<description>Break error interrupt mask.</description>
<access>read-write</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rtim</name>
<description>RX timeout interrupt mask.</description>
<access>read-write</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>txim</name>
<description>TX interrupt mask.</description>
<access>read-write</access>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxim</name>
<description>RX interrupt mask.</description>
<access>read-write</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART_RIS</name>
<description>UART_RIS is the raw interrupt state register.</description>
<addressOffset>0x03C</addressOffset>
<size>16</size>
<resetValue>0x000F</resetValue>
<fields>
<field>
<name>oeris</name>
<description>Raw overflow error interrupt state.</description>
<access>read-only</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>beris</name>
<description>Raw break error interrupt state.</description>
<access>read-only</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>peris</name>
<description>Raw parity interrupt state.</description>
<access>read-only</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>feris</name>
<description>Raw error interrupt state.</description>
<access>read-only</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rtris</name>
<description>Raw RX timeout interrupt state.</description>
<access>read-only</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>txris</name>
<description>Raw TX interrupt state.</description>
<access>read-only</access>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxris</name>
<description>Raw RX interrupt state.</description>
<access>read-only</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART_MIS</name>
<description>UART_MIS is the masked interrupt status register.</description>
<addressOffset>0x040</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>oemis</name>
<description>Masked overflow error interrupt state.</description>
<access>read-only</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>bemis</name>
<description>Masked break error interrupt state.</description>
<access>read-only</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>pemis</name>
<description>Masked parity interrupt state.</description>
<access>read-only</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>femis</name>
<description>Masked error interrupt state.</description>
<access>read-only</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rtmis</name>
<description>Masked RX timeout interrupt state.</description>
<access>read-only</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>txmis</name>
<description>Masked TX interrupt state.</description>
<access>read-only</access>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxmis</name>
<description>Masked RX interrupt state.</description>
<access>read-only</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>no_interrupt</name>
<description>No interrupt is generated.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>has_interrupt</name>
<description>An interrupt is generated.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART_ICR</name>
<description>UART_ICR is the interrupt clear register.</description>
<addressOffset>0x044</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>oeic</name>
<description>Overflow error interrupt clear.</description>
<access>write-only</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>beic</name>
<description>Break error interrupt clear.</description>
<access>write-only</access>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>peic</name>
<description>Parity interrupt clear.</description>
<access>write-only</access>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>feic</name>
<description>Error interrupt clear.</description>
<access>write-only</access>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rtic</name>
<description>RX timeout interrupt clear.</description>
<access>write-only</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>txic</name>
<description>TX interrupt clear.</description>
<access>write-only</access>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rxic</name>
<description>RX interrupt clear.</description>
<access>write-only</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>UART_DMACR</name>
<description>UART_DMACR is the DMA control register.</description>
<addressOffset>0x048</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>dmaonerr</name>
<description>DMA enable control for the RX channel when the UART error interrupt (UARTEINTR) occurs.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>valid</name>
<description>The request output (UARTRXDMASREQ or UARRTXDMABREQ) is valid.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>invalid</name>
<description>The request output (UARTRXDMASREQ or UARRTXDMABREQ) is invalid.</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>txdmae</name>
<description>TX FIFO DMA enable.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RX FIFO DMA enable</name>
<description>TX FIFO DMA enable.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled</description>
<value>0x1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- UART0 -->
<!-- UART1 -->
<peripheral derivedFrom="UART0">
<name>UART1</name>
<description>Inter-Integrated Circuit Bus 1</description>
<baseAddress>0x40009000</baseAddress>
<interrupt>
<name>UART1</name>
<description>UART1 interrupt</description>
<value>39</value>
</interrupt>
</peripheral>
<!-- UART1 -->
<!-- UART2 -->
<peripheral derivedFrom="UART0">
<name>UART2</name>
<description>Inter-Integrated Circuit Bus 2</description>
<baseAddress>0x4000A000</baseAddress>
<interrupt>
<name>UART2</name>
<description>UART2 interrupt</description>
<value>40</value>
</interrupt>
</peripheral>
<!-- UART2 -->
<peripheral>
<name>WDT</name>
<description>Watchdog timer</description>
<baseAddress>0x40000000</baseAddress>
<registers>
<register>
<name>cr</name>
<description>WDT control register</description>
<addressOffset>0x00</addressOffset>
<access>read-write</access>
<resetValue>0x00000008</resetValue>
<fields>
<!-- [31:6]: reserved, 0x0000000 -->
<!-- <field>
<name>cr_bit5</name>
<description>Meaningless</description>
<bitRange>[5:5]</bitRange>
</field> -->
<!-- [4:2]: reserved, 0x2 -->
<field>
<name>rmod</name>
<description>Reset mode select</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>reset</name>
<description>A system reset is generated upon each WDT timeout.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>interrupt</name>
<description>When the first timerout occurs, the WDT generates an interrupt. If the interrupt is not cleared until the second timeout, a system reset is generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>en</name>
<description>WDT enable</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>torr</name>
<description>Timerout period register</description>
<addressOffset>0x04</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<!-- [31:4]: reserved, 0x0000000 -->
<field>
<name>top</name>
<description>WDT interval (in clock cycles)</description>
<bitRange>[3:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>ccvr</name>
<description>Current WDT value register</description>
<addressOffset>0x08</addressOffset>
<access>read-only</access>
</register>
<register>
<name>crr</name>
<description>Counter restart register</description>
<addressOffset>0x0C</addressOffset>
<access>write-only</access>
</register>
<register>
<name>stat</name>
<description>Interrupt state register</description>
<addressOffset>0x10</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>isr</name>
<description>Masked interrupt status</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>eoi</name>
<description>Interrupt clear register</description>
<addressOffset>0x14</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>eoi</name>
<description>Interrupt clear. The interrupt is cleared by reading this register.</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- W_CTL -->
<peripheral>
<name>W_CTL</name>
<description>W_CTL/TSensor is the analog temperature detection IP, that is, a digital temperature sensor IP with 8-bit parallel outputs.</description>
<baseAddress>0x40028000</baseAddress>
<interrupt>
<name>TSensor</name>
<description>T-Sensor interrupt interrupt</description>
<value>46</value>
</interrupt>
<registers>
<register>
<name>RF_TEMP_MODE</name>
<description>RF_TEMP_MODE is the RF TEMP mode configuration register.</description>
<addressOffset>0x0490</addressOffset>
<size>32</size>
<resetValue>0xFF44</resetValue>
<fields>
<field>
<name>rf_over_temp_prt_hw_src</name>
<description>Hardware report source select.</description>
<access>read-write</access>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>rf_tsensor</name>
<description>TSensor inside the RF module reports temperature protection alarm.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>tsensor</name>
<description>TSensor reports the temperature protection alarm.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rf_over_temp_prt_polar</name>
<description>Polarity of the overtemperature protection signal.</description>
<access>read-write</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>zero_valid</name>
<description>Logic signal 0 means over temperature signal is valid, 1 is invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>one_valid</name>
<description>Logic signal 1 means over temperature signal is valid, 0 is invalid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rf_over_temp_prt_sel</name>
<description>Overtemperature protection signal select.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>hardware</name>
<description>hardware control.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>manual</name>
<description>manual control.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rf_over_temp_prt_man</name>
<description>Overtemperature protection manual control signal.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>valid</name>
<description>valid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>invalid</name>
<description>invalid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RF_TEMP_STS</name>
<description>RF_TEMP_STS is the RF TEMP overtemperature status register.</description>
<addressOffset>0x04B4</addressOffset>
<size>16</size>
<resetValue>0x000E</resetValue>
<fields>
<field>
<name>tsensor_overtemp_prt</name>
<description>TSensor overtemperature protection control.</description>
<access>read-only</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>working</name>
<description>normal working mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>rf_over_temp_prt</name>
<description>Overtemperature protection control signal.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x1</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>working</name>
<description>normal working mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RF_OVER_TEMP_INT_EN</name>
<description>RF_OVER_TEMP_INT_EN is the RF TEMP overtemperature interrupt enable register.</description>
<addressOffset>0x04C0</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>rf_over_temp_int_en</name>
<description>Overtemperature interrupt enable.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<!-- ??? -->
<register>
<name>RF_OVER_TEMP_INT_CLR</name>
<description>RF_OVER_TEMP_INT_CLR is the RF TEMP overtemperature interrupt clear register.</description>
<addressOffset>0x04C4</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>rf_over_temp_int_clr</name>
<description>RF overtemperature protection interrupt clear signal.</description>
<access>write-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>interrupt cleared.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RF_OVER_TEMP_INT_STS</name>
<description>RF_OVER_TEMP_INT_STS is the RF TEMP overtemperature interrupt register.</description>
<addressOffset>0x04C8</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>rf_over_temp_int</name>
<description>RF overtemperature protection interrupt status.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>invalid.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TSENSOR_START</name>
<description>TSENSOR_START is the TSensor start register.</description>
<addressOffset>0x0500</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>tsensor_start</name>
<description>Temperature code update in automatic mode.</description>
<access>write-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>start</name>
<description>If TSENSOR_AUTO_STS[tsensor_data_auto] is 1, the temperature is valid.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TSENSOR_CTRL</name>
<description>TSENSOR_CTRL is the TSensor control register.</description>
<addressOffset>0x0504</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>gate_tsensor_vddio_polar</name>
<description>TSensor power gating polarity.</description>
<access>read-write</access>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>one_enable</name>
<description>The TSensor IP is enabled at 1 and disabled at 0.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>zero_enable</name>
<description>The TSensor IP is enabled at 0 and disabled at 1.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_mode</name>
<description>TSensor temperature reporting mode.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>mode_16_avg_single</name>
<description>16-sample averaging single reporting mode.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>mode_16_avg_cyclic</name>
<description>16-sample averaging cyclic reporting mode.</description>
<value>0x01</value>
</enumeratedValue>
<enumeratedValue>
<name>mode_one_cyclic</name>
<description>Single-sample cyclic reporting mode.</description>
<value>0x02</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_enable</name>
<description>TSENSOR_CTRL switch.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TSENSOR_MAN_STS</name>
<description>TSENSOR_MAN_STS is the TSensor manual control status register.</description>
<addressOffset>0x0508</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>tsensor_data_man</name>
<description>A valid temperature code word of a single point is reported cyclically.</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x00</resetMask>
</field>
<field>
<name>tsensor_rdy_man</name>
<description>Temperature valid signal in single-point cyclic report mode.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_ready</name>
<description>The detection is not started or is being performed manually.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>ready</name>
<description>The value of [tsensor_data_man] is valid.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_man_clr</name>
<description>Clears the status of the single-point cyclic report mode.</description>
<access>write-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TSENSOR_AUTO_STS</name>
<description>TSENSOR_AUTO_STS is the TSensor automatic control status register.</description>
<addressOffset>0x050C</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>tsensor_data_auto</name>
<description>Valid temperature code word in 16-sample averaging single reporting mode or 16-sample averaging cyclic reporting mode.</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x00</resetMask>
</field>
<field>
<name>tsensor_rdy_auto</name>
<description>Temperature valid signal in 16-sample averaging single reporting mode or 16-sample averaging cyclic reporting mode.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>not_ready</name>
<description>The automatic detection is not started or is in progress.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>ready</name>
<description>The value of [tsensor_data_man] is valid.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_auto_clr</name>
<description>Clears the status of the 16-sample averaging single reporting mode or the 16-sample averaging cyclic reporting mode.</description>
<access>write-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TSENSOR_CTRL1</name>
<description>TSENSOR_CTRL1 is the TSensor control register 1.</description>
<addressOffset>0x0510</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>tsensor_temp_trim_sel</name>
<description>TSensor IP Trim adjustment function source select.</description>
<access>read-write</access>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x00</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>by_efuse</name>
<description>The temp_trim of the TSensor IP is directly loaded by the eFUSE.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>by_register</name>
<description>The temp_trim of the TSensor IP is selected.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_temp_trim</name>
<description>Trim value for calibrating the TSensor IP temperature.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<resetMask>0x00</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>trim_p0p000</name>
<description>0.000°C.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_p1p410</name>
<description>1.410℃.</description>
<value>0x01</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_p2p820</name>
<description>2.820℃.</description>
<value>0x02</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_p4p230</name>
<description>4.230℃.</description>
<value>0x03</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_p5p640</name>
<description>5.640℃.</description>
<value>0x04</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_p7p050</name>
<description>7.050℃.</description>
<value>0x05</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_p8p460</name>
<description>8.460℃.</description>
<value>0x06</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_p9p970</name>
<description>9.870℃.</description>
<value>0x07</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_n0p000</name>
<description>0.000℃.</description>
<value>0x08</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_n1p410</name>
<description>–1.410℃.</description>
<value>0x09</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_n2p820</name>
<description>–2.820℃.</description>
<value>0x0A</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_n4p230</name>
<description>–4.230℃.</description>
<value>0x0B</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_n5p640</name>
<description>–5.640℃.</description>
<value>0x0C</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_n7p050</name>
<description>–7.050℃.</description>
<value>0x0D</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_n8p460</name>
<description>–8.460℃.</description>
<value>0x0E</value>
</enumeratedValue>
<enumeratedValue>
<name>trim_n9p870</name>
<description>–9.870°C.</description>
<value>0x0F</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TSENSOR_TEMP_LIMIT1</name>
<description>TSENSOR_TEMP_LIMIT1 is the TSensor temperature upper threshold register.</description>
<addressOffset>0x0514</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>tsensor_temp_high_limit</name>
<description>High temperature threshold in 16-sample averaging single reporting mode or the 16-sample averaging cyclic reporting mode.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>TSENSOR_TEMP_LIMIT2</name>
<description>TSENSOR_TEMP_LIMIT2 is the TSensor temperature lower threshold register.</description>
<addressOffset>0x0518</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>tsensor_temp_low_limit</name>
<description>Low temperature threshold in 16-sample averaging single reporting mode or16-sample averaging cyclic reporting mode.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0x0</resetMask>
</field>
</fields>
</register>
<register>
<name>TSENSOR_OVER_TEMP</name>
<description>TSENSOR_OVER_TEMP is the TSensor overtemperature control register.</description>
<addressOffset>0x051C</addressOffset>
<size>16</size>
<resetValue>0x00FF</resetValue>
<fields>
<field>
<name>tsensor_overtemp_thresh_en</name>
<description>Overtemperature PA protection enable in 16-sample averaging single reporting mode or 16-sample averaging cyclic reporting mode.</description>
<access>read-write</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_overtemp_thresh</name>
<description>Overtemperature PA protection threshold in 16-sample averaging single reporting mode or 16-sample averaging cyclic reporting mode.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0xFF</resetMask>
</field>
</fields>
</register>
<register>
<name>TSENSOR_TEMP_INT_EN</name>
<description>TSENSOR_TEMP_INT_EN is the TSensor interrupt enable register.</description>
<addressOffset>0x0520</addressOffset>
<size>16</size>
<resetValue>0x00FF</resetValue>
<fields>
<field>
<name>tsensor_overtemp_int_en</name>
<description>TSensor overtemperature interrupt enable.</description>
<access>read-write</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_out_thresh_int_en</name>
<description>TSensor temperature threshold exceeding interrupt enable.</description>
<access>read-write</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_done_int_en</name>
<description>TSensor temperature measurement completion interrupt enable.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TSENSOR_TEMP_INT_CLR</name>
<description>TSENSOR_TEMP_INT_CLR is the RF TEMP configuration register.</description>
<addressOffset>0x0524</addressOffset>
<size>16</size>
<resetValue>0x00FF</resetValue>
<fields>
<field>
<name>tsensor_int_clr</name>
<description>TSensor interrupt clear.</description>
<access>write-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>clear</name>
<description>cleared.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TSENSOR_TEMP_INT_STS</name>
<description>TSENSOR_TEMP_INT_STS is the RF TEMP configuration register.</description>
<addressOffset>0x0528</addressOffset>
<size>16</size>
<resetValue>0x00FF</resetValue>
<fields>
<field>
<name>tsensor_overtemp_int_sts</name>
<description>TSensor overtemperature interrupt status.</description>
<access>read-only</access>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>invalid.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>valid.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_out_thresh_int_sts</name>
<description>TSensor temperature threshold exceeding interrupt status.</description>
<access>read-only</access>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>invalid.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>valid.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_done_int_sts</name>
<description>TSensor temperature measurement completion interrupt status.</description>
<access>read-only</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>invalid</name>
<description>invalid.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>valid</name>
<description>valid.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TSENSOR_OVER_TEMP_PD</name>
<description>TSENSOR_OVER_TEMP_PD is the TSensor overtemperature power-off control register.</description>
<addressOffset>0x0530</addressOffset>
<size>16</size>
<resetValue>0x00FF</resetValue>
<fields>
<field>
<name>tsensor_overtemp_pd_en</name>
<description>Overtemperature power-off protection enable in 16-sample averaging single reporting mode or 16-sample averaging cyclic reporting mode.</description>
<access>read-write</access>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>tsensor_overtemp_pd_thresh</name>
<description>Overtemperature power-off protection threshold in 16-sample averaging single reporting mode or 16-sample averaging cyclic reporting mode.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<resetMask>0xFF</resetMask>
</field>
</fields>
</register>
<register>
<name>TSENSOR_AUTO_REFRESH_PERIOD</name>
<description>TSENSOR_AUTO_REFRESH_PERIOD is the TSensor automatic detection period configuration register.</description>
<addressOffset>0x0540</addressOffset>
<size>16</size>
<resetValue>0xFFFF</resetValue>
<fields>
<field>
<name>tsensor_auto_refresh_period</name>
<description>TSensor automatic detection period (number of 32 kHz clock cycles).</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<resetMask>0xFFFF</resetMask>
</field>
</fields>
</register>
<register>
<name>TSENSOR_AUTO_REFRESH_CFG</name>
<description>TSENSOR_AUTO_REFRESH_CFG is the TSensor automatic detection enable control register.</description>
<addressOffset>0x0544</addressOffset>
<size>16</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>tsensor_auto_refresh_enable</name>
<description>Periodic detection enable in 16-sample averaging cyclic reporting mode.</description>
<access>read-write</access>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<resetMask>0x0</resetMask>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>disabled.</description>
<value>0x00</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>enabled.</description>
<value>0x01</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<!-- W_CTL -->
</peripherals>
</device>
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