Updates for HiSilicon L3C PMU driver
Yicong Yang (7):
drivers/perf: hisi: Relax the event ID check in the framework
drivers/perf: hisi: Export hisi_uncore_pmu_isr()
drivers/perf: hisi: Simplify the probe process of each L3C PMU version
drivers/perf: hisi: Extract the event filter check of L3C PMU
drivers/perf: hisi: Extend the field of tt_core
drivers/perf: hisi: Refactor the event configuration of L3C PMU
drivers/perf: hisi: Add support for L3C PMU v3
1/Event ID is only using the attr::config bit [7, 0] but we check the
event range using the whole 64bit field. It blocks the usage of the
resident field of attr::config. Relax the check by only using the
bit [7, 0].
2/Currently Uncore PMU framework assume one PMU device only have one
interrupt and will help register the interrupt handler. It cannot
support a PMU with multiple interrupt resources. However the interrupt
handling for the Uncore PMU maybe the same and could share the same
interrupt handler. Export hisi_uncore_pmu_isr() to allow drivers
register the irq handler by their own routine.
3/Version 1 and 2 of L3C PMU also use different HID. Make use of
struct acpi_device_id::driver_data for version specific information
rather than judge the version register. This will help to
simplify the probe process and also a bit easier for extension.
4/L3C PMU has 4 filter options which are sharing perf_event_attr::config1.
Driver will check config1 to see whether a certain event has a filter
setting. It'll be incorrect if we make use of other bits in config1
for non-filter options. So check whether each filter options are set
directly in a separate function instead.
5/Currently the tt_core's using config1's bit [7, 0] and can not be
extended. For some platforms there's more the 8 CPUs sharing the
L3 cache. So make tt_core use config2's bit [15, 0] and the remaining
bits in config2 is reserved for extension.
6/The event register is configured using hisi_pmu::base directly
since only one address space is supported for L3C PMU. It'll
be hard to extend if events configuration locates in different
address space. In order to make preparation for such hardware,
extract the event register configuration to separate function
using hw_perf_event::event_base as each event's base address.
Implement a private hisi_uncore_ops::get_event_idx() callback
for initialize the event_base besides get the hardware index.
7/This patch adds support for L3C PMU v3. The v3 L3C PMU supports
an extended events space which can be controlled in a second
address space with a separate overflow interrupt. The offset
of the control/event registers keep the same. The extended events
with original ones together cover the monitoring of all the L3C
transactions.