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Added new firmware support to enable RAS (Reliability, Availability, and Serviceability) functionality.
Secure Partition Manager (SPM): A Secure Partition is a software execution environment instantiated in S-EL0 that can be used to implement simple management and security services. The SPM is the firmware component that is responsible for managing a Secure Partition.
SDEI dispatcher: Support for interrupt-based SDEI events and all interfaces as defined by the SDEI specification v1.0, see SDEI Specification
Exception Handling Framework (EHF): Framework that allows dispatching of EL3 interrupts to their registered handlers which are registered based on their priorities. Facilitates firmware-first error handling policy where asynchronous exceptions may be routed to EL3.
Integrated the TSPD with EHF.
Updated PSCI support:
Implemented PSCI v1.1 optional features MEM_PROTECT and SYSTEM_RESET2. The supported PSCI version was updated to v1.1.
Improved PSCI STAT timestamp collection, including moving accounting for retention states to be inside the locks and fixing handling of wrap-around when calculating residency in AArch32 execution state.
Added optional handler for early suspend that executes when suspending to a power-down state and with data caches enabled.
This may provide a performance improvement on platforms where it is safe to perform some or all of the platform actions from pwr_domain_suspend with the data caches enabled.
Enabled build option, BL2_AT_EL3, for BL2 to allow execution at EL3 without any dependency on TF BL1.
This allows platforms which already have a non-TF Boot ROM to directly load and execute BL2 and subsequent BL stages without need for BL1. This was not previously possible because BL2 executes at S-EL1 and cannot jump straight to EL3.
Implemented support for SMCCC v1.1, including SMCCC_VERSION and SMCCC_ARCH_FEATURES.
Additionally, added support for SMCCC_VERSION in PSCI features to enable discovery of the SMCCC version via PSCI feature call.
Added Dynamic Configuration framework which enables each of the boot loader stages to be dynamically configured at runtime if required by the platform. The boot loader stage may optionally specify a firmware configuration file and/or hardware configuration file that can then be shared with the next boot loader stage.
Introduced a new BL handover interface that essentially allows passing of 4 arguments between the different BL stages.
Updated cert_create and fip_tool to support the dynamic configuration files. The COT also updated to support these new files.
Code hygiene changes and alignment with MISRA guideline:
Added support for Armv8.2-A architectural features:
extensions.
In addition to the v8.4 architectural extension, AMU support on Cortex-A75 was implemented.
Enhanced OP-TEE support to enable use of pageable OP-TEE image. The Arm standard platforms are updated to load up to 3 images for OP-TEE; header, pager image and paged image.
The chain of trust is extended to support the additional images.
Enhancements to the translation table library:
Updated GIC support:
Introduce new APIs for GICv2 and GICv3 that provide the capability to specify interrupt properties rather than list of interrupt numbers alone. The Arm platforms and other upstream platforms are migrated to use interrupt properties.
Added helpers to save / restore the GICv3 context, specifically the Distributor and Redistributor contexts and architectural parts of the ITS power management. The Distributor and Redistributor helpers also support the implementation-defined part of GIC-500 and GIC-600.
Updated the Arm FVP platform to save / restore the GICv3 context on system suspend / resume as an example of how to use the helpers.
Introduced a new TZC secured DDR carve-out for use by Arm platforms for storing EL3 runtime data such as the GICv3 register context.
Added support for Armv7-A architecture via build option ARM_ARCH_MAJOR=7. This includes following features:
Enhancements to Firmware Update feature:
Enhancements to Trusted Board Boot feature:
Added support for secure interrupt handling in AArch32 sp_min, hardcoded to only handle FIQs.
Added support to allow a platform to load images from multiple boot sources, for example from a second flash drive.
Added a logging framework that allows platforms to reduce the logging level at runtime and additionally the prefix string can be defined by the platform.
Further improvements to register initialisation:
Enhanced support for Arm platforms:
Introduced driver for Shared-Data-Structure (SDS) framework which is used for communication between SCP and the AP CPU, replacing Boot-Over_MHU (BOM) protocol.
The Juno platform is migrated to use SDS with the SCMI support added in v1.3 and is set as default.
The driver can be found in the plat/arm/css/drivers folder.
Improved memory usage by only mapping TSP memory region when the TSPD has been included in the build. This reduces the memory footprint and avoids unnecessary memory being mapped.
Updated support for multi-threading CPUs for FVP platforms - always check the MT field in MPDIR and access the bit fields accordingly.
Support building for platforms that model DynamIQ configuration by implementing all CPUs in a single cluster.
Improved nor flash driver, for instance clearing status registers before sending commands. Driver can be found plat/arm/board/common folder.
Enhancements to QEMU platform:
Applied workarounds CVE-2017-5715 on Arm Cortex-A57, -A72, -A73 and -A75, and for Armv7-A CPUs Cortex-A9, -A15 and -A17.
Applied errata workaround for Arm Cortex-A57: 859972.
Applied errata workaround for Arm Cortex-A72: 859971.
Added support for Poplar 96Board platform.
Added support for Raspberry Pi 3 platform.
Added Call Frame Information (CFI) assembler directives to the vector entries which enables debuggers to display the backtrace of functions that triggered a synchronous abort.
Added ability to build dtb.
Added support for pre-tool (cert_create and fiptool) image processing enabling compression of the image files before processing by cert_create and fiptool.
This can reduce fip size and may also speed up loading of images. The image verification will also get faster because certificates are generated based on compressed images.
Imported zlib 1.2.11 to implement gunzip() for data compression.
Enhancements to fiptool:
Enabled support for platforms with hardware assisted coherency.
A new build option HW_ASSISTED_COHERENCY allows platforms to take advantage of the following optimisations:
Added support for Cortex-A75 and Cortex-A55 processors.
Both Cortex-A75 and Cortex-A55 processors use the Arm DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, reducing complexity of the software operations.
Introduced Arm GIC-600 driver.
Arm GIC-600 IP complies with Arm GICv3 architecture. For FVP platforms, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600.
Updated GICv3 support:
Introduced power management APIs for GICv3 Redistributor. These APIs allow platforms to power down the Redistributor during CPU power on/off. Requires the GICv3 implementations to have power management operations.
Implemented the power management APIs for FVP.
GIC driver data is flushed by the primary CPU so that secondary CPU do not read stale GIC data.
Added support for Arm System Control and Management Interface v1.0 (SCMI).
The SCMI driver implements the power domain management and system power management protocol of the SCMI specification (Arm DEN 0056ASCMI) for communicating with any compliant power controller.
Support is added for the Juno platform. The driver can be found in the plat/arm/css/drivers folder.
Added support to enable pre-integration of TBB with the Arm TrustZone CryptoCell product, to take advantage of its hardware Root of Trust and crypto acceleration services.
Enabled Statistical Profiling Extensions for lower ELs.
The firmware support is limited to the use of SPE in the Non-secure state and accesses to the SPE specific registers from S-EL1 will trap to EL3.
The SPE are architecturally specified for AArch64 only.
Code hygiene changes aligned with MISRA guidelines:
Enhancements to Firmware Update feature:
Introduced support for Arm Compiler 6 and LLVM (clang).
TF-A can now also be built with the Arm Compiler 6 or the clang compilers. The assembler and linker must be provided by the GNU toolchain.
Tested with Arm CC 6.7 and clang 3.9.x and 4.0.x.
Memory footprint improvements:
Introduced tf_snprintf, a reduced version of snprintf which has support for a limited set of formats.
The mbedtls driver is updated to optionally use tf_snprintf instead of snprintf.
The assert() is updated to no longer print the function name, and additional logging options are supported via an optional platform define PLAT_LOG_LEVEL_ASSERT, which controls how verbose the assert output is.
Enhancements to TF-A support when running in AArch32 execution state:
Introduced Arm SiP service for use by Arm standard platforms.
Added new Arm SiP Service SMCs to enable the Non-secure world to read PMF timestamps.
Added PMF instrumentation points in TF-A in order to quantify the overall time spent in the PSCI software implementation.
Added new Arm SiP service SMC to switch execution state.
This allows the lower exception level to change its execution state from AArch64 to AArch32, or vice verse, via a request to EL3.
Migrated to use SPDX[0] license identifiers to make software license auditing simpler.
NOTE: Files that have been imported by FreeBSD have not been modified.
[0]: https://spdx.org/
Enhancements to the translation table library:
Added version 2 of translation table library that allows different translation tables to be modified by using different 'contexts'. Version 1 of the translation table library only allows the current EL's translation tables to be modified.
Version 2 of the translation table also added support for dynamic regions; regions that can be added and removed dynamically whilst the MMU is enabled. Static regions can only be added or removed before the MMU is enabled.
The dynamic mapping functionality is enabled or disabled when compiling by setting the build option PLAT_XLAT_TABLES_DYNAMIC to 1 or 0. This can be done per-image.
Added support for translation regimes with two virtual address spaces such as the one shared by EL1 and EL0.
The library does not support initializing translation tables for EL0 software.
Added support to mark the translation tables as non-cacheable using an additional build option XLAT_TABLE_NC.
Added support for GCC stack protection. A new build option ENABLE_STACK_PROTECTOR was introduced that enables compilation of all BL images with one of the GCC -fstack-protector-* options.
A new platform function plat_get_stack_protector_canary() was introduced that returns a value used to initialize the canary for stack corruption detection. For increased effectiveness of protection platforms must provide an implementation that returns a random value.
Enhanced support for Arm platforms:
Added support for multi-threading CPUs, indicated by MT field in MPDIR. A new build flag ARM_PLAT_MT is added, and when enabled, the functions accessing MPIDR assume that the MT bit is set for the platform and access the bit fields accordingly.
Also, a new API plat_arm_get_cpu_pe_count is added when ARM_PLAT_MT is enabled, returning the Processing Element count within the physical CPU corresponding to mpidr.
The Arm platforms migrated to use version 2 of the translation tables.
Introduced a new Arm platform layer API plat_arm_psci_override_pm_ops which allows Arm platforms to modify plat_arm_psci_pm_ops and therefore dynamically define PSCI capability.
The Arm platforms migrated to use IMAGE_LOAD_V2 by default.
Enhanced reporting of errata workaround status with the following policy:
Added build options ARM_ARCH_MAJOR and ARM_ARM_MINOR to choose the architecture version to target TF-A.
Updated the spin lock implementation to use the more efficient CAS (Compare And Swap) instruction when available. This instruction was introduced in Armv8.1-A.
Applied errata workaround for Arm Cortex-A53: 855873.
Applied errata workaround for Arm-Cortex-A57: 813419.
Enabled all A53 and A57 errata workarounds for Juno, both in AArch64 and AArch32 execution states.
Added support for Socionext UniPhier SoC platform.
Added support for Hikey960 and Hikey platforms.
Added support for Rockchip RK3328 platform.
Added support for NVidia Tegra T186 platform.
Added support for Designware emmc driver.
Imported libfdt v1.4.2 that addresses buffer overflow in fdt_offset_ptr().
Enhanced the CPU operations framework to allow power handlers to be registered on per-level basis. This enables support for future CPUs that have multiple threads which might need powering down individually.
Updated register initialisation to prevent unexpected behaviour:
Enhanced PSCI support:
Simplified fiptool to have a single linked list of image descriptors.
For the TSP, resolved corruption of pre-empted secure context by aborting any pre-empted SMC during PSCI power management requests.
Added support for running TF-A in AArch32 execution state.
The PSCI library has been refactored to allow integration with EL3 Runtime Software. This is software that is executing at the highest secure privilege which is EL3 in AArch64 or Secure SVC/Monitor mode in AArch32. See PSCI Integration Guide.
Included is a minimal AArch32 Secure Payload, SP-MIN, that illustrates the usage and integration of the PSCI library with EL3 Runtime Software running in AArch32 state.
Booting to the BL1/BL2 images as well as booting straight to the Secure Payload is supported.
Improvements to the initialization framework for the PSCI service and Arm Standard Services in general.
The PSCI service is now initialized as part of Arm Standard Service initialization. This consolidates the initializations of any Arm Standard Service that may be added in the future.
A new function get_arm_std_svc_args() is introduced to get arguments
corresponding to each standard service and must be implemented by the EL3
Runtime Software.
For PSCI, a new versioned structure psci_lib_args_t is introduced to
initialize the PSCI Library. Note this is a compatibility break due to
the change in the prototype of psci_setup().
To support AArch32 builds of BL1 and BL2, implemented a new, alternative firmware image loading mechanism that adds flexibility.
The current mechanism has a hard-coded set of images and execution order (BL31, BL32, etc). The new mechanism is data-driven by a list of image descriptors provided by the platform code.
Arm platforms have been updated to support the new loading mechanism.
The new mechanism is enabled by a build flag (LOAD_IMAGE_V2) which is
currently off by default for the AArch64 build.
Note TRUSTED_BOARD_BOOT is currently not supported when
LOAD_IMAGE_V2 is enabled.
Updated requirements for making contributions to TF-A.
Commits now must have a 'Signed-off-by:' field to certify that the contribution has been made under the terms of the Developer Certificate of Origin.
A signed CLA is no longer required.
The Contribution Guide has been updated to reflect this change.
Introduced Performance Measurement Framework (PMF) which provides support for capturing, storing, dumping and retrieving time-stamps to measure the execution time of critical paths in the firmware. This relies on defining fixed sample points at key places in the code.
To support the QEMU platform port, imported libfdt v1.4.1 from https://git.kernel.org/cgit/utils/dtc/dtc.git
Updated PSCI support:
pwr_domain_pwr_down_wfi(), in
plat_psci_ops to enable platforms to perform platform-specific actions
needed to enter powerdown, including the 'wfi' invocation.Enhancements to the translation table library:
Limited memory mapping support for region overlaps to only allow regions to overlap that are identity mapped or have the same virtual to physical address offset, and overlap completely but must not cover the same area.
This limitation will enable future enhancements without having to support complex edge cases that may not be necessary.
The initial translation lookup level is now inferred from the virtual address space size. Previously, it was hard-coded.
Added support for mapping Normal, Inner Non-cacheable, Outer Non-cacheable memory in the translation table library.
This can be useful to map a non-cacheable memory region, such as a DMA buffer.
Introduced the MT_EXECUTE/MT_EXECUTE_NEVER memory mapping attributes to specify the access permissions for instruction execution of a memory region.
Enabled support to isolate code and read-only data on separate memory pages, allowing independent access control to be applied to each.
Enabled SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and BL31 common architectural setup code, preventing fetching instructions from non-secure memory when in secure state.
Enhancements to FIP support:
fip_create with fiptool which provides a more consistent
and intuitive interface as well as additional support to remove an image
from a FIP file.Refactored the TZC-400 driver to also support memory controllers that integrate TZC functionality, for example Arm CoreLink DMC-500. Also added DMC-500 specific support.
Implemented generic delay timer based on the system generic counter and migrated all platforms to use it.
Enhanced support for Arm platforms:
Applied following erratum workarounds for Cortex-A57: 833471, 826977, 829520, 828024 and 826974.
Added support for Mediatek MT6795 platform.
Added support for QEMU virtualization Armv8-A target.
Added support for Rockchip RK3368 and RK3399 platforms.
Added support for Xilinx Zynq UltraScale+ MPSoC platform.
Added support for Arm Cortex-A73 MPCore Processor.
Added support for Arm Cortex-A72 processor.
Added support for Arm Cortex-A35 processor.
Added support for Arm Cortex-A32 MPCore Processor.
Enabled preloaded BL33 alternative boot flow, in which BL2 does not load BL33 from non-volatile storage and BL31 hands execution over to a preloaded BL33. The User Guide has been updated with an example of how to use this option with a bootwrapped kernel.
Added support to build TF-A on a Windows-based host machine.
Updated Trusted Board Boot prototype implementation:
ROTPK_NOT_DEPLOYED bit is set.Updated GICv3 support:
SYSTEM_OFF API. This issue will be fixed in a future version of
the model.-O0) fails.The Trusted Board Boot implementation on Arm platforms now conforms to the mandatory requirements of the TBBR specification.
In particular, the boot process is now guarded by a Trusted Watchdog, which will reset the system in case of an authentication or loading error. On Arm platforms, a secure instance of Arm SP805 is used as the Trusted Watchdog.
Also, a firmware update process has been implemented. It enables authenticated firmware to update firmware images from external interfaces to SoC Non-Volatile memories. This feature functions even when the current firmware in the system is corrupt or missing; it therefore may be used as a recovery mode.
Improvements have been made to the Certificate Generation Tool
(cert_create) as follows.
Extended the FIP tool (fip_create) to support the new set of images
involved in the Firmware Update process.
Various memory footprint improvements. In particular:
Added the following new design documents:
Applied the new image terminology to the code base and documentation, as described on the TF-A wiki on GitHub.
The build system has been reworked to improve readability and facilitate adding future extensions.
On Arm standard platforms, BL31 uses the boot console during cold boot but switches to the runtime console for any later logs at runtime. The TSP uses the runtime console for all output.
Implemented a basic NOR flash driver for Arm platforms. It programs the device using CFI (Common Flash Interface) standard commands.
Implemented support for booting EL3 payloads on Arm platforms, which reduces the complexity of developing EL3 baremetal code by doing essential baremetal initialization.
Provided separate drivers for GICv3 and GICv2. These expect the entire software stack to use either GICv2 or GICv3; hybrid GIC software systems are no longer supported and the legacy Arm GIC driver has been deprecated.
Added support for Juno r1 and r2. A single set of Juno TF-A binaries can run on Juno r0, r1 and r2 boards. Note that this TF-A version depends on a Linaro release that does not contain Juno r2 support.
Added support for MediaTek mt8173 platform.
Implemented a generic driver for Arm CCN IP.
Major rework of the PSCI implementation.
Added support for the SYSTEM_SUSPEND PSCI API on Arm platforms. When invoked on the last running core on a supported platform, this puts the system into a low power mode with memory retention.
Unified the reset handling code as much as possible across BL stages. Also introduced some build options to enable optimization of the reset path on platforms that support it.
Added a simple delay timer API, as well as an SP804 timer driver, which is enabled on FVP.
Added support for NVidia Tegra T210 and T132 SoCs.
Reorganised Arm platforms ports to greatly improve code shareability and facilitate the reuse of some of this code by other platforms.
Added support for Arm Cortex-A72 processor in the CPU specific framework.
Provided better error handling. Platform ports can now define their own error handling, for example to perform platform specific bookkeeping or post-error actions.
Implemented a unified driver for Arm Cache Coherent Interconnects used for both CCI-400 & CCI-500 IPs. Arm platforms ports have been migrated to this common driver. The standalone CCI-400 driver has been deprecated.
ARM_ROTPK_LOCATION build option.SYSTEM_OFF API. This issue will be fixed in a future version of
the model.-O0) fails.A prototype implementation of Trusted Board Boot has been added. Boot
loader images are verified by BL1 and BL2 during the cold boot path. BL1 and
BL2 use the PolarSSL SSL library to verify certificates and images. The
OpenSSL library is used to create the X.509 certificates. Support has been
added to fip_create tool to package the certificates in a FIP.
Support for calling CPU and platform specific reset handlers upon entry into
BL3-1 during the cold and warm boot paths has been added. This happens after
another Boot ROM reset_handler() has already run. This enables a developer
to perform additional actions or undo actions already performed during the
first call of the reset handlers e.g. apply additional errata workarounds.
Support has been added to demonstrate routing of IRQs to EL3 instead of S-EL1 when execution is in secure world.
The PSCI implementation now conforms to version 1.0 of the PSCI
specification. All the mandatory APIs and selected optional APIs are
supported. In particular, support for the PSCI_FEATURES API has been
added. A capability variable is constructed during initialization by
examining the plat_pm_ops and spd_pm_ops exported by the platform and
the Secure Payload Dispatcher. This is used by the PSCI FEATURES function
to determine which PSCI APIs are supported by the platform.
Improvements have been made to the PSCI code as follows.
CPU_SUSPEND, CPU_ON and
CPU_OFF calls to facilitate an early return to the caller in case a
failure condition is detected. For example, a PSCI CPU_SUSPEND call
returns SUCCESS to the caller if a pending interrupt is detected early
in the code path.power_state and
entrypoint parameters early in PSCI CPU_ON and CPU_SUSPEND code
paths.MIGRATE call, the SPD hook to migrate
the Trusted OS is invoked.It is now possible to build TF-A without marking at least an extra page of
memory as coherent. The build flag USE_COHERENT_MEM can be used to
choose between the two implementations. This has been made possible through
these changes.
Approximately, 4K worth of memory is saved for each boot loader stage when
USE_COHERENT_MEM=0. Enabling this option increases the latencies
associated with acquire and release of locks. It also requires changes to
the platform ports.
It is now possible to specify the name of the FIP at build time by defining
the FIP_NAME variable.
Issues with depedencies on the 'fiptool' makefile target have been
rectified. The fip_create tool is now rebuilt whenever its source files
change.
The BL3-1 runtime console is now also used as the crash console. The crash console is changed to SoC UART0 (UART2) from the previous FPGA UART0 (UART0) on Juno. In FVP, it is changed from UART0 to UART1.
CPU errata workarounds are applied only when the revision and part number match. This behaviour has been made consistent across the debug and release builds. The debug build additionally prints a warning if a mismatch is detected.
It is now possible to issue cache maintenance operations by set/way for a particular level of data cache. Levels 1-3 are currently supported.
The following improvements have been made to the FVP port.
FVP_SHARED_DATA_LOCATION which allowed relocation of
shared data into the Trusted DRAM has been deprecated. Shared data is
now always located at the base of Trusted SRAM.FVP_TSP_RAM_LOCATION to the value dram.Separate transation tables are created for each boot loader image. The
IMAGE_BLx build options are used to do this. This allows each stage to
create mappings only for areas in the memory map that it needs.
A Secure Payload Dispatcher (OPTEED) for the OP-TEE Trusted OS has been added. Details of using it with TF-A can be found in OP-TEE Dispatcher
CPU_SUSPEND calls that target a standby state are now supported.plat_match_rotpk() function. This prevents the correct establishment of
the Chain of Trust at the first step in the Trusted Board Boot process.SYSTEM_OFF API. This issue will be fixed in a future version of
the model.early_exception vectors from BL3-1 (2KB code size
saving).psci_suspend_context array, saving 2KB.aff_map_node array, saving 1.5KB in the
FVP port.tf_printf() function, allowing the stack to be
greatly reduced.cpu_context structure
so that registers that do not change during normal execution are
re-initialized each time during cold/warm boot, rather than restored
from memory. This saves about 1.2KB.entry_point_info. BL3-1 fully
determines the exception level to use for the non-trusted firmware (BL3-3)
based on the SPSR value provided by the BL2 platform code (or otherwise
provided to BL3-1). This allows platform code to directly run non-trusted
firmware payloads at either EL2 or EL1 without requiring an EL2 stub or OS
loader.fvp_config into a common platform header.io_init()
and moved all the IO storage framework code to one place.SYSTEM_OFF and SYSTEM_RESET APIs.GICv3 support is experimental. The Linux kernel patches to support this are not widely available. There are known issues with GICv3 initialization in the TF-A.
While this version greatly reduces the on-chip RAM requirements, there are further RAM usage enhancements that could be made.
The firmware design documentation for the Test Secure-EL1 Payload (TSP) and its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
The Juno-specific firmware design documentation is incomplete.
Some recent enhancements to the FVP port have not yet been translated into the Juno port. These will be tracked via the tf-issues project.
The Linux kernel version referred to in the user guide has DVFS and HMP support disabled due to some known instabilities at the time of this release. A future kernel version will re-enable these features.
DS-5 v5.19 does not detect Version 5.8 of the Cortex-A57-A53 Base FVPs in
CADI server mode. This is because the <SimName> reported by the FVP in
this version has changed. For example, for the Cortex-A57x4-A53x4 Base FVP,
the <SimName> reported by the FVP is FVP_Base_Cortex_A57x4_A53x4, while
DS-5 expects it to be FVP_Base_A57x4_A53x4.
The temporary fix to this problem is to change the name of the FVP in
sw/debugger/configdb/Boards/ARM FVP/Base_A57x4_A53x4/cadi_config.xml.
Change the following line:
<SimName>System Generator:FVP_Base_A57x4_A53x4</SimName>
to System Generator:FVP_Base_Cortex-A57x4_A53x4
A similar change can be made to the other Cortex-A57-A53 Base FVP variants.
dump target (build now always produces dump files).fip target optional.vpath
keyword.-ffunction-sections, -fdata-sections and
--gc-sections compiler/linker options to remove unused code and data
from the images. Previously, all common functions were being built into
all binary images, whether or not they were actually used.-C bp.secure_memory=1 is now supported.-C bp.secure_memory=1 in the Base
FVPs (see New features).Support for Foundation FVP Version 2.0 added. The documented UEFI configuration disables some devices that are unavailable in the Foundation FVP, including MMC and CLCD. The resultant UEFI binary can be used on the AEMv8 and Cortex-A57-A53 Base FVPs, as well as the Foundation FVP.
NOTE: The software will not work on Version 1.0 of the Foundation FVP.
Enabled third party contributions. Added a new contributing.md containing instructions for how to contribute and updated copyright text in all files to acknowledge contributors.
The PSCI CPU_SUSPEND API has been stabilised to the extent where it can be used for entry into power down states with the following restrictions:
The PSCI AFFINITY_INFO api has undergone limited testing on the Base FVPs to allow experimental use.
Required C library and runtime header files are now included locally in TF-A instead of depending on the toolchain standard include paths. The local implementation has been cleaned up and reduced in scope.
Added I/O abstraction framework, primarily to allow generic code to load images in a platform-independent way. The existing image loading code has been reworked to use the new framework. Semi-hosting and NOR flash I/O drivers are provided.
Introduced Firmware Image Package (FIP) handling code and tools. A FIP combines multiple firmware images with a Table of Contents (ToC) into a single binary image. The new FIP driver is another type of I/O driver. The Makefile builds a FIP by default and the FVP platform code expect to load a FIP from NOR flash, although some support for image loading using semi- hosting is retained.
NOTE: Building a FIP by default is a non-backwards-compatible change.
NOTE: Generic BL2 code now loads a BL3-3 (non-trusted firmware) image into DRAM instead of expecting this to be pre-loaded at known location. This is also a non-backwards-compatible change.
NOTE: Some non-trusted firmware (e.g. UEFI) will need to be rebuilt so that it knows the new location to execute from and no longer needs to copy particular code modules to DRAM itself.
Reworked BL2 to BL3-1 handover interface. A new composite structure (bl31_args) holds the superset of information that needs to be passed from BL2 to BL3-1, including information on how handover execution control to BL3-2 (if present) and BL3-3 (non-trusted firmware).
Added library support for CPU context management, allowing the saving and restoring of
Added a framework for implementing EL3 runtime services. Reworked the PSCI implementation to be one such runtime service.
Reworked the exception handling logic, making use of both SP_EL0 and SP_EL3 stack pointers for determining the type of exception, managing general purpose and system register context on exception entry/exit, and handling SMCs. SMCs are directed to the correct EL3 runtime service.
Added support for a Test Secure-EL1 Payload (TSP) and a corresponding Dispatcher (TSPD), which is loaded as an EL3 runtime service. The TSPD implements Secure Monitor functionality such as world switching and EL1 context management, and is responsible for communication with the TSP. NOTE: The TSPD does not yet contain support for secure world interrupts. NOTE: The TSP/TSPD is not built by default.
AFFINITY_INFO & PSCI_VERSION have now been tested (to
a limited extent)../build directory and
sub-directories instead of being placed in the root of the project.The following is a list of issues which are expected to be fixed in the future releases of TF-A.
-C bp.secure_memory=1 is not supported.The following is a list of issues which are expected to be fixed in the future releases of TF-A.
-C bp.secure_memory=1 is not supported.CPU_SUSPEND is present, it is not yet stable
and ready for use.AFFINITY_INFO & PSCI_VERSION are implemented but have
not been tested.init from the RAM-disk. As an alternative,
the VirtioBlock mechanism can be used to provide a file-system to the
kernel.Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
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