RISC-V: KVM: add vector CSRs · Pull Request !5696 · anolis/cloud-kernel

bugzilla: https://bugzilla.openanolis.cn/show_bug.cgi?id=24331

如下备注已合入的patch是在当前devel-6.6分支上已经合入的patch，本PR只合入了对应patchset中没有合入的patch。

https://lore.kernel.org/r/20230912072510.2510-1-jszhang@kernel.org
riscv: mm: update T-Head memory type definitions

https://lore.kernel.org/all/tencent_E19FA1A095768063102E654C6FC858A32F06@qq.com/
riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly

https://lore.kernel.org/r/20231130111704.1319081-1-cleger@rivosinc.com
RISC-V: Implement archrandom when Zkr is available

https://lore.kernel.org/all/20231206110807.35882-3-ajones@ventanamicro.com/
riscv: sbi: Introduce system suspend support

https://lore.kernel.org/all/20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com
[PATCH 1/5] riscv: dts: renesas: r9a07g043f: Add L2 cache node 已合入
[PATCH 2/5] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
[PATCH 3/5] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled
[PATCH 4/5] riscv: dts: renesas: rzfive-smarc: Drop dma properties from SSI1 node
[PATCH 5/5] riscv: configs: defconfig: Enable configs required for RZ/Five SoC

https://lore.kernel.org/all/20240118062930.245937-1-sunilvl@ventanamicro.com/
[PATCH v3 -next 1/3] cpuidle: RISC-V: Move few functions to arch/riscv
[PATCH v3 -next 2/3] ACPI: RISC-V: Add LPI driver
[PATCH v3 -next 3/3] ACPI: Enable ACPI_PROCESSOR for RISC-V 已合入

RISC-V: KVM: Fix indentation in kvm_riscv_vcpu_set_reg_csr()

https://lore.kernel.org/all/20240229121056.203419-1-alexghiti@rivosinc.com/
[PATCH v3 1/2] riscv: Remove superfluous smp_mb()
[PATCH v3 2/2] riscv: Fix text patching when IPI are used 已合入

https://lore.kernel.org/all/20230919080929.3807123-1-xu.yang_2@nxp.com/
perf jevents: fix no member named 'entries' issue

https://lore.kernel.org/all/20231205174509.2238870-1-dbarboza@ventanamicro.com/
[PATCH v3 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context()
[PATCH v3 2/3] RISC-V: KVM: add 'vlenb' Vector CSR Daniel Henrique Barboza
[PATCH v3 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST

https://lore.kernel.org/all/20240130061730.21118-1-yangtiezhu@loongson.cn/
[PATCH v6 1/8] objtool/LoongArch: Enable objtool to be built 已合入
[PATCH v6 2/8] objtool/LoongArch: Implement instruction decoder 已合入
[PATCH v6 3/8] objtool/x86: Separate arch-specific and generic parts
[PATCH v6 4/8] objtool/LoongArch: Enable orc to be built 已合入
[PATCH v6 5/8] objtool: Check local label in add_dead_ends() 已合入
[PATCH v6 6/8] objtool: Check local label in read_unwind_hints()已合入
[PATCH v6 7/8] LoongArch: Add ORC stack unwinder support 已合入
[PATCH v6 8/8] LoongArch: Add kernel livepatching support已合入

https://lore.kernel.org/all/20231123185821.2272504-1-christoph.muellner@vrull.eu/
tools: selftests: riscv: Fix compile warnings in cbo

https://lore.kernel.org/all/20240117130933.57514-2-ajones@ventanamicro.com/
RISC-V: selftests: cbo: Ensure asm operands match constraints

https://lore.kernel.org/all/20240322134728.151255-2-ajones@ventanamicro.com/
RISC-V: selftests: cbo: Ensure asm operands match constraints, take 2

https://lore.kernel.org/all/20241103145153.105097-1-alexghiti@rivosinc.com/
[PATCH v6 01/13] riscv: Move cpufeature.h macros into their own header 已合入
[PATCH v6 02/13] riscv: Do not fail to build on byte/halfword operations with Zawrs 已合入
[PATCH v6 03/13] riscv: Implement cmpxchg32/64() using Zacas 已合入
[PATCH v6 04/13] dt-bindings: riscv: Add Zabha ISA extension description 已合入
[PATCH v6 05/13] riscv: Implement cmpxchg8/16() using Zabha 已合入
[PATCH v6 06/13] riscv: Improve zacas fully-ordered cmpxchg() 已合入
[PATCH v6 07/13] riscv: Implement arch_cmpxchg128() using Zacas 已合入
[PATCH v6 08/13] riscv: Implement xchg8/16() using Zabha 已合入
[PATCH v6 09/13] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock 已合入
[PATCH v6 10/13] asm-generic: ticket-lock: Add separate ticket-lock.h 已合入
[PATCH v6 11/13] riscv: Add ISA extension parsing for Ziccrse 已合入
[PATCH v6 12/13] dt-bindings: riscv: Add Ziccrse ISA extension description
[PATCH v6 13/13] riscv: Add qspinlock support 已合入

启动命令：
qemu-system-riscv64 -nographic -cpu rv64,v=true,zk=true,zvksh=true,zvkned=true -smp 8
-M virt,pflash0=pflash0,pflash1=pflash1,aia=aplic-imsic,acpi=on,aia-guests=2 -m 4G
-serial mon:stdio
-blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd
-blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd
-kernel Image
-initrd rootfs.cpio
-append "rdinit=/sbin/init ro console=ttyS0 rootwait earlycon=uart8250"

Saving 256 bits of non-creditable seed for next boot
Starting syslogd: OK
Starting acpid: OK
Starting klogd: OK
Running sysctl: OK
Starting network: Waiting for interface eth0 to appear............... timeout!
run-parts: /etc/network/if-pre-up.d/wait_iface: exit status 1
FAIL
Starting crond: OK

Welcome to Buildroot
buildroot login: root

1,zkr实现archrandom测试
#time dd if=/dev/random of=/dev/null bs=10240 count=10240
10240+0 records in
10240+0 records out
real 0m 5.89s
user 0m 0.04s
sys 0m 5.84s
#time dd if=/dev/urandom of=/dev/null bs=10240 count=10240
10240+0 records in
10240+0 records out
real 0m 6.08s
user 0m 0.02s
sys 0m 6.03s
2，system suspend 测试
#echo mem > /sys/power/state
[ 28.543867] PM: suspend entry (s2idle)
[ 28.551020] Filesystems sync: 0.001 seconds
[ 28.626324] Freezing user space processes
[ 28.633969] Freezing user space processes completed (elapsed 0.007 seconds)
[ 28.634932] OOM killer disabled.
[ 28.635316] Freezing remaining freezable tasks
[ 28.637843] Freezing remaining freezable tasks completed (elapsed 0.002 seconds)
[ 28.638577] printk: Suspending console(s) (use no_console_suspend to debug)
3，cbo selftest测试
#./cbo
TAP version 13
1..3
ok 1 Zicboz block size
#Zicboz block size: 64
ok 2 cbo.zero
ok 3 cbo.zero check
#Totals: pass:3 fail:0 xfail:0 xpass:0 skip:0 error:0
#./hwprobe
TAP version 13
1..5
ok 1 NULL CPU set
ok 2 Bad CPU set
ok 3 NULL CPU set with non-zero size
ok 4 Existing key is maintained
ok 5 Unknown key overwritten with -1 and doesn't block other elements
#Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0

类型	指派人员	状态
审查	Guanjun xunlei 半叶枫尘 Artie Ding winterddd maqiao-alibaba Guixin Liu health_jay kun-llfl Xuchun Shang fangyu0809	已完成 (0/0人)
测试	小龙已测试通过	已完成 (1/1人)

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