[devel-6.6] AMD's Venice Essential Patches for Anolis 6.6 kernel · Pull Request !6210 · anolis/cloud-kernel

bugzilla:https://bugzilla.openanolis.cn/show_bug.cgi?id=28102

**Support for AMD Venice Machines on Anolis 6.6 kernel**
x86/amd_nb: Clean up early_is_amd_nb()
x86: Start moving AMD node functionality out of AMD_NB
crypto: ccp - Add support for PCI device 0x17D8
x86/amd_nb: Add AMD Family MI300 PCI IDs
x86/amd_nb: Add new PCI IDs for AMD family 1Ah model 60h-70h
x86/amd_nb: Add new PCI ID for AMD family 1Ah model 20h
x86/amd_nb: Simplify function 4 search
x86/amd_nb: Simplify root device search
x86/cpu: Encapsulate topology information in cpuinfo_x86
x86/cpu: Move phys_proc_id into topology info
x86/cpu/amd: Provide a separate accessor for Node ID
x86/amd_nb: Use topology info to get AMD node count
x86/amd_nb: Simplify function 3 search
EDAC/amd64: Check return value of amd_smn_read()
EDAC/amd64: Remove unused register accesses
x86/amd_nb: Enhance SMN access error checking
x86/amd_nb: Move SMN access code to a new amd_node driver
x86/amd_node: Update __amd_smn_rw() error paths
x86/amd_node: Remove dependency on AMD_NB
x86/amd_node: Use defines for SMN register offsets
anolis: configs: classify CONFIG_AMD_NODE as L1 for x86 AMD64

This patch series includes 21 commits. The first 20 commits backports Venice essential upstream kernel patches to the OpenAnolis cloud kernel v6.6 devel branch, focusing on AMD Node / SMN infrastructure refactoring, topology cleanups, and platform enablement fixes.

The changes migrate SMN and AMD node functionality away from legacy AMD_NB, improve SMN error handling and robustness, modernize CPU topology accessors, and add required PCI IDs for newer AMD platforms.
All backports reference their corresponding upstream commits.

To avoid regressions, l **egacy Hygon Family 18h Model 04h–0Fh support  is explicitly preserved** , retaining PCI-based enumeration paths where upstream has transitioned to topology-driven discovery.

This PR also includes a small ACPI SRAT fix to correct Generic Initiator device handle validation.

**Impact** : Low risk. Mostly refactoring, correctness fixes, and enablement changes with no functional behavior change for existing supported platforms.
 **Compatibility** : Backward-compatible with existing OpenAnolis AMD and Hygon systems.

**Test & Verification** 
 **Test Environment**

Platform:  **AMD Venice**

Kernel:  **cloud-kernel v6.6 devel**

Validation scope:  **Functional verification of Venice essential backports**

**Configuration Verification** 
```
# grep -i CONFIG_AMD_NODE /boot/config-6.6.102_venice_essential+
CONFIG_AMD_NODE=y
```
 **Test Method** 
 **1. Baseline (Without Patches)** 
The system was booted with and without the Venice essential backport patches, and EDAC functionality was verified using module status and kernel logs.

**Test Results** 
```
$ grep -i edac /proc/modules
edac_mce_amd 45056 0 - Live 0x0000000000000000 (E)

$ lsmod | grep edac
edac_mce_amd           45056  0
```
```
$ dmesg | grep -i edac
EDAC MC: Ver: 3.0.0
EDAC amd64: Node 0: No DIMMs detected.
EDAC amd64: Node 1: No DIMMs detected.
(repeated for all nodes)
```
 **Observation:** 
amd64_edac is not loaded and memory controllers are not enumerated correctly on Venice systems.

**2. With Venice Essential Backports Applied** 
```
$ grep -i edac /proc/modules
amd64_edac 61440 0 - Live 0x0000000000000000 (E)
edac_mce_amd 45056 1 amd64_edac, Live 0x0000000000000000 (E)

$ lsmod | grep edac
amd64_edac             61440  0
edac_mce_amd           45056  1 amd64_edac
```

```
$ dmesg | grep -i edac
EDAC MC: Ver: 3.0.0
EDAC amd64: F1Ah_M50h detected (node 0)
EDAC MCx: UMCy chip selects detected
EDAC amd64: MC: <memory size reported correctly>
```
 **Observation:**

- `amd64_edac` is correctly loaded
- Venice platform (F1Ah_M50h) is detected
- UMC instances are enumerated
- Memory configuration is correctly reported

**Conclusion** 
The Venice essential backports restore correct EDAC initialization and memory controller detection on AMD Venice platforms.
No regressions were observed compared to the baseline kernel, and functional behavior matches upstream expectations.

**Disclaimer** 
This pull request  **does not include the complete set of patches required**  for the full Venice backport.

As per OpenAnolis contribution policy, backport work has been split across multiple pull requests, with each  **PR limited to a maximum of 25 patches**  for submission to the  **cloud-kernel v6.6 devel branch.**

The functional validation described above was performed  ** with all related Venice backport pull requests applied together.** 
To reproduce the same test results, ** all corresponding Venice backport PRs must be merged into the Anolis 6.6 devel branch.**

类型	指派人员	状态
审查	Tianjia Zhang 王鹏 xunlei 半叶枫尘 Artie Ding winterddd xueshuai alu maqiao-alibaba 冯光辉 Guixin Liu kun-llfl Xuchun Shang Xiaochen Shen yehuaisheng hygon-anolis-reviewers	已完成 (0/0人)
测试	小龙已测试通过	已完成 (1/1人)

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