[5.10] [Feature] anolis: dma: swiotlb: align SWIOTLB buffer to 2MB for TDX guest · Pull Request !6857 · anolis/cloud-kernel

bugzilla: https://bugzilla.openanolis.cn/show_bug.cgi?id=34088

Align SWIOTLB buffer to 2MB for TDX guest to optimize performance

In TDX (Intel Trust Domain Extensions) guest environments, all DMA operations must use shared (unencrypted) memory. The kernel uses SWIOTLB (Software I/O Translation Lookaside Buffer) as bounce buffers to facilitate DMA without modifying device drivers.Currently, the SWIOTLB buffer is allocated with PAGE_SIZE (4KB) alignment. However, this creates several performance and efficiency issues in TDX guests:

**Problems** 
IOMMU Page Table Overhead
The IOMMU must map SWIOTLB buffers using 4KB page table entries
For a typical 256MB SWIOTLB buffer, this requires 65,536 page table entries
Using 2MB pages would reduce this to just 128 entries (512x reduction)
High IOTLB (IOMMU TLB) miss rate during DMA operations
EPT (Extended Page Table) Large Page Splitting
When SWIOTLB buffer boundaries don't align with 2MB boundaries, the hypervisor must split existing 2MB EPT entries into 4KB entries
This causes:
EPT page table fragmentation
Additional EPT violations during split operations
Increased memory overhead for page tables
Performance degradation from more page table walks
TLB Efficiency
Both CPU TLB and IOTLB suffer from using small pages
More TLB entries consumed for SWIOTLB mappings
Higher TLB miss rate affecting DMA performance
 **Impact** 
In TDX guest environments with high I/O workloads:
Increased DMA latency due to IOMMU and EPT overhead
Higher memory consumption for page tables
Degraded overall I/O performance, especially for devices requiring frequent bounce buffer usage
Proposed Solution
Align SWIOTLB buffer allocation to 2MB (PMD size) boundaries when:
swiotlb=any parameter is specified
Buffer size is naturally 2MB aligned
Running in TDX guest environment (detected via X86_FEATURE_TDX_GUEST)
 **Benefits** 
IOMMU Optimization: 512x reduction in page table entries, improved IOTLB hit rate
Avoid EPT Splitting: Buffer boundaries align with large page boundaries, preventing hypervisor from splitting 2MB EPT entries
Better TLB Utilization: Both CPU and IOMMU TLBs benefit from large page mappings
Reduced Memory Overhead: Less memory consumed by page tables
 **Implementation** 
The optimization is x86-specific and only activates in TDX guests. Other architectures and platforms continue using PAGE_SIZE alignment.

类型	指派人员	状态
审查	xunlei 半叶枫尘 Artie Ding winterddd xueshuai 冯光辉 Guixin Liu kun-llfl Xuchun Shang XiangZao yixingrui	已完成 (0/0人)
测试	小龙已测试通过	已完成 (1/1人)

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