代码拉取完成，页面将自动刷新
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2022 Spacemit, Inc */
/dts-v1/;
#include <dt-bindings/mmc/k1x_sdhci.h>
#include <dt-bindings/usb/k1x_ci_usb.h>
#include <dt-bindings/reset/spacemit-k1x-reset.h>
#include <dt-bindings/clock/spacemit-k1x-clock.h>
#include <dt-bindings/display/spacemit-dpu.h>
#include <dt-bindings/pmu/k1x_pmu.h>
#include <dt-bindings/dma/k1x-dmac.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "spacemit,k1-x";
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
serial7 = &uart7;
serial8 = &uart8;
serial9 = &uart9;
serial10 = &r_uart0;
serial11 = &r_uart1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
mmc2 = &sdhci2;
ethernet0 = ð0;
ethernet1 = ð1;
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <10000000>;
cpu_0: cpu@0 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
model = "Spacemit(R) X60";
reg = <0>;
status = "okay";
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v",
"zicbom", "zicboz", "zicntr", "zicond",
"zicsr", "zifencei", "zihintpause", "zihpm",
"zfh", "zfhmin", "zba", "zbb", "zbc", "zbs",
"zkt", "zvfh", "zvfhmin", "zvkt", "sscofpmf",
"sstc", "svinval", "svnapot", "svpbmt" ;
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&clst0_l2_cache>;
mmu-type = "riscv,sv39";
// cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
#cooling-cells = <2>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu_1: cpu@1 {
device_type = "cpu";
reg = <1>;
status = "okay";
compatible = "spacemit,x60", "riscv";
model = "Spacemit(R) X60";
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v",
"zicbom", "zicboz", "zicntr", "zicond",
"zicsr", "zifencei", "zihintpause", "zihpm",
"zfh", "zfhmin", "zba", "zbb", "zbc", "zbs",
"zkt", "zvfh", "zvfhmin", "zvkt", "sscofpmf",
"sstc", "svinval", "svnapot", "svpbmt" ;
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&clst0_l2_cache>;
mmu-type = "riscv,sv39";
// cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
#cooling-cells = <2>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu_2: cpu@2 {
device_type = "cpu";
reg = <2>;
status = "okay";
compatible = "spacemit,x60", "riscv";
model = "Spacemit(R) X60";
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v",
"zicbom", "zicboz", "zicntr", "zicond",
"zicsr", "zifencei", "zihintpause", "zihpm",
"zfh", "zfhmin", "zba", "zbb", "zbc", "zbs",
"zkt", "zvfh", "zvfhmin", "zvkt", "sscofpmf",
"sstc", "svinval", "svnapot", "svpbmt" ;
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&clst0_l2_cache>;
mmu-type = "riscv,sv39";
// cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
#cooling-cells = <2>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu_3: cpu@3 {
device_type = "cpu";
reg = <3>;
status = "okay";
compatible = "spacemit,x60", "riscv";
model = "Spacemit(R) X60";
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v",
"zicbom", "zicboz", "zicntr", "zicond",
"zicsr", "zifencei", "zihintpause", "zihpm",
"zfh", "zfhmin", "zba", "zbb", "zbc", "zbs",
"zkt", "zvfh", "zvfhmin", "zvkt", "sscofpmf",
"sstc", "svinval", "svnapot", "svpbmt" ;
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&clst0_l2_cache>;
mmu-type = "riscv,sv39";
// cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
#cooling-cells = <2>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu_4: cpu@4 {
device_type = "cpu";
reg = <4>;
status = "okay";
compatible = "spacemit,x60", "riscv";
model = "Spacemit(R) X60";
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v",
"zicbom", "zicboz", "zicntr", "zicond",
"zicsr", "zifencei", "zihintpause", "zihpm",
"zfh", "zfhmin", "zba", "zbb", "zbc", "zbs",
"zkt", "zvfh", "zvfhmin", "zvkt", "sscofpmf",
"sstc", "svinval", "svnapot", "svpbmt" ;
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&clst1_l2_cache>;
mmu-type = "riscv,sv39";
// cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
#cooling-cells = <2>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu_5: cpu@5 {
device_type = "cpu";
reg = <5>;
status = "okay";
compatible = "spacemit,x60", "riscv";
model = "Spacemit(R) X60";
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v",
"zicbom", "zicboz", "zicntr", "zicond",
"zicsr", "zifencei", "zihintpause", "zihpm",
"zfh", "zfhmin", "zba", "zbb", "zbc", "zbs",
"zkt", "zvfh", "zvfhmin", "zvkt", "sscofpmf",
"sstc", "svinval", "svnapot", "svpbmt" ;
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&clst1_l2_cache>;
mmu-type = "riscv,sv39";
// cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
#cooling-cells = <2>;
cpu5_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu_6: cpu@6 {
device_type = "cpu";
reg = <6>;
status = "okay";
compatible = "spacemit,x60", "riscv";
model = "Spacemit(R) X60";
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v",
"zicbom", "zicboz", "zicntr", "zicond",
"zicsr", "zifencei", "zihintpause", "zihpm",
"zfh", "zfhmin", "zba", "zbb", "zbc", "zbs",
"zkt", "zvfh", "zvfhmin", "zvkt", "sscofpmf",
"sstc", "svinval", "svnapot", "svpbmt" ;
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&clst1_l2_cache>;
mmu-type = "riscv,sv39";
// cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
#cooling-cells = <2>;
cpu6_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu_7: cpu@7 {
device_type = "cpu";
reg = <7>;
status = "okay";
compatible = "spacemit,x60", "riscv";
model = "Spacemit(R) X60";
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v",
"zicbom", "zicboz", "zicntr", "zicond",
"zicsr", "zifencei", "zihintpause", "zihpm",
"zfh", "zfhmin", "zba", "zbb", "zbc", "zbs",
"zkt", "zvfh", "zvfhmin", "zvkt", "sscofpmf",
"sstc", "svinval", "svnapot", "svpbmt" ;
riscv,cbom-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&clst1_l2_cache>;
mmu-type = "riscv,sv39";
// cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */;
#cooling-cells = <2>;
cpu7_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
clst0_l2_cache: l2-cache0 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-size = <524288>;
cache-sets = <512>;
cache-unified;
};
clst1_l2_cache: l2-cache1 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-size = <524288>;
cache-sets = <512>;
cache-unified;
};
/*
idle-states {
CPU_NONRET: cpu-nonret {
compatible = "riscv,idle-state";
idle-state-name = "riscv,cpu-nonret";
riscv,sbi-suspend-param = <0x90000000>;
local-timer-stop;
entry-latency-us = <200>;
exit-latency-us = <500>;
min-residency-us = <950>;
};
CLUSTER_NONRET: cluster-nonret {
compatible = "riscv,idle-state";
idle-state-name = "riscv,cluster-nonret";
riscv,sbi-suspend-param = <0x91000000>;
local-timer-stop;
entry-latency-us = <600>;
exit-latency-us = <1100>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
TOP_NONRET: top-nonret {
compatible = "riscv,idle-state";
idle-state-name = "riscv,top-nonret";
riscv,sbi-suspend-param = <0x92000000>;
local-timer-stop;
entry-latency-us = <700>;
exit-latency-us = <1200>;
min-residency-us = <2800>;
wakeup-latency-us = <1600>;
};
};
*/
};
clocks {
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
vctcxo_24: clock-vctcxo_24 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "vctcxo_24";
};
vctcxo_3: clock-vctcxo_3 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <3000000>;
clock-output-names = "vctcxo_3";
};
vctcxo_1: clock-vctcxo_1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <1000000>;
clock-output-names = "vctcxo_1";
};
pll1_2457p6_vco: clock-pll1_2457p6_vco {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <2457600000>;
clock-output-names = "pll1_2457p6_vco";
};
clk_32k: clock-clk32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "clk_32k";
};
pll_clk_cluster0: clock-pll_clk_cluster0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <10000000>;
clock-output-names = "pll_clk_cluster0";
};
pll_clk_cluster1: clock-pll_clk_cluster1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <10000000>;
clock-output-names = "pll_clk_cluster1";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* rcpu's heap */
rcpu_mem_heap: rcpu_mem_heap@100000 {
reg = <0x0 0x100000 0x0 0x200000>;
da_base = <0x30000000>;
no-map;
};
/* vring0 */
vdev0vring0: vdev0vring0@300000 {
reg = <0x0 0x300000 0x0 0x3000>;
da_base = <0x30200000>;
no-map;
};
/* vring1 */
vdev0vring1: vdev0vring1@303000 {
reg = <0x0 0x303000 0x0 0x3000>;
da_base = <0x30203000>;
no-map;
};
/* share memory buffer */
vdev0buffer: vdev0buffer@306000 {
compatible = "shared-dma-pool";
reg = <0x0 0x306000 0x0 0xf6000>;
da_base = <0x30206000>;
no-map;
};
/* the resource table */
rsc_table: rsc_table@3fc000 {
reg = <0x0 0x3fc000 0x0 0x4000>;
da_base = <0x302fc000>;
no-map;
};
/* used for rcpu code & data & bss space */
rcpu_mem_0: rcpu_mem_0@400000 {
reg = <0x0 0x400000 0x0 0x200000>;
da_base = <0x30300000>;
no-map;
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
ranges;
/* dram mapping for usb/sdh for ex. */
dram_range0: dram_range@0 {
compatible = "spacemit-dram-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
#interconnect-cells = <0>;
status = "okay";
};
/* dram mapping for vpu/gpu/dpu for ex. */
dram_range1: dram_range@1 {
compatible = "spacemit-dram-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>;
#interconnect-cells = <0>;
status = "okay";
};
/* dram mapping for pcie0 for ex. */
dram_range2: dram_range@2 {
compatible = "spacemit-dram-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0x90000000 0x1 0x10000000 0x3 0x70000000>;
#interconnect-cells = <0>;
status = "okay";
};
/* dram mapping for v2d/isp/csi/vi/cpp for ex. */
dram_range3: dram_range@3 {
compatible = "spacemit-dram-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0x80000000 0x1 0x00000000 0x1 0x80000000>;
#interconnect-cells = <0>;
status = "okay";
};
/* dram mapping for dma&users for ex. */
dram_range4: dram_range@4 {
compatible = "spacemit-dram-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>;
#interconnect-cells = <0>;
status = "okay";
};
/* dram mapping for eth/crypto/jpu for ex. */
dram_range5: dram_range@5 {
compatible = "spacemit-dram-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>;
#interconnect-cells = <0>;
status = "okay";
};
/* dram mapping for pcie1 for ex. */
dram_range6: dram_range@6 {
compatible = "spacemit-dram-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0x80000000 0x1 0x00000000 0x0 0x10000000>,
<0x0 0xa0000000 0x1 0x20000000 0x3 0x60000000>;
#interconnect-cells = <0>;
status = "okay";
};
/* dram mapping for pcie2 for ex. */
dram_range7: dram_range@7 {
compatible = "spacemit-dram-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0x80000000 0x1 0x00000000 0x0 0x20000000>,
<0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
#interconnect-cells = <0>;
status = "okay";
};
/* for rcpu vqueue buffer . */
dram_range8: dram_range@8 {
compatible = "spacemit-dram-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0x0 0x30200000 0x0 0x300000 0x0 0xfc000>;
#interconnect-cells = <0>;
status = "okay";
};
clint0: clint@e4000000 {
compatible = "riscv,clint0";
interrupts-extended = <
&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7
&cpu2_intc 3 &cpu2_intc 7
&cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7
&cpu5_intc 3 &cpu5_intc 7
&cpu6_intc 3 &cpu6_intc 7
&cpu7_intc 3 &cpu7_intc 7
>;
reg = <0x0 0xE4000000 0x0 0x00010000>;
};
ccu: clock-controller@d4050000 {
compatible = "spacemit,k1x-clock";
reg = <0x0 0xd4050000 0x0 0x209c>,
<0x0 0xd4282800 0x0 0x400>,
<0x0 0xd4015000 0x0 0x1000>,
<0x0 0xd4090000 0x0 0x1000>,
<0x0 0xd4282c00 0x0 0x400>,
<0x0 0xd8440000 0x0 0x98>,
<0x0 0xc0000000 0x0 0x4280>,
<0x0 0xf0610000 0x0 0x20>,
<0x0 0xc0880000 0x0 0x2050>,
<0x0 0xc0888000 0x0 0x30>,
<0x0 0xc088c000 0x0 0x40>;
reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2", "rcpu", "rcpu2", "audpmu";
clocks = <&vctcxo_24>, <&vctcxo_3>, <&vctcxo_1>, <&pll1_2457p6_vco>,
<&clk_32k>;
clock-names = "vctcxo_24", "vctcxo_3", "vctcxo_1", "pll1_2457p6_vco",
"clk_32k";
#clock-cells = <1>;
status = "okay";
};
reset: reset-controller@d4050000 {
compatible = "spacemit,k1x-reset";
reg = <0x0 0xd4050000 0x0 0x209c>,
<0x0 0xd4282800 0x0 0x400>,
<0x0 0xd4015000 0x0 0x1000>,
<0x0 0xd4090000 0x0 0x1000>,
<0x0 0xd4282c00 0x0 0x400>,
<0x0 0xd8440000 0x0 0x98>,
<0x0 0xc0000000 0x0 0x4280>,
<0x0 0xf0610000 0x0 0x20>,
<0x0 0xc0880000 0x0 0x2050>,
<0x0 0xc0888000 0x0 0x30>;
reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2", "rcpu", "rcpu2";
#reset-cells = <1>;
status = "okay";
};
intc: interrupt-controller@e0000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <
&cpu0_intc 11 &cpu0_intc 9
&cpu1_intc 11 &cpu1_intc 9
&cpu2_intc 11 &cpu2_intc 9
&cpu3_intc 11 &cpu3_intc 9
&cpu4_intc 11 &cpu4_intc 9
&cpu5_intc 11 &cpu5_intc 9
&cpu6_intc 11 &cpu6_intc 9
&cpu7_intc 11 &cpu7_intc 9
>;
reg = <0x0 0xE0000000 0x0 0x04000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <159>;
};
pinctrl: pinctrl@d401e000 {
compatible = "pinconf-single-aib";
reg = <0x0 0xd401e000 0x0 0x27c>,
<0x0 0xd4019800 0x0 0x10>,
<0x0 0xd4019000 0x0 0x800>,
<0x0 0xd4282904 0x0 0x4>;
#address-cells = <1>;
#size-cells = <1>;
#pinctrl-cells = <2>;
#gpio-range-cells = <3>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xff77>;
clocks = <&ccu CLK_AIB>;
clock-names = "clk_aib";
resets = <&reset RESET_AIB>;
reset-names = "aib_rst";
interrupt-parent = <&intc>;
interrupts = <60>;
interrupt-controller;
#interrupt-cells = <1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
pmu: power-management@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
mpmu: mpmu@1 {
compatible = "simple-mfd", "spacemit,spacemit-mpmu", "syscon";
reg = <0x0 0xd4050000 0x0 0x3004>;
};
apmu: apmu@2 {
compatible = "simple-mfd", "spacemit,spacemit-apmu", "syscon";
reg = <0x0 0xd4282800 0x0 0x400>;
};
power: power-controller {
compatible = "spacemit,power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
domains = <0x9>;
power-domain@SPT_PD_BUS {
reg = <0x0>;
pm_qos = <0x7>;
#power-domain-cells = <0>;
};
power-domain@SPT_PD_VPU {
reg = <0x1>;
pm_qos = <12>;
reg_pwr_ctrl = <0xa8>;
bit_sleep2 = <3>;
bit_sleep1 = <2>;
bit_isolation = <1>;
bit_pwr_stat = <1>;
bit_hw_pwr_stat = <9>;
#power-domain-cells = <0>;
};
power-domain@SPT_PD_GPU {
reg = <0x2>;
pm_qos = <12>;
reg_pwr_ctrl = <0xd0>;
bit_sleep2 = <3>;
bit_sleep1 = <2>;
bit_isolation = <1>;
bit_pwr_stat = <0>;
#power-domain-cells = <0>;
};
power-domain@SPT_PD_LCD {
reg = <0x3>;
pm_qos = <12>;
reg_pwr_ctrl = <0x380>;
bit_hw_mode = <4>;
bit_sleep2 = <3>;
bit_sleep1 = <2>;
bit_isolation = <1>;
bit_auto_pwr_on = <0>;
bit_pwr_stat = <4>;
bit_hw_pwr_stat = <12>;
use_hw = <1>;
#power-domain-cells = <0>;
};
power-domain@SPT_PD_ISP {
reg = <0x4>;
pm_qos = <12>;
reg_pwr_ctrl = <0x37c>;
bit_hw_mode = <4>;
bit_sleep2 = <3>;
bit_sleep1 = <2>;
bit_isolation = <1>;
bit_auto_pwr_on = <0>;
bit_pwr_stat = <2>;
bit_hw_pwr_stat = <10>;
#power-domain-cells = <0>;
};
power-domain@SPT_PD_AUDIO {
reg = <0x5>;
pm_qos = <15>;
reg_pwr_ctrl = <0x378>;
bit_hw_mode = <4>;
bit_sleep2 = <3>;
bit_sleep1 = <2>;
bit_isolation = <1>;
bit_auto_pwr_on = <0>;
bit_pwr_stat = <3>;
bit_hw_pwr_stat = <11>;
use_hw = <1>;
#power-domain-cells = <0>;
};
power-domain@SPT_PD_GNSS {
reg = <0x6>;
pm_qos = <15>;
reg_pwr_ctrl = <0x13c>;
bit_hw_mode = <4>;
bit_sleep2 = <3>;
bit_sleep1 = <2>;
bit_isolation = <1>;
bit_auto_pwr_on = <0>;
bit_pwr_stat = <6>;
bit_hw_pwr_stat = <14>;
#power-domain-cells = <0>;
};
power-domain@SPT_PD_HDMI {
reg = <0x7>;
pm_qos = <12>;
reg_pwr_ctrl = <0x3f4>;
bit_hw_mode = <4>;
bit_sleep2 = <3>;
bit_sleep1 = <2>;
bit_isolation = <1>;
bit_auto_pwr_on = <0>;
bit_pwr_stat = <7>;
bit_hw_pwr_stat = <15>;
use_hw = <1>;
#power-domain-cells = <0>;
};
power-domain@SPT_PD_DUMMY {
reg = <0x8>;
pm_qos = <15>;
#power-domain-cells = <0>;
};
};
};
uart0: serial@d4017000 {
compatible = "spacemit,pxa-uart";
reg = <0x0 0xd4017000 0x0 0x100>;
interrupt-parent = <&intc>;
interrupts = <42>;
clocks = <&ccu CLK_UART1>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
clk-fpga = <14750000>;
resets = <&reset RESET_UART1>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
dmas = <&pdma0 DMA_UART0_RX 1
&pdma0 DMA_UART0_TX 1>;
dma-names = "rx", "tx";
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
reg-shift = <2>;
reg-io-width = <4>;
status = "ok";
};
uart1: uart@f0612000 {
compatible = "spacemit,pxa-uart";
reg = <0x0 0xf0612000 0x0 0x100>;
interrupt-parent = <&intc>;
interrupts = <43>;
clocks = <&ccu CLK_SEC_UART1>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
resets = <&reset RESET_SEC_UART1>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
uart2: uart@d4017100 {
compatible = "spacemit,pxa-uart";
reg = <0x0 0xd4017100 0x0 0x100>;
interrupt-parent = <&intc>;
interrupts = <44>;
clocks = <&ccu CLK_UART2>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
clk-fpga = <14750000>;
resets = <&reset RESET_UART2>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
uart3: uart@d4017200 {
compatible = "spacemit,pxa-uart";
reg = <0x0 0xd4017200 0x0 0x100>;
interrupt-parent = <&intc>;
interrupts = <45>;
clocks = <&ccu CLK_UART3>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
clk-fpga = <14750000>;
resets = <&reset RESET_UART3>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
uart4: uart@d4017300 {
compatible = "spacemit,pxa-uart";
interrupt-parent = <&intc>;
reg = <0x0 0xd4017300 0x0 0x100>;
interrupts = <46>;
clocks = <&ccu CLK_UART4>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
clk-fpga = <14750000>;
resets = <&reset RESET_UART4>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
uart5: uart@d4017400 {
compatible = "spacemit,pxa-uart";
interrupt-parent = <&intc>;
reg = <0x0 0xd4017400 0x0 0x100>;
interrupts = <47>;
clocks = <&ccu CLK_UART5>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
clk-fpga = <14750000>;
resets = <&reset RESET_UART5>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
uart6: uart@d4017500 {
compatible = "spacemit,pxa-uart";
interrupt-parent = <&intc>;
reg = <0x0 0xd4017500 0x0 0x100>;
interrupts = <48>;
clocks = <&ccu CLK_UART6>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
clk-fpga = <14750000>;
resets = <&reset RESET_UART6>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
uart7: uart@d4017600 {
compatible = "spacemit,pxa-uart";
interrupt-parent = <&intc>;
reg = <0x0 0xd4017600 0x0 0x100>;
interrupts = <49>;
clocks = <&ccu CLK_UART7>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
clk-fpga = <14750000>;
resets = <&reset RESET_UART7>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
uart8: uart@d4017700 {
compatible = "spacemit,pxa-uart";
interrupt-parent = <&intc>;
reg = <0x0 0xd4017700 0x0 0x100>;
interrupts = <50>;
clocks = <&ccu CLK_UART8>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
clk-fpga = <14750000>;
resets = <&reset RESET_UART8>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
uart9: uart@d4017800 {
compatible = "spacemit,pxa-uart";
interrupt-parent = <&intc>;
reg = <0x0 0xd4017800 0x0 0x100>;
interrupts = <51>;
clocks = <&ccu CLK_UART9>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
clk-fpga = <14750000>;
resets = <&reset RESET_UART9>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
r_uart0: r_uart0@c0881000 {
compatible = "spacemit,rcpu-pxa-uart0";
reg = <0x0 0xc0881000 0x0 0x100>;
clocks = <&ccu CLK_RCPU_UART0>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
resets = <&reset RESET_RCPU_UART0>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
rcpu-uart;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
r_uart1: r_uart1@c088d000 {
compatible = "spacemit,rcpu-pxa-uart1";
reg = <0x0 0xc088d000 0x0 0x100>;
clocks = <&ccu CLK_RCPU_UART1>, <&ccu CLK_SLOW_UART>;
clock-names = "func", "gate";
resets = <&reset RESET_RCPU_UART1>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
rcpu-uart;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
mailbox: mailbox@d4013400 {
compatible = "spacemit,k1-x-mailbox";
reg = <0x0 0xd4013400 0x0 0x100>;
interrupt-parent = <&intc>;
interrupts = <52>;
#mbox-cells = <1>;
clocks = <&ccu CLK_IPC_AP2AUD>;
clock-names = "core";
resets = <&reset RESET_IPC_AP2AUD>;
reset-names = "core_reset";
power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>;
status = "okay";
};
rcpu: rcpu_rproc@0 {
compatible = "spacemit,k1-x-rproc";
reg = <0 0xc088c000 0 0x1000>,
<0 0xc0880000 0 0x200>;
ddr-remap-base = <0x100000>;
esos-entry-point = <0x30300114>;
clocks = <&ccu CLK_AUDIO>, <&ccu CLK_AUDIO_APB>;
clock-names = "core", "apb";
apb-clk-rate = <122880000>;
resets = <&reset RESET_AUDIO_SYS>;
reset-names = "core_reset";
mboxes = <&mailbox 0>, <&mailbox 1>;
mbox-names = "vq0", "vq1";
firmware-name = "esos.elf";
power-domains = <&power K1X_PMU_AUD_PWR_DOMAIN>;
interconnects = <&dram_range8>;
interconnect-names = "dma-mem";
memory-region = <&rcpu_mem_0>, <&rcpu_mem_heap>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>;
status = "okay";
};
pdma0: pdma@d4000000 {
compatible = "spacemit,pdma-1.0";
reg = <0x0 0xd4000000 0x0 0x4000>;
interrupts = <72>;
interrupt-parent = <&intc>;
clocks = <&ccu CLK_DMA>;
resets = <&reset RESET_DMA>;
#dma-cells= <2>;
#dma-channels = <16>;
max-burst-size = <64>;
reserved-channels = <15 45>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "ok";
};
hdmi_adma: adma@C0883800 {
compatible = "spacemit,k1x-adma";
reg = <0x0 0xc0883800 0x0 0x100>,
<0x0 0xc0882050 0x0 0x4>,
<0x0 0xc08d0000 0x0 0x400>;
reg-names = "adma_reg", "ctrl_reg", "buf_addr";
#dma-cells = <0>;
hdmi-sample;
status = "ok";
};
spi0: spi@d4026000 {
compatible = "spacemit,k1x-spi";
reg = <0x0 0xd4026000 0x0 0x30>;
k1x,ssp-id = <0>;
k1x,ssp-clock-rate = <26000000>;
dmas = <&pdma0 DMA_SSPA0_RX 1
&pdma0 DMA_SSPA0_TX 1>;
dma-names = "rx", "tx";
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interrupt-parent = <&intc>;
interrupts = <56>;
clocks = <&ccu CLK_SSPA0>;
resets = <&reset RESET_SSPA0>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
spi1: spi@d4026800 {
compatible = "spacemit,k1x-spi";
reg = <0x0 0xd4026800 0x0 0x30>;
k1x,ssp-id = <1>;
k1x,ssp-clock-rate = <26000000>;
dmas = <&pdma0 DMA_SSPA1_RX 1
&pdma0 DMA_SSPA1_TX 1>;
dma-names = "rx", "tx";
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interrupt-parent = <&intc>;
interrupts = <57>;
clocks = <&ccu CLK_SSPA1>;
resets = <&reset RESET_SSPA1>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
spi2: spi@f0613000 {
compatible = "spacemit,k1x-spi";
reg = <0x0 0xf0613000 0x0 0x34>;
k1x,ssp-id = <2>;
k1x,ssp-clock-rate = <51200000>;
k1x,ssp-disable-dma;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interrupt-parent = <&intc>;
interrupts = <54>;
clocks = <&ccu CLK_SEC_SSP2>;
resets = <&reset RESET_SEC_SSP2>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
spi3: spi@d401c000 {
compatible = "spacemit,k1x-spi";
reg = <0x0 0xd401c000 0x0 0x34>;
k1x,ssp-id = <3>;
k1x,ssp-clock-rate = <51200000>;
dmas = <&pdma0 DMA_SSP3_RX 1
&pdma0 DMA_SSP3_TX 1>;
dma-names = "rx", "tx";
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interrupt-parent = <&intc>;
interrupts = <55>;
clocks = <&ccu CLK_SSP3>;
resets = <&reset RESET_SSP3>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
i2c0: i2c@d4010800 {
compatible = "spacemit,k1x-i2c";
spacemit,adapter-id = <0>;
reg = <0x0 0xd4010800 0x0 0x38>;
/* usually i2c client has only 1 reg field */
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <36>;
clocks = <&ccu CLK_TWSI0>;
resets = <&reset RESET_TWSI0>;
/*
dmas = <&pdma0 DMA_I2C0_RX 1
&pdma0 DMA_I2C0_TX 1>;
dma-names = "rx", "tx";
*/
spacemit,dma-disable;
/* spacemit,i2c-fast-mode; */
/* spacemit,i2c-high-mode; */
spacemit,i2c-master-code = /bits/ 8 <0x0e>;
spacemit,i2c-clk-rate = <32000000>;
spacemit,i2c-lcr = <0x82c469f>;
spacemit,i2c-wcr = <0x142a>;
/* apb clock: 26MHz or 52MHz */
spacemit,apb_clock = <52000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
i2c1: i2c@d4011000 {
compatible = "spacemit,k1x-i2c";
spacemit,adapter-id = <1>;
reg = <0x0 0xd4011000 0x0 0x38>;
/* usually i2c client has only 1 reg field */
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <37>;
clocks = <&ccu CLK_TWSI1>;
resets = <&reset RESET_TWSI1>;
/*
dmas = <&pdma0 DMA_I2C1_RX 1
&pdma0 DMA_I2C1_TX 1>;
dma-names = "rx", "tx";
*/
spacemit,dma-disable;
/* spacemit,i2c-fast-mode; */
/* spacemit,i2c-high-mode; */
spacemit,i2c-master-code = /bits/ 8 <0x0e>;
spacemit,i2c-clk-rate = <32000000>;
spacemit,i2c-lcr = <0x82c469f>;
spacemit,i2c-wcr = <0x142a>;
/* apb clock: 26MHz or 52MHz */
spacemit,apb_clock = <52000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
i2c2: i2c@d4012000 {
compatible = "spacemit,k1x-i2c";
spacemit,adapter-id = <2>;
reg = <0x0 0xd4012000 0x0 0x38>;
/* usually i2c client has only 1 reg field */
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <38>;
clocks = <&ccu CLK_TWSI2>;
resets = <&reset RESET_TWSI2>;
/*
dmas = <&pdma0 DMA_I2C2_RX 1
&pdma0 DMA_I2C2_TX 1>;
dma-names = "rx", "tx";
*/
spacemit,dma-disable;
/* spacemit,i2c-fast-mode; */
/* spacemit,i2c-high-mode; */
spacemit,i2c-master-code = /bits/ 8 <0x0e>;
spacemit,i2c-clk-rate = <32000000>;
spacemit,i2c-lcr = <0x82c469f>;
spacemit,i2c-wcr = <0x142a>;
/* apb clock: 26MHz or 52MHz */
spacemit,apb_clock = <52000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
i2c3: i2c@f0614000 {
compatible = "spacemit,k1x-i2c";
spacemit,adapter-id = <3>;
reg = <0x0 0xf0614000 0x0 0x38>;
/* usually i2c client has only 1 reg field */
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <39>;
clocks = <&ccu CLK_SEC_TWSI3>;
resets = <&reset RESET_SEC_TWSI3>;
spacemit,dma-disable;
/* spacemit,i2c-fast-mode; */
/* spacemit,i2c-high-mode; */
spacemit,i2c-master-code = /bits/ 8 <0x0e>;
spacemit,i2c-clk-rate = <32000000>;
spacemit,i2c-lcr = <0x82c469f>;
spacemit,i2c-wcr = <0x142a>;
/* apb clock: 26MHz or 52MHz */
spacemit,apb_clock = <52000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
i2c4: i2c@d4012800 {
compatible = "spacemit,k1x-i2c";
spacemit,adapter-id = <4>;
reg = <0x0 0xd4012800 0x0 0x38>;
/* usually i2c client has only 1 reg field */
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <40>;
clocks = <&ccu CLK_TWSI4>;
resets = <&reset RESET_TWSI4>;
/*
dmas = <&pdma0 DMA_I2C4_RX 1
&pdma0 DMA_I2C4_TX 1>;
dma-names = "rx", "tx";
*/
spacemit,dma-disable;
/* spacemit,i2c-fast-mode; */
/* spacemit,i2c-high-mode; */
spacemit,i2c-master-code = /bits/ 8 <0x0e>;
spacemit,i2c-clk-rate = <32000000>;
spacemit,i2c-lcr = <0x82c469f>;
spacemit,i2c-wcr = <0x142a>;
/* apb clock: 26MHz or 52MHz */
spacemit,apb_clock = <52000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
i2c5: i2c@d4013800 {
compatible = "spacemit,k1x-i2c";
spacemit,adapter-id = <5>;
reg = <0x0 0xd4013800 0x0 0x38>;
/* usually i2c client has only 1 reg field */
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <41>;
clocks = <&ccu CLK_TWSI5>;
resets = <&reset RESET_TWSI5>;
/*
dmas = <&pdma0 DMA_I2C5_RX 1
&pdma0 DMA_I2C5_TX 1>;
dma-names = "rx", "tx";
*/
spacemit,dma-disable;
/* spacemit,i2c-fast-mode; */
/* spacemit,i2c-high-mode; */
spacemit,i2c-master-code = /bits/ 8 <0x0e>;
spacemit,i2c-clk-rate = <32000000>;
spacemit,i2c-lcr = <0x82c469f>;
spacemit,i2c-wcr = <0x142a>;
/* apb clock: 26MHz or 52MHz */
spacemit,apb_clock = <52000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
i2c6: i2c@d4018800 {
compatible = "spacemit,k1x-i2c";
spacemit,adapter-id = <6>;
reg = <0x0 0xd4018800 0x0 0x38>;
/* usually i2c client has only 1 reg field */
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <70>;
clocks = <&ccu CLK_TWSI6>;
resets = <&reset RESET_TWSI6>;
/*
dmas = <&pdma0 DMA_I2C6_RX 1
&pdma0 DMA_I2C6_TX 1>;
dma-names = "rx", "tx";
*/
spacemit,dma-disable;
/* spacemit,i2c-fast-mode; */
/* spacemit,i2c-high-mode; */
spacemit,i2c-master-code = /bits/ 8 <0x0e>;
spacemit,i2c-clk-rate = <32000000>;
spacemit,i2c-lcr = <0x82c469f>;
spacemit,i2c-wcr = <0x142a>;
/* apb clock: 26MHz or 52MHz */
spacemit,apb_clock = <52000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
i2c7: i2c@d401d000 {
compatible = "spacemit,k1x-i2c";
spacemit,adapter-id = <7>;
reg = <0x0 0xd401d000 0x0 0x38>;
/* usually i2c client has only 1 reg field */
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <18>;
clocks = <&ccu CLK_TWSI7>;
resets = <&reset RESET_TWSI7>;
/*
dmas = <&pdma0 DMA_I2C7_RX 1
&pdma0 DMA_I2C7_TX 1>;
dma-names = "rx", "tx";
*/
spacemit,dma-disable;
/* spacemit,i2c-fast-mode; */
/* spacemit,i2c-high-mode; */
spacemit,i2c-master-code = /bits/ 8 <0x0e>;
spacemit,i2c-clk-rate = <32000000>;
spacemit,i2c-lcr = <0x82c469f>;
spacemit,i2c-wcr = <0x142a>;
/* apb clock: 26MHz or 52MHz */
spacemit,apb_clock = <52000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
i2c8: i2c@d401d800 {
compatible = "spacemit,k1x-i2c";
spacemit,adapter-id = <8>;
reg = <0x0 0xd401d800 0x0 0x38>;
/* usually i2c client has only 1 reg field */
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <19>;
clocks = <&ccu CLK_TWSI8>;
resets = <&reset RESET_TWSI8>;
/*
dmas = <&pdma0 DMA_I2C8_RX 1
&pdma0 DMA_I2C8_TX 1>;
dma-names = "rx", "tx";
*/
spacemit,dma-disable;
/* spacemit,i2c-fast-mode; */
/* spacemit,i2c-high-mode; */
spacemit,i2c-master-code = /bits/ 8 <0x0e>;
spacemit,i2c-clk-rate = <32000000>;
spacemit,i2c-lcr = <0x82c469f>;
spacemit,i2c-wcr = <0x142a>;
/* apb clock: 26MHz or 52MHz */
spacemit,apb_clock = <52000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
ri2c0: ri2c@c0887000 {
compatible = "spacemit,k1x-i2c-rcpu";
spacemit,adapter-id = <9>;
reg = <0x0 0xc0887000 0x0 0x38>;
/* usually i2c client has only 1 reg field */
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ccu CLK_RCPU_I2C0>;
resets = <&reset RESET_RCPU_I2C0>;
/*
dmas = <&pdma0 DMA_I2C0_RX 1
&pdma0 DMA_I2C0_TX 1>;
dma-names = "rx", "tx";
*/
rcpu-i2c;
spacemit,dma-disable;
/* spacemit,i2c-fast-mode; */
/* spacemit,i2c-high-mode; */
spacemit,i2c-master-code = /bits/ 8 <0x0e>;
spacemit,i2c-clk-rate = <32000000>;
spacemit,i2c-lcr = <0x82c469f>;
spacemit,i2c-wcr = <0x142a>;
/* apb clock: 26MHz or 52MHz */
spacemit,apb_clock = <52000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "okay";
};
pwm0: pwm@d401a000 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd401a000 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM0>;
resets = <&reset RESET_PWM0>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm1: pwm@d401a400 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd401a400 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM1>;
resets = <&reset RESET_PWM1>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm2: pwm@d401a800 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd401a800 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM2>;
resets = <&reset RESET_PWM2>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm3: pwm@d401ac00 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd401ac00 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM3>;
resets = <&reset RESET_PWM3>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm4: pwm@d401b000 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd401b000 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM4>;
resets = <&reset RESET_PWM4>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm5: pwm@d401b400 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd401b400 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM5>;
resets = <&reset RESET_PWM5>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm6: pwm@d401b800 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd401b800 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM6>;
resets = <&reset RESET_PWM6>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm7: pwm@d401bc00 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd401bc00 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM7>;
resets = <&reset RESET_PWM7>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm8: pwm@d4020000 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4020000 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM8>;
resets = <&reset RESET_PWM8>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm9: pwm@d4020400 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4020400 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM9>;
resets = <&reset RESET_PWM9>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm10: pwm@d4020800 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4020800 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM10>;
resets = <&reset RESET_PWM10>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm11: pwm@d4020c00 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4020c00 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM11>;
resets = <&reset RESET_PWM11>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm12: pwm@d4021000 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4021000 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM12>;
resets = <&reset RESET_PWM12>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm13: pwm@d4021400 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4021400 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM13>;
resets = <&reset RESET_PWM13>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm14: pwm@d4021800 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4021800 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM14>;
resets = <&reset RESET_PWM14>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm15: pwm@d4021c00 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4021c00 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM15>;
resets = <&reset RESET_PWM15>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm16: pwm@d4022000 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4022000 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM16>;
resets = <&reset RESET_PWM16>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm17: pwm@d4022400 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4022400 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM17>;
resets = <&reset RESET_PWM17>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm18: pwm@d4022800 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4022800 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM18>;
resets = <&reset RESET_PWM18>;
k1x,pwm-disable-fd;
status = "disabled";
};
pwm19: pwm@d4022c00 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xd4022c00 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_PWM19>;
resets = <&reset RESET_PWM19>;
k1x,pwm-disable-fd;
status = "disabled";
};
rpwm0: pwm@c0888100 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xc0888100 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_RCPU2_PWM0>;
resets = <&reset RESET_RCPU2_PWM0>;
k1x,pwm-disable-fd;
rcpu-pwm;
status = "disabled";
};
rpwm1: pwm@c0888200 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xc0888200 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_RCPU2_PWM1>;
resets = <&reset RESET_RCPU2_PWM1>;
k1x,pwm-disable-fd;
rcpu-pwm;
status = "disabled";
};
rpwm2: pwm@c0888300 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xc0888300 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_RCPU2_PWM2>;
resets = <&reset RESET_RCPU2_PWM2>;
k1x,pwm-disable-fd;
rcpu-pwm;
status = "disabled";
};
rpwm3: pwm@c0888400 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xc0888400 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_RCPU2_PWM3>;
resets = <&reset RESET_RCPU2_PWM3>;
k1x,pwm-disable-fd;
rcpu-pwm;
status = "disabled";
};
rpwm4: pwm@c0888500 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xc0888500 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_RCPU2_PWM4>;
resets = <&reset RESET_RCPU2_PWM4>;
k1x,pwm-disable-fd;
rcpu-pwm;
status = "disabled";
};
rpwm5: pwm@c0888600 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xc0888600 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_RCPU2_PWM5>;
resets = <&reset RESET_RCPU2_PWM5>;
k1x,pwm-disable-fd;
rcpu-pwm;
status = "disabled";
};
rpwm6: pwm@c0888700 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xc0888700 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_RCPU2_PWM6>;
resets = <&reset RESET_RCPU2_PWM6>;
k1x,pwm-disable-fd;
rcpu-pwm;
status = "disabled";
};
rpwm7: pwm@c0888800 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xc0888800 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_RCPU2_PWM7>;
resets = <&reset RESET_RCPU2_PWM7>;
k1x,pwm-disable-fd;
rcpu-pwm;
status = "disabled";
};
rpwm8: pwm@c0888900 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xc0888900 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_RCPU2_PWM8>;
resets = <&reset RESET_RCPU2_PWM8>;
k1x,pwm-disable-fd;
rcpu-pwm;
status = "disabled";
};
rpwm9: pwm@c0888a00 {
compatible = "spacemit,k1x-pwm";
reg = <0x0 0xc0888a00 0x0 0x10>;
#pwm-cells = <1>;
clocks = <&ccu CLK_RCPU2_PWM9>;
resets = <&reset RESET_RCPU2_PWM9>;
k1x,pwm-disable-fd;
rcpu-pwm;
status = "disabled";
};
ircrx: irc-rx@d4017f00 {
compatible = "spacemit,k1x-irc";
reg = <0x0 0xd4017f00 0x0 0x100>;
interrupts = <69>;
interrupt-parent = <&intc>;
clocks = <&ccu CLK_IR>;
resets = <&reset RESET_IR>;
clock-frequency = <102400000>;
status = "disabled";
};
r_ircrx: irc-rx@c088e000 {
compatible = "spacemit,k1x-rirc";
reg = <0x0 0xc088e000 0x0 0x100>;
clocks = <&ccu CLK_RCPU_IR>;
resets = <&reset RESET_RCPU_IR>;
clock-frequency = <30720000>;
rcpu-ir;
status = "disabled";
};
ddraxi_mon: ddraxi_mon@c0058500 {
compatible = "spacemit,ddraxi-mon";
reg = <0 0xc0058500 0 0x80>;
status = "ok";
};
timer0: timer@d4014000 {
compatible = "spacemit,soc-timer";
reg = <0x0 0xd4014000 0x0 0xc8>;
spacemit,timer-id = <0>;
spacemit,timer-fastclk-frequency = <12800000>;
spacemit,timer-apb-frequency = <52000000>;
spacemit,timer-frequency = <12800000>;
clocks = <&ccu CLK_TIMERS1>;
resets = <&reset RESET_TIMERS1>;
status = "ok";
counter0 {
compatible = "spacemit,timer-match";
interrupts = <23>;
interrupt-parent = <&intc>;
spacemit,timer-broadcast;
spacemit,timer-counter-id = <0>;
status = "ok";
};
};
timer1: timer@d4016000 {
compatible = "spacemit,soc-timer";
reg = <0x0 0xd4016000 0x0 0xc8>;
spacemit,timer-id = <1>;
spacemit,timer-fastclk-frequency = <12800000>;
spacemit,timer-apb-frequency = <52000000>;
spacemit,timer-frequency = <12800000>;
clocks = <&ccu CLK_TIMERS2>;
resets = <&reset RESET_TIMERS2>;
status = "disabled";
counter0 {
compatible = "spacemit,timer-match";
interrupts = <26>;
interrupt-parent = <&intc>;
spacemit,timer-counter-id = <0>;
status = "disabled";
};
};
watchdog: watchdog@d4080000 {
compatible = "spacemit,soc-wdt";
clocks = <&ccu CLK_WDT>;
resets = <&reset RESET_WDT>;
reg = <0x0 0xd4080000 0x0 0xff>,
<0x0 0xd4050000 0x0 0x1024>;
interrupts = <35>;
interrupt-parent = <&intc>;
spa,wdt-disabled;
status = "disabled";
};
reboot: handler@d4282f90 {
compatible = "spacemit,k1x-reboot";
reg = <0x0 0xd4282f90 0x0 0x4>;
status = "ok";
};
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0x0 0xd4010000 0x0 0x100>;
interrupt-parent = <&intc>;
interrupts = <21>, <22>;
interrupt-names = "rtc 1Hz", "rtc alarm";
clocks = <&ccu CLK_RTC>;
resets = <&reset RESET_RTC>;
status = "disabled";
};
flexcan0: fdcan@d4028000 {
compatible = "spacemit,k1x-flexcan";
reg = <0x0 0xd4028000 0x0 0x4000>;
interrupts = <16>;
interrupt-parent = <&intc>;
clocks = <&ccu CLK_CAN0>,<&ccu CLK_CAN0_BUS>;
clock-names = "per","ipg";
resets = <&reset RESET_CAN0>;
fsl,clk-source = <0>;
status = "disabled";
};
r_flexcan: fdcan@c0870000 {
compatible = "spacemit,k1x-r-flexcan";
reg = <0x0 0xc0870000 0x0 0x4000>;
interrupt-parent = <&intc>;
fsl,clk-source = <0>;
clocks = <&ccu CLK_RCPU_CAN>,<&ccu CLK_RCPU_CAN_BUS>;
clock-names = "per","ipg";
resets = <&reset RESET_RCPU_CAN>;
status = "disabled";
};
gpio: gpio@d4019000 {
compatible = "spacemit,k1x-gpio";
reg = <0x0 0xd4019000 0x0 0x800>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <58>;
clocks = <&ccu CLK_GPIO>;
interrupt-names = "gpio_mux";
interrupt-parent = <&intc>;
interrupt-controller;
#interrupt-cells = <2>;
gcb0: gpio0 {
reg-offset = <0x0>;
};
gcb1: gpio1 {
reg-offset = <0x4>;
};
gcb2: gpio2 {
reg-offset = <0x8>;
};
gcb3: gpio3 {
reg-offset = <0x100>;
};
};
ec_master: ethercat_master {
compatible = "igh,k1x-ec-master";
run-on-cpu = <1>;
debug-level = <0>;
master-count = <1>;
ec-devices = <ð0>,<ð1>;
master-indexes = <0>,<0>;
modes = "ec_main","ec_backup";
status = "disable";
};
eth0: ethernet@cac80000 {
compatible = "spacemit,k1x-emac";
reg = <0x00000000 0xCAC80000 0x00000000 0x00000420>;
k1x,apmu-base-reg = <0xD4282800>;
ctrl-reg = <0x3e4>;
dline-reg = <0x3e8>;
clocks = <&ccu CLK_EMAC0_BUS>,
<&ccu CLK_EMAC0_PTP>;
clock-names = "emac-clk", "ptp-clk";
resets = <&reset RESET_EMAC0>;
reset-names = "emac-reset";
interrupts-extended = <&intc 131>;
mac-address = [ 00 00 00 00 00 00 ];
ptp-support;
ptp-clk-rate = <10000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range5>;
interconnect-names = "dma-mem";
status = "disabled";
};
eth1: ethernet@cac81000 {
compatible = "spacemit,k1x-emac";
reg = <0x00000000 0xCAC81000 0x00000000 0x00000420>;
k1x,apmu-base-reg = <0xD4282800>;
ctrl-reg = <0x3ec>;
dline-reg = <0x3f0>;
clocks = <&ccu CLK_EMAC1_BUS>,
<&ccu CLK_EMAC1_PTP>;
clock-names = "emac-clk", "ptp-clk";
resets = <&reset RESET_EMAC1>;
reset-names = "emac-reset";
interrupts-extended = <&intc 133>;
mac-address = [ 00 00 00 00 00 00 ];
ptp-support;
ptp-clk-rate = <10000000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
interconnects = <&dram_range5>;
interconnect-names = "dma-mem";
status = "disabled";
};
extcon: extcon@d428287c {
compatible = "spacemit,vbus-id";
reg = <0x0 0xd428287c 0x0 0x4>,
<0x0 0xd4282918 0x0 0x4>;
reg-names = "reg_pmuap", "pin_state";
interrupts = <106>;
interrupt-parent = <&intc>;
clocks = <&ccu CLK_USB_AXI>;
status = "disabled";
};
usbphy: usbphy@c0940000 {
compatible = "spacemit,usb2-phy";
reg = <0x0 0xc0940000 0x0 0x200>;
clocks = <&ccu CLK_USB_AXI>;
status = "disabled";
};
otg: otg@c0900100 {
compatible = "spacemit,mv-otg";
reg = <0x0 0xc0900100 0x0 0x4000>,
<0x0 0xd428287c 0x0 0x4>;
interrupts = <105>;
interrupt-parent = <&intc>;
spacemit,otg-name = "mv-otg";
spacemit,otg-force-a-bus-req;
clocks = <&ccu CLK_USB_AXI>;
resets = <&reset RESET_USB_AXI>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
usb-phy = <&usbphy>;
status = "disabled";
};
udc: udc@c0900100 {
compatible = "spacemit,mv-udc";
reg = <0x0 0xc0900100 0x0 0x4000>;
interrupts = <105>;
interrupt-parent = <&intc>;
spacemit,udc-name = "mv-udc";
spacemit,otg-force-a-bus-req;
resets = <&reset RESET_USB_AXI>;
clocks = <&ccu CLK_USB_AXI>;
usb-phy = <&usbphy>;
interconnects = <&dram_range0>;
interconnect-names = "dma-mem";
usb-otg = <&otg>;
status = "disabled";
};
ehci: ehci@c0900100 {
compatible = "spacemit,mv-ehci";
reg = <0x0 0xc0900100 0x0 0x4000>,
<0x0 0xd428287c 0x0 0x4>;
interrupts = <105>,<106>;
interrupt-parent = <&intc>;
spacemit,ehci-name = "mv-ehci";
spacemit,otg-force-a-bus-req;
resets = <&reset RESET_USB_AXI>;
clocks = <&ccu CLK_USB_AXI>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
usb-phy = <&usbphy>;
usb-otg = <&otg>;
interconnects = <&dram_range0>;
interconnect-names = "dma-mem";
status = "disabled";
};
usbphy1: usbphy1@c09c0000 {
compatible = "spacemit,usb2-phy";
reg = <0x0 0xc09c0000 0x0 0x200>;
clocks = <&ccu CLK_USB_P1>;
status = "disabled";
};
otg1: otg1@c0980100 {
compatible = "spacemit,mv-otg";
reg = <0x0 0xc0980100 0x0 0x4000>,
<0x0 0xd4282bc4 0x0 0x4>;
interrupts = <118>;
interrupt-parent = <&intc>;
spacemit,otg-name = "mv-otg1";
spacemit,otg-force-a-bus-req;
clocks = <&ccu CLK_USB_P1>;
resets = <&reset RESET_USBP1_AXI>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
usb-phy = <&usbphy1>;
status = "disabled";
};
udc1: udc1@c0980100 {
compatible = "spacemit,mv-udc";
reg = <0x0 0xc0980100 0x0 0x4000>;
interrupts = <118>;
interrupt-parent = <&intc>;
spacemit,udc-name = "mv-udc1";
spacemit,otg-force-a-bus-req;
resets = <&reset RESET_USBP1_AXI>;
clocks = <&ccu CLK_USB_P1>;
usb-phy = <&usbphy1>;
usb-otg = <&otg1>;
interconnects = <&dram_range0>;
interconnect-names = "dma-mem";
status = "disabled";
};
ehci1: ehci1@c0980100 {
compatible = "spacemit,mv-ehci";
reg = <0x0 0xc0980100 0x0 0x4000>,
<0x0 0xd4282bc4 0x0 0x4>;
interrupts = <118>,<148>;
interrupt-parent = <&intc>;
spacemit,ehci-name = "mv-ehci1";
spacemit,otg-force-a-bus-req;
resets = <&reset RESET_USBP1_AXI>;
clocks = <&ccu CLK_USB_P1>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
usb-phy = <&usbphy1>;
usb-otg = <&otg1>;
interconnects = <&dram_range0>;
interconnect-names = "dma-mem";
status = "disabled";
};
combphy: phy@c0b10000{
compatible = "spacemit,k1x-combphy";
reg = <0x0 0xc0b10000 0x0 0x800>,
<0x0 0xd4282910 0x0 0x400>;
reg-names = "puphy", "phy_sel";
resets = <&reset RESET_COMBO_PHY>;
reset-names = "phy_rst";
#phy-cells = <1>;
status = "disabled";
};
usb2phy: usb2phy@0xc0a30000 {
compatible = "spacemit,usb2-phy";
reg = <0x0 0xc0a30000 0x0 0x200>;
spacemit,handle_connect_change;
clocks = <&ccu CLK_USB30>;
status = "disabled";
};
usb3hub: usb3hub@0 {
compatible = "spacemit,usb3-hub";
power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
status = "disabled";
};
usbdrd3: usb3@0 {
compatible = "spacemit,k1-x-dwc3";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0xd4282bc8 0x0 0x4>;
resets = <&reset RESET_USB3_0>;
reset-names = "ctl_rst";
clocks = <&ccu CLK_USB30>;
clock-names = "usbdrd30";
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
phys = <&combphy PHY_TYPE_USB3>;
phy-names = "usb3-phy";
usb-phy = <&usb2phy>;
interrupt-parent = <&intc>;
interrupts = <149>;
ranges;
interconnects = <&dram_range0>;
interconnect-names = "dma-mem";
status = "disabled";
dwc3@c0a00000 {
compatible = "snps,dwc3";
reg = <0x0 0xc0a00000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <125>;
};
};
sdhci0: sdh@d4280000 {
compatible = "spacemit,k1-x-sdhci";
reg = <0x0 0xd4280000 0x0 0x200>;
interrupts = <99>;
interrupt-parent = <&intc>;
resets = <&reset RESET_SDH_AXI>,
<&reset RESET_SDH0>;
reset-names = "sdh_axi", "sdh0";
clocks = <&ccu CLK_SDH0>,
<&ccu CLK_SDH_AXI>,
<&ccu CLK_AIB>;
clock-names = "sdh-io", "sdh-core","aib-clk";
interconnects = <&dram_range0>;
interconnect-names = "dma-mem";
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
regulator,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
status = "disabled";
};
sdhci1: sdh@d4280800 {
compatible = "spacemit,k1-x-sdhci";
reg = <0x0 0xd4280800 0x0 0x200>;
interrupts = <100>;
interrupt-parent = <&intc>;
resets = <&reset RESET_SDH_AXI>,
<&reset RESET_SDH1>;
reset-names = "sdh_axi", "sdh1";
clocks = <&ccu CLK_SDH1>,
<&ccu CLK_SDH_AXI>;
clock-names = "sdh-io", "sdh-core";
interconnects = <&dram_range0>;
interconnect-names = "dma-mem";
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
regulator,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
status = "disabled";
};
sdhci2: sdh@d4281000 {
compatible = "spacemit,k1-x-sdhci";
reg = <0x0 0xd4281000 0x0 0x200>;
interrupts = <101>;
interrupt-parent = <&intc>;
resets = <&reset RESET_SDH_AXI>,
<&reset RESET_SDH2>;
reset-names = "sdh_axi", "sdh2";
clocks = <&ccu CLK_SDH2>,
<&ccu CLK_SDH_AXI>;
clock-names = "sdh-io", "sdh-core";
interconnects = <&dram_range0>;
interconnect-names = "dma-mem";
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
clk,pm-runtime,no-sleep;
regulator,pm-runtime,no-sleep;
cpuidle,pm-runtime,sleep;
status = "disabled";
};
pcie0_rc: pcie@ca000000 {
compatible = "k1x,dwc-pcie";
reg = <0x0 0xca000000 0x0 0x00001000>, /* dbi */
<0x0 0xca300000 0x0 0x0001ff24>, /* atu registers */
<0x0 0x8f000000 0x0 0x00002000>, /* config space */
<0x0 0xd4282bcc 0x0 0x00000008>, /* k1x soc config addr */
<0x0 0xc0b20000 0x0 0x00001000>, /* phy ahb */
<0x0 0xc0b10000 0x0 0x00001000>, /* phy addr */
<0x0 0xd4282bcc 0x0 0x00000008>, /* conf0 addr */
<0x0 0xc0b10000 0x0 0x00001000>; /* phy0 addr */
reg-names = "dbi", "atu", "config", "k1x_conf", "phy_ahb", "phy_addr", "conf0_addr", "phy0_addr";
k1x,pcie-port = <0>;
clocks = <&ccu CLK_PCIE0>;
clock-names = "pcie-clk";
resets = <&reset RESET_PCIE0>;
reset-names = "pcie-reset";
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
bus-range = <0x00 0xff>;
max-link-speed = <2>;
num-lanes = <1>;
num-viewport = <8>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x8f002000 0 0x8f002000 0x0 0x100000>,
<0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x0f000000>;
interconnects = <&dram_range2>;
interconnect-names = "dma-mem";
interrupts = <141>, <145>;
interrupt-parent = <&intc>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0000 0 0 1 &pcie0_intc 1>, /* int_a */
<0000 0 0 2 &pcie0_intc 2>, /* int_b */
<0000 0 0 3 &pcie0_intc 3>, /* int_c */
<0000 0 0 4 &pcie0_intc 4>; /* int_d */
linux,pci-domain = <0>;
status = "disabled";
pcie0_intc: interrupt-controller@0 {
interrupt-controller;
reg = <0 0 0 0 0>;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1_rc: pcie@ca400000 {
compatible = "k1x,dwc-pcie";
reg = <0x0 0xca400000 0x0 0x00001000>, /* dbi */
<0x0 0xca700000 0x0 0x0001ff24>, /* atu registers */
<0x0 0x9f000000 0x0 0x00002000>, /* config space */
<0x0 0xd4282bd4 0x0 0x00000008>, /* k1x soc config addr */
<0x0 0xc0c20000 0x0 0x00001000>, /* phy ahb */
<0x0 0xc0c10000 0x0 0x00001000>, /* phy addr */
<0x0 0xd4282bcc 0x0 0x00000008>, /* conf0 addr */
<0x0 0xc0b10000 0x0 0x00001000>; /* phy0 addr */
reg-names = "dbi", "atu", "config", "k1x_conf", "phy_ahb", "phy_addr", "conf0_addr", "phy0_addr";
k1x,pcie-port = <1>;
clocks = <&ccu CLK_PCIE1>;
clock-names = "pcie-clk";
resets = <&reset RESET_PCIE1>;
reset-names = "pcie-reset";
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
bus-range = <0x00 0xff>;
max-link-speed = <2>;
num-lanes = <2>;
num-viewport = <8>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x9f002000 0 0x9f002000 0x0 0x100000>,
<0x02000000 0x0 0x90000000 0 0x90000000 0x0 0x0f000000>;
interconnects = <&dram_range6>;
interconnect-names = "dma-mem";
interrupts = <142>, <146>;
interrupt-parent = <&intc>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0000 0 0 1 &pcie1_intc 1>, /* int_a */
<0000 0 0 2 &pcie1_intc 2>, /* int_b */
<0000 0 0 3 &pcie1_intc 3>, /* int_c */
<0000 0 0 4 &pcie1_intc 4>; /* int_d */
linux,pci-domain = <1>;
status = "disabled";
pcie1_intc: interrupt-controller@0 {
interrupt-controller;
reg = <0 0 0 0 0>;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie2_rc: pcie@ca800000 {
compatible = "k1x,dwc-pcie";
reg = <0x0 0xca800000 0x0 0x00001000>, /* dbi */
<0x0 0xcab00000 0x0 0x0001ff24>, /* atu registers */
<0x0 0xb7000000 0x0 0x00002000>, /* config space */
<0x0 0xd4282bdc 0x0 0x00000008>, /* k1x soc config addr */
<0x0 0xc0d20000 0x0 0x00001000>, /* phy ahb */
<0x0 0xc0d10000 0x0 0x00001000>, /* phy addr */
<0x0 0xd4282bcc 0x0 0x00000008>, /* conf0 addr */
<0x0 0xc0b10000 0x0 0x00001000>; /* phy0 addr */
reg-names = "dbi", "atu", "config", "k1x_conf", "phy_ahb", "phy_addr", "conf0_addr", "phy0_addr";
k1x,pcie-port = <2>;
clocks = <&ccu CLK_PCIE2>;
clock-names = "pcie-clk";
resets = <&reset RESET_PCIE2>;
reset-names = "pcie-reset";
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
bus-range = <0x00 0xff>;
max-link-speed = <2>;
num-lanes = <2>;
num-viewport = <8>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0xb7002000 0 0xb7002000 0x0 0x100000>,
<0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x17000000>;
interconnects = <&dram_range7>;
interconnect-names = "dma-mem";
interrupts = <143>, <147>;
interrupt-parent = <&intc>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0000 0 0 1 &pcie2_intc 1>, /* int_a */
<0000 0 0 2 &pcie2_intc 2>, /* int_b */
<0000 0 0 3 &pcie2_intc 3>, /* int_c */
<0000 0 0 4 &pcie2_intc 4>; /* int_d */
linux,pci-domain = <2>;
status = "disabled";
pcie2_intc: interrupt-controller@0 {
interrupt-controller;
reg = <0 0 0 0 0>;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
qspi: spi@d420c000 {
compatible = "spacemit,k1x-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0xd420c000 0x0 0x1000>,
<0x0 0xb8000000 0x0 0xc00000>;
reg-names = "qspi-base", "qspi-mmap";
k1x,qspi-sfa1ad = <0x4000000>;
k1x,qspi-sfa2ad = <0x100000>;
k1x,qspi-sfb1ad = <0x100000>;
k1x,qspi-sfb2ad = <0x100000>;
clocks = <&ccu CLK_QSPI>,
<&ccu CLK_QSPI_BUS>;
clock-names = "qspi_clk", "qspi_bus_clk";
resets = <&reset RESET_QSPI>,
<&reset RESET_QSPI_BUS>;
reset-names = "qspi_reset", "qspi_bus_reset";
k1x,qspi-pmuap-reg = <0xd4282860>;
k1x,qspi-mpmu-acgr-reg = <0xd4051024>;
k1x,qspi-freq = <26500000>;
k1x,qspi-id = <4>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
cpuidle,pm-runtime,sleep;
interrupts = <117>;
interrupt-parent = <&intc>;
k1x,qspi-tx-dma = <1>;
k1x,qspi-rx-dma = <1>;
dmas = <&pdma0 45 1>;
dma-names = "tx-dma";
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
status = "disabled";
};
thermal: thermal@d4018000 {
compatible = "spacemit,k1x-tsensor";
reg = <0x0 0xd4018000 0x0 0x100>;
interrupt-parent = <&intc>;
interrupts = <61>;
clocks = <&ccu CLK_TSEN>;
clock-names = "thermal_core";
resets = <&reset RESET_TSEN>;
reset-names = "tsen_reset";
/* bjt-tsensor map:
* bjt0: local, bjt1: top,
* bjt2: gpu, bjt3: cluster0,
* bjt4: cluster1,
*/
sensor_range = <0x3 0x4>;
/* emergent_reboot_threshold = <110>; */
#thermal-sensor-cells = <1>;
status = "okay";
};
thermal_zones: thermal-zones {
};
tcm: tcm@0xd8000000 {
compatible = "spacemit,k1-x-tcm";
reg = <0x0 0xd8000000 0x0 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xd8000000 0x80000>;
no-memory-wc;
core0_tcm@0 {
reg = <0x00000 0x20000>;
pool;
};
core1_tcm@20000 {
reg = <0x20000 0x20000>;
pool;
};
core2_tcm@40000 {
reg = <0x40000 0x20000>;
pool;
};
core3_tcm@60000 {
reg = <0x60000 0x20000>;
pool;
};
};
linlon-v5@c0500000 {
compatible = "arm china,linlon-v5";
reg = <0x0 0xC0500000 0x0 0x10000>;
interrupt-parent = <&intc>;
interrupts = <74>;
clocks = <&ccu CLK_VPU>;
clock-names = "vpu_clk";
power-domains = <&power K1X_PMU_VPU_PWR_DOMAIN>;
resets = <&reset RESET_VPU>;
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
clk,pm-runtime,no-sleep;
status = "okay";
};
v2d@c0100000 {
compatible = "spacemit,v2d";
reg = <0x0 0xc0100000 0x0 0x1000>;
reg-names = "v2dreg";
clocks = <&ccu CLK_DPU_MCLK>,
<&ccu CLK_V2D>;
clock-names = "v2d-io", "v2d-core";
resets = <&reset RESET_V2D>;
reset-names= "v2d_reset";
interrupt-parent = <&intc>;
interrupts = <86>;
interconnects = <&dram_range3>;
interconnect-names = "dma-mem";
status = "ok";
};
jpu@c02f8000 {
compatible = "chip-media, jpu";
reg = <0 0xc02f8000 0 0x700>;
interrupt-parent = <&intc>;
interrupts = <87>;
jpu,chip-id = <0>;
clocks = <&ccu CLK_JPG>,
<&ccu CLK_DPU_MCLK>,
<&ccu CLK_ISP_BUS>;
clock-names ="cclk", "aclk", "iclk";
power-domains = <&power K1X_PMU_ISP_PWR_DOMAIN>;
resets = <&reset RESET_JPG>,
<&reset RESET_LCD_MCLK>,
<&reset RESET_ISP_CI>,
<&reset RESET_ISP>,
<&reset RESET_ISP_AHB>;
reset-names = "jpg_reset", "lcd_mclk_reset", "isp_ci_reset", "freset", "sreset";
jpu,cclk-max-frequency = /bits/ 64 <1000000000>;
jpu,cclk-min-frequency = <409000000>;
jpu,cclk-default-frequency = <614000000>;
page-size = <4>;
interconnects = <&dram_range5>;
interconnect-names = "dma-mem";
clk,pm-runtime,no-sleep;
status = "okay";
};
pwm_bl: lcd_backlight {
compatible = "pwm-backlight";
status = "disabled";
};
imggpu: imggpu@cac00000 {
compatible = "img,rgx";
interrupt-names = "rgxirq";
interrupt-parent = <&intc>;
interrupts = <75>;
reg = <0x0 0xcac00000 0x0 0x80000>;
reg-names = "rgxregs";
clocks = <&ccu CLK_GPU>;
clock-names = "gpu_clk";
resets = <&reset RESET_GPU>;
power-domains = <&power K1X_PMU_GPU_PWR_DOMAIN>;
interconnects = <&dram_range1>;
interconnect-names = "dma-mem";
status = "ok";
};
spacemit_crypto_engine@d8600000 {
compatible = "spacemit,crypto_engine";
spacemit-crypto-engine-0 = <0xd8600000 0x00100000>;
interrupt-parent = <&intc>;
interrupts = <113>;
num-engines = <1>;
clocks = <&ccu CLK_AES>;
resets = <&reset RESET_AES>;
interconnects = <&dram_range5>;
interconnect-names = "dma-mem";
status = "okay";
};
crng: crng@f0703800 {
compatible = "spacemit,hw_crng";
reg = <0x0 0xf0703800 0x0 0x100>;
clocks = <&ccu CLK_AES>;
resets = <&reset RESET_AES>;
status = "okay";
};
efuse: fuse@f0702800 {
compatible = "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0xf0702800 0x400>;
status = "disabled";
};
keypad: keypad@f0617000 {
compatible = "marvell,pxa27x-keypad";
reg = <0x0 0xf0617000 0x0 0x1000>,
<0x0 0xd428287c 0x0 0x4>;
interrupt-parent = <&intc>;
interrupts = <63>;
clocks = <&ccu CLK_SEC_KPC>;
clock-names = "kpc-clk";
resets = <&reset RESET_SEC_KPC>;
reset-names = "kpc-reset";
status = "disabled";
};
socinfo: socinfo@0 {
compatible = "spacemit,socinfo-k1x";
status = "disabled";
};
ciu: ciu@d4282c00 {
compatible = "spacemit,aquila-ciu", "spacemit,ciu", "syscon";
reg = <0x0 0xd4282c00 0x0 0x2d0>;
};
};
pmu {
compatible = "riscv,pmu";
riscv,event-to-mhpmevent =
/* BRANCH_INSTRUCTIONS */
<0x00005 0x0 0x01>,
/* BRANCH_MISSES */
<0x00006 0x0 0x02>,
/* STALLED_CYCLES_FRONTEND */
<0x00008 0x0 0x03>,
/* STALLED_CYCLES_BACKEND */
<0x00009 0x0 0x04>,
/* L1D_READ_ACCESS */
<0x10000 0x0 0x06>,
/* L1D_READ_MISS */
<0x10001 0x0 0x05>,
/* L1D_WRITE_ACCESS */
<0x10002 0x0 0x0a>,
/* L1D_WRITE_MISS */
<0x10003 0x0 0x09>,
/* L1I_READ_ACCESS */
<0x10008 0x0 0x0c>,
/* L1I_READ_MISS */
<0x10009 0x0 0x0b>,
/* L1I_PREFETCH_ACCESS */
<0x1000c 0x0 0x0e>,
/* L1I_PREFETCH_MISS */
<0x1000d 0x0 0x0d>,
/* DTLB_READ_MISS */
<0x10019 0x0 0x15>,
/* DTLB_WRITE_MISS */
<0x1001b 0x0 0x19>,
/* ITLB_READ_MISS */
<0x10021 0x0 0x1b>;
/* 16 valid counters: mhpmcounter3 ~ mhpmcounter18 */
riscv,event-to-mhpmcounters =
<0x00005 0x00006 0x0007fff8>,
<0x00008 0x00009 0x0007fff8>,
<0x10000 0x10003 0x0007fff8>,
<0x10008 0x10009 0x0007fff8>,
<0x1000c 0x1000d 0x0007fff8>,
<0x10019 0x10019 0x0007fff8>,
<0x1001b 0x1001b 0x0007fff8>,
<0x10021 0x10021 0x0007fff8>;
riscv,raw-event-to-mhpmcounters =
/*
* For convenience, we treat 0x1~0xff as valid indexes,
* but actually in hardware the valid indexes are 0x1~0xbd.
*/
<0x0 0x0 0xffffffff 0xffffff00 0x0007fff8>;
};
hdmi_dma: spacemit_snd_dma_hdmi {
compatible = "spacemit,spacemit-snd-dma-hdmi";
reg = <0 0xc08d0400 0 0x3c00>;
dmas = <&hdmi_adma>;
dma-names = "tx";
#sound-dai-cells = <0>;
status = "okay";
};
dummy_codec: dummy_codec{
compatible = "spacemit,dummy-codec";
#sound-dai-cells = <0>;
status = "okay";
};
i2s0: i2s0@d4026000 {
compatible = "spacemit,spacemit-i2s0";
reg = <0x0 0xD4026000 0x0 0x30>;
reg-names = "i2s0";
#sound-dai-cells = <0>;
clocks = <&ccu CLK_SSPA0_I2S>, <&ccu CLK_SSPA0>;
clock-names = "sspa-i2S-clk", "sspa-clk";
resets = <&reset RESET_SSPA0>;
reset-names = "sspa-rst";
assigned-clocks = <&ccu CLK_SSPA0_I2S>, <&ccu CLK_SSPA0>;
assigned-clock-rates = <1536000>, <1536000>;
power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>;
status = "disabled";
};
i2s1: i2s1@d4026800 {
compatible = "spacemit,spacemit-i2s1";
reg = <0x0 0xD4026800 0x0 0x30>;
reg-names = "i2s1";
#sound-dai-cells = <0>;
clocks = <&ccu CLK_SSPA0_I2S>, <&ccu CLK_SSPA1>;
clock-names = "sspa-i2S-clk", "sspa-clk";
resets = <&reset RESET_SSPA1>;
reset-names = "sspa-rst";
assigned-clocks = <&ccu CLK_SSPA0_I2S>, <&ccu CLK_SSPA1>;
assigned-clock-rates = <1536000>, <1536000>;
power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>;
status = "disabled";
};
i2s3: i2s3@d401c000 {
compatible = "spacemit,spacemit-i2s3";
reg = <0x0 0xd401c000 0x0 0x30>;
reg-names = "i2s3";
#sound-dai-cells = <0>;
clocks = <&ccu CLK_SSP3_I2S>, <&ccu CLK_SSP3>;
clock-names = "sspa-i2S-clk", "sspa-clk";
resets = <&reset RESET_SSP3>;
reset-names = "sspa-rst";
assigned-clocks = <&ccu CLK_SSP3_I2S>, <&ccu CLK_SSP3>;
assigned-clock-rates = <1536000>, <1536000>;
power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>;
status = "disabled";
};
i2s0_dma: spacemit-snd-dma0 {
compatible = "spacemit,spacemit-snd-dma0";
dmas = <&pdma0 22 1
&pdma0 21 1>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
status = "okay";
};
i2s1_dma: spacemit-snd-dma1 {
compatible = "spacemit,spacemit-snd-dma1";
dmas = <&pdma0 24 1
&pdma0 23 1>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
status = "okay";
};
i2s3_dma: spacemit-snd-dma3 {
compatible = "spacemit,spacemit-snd-dma3";
dmas = <&pdma0 DMA_SSP3_RX 1
&pdma0 DMA_SSP3_TX 1>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
status = "okay";
};
sound_hdmi: snd-card@0 {
compatible = "spacemit,simple-audio-card";
simple-audio-card,name = "snd-hdmi";
simple-audio-card,playback_only;
status = "disabled";
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
simple-audio-card,plat {
sound-dai = <&hdmi_dma>;
};
simple-audio-card,codec {
sound-dai = <&dummy_codec>;
};
};
sound_codec: snd-card@1 {
compatible = "spacemit,simple-audio-card";
simple-audio-card,format = "i2s";
status = "disabled";
interconnects = <&dram_range4>;
interconnect-names = "dma-mem";
spacemit,init-jack;
simple-audio-card,cpu {
sound-dai = <&i2s0>;
};
simple-audio-card,plat {
sound-dai = <&i2s0_dma>;
};
};
};
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