Verilog Generator of Neural Net Digit Detector for FPGA
Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
:zap: Yolo universal target detection model combined with EfficientNet-lite, the calculation amount is only 230Mflops(0.23Bflops), and the model size is 1.3MB