2116178 lvcs 1637255225
23
西安交通大学FPGA专题实验 数字钟和出租车计价器
VHDL
over 1 year ago
5440949 yuanbo peng 1578986769
0
This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.
VHDL
almost 4 years ago

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