一个从零开始写的极简、非常易懂的RISC-V处理器核。
Icarus Verilog is intended to compile ALL of the Verilog HDL as
described in the IEEE-1364 standard. Of course, it's not quite there
yet. It does currently handle a mix of structural and behavioural
constructs. For a view of the current state of Icarus Verilog, see its
home page at <http://iverilog.icarus.com/>.
A prototype technology mapper for dual-output LUTs.
从零写一个16位处理器，采用自主设计的大黄鸭指令集，单周期3级流水线，8位指令双发射。配套大黄鸭汇编器，简化程序开发。目前主体设计已完成，大家的支持是我前进的动力。
openLA500是一款实现了龙芯架构32位精简版指令集（loongarch32r）的处理器核
chiplab项目致力于构建基于LoongArch32 Reduced的soc敏捷开发平台
