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liangkangnan / tinyriscvVerilogApache-2.0

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一个从零开始写的极简、非常易懂的RISC-V处理器核。 spread retract

  • Assembly 47.4%
  • Verilog 35.8%
  • C 15.0%
  • Makefile 1.2%
  • Python 0.4%
  • Other 0.2%
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README.en.md

###1.Introduction

This opensource project is a tiny riscv processor core which written by verilog. It is very simple and easy to understand. Tinyriscv has the following characteristics:

1)Implemented RV32I instruction set.

2)Use three-stage flow line.

3)Can run simple C program.

###2.How to use

Tinyriscv run on windows platform, it Compiled and simulated with iverilog. Before to use, you need install these tools below:

1)iverilog

Download from http://bleyer.org/icarus/](http://bleyer.org/icarus/, install it and add to system environment PATH.

2)GNU Toolchain

Download from BaiduNetDisk https://pan.baidu.com/s/1bYgslKxHMjtiZtIPsB2caQ, extraction code is 9n3c, decompress it into tools directory.

3)make tool

Download from BaiduNetDisk https://pan.baidu.com/s/1nFaUIwv171PDXuF7TziDFg, extraction code is 9ntc, decompress it and add to system environment PATH.

Take the "add" instruction as an example to show how to use:

Open the CMD and goto the sim directory and run command below:

sim_new_nowave.bat ..\tests\isa\generated\rv32ui-p-add.bin inst.data

You can see the following print if it run successfully:

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