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打野/Verilog练习代码

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文件
2024-1-12.v
2024-1-13.v
DFF.v
Hello Verilog.v
LICENSE
all kinds of cells.v
and gate.v
and_gate(review).v
comp_conv(1).v
comp_conv(2).v
comp_conv(3).v
comp_conv(4).v
comp_conv(review).v
comp_conv(review1).v
comp_conv(review2).v
comp_conv(补码转换) 草稿.v
comp_conv.v
either-or always(review).v
either-or assign(review).v
either-or logic(2).v
either-or logic.v
if-else if-else.v
if-else 嵌套语句.v
inv(compare look tb name).v
inv(review).v
inv.v
inv_8bits (2).v
inv_8bits.v
many-way selection logic.v
many-way selection logic(草稿).v
many-way selection(if-else).v
many-way selection(review).v
nand_gate(review) (2).v
nand_gate(review).v
nand_gate.v
nand_gate_4bits(review) (2).v
nand_gate_4bits(review).v
nand_gate_4bits.v
pracice_1.5.v
pracice_1.5(测试).v
practce_11.23.v
practice.v
practice1.v
practice2.v
practice_1.1.v
practice_1.10.v
practice_1.11.v
practice_1.14.v
practice_1.2.v
practice_1.3.v
practice_1.4.v
practice_1.7.v
practice_1.8.v
practice_1.9.v
practice_10.13.v
practice_10.14(2).v
practice_10.14.v
practice_10.15.v
practice_10.16.v
practice_10.17.v
practice_10.18.v
practice_10.22.v
practice_10.23.v
practice_10.24.v
practice_10.25.v
practice_10.26.v
practice_10.27.v
practice_10.28.v
practice_10.29.v
practice_10.30.v
practice_10.31.v
practice_11.1.v
practice_11.10.v
practice_11.11.v
practice_11.12.v
practice_11.13.v
practice_11.14.v
practice_11.15.v
practice_11.16(comp-myself).v
practice_11.18.v
practice_11.19.v
practice_11.2.v
practice_11.20.v
practice_11.21.v
practice_11.22.v
practice_11.24.v
practice_11.4.v
practice_11.5.v
practice_11.6.v
practice_11.7.v
practice_11.8.v
practice_11.9.v
practice_24.1.17.v
practice_24.1.18.v
practice_24.1.19(correct).v
practice_24.1.19(改正).v
practice_24.1.19.v
practice_24.1.22(correct).v
practice_24.1.22.v
practice_24.1.24.v
practice_24.1.30.v
practice_24.1.31.v
practice_24.2.1.v
practice_24.2.10.v
practice_24.2.11 (2).v
practice_24.2.11.v
practice_24.2.12.v
practice_24.2.13.v
practice_24.2.14.v
practice_24.2.15.v
practice_24.2.16.v
practice_24.2.18.v
practice_24.2.2.v
practice_24.2.20.v
practice_24.2.21.v
practice_24.2.22.v
practice_24.2.23.v
practice_24.2.24.v
practice_24.2.27.v
practice_24.2.28.v
practice_24.2.29.v
practice_24.2.3.v
practice_24.2.4.v
practice_24.2.5 (2).v
practice_24.2.5.v
practice_24.2.7.v
practice_24.3.1.v
practice_24.3.2.v
practice_24.3.3.v
practice_24.3.4.v
practice_24.3.5.v
practice_24.6.14.v
practice_24.6.16.v
practice_24.6.17.v
practice_24.6.18.v
practice_24.6.22.v
practice_24.6.23.v
practice_24.6.24.v
practice_24.6.26 (2).v
practice_24.6.26.v
practice_24.6.29.v
practice_24.7.5.v
selection(review).v
tb_cells.v
tb_dFF.v
乱码问题测试(GBK).v
乱码问题测试(UTF-8).v
测试新电脑.v
克隆/下载
practice_1.2.v 974 Bytes
一键复制 编辑 原始数据 按行查看 历史
打野 提交于 1年前 . 2024-1-2
//2024-1-2 姜青羊
//8位反相器(输入输出端口那里加上位宽即可)
`timescale 1ns/10ps
module inv_8bits (
A,
Y
);
input[7:0] A;
output[7:0] Y;
assign Y=~A;
endmodule
//---------testbench------------
module tb_inv_8bits ();
reg[7:0] a;
wire[7:0] y;
initial begin
a=0000_0000;
#10 a=0000_0001;
#10 a=0000_0010;
#10 a=0000_0011;
#10 a=0000_0100;
#10 a=0000_0101;
#10 a=0000_0110;
#10 a=0000_0111;
#10 a=0000_1000;
#10 a=0000_1001;
#10 a=0000_1010;
$stop;
end
inv_8bits u_inv_8bits (
.A(a),
.Y(y)
);
endmodule
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